forked from espressif/esp-idf
		
	Small changes to clock calibration value will cause increasing errors
the longer the device runs. Consider the case of deep sleep, assuming
that RTC counter is used for timekeeping:
- before sleep:
   time_before = rtc_counter * calibration_val
- after sleep:
   time_after = (rtc_counter + sleep_count) * (calibration_val + epsilon)
where 'epsilon' is a small estimation error of 'calibration_val'.
The apparent sleep duration thus will be:
time_after - time_before = sleep_count * (calibration_val + epsilon)
                           + rtc_counter * epsilon
Second term on the right hand side is the error in time difference
estimation, it is proportional to the total system runtime (rtc_counter).
To avoid this issue, this change makes RTC_SLOW_CLK calibration value
persistent across restarts. This allows the calibration value update to
be preformed, while keeping time after update same as before the update.
		
	
		
			
				
	
	
		
			128 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			128 lines
		
	
	
		
			4.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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//     http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdint.h>
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#include <sys/cdefs.h>
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#include <sys/time.h>
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#include "sdkconfig.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_clk.h"
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "rom/rtc.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
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 * Larger values increase startup delay. Smaller values may cause false positive
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 * detection (i.e. oscillator runs for a few cycles and then stops).
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 */
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#define XTAL_32K_DETECT_CYCLES  32
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#define SLOW_CLK_CAL_CYCLES     CONFIG_ESP32_RTC_CLK_CAL_CYCLES
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static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
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static const char* TAG = "clk";
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/*
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 * This function is not exposed as an API at this point,
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 * because FreeRTOS doesn't yet support dynamic changing of
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 * CPU frequency. Also we need to implement hooks for
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 * components which want to be notified of CPU frequency
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 * changes.
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 */
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void esp_clk_init(void)
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{
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    rtc_config_t cfg = RTC_CONFIG_DEFAULT();
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    rtc_init(cfg);
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    rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
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#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
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    select_rtc_slow_clk(RTC_SLOW_FREQ_32K_XTAL);
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#else
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    select_rtc_slow_clk(RTC_SLOW_FREQ_RTC);
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#endif
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    uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
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    rtc_cpu_freq_t freq = RTC_CPU_FREQ_80M;
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    switch(freq_mhz) {
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        case 240:
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            freq = RTC_CPU_FREQ_240M;
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            break;
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        case 160:
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            freq = RTC_CPU_FREQ_160M;
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            break;
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        default:
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            freq_mhz = 80;
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            /* no break */
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        case 80:
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            freq = RTC_CPU_FREQ_80M;
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            break;
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    }
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    // Wait for UART TX to finish, otherwise some UART output will be lost
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    // when switching APB frequency
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    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
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    rtc_clk_cpu_freq_set(freq);
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}
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void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
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{
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    extern uint32_t g_ticks_per_us_pro;  // g_ticks_us defined in ROM for PRO CPU
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    extern uint32_t g_ticks_per_us_app;  // same defined for APP CPU
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    g_ticks_per_us_pro = ticks_per_us;
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    g_ticks_per_us_app = ticks_per_us;
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}
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static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk)
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{
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    if (slow_clk == RTC_SLOW_FREQ_32K_XTAL) {
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        /* 32k XTAL oscillator needs to be enabled and running before it can
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         * be used. Hardware doesn't have a direct way of checking if the
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         * oscillator is running. Here we use rtc_clk_cal function to count
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         * the number of main XTAL cycles in the given number of 32k XTAL
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         * oscillator cycles. If the 32k XTAL has not started up, calibration
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         * will time out, returning 0.
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         */
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        rtc_clk_32k_enable(true);
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        uint32_t cal_val = 0;
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        uint32_t wait = 0;
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        // increment of 'wait' counter equivalent to 3 seconds
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        const uint32_t warning_timeout = 3 /* sec */ * 32768 /* Hz */ / (2 * XTAL_32K_DETECT_CYCLES);
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        ESP_EARLY_LOGD(TAG, "waiting for 32k oscillator to start up")
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        do {
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            ++wait;
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            cal_val = rtc_clk_cal(RTC_CAL_32K_XTAL, XTAL_32K_DETECT_CYCLES);
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            if (wait % warning_timeout == 0) {
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                ESP_EARLY_LOGW(TAG, "still waiting for 32k oscillator to start up");
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            }
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        } while (cal_val == 0);
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        ESP_EARLY_LOGD(TAG, "32k oscillator ready, wait=%d", wait);
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    }
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    rtc_clk_slow_freq_set(slow_clk);
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    uint32_t cal_val;
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    if (SLOW_CLK_CAL_CYCLES > 0) {
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        /* TODO: 32k XTAL oscillator has some frequency drift at startup.
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         * Improve calibration routine to wait until the frequency is stable.
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         */
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        cal_val = rtc_clk_cal(RTC_CAL_RTC_MUX, SLOW_CLK_CAL_CYCLES);
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    } else {
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        const uint64_t cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL;
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        cal_val = (uint32_t) (cal_dividend / rtc_clk_slow_freq_get_hz());
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    }
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    ESP_EARLY_LOGD(TAG, "RTC_SLOW_CLK calibration value: %d", cal_val);
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    esp_clk_slowclk_cal_set(cal_val);
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}
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