forked from espressif/esp-modbus
modbus master fix event loop and kconfig
This commit is contained in:
8
Kconfig
8
Kconfig
@@ -57,8 +57,8 @@ menu "Modbus configuration"
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config FMB_MASTER_TIMEOUT_MS_RESPOND
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config FMB_MASTER_TIMEOUT_MS_RESPOND
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int "Slave respond timeout (Milliseconds)"
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int "Slave respond timeout (Milliseconds)"
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default 150
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default 3000
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range 50 3000
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range 150 15000
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help
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help
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If master sends a frame which is not broadcast, it has to wait sometime for slave response.
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If master sends a frame which is not broadcast, it has to wait sometime for slave response.
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if slave is not respond in this time, the master will process timeout error.
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if slave is not respond in this time, the master will process timeout error.
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@@ -66,7 +66,7 @@ menu "Modbus configuration"
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config FMB_MASTER_DELAY_MS_CONVERT
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config FMB_MASTER_DELAY_MS_CONVERT
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int "Slave conversion delay (Milliseconds)"
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int "Slave conversion delay (Milliseconds)"
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default 200
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default 200
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range 50 400
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range 150 2000
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help
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help
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If master sends a broadcast frame, it has to wait conversion time to delay,
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If master sends a broadcast frame, it has to wait conversion time to delay,
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then master can send next frame.
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then master can send next frame.
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@@ -107,7 +107,7 @@ menu "Modbus configuration"
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config FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS
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config FMB_SERIAL_ASCII_TIMEOUT_RESPOND_MS
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int "Response timeout for ASCII communication mode (ms)"
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int "Response timeout for ASCII communication mode (ms)"
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default 1000
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default 1000
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range 300 2000
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range 200 5000
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depends on FMB_COMM_MODE_ASCII_EN
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depends on FMB_COMM_MODE_ASCII_EN
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help
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help
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This option defines response timeout of slave in milliseconds for ASCII communication mode.
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This option defines response timeout of slave in milliseconds for ASCII communication mode.
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@@ -91,6 +91,10 @@
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#define MB_TCP_SEND_TIMEOUT (pdMS_TO_TICKS(MB_TCP_SEND_TIMEOUT_MS))
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#define MB_TCP_SEND_TIMEOUT (pdMS_TO_TICKS(MB_TCP_SEND_TIMEOUT_MS))
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#define MB_TCP_PORT_MAX_CONN (CONFIG_FMB_TCP_PORT_MAX_CONN)
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#define MB_TCP_PORT_MAX_CONN (CONFIG_FMB_TCP_PORT_MAX_CONN)
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// Set the API unlock time to maximum response time
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// The actual release time will be dependent on the timer time
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#define MB_MAX_RESPONSE_TIME_MS (5000)
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#define MB_TCP_FRAME_LOG_BUFSIZE (256)
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#define MB_TCP_FRAME_LOG_BUFSIZE (256)
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#define MB_PORT_HAS_CLOSE (1) // Define to explicitly close port on destroy
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#define MB_PORT_HAS_CLOSE (1) // Define to explicitly close port on destroy
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@@ -27,8 +27,8 @@
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extern BOOL xMBMasterPortSerialTxPoll(void);
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extern BOOL xMBMasterPortSerialTxPoll(void);
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/*-----------------------Master mode use these variables----------------------*/
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/*-----------------------Master mode use these variables----------------------*/
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#define MB_RESPONSE_TICS pdMS_TO_TICKS(CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND + 10)
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// Actual wait time depends on the response timer
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#define MB_SERIAL_API_RESP_TICS (pdMS_TO_TICKS(MB_MAX_RESPONSE_TIME_MS))
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static mb_master_interface_t* mbm_interface_ptr = NULL;
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static mb_master_interface_t* mbm_interface_ptr = NULL;
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static const char *TAG = "MB_CONTROLLER_MASTER";
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static const char *TAG = "MB_CONTROLLER_MASTER";
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@@ -176,7 +176,7 @@ static esp_err_t mbc_serial_master_send_request(mb_param_request_t* request, voi
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eMBMasterReqErrCode mb_error = MB_MRE_MASTER_BUSY;
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eMBMasterReqErrCode mb_error = MB_MRE_MASTER_BUSY;
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esp_err_t error = ESP_FAIL;
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esp_err_t error = ESP_FAIL;
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if (xMBMasterRunResTake(MB_RESPONSE_TICS)) {
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if (xMBMasterRunResTake(MB_SERIAL_API_RESP_TICS)) {
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uint8_t mb_slave_addr = request->slave_addr;
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uint8_t mb_slave_addr = request->slave_addr;
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uint8_t mb_command = request->command;
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uint8_t mb_command = request->command;
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@@ -194,43 +194,43 @@ static esp_err_t mbc_serial_master_send_request(mb_param_request_t* request, voi
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{
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{
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case MB_FUNC_READ_COILS:
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case MB_FUNC_READ_COILS:
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mb_error = eMBMasterReqReadCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size , (LONG)MB_RESPONSE_TICS );
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(USHORT)mb_size , (LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_WRITE_SINGLE_COIL:
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case MB_FUNC_WRITE_SINGLE_COIL:
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mb_error = eMBMasterReqWriteCoil((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqWriteCoil((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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*(USHORT*)data_ptr, (LONG)MB_RESPONSE_TICS );
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*(USHORT*)data_ptr, (LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_WRITE_MULTIPLE_COILS:
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case MB_FUNC_WRITE_MULTIPLE_COILS:
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mb_error = eMBMasterReqWriteMultipleCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqWriteMultipleCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (UCHAR*)data_ptr, (LONG)MB_RESPONSE_TICS);
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(USHORT)mb_size, (UCHAR*)data_ptr, (LONG)MB_SERIAL_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_READ_DISCRETE_INPUTS:
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case MB_FUNC_READ_DISCRETE_INPUTS:
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mb_error = eMBMasterReqReadDiscreteInputs((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadDiscreteInputs((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG)MB_RESPONSE_TICS );
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(USHORT)mb_size, (LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_READ_HOLDING_REGISTER:
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case MB_FUNC_READ_HOLDING_REGISTER:
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mb_error = eMBMasterReqReadHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG)MB_RESPONSE_TICS );
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(USHORT)mb_size, (LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_WRITE_REGISTER:
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case MB_FUNC_WRITE_REGISTER:
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mb_error = eMBMasterReqWriteHoldingRegister( (UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqWriteHoldingRegister( (UCHAR)mb_slave_addr, (USHORT)mb_offset,
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*(USHORT*)data_ptr, (LONG)MB_RESPONSE_TICS );
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*(USHORT*)data_ptr, (LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_WRITE_MULTIPLE_REGISTERS:
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case MB_FUNC_WRITE_MULTIPLE_REGISTERS:
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mb_error = eMBMasterReqWriteMultipleHoldingRegister( (UCHAR)mb_slave_addr,
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mb_error = eMBMasterReqWriteMultipleHoldingRegister( (UCHAR)mb_slave_addr,
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(USHORT)mb_offset, (USHORT)mb_size,
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(USHORT)mb_offset, (USHORT)mb_size,
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(USHORT*)data_ptr, (LONG)MB_RESPONSE_TICS );
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(USHORT*)data_ptr, (LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_READWRITE_MULTIPLE_REGISTERS:
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case MB_FUNC_READWRITE_MULTIPLE_REGISTERS:
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mb_error = eMBMasterReqReadWriteMultipleHoldingRegister( (UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadWriteMultipleHoldingRegister( (UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (USHORT*)data_ptr,
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(USHORT)mb_size, (USHORT*)data_ptr,
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(USHORT)mb_offset, (USHORT)mb_size,
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(USHORT)mb_offset, (USHORT)mb_size,
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(LONG)MB_RESPONSE_TICS );
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(LONG)MB_SERIAL_API_RESP_TICS );
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break;
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break;
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case MB_FUNC_READ_INPUT_REGISTER:
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case MB_FUNC_READ_INPUT_REGISTER:
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mb_error = eMBMasterReqReadInputRegister( (UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadInputRegister( (UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG) MB_RESPONSE_TICS );
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(USHORT)mb_size, (LONG) MB_SERIAL_API_RESP_TICS );
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break;
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break;
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default:
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default:
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ESP_LOGE(TAG, "%s: Incorrect function in request (%u) ", __FUNCTION__, (unsigned)mb_command);
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ESP_LOGE(TAG, "%s: Incorrect function in request (%u) ", __FUNCTION__, (unsigned)mb_command);
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@@ -29,9 +29,10 @@
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/*-----------------------Master mode use these variables----------------------*/
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/*-----------------------Master mode use these variables----------------------*/
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// The response time is average processing time + data transmission
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#define MB_TCP_CONNECTION_TOUT (pdMS_TO_TICKS(CONFIG_FMB_TCP_CONNECTION_TOUT_SEC * 1000))
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#define MB_RESPONSE_TIMEOUT pdMS_TO_TICKS(CONFIG_FMB_MASTER_TIMEOUT_MS_RESPOND)
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#define MB_TCP_CONNECTION_TOUT pdMS_TO_TICKS(CONFIG_FMB_TCP_CONNECTION_TOUT_SEC * 1000)
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// Actual wait time depends on the response timer
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#define MB_TCP_API_RESP_TICS (pdMS_TO_TICKS(MB_MAX_RESPONSE_TIME_MS))
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static mb_master_interface_t* mbm_interface_ptr = NULL;
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static mb_master_interface_t* mbm_interface_ptr = NULL;
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static const char *TAG = "MB_CONTROLLER_MASTER";
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static const char *TAG = "MB_CONTROLLER_MASTER";
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@@ -257,7 +258,7 @@ static esp_err_t mbc_tcp_master_send_request(mb_param_request_t* request, void*
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eMBMasterReqErrCode mb_error = MB_MRE_MASTER_BUSY;
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eMBMasterReqErrCode mb_error = MB_MRE_MASTER_BUSY;
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esp_err_t error = ESP_FAIL;
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esp_err_t error = ESP_FAIL;
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if (xMBMasterRunResTake(MB_RESPONSE_TIMEOUT)) {
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if (xMBMasterRunResTake(MB_TCP_API_RESP_TICS)) {
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uint8_t mb_slave_addr = request->slave_addr;
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uint8_t mb_slave_addr = request->slave_addr;
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uint8_t mb_command = request->command;
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uint8_t mb_command = request->command;
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@@ -275,44 +276,44 @@ static esp_err_t mbc_tcp_master_send_request(mb_param_request_t* request, void*
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{
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{
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case MB_FUNC_READ_COILS:
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case MB_FUNC_READ_COILS:
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mb_error = eMBMasterReqReadCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG)MB_RESPONSE_TIMEOUT);
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(USHORT)mb_size, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_WRITE_SINGLE_COIL:
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case MB_FUNC_WRITE_SINGLE_COIL:
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mb_error = eMBMasterReqWriteCoil((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqWriteCoil((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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*(USHORT *)data_ptr, (LONG)MB_RESPONSE_TIMEOUT);
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*(USHORT *)data_ptr, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_WRITE_MULTIPLE_COILS:
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case MB_FUNC_WRITE_MULTIPLE_COILS:
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mb_error = eMBMasterReqWriteMultipleCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqWriteMultipleCoils((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (UCHAR *)data_ptr,
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(USHORT)mb_size, (UCHAR *)data_ptr,
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(LONG)MB_RESPONSE_TIMEOUT);
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(LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_READ_DISCRETE_INPUTS:
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case MB_FUNC_READ_DISCRETE_INPUTS:
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mb_error = eMBMasterReqReadDiscreteInputs((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadDiscreteInputs((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG)MB_RESPONSE_TIMEOUT);
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(USHORT)mb_size, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_READ_HOLDING_REGISTER:
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case MB_FUNC_READ_HOLDING_REGISTER:
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mb_error = eMBMasterReqReadHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG)MB_RESPONSE_TIMEOUT);
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(USHORT)mb_size, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_WRITE_REGISTER:
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case MB_FUNC_WRITE_REGISTER:
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mb_error = eMBMasterReqWriteHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqWriteHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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*(USHORT *)data_ptr, (LONG)MB_RESPONSE_TIMEOUT);
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*(USHORT *)data_ptr, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_WRITE_MULTIPLE_REGISTERS:
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case MB_FUNC_WRITE_MULTIPLE_REGISTERS:
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mb_error = eMBMasterReqWriteMultipleHoldingRegister((UCHAR)mb_slave_addr,
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mb_error = eMBMasterReqWriteMultipleHoldingRegister((UCHAR)mb_slave_addr,
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(USHORT)mb_offset, (USHORT)mb_size,
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(USHORT)mb_offset, (USHORT)mb_size,
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(USHORT *)data_ptr, (LONG)MB_RESPONSE_TIMEOUT);
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(USHORT *)data_ptr, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_READWRITE_MULTIPLE_REGISTERS:
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case MB_FUNC_READWRITE_MULTIPLE_REGISTERS:
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mb_error = eMBMasterReqReadWriteMultipleHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadWriteMultipleHoldingRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (USHORT *)data_ptr,
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(USHORT)mb_size, (USHORT *)data_ptr,
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(USHORT)mb_offset, (USHORT)mb_size,
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(USHORT)mb_offset, (USHORT)mb_size,
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(LONG)MB_RESPONSE_TIMEOUT);
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(LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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case MB_FUNC_READ_INPUT_REGISTER:
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case MB_FUNC_READ_INPUT_REGISTER:
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mb_error = eMBMasterReqReadInputRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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mb_error = eMBMasterReqReadInputRegister((UCHAR)mb_slave_addr, (USHORT)mb_offset,
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(USHORT)mb_size, (LONG)MB_RESPONSE_TIMEOUT);
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(USHORT)mb_size, (LONG)MB_TCP_API_RESP_TICS);
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break;
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break;
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default:
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default:
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ESP_LOGE(TAG, "%s: Incorrect function in request (%u) ", __FUNCTION__, (unsigned)mb_command);
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ESP_LOGE(TAG, "%s: Incorrect function in request (%u) ", __FUNCTION__, (unsigned)mb_command);
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