From 705d7ea5ab97fbe8909f7c487eb5ab9ab76ebbf3 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Sat, 16 May 2020 12:03:09 +0200 Subject: [PATCH 01/25] Added load elf and dummy instructions --- data/languages/xtensaInstructions.sinc | 39 +++ data/languages/xtensaTodo.sinc | 87 +++++- .../Xtensa_ElfRelocationConstants.java | 58 ++++ .../Xtensa_ElfRelocationHandler.java | 292 ++++++++++++++++++ 4 files changed, 461 insertions(+), 15 deletions(-) create mode 100644 src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationConstants.java create mode 100644 src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationHandler.java diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 1647f43..c0ed1ae 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -314,6 +314,45 @@ macro extract_bit(val, bit, result) { call [dst]; } +# ENTRY - Subroutine Entry, pg. 340. +:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { + #as=as-u15_12.23_sb3; +} + +# if (u15_12.23_sb3 ==4) +# goto ; +# if (u15_12.23_sb3 ==8) +# goto ; +# if (u15_12.23_sb3 ==12) +# goto ; +# +# a2=a6; +# a3=a7; +# a4=a8; +# a5=a9; +# a6=a10; +# a7=a11; +# a8=a12; +# a9=a13; +# a10=a14; +# a11=a15; +# goto ; +# +# a2=a10; +# a3=a11; +# a4=a12; +# a5=a13; +# a6=a14; +# a7=a15; +# goto ; +# +# a2=a14; +# a3=a15; +# + + + + # CEIL.S - Ceiling Single to Fixed, pg. 311. :ceil.s ar, fs, u4_4.7 is op2 = 0b1011 & op1 = 0b1010 & ar & fs & u4_4.7 & op0 = 0 { local scale:4 = int2float(1:1 << u4_4.7:1); diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index b89eea5..2e88327 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -1,25 +1,79 @@ ## Windowed Register Option ## # CALL4 - Call PC-relative, Rotate Window by 4, pg. 298. -:call4 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b01 & op0 = 0b0101 unimpl +:call4 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b01 & op0 = 0b0101 { + local dst = srel_6.23_sb2; + a2=a6; + a3=a7; + a4=a8; + a5=a9; + a0 = inst_start + 3; + call [dst]; +} # CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. -:call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 unimpl +:call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 { + local dst = srel_6.23_sb2; + a2=a10; + a3=a11; + a4=a12; + a5=a13; + a6=a14; + a7=a15; + a0 = inst_start + 3; + call [dst]; +} # CALL12 - Call PC-relative, Rotate Window by 12, pg. 302. -:call12 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b11 & op0 = 0b0101 unimpl - -# CALLX4 - Call Register, Rotate Window by 4, pg. 305. -:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b01 & op0 = 0 unimpl - -# CALLX8 - Call Register, Rotate Window by 8, pg. 307. -:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b10 & op0 = 0 unimpl - -# CALLX12 - Call Register, Rotate Window by 12, pg. 308. -:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b11 & op0 = 0 unimpl +:call12 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b11 & op0 = 0b0101 { + local dst = srel_6.23_sb2; + a2=a14; + a3=a15; + a0 = inst_start + 3; + call [dst]; +} # ENTRY - Subroutine Entry, pg. 340. -:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 unimpl +#:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { +# as normally a1 +# #a1=a1-u15_12.23_sb3; +#} + + +# CALLX4 - Call Register, Rotate Window by 4, pg. 305. +:callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b01 & op0 = 0 { + local dst = as; + a2=a6; + a3=a7; + a4=a8; + a5=a9; + a6=a10; + a7=a11; + a8=a12; + a9=a13; + a10=a14; + a11=a15; + a0 = inst_start + 3; + call [dst]; +} + +# CALLX8 - Call Register, Rotate Window by 8, pg. 307. +:callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b10 & op0 = 0 { + local dst = as; + a0 = inst_start + 3; + call [dst]; +} + +# CALLX12 - Call Register, Rotate Window by 12, pg. 308. +:callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b11 & op0 = 0 { + local dst = as; + a2=a14; + a3=a15; + a0 = inst_start + 3; + call [dst]; +} + + # L32E - Load 32-bit for Window Exceptions, pg. 376. :l32e at, as, s5_12.15_oex is op2 = 0 & op1 = 0b1001 & s5_12.15_oex & as & at & op0 = 0 unimpl @@ -28,10 +82,13 @@ :movsp at, as is op2 = 0 & op1 = 0 & ar = 0b0001 & as & at & op0 = 0 unimpl # RETW - Windowed Return, pg. 480. -:retw is op2 = 0 & ar = 0 & as = 0 & at = 0 & u2_18.19 = 0b10 & u2_16.17 = 0b01 & op0 = 0 unimpl +:retw is op2 = 0 & ar = 0 & as = 0 & at = 0 & u2_18.19 = 0b10 & u2_16.17 = 0b01 & op0 = 0 { + +} # RETW.N - Narrow Windowed Return, pg. 482. -:retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 unimpl +:retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { +} # ROTW - Rotate Window, pg. 496. :rotw s4_4.7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4.7 & op0 = 0 unimpl diff --git a/src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationConstants.java b/src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationConstants.java new file mode 100644 index 0000000..f74eb6d --- /dev/null +++ b/src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationConstants.java @@ -0,0 +1,58 @@ +package ghidra.app.util.bin.format.elf.relocation; + +public class Xtensa_ElfRelocationConstants { + /* Xtensa processor ELF architecture-magic number */ + + // EM_XTENSA is already definded + public static final int EM_XTENSA_OLD = 0xABC7; + + /* Xtensa relocations defined by the ABIs */ + + public static final int R_XTENSA_NONE = 0; + public static final int R_XTENSA_32 = 1; + public static final int R_XTENSA_RTLD = 2; + public static final int R_XTENSA_GLOB_DAT = 3; + public static final int R_XTENSA_JMP_SLOT = 4; + public static final int R_XTENSA_RELATIVE = 5; + public static final int R_XTENSA_PLT = 6; + public static final int R_XTENSA_OP0 = 8; + public static final int R_XTENSA_OP1 = 9; + public static final int R_XTENSA_OP2 = 10; + public static final int R_XTENSA_ASM_EXPAND = 11; + public static final int R_XTENSA_ASM_SIMPLIFY = 12; + public static final int R_XTENSA_GNU_VTINHERIT = 15; + public static final int R_XTENSA_GNU_VTENTRY = 16; + public static final int R_XTENSA_DIFF8 = 17; + public static final int R_XTENSA_DIFF16 = 18; + public static final int R_XTENSA_DIFF32 = 19; + public static final int R_XTENSA_SLOT0_OP = 20; + public static final int R_XTENSA_SLOT1_OP = 21; + public static final int R_XTENSA_SLOT2_OP = 22; + public static final int R_XTENSA_SLOT3_OP = 23; + public static final int R_XTENSA_SLOT4_OP = 24; + public static final int R_XTENSA_SLOT5_OP = 25; + public static final int R_XTENSA_SLOT6_OP = 26; + public static final int R_XTENSA_SLOT7_OP = 27; + public static final int R_XTENSA_SLOT8_OP = 28; + public static final int R_XTENSA_SLOT9_OP = 29; + public static final int R_XTENSA_SLOT10_OP = 30; + public static final int R_XTENSA_SLOT11_OP = 31; + public static final int R_XTENSA_SLOT12_OP = 32; + public static final int R_XTENSA_SLOT13_OP = 33; + public static final int R_XTENSA_SLOT14_OP = 34; + public static final int R_XTENSA_SLOT0_ALT = 35; + public static final int R_XTENSA_SLOT1_ALT = 36; + public static final int R_XTENSA_SLOT2_ALT = 37; + public static final int R_XTENSA_SLOT3_ALT = 38; + public static final int R_XTENSA_SLOT4_ALT = 39; + public static final int R_XTENSA_SLOT5_ALT = 40; + public static final int R_XTENSA_SLOT6_ALT = 41; + public static final int R_XTENSA_SLOT7_ALT = 42; + public static final int R_XTENSA_SLOT8_ALT = 43; + public static final int R_XTENSA_SLOT9_ALT = 44; + public static final int R_XTENSA_SLOT10_ALT = 45; + public static final int R_XTENSA_SLOT11_ALT = 46; + public static final int R_XTENSA_SLOT12_ALT = 47; + public static final int R_XTENSA_SLOT13_ALT = 48; + public static final int R_XTENSA_SLOT14_ALT = 49; +} diff --git a/src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationHandler.java b/src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationHandler.java new file mode 100644 index 0000000..5882690 --- /dev/null +++ b/src/main/java/ghidra/app/util/bin/format/elf/relocation/Xtensa_ElfRelocationHandler.java @@ -0,0 +1,292 @@ +package ghidra.app.util.bin.format.elf.relocation; + +import ghidra.app.util.bin.format.elf.ElfConstants; +import ghidra.app.util.bin.format.elf.ElfHeader; +import ghidra.app.util.bin.format.elf.ElfRelocation; +import ghidra.app.util.bin.format.elf.ElfSymbol; +import ghidra.program.model.address.Address; +import ghidra.program.model.listing.Program; +import ghidra.program.model.mem.Memory; +import ghidra.program.model.mem.MemoryAccessException; +import ghidra.util.exception.NotFoundException; + +public class Xtensa_ElfRelocationHandler extends ElfRelocationHandler { + + @Override + public boolean canRelocate(ElfHeader elf) { + return elf.e_machine() == ElfConstants.EM_XTENSA || + elf.e_machine() == Xtensa_ElfRelocationConstants.EM_XTENSA_OLD; + } + + @Override + public void relocate(ElfRelocationContext elfRelocationContext, ElfRelocation relocation, Address relocationAddress) + throws MemoryAccessException, NotFoundException { + ElfHeader elf = elfRelocationContext.getElfHeader(); + if (!canRelocate(elf)) { + return; + } + + int type=relocation.getType(); + if (Xtensa_ElfRelocationConstants.R_XTENSA_NONE == type) { + return; + } + + Program program = elfRelocationContext.getProgram(); + Memory memory = program.getMemory(); + + long addend = relocation.hasAddend() ? relocation.getAddend() : memory.getInt(relocationAddress); + long offset = relocationAddress.getOffset(); + long base = elfRelocationContext.getImageBaseWordAdjustmentOffset(); + ElfSymbol sym = null; + long symbolValue = 0; + String symbolName = null; + + int symbolIndex = relocation.getSymbolIndex(); + if (symbolIndex != 0) { + sym = elfRelocationContext.getSymbol(symbolIndex); + } + + if (null != sym) { + symbolValue = elfRelocationContext.getSymbolValue(sym); + symbolName = sym.getNameAsString(); + } + + switch(type) { + case Xtensa_ElfRelocationConstants.R_XTENSA_32: + markAsWarning(program, relocationAddress, "R_XTENSA_32", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_RTLD: + markAsWarning(program, relocationAddress, "R_XTENSA_RTLD", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_GLOB_DAT: + markAsWarning(program, relocationAddress, "R_XTENSA_GLOB_DAT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_JMP_SLOT: + markAsWarning(program, relocationAddress, "R_XTENSA_JMP_SLOT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_RELATIVE: + markAsWarning(program, relocationAddress, "R_XTENSA_RELATIVE", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_PLT: + markAsWarning(program, relocationAddress, "R_XTENSA_PLT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_OP0: + markAsWarning(program, relocationAddress, "R_XTENSA_OP0", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_OP1: + markAsWarning(program, relocationAddress, "R_XTENSA_OP1", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_OP2: + markAsWarning(program, relocationAddress, "R_XTENSA_OP2", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_ASM_EXPAND: + markAsWarning(program, relocationAddress, "R_XTENSA_ASM_EXPAND", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_ASM_SIMPLIFY: + markAsWarning(program, relocationAddress, "R_XTENSA_ASM_SIMPLIFY", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_GNU_VTINHERIT: + markAsWarning(program, relocationAddress, "R_XTENSA_GNU_VTINHERIT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_GNU_VTENTRY: + markAsWarning(program, relocationAddress, "R_XTENSA_GNU_VTENTRY", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_DIFF8: + markAsWarning(program, relocationAddress, "R_XTENSA_DIFF8", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_DIFF16: + markAsWarning(program, relocationAddress, "R_XTENSA_DIFF16", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_DIFF32: + markAsWarning(program, relocationAddress, "R_XTENSA_DIFF32", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT0_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT0_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT1_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT1_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT2_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT2_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT3_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT3_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT4_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT4_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT5_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT5_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT6_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT6_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT7_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT7_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT8_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT8_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT9_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT9_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT10_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT10_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT11_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT11_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT12_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT12_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT13_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT13_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT14_OP: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT14_OP", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT0_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT0_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT1_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT1_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT2_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT2_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT3_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT3_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT4_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT4_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT5_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT5_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT6_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT6_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT7_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT7_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT8_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT8_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT9_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT9_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT10_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT10_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT11_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT11_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT12_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT12_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT13_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT13_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + case Xtensa_ElfRelocationConstants.R_XTENSA_SLOT14_ALT: + markAsWarning(program, relocationAddress, "R_XTENSA_SLOT14_ALT", + symbolName, symbolIndex, "TODO, needs support ", + elfRelocationContext.getLog()); + break; + default: + markAsUnhandled(program, relocationAddress, type, symbolIndex, + symbolName, elfRelocationContext.getLog()); + break; + } + } + +} From d5a5eb7a6e090053a3eababb003e4a910fd593bd Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Sat, 16 May 2020 12:21:28 +0200 Subject: [PATCH 02/25] Updated with upstream manual merge --- data/languages/xtensa.dwarf | 2 +- data/languages/xtensa.ldefs | 2 +- data/languages/xtensa.sinc | 28 ++------- data/languages/xtensaInstructions.sinc | 78 ++++++++++---------------- data/languages/xtensaTodo.sinc | 40 ++++++++++++- 5 files changed, 73 insertions(+), 77 deletions(-) diff --git a/data/languages/xtensa.dwarf b/data/languages/xtensa.dwarf index afe6a2e..1790648 100644 --- a/data/languages/xtensa.dwarf +++ b/data/languages/xtensa.dwarf @@ -2,6 +2,6 @@ - + diff --git a/data/languages/xtensa.ldefs b/data/languages/xtensa.ldefs index e4e4a0e..80c6e25 100644 --- a/data/languages/xtensa.ldefs +++ b/data/languages/xtensa.ldefs @@ -12,6 +12,6 @@ id="Xtensa:LE:32:default"> Tensilica Xtensa 32-bit little-endian - + diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index efe9420..5b3ac59 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -67,7 +67,7 @@ define token insn(24) u1_12 = (12,12) u4_8.11 = (8,11) u8_4.11 = (4,11) - # s4_8.11 = (8,11) signed + s4_8.11 = (8,11) signed u2_6.7 = (6,7) u3_5.7 = (5,7) u4_4.7 = (4,7) @@ -138,11 +138,8 @@ u5_4.7_12: tmp is u1_12 & u4_4.7 [ tmp = (u1_12 << 4) | u4_4.7; ] { export * u5_8.11_4: tmp is u1_4 & u4_8.11 [ tmp = (u1_4 << 4) | u4_8.11; ] { export *[const]:1 tmp; } # Signed 12-bit (extended to 16) immediate, used by MOVI. -s16_16.23_8.11: tmp is u4_8.11 & u8_16.23 [ - # FIXME: This table, and the fields used, should be signed, but using s4_8.11 and s8_16.23 - # somehow confuses Ghidra. - tmp = (0xf000 * (u4_8.11 >> 3)) | # Sign-extend. - (u4_8.11 << 8) | u8_16.23; +s16_16.23_8.11: tmp is s4_8.11 & u8_16.23 [ + tmp = (s4_8.11 << 8) | u8_16.23; ] { export *[const]:2 tmp; } # An “asymmetric” immediate from -32..95, used by MOVI.N. @@ -167,25 +164,10 @@ n_u6_12.15_sb2: tmp is n_u4_12.15 [ tmp = n_u4_12.15 << 2; ] { export *[const]: s5_12.15_oex: tmp is u4_12.15 [ tmp = (2 << u4_12.15) * -1; ] { export *[const]:2 tmp; } # Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action. -# FIXME: “foo: tmp is u4_foo [ tmp = u4_foo; ]” doesn’t work when a more special constructor exists. # n_u4_4.7 with 0 being -1, used by ADDI.N. -n_s4_4.7_nozero: tmp is n_u4_4.7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 1 [ tmp = 1; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 2 [ tmp = 2; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 3 [ tmp = 3; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 4 [ tmp = 4; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 5 [ tmp = 5; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 6 [ tmp = 6; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 7 [ tmp = 7; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 8 [ tmp = 8; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 9 [ tmp = 9; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 10 [ tmp = 10; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 11 [ tmp = 11; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 12 [ tmp = 12; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 13 [ tmp = 13; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 14 [ tmp = 14; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 15 [ tmp = 15; ] { export *[const]:4 tmp; } +n_s4_4.7_nozero: tmp is n_u4_4.7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; } +n_s4_4.7_nozero: tmp is n_u4_4.7 [ tmp = n_u4_4.7+0; ] { export *[const]:4 tmp; } # B4CONST(ar) (Branch Immediate) encodings, pg. 41 f. r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; } diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index c0ed1ae..ec76230 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -314,45 +314,6 @@ macro extract_bit(val, bit, result) { call [dst]; } -# ENTRY - Subroutine Entry, pg. 340. -:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { - #as=as-u15_12.23_sb3; -} - -# if (u15_12.23_sb3 ==4) -# goto ; -# if (u15_12.23_sb3 ==8) -# goto ; -# if (u15_12.23_sb3 ==12) -# goto ; -# -# a2=a6; -# a3=a7; -# a4=a8; -# a5=a9; -# a6=a10; -# a7=a11; -# a8=a12; -# a9=a13; -# a10=a14; -# a11=a15; -# goto ; -# -# a2=a10; -# a3=a11; -# a4=a12; -# a5=a13; -# a6=a14; -# a7=a15; -# goto ; -# -# a2=a14; -# a3=a15; -# - - - - # CEIL.S - Ceiling Single to Fixed, pg. 311. :ceil.s ar, fs, u4_4.7 is op2 = 0b1011 & op1 = 0b1010 & ar & fs & u4_4.7 & op0 = 0 { local scale:4 = int2float(1:1 << u4_4.7:1); @@ -868,7 +829,21 @@ macro extract_bit(val, bit, result) { # NSAU - Normalization Shift Amount Unsigned, pg. 462. (Count leading zeros) :nsau at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 { - at = nsau(as); + local z4 = as[16,16] == 0; + + local t3 = zext(z4)*as[0,16] + zext(!z4)*as[16,16]; + local z3 = t3[8,8] == 0; + + local t2 = (z3)*t3[0,8] + (!z3)*t3[8,8]; + local z2 = t2[4,4] == 0; + + local t1 = (z2)*t2[0,4] + (!z2)*t2[4,4]; + local z1 = t1[2,2] == 0; + + local z0 = (z1)*(t1[1,1] == 0) + (!z1)*(t1[3,1] == 0); + local all0 = as == 0; + + at = zext((all0)*32 + (!all0)*(z4<<4 | z3<<3 | z2<<2 | z1<<1 | z0)); } # OEQ.S - Compare Single Equal, pg. 463. @@ -1108,13 +1083,13 @@ macro extract_bit(val, bit, result) { # SLL - Shift Left Logical, pg. 524. :sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 { - local sa:1 = 32 - (sar & 0xf); # XXX check this + local sa:1 = 32 - sar; ar = as << sa; } # SLLI - Shift Left Logical Immediate, pg. 525. :slli ar, as, u5_4.7_20 is u3_21.23 = 0 & u5_4.7_20 & op1 = 0b0001 & ar & as & op0 = 0 { - local sa:1 = 32 - u5_4.7_20; # XXX check this + local sa:1 = 32 - u5_4.7_20; ar = as << sa; } @@ -1179,12 +1154,12 @@ macro extract_bit(val, bit, result) { # SSL - Set Shift Amount for Left Shift, pg. 538. :ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 { - sar = 32 - (as:1 & 0xf); + sar = 32 - (as:1 & 0x1f); } # SSR - Set Shift Amount for Right Shift, pg. 539. :ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 { - sar = (as:1 & 0xf); + sar = (as:1 & 0x1f); } # SSX - Store Singe Indexed, pg. 540. @@ -1241,9 +1216,10 @@ macro extract_bit(val, bit, result) { br = nan(fs) || nan(ft) || fs f== ft; } -# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550. XXX: How is this different from float.as? +# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550. :ufloat.s fr, as, u4_4.7 is op2 = 0b1101 & op1 = 0b1010 & fr & as & u4_4.7 & op0 = 0 { - local f = int2float(as); + local tmp:8 = zext(as); + local f = int2float(tmp); local d = int2float(1:2 << u4_4.7:2); fr = d f/ f; } @@ -1265,10 +1241,14 @@ macro extract_bit(val, bit, result) { br = nan(fs) || nan(ft); } -# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555. FIXME: difference to trunc.s? +# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555. :utrunc.s ar, fs, u4_4.7 is op2 = 0b1110 & op1 = 0b1010 & ar & fs & u4_4.7 & op0 = 0 { local scale:4 = int2float(1:2 << u4_4.7:2); - ar = trunc(fs f* scale); + local tmp:8 = trunc(fs f* scale); + local posof = nan(fs) || (tmp >> 16) != 0; + local negof = tmp s< 0; + local noof = !posof && !negof; + ar = zext(posof)*0xffffffff + zext(negof)*0x80000000 + zext(noof)*tmp:4; } # WAITI - Wait Interrupt, pg. 556. @@ -1317,6 +1297,6 @@ macro extract_bit(val, bit, result) { } # XSR - Exchange Special Register, pg. 566. -:xsr at, u8_8.15 is op2 = 0b1110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 { +:xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 { at = xsr(u8_8.15:1, at); } diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 2e88327..f85693f 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -34,10 +34,44 @@ } # ENTRY - Subroutine Entry, pg. 340. -#:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { +:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { # as normally a1 -# #a1=a1-u15_12.23_sb3; -#} +# a1=a1-u15_12.23_sb3; +} + +# if (u15_12.23_sb3 ==4) +# goto ; +# if (u15_12.23_sb3 ==8) +# goto ; +# if (u15_12.23_sb3 ==12) +# goto ; +# +# a2=a6; +# a3=a7; +# a4=a8; +# a5=a9; +# a6=a10; +# a7=a11; +# a8=a12; +# a9=a13; +# a10=a14; +# a11=a15; +# goto ; +# +# a2=a10; +# a3=a11; +# a4=a12; +# a5=a13; +# a6=a14; +# a7=a15; +# goto ; +# +# a2=a14; +# a3=a15; +# + + + # CALLX4 - Call Register, Rotate Window by 4, pg. 305. From ce8892e5650e95bbb69b930fe593f21ad492d6dd Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 18 May 2020 11:40:29 +0200 Subject: [PATCH 03/25] Better return implementation --- data/languages/xtensaTodo.sinc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index f85693f..f4ca3d3 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -117,11 +117,12 @@ # RETW - Windowed Return, pg. 480. :retw is op2 = 0 & ar = 0 & as = 0 & at = 0 & u2_18.19 = 0b10 & u2_16.17 = 0b01 & op0 = 0 { - + return [a0]; } # RETW.N - Narrow Windowed Return, pg. 482. :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { + return [a0]; } # ROTW - Rotate Window, pg. 496. From 8a62cd2dbf720ddfb1c641358f8dc55dee92d693 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 18 May 2020 15:11:37 +0200 Subject: [PATCH 04/25] Better entry? --- data/languages/xtensaTodo.sinc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index f4ca3d3..00a06de 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -36,7 +36,7 @@ # ENTRY - Subroutine Entry, pg. 340. :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { # as normally a1 -# a1=a1-u15_12.23_sb3; + as = as - u15_12.23_sb3; } # if (u15_12.23_sb3 ==4) @@ -126,7 +126,9 @@ } # ROTW - Rotate Window, pg. 496. -:rotw s4_4.7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4.7 & op0 = 0 unimpl +:rotw s4_4.7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4.7 & op0 = 0 { + +} # S32E - Store 32-bit for Window Exceptions, pg. 508. :s32e at, as, s5_12.15_oex is op2 = 0b0100 & op1 = 0b1001 & s5_12.15_oex & as & at & op0 = 0 unimpl From 2c7730e650d40c28be095da49f2089ac8574d207 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 18 May 2020 18:02:44 +0200 Subject: [PATCH 05/25] Moving sp=a1 did not work --- data/languages/xtensaTodo.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 00a06de..15f87a9 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -36,7 +36,7 @@ # ENTRY - Subroutine Entry, pg. 340. :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { # as normally a1 - as = as - u15_12.23_sb3; +# a1 = a1 - u15_12.23_sb3; } # if (u15_12.23_sb3 ==4) From 9266d6b8d89c0edd3f060b3a3efdb9f854ff6760 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 25 May 2020 10:19:10 +0200 Subject: [PATCH 06/25] Improved entry instruction --- data/languages/xtensaTodo.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 15f87a9..ba760ca 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -35,8 +35,8 @@ # ENTRY - Subroutine Entry, pg. 340. :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { -# as normally a1 -# a1 = a1 - u15_12.23_sb3; + local amn = sext(u15_12.23_sb3); + as = as - amn; } # if (u15_12.23_sb3 ==4) From 302174465a743c8eb36d3e3cba074296ce4cb058 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Fri, 12 Jun 2020 16:11:39 +0200 Subject: [PATCH 07/25] Added special register decoding for wsr and rsr --- data/languages/xtensa.sinc | 31 ++++++++++++++++++++++++++ data/languages/xtensaInstructions.sinc | 20 +++++++++++------ data/languages/xtensaTodo.sinc | 8 ++++++- 3 files changed, 51 insertions(+), 8 deletions(-) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index 5b3ac59..0a78226 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -3,6 +3,7 @@ define alignment=1; define space ram type=ram_space size=4 default; define space register type=register_space size=4; +define space special_register type=ram_space size=4; # Address registers (AR). define register offset=0x0000 size=4 [ @@ -27,6 +28,32 @@ define register offset=0x1000 size=4 [ pc ]; # Shift amount register. (TODO: other special registers) define register offset=0x2000 size=1 [ sar ]; + +#not all registers are 32Bit but for sake of simplicity they are here +define special_register offset=0 size=4 [ LBEG LEND LCOUNT SAR BR LITBASE ]; +define special_register offset=48 size=4 [ SCOMPARE1 ]; +define special_register offset=64 size=4 [ ACCLO ACCHI ]; +define special_register offset=128 size=4 [ M0 M1 M2 M3 ]; +define special_register offset=288 size=4 [ WindowBase WindowStart ]; +define special_register offset=332 size=4 [ PTEVADDR ]; +define special_register offset=356 size=4 [ MMID RASID ITLBCFG DTLBCFG ]; +define special_register offset=384 size=4 [ IBREAKENABLE ]; +define special_register offset=392 size=4 [ CACHEATTR ATOMCTL ]; +define special_register offset=416 size=4 [ DDR ]; +define special_register offset=424 size=4 [ MEPC MEPS MESAVE MESR MECR MEVADDR ]; +define special_register offset=512 size=4 [ IBREAKA0 IBREAKA1 ]; +define special_register offset=576 size=4 [ DBREAKA0 DBREAKA1 ]; +define special_register offset=640 size=4 [ DBREAKC0 DBREAKC1 ]; +define special_register offset=708 size=4 [ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 ]; +define special_register offset=768 size=4 [ DEPC ]; +define special_register offset=776 size=4 [ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 ]; +define special_register offset=836 size=4 [ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 ]; +define special_register offset=896 size=4 [ CPENABLE ]; +define special_register offset=900 size=4 [ INTERRUPT INTSET INTCLEAR INTENABLE ];# assuming it's a typo in the manual and INTERRUPT has number 225 +define special_register offset=920 size=4 [ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR ]; +define special_register offset=960 size=4 [ CCOMPARE0 CCOMPARE1 CCOMPARE2 ]; +define special_register offset=976 size=4 [ MISC0 MISC1 MISC2 MISC3 ]; + # Regular 24-bit instruction. define token insn(24) # Named opcode/register fields. @@ -37,6 +64,7 @@ define token insn(24) as = (8,11) fs = (8,11) bs = (8,11) + sr = (8,15) at = (4,7) ft = (4,7) bt = (4,7) @@ -106,6 +134,9 @@ attach variables [ br bs bt ] [ b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 ]; +attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; + + # Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive # bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least # singificant operand half, LM the most significant bits of the least significant operand half, etc. diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index ec76230..535c4e6 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1002,9 +1002,10 @@ macro extract_bit(val, bit, result) { at = rsil(u4_8.11:1); } -# RSR - Read Special Register, pg. 500. -:rsr at, u8_8.15 is op0 = 0 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { - at = rsr(u8_8.15:1); +# RSR - Read Special Register, pg. 500. u8_8.15 +:rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 { + #at = rsr(u8_8.15:1); + at = *[special_register]sr; } # RSYNC - Register Read Synchronize, pg. 502. @@ -1276,9 +1277,11 @@ macro extract_bit(val, bit, result) { witlb(as, at); } -# WSR - Write Special Register, pg. 561. -:wsr at, u8_8.15 is op2 = 0b0001 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { - wsr(u8_8.15:1, at); +#WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0 +# WSR - Write Special Register, pg. 561. u8_8.15 +:wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 { + #wsr(u8_8.15:1, at); + *[special_register]:4 sr = at; } # WUR - Write User Register, pg. 563. @@ -1296,7 +1299,10 @@ macro extract_bit(val, bit, result) { br = bs ^^ bt; } -# XSR - Exchange Special Register, pg. 566. +# XSR - Exchange Special Register, pg. 566. u8_8.15 :xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 { at = xsr(u8_8.15:1, at); + #tmp = *[special_register]sr; + #*[special_register]:4 sr = at; + #at = tmp; } diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index ba760ca..0f6e988 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -122,7 +122,13 @@ # RETW.N - Narrow Windowed Return, pg. 482. :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { - return [a0]; + a10=a2; + a11=a3; + a12=a4; + a13=a5; + a14=a6; + a15=a7; + return [a0]; } # ROTW - Rotate Window, pg. 496. From 201ffbb26b13cb51881cafcab07054f9facce522 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Sun, 14 Jun 2020 11:13:48 +0200 Subject: [PATCH 08/25] Added pad dummy instructions --- data/languages/xtensa.sinc | 8 ++++++++ data/languages/xtensaInstructions.sinc | 8 ++++++++ data/languages/xtensaTodo.sinc | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index 0a78226..ed4eb74 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -122,6 +122,14 @@ define token narrowinsn(16) ; +define token opbyte (8) + op0_8 = (0,7) +; + +define token opword (16) + op0_16 = (0,15) +; + attach variables [ ar as at n_ar n_as n_at ] [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 ]; diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 535c4e6..51228db 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1306,3 +1306,11 @@ macro extract_bit(val, bit, result) { #*[special_register]:4 sr = at; #at = tmp; } + +:pad is op0_16=0x0 { +} + +:pad is op0_8=0x0 { +} + + diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 0f6e988..24c3158 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -116,7 +116,7 @@ :movsp at, as is op2 = 0 & op1 = 0 & ar = 0b0001 & as & at & op0 = 0 unimpl # RETW - Windowed Return, pg. 480. -:retw is op2 = 0 & ar = 0 & as = 0 & at = 0 & u2_18.19 = 0b10 & u2_16.17 = 0b01 & op0 = 0 { +:retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6.7 = 0b10 & u2_4.5 = 0b01 & op0 = 0 { return [a0]; } From a3e8b8b2dd9eceacee5e47dad1755db16e1110ad Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Tue, 16 Jun 2020 22:22:32 +0200 Subject: [PATCH 09/25] Removed pad, added callX8 --- data/languages/xtensa.sinc | 12 ++++++------ data/languages/xtensaInstructions.sinc | 10 ++++++---- data/languages/xtensaTodo.sinc | 10 ++++++++-- 3 files changed, 20 insertions(+), 12 deletions(-) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index ed4eb74..ca373c3 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -122,13 +122,13 @@ define token narrowinsn(16) ; -define token opbyte (8) - op0_8 = (0,7) -; +#define token opbyte (8) +# op0_8 = (0,7) +#; -define token opword (16) - op0_16 = (0,15) -; +#define token opword (16) +# op0_16 = (0,15) +#; attach variables [ ar as at n_ar n_as n_at ] [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 51228db..4c06099 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1307,10 +1307,12 @@ macro extract_bit(val, bit, result) { #at = tmp; } -:pad is op0_16=0x0 { -} +# PAD, dummy +#:pad is op0_16=0x0 { +#} -:pad is op0_8=0x0 { -} +# PAD, dummy +#:pad is op0_8=0x0 { +#} diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 24c3158..9d73555 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -35,8 +35,8 @@ # ENTRY - Subroutine Entry, pg. 340. :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { - local amn = sext(u15_12.23_sb3); - as = as - amn; + #local amn = sext(u15_12.23_sb3); + #as = as + amn; } # if (u15_12.23_sb3 ==4) @@ -94,6 +94,12 @@ # CALLX8 - Call Register, Rotate Window by 8, pg. 307. :callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b10 & op0 = 0 { local dst = as; + a2=a10; + a3=a11; + a4=a12; + a5=a13; + a6=a14; + a7=a15; a0 = inst_start + 3; call [dst]; } From c290afca4d34d3c526264b0542f002d1b777891d Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Sun, 28 Jun 2020 02:47:54 +0200 Subject: [PATCH 10/25] Improved stack allocation on enter --- data/languages/xtensaTodo.sinc | 47 ++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 9d73555..a27e51a 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -1,3 +1,17 @@ +macro pushVal(val32) { + local addr:4 = a1; + a1 = a1 - 4; + *:4 addr = val32; +} + +macro popVal(val32) { + local addr:4 = a1; + val32 = *:4 addr; + a1 = a1 + 4; +} + + + ## Windowed Register Option ## # CALL4 - Call PC-relative, Rotate Window by 4, pg. 298. @@ -14,6 +28,12 @@ # CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. :call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 { local dst = srel_6.23_sb2; + #s2=a2; + #s3=a3; + #s4=a4; + #s5=a5; + #s6=a6; + #s7=a7; a2=a10; a3=a11; a4=a12; @@ -35,8 +55,10 @@ # ENTRY - Subroutine Entry, pg. 340. :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { - #local amn = sext(u15_12.23_sb3); + local amn = sext(u15_12.23_sb3); #as = as + amn; + WindowBase = amn; + a1 = a1 - amn; } # if (u15_12.23_sb3 ==4) @@ -94,6 +116,12 @@ # CALLX8 - Call Register, Rotate Window by 8, pg. 307. :callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b10 & op0 = 0 { local dst = as; + #s2=a2; + #s3=a3; + #s4=a4; + #s5=a5; + #s6=a6; + #s7=a7; a2=a10; a3=a11; a4=a12; @@ -123,6 +151,20 @@ # RETW - Windowed Return, pg. 480. :retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6.7 = 0b10 & u2_4.5 = 0b01 & op0 = 0 { +# Assume call8 + a10=a2; + a11=a3; + a12=a4; + a13=a5; + a14=a6; + a15=a7; + #a2=s2; + #a3=s3; + #a4=s4; + #a5=s5; + #a6=s6; + #a7=s7; + a1 = a1 + WindowBase; return [a0]; } @@ -133,7 +175,8 @@ a12=a4; a13=a5; a14=a6; - a15=a7; + a15=a7; + a1 = a1 + WindowBase; return [a0]; } From fb191336c8c8a3398a9f5d5244e01114479e334d Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Tue, 14 Jul 2020 09:47:53 +0200 Subject: [PATCH 11/25] Goto inst_start on illegal instructions --- data/languages/xtensaInstructions.sinc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 4c06099..468b9fe 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -480,11 +480,13 @@ macro extract_bit(val, bit, result) { # ILL - Illegal Instruction, pg. 358. :ill is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & at = 0 & op0 = 0 { ill(); + goto inst_start; } # ILL.N - Narrow Illegal Instruction, pg. 359. :ill.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0110 & n_op0 = 0b1101 { ill(); + goto inst_start; } # IPF - Instruction Cache Prefetch, pg. 360. From f471375e24d2e4dead3d96d6636a6dd0d02644be Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Tue, 14 Jul 2020 11:27:40 +0200 Subject: [PATCH 12/25] sr register varnode issue --- data/languages/xtensa.sinc | 3 +-- data/languages/xtensaInstructions.sinc | 24 +++++++++++------------- data/languages/xtensaTodo.sinc | 4 ++-- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index ca373c3..0d269ac 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -64,7 +64,6 @@ define token insn(24) as = (8,11) fs = (8,11) bs = (8,11) - sr = (8,15) at = (4,7) ft = (4,7) bt = (4,7) @@ -142,7 +141,7 @@ attach variables [ br bs bt ] [ b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 ]; -attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; +#attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; # Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 468b9fe..479ccfd 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1004,10 +1004,9 @@ macro extract_bit(val, bit, result) { at = rsil(u4_8.11:1); } -# RSR - Read Special Register, pg. 500. u8_8.15 -:rsr at, sr is op0 = 0 & op1 = 0b0011 & sr & at & op0 = 0 { - #at = rsr(u8_8.15:1); - at = *[special_register]sr; +# RSR - Read Special Register, pg. 500. +:rsr at, u8_8.15 is op0 = 0 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { + at = rsr(u8_8.15:1); } # RSYNC - Register Read Synchronize, pg. 502. @@ -1279,12 +1278,14 @@ macro extract_bit(val, bit, result) { witlb(as, at); } -#WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0 -# WSR - Write Special Register, pg. 561. u8_8.15 -:wsr at, sr is op2 = 0b0001 & op1 = 0b0011 & sr & at & op0 = 0 { - #wsr(u8_8.15:1, at); - *[special_register]:4 sr = at; +# WSR - Write Special Register, pg. 561. +:wsr at, u8_8.15 is op2 = 0b0001 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { + wsr(u8_8.15:1, at); } +#:WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0 +#{ +# *[special_register]:4 sr = at; +#} # WUR - Write User Register, pg. 563. :wur at, u8_8.15 is op2 = 0b1111 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { @@ -1301,12 +1302,9 @@ macro extract_bit(val, bit, result) { br = bs ^^ bt; } -# XSR - Exchange Special Register, pg. 566. u8_8.15 +# XSR - Exchange Special Register, pg. 566. :xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 { at = xsr(u8_8.15:1, at); - #tmp = *[special_register]sr; - #*[special_register]:4 sr = at; - #at = tmp; } # PAD, dummy diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index a27e51a..58c2316 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -164,7 +164,7 @@ macro popVal(val32) { #a5=s5; #a6=s6; #a7=s7; - a1 = a1 + WindowBase; + #a1 = a1 + WindowBase; return [a0]; } @@ -176,7 +176,7 @@ macro popVal(val32) { a13=a5; a14=a6; a15=a7; - a1 = a1 + WindowBase; + #a1 = a1 + WindowBase; return [a0]; } From 4c65ae60c585edcc1b20acfd18988c947c332dce Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Tue, 14 Jul 2020 12:45:39 +0200 Subject: [PATCH 13/25] Reserve space on stack --- data/languages/xtensaTodo.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 58c2316..a27e51a 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -164,7 +164,7 @@ macro popVal(val32) { #a5=s5; #a6=s6; #a7=s7; - #a1 = a1 + WindowBase; + a1 = a1 + WindowBase; return [a0]; } @@ -176,7 +176,7 @@ macro popVal(val32) { a13=a5; a14=a6; a15=a7; - #a1 = a1 + WindowBase; + a1 = a1 + WindowBase; return [a0]; } From 7c0d6f329d2301df1c47ebfb1e1ea5f12a13b9e3 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Tue, 14 Jul 2020 14:13:04 +0200 Subject: [PATCH 14/25] Experiments with save/restore registers for call8 --- data/languages/xtensa.sinc | 7 +++++++ data/languages/xtensaTodo.sinc | 18 ++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index 0d269ac..5260c3a 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -4,6 +4,13 @@ define alignment=1; define space ram type=ram_space size=4 default; define space register type=register_space size=4; define space special_register type=ram_space size=4; +define space save_register type=ram_space size=4; + +# Address registers (AR). +define save_register offset=0x0000 size=4 [ + sa0 sa1 sa2 sa3 sa4 sa5 sa6 sa7 sa8 sa9 sa10 sa11 sa12 sa13 sa14 sa15 +]; + # Address registers (AR). define register offset=0x0000 size=4 [ diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index a27e51a..c40177c 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -11,6 +11,22 @@ macro popVal(val32) { } +macro save() { + sa3 = a3; + sa4 = a4; + sa5 = a5; + sa6 = a6; + sa7 = a7; +} + +macro restore() { + a3 = sa3; + a4 = sa4; + a5 = sa5; + a6 = sa6; + a7 = sa7; +} + ## Windowed Register Option ## @@ -28,6 +44,7 @@ macro popVal(val32) { # CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. :call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 { local dst = srel_6.23_sb2; + save(); #s2=a2; #s3=a3; #s4=a4; @@ -42,6 +59,7 @@ macro popVal(val32) { a7=a15; a0 = inst_start + 3; call [dst]; + restore(); } # CALL12 - Call PC-relative, Rotate Window by 12, pg. 302. From 16a3fcf124f9a26cb2af243bc9dc60bb09273625 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Thu, 16 Jul 2020 02:59:59 +0200 Subject: [PATCH 15/25] Updated links --- README.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 02f336c..e660867 100644 --- a/README.md +++ b/README.md @@ -6,7 +6,7 @@ ``` $ cd ghidra_9.1.X/Ghidra/Processors -$ git clone https://github.com/yath/ghidra-xtensa Xtensa +$ git clone https://github.com/Ebiroll/ghidra-xtensa Xtensa $ cd Xtensa $ make $ @@ -18,10 +18,13 @@ Or download a pre-built release and unzip it to `Ghidra/Processors`. * Probably a lot in instructions I did not yet happen to encouter. Pull requests appreciated. +Also see these, Flash loader +* https://github.com/Ebiroll/esp32_flash_loader +* https://medium.com/@olof.astrand/a-story-about-elfs-dwarfs-and-dragons-6de2a1df42ad # TODO * Windowed Register Option * MAC16 Option * Loop Option -* ESP8266/ESP32 image loaders? + From 7c2f3dfea23983fa7d1719dd0bab80e92c968502 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Fri, 31 Jul 2020 03:16:54 +0200 Subject: [PATCH 16/25] Add fake iX and oX registers to get a better decompilation for esp32 binaries --- build.gradle | 10 ++ data/languages/xtensa.cspec | 29 +++-- data/languages/xtensa.sinc | 2 + data/languages/xtensaInstructions.sinc | 15 +++ data/languages/xtensaTodo.sinc | 141 +++++++++---------------- 5 files changed, 94 insertions(+), 103 deletions(-) create mode 100644 build.gradle diff --git a/build.gradle b/build.gradle new file mode 100644 index 0000000..c190f1f --- /dev/null +++ b/build.gradle @@ -0,0 +1,10 @@ +apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" +apply from: "$rootProject.projectDir/gradle/javaProject.gradle" +apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle" +apply from: "$rootProject.projectDir/gradle/processorProject.gradle" +apply plugin: 'eclipse' +eclipse.project.name = 'Processors Xtensa' + +dependencies { + compile project(':Base') +} diff --git a/data/languages/xtensa.cspec b/data/languages/xtensa.cspec index f7049a2..7c1b787 100644 --- a/data/languages/xtensa.cspec +++ b/data/languages/xtensa.cspec @@ -30,22 +30,22 @@ - + - + - + - + - + - + @@ -53,16 +53,16 @@ - + - + - + - + @@ -70,6 +70,15 @@ + + + + + + + + + diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index 5260c3a..55d32ab 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -15,6 +15,8 @@ define save_register offset=0x0000 size=4 [ # Address registers (AR). define register offset=0x0000 size=4 [ a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 + i2 i3 i4 i5 i6 i7 + o2 o3 o4 o5 o6 o7 ]; # Floating Point registers (FR + FCR (control) + FSR (status)). diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 479ccfd..d6f9c4e 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -303,15 +303,29 @@ macro extract_bit(val, bit, result) { # CALL0 - Non-windowed Call, pg. 297. :call0 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0 & op0 = 0b0101 { + i2 = a2; + i3 = a3; + i4 = a4; + i5 = a5; + i6 = a6; + i7 = a7; a0 = inst_start + 3; call srel_6.23_sb2; + a2=o2; } # CALLX0 - Non-windowed Call Register, pg. 304. :callx0 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0 & op0 = 0 { local dst = as; + i2 = a2; + i3 = a3; + i4 = a4; + i5 = a5; + i6 = a6; + i7 = a7; a0 = inst_start + 3; call [dst]; + a2=o2; } # CEIL.S - Ceiling Single to Fixed, pg. 311. @@ -931,6 +945,7 @@ macro extract_bit(val, bit, result) { # RET.N - Narrow Non-Windowed Return, pg. 479. :ret.n is n_ar = 0b1111 & n_as = 0 & n_at = 0 & n_op0 = 0b1101 { return [a0]; + o2=a2; } # RFDD - Return from Debug and Dispatch, pg. 484. diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index c40177c..aa820b9 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -33,130 +33,92 @@ macro restore() { # CALL4 - Call PC-relative, Rotate Window by 4, pg. 298. :call4 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b01 & op0 = 0b0101 { local dst = srel_6.23_sb2; - a2=a6; - a3=a7; - a4=a8; - a5=a9; + i2=a6; + i3=a7; + i4=a8; + i5=a9; a0 = inst_start + 3; call [dst]; + a6=o2; } # CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. :call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 { local dst = srel_6.23_sb2; - save(); - #s2=a2; - #s3=a3; - #s4=a4; - #s5=a5; - #s6=a6; - #s7=a7; - a2=a10; - a3=a11; - a4=a12; - a5=a13; - a6=a14; - a7=a15; + i2=a10; + i3=a11; + i4=a12; + i5=a13; + i6=a14; + i7=a15; a0 = inst_start + 3; call [dst]; - restore(); + a10=o2; } # CALL12 - Call PC-relative, Rotate Window by 12, pg. 302. :call12 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b11 & op0 = 0b0101 { local dst = srel_6.23_sb2; - a2=a14; - a3=a15; + i2=a14; + i3=a15; a0 = inst_start + 3; call [dst]; + a14=o2; } # ENTRY - Subroutine Entry, pg. 340. :entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { local amn = sext(u15_12.23_sb3); + a2=i2; + a3=i3; + a4=i4; + a5=i5; + a6=i6; + a7=i7; #as = as + amn; WindowBase = amn; a1 = a1 - amn; } -# if (u15_12.23_sb3 ==4) -# goto ; -# if (u15_12.23_sb3 ==8) -# goto ; -# if (u15_12.23_sb3 ==12) -# goto ; -# -# a2=a6; -# a3=a7; -# a4=a8; -# a5=a9; -# a6=a10; -# a7=a11; -# a8=a12; -# a9=a13; -# a10=a14; -# a11=a15; -# goto ; -# -# a2=a10; -# a3=a11; -# a4=a12; -# a5=a13; -# a6=a14; -# a7=a15; -# goto ; -# -# a2=a14; -# a3=a15; -# - - # CALLX4 - Call Register, Rotate Window by 4, pg. 305. :callx4 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b01 & op0 = 0 { local dst = as; - a2=a6; - a3=a7; - a4=a8; - a5=a9; - a6=a10; - a7=a11; - a8=a12; - a9=a13; - a10=a14; - a11=a15; + i2=a6; + i3=a7; + i4=a8; + i5=a9; + i6=a10; + i7=a11; a0 = inst_start + 3; call [dst]; + a6=o2; } # CALLX8 - Call Register, Rotate Window by 8, pg. 307. :callx8 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b10 & op0 = 0 { local dst = as; - #s2=a2; - #s3=a3; - #s4=a4; - #s5=a5; - #s6=a6; - #s7=a7; - a2=a10; - a3=a11; - a4=a12; - a5=a13; - a6=a14; - a7=a15; + i2=a10; + i3=a11; + i4=a12; + i5=a13; + i6=a14; + i7=a15; a0 = inst_start + 3; call [dst]; + a10=o2; } # CALLX12 - Call Register, Rotate Window by 12, pg. 308. :callx12 as is op2 = 0 & op1 = 0 & ar = 0 & as & u2_6.7 = 0b11 & u2_4.5 = 0b11 & op0 = 0 { local dst = as; - a2=a14; - a3=a15; + i2=a14; + i3=a15; a0 = inst_start + 3; call [dst]; + a14=o2; } @@ -170,30 +132,23 @@ macro restore() { # RETW - Windowed Return, pg. 480. :retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6.7 = 0b10 & u2_4.5 = 0b01 & op0 = 0 { # Assume call8 - a10=a2; - a11=a3; - a12=a4; - a13=a5; - a14=a6; - a15=a7; - #a2=s2; - #a3=s3; - #a4=s4; - #a5=s5; - #a6=s6; - #a7=s7; + o2=a2; + o3=a3; + o4=a4; + a10=a2; a1 = a1 + WindowBase; return [a0]; } # RETW.N - Narrow Windowed Return, pg. 482. :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { + o2=a2; + o3=a3; + o4=a4; + o5=a5; + o6=a6; + o7=a7; a10=a2; - a11=a3; - a12=a4; - a13=a5; - a14=a6; - a15=a7; a1 = a1 + WindowBase; return [a0]; } From a4f9f6306355c38fb73acf05e93d1ada778a6b87 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 3 Aug 2020 01:53:02 +0200 Subject: [PATCH 17/25] Updated call0 --- data/languages/xtensaInstructions.sinc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index d6f9c4e..3e408ef 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -303,6 +303,7 @@ macro extract_bit(val, bit, result) { # CALL0 - Non-windowed Call, pg. 297. :call0 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0 & op0 = 0b0101 { + local dst = srel_6.23_sb2; i2 = a2; i3 = a3; i4 = a4; @@ -310,7 +311,7 @@ macro extract_bit(val, bit, result) { i6 = a6; i7 = a7; a0 = inst_start + 3; - call srel_6.23_sb2; + call [dst]; a2=o2; } From 0fdb885926193fd6e32d8d13ada5fbc8bac8d408 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 3 Aug 2020 02:38:54 +0200 Subject: [PATCH 18/25] Only one output variable --- data/languages/xtensaTodo.sinc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index aa820b9..9f39b09 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -133,9 +133,6 @@ macro restore() { :retw is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & u2_6.7 = 0b10 & u2_4.5 = 0b01 & op0 = 0 { # Assume call8 o2=a2; - o3=a3; - o4=a4; - a10=a2; a1 = a1 + WindowBase; return [a0]; } @@ -143,12 +140,6 @@ macro restore() { # RETW.N - Narrow Windowed Return, pg. 482. :retw.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0001 & n_op0 = 0b1101 { o2=a2; - o3=a3; - o4=a4; - o5=a5; - o6=a6; - o7=a7; - a10=a2; a1 = a1 + WindowBase; return [a0]; } From 993caed1c20c6fefb2a6706be3677da6b3b21d22 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 3 Aug 2020 04:33:16 +0200 Subject: [PATCH 19/25] No o2 on call 0 --- data/languages/xtensaInstructions.sinc | 2 -- data/languages/xtensaTodo.sinc | 5 ++++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 3e408ef..4e68f53 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -312,7 +312,6 @@ macro extract_bit(val, bit, result) { i7 = a7; a0 = inst_start + 3; call [dst]; - a2=o2; } # CALLX0 - Non-windowed Call Register, pg. 304. @@ -326,7 +325,6 @@ macro extract_bit(val, bit, result) { i7 = a7; a0 = inst_start + 3; call [dst]; - a2=o2; } # CEIL.S - Ceiling Single to Fixed, pg. 311. diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 9f39b09..1e0a8eb 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -150,7 +150,10 @@ macro restore() { } # S32E - Store 32-bit for Window Exceptions, pg. 508. -:s32e at, as, s5_12.15_oex is op2 = 0b0100 & op1 = 0b1001 & s5_12.15_oex & as & at & op0 = 0 unimpl +:s32e at, as, s5_12.15_oex is op2 = 0b0100 & op1 = 0b1001 & s5_12.15_oex & as & at & op0 = 0 { + #local vAddr:4 = as + s5_12.15_oex; + #*:4 vAddr = at; +} ## MAC16 option ## From 47eea0d9f758e58d5ddf9cc7078c6e3ee6faffd3 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 3 Aug 2020 20:30:18 +0200 Subject: [PATCH 20/25] Do not call from temporary vaiable --- data/languages/xtensaInstructions.sinc | 4 ++-- data/languages/xtensaTodo.sinc | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 4e68f53..b54eee7 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -303,7 +303,7 @@ macro extract_bit(val, bit, result) { # CALL0 - Non-windowed Call, pg. 297. :call0 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0 & op0 = 0b0101 { - local dst = srel_6.23_sb2; + #local dst = srel_6.23_sb2; i2 = a2; i3 = a3; i4 = a4; @@ -311,7 +311,7 @@ macro extract_bit(val, bit, result) { i6 = a6; i7 = a7; a0 = inst_start + 3; - call [dst]; + call srel_6.23_sb2; } # CALLX0 - Non-windowed Call Register, pg. 304. diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 1e0a8eb..ecdfb2a 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -32,19 +32,19 @@ macro restore() { # CALL4 - Call PC-relative, Rotate Window by 4, pg. 298. :call4 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b01 & op0 = 0b0101 { - local dst = srel_6.23_sb2; + #local dst = srel_6.23_sb2; i2=a6; i3=a7; i4=a8; i5=a9; a0 = inst_start + 3; - call [dst]; + call srel_6.23_sb2; a6=o2; } # CALL8 - Call PC-relative, Rotate Window by 8, pg. 300. :call8 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b10 & op0 = 0b0101 { - local dst = srel_6.23_sb2; + #local dst:4 = i2=a10; i3=a11; i4=a12; @@ -52,17 +52,17 @@ macro restore() { i6=a14; i7=a15; a0 = inst_start + 3; - call [dst]; + call srel_6.23_sb2; a10=o2; } # CALL12 - Call PC-relative, Rotate Window by 12, pg. 302. :call12 srel_6.23_sb2 is srel_6.23_sb2 & u2_4.5 = 0b11 & op0 = 0b0101 { - local dst = srel_6.23_sb2; + #local dst = srel_6.23_sb2; i2=a14; i3=a15; a0 = inst_start + 3; - call [dst]; + call srel_6.23_sb2; a14=o2; } From ca97d47a74332c60fea56150efab5a09ebd44b23 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 3 Aug 2020 20:46:11 +0200 Subject: [PATCH 21/25] Added information links --- README.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index e660867..2e300ff 100644 --- a/README.md +++ b/README.md @@ -18,13 +18,14 @@ Or download a pre-built release and unzip it to `Ghidra/Processors`. * Probably a lot in instructions I did not yet happen to encouter. Pull requests appreciated. -Also see these, Flash loader + +# More info * https://github.com/Ebiroll/esp32_flash_loader * https://medium.com/@olof.astrand/a-story-about-elfs-dwarfs-and-dragons-6de2a1df42ad +* https://medium.com/@olof.astrand/enter-home-dragon-with-ghidra-3ed7ddf75935 # TODO -* Windowed Register Option * MAC16 Option * Loop Option From 7efcae47e765377b2fa6f68b42eb4166b74332c6 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Wed, 5 Aug 2020 16:56:42 +0200 Subject: [PATCH 22/25] Improved decoding of special registers --- data/languages/xtensa.sinc | 3 ++- data/languages/xtensaInstructions.sinc | 4 ++++ data/languages/xtensaTodo.sinc | 6 ++++-- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index 55d32ab..c86cf62 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -47,6 +47,7 @@ define special_register offset=288 size=4 [ WindowBase WindowStart ]; define special_register offset=332 size=4 [ PTEVADDR ]; define special_register offset=356 size=4 [ MMID RASID ITLBCFG DTLBCFG ]; define special_register offset=384 size=4 [ IBREAKENABLE ]; +define special_register offset=388 size=4 [ MEMCTL ]; define special_register offset=392 size=4 [ CACHEATTR ATOMCTL ]; define special_register offset=416 size=4 [ DDR ]; define special_register offset=424 size=4 [ MEPC MEPS MESAVE MESR MECR MEVADDR ]; @@ -150,7 +151,7 @@ attach variables [ br bs bt ] [ b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 ]; -#attach variables [ sr ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE _ CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; +attach variables [ u8_8.15 ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE MEMCTL CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; # Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index b54eee7..59b9fd8 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1020,7 +1020,9 @@ macro extract_bit(val, bit, result) { # RSR - Read Special Register, pg. 500. :rsr at, u8_8.15 is op0 = 0 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { + local src:4 = zext(u8_8.15:1); at = rsr(u8_8.15:1); + at = *[special_register]:4 src; } # RSYNC - Register Read Synchronize, pg. 502. @@ -1294,6 +1296,8 @@ macro extract_bit(val, bit, result) { # WSR - Write Special Register, pg. 561. :wsr at, u8_8.15 is op2 = 0b0001 & op1 = 0b0011 & u8_8.15 & at & op0 = 0 { + local dst:4 = zext(u8_8.15:1); + *[special_register]:4 dst = at; wsr(u8_8.15:1, at); } #:WSR.^sr at is op2=0x1 & op1=0x3 & sr & at & op0=0x0 diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index ecdfb2a..b941c09 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -124,7 +124,9 @@ macro restore() { # L32E - Load 32-bit for Window Exceptions, pg. 376. -:l32e at, as, s5_12.15_oex is op2 = 0 & op1 = 0b1001 & s5_12.15_oex & as & at & op0 = 0 unimpl +:l32e at, as, s5_12.15_oex is op2 = 0 & op1 = 0b1001 & s5_12.15_oex & as & at & op0 = 0 { + +} # MOVSP - Move to Stack Pointer, pg. 427. :movsp at, as is op2 = 0 & op1 = 0 & ar = 0b0001 & as & at & op0 = 0 unimpl @@ -146,7 +148,7 @@ macro restore() { # ROTW - Rotate Window, pg. 496. :rotw s4_4.7 is op2 = 0b0100 & op1 = 0 & ar = 0b1000 & as = 0 & s4_4.7 & op0 = 0 { - + WindowBase = WindowBase + s4_4.7; } # S32E - Store 32-bit for Window Exceptions, pg. 508. From c39a1d507678810bad63fb39028c8d03b83ccd2c Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 12 Oct 2020 11:31:29 +0200 Subject: [PATCH 23/25] Fix bbsi --- data/languages/xtensaInstructions.sinc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 59b9fd8..7885779 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -155,7 +155,7 @@ macro extract_bit(val, bit, result) { :bbsi as, u5_4.7_12, srel_16.23 is srel_16.23 & u3_13.15 = 0b111 & as & u5_4.7_12 & op0 = 0b0111 { local bval; extract_bit(as, u5_4.7_12, bval); - if (bval == 0) + if (bval != 0) goto srel_16.23; } From 98356cbd10a601b89af4cdcc69bf61e045ce63be Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Fri, 4 Dec 2020 17:32:07 +0100 Subject: [PATCH 24/25] slli high bit correction --- data/languages/xtensaInstructions.sinc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index 7885779..3f20661 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1106,11 +1106,12 @@ macro extract_bit(val, bit, result) { } # SLLI - Shift Left Logical Immediate, pg. 525. -:slli ar, as, u5_4.7_20 is u3_21.23 = 0 & u5_4.7_20 & op1 = 0b0001 & ar & as & op0 = 0 { - local sa:1 = 32 - u5_4.7_20; +:slli ar, as, u5_4.7_20 is u3_21.23 = 0 & u1_20 & u5_4.7_20 & op1 = 0b0001 & ar & as & op0 = 0 { + local sa:1 = 32 - 16 * u1_20 - u5_4.7_20; ar = as << sa; } + # SRA - Shift Right Arithmetic, pg. 526. :sra ar, at is op2 = 0b1011 & op1 = 0b0001 & ar & as = 0 & at & op0 = 0 { ar = at s>> sar; From 4c6216bcd7d458ab2540f15a1dce9478943fd119 Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Mon, 19 Jul 2021 16:03:11 +0200 Subject: [PATCH 25/25] Updates to work with Ghidra 10.0 --- data/languages/xtensa.sinc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index c86cf62..0d93bf4 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -39,7 +39,7 @@ define register offset=0x2000 size=1 [ sar ]; #not all registers are 32Bit but for sake of simplicity they are here -define special_register offset=0 size=4 [ LBEG LEND LCOUNT SAR BR LITBASE ]; +define special_register offset=0 size=4 [ LBEG LEND LCOUNT OSAR BR LITBASE ]; define special_register offset=48 size=4 [ SCOMPARE1 ]; define special_register offset=64 size=4 [ ACCLO ACCHI ]; define special_register offset=128 size=4 [ M0 M1 M2 M3 ]; @@ -151,7 +151,7 @@ attach variables [ br bs bt ] [ b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 ]; -attach variables [ u8_8.15 ] [ LBEG LEND LCOUNT SAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE MEMCTL CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; +attach variables [ u8_8.15 ] [ LBEG LEND LCOUNT OSAR BR LITBASE _ _ _ _ _ _ SCOMPARE1 _ _ _ ACCLO ACCHI _ _ _ _ _ _ _ _ _ _ _ _ _ _ M0 M1 M2 M3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ WindowBase WindowStart _ _ _ _ _ _ _ _ _ PTEVADDR _ _ _ _ _ MMID RASID ITLBCFG DTLBCFG _ _ _ IBREAKENABLE MEMCTL CACHEATTR ATOMCTL _ _ _ _ DDR _ MEPC MEPS MESAVE MESR MECR MEVADDR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ IBREAKA0 IBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKA0 DBREAKA1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ DBREAKC0 DBREAKC1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ EPC1 EPC2 EPC3 EPC4 EPC5 EPC6 EPC7 _ _ _ _ _ _ _ _ DEPC _ EPS2 EPS3 EPS4 EPS5 EPS6 EPS7 _ _ _ _ _ _ _ _ _ EXCSAVE1 EXCSAVE2 EXCSAVE3 EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 _ _ _ _ _ _ _ _ CPENABLE INTERRUPT INTSET INTCLEAR INTENABLE _ PS VECBASE EXCCAUSE DEBUGCAUSE CCOUNT PRID ICOUNT ICOUNTLEVEL EXCVADDR _ CCOMPARE0 CCOMPARE1 CCOMPARE2 _ MISC0 MISC1 MISC2 MISC3 _ _ _ _ _ _ _ _ ]; # Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive