From d5a5eb7a6e090053a3eababb003e4a910fd593bd Mon Sep 17 00:00:00 2001 From: Olof Astrand Date: Sat, 16 May 2020 12:21:28 +0200 Subject: [PATCH] Updated with upstream manual merge --- data/languages/xtensa.dwarf | 2 +- data/languages/xtensa.ldefs | 2 +- data/languages/xtensa.sinc | 28 ++------- data/languages/xtensaInstructions.sinc | 78 ++++++++++---------------- data/languages/xtensaTodo.sinc | 40 ++++++++++++- 5 files changed, 73 insertions(+), 77 deletions(-) diff --git a/data/languages/xtensa.dwarf b/data/languages/xtensa.dwarf index afe6a2e..1790648 100644 --- a/data/languages/xtensa.dwarf +++ b/data/languages/xtensa.dwarf @@ -2,6 +2,6 @@ - + diff --git a/data/languages/xtensa.ldefs b/data/languages/xtensa.ldefs index e4e4a0e..80c6e25 100644 --- a/data/languages/xtensa.ldefs +++ b/data/languages/xtensa.ldefs @@ -12,6 +12,6 @@ id="Xtensa:LE:32:default"> Tensilica Xtensa 32-bit little-endian - + diff --git a/data/languages/xtensa.sinc b/data/languages/xtensa.sinc index efe9420..5b3ac59 100644 --- a/data/languages/xtensa.sinc +++ b/data/languages/xtensa.sinc @@ -67,7 +67,7 @@ define token insn(24) u1_12 = (12,12) u4_8.11 = (8,11) u8_4.11 = (4,11) - # s4_8.11 = (8,11) signed + s4_8.11 = (8,11) signed u2_6.7 = (6,7) u3_5.7 = (5,7) u4_4.7 = (4,7) @@ -138,11 +138,8 @@ u5_4.7_12: tmp is u1_12 & u4_4.7 [ tmp = (u1_12 << 4) | u4_4.7; ] { export * u5_8.11_4: tmp is u1_4 & u4_8.11 [ tmp = (u1_4 << 4) | u4_8.11; ] { export *[const]:1 tmp; } # Signed 12-bit (extended to 16) immediate, used by MOVI. -s16_16.23_8.11: tmp is u4_8.11 & u8_16.23 [ - # FIXME: This table, and the fields used, should be signed, but using s4_8.11 and s8_16.23 - # somehow confuses Ghidra. - tmp = (0xf000 * (u4_8.11 >> 3)) | # Sign-extend. - (u4_8.11 << 8) | u8_16.23; +s16_16.23_8.11: tmp is s4_8.11 & u8_16.23 [ + tmp = (s4_8.11 << 8) | u8_16.23; ] { export *[const]:2 tmp; } # An “asymmetric” immediate from -32..95, used by MOVI.N. @@ -167,25 +164,10 @@ n_u6_12.15_sb2: tmp is n_u4_12.15 [ tmp = n_u4_12.15 << 2; ] { export *[const]: s5_12.15_oex: tmp is u4_12.15 [ tmp = (2 << u4_12.15) * -1; ] { export *[const]:2 tmp; } # Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action. -# FIXME: “foo: tmp is u4_foo [ tmp = u4_foo; ]” doesn’t work when a more special constructor exists. # n_u4_4.7 with 0 being -1, used by ADDI.N. -n_s4_4.7_nozero: tmp is n_u4_4.7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 1 [ tmp = 1; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 2 [ tmp = 2; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 3 [ tmp = 3; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 4 [ tmp = 4; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 5 [ tmp = 5; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 6 [ tmp = 6; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 7 [ tmp = 7; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 8 [ tmp = 8; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 9 [ tmp = 9; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 10 [ tmp = 10; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 11 [ tmp = 11; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 12 [ tmp = 12; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 13 [ tmp = 13; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 14 [ tmp = 14; ] { export *[const]:4 tmp; } -n_s4_4.7_nozero: tmp is n_u4_4.7 = 15 [ tmp = 15; ] { export *[const]:4 tmp; } +n_s4_4.7_nozero: tmp is n_u4_4.7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; } +n_s4_4.7_nozero: tmp is n_u4_4.7 [ tmp = n_u4_4.7+0; ] { export *[const]:4 tmp; } # B4CONST(ar) (Branch Immediate) encodings, pg. 41 f. r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; } diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index c0ed1ae..ec76230 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -314,45 +314,6 @@ macro extract_bit(val, bit, result) { call [dst]; } -# ENTRY - Subroutine Entry, pg. 340. -:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { - #as=as-u15_12.23_sb3; -} - -# if (u15_12.23_sb3 ==4) -# goto ; -# if (u15_12.23_sb3 ==8) -# goto ; -# if (u15_12.23_sb3 ==12) -# goto ; -# -# a2=a6; -# a3=a7; -# a4=a8; -# a5=a9; -# a6=a10; -# a7=a11; -# a8=a12; -# a9=a13; -# a10=a14; -# a11=a15; -# goto ; -# -# a2=a10; -# a3=a11; -# a4=a12; -# a5=a13; -# a6=a14; -# a7=a15; -# goto ; -# -# a2=a14; -# a3=a15; -# - - - - # CEIL.S - Ceiling Single to Fixed, pg. 311. :ceil.s ar, fs, u4_4.7 is op2 = 0b1011 & op1 = 0b1010 & ar & fs & u4_4.7 & op0 = 0 { local scale:4 = int2float(1:1 << u4_4.7:1); @@ -868,7 +829,21 @@ macro extract_bit(val, bit, result) { # NSAU - Normalization Shift Amount Unsigned, pg. 462. (Count leading zeros) :nsau at, as is op2 = 0b0100 & op1 = 0 & ar = 0b1111 & as & at & op0 = 0 { - at = nsau(as); + local z4 = as[16,16] == 0; + + local t3 = zext(z4)*as[0,16] + zext(!z4)*as[16,16]; + local z3 = t3[8,8] == 0; + + local t2 = (z3)*t3[0,8] + (!z3)*t3[8,8]; + local z2 = t2[4,4] == 0; + + local t1 = (z2)*t2[0,4] + (!z2)*t2[4,4]; + local z1 = t1[2,2] == 0; + + local z0 = (z1)*(t1[1,1] == 0) + (!z1)*(t1[3,1] == 0); + local all0 = as == 0; + + at = zext((all0)*32 + (!all0)*(z4<<4 | z3<<3 | z2<<2 | z1<<1 | z0)); } # OEQ.S - Compare Single Equal, pg. 463. @@ -1108,13 +1083,13 @@ macro extract_bit(val, bit, result) { # SLL - Shift Left Logical, pg. 524. :sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 { - local sa:1 = 32 - (sar & 0xf); # XXX check this + local sa:1 = 32 - sar; ar = as << sa; } # SLLI - Shift Left Logical Immediate, pg. 525. :slli ar, as, u5_4.7_20 is u3_21.23 = 0 & u5_4.7_20 & op1 = 0b0001 & ar & as & op0 = 0 { - local sa:1 = 32 - u5_4.7_20; # XXX check this + local sa:1 = 32 - u5_4.7_20; ar = as << sa; } @@ -1179,12 +1154,12 @@ macro extract_bit(val, bit, result) { # SSL - Set Shift Amount for Left Shift, pg. 538. :ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 { - sar = 32 - (as:1 & 0xf); + sar = 32 - (as:1 & 0x1f); } # SSR - Set Shift Amount for Right Shift, pg. 539. :ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 { - sar = (as:1 & 0xf); + sar = (as:1 & 0x1f); } # SSX - Store Singe Indexed, pg. 540. @@ -1241,9 +1216,10 @@ macro extract_bit(val, bit, result) { br = nan(fs) || nan(ft) || fs f== ft; } -# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550. XXX: How is this different from float.as? +# UFLOAT.S - Convert Unsigned Fixed to Single, pg. 550. :ufloat.s fr, as, u4_4.7 is op2 = 0b1101 & op1 = 0b1010 & fr & as & u4_4.7 & op0 = 0 { - local f = int2float(as); + local tmp:8 = zext(as); + local f = int2float(tmp); local d = int2float(1:2 << u4_4.7:2); fr = d f/ f; } @@ -1265,10 +1241,14 @@ macro extract_bit(val, bit, result) { br = nan(fs) || nan(ft); } -# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555. FIXME: difference to trunc.s? +# UTRUNC.S - Truncate Single to Fixed Unsigned, pg. 555. :utrunc.s ar, fs, u4_4.7 is op2 = 0b1110 & op1 = 0b1010 & ar & fs & u4_4.7 & op0 = 0 { local scale:4 = int2float(1:2 << u4_4.7:2); - ar = trunc(fs f* scale); + local tmp:8 = trunc(fs f* scale); + local posof = nan(fs) || (tmp >> 16) != 0; + local negof = tmp s< 0; + local noof = !posof && !negof; + ar = zext(posof)*0xffffffff + zext(negof)*0x80000000 + zext(noof)*tmp:4; } # WAITI - Wait Interrupt, pg. 556. @@ -1317,6 +1297,6 @@ macro extract_bit(val, bit, result) { } # XSR - Exchange Special Register, pg. 566. -:xsr at, u8_8.15 is op2 = 0b1110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 { +:xsr at, u8_8.15 is op2 = 0b0110 & op1 = 0b0001 & u8_8.15 & at & op0 = 0 { at = xsr(u8_8.15:1, at); } diff --git a/data/languages/xtensaTodo.sinc b/data/languages/xtensaTodo.sinc index 2e88327..f85693f 100644 --- a/data/languages/xtensaTodo.sinc +++ b/data/languages/xtensaTodo.sinc @@ -34,10 +34,44 @@ } # ENTRY - Subroutine Entry, pg. 340. -#:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { +:entry as, u15_12.23_sb3 is u15_12.23_sb3 & as & u2_6.7 = 0b00 & u2_4.5 = 0b11 & op0 = 0b0110 { # as normally a1 -# #a1=a1-u15_12.23_sb3; -#} +# a1=a1-u15_12.23_sb3; +} + +# if (u15_12.23_sb3 ==4) +# goto ; +# if (u15_12.23_sb3 ==8) +# goto ; +# if (u15_12.23_sb3 ==12) +# goto ; +# +# a2=a6; +# a3=a7; +# a4=a8; +# a5=a9; +# a6=a10; +# a7=a11; +# a8=a12; +# a9=a13; +# a10=a14; +# a11=a15; +# goto ; +# +# a2=a10; +# a3=a11; +# a4=a12; +# a5=a13; +# a6=a14; +# a7=a15; +# goto ; +# +# a2=a14; +# a3=a15; +# + + + # CALLX4 - Call Register, Rotate Window by 4, pg. 305.