forked from yath/ghidra-xtensa
295 lines
11 KiB
Plaintext
295 lines
11 KiB
Plaintext
define endian=little;
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define alignment=1;
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define space ram type=ram_space size=4 default;
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define space register type=register_space size=4;
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# Address registers (AR).
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define register offset=0x0000 size=4 [
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a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
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];
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# Floating Point registers (FR + FCR (control) + FSR (status)).
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# TODO: FCR and FSR seem unused?
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define register offset=0x0100 size=4 [
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f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
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fcr fsr
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];
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# Boolean registers (BR).
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define register offset=0x0200 size=1 [
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b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
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];
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# Program counter.
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define register offset=0x1000 size=4 [ pc ];
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# Shift amount register. (TODO: other special registers)
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define register offset=0x2000 size=1 [ sar ];
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# Regular 24-bit instruction.
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define token insn(24)
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# Named opcode/register fields.
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op2 = (20,23)
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ar = (12,15)
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fr = (12,15)
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br = (12,15)
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as = (8,11)
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fs = (8,11)
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bs = (8,11)
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at = (4,7)
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ft = (4,7)
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bt = (4,7)
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op1 = (16,19)
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op0 = (0,3)
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# Signed and unsigned immediates. Named [us]N_L.M, where u and s denote signedness, L and M the
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# least and most significant bit of the immediate in the instruction word, and N the length
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# (i.e. M-L+1).
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u3_21.23 = (21,23)
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u4_20.23 = (20,23)
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s8_16.23 = (16,23) signed
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u8_16.23 = (16,23)
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u12_12.23 = (12,23)
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s12_12.23 = (12,23) signed
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u16_8.23 = (8,23)
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s8_6.23 = (6,23) signed
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u1_20 = (20,20)
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u2_18.19 = (18,19)
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u3_17.19 = (17,19)
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u2_16.17 = (16,17)
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u1_16 = (16,16)
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u2_14.15 = (14,15)
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u3_13.15 = (13,15)
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u4_12.15 = (12,15)
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u8_8.15 = (8,15)
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u2_12.13 = (12,13)
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u1_12 = (12,12)
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u4_8.11 = (8,11)
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u8_4.11 = (4,11)
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# s4_8.11 = (8,11) signed
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u2_6.7 = (6,7)
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u3_5.7 = (5,7)
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u4_4.7 = (4,7)
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s4_4.7 = (4,7)
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u2_4.5 = (4,5)
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u1_4 = (4,4)
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;
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# Narrow 16-bit instructions; fields are always prefixed with n_.
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define token narrowinsn(16)
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n_ar = (12,15)
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n_as = (8,11)
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n_at = (4,7)
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n_op0 = (0, 3)
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n_u4_12.15 = (12,15)
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n_s4_12.15 = (12,15) signed
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n_u4_8.11 = (8,11)
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n_u1_7 = (7,7)
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n_u2_6.7 = (6,7)
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n_u4_4.7 = (4,7)
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n_s3_4.6 = (4,6)
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n_u2_4.5 = (4,5)
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;
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attach variables [ ar as at n_ar n_as n_at ] [
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a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
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];
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attach variables [ fr fs ft ] [
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f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
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];
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attach variables [ br bs bt ] [
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b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
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];
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# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive
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# bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least
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# singificant operand half, LM the most significant bits of the least significant operand half, etc.
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urel_16.23: rel is u8_16.23 [ rel = inst_start + u8_16.23 + 4; ] { export *:4 rel; }
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srel_16.23: rel is s8_16.23 [ rel = inst_start + s8_16.23 + 4; ] { export *:4 rel; }
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srel_12.23: rel is s12_12.23 [ rel = inst_start + s12_12.23 + 4; ] { export *:4 rel; }
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srel_6.23: rel is s8_6.23 [ rel = inst_start + s8_6.23 + 4; ] { export *:4 rel; }
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urel_12.15_4.5: rel is n_u2_4.5 & n_u4_12.15 [
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rel = inst_start + ((n_u2_4.5 << 4) | n_u4_12.15) + 4;
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] { export *:4 rel; }
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srel_6.23_sb2: rel is s8_6.23 [
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rel = (inst_start & ~3) + ( s8_6.23 << 2 ) + 4;
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] { export *:4 rel; }
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srel_8.23_oex_sb2: rel is u16_8.23 [
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rel = ((inst_start + 3) & ~3) + ((u16_8.23 | 0xffff0000) << 2);
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] { export *:4 rel; }
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# Immediates split across the instruction.
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u5_8.11_20: tmp is u1_20 & u4_8.11 [ tmp = (u1_20 << 4) | u4_8.11; ] { export *[const]:1 tmp; }
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u5_4.7_20: tmp is u1_20 & u4_4.7 [ tmp = (u1_20 << 4) | u4_4.7; ] { export *[const]:1 tmp; }
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u5_8.11_16: tmp is u1_16 & u4_8.11 [ tmp = (u1_16 << 4) | u4_8.11; ] { export *[const]:1 tmp; }
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u5_4.7_12: tmp is u1_12 & u4_4.7 [ tmp = (u1_12 << 4) | u4_4.7; ] { export *[const]:1 tmp; }
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u5_8.11_4: tmp is u1_4 & u4_8.11 [ tmp = (u1_4 << 4) | u4_8.11; ] { export *[const]:1 tmp; }
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# Signed 12-bit (extended to 16) immediate, used by MOVI.
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s16_16.23_8.11: tmp is u4_8.11 & u8_16.23 [
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# FIXME: This table, and the fields used, should be signed, but using s4_8.11 and s8_16.23
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# somehow confuses Ghidra.
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tmp = (0xf000 * (u4_8.11 >> 3)) | # Sign-extend.
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(u4_8.11 << 8) | u8_16.23;
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] { export *[const]:2 tmp; }
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# An “asymmetric” immediate from -32..95, used by MOVI.N.
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n_s8_12.15_4.6_asymm: tmp is n_s3_4.6 & n_s4_12.15 [
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tmp = ((((n_s3_4.6 & 7) << 4) | (n_s4_12.15 & 15)) |
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((((n_s3_4.6 >> 2) & 1) & ((n_s3_4.6 >> 1) & 1)) << 7));
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] { export *[const]:1 tmp; }
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# Immediates shifted or with offset.
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s16_16.23_sb8: tmp is s8_16.23 [ tmp = s8_16.23 << 8; ] { export *[const]:2 tmp; }
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u15_12.23_sb3: tmp is u12_12.23 [ tmp = u12_12.23 << 3; ] { export *[const]:2 tmp; }
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u10_16.23_sb2: tmp is u8_16.23 [ tmp = u8_16.23 << 2; ] { export *[const]:2 tmp; }
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u9_16.23_sb1: tmp is u8_16.23 [ tmp = u8_16.23 << 1; ] { export *[const]:2 tmp; }
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u5_20.23_plus1: tmp is u4_20.23 [ tmp = u4_20.23 + 1; ] { export *[const]:1 tmp; }
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u8_20.23_sb4: tmp is u4_20.23 [ tmp = u4_20.23 << 4; ] { export *[const]:1 tmp; }
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u5_4.7_plus7: tmp is u4_4.7 [ tmp = u4_4.7 + 7; ] { export *[const]:1 tmp; }
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n_u6_12.15_sb2: tmp is n_u4_12.15 [ tmp = n_u4_12.15 << 2; ] { export *[const]:1 tmp; }
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# One-extended. FIXME: Verify this. Only used by [LS]32E (window extension), which aren’t yet
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# implemented.
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s5_12.15_oex: tmp is u4_12.15 [ tmp = (2 << u4_12.15) * -1; ] { export *[const]:2 tmp; }
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# Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action.
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# FIXME: “foo: tmp is u4_foo [ tmp = u4_foo; ]” doesn’t work when a more special constructor exists.
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# n_u4_4.7 with 0 being -1, used by ADDI.N.
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 0 [ tmp = -1; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 1 [ tmp = 1; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 2 [ tmp = 2; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 3 [ tmp = 3; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 4 [ tmp = 4; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 5 [ tmp = 5; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 6 [ tmp = 6; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 7 [ tmp = 7; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 8 [ tmp = 8; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 9 [ tmp = 9; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 10 [ tmp = 10; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 11 [ tmp = 11; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 12 [ tmp = 12; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 13 [ tmp = 13; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 14 [ tmp = 14; ] { export *[const]:4 tmp; }
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n_s4_4.7_nozero: tmp is n_u4_4.7 = 15 [ tmp = 15; ] { export *[const]:4 tmp; }
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# B4CONST(ar) (Branch Immediate) encodings, pg. 41 f.
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r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 1 [ tmp = 0x1; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 2 [ tmp = 0x2; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 3 [ tmp = 0x3; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 4 [ tmp = 0x4; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 5 [ tmp = 0x5; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 6 [ tmp = 0x6; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 7 [ tmp = 0x7; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 8 [ tmp = 0x8; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 9 [ tmp = 0xa; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 10 [ tmp = 0xc; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 11 [ tmp = 0x10; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 12 [ tmp = 0x20; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 13 [ tmp = 0x40; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 14 [ tmp = 0x80; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 15 [ tmp = 0x100; ] { export *[const]:4 tmp; }
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# B4CONSTU(ar) (Branch Unsigned Immediate) encodings, pg. 42.
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r_b4constu: tmp is ar = 0 [ tmp = 0x8000; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 1 [ tmp = 0x1000; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 2 [ tmp = 0x2; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 3 [ tmp = 0x3; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 4 [ tmp = 0x4; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 5 [ tmp = 0x5; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 6 [ tmp = 0x6; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 7 [ tmp = 0x7; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 8 [ tmp = 0x8; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 9 [ tmp = 0xa; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 10 [ tmp = 0xc; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 11 [ tmp = 0x10; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 12 [ tmp = 0x20; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 13 [ tmp = 0x40; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 14 [ tmp = 0x80; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 15 [ tmp = 0x100; ] { export *[const]:4 tmp; }
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define pcodeop breakpoint;
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define pcodeop dhi;
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define pcodeop dhu;
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define pcodeop dhwb;
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define pcodeop dhwbi;
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define pcodeop dii;
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define pcodeop diu;
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define pcodeop diwb;
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define pcodeop diwbi;
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define pcodeop dpfl;
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define pcodeop dpfr;
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define pcodeop dpfro;
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define pcodeop dpfw;
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define pcodeop dpfwo;
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define pcodeop dsync;
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define pcodeop esync;
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define pcodeop excw;
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define pcodeop extw;
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define pcodeop idtlb;
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define pcodeop ihi;
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define pcodeop ihu;
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define pcodeop iii;
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define pcodeop iitlb;
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define pcodeop iiu;
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define pcodeop ill;
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define pcodeop ipf;
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define pcodeop ipfl;
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define pcodeop isync;
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define pcodeop acquire;
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define pcodeop ldct;
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define pcodeop lict;
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define pcodeop licw;
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define pcodeop memw;
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define pcodeop nsa;
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define pcodeop nsau;
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define pcodeop pdtlb;
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define pcodeop pitlb;
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define pcodeop rdtlb0;
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define pcodeop rdtlb1;
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define pcodeop rer;
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define pcodeop rfdd;
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define pcodeop rfde;
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define pcodeop rfdo;
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define pcodeop rfe;
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define pcodeop rfi;
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define pcodeop rfme;
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define pcodeop rfue;
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define pcodeop rfwo;
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define pcodeop rfwu;
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define pcodeop ritlb0;
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define pcodeop ritlb1;
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define pcodeop rsil;
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define pcodeop rsr; # TODO: Map known special registers.
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define pcodeop rsync;
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define pcodeop rur;
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define pcodeop s32c1i;
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define pcodeop release;
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define pcodeop sdct;
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define pcodeop sict;
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define pcodeop sicw;
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define pcodeop simcall;
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define pcodeop syscall;
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define pcodeop waiti;
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define pcodeop wdtlb;
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define pcodeop wer;
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define pcodeop witlb;
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define pcodeop wsr; # TODO: Map known special registers.
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define pcodeop wur;
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define pcodeop xsr;
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