diff --git a/HISTORY.rst b/HISTORY.rst index 19313d87..45380573 100644 --- a/HISTORY.rst +++ b/HISTORY.rst @@ -9,6 +9,10 @@ PlatformIO 2.0 * Project generator for `CodeBlocks IDE `__ (`issue #600 `_) +* New `Lattice iCE40 FPGA `__ + development platform for Lattice iCEstick FPGA Evaluation Kit and BQ IceZUM + Alhambra FPGA + (`issue #480 `_) * PlatformIO Library Registry in JSON format! Implemented ``--json-output`` and ``--page`` options for `platformio lib search `__ diff --git a/docs/platforms/creating_platform.rst b/docs/platforms/creating_platform.rst index 90fea1c7..fd14549e 100644 --- a/docs/platforms/creating_platform.rst +++ b/docs/platforms/creating_platform.rst @@ -152,6 +152,9 @@ Packages * - ``toolchain-gccmingw32`` - `MinGW `_ + * - ``toolchain-icestorm`` + - `GCC for FPGA IceStorm `_ + * - ``toolchain-timsp430`` - `msp-gcc `_, `GDB `_ diff --git a/docs/platforms/lattice_ice40.rst b/docs/platforms/lattice_ice40.rst new file mode 100644 index 00000000..b21d8bbd --- /dev/null +++ b/docs/platforms/lattice_ice40.rst @@ -0,0 +1,91 @@ +.. Copyright 2014-2016 Ivan Kravets + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + http://www.apache.org/licenses/LICENSE-2.0 + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +.. _platform_lattice_ice40: + +Platform ``lattice_ice40`` +========================== +The iCE40 family of ultra-low power, non-volatile FPGAs has five devices with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition to LUT-based,low-cost programmable logic, these devices feature Embedded Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked Loops (PLLs). These features allow the devices to be used in low-cost, high-volume consumer and system applications. + +For more detailed information please visit `vendor site `_. + +.. contents:: + +Packages +-------- + +.. list-table:: + :header-rows: 1 + + * - Name + - Contents + + * - ``toolchain-icestorm`` + - `GCC for FPGA IceStorm `_ + +.. warning:: + **Linux Users:** Don't forget to install "udev" rules file + `99-platformio-udev.rules `_ (an instruction is located in the file). + + + **Windows Users:** Please check that you have correctly installed USB + driver from board manufacturer + + + +Boards +------ + +.. note:: + * You can list pre-configured boards by :ref:`cmd_boards` command or + `PlatformIO Boards Explorer `_ + * For more detailed ``board`` information please scroll tables below by + horizontal. + +BQ +~~ + +.. list-table:: + :header-rows: 1 + + * - Type ``board`` + - Name + - Microcontroller + - Frequency + - Flash + - RAM + + * - ``icezum`` + - `BQ IceZUM Alhambra FPGA `_ + - ICE40HX1K + - 12 MHz + - 32 Kb + - 32 Kb + +Lattice +~~~~~~~ + +.. list-table:: + :header-rows: 1 + + * - Type ``board`` + - Name + - Microcontroller + - Frequency + - Flash + - RAM + + * - ``icestick`` + - `Lattice iCEstick FPGA Evaluation Kit `_ + - ICE40HX1K + - 12 MHz + - 32 Kb + - 32 Kb diff --git a/examples b/examples index 0a360867..24c2dfba 160000 --- a/examples +++ b/examples @@ -1 +1 @@ -Subproject commit 0a3608679446a75be4df10d454686618a33ed9f5 +Subproject commit 24c2dfbaa848e26dae81e1666382b1b26d766089 diff --git a/platformio/boards/lattice.json b/platformio/boards/lattice.json new file mode 100755 index 00000000..ce31a2e4 --- /dev/null +++ b/platformio/boards/lattice.json @@ -0,0 +1,45 @@ +{ + "icestick": { + "build": { + "core": "icestick", + "f_cpu": "12000000L", + "cpu": "fpga", + "mcu": "ice40hx1k", + "variant": "1k", + "hwid": [ + ["0x0403", "0x6010"] + ] + }, + "frameworks": ["icestorm"], + "name": "Lattice iCEstick FPGA Evaluation Kit", + "platform": "lattice_ice40", + "upload": { + "maximum_ram_size": 32768, + "maximum_size": 32768 + }, + "url": "http://www.latticesemi.com/icestick", + "vendor": "Lattice" + }, + + "icezum": { + "build": { + "core": "icezum", + "f_cpu": "12000000L", + "cpu": "fpga", + "mcu": "ice40hx1k", + "variant": "1k", + "hwid": [ + ["0x0403", "0x6010"] + ] + }, + "frameworks": ["icestorm"], + "name": "BQ IceZUM Alhambra FPGA", + "platform": "lattice_ice40", + "upload": { + "maximum_ram_size": 32768, + "maximum_size": 32768 + }, + "url": "https://github.com/bqlabs/icezum/wiki", + "vendor": "BQ" + } +} diff --git a/platformio/builder/scripts/lattice_ice40.py b/platformio/builder/scripts/lattice_ice40.py new file mode 100755 index 00000000..d57d58a3 --- /dev/null +++ b/platformio/builder/scripts/lattice_ice40.py @@ -0,0 +1,149 @@ +""" + Build script for lattice ice40 FPGAs + latticeice40-builder.py +""" +import os +from os.path import join + +from SCons.Script import (COMMAND_LINE_TARGETS, AlwaysBuild, Builder, Default, + DefaultEnvironment, Environment, Exit, GetOption, + Glob) + +env = DefaultEnvironment() +env.Replace(PROGNAME="hardware") +env.Append(SIMULNAME="simulation") + +# -- Get the local folder in which the icestorm tools should be installed +piopackages_dir = env.subst('$PIOPACKAGES_DIR') +bin_dir = join(piopackages_dir, 'toolchain-icestorm', 'bin') + +# -- Add this path to the PATH env variable. First the building tools will be +# -- searched in the local PATH. If they are not founde, the global ones will +# -- be executed (if installed) +env.PrependENVPath('PATH', bin_dir) + +# -- Target name for synthesis +TARGET = join(env['BUILD_DIR'], env['PROGNAME']) + +# -- Target name for simulation +# TARGET_SIM = join(env['PROJECT_DIR'], env['SIMULNAME']) + +# -- Get a list of all the verilog files in the src folfer, in ASCII, with +# -- the full path. All these files are used for the simulation +v_nodes = Glob(join(env['PROJECTSRC_DIR'], '*.v')) +src_sim = ["{}".format(f) for f in v_nodes] + +# --------- Get the Testbench file (there should be only 1) +# -- Create a list with all the files finished in _tb.v. It should contain +# -- the test bench +list_tb = [f for f in src_sim if f[-5:].upper() == "_TB.V"] + +if len(list_tb) > 1: + print "---> WARNING: More than one testbenches used" + +# -- Error checking +try: + testbench = list_tb[0] + +# -- there is no testbench +except IndexError: + testbench = None + +if 'sim' in COMMAND_LINE_TARGETS: + if testbench is None: + print "ERROR!!! NO testbench found for simulation" + Exit(1) + + # -- Simulation name + testbench_file = os.path.split(testbench)[-1] + SIMULNAME, ext = os.path.splitext(testbench_file) +else: + SIMULNAME = '' + + +TARGET_SIM = join(env.subst('$BUILD_DIR'), SIMULNAME) + +# -------- Get the synthesis files. They are ALL the files except the +# -------- testbench +src_synth = [f for f in src_sim if f not in list_tb] + +# -- For debugging +print "Testbench: {}".format(testbench) + +# -- Get the PCF file +src_dir = env.subst('$PROJECTSRC_DIR') +PCFs = join(src_dir, '*.pcf') +PCF_list = Glob(PCFs) + +try: + PCF = PCF_list[0] +except IndexError: + print "\n--------> ERROR: no .pcf file found <----------\n" + Exit(2) + +# -- Debug +print "----> PCF Found: {}".format(PCF) + +# -- Builder 1 (.v --> .blif) +synth = Builder(action='yosys -p \"synth_ice40 -blif {}.blif\" \ + $SOURCES'.format(TARGET), + suffix='.blif', + src_suffix='.v') + +# -- Builder 2 (.blif --> .asc) +pnr = Builder(action='arachne-pnr -d 1k -o $TARGET -p {} \ + $SOURCE'.format(PCF), + suffix='.asc', + src_suffix='.blif') + +# -- Builder 3 (.asc --> .bin) +bitstream = Builder(action='icepack $SOURCE $TARGET', + suffix='.bin', + src_suffix='.asc') + +# -- Builder 4 (.asc --> .rpt) +time_rpt = Builder(action='icetime -mtr $TARGET $SOURCE', + suffix='.rpt', + src_suffix='.asc') + +env.Append(BUILDERS={'Synth': synth, 'PnR': pnr, 'Bin': bitstream, + 'Time': time_rpt}) + +blif = env.Synth(TARGET, [src_synth]) +asc = env.PnR(TARGET, [blif, PCF]) +binf = env.Bin(TARGET, asc) + +upload = env.Alias('upload', binf, 'iceprog ' + ' $SOURCE') +AlwaysBuild(upload) + +# -- Target for calculating the time (.rpt) +# rpt = env.Time(asc) +t = env.Alias('time', env.Time('time.rpt', asc)) + +# -------------------- Simulation ------------------ +# -- Constructor para generar simulacion: icarus Verilog +iverilog = Builder(action='iverilog -o $TARGET $SOURCES ', + suffix='.out', + src_suffix='.v') + +vcd = Builder(action=' $SOURCE', + suffix='.vcd', src_suffix='.out') + +simenv = Environment(BUILDERS={'IVerilog': iverilog, 'VCD': vcd}, + ENV=os.environ) + +out = simenv.IVerilog(TARGET_SIM, src_sim) +vcd_file = simenv.VCD(SIMULNAME, out) + +waves = simenv.Alias('sim', vcd_file, 'gtkwave ' + + join(env['PROJECT_DIR'], "{} ".format(vcd_file[0])) + + join(env['PROJECTSRC_DIR'], SIMULNAME) + + '.gtkw') +AlwaysBuild(waves) + +Default([binf]) + +# -- These is for cleaning the files generated using the alias targets +if GetOption('clean'): + env.Default([t]) + simenv.Default([out, vcd_file]) diff --git a/platformio/platforms/base.py b/platformio/platforms/base.py index 734d4660..e9498f8e 100644 --- a/platformio/platforms/base.py +++ b/platformio/platforms/base.py @@ -117,6 +117,9 @@ PLATFORM_PACKAGES = { ("msp-gcc", "http://sourceforge.net/projects/mspgcc/"), ("GDB", "http://www.gnu.org/software/gdb/") ], + "toolchain-icestorm": [ + ("GCC for FPGA IceStorm", "http://www.clifford.at/icestorm/") + ], "tool-scons": [ ("SCons software construction tool", "http://www.scons.org") ], diff --git a/platformio/platforms/lattice_ice40.py b/platformio/platforms/lattice_ice40.py new file mode 100755 index 00000000..1791a51c --- /dev/null +++ b/platformio/platforms/lattice_ice40.py @@ -0,0 +1,40 @@ +# Copyright 2014-2016 Ivan Kravets +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from platformio.platforms.base import BasePlatform + + +class Lattice_ice40Platform(BasePlatform): + + """ + The iCE40 family of ultra-low power, non-volatile FPGAs has five devices + with densities ranging from 384 to 7680 Look-Up Tables (LUTs). In addition + to LUT-based,low-cost programmable logic, these devices feature Embedded + Block RAM (EBR), Non-volatile Configuration Memory (NVCM) and Phase Locked + Loops (PLLs). These features allow the devices to be used in low-cost, + high-volume consumer and system applications. + + http://www.latticesemi.com/Products/FPGAandCPLD/iCE40.aspx + """ + + PACKAGES = { + + "toolchain-icestorm": { + "alias": "toolchain", + "default": True + } + } + + def is_embedded(self): + return True