forked from platformio/platformio-core
Fix latice_ice40 dev platform for Python 2.6 // Issue #480
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@ -31,7 +31,7 @@ TARGET = join(env['BUILD_DIR'], env['PROGNAME'])
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# -- Get a list of all the verilog files in the src folfer, in ASCII, with
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# -- Get a list of all the verilog files in the src folfer, in ASCII, with
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# -- the full path. All these files are used for the simulation
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# -- the full path. All these files are used for the simulation
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v_nodes = Glob(join(env['PROJECTSRC_DIR'], '*.v'))
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v_nodes = Glob(join(env['PROJECTSRC_DIR'], '*.v'))
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src_sim = ["{}".format(f) for f in v_nodes]
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src_sim = [str(f) for f in v_nodes]
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# --------- Get the Testbench file (there should be only 1)
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# --------- Get the Testbench file (there should be only 1)
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# -- Create a list with all the files finished in _tb.v. It should contain
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# -- Create a list with all the files finished in _tb.v. It should contain
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@ -68,7 +68,7 @@ TARGET_SIM = join(env.subst('$BUILD_DIR'), SIMULNAME)
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src_synth = [f for f in src_sim if f not in list_tb]
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src_synth = [f for f in src_sim if f not in list_tb]
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# -- For debugging
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# -- For debugging
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print "Testbench: {}".format(testbench)
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print "Testbench: %s" % testbench
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# -- Get the PCF file
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# -- Get the PCF file
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src_dir = env.subst('$PROJECTSRC_DIR')
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src_dir = env.subst('$PROJECTSRC_DIR')
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@ -82,17 +82,17 @@ except IndexError:
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Exit(2)
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Exit(2)
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# -- Debug
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# -- Debug
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print "----> PCF Found: {}".format(PCF)
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print "----> PCF Found: %s" % PCF
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# -- Builder 1 (.v --> .blif)
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# -- Builder 1 (.v --> .blif)
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synth = Builder(action='yosys -p \"synth_ice40 -blif {}.blif\" \
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synth = Builder(action='yosys -p \"synth_ice40 -blif %s.blif\" \
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$SOURCES'.format(TARGET),
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$SOURCES' % TARGET,
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suffix='.blif',
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suffix='.blif',
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src_suffix='.v')
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src_suffix='.v')
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# -- Builder 2 (.blif --> .asc)
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# -- Builder 2 (.blif --> .asc)
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pnr = Builder(action='arachne-pnr -d 1k -o $TARGET -p {} \
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pnr = Builder(action='arachne-pnr -d 1k -o $TARGET -p %s \
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$SOURCE'.format(PCF),
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$SOURCE' % PCF,
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suffix='.asc',
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suffix='.asc',
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src_suffix='.blif')
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src_suffix='.blif')
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@ -136,7 +136,7 @@ out = simenv.IVerilog(TARGET_SIM, src_sim)
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vcd_file = simenv.VCD(SIMULNAME, out)
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vcd_file = simenv.VCD(SIMULNAME, out)
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waves = simenv.Alias('sim', vcd_file, 'gtkwave ' +
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waves = simenv.Alias('sim', vcd_file, 'gtkwave ' +
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join(env['PROJECT_DIR'], "{} ".format(vcd_file[0])) +
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join(env['PROJECT_DIR'], "%s " % vcd_file[0]) +
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join(env['PROJECTSRC_DIR'], SIMULNAME) +
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join(env['PROJECTSRC_DIR'], SIMULNAME) +
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'.gtkw')
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'.gtkw')
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AlwaysBuild(waves)
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AlwaysBuild(waves)
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