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wolfssl/IDE/XilinxSDK/combine.sh

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Integrate Xilinx Versal * add Versal specific glue The same structure of an "XSecure client" is used throughout the API's, therefor define it once and re-use in all clients. * integrate Versal AES-GCM engine * integrate Versal SHA3-384 engine * add versal support to tests - There's no intermediate-hash API for Versal. * add specific test with large AAD Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the hardware engine. * add specific test with misaligned AES-GCM arguments * integrate Versal RSA engine * disable failing RSA test-case when Xilinx Crypto is enabled * introduce define `WOLFSSL_XILINX_CRYPT_VERSAL` * integrate Versal TRNG engine * allow using Versal TRNG w/o wolfcrypt DRBG Versal TRNG already provides a HRNG mode which does the same as the wolfcrypt DRBG implementation. * add support for user-supplied nonce to Versal TRNG * add `wc_XsecureErrorToString()` to map PLM error codes to messages. * integrate Versal EcDSA engine * update tests to work with Versal EcDSA If deterministic K is enabled, the tests failed here since the Versal EcDSA engine doesn't support the SECP256R1 curve yet. * Xilinx crypto engines like aligned memory very much Make this a default choice, not via the user configuration. * add Xilinx-specific `WOLFSSL_MSG()` equivalent `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for 1 second before printing to stdout, since the PLM maybe prints to same and outputs would be mixed up. This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`. * add option to enable DPA CounterMeasures in AES-GCM crypto engine * add "command mode" to Xilinx bare-metal example * update Xilinx default user settings * add script to execute benchmarks * add scripts to create graphics * add Vitis 2022.1 example projects Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-05-20 14:28:39 +02:00
#!/usr/bin/env bash
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Parametrisation to this script is as follows:
# * none yet
###
# Preamble
###
my_path="$(dirname $(readlink -f $0))" || exit $?
readonly my_path
Integrate Xilinx Versal * add Versal specific glue The same structure of an "XSecure client" is used throughout the API's, therefor define it once and re-use in all clients. * integrate Versal AES-GCM engine * integrate Versal SHA3-384 engine * add versal support to tests - There's no intermediate-hash API for Versal. * add specific test with large AAD Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the hardware engine. * add specific test with misaligned AES-GCM arguments * integrate Versal RSA engine * disable failing RSA test-case when Xilinx Crypto is enabled * introduce define `WOLFSSL_XILINX_CRYPT_VERSAL` * integrate Versal TRNG engine * allow using Versal TRNG w/o wolfcrypt DRBG Versal TRNG already provides a HRNG mode which does the same as the wolfcrypt DRBG implementation. * add support for user-supplied nonce to Versal TRNG * add `wc_XsecureErrorToString()` to map PLM error codes to messages. * integrate Versal EcDSA engine * update tests to work with Versal EcDSA If deterministic K is enabled, the tests failed here since the Versal EcDSA engine doesn't support the SECP256R1 curve yet. * Xilinx crypto engines like aligned memory very much Make this a default choice, not via the user configuration. * add Xilinx-specific `WOLFSSL_MSG()` equivalent `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for 1 second before printing to stdout, since the PLM maybe prints to same and outputs would be mixed up. This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`. * add option to enable DPA CounterMeasures in AES-GCM crypto engine * add "command mode" to Xilinx bare-metal example * update Xilinx default user settings * add script to execute benchmarks * add scripts to create graphics * add Vitis 2022.1 example projects Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-05-20 14:28:39 +02:00
readonly csv_path="$my_path/data"
function cleanup() {
echo OK
}
trap cleanup EXIT
function error_out() {
exit 1
}
trap error_out INT TERM
###
# Functions
###
###
# Implementation
###
configs=$(find $csv_path -maxdepth 1 -type d -name '*results_*' | sed 's@.*results_@@g') || exit $?
readonly configs
Integrate Xilinx Versal * add Versal specific glue The same structure of an "XSecure client" is used throughout the API's, therefor define it once and re-use in all clients. * integrate Versal AES-GCM engine * integrate Versal SHA3-384 engine * add versal support to tests - There's no intermediate-hash API for Versal. * add specific test with large AAD Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the hardware engine. * add specific test with misaligned AES-GCM arguments * integrate Versal RSA engine * disable failing RSA test-case when Xilinx Crypto is enabled * introduce define `WOLFSSL_XILINX_CRYPT_VERSAL` * integrate Versal TRNG engine * allow using Versal TRNG w/o wolfcrypt DRBG Versal TRNG already provides a HRNG mode which does the same as the wolfcrypt DRBG implementation. * add support for user-supplied nonce to Versal TRNG * add `wc_XsecureErrorToString()` to map PLM error codes to messages. * integrate Versal EcDSA engine * update tests to work with Versal EcDSA If deterministic K is enabled, the tests failed here since the Versal EcDSA engine doesn't support the SECP256R1 curve yet. * Xilinx crypto engines like aligned memory very much Make this a default choice, not via the user configuration. * add Xilinx-specific `WOLFSSL_MSG()` equivalent `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for 1 second before printing to stdout, since the PLM maybe prints to same and outputs would be mixed up. This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`. * add option to enable DPA CounterMeasures in AES-GCM crypto engine * add "command mode" to Xilinx bare-metal example * update Xilinx default user settings * add script to execute benchmarks * add scripts to create graphics * add Vitis 2022.1 example projects Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-05-20 14:28:39 +02:00
declare -A algos
algos["asym"]="ecc rsa"
algos["hashes"]="sha2 sha3"
algos["mac"]="cmac"
algos["rng"]="rng"
algos["sym"]="cbc ccm gcm"
declare -A headers
headers["asym"]="config,keysize_2,algorithm,keysize,operation,avg ms,ops/sec,"
headers["hashes"]="config,unused,algorithm,MiB/s,"
headers["mac"]="config,unused,algorithm,keysize,MiB/s,"
headers["rng"]="config,unused,algorithm,MiB/s,"
headers["sym"]="config,chunksize,algorithm,blocksize,direction,AAD,MiB/s,"
# "... now you have two problems"
declare -A filters
filters["ccm"]="-e s/-\(enc\|dec\)-\(no_AAD\|custom\)/,128,\1,\2/g -e s/-\(enc\|dec\),/,128,\1,,/g"
filters["gcm"]="-e /-192-/d -e /GMAC/d -e s/-\(enc\|dec\)-\(no_AAD\|custom\)/,\1,\2/g -e s/-\(enc\|dec\),/,\1,default,/g -e s/\(128\|256\)-GCM/GCM,\1/g"
filters["cbc"]="-e /-192-/d -e s/-\(enc\|dec\),/,\1,,/g -e s/\(128\|256\)-CBC/CBC,\1/g"
filters["cmac"]="-e s/\(128\|256\)-CMAC/CMAC,\1/g"
filters["ecc"]='-e 1!{/SECP384R1\|SECP521R1/!d}'
filters["sha2"]="-e s/SHA-/SHA2-/g"
for t in "${!algos[@]}"
Integrate Xilinx Versal * add Versal specific glue The same structure of an "XSecure client" is used throughout the API's, therefor define it once and re-use in all clients. * integrate Versal AES-GCM engine * integrate Versal SHA3-384 engine * add versal support to tests - There's no intermediate-hash API for Versal. * add specific test with large AAD Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the hardware engine. * add specific test with misaligned AES-GCM arguments * integrate Versal RSA engine * disable failing RSA test-case when Xilinx Crypto is enabled * introduce define `WOLFSSL_XILINX_CRYPT_VERSAL` * integrate Versal TRNG engine * allow using Versal TRNG w/o wolfcrypt DRBG Versal TRNG already provides a HRNG mode which does the same as the wolfcrypt DRBG implementation. * add support for user-supplied nonce to Versal TRNG * add `wc_XsecureErrorToString()` to map PLM error codes to messages. * integrate Versal EcDSA engine * update tests to work with Versal EcDSA If deterministic K is enabled, the tests failed here since the Versal EcDSA engine doesn't support the SECP256R1 curve yet. * Xilinx crypto engines like aligned memory very much Make this a default choice, not via the user configuration. * add Xilinx-specific `WOLFSSL_MSG()` equivalent `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for 1 second before printing to stdout, since the PLM maybe prints to same and outputs would be mixed up. This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`. * add option to enable DPA CounterMeasures in AES-GCM crypto engine * add "command mode" to Xilinx bare-metal example * update Xilinx default user settings * add script to execute benchmarks * add scripts to create graphics * add Vitis 2022.1 example projects Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-05-20 14:28:39 +02:00
do
for algo in ${algos[$t]}
do
outfile="$csv_path/combined_${algo}.csv"
echo ${headers[$t]} > "$outfile"
for cfg in $configs
do
for f in $(find $csv_path/results_${cfg} -name "*${algo}*.csv" | sort -V)
do
sz=$(basename $f | sed -e s/${algo}// -e s/_// -e s/\.csv//)
sz=",$sz"
for l in $(tail -n +2 $f | tr -d ' ')
do
echo "${cfg}${sz},${l}" >> "$outfile"
done
[ "${filters[$algo]}" == "" ] || sed -i "$outfile" ${filters[$algo]}
done
echo $algo $t $cfg
done
done
done