From 0201662094db9f4fbdf67188f37bd95e13031a35 Mon Sep 17 00:00:00 2001 From: David Garske Date: Mon, 27 Mar 2023 11:49:32 -0700 Subject: [PATCH 1/3] Support for STM32H5 --- IDE/STM32Cube/README.md | 5 ++++- IDE/STM32Cube/default_conf.ftl | 6 ++++++ wolfssl/wolfcrypt/port/st/stm32.h | 11 ++++++++--- wolfssl/wolfcrypt/settings.h | 8 ++++++-- 4 files changed, 24 insertions(+), 6 deletions(-) diff --git a/IDE/STM32Cube/README.md b/IDE/STM32Cube/README.md index 010c1546d..3ba49fc9a 100644 --- a/IDE/STM32Cube/README.md +++ b/IDE/STM32Cube/README.md @@ -97,16 +97,19 @@ The section for "Hardware platform" may need to be adjusted depending on your pr * To enable STM32L5 support define `WOLFSSL_STM32L5`. * To enable STM32H7 support define `WOLFSSL_STM32H7`. * To enable STM32WB support define `WOLFSSL_STM32WB`. +* To enable STM32U5 support define `WOLFSSL_STM32U5`. +* To enable STM32H5 support define `WOLFSSL_STM32H5`. To use the STM32 Cube HAL support make sure `WOLFSSL_STM32_CUBEMX` is defined. -The PKA acceleration for ECC is avaialble on some U5, L5 and WB55 chips. +The PKA acceleration for ECC is available on some U5, L5 and WB55 chips. This is enabled with `WOLFSSL_STM32_PKA`. You can see some of the benchmarks [here](STM32_Benchmarks.md). To disable hardware crypto acceleration you can define: * `NO_STM32_HASH` * `NO_STM32_CRYPTO` +* `NO_STM32_RNG` To enable the latest Cube HAL support please define `STM32_HAL_V2`. diff --git a/IDE/STM32Cube/default_conf.ftl b/IDE/STM32Cube/default_conf.ftl index 0b0b85cce..71ba570b2 100644 --- a/IDE/STM32Cube/default_conf.ftl +++ b/IDE/STM32Cube/default_conf.ftl @@ -152,6 +152,12 @@ extern ${variable.value} ${variable.name}; #undef NO_STM32_CRYPTO #define WOLFSSL_STM32_PKA #endif +#elif defined(STM32H563xx) + #define WOLFSSL_STM32H5 + #define HAL_CONSOLE_UART huart3 + #define STM32_HAL_V2 + #undef NO_STM32_HASH + #else #warning Please define a hardware platform! /* This means there is not a pre-defined platform for your board/CPU */ diff --git a/wolfssl/wolfcrypt/port/st/stm32.h b/wolfssl/wolfcrypt/port/st/stm32.h index 182e6e284..68b6ef76a 100644 --- a/wolfssl/wolfcrypt/port/st/stm32.h +++ b/wolfssl/wolfcrypt/port/st/stm32.h @@ -46,8 +46,12 @@ #if !defined(HASH_ALGOMODE_HASH) && defined(HASH_AlgoMode_HASH) #define HASH_ALGOMODE_HASH HASH_AlgoMode_HASH #endif -#if !defined(HASH_DATATYPE_8B) && defined(HASH_DataType_8b) - #define HASH_DATATYPE_8B HASH_DataType_8b +#if !defined(HASH_DATATYPE_8B) + #if defined(HASH_DataType_8b) + #define HASH_DATATYPE_8B HASH_DataType_8b + #elif defined(HASH_BYTE_SWAP) + #define HASH_DATATYPE_8B HASH_BYTE_SWAP + #endif #endif #ifndef HASH_STR_NBW #define HASH_STR_NBW HASH_STR_NBLW @@ -120,7 +124,8 @@ int wc_Stm32_Hash_Final(STM32_HASH_Context* stmCtx, word32 algo, /* Detect newer CubeMX crypto HAL (HAL_CRYP_Encrypt / HAL_CRYP_Decrypt) */ #if !defined(STM32_HAL_V2) && defined(CRYP_AES_GCM) && \ (defined(WOLFSSL_STM32F7) || defined(WOLFSSL_STM32L5) || \ - defined(WOLFSSL_STM32H7) || defined(WOLFSSL_STM32U5)) + defined(WOLFSSL_STM32H7) || defined(WOLFSSL_STM32U5)) || \ + defined(WOLFSSL_STM32H5) #define STM32_HAL_V2 #endif diff --git a/wolfssl/wolfcrypt/settings.h b/wolfssl/wolfcrypt/settings.h index 8b8538b1f..f89b57220 100644 --- a/wolfssl/wolfcrypt/settings.h +++ b/wolfssl/wolfcrypt/settings.h @@ -1368,7 +1368,8 @@ extern void uITRON4_free(void *p) ; defined(WOLFSSL_STM32F7) || defined(WOLFSSL_STM32F1) || \ defined(WOLFSSL_STM32L4) || defined(WOLFSSL_STM32L5) || \ defined(WOLFSSL_STM32WB) || defined(WOLFSSL_STM32H7) || \ - defined(WOLFSSL_STM32G0) || defined(WOLFSSL_STM32U5) + defined(WOLFSSL_STM32G0) || defined(WOLFSSL_STM32U5) || \ + defined(WOLFSSL_STM32H5) #define SIZEOF_LONG_LONG 8 #ifndef CHAR_BIT @@ -1423,6 +1424,8 @@ extern void uITRON4_free(void *p) ; #include "stm32g0xx_hal.h" #elif defined(WOLFSSL_STM32U5) #include "stm32u5xx_hal.h" + #elif defined(WOLFSSL_STM32H5) + #include "stm32h5xx_hal.h" #endif #if defined(WOLFSSL_CUBEMX_USE_LL) && defined(WOLFSSL_STM32L4) #include "stm32l4xx_ll_rng.h" @@ -1474,7 +1477,8 @@ extern void uITRON4_free(void *p) ; #endif /* WOLFSSL_STM32_CUBEMX */ #endif /* WOLFSSL_STM32F2 || WOLFSSL_STM32F4 || WOLFSSL_STM32L4 || WOLFSSL_STM32L5 || WOLFSSL_STM32F7 || WOLFSSL_STMWB || - WOLFSSL_STM32H7 || WOLFSSL_STM32G0 || WOLFSSL_STM32U5 */ + WOLFSSL_STM32H7 || WOLFSSL_STM32G0 || WOLFSSL_STM32U5 || + WOLFSSL_STM32H5 */ #ifdef WOLFSSL_DEOS #include #include From d99514a41c9d9d6183e0ec98f99e7de731dcb645 Mon Sep 17 00:00:00 2001 From: David Garske Date: Mon, 27 Mar 2023 13:39:29 -0700 Subject: [PATCH 2/3] Added benchmarks for STM32H563ZI. --- IDE/STM32Cube/STM32_Benchmarks.md | 50 +++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/IDE/STM32Cube/STM32_Benchmarks.md b/IDE/STM32Cube/STM32_Benchmarks.md index 4c45a45e0..ffb63c0b9 100644 --- a/IDE/STM32Cube/STM32_Benchmarks.md +++ b/IDE/STM32Cube/STM32_Benchmarks.md @@ -7,6 +7,7 @@ * [STM32L562E](#stm32l562e) * [STM32F777](#stm32f777) * [STM32U585](#stm32u585) +* [STM32H563ZI](#stm32h563zi) ## STM32H753ZI @@ -708,3 +709,52 @@ ECDSA [ SECP256R1] 256 verify 4 ops took 1.196 sec, avg 299.000 Benchmark complete Benchmark Test: Return code 0 ``` + +## STM32H563ZI + +Cortex-M33 at 150MHz + +### STM32H563ZI (No STM HW Crypto, SP Math ASM Cortex M) + +``` +------------------------------------------------------------------------------ + wolfSSL version 5.6.0 +------------------------------------------------------------------------------ +Running wolfCrypt Benchmarks... +wolfCrypt Benchmark (block bytes 1024, min 1.0 sec each) +RNG 2 MB took 1.011 seconds, 1.950 MB/s +AES-128-CBC-enc 4 MB took 1.000 seconds, 3.686 MB/s +AES-128-CBC-dec 4 MB took 1.004 seconds, 3.723 MB/s +AES-192-CBC-enc 3 MB took 1.004 seconds, 3.187 MB/s +AES-192-CBC-dec 3 MB took 1.000 seconds, 3.046 MB/s +AES-256-CBC-enc 3 MB took 1.000 seconds, 2.816 MB/s +AES-256-CBC-dec 3 MB took 1.004 seconds, 2.728 MB/s +AES-128-GCM-enc 2 MB took 1.000 seconds, 2.048 MB/s +AES-128-GCM-dec 2 MB took 1.004 seconds, 2.091 MB/s +AES-192-GCM-enc 2 MB took 1.008 seconds, 1.879 MB/s +AES-192-GCM-dec 2 MB took 1.011 seconds, 1.874 MB/s +AES-256-GCM-enc 2 MB took 1.000 seconds, 1.741 MB/s +AES-256-GCM-dec 2 MB took 1.012 seconds, 1.745 MB/s +AES-128-GCM-enc-no_AAD 2 MB took 1.008 seconds, 2.057 MB/s +AES-128-GCM-dec-no_AAD 2 MB took 1.008 seconds, 2.108 MB/s +AES-192-GCM-enc-no_AAD 2 MB took 1.000 seconds, 1.894 MB/s +AES-192-GCM-dec-no_AAD 2 MB took 1.000 seconds, 1.894 MB/s +AES-256-GCM-enc-no_AAD 2 MB took 1.004 seconds, 1.759 MB/s +AES-256-GCM-dec-no_AAD 2 MB took 1.004 seconds, 1.759 MB/s +GMAC Table 4-bit 4 MB took 1.000 seconds, 4.400 MB/s +CHACHA 8 MB took 1.000 seconds, 8.448 MB/s +CHA-POLY 6 MB took 1.000 seconds, 5.683 MB/s +POLY1305 26 MB took 1.000 seconds, 25.574 MB/s +SHA-256 5 MB took 1.004 seconds, 4.972 MB/s +HMAC-SHA256 5 MB took 1.000 seconds, 4.941 MB/s +RSA 2048 public 122 ops took 1.000 sec, avg 8.197 ms, 122.000 ops/sec +RSA 2048 private 4 ops took 1.231 sec, avg 307.750 ms, 3.249 ops/sec +DH 2048 key gen 7 ops took 1.000 sec, avg 142.857 ms, 7.000 ops/sec +DH 2048 agree 8 ops took 1.141 sec, avg 142.625 ms, 7.011 ops/sec +ECC [ SECP256R1] 256 key gen 204 ops took 1.000 sec, avg 4.902 ms, 204.000 ops/sec +ECDHE [ SECP256R1] 256 agree 94 ops took 1.007 sec, avg 10.713 ms, 93.347 ops/sec +ECDSA [ SECP256R1] 256 sign 136 ops took 1.012 sec, avg 7.441 ms, 134.387 ops/sec +ECDSA [ SECP256R1] 256 verify 66 ops took 1.012 sec, avg 15.333 ms, 65.217 ops/sec +Benchmark complete +Benchmark Test: Return code 0 +``` From c7a76365f0db746bed381e8c072b38ca7b883a25 Mon Sep 17 00:00:00 2001 From: David Garske Date: Tue, 28 Mar 2023 16:15:47 -0700 Subject: [PATCH 3/3] Fixes to support larger H5 save/restore and larger digest result (for SHA2-512). --- wolfcrypt/src/port/st/stm32.c | 32 ++++++++++++++++++------------- wolfssl/wolfcrypt/port/st/stm32.h | 11 ++++++++--- 2 files changed, 27 insertions(+), 16 deletions(-) diff --git a/wolfcrypt/src/port/st/stm32.c b/wolfcrypt/src/port/st/stm32.c index 39b4417b3..3da7d90ee 100644 --- a/wolfcrypt/src/port/st/stm32.c +++ b/wolfcrypt/src/port/st/stm32.c @@ -164,22 +164,25 @@ static void wc_Stm32_Hash_RestoreContext(STM32_HASH_Context* ctx, int algo) static void wc_Stm32_Hash_GetDigest(byte* hash, int digestSize) { word32 digest[HASH_MAX_DIGEST/sizeof(word32)]; + int i = 0, sz; - /* get digest result */ - digest[0] = HASH->HR[0]; - digest[1] = HASH->HR[1]; - digest[2] = HASH->HR[2]; - digest[3] = HASH->HR[3]; - if (digestSize >= 20) { - digest[4] = HASH->HR[4]; + if (digestSize > HASH_MAX_DIGEST) + digestSize = HASH_MAX_DIGEST; + + sz = digestSize; + while (sz > 0) { + /* first 20 bytes come from instance HR */ + if (i < 5) { + digest[i] = HASH->HR[i]; + } #ifdef HASH_DIGEST - if (digestSize >= 28) { - digest[5] = HASH_DIGEST->HR[5]; - digest[6] = HASH_DIGEST->HR[6]; - if (digestSize == 32) - digest[7] = HASH_DIGEST->HR[7]; + /* reset comes from HASH_DIGEST */ + else { + digest[i] = HASH_DIGEST->HR[i]; } #endif + i++; + sz -= 4; } ByteReverseWords(digest, digest, digestSize); @@ -202,11 +205,14 @@ static int wc_Stm32_Hash_WaitDone(STM32_HASH_Context* stmCtx) int timeout = 0; (void)stmCtx; - /* wait until hash digest is complete */ + /* wait until not busy and hash digest / input block are complete */ while ((HASH->SR & HASH_SR_BUSY) && #ifdef HASH_IMR_DCIE (HASH->SR & HASH_SR_DCIS) == 0 && #endif + #ifdef HASH_IMR_DINIE + (HASH->SR & HASH_SR_DINIS) == 0 && + #endif ++timeout < STM32_HASH_TIMEOUT) { }; diff --git a/wolfssl/wolfcrypt/port/st/stm32.h b/wolfssl/wolfcrypt/port/st/stm32.h index 68b6ef76a..570a79e85 100644 --- a/wolfssl/wolfcrypt/port/st/stm32.h +++ b/wolfssl/wolfcrypt/port/st/stm32.h @@ -35,10 +35,15 @@ #ifdef HASH_DIGEST /* The HASH_DIGEST register indicates SHA224/SHA256 support */ #define STM32_HASH_SHA2 - #define HASH_CR_SIZE 54 - #define HASH_MAX_DIGEST 32 + #if defined(WOLFSSL_STM32H5) + #define HASH_CR_SIZE 103 + #define HASH_MAX_DIGEST 64 /* Up to SHA512 */ + #else + #define HASH_CR_SIZE 54 + #define HASH_MAX_DIGEST 32 + #endif #else - #define HASH_CR_SIZE 50 + #define HASH_CR_SIZE 50 #define HASH_MAX_DIGEST 20 #endif