From 591101fd8bbb2aea70bf3bba8f5711665111c315 Mon Sep 17 00:00:00 2001
From: Sean Parkinson <sean@wolfssl.com>
Date: Wed, 5 Oct 2022 16:33:52 +1000
Subject: [PATCH] AES for ARM32 without using crypto hardware instructions

AES-ECB, AES-CBC, AES-CTR, AES-GCM, AES-CCM
Fix ldrd and strd to use even first first register and have
second register be next after first.
---
 configure.ac                                  |     7 +
 src/include.am                                |    14 +-
 wolfcrypt/src/aes.c                           |     8 +-
 wolfcrypt/src/port/arm/armv8-32-aes-asm.S     |  3594 ++++
 wolfcrypt/src/port/arm/armv8-32-curve25519.S  |  6245 +++----
 .../src/port/arm/armv8-32-curve25519_c.c      |  5147 +++---
 wolfcrypt/src/port/arm/armv8-32-sha256-asm.S  |  2770 ++--
 .../src/port/arm/armv8-32-sha256-asm_c.c      |  2738 ++--
 wolfcrypt/src/port/arm/armv8-32-sha512-asm.S  | 13464 +++++++--------
 .../src/port/arm/armv8-32-sha512-asm_c.c      | 13578 ++++++++--------
 wolfcrypt/src/port/arm/armv8-aes.c            |   847 +-
 wolfcrypt/src/port/arm/armv8-chacha.c         |    17 +-
 12 files changed, 26445 insertions(+), 21984 deletions(-)
 create mode 100644 wolfcrypt/src/port/arm/armv8-32-aes-asm.S

diff --git a/configure.ac b/configure.ac
index ab9572e5b..a31621be0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1994,6 +1994,7 @@ AC_ARG_ENABLE([aescbc],
 if test "$ENABLED_AESCBC" = "no"
 then
     AM_CFLAGS="$AM_CFLAGS -DNO_AES_CBC"
+    AM_CCASFLAGS="$AM_CCASFLAGS -DHAVE_AES_CBC"
 fi
 
 # AES-CBC length checks (checks that input lengths are multiples of block size)
@@ -2045,6 +2046,7 @@ AC_ARG_ENABLE([aesccm],
 if test "$ENABLED_AESCCM" = "yes" || test "$ENABLED_WOLFENGINE" = "yes"
 then
     AM_CFLAGS="$AM_CFLAGS -DHAVE_AESCCM"
+    AM_CCASFLAGS="$AM_CCASFLAGS -DHAVE_AESCCM"
 fi
 
 # AES-SIV (RFC 5297)
@@ -4173,6 +4175,8 @@ AS_CASE([$FIPS_VERSION],
 
         AS_IF([test "$ENABLED_AESGCM" = "no" && (test "$FIPS_VERSION" != "dev" || test "$enable_aesgcm" != "no")],
             [ENABLED_AESGCM="yes"; AM_CFLAGS="$AM_CFLAGS -DHAVE_AESGCM"])
+        AS_IF([test "$ENABLED_AESGCM" = "no" && (test "$FIPS_VERSION" != "dev" || test "$enable_aesgcm" != "no")],
+            [ENABLED_AESGCM="yes"; AM_CCASFLAGS="$AM_CCASFLAGS -DHAVE_AESGCM"])
 
         # Old TLS requires MD5 + HMAC, which is not allowed under FIPS 140-3
         AS_IF([test "$ENABLED_OLD_TLS" != "no"],
@@ -4226,6 +4230,9 @@ AS_CASE([$FIPS_VERSION],
         AS_IF([test "x$ENABLED_AESCTR" != "xyes"],
               [ENABLED_AESCTR="yes"
                AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_AES_COUNTER"])
+        AS_IF([test "x$ENABLED_AESCTR" != "xyes"],
+              [ENABLED_AESCTR="yes"
+               AM_CCASFLAGS="$AM_CCASFLAGS -DWOLFSSL_AES_COUNTER"])
         AS_IF([test "x$ENABLED_CMAC" != "xyes"],
               [ENABLED_CMAC="yes"
                AM_CFLAGS="$AM_CFLAGS -DWOLFSSL_CMAC"])
diff --git a/src/include.am b/src/include.am
index 807f43e41..41630f36a 100644
--- a/src/include.am
+++ b/src/include.am
@@ -203,8 +203,11 @@ endif
 
 if BUILD_AES
 src_libwolfssl_la_SOURCES += wolfcrypt/src/aes.c
-if BUILD_ARMASM_CRYPTO
+if BUILD_ARMASM
 src_libwolfssl_la_SOURCES += wolfcrypt/src/port/arm/armv8-aes.c
+if !BUILD_ARMASM_CRYPTO
+src_libwolfssl_la_SOURCES += wolfcrypt/src/port/arm/armv8-32-aes-asm.S
+endif
 endif
 endif
 
@@ -409,13 +412,16 @@ endif
 if !BUILD_FIPS_CURRENT
 if BUILD_AES
 src_libwolfssl_la_SOURCES += wolfcrypt/src/aes.c
-if BUILD_ARMASM_CRYPTO
+if BUILD_ARMASM
 src_libwolfssl_la_SOURCES += wolfcrypt/src/port/arm/armv8-aes.c
-endif
+if !BUILD_ARMASM_CRYPTO
+src_libwolfssl_la_SOURCES += wolfcrypt/src/port/arm/armv8-32-aes-asm.S
+endif !BUILD_ARMASM_CRYPTO
+endif BUILD_ARMASM
 if BUILD_AFALG
 src_libwolfssl_la_SOURCES += wolfcrypt/src/port/af_alg/afalg_aes.c
 endif
-endif
+endif BUILD_AES
 endif !BUILD_FIPS_CURRENT
 
 if !BUILD_FIPS_CURRENT
diff --git a/wolfcrypt/src/aes.c b/wolfcrypt/src/aes.c
index a4ab8c1e0..f31a4a9ec 100644
--- a/wolfcrypt/src/aes.c
+++ b/wolfcrypt/src/aes.c
@@ -306,7 +306,7 @@ block cipher mechanism that uses n-bit binary string parameter key with 128-bits
     #include <wolfcrypt/src/misc.c>
 #endif
 
-#if !defined(WOLFSSL_ARMASM) || defined(WOLFSSL_ARMASM_NO_HW_CRYPTO)
+#ifndef WOLFSSL_ARMASM
 
 #ifdef WOLFSSL_IMX6_CAAM_BLOB
     /* case of possibly not using hardware acceleration for AES but using key
@@ -4224,7 +4224,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
 
         return 0;
     }
-    #endif
+    #endif /* HAVE_AES_DECRYPT */
 
 #endif /* AES-CBC block */
 #endif /* HAVE_AES_CBC */
@@ -4601,7 +4601,7 @@ static WC_INLINE void IncCtr(byte* ctr, word32 ctrSz)
 
 #endif
 
-#if defined(WOLFSSL_ARMASM) && !defined(WOLFSSL_ARMASM_NO_HW_CRYPTO)
+#ifdef WOLFSSL_ARMASM
     /* implementation is located in wolfcrypt/src/port/arm/armv8-aes.c */
 
 #elif defined(WOLFSSL_AFALG)
@@ -9931,7 +9931,7 @@ int wc_AesCcmCheckTagSize(int sz)
     return 0;
 }
 
-#if defined(WOLFSSL_ARMASM) && !defined(WOLFSSL_ARMASM_NO_HW_CRYPTO)
+#ifdef WOLFSSL_ARMASM
     /* implementation located in wolfcrypt/src/port/arm/armv8-aes.c */
 
 #elif defined(HAVE_COLDFIRE_SEC)
diff --git a/wolfcrypt/src/port/arm/armv8-32-aes-asm.S b/wolfcrypt/src/port/arm/armv8-32-aes-asm.S
new file mode 100644
index 000000000..4ff995faa
--- /dev/null
+++ b/wolfcrypt/src/port/arm/armv8-32-aes-asm.S
@@ -0,0 +1,3594 @@
+/* armv8-32-aes-asm
+ *
+ * Copyright (C) 2006-2022 wolfSSL Inc.
+ *
+ * This file is part of wolfSSL.
+ *
+ * wolfSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+/* Generated using (from wolfssl):
+ *   cd ../scripts
+ *   ruby ./aes/aes.rb arm32 ../wolfssl/wolfcrypt/src/port/arm/armv8-32-aes-asm.S
+ */
+
+#include <wolfssl/wolfcrypt/settings.h>
+
+#ifdef WOLFSSL_ARMASM
+#ifndef __aarch64__
+	.text
+	.type	L_AES_ARM32_te, %object
+	.size	L_AES_ARM32_te, 1024
+	.align	4
+L_AES_ARM32_te:
+	.word	0xa5c66363
+	.word	0x84f87c7c
+	.word	0x99ee7777
+	.word	0x8df67b7b
+	.word	0xdfff2f2
+	.word	0xbdd66b6b
+	.word	0xb1de6f6f
+	.word	0x5491c5c5
+	.word	0x50603030
+	.word	0x3020101
+	.word	0xa9ce6767
+	.word	0x7d562b2b
+	.word	0x19e7fefe
+	.word	0x62b5d7d7
+	.word	0xe64dabab
+	.word	0x9aec7676
+	.word	0x458fcaca
+	.word	0x9d1f8282
+	.word	0x4089c9c9
+	.word	0x87fa7d7d
+	.word	0x15effafa
+	.word	0xebb25959
+	.word	0xc98e4747
+	.word	0xbfbf0f0
+	.word	0xec41adad
+	.word	0x67b3d4d4
+	.word	0xfd5fa2a2
+	.word	0xea45afaf
+	.word	0xbf239c9c
+	.word	0xf753a4a4
+	.word	0x96e47272
+	.word	0x5b9bc0c0
+	.word	0xc275b7b7
+	.word	0x1ce1fdfd
+	.word	0xae3d9393
+	.word	0x6a4c2626
+	.word	0x5a6c3636
+	.word	0x417e3f3f
+	.word	0x2f5f7f7
+	.word	0x4f83cccc
+	.word	0x5c683434
+	.word	0xf451a5a5
+	.word	0x34d1e5e5
+	.word	0x8f9f1f1
+	.word	0x93e27171
+	.word	0x73abd8d8
+	.word	0x53623131
+	.word	0x3f2a1515
+	.word	0xc080404
+	.word	0x5295c7c7
+	.word	0x65462323
+	.word	0x5e9dc3c3
+	.word	0x28301818
+	.word	0xa1379696
+	.word	0xf0a0505
+	.word	0xb52f9a9a
+	.word	0x90e0707
+	.word	0x36241212
+	.word	0x9b1b8080
+	.word	0x3ddfe2e2
+	.word	0x26cdebeb
+	.word	0x694e2727
+	.word	0xcd7fb2b2
+	.word	0x9fea7575
+	.word	0x1b120909
+	.word	0x9e1d8383
+	.word	0x74582c2c
+	.word	0x2e341a1a
+	.word	0x2d361b1b
+	.word	0xb2dc6e6e
+	.word	0xeeb45a5a
+	.word	0xfb5ba0a0
+	.word	0xf6a45252
+	.word	0x4d763b3b
+	.word	0x61b7d6d6
+	.word	0xce7db3b3
+	.word	0x7b522929
+	.word	0x3edde3e3
+	.word	0x715e2f2f
+	.word	0x97138484
+	.word	0xf5a65353
+	.word	0x68b9d1d1
+	.word	0x0
+	.word	0x2cc1eded
+	.word	0x60402020
+	.word	0x1fe3fcfc
+	.word	0xc879b1b1
+	.word	0xedb65b5b
+	.word	0xbed46a6a
+	.word	0x468dcbcb
+	.word	0xd967bebe
+	.word	0x4b723939
+	.word	0xde944a4a
+	.word	0xd4984c4c
+	.word	0xe8b05858
+	.word	0x4a85cfcf
+	.word	0x6bbbd0d0
+	.word	0x2ac5efef
+	.word	0xe54faaaa
+	.word	0x16edfbfb
+	.word	0xc5864343
+	.word	0xd79a4d4d
+	.word	0x55663333
+	.word	0x94118585
+	.word	0xcf8a4545
+	.word	0x10e9f9f9
+	.word	0x6040202
+	.word	0x81fe7f7f
+	.word	0xf0a05050
+	.word	0x44783c3c
+	.word	0xba259f9f
+	.word	0xe34ba8a8
+	.word	0xf3a25151
+	.word	0xfe5da3a3
+	.word	0xc0804040
+	.word	0x8a058f8f
+	.word	0xad3f9292
+	.word	0xbc219d9d
+	.word	0x48703838
+	.word	0x4f1f5f5
+	.word	0xdf63bcbc
+	.word	0xc177b6b6
+	.word	0x75afdada
+	.word	0x63422121
+	.word	0x30201010
+	.word	0x1ae5ffff
+	.word	0xefdf3f3
+	.word	0x6dbfd2d2
+	.word	0x4c81cdcd
+	.word	0x14180c0c
+	.word	0x35261313
+	.word	0x2fc3ecec
+	.word	0xe1be5f5f
+	.word	0xa2359797
+	.word	0xcc884444
+	.word	0x392e1717
+	.word	0x5793c4c4
+	.word	0xf255a7a7
+	.word	0x82fc7e7e
+	.word	0x477a3d3d
+	.word	0xacc86464
+	.word	0xe7ba5d5d
+	.word	0x2b321919
+	.word	0x95e67373
+	.word	0xa0c06060
+	.word	0x98198181
+	.word	0xd19e4f4f
+	.word	0x7fa3dcdc
+	.word	0x66442222
+	.word	0x7e542a2a
+	.word	0xab3b9090
+	.word	0x830b8888
+	.word	0xca8c4646
+	.word	0x29c7eeee
+	.word	0xd36bb8b8
+	.word	0x3c281414
+	.word	0x79a7dede
+	.word	0xe2bc5e5e
+	.word	0x1d160b0b
+	.word	0x76addbdb
+	.word	0x3bdbe0e0
+	.word	0x56643232
+	.word	0x4e743a3a
+	.word	0x1e140a0a
+	.word	0xdb924949
+	.word	0xa0c0606
+	.word	0x6c482424
+	.word	0xe4b85c5c
+	.word	0x5d9fc2c2
+	.word	0x6ebdd3d3
+	.word	0xef43acac
+	.word	0xa6c46262
+	.word	0xa8399191
+	.word	0xa4319595
+	.word	0x37d3e4e4
+	.word	0x8bf27979
+	.word	0x32d5e7e7
+	.word	0x438bc8c8
+	.word	0x596e3737
+	.word	0xb7da6d6d
+	.word	0x8c018d8d
+	.word	0x64b1d5d5
+	.word	0xd29c4e4e
+	.word	0xe049a9a9
+	.word	0xb4d86c6c
+	.word	0xfaac5656
+	.word	0x7f3f4f4
+	.word	0x25cfeaea
+	.word	0xafca6565
+	.word	0x8ef47a7a
+	.word	0xe947aeae
+	.word	0x18100808
+	.word	0xd56fbaba
+	.word	0x88f07878
+	.word	0x6f4a2525
+	.word	0x725c2e2e
+	.word	0x24381c1c
+	.word	0xf157a6a6
+	.word	0xc773b4b4
+	.word	0x5197c6c6
+	.word	0x23cbe8e8
+	.word	0x7ca1dddd
+	.word	0x9ce87474
+	.word	0x213e1f1f
+	.word	0xdd964b4b
+	.word	0xdc61bdbd
+	.word	0x860d8b8b
+	.word	0x850f8a8a
+	.word	0x90e07070
+	.word	0x427c3e3e
+	.word	0xc471b5b5
+	.word	0xaacc6666
+	.word	0xd8904848
+	.word	0x5060303
+	.word	0x1f7f6f6
+	.word	0x121c0e0e
+	.word	0xa3c26161
+	.word	0x5f6a3535
+	.word	0xf9ae5757
+	.word	0xd069b9b9
+	.word	0x91178686
+	.word	0x5899c1c1
+	.word	0x273a1d1d
+	.word	0xb9279e9e
+	.word	0x38d9e1e1
+	.word	0x13ebf8f8
+	.word	0xb32b9898
+	.word	0x33221111
+	.word	0xbbd26969
+	.word	0x70a9d9d9
+	.word	0x89078e8e
+	.word	0xa7339494
+	.word	0xb62d9b9b
+	.word	0x223c1e1e
+	.word	0x92158787
+	.word	0x20c9e9e9
+	.word	0x4987cece
+	.word	0xffaa5555
+	.word	0x78502828
+	.word	0x7aa5dfdf
+	.word	0x8f038c8c
+	.word	0xf859a1a1
+	.word	0x80098989
+	.word	0x171a0d0d
+	.word	0xda65bfbf
+	.word	0x31d7e6e6
+	.word	0xc6844242
+	.word	0xb8d06868
+	.word	0xc3824141
+	.word	0xb0299999
+	.word	0x775a2d2d
+	.word	0x111e0f0f
+	.word	0xcb7bb0b0
+	.word	0xfca85454
+	.word	0xd66dbbbb
+	.word	0x3a2c1616
+	.text
+	.type	L_AES_ARM32_td, %object
+	.size	L_AES_ARM32_td, 1024
+	.align	4
+L_AES_ARM32_td:
+	.word	0x5051f4a7
+	.word	0x537e4165
+	.word	0xc31a17a4
+	.word	0x963a275e
+	.word	0xcb3bab6b
+	.word	0xf11f9d45
+	.word	0xabacfa58
+	.word	0x934be303
+	.word	0x552030fa
+	.word	0xf6ad766d
+	.word	0x9188cc76
+	.word	0x25f5024c
+	.word	0xfc4fe5d7
+	.word	0xd7c52acb
+	.word	0x80263544
+	.word	0x8fb562a3
+	.word	0x49deb15a
+	.word	0x6725ba1b
+	.word	0x9845ea0e
+	.word	0xe15dfec0
+	.word	0x2c32f75
+	.word	0x12814cf0
+	.word	0xa38d4697
+	.word	0xc66bd3f9
+	.word	0xe7038f5f
+	.word	0x9515929c
+	.word	0xebbf6d7a
+	.word	0xda955259
+	.word	0x2dd4be83
+	.word	0xd3587421
+	.word	0x2949e069
+	.word	0x448ec9c8
+	.word	0x6a75c289
+	.word	0x78f48e79
+	.word	0x6b99583e
+	.word	0xdd27b971
+	.word	0xb6bee14f
+	.word	0x17f088ad
+	.word	0x66c920ac
+	.word	0xb47dce3a
+	.word	0x1863df4a
+	.word	0x82e51a31
+	.word	0x60975133
+	.word	0x4562537f
+	.word	0xe0b16477
+	.word	0x84bb6bae
+	.word	0x1cfe81a0
+	.word	0x94f9082b
+	.word	0x58704868
+	.word	0x198f45fd
+	.word	0x8794de6c
+	.word	0xb7527bf8
+	.word	0x23ab73d3
+	.word	0xe2724b02
+	.word	0x57e31f8f
+	.word	0x2a6655ab
+	.word	0x7b2eb28
+	.word	0x32fb5c2
+	.word	0x9a86c57b
+	.word	0xa5d33708
+	.word	0xf2302887
+	.word	0xb223bfa5
+	.word	0xba02036a
+	.word	0x5ced1682
+	.word	0x2b8acf1c
+	.word	0x92a779b4
+	.word	0xf0f307f2
+	.word	0xa14e69e2
+	.word	0xcd65daf4
+	.word	0xd50605be
+	.word	0x1fd13462
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+	.word	0xa0a2f355
+	.word	0x32058ae1
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+	.word	0xb591548d
+	.word	0x571c45d
+	.word	0x6f0406d4
+	.word	0xff605015
+	.word	0x241998fb
+	.word	0x97d6bde9
+	.word	0xcc894043
+	.word	0x7767d99e
+	.word	0xbdb0e842
+	.word	0x8807898b
+	.word	0x38e7195b
+	.word	0xdb79c8ee
+	.word	0x47a17c0a
+	.word	0xe97c420f
+	.word	0xc9f8841e
+	.word	0x0
+	.word	0x83098086
+	.word	0x48322bed
+	.word	0xac1e1170
+	.word	0x4e6c5a72
+	.word	0xfbfd0eff
+	.word	0x560f8538
+	.word	0x1e3daed5
+	.word	0x27362d39
+	.word	0x640a0fd9
+	.word	0x21685ca6
+	.word	0xd19b5b54
+	.word	0x3a24362e
+	.word	0xb10c0a67
+	.word	0xf9357e7
+	.word	0xd2b4ee96
+	.word	0x9e1b9b91
+	.word	0x4f80c0c5
+	.word	0xa261dc20
+	.word	0x695a774b
+	.word	0x161c121a
+	.word	0xae293ba
+	.word	0xe5c0a02a
+	.word	0x433c22e0
+	.word	0x1d121b17
+	.word	0xb0e090d
+	.word	0xadf28bc7
+	.word	0xb92db6a8
+	.word	0xc8141ea9
+	.word	0x8557f119
+	.word	0x4caf7507
+	.word	0xbbee99dd
+	.word	0xfda37f60
+	.word	0x9ff70126
+	.word	0xbc5c72f5
+	.word	0xc544663b
+	.word	0x345bfb7e
+	.word	0x768b4329
+	.word	0xdccb23c6
+	.word	0x68b6edfc
+	.word	0x63b8e4f1
+	.word	0xcad731dc
+	.word	0x10426385
+	.word	0x40139722
+	.word	0x2084c611
+	.word	0x7d854a24
+	.word	0xf8d2bb3d
+	.word	0x11aef932
+	.word	0x6dc729a1
+	.word	0x4b1d9e2f
+	.word	0xf3dcb230
+	.word	0xec0d8652
+	.word	0xd077c1e3
+	.word	0x6c2bb316
+	.word	0x99a970b9
+	.word	0xfa119448
+	.word	0x2247e964
+	.word	0xc4a8fc8c
+	.word	0x1aa0f03f
+	.word	0xd8567d2c
+	.word	0xef223390
+	.word	0xc787494e
+	.word	0xc1d938d1
+	.word	0xfe8ccaa2
+	.word	0x3698d40b
+	.word	0xcfa6f581
+	.word	0x28a57ade
+	.word	0x26dab78e
+	.word	0xa43fadbf
+	.word	0xe42c3a9d
+	.word	0xd507892
+	.word	0x9b6a5fcc
+	.word	0x62547e46
+	.word	0xc2f68d13
+	.word	0xe890d8b8
+	.word	0x5e2e39f7
+	.word	0xf582c3af
+	.word	0xbe9f5d80
+	.word	0x7c69d093
+	.word	0xa96fd52d
+	.word	0xb3cf2512
+	.word	0x3bc8ac99
+	.word	0xa710187d
+	.word	0x6ee89c63
+	.word	0x7bdb3bbb
+	.word	0x9cd2678
+	.word	0xf46e5918
+	.word	0x1ec9ab7
+	.word	0xa8834f9a
+	.word	0x65e6956e
+	.word	0x7eaaffe6
+	.word	0x821bccf
+	.word	0xe6ef15e8
+	.word	0xd9bae79b
+	.word	0xce4a6f36
+	.word	0xd4ea9f09
+	.word	0xd629b07c
+	.word	0xaf31a4b2
+	.word	0x312a3f23
+	.word	0x30c6a594
+	.word	0xc035a266
+	.word	0x37744ebc
+	.word	0xa6fc82ca
+	.word	0xb0e090d0
+	.word	0x1533a7d8
+	.word	0x4af10498
+	.word	0xf741ecda
+	.word	0xe7fcd50
+	.word	0x2f1791f6
+	.word	0x8d764dd6
+	.word	0x4d43efb0
+	.word	0x54ccaa4d
+	.word	0xdfe49604
+	.word	0xe39ed1b5
+	.word	0x1b4c6a88
+	.word	0xb8c12c1f
+	.word	0x7f466551
+	.word	0x49d5eea
+	.word	0x5d018c35
+	.word	0x73fa8774
+	.word	0x2efb0b41
+	.word	0x5ab3671d
+	.word	0x5292dbd2
+	.word	0x33e91056
+	.word	0x136dd647
+	.word	0x8c9ad761
+	.word	0x7a37a10c
+	.word	0x8e59f814
+	.word	0x89eb133c
+	.word	0xeecea927
+	.word	0x35b761c9
+	.word	0xede11ce5
+	.word	0x3c7a47b1
+	.word	0x599cd2df
+	.word	0x3f55f273
+	.word	0x791814ce
+	.word	0xbf73c737
+	.word	0xea53f7cd
+	.word	0x5b5ffdaa
+	.word	0x14df3d6f
+	.word	0x867844db
+	.word	0x81caaff3
+	.word	0x3eb968c4
+	.word	0x2c382434
+	.word	0x5fc2a340
+	.word	0x72161dc3
+	.word	0xcbce225
+	.word	0x8b283c49
+	.word	0x41ff0d95
+	.word	0x7139a801
+	.word	0xde080cb3
+	.word	0x9cd8b4e4
+	.word	0x906456c1
+	.word	0x617bcb84
+	.word	0x70d532b6
+	.word	0x74486c5c
+	.word	0x42d0b857
+	.text
+	.type	L_AES_ARM32_td4, %object
+	.size	L_AES_ARM32_td4, 256
+	.align	4
+L_AES_ARM32_td4:
+	.byte	0x52
+	.byte	0x9
+	.byte	0x6a
+	.byte	0xd5
+	.byte	0x30
+	.byte	0x36
+	.byte	0xa5
+	.byte	0x38
+	.byte	0xbf
+	.byte	0x40
+	.byte	0xa3
+	.byte	0x9e
+	.byte	0x81
+	.byte	0xf3
+	.byte	0xd7
+	.byte	0xfb
+	.byte	0x7c
+	.byte	0xe3
+	.byte	0x39
+	.byte	0x82
+	.byte	0x9b
+	.byte	0x2f
+	.byte	0xff
+	.byte	0x87
+	.byte	0x34
+	.byte	0x8e
+	.byte	0x43
+	.byte	0x44
+	.byte	0xc4
+	.byte	0xde
+	.byte	0xe9
+	.byte	0xcb
+	.byte	0x54
+	.byte	0x7b
+	.byte	0x94
+	.byte	0x32
+	.byte	0xa6
+	.byte	0xc2
+	.byte	0x23
+	.byte	0x3d
+	.byte	0xee
+	.byte	0x4c
+	.byte	0x95
+	.byte	0xb
+	.byte	0x42
+	.byte	0xfa
+	.byte	0xc3
+	.byte	0x4e
+	.byte	0x8
+	.byte	0x2e
+	.byte	0xa1
+	.byte	0x66
+	.byte	0x28
+	.byte	0xd9
+	.byte	0x24
+	.byte	0xb2
+	.byte	0x76
+	.byte	0x5b
+	.byte	0xa2
+	.byte	0x49
+	.byte	0x6d
+	.byte	0x8b
+	.byte	0xd1
+	.byte	0x25
+	.byte	0x72
+	.byte	0xf8
+	.byte	0xf6
+	.byte	0x64
+	.byte	0x86
+	.byte	0x68
+	.byte	0x98
+	.byte	0x16
+	.byte	0xd4
+	.byte	0xa4
+	.byte	0x5c
+	.byte	0xcc
+	.byte	0x5d
+	.byte	0x65
+	.byte	0xb6
+	.byte	0x92
+	.byte	0x6c
+	.byte	0x70
+	.byte	0x48
+	.byte	0x50
+	.byte	0xfd
+	.byte	0xed
+	.byte	0xb9
+	.byte	0xda
+	.byte	0x5e
+	.byte	0x15
+	.byte	0x46
+	.byte	0x57
+	.byte	0xa7
+	.byte	0x8d
+	.byte	0x9d
+	.byte	0x84
+	.byte	0x90
+	.byte	0xd8
+	.byte	0xab
+	.byte	0x0
+	.byte	0x8c
+	.byte	0xbc
+	.byte	0xd3
+	.byte	0xa
+	.byte	0xf7
+	.byte	0xe4
+	.byte	0x58
+	.byte	0x5
+	.byte	0xb8
+	.byte	0xb3
+	.byte	0x45
+	.byte	0x6
+	.byte	0xd0
+	.byte	0x2c
+	.byte	0x1e
+	.byte	0x8f
+	.byte	0xca
+	.byte	0x3f
+	.byte	0xf
+	.byte	0x2
+	.byte	0xc1
+	.byte	0xaf
+	.byte	0xbd
+	.byte	0x3
+	.byte	0x1
+	.byte	0x13
+	.byte	0x8a
+	.byte	0x6b
+	.byte	0x3a
+	.byte	0x91
+	.byte	0x11
+	.byte	0x41
+	.byte	0x4f
+	.byte	0x67
+	.byte	0xdc
+	.byte	0xea
+	.byte	0x97
+	.byte	0xf2
+	.byte	0xcf
+	.byte	0xce
+	.byte	0xf0
+	.byte	0xb4
+	.byte	0xe6
+	.byte	0x73
+	.byte	0x96
+	.byte	0xac
+	.byte	0x74
+	.byte	0x22
+	.byte	0xe7
+	.byte	0xad
+	.byte	0x35
+	.byte	0x85
+	.byte	0xe2
+	.byte	0xf9
+	.byte	0x37
+	.byte	0xe8
+	.byte	0x1c
+	.byte	0x75
+	.byte	0xdf
+	.byte	0x6e
+	.byte	0x47
+	.byte	0xf1
+	.byte	0x1a
+	.byte	0x71
+	.byte	0x1d
+	.byte	0x29
+	.byte	0xc5
+	.byte	0x89
+	.byte	0x6f
+	.byte	0xb7
+	.byte	0x62
+	.byte	0xe
+	.byte	0xaa
+	.byte	0x18
+	.byte	0xbe
+	.byte	0x1b
+	.byte	0xfc
+	.byte	0x56
+	.byte	0x3e
+	.byte	0x4b
+	.byte	0xc6
+	.byte	0xd2
+	.byte	0x79
+	.byte	0x20
+	.byte	0x9a
+	.byte	0xdb
+	.byte	0xc0
+	.byte	0xfe
+	.byte	0x78
+	.byte	0xcd
+	.byte	0x5a
+	.byte	0xf4
+	.byte	0x1f
+	.byte	0xdd
+	.byte	0xa8
+	.byte	0x33
+	.byte	0x88
+	.byte	0x7
+	.byte	0xc7
+	.byte	0x31
+	.byte	0xb1
+	.byte	0x12
+	.byte	0x10
+	.byte	0x59
+	.byte	0x27
+	.byte	0x80
+	.byte	0xec
+	.byte	0x5f
+	.byte	0x60
+	.byte	0x51
+	.byte	0x7f
+	.byte	0xa9
+	.byte	0x19
+	.byte	0xb5
+	.byte	0x4a
+	.byte	0xd
+	.byte	0x2d
+	.byte	0xe5
+	.byte	0x7a
+	.byte	0x9f
+	.byte	0x93
+	.byte	0xc9
+	.byte	0x9c
+	.byte	0xef
+	.byte	0xa0
+	.byte	0xe0
+	.byte	0x3b
+	.byte	0x4d
+	.byte	0xae
+	.byte	0x2a
+	.byte	0xf5
+	.byte	0xb0
+	.byte	0xc8
+	.byte	0xeb
+	.byte	0xbb
+	.byte	0x3c
+	.byte	0x83
+	.byte	0x53
+	.byte	0x99
+	.byte	0x61
+	.byte	0x17
+	.byte	0x2b
+	.byte	0x4
+	.byte	0x7e
+	.byte	0xba
+	.byte	0x77
+	.byte	0xd6
+	.byte	0x26
+	.byte	0xe1
+	.byte	0x69
+	.byte	0x14
+	.byte	0x63
+	.byte	0x55
+	.byte	0x21
+	.byte	0xc
+	.byte	0x7d
+#ifndef NO_AES
+	.text
+	.type	L_AES_SEK_ARM32_tep, %object
+	.size	L_AES_SEK_ARM32_tep, 4
+	.align	4
+L_AES_SEK_ARM32_tep:
+	.word	L_AES_ARM32_te
+	.text
+	.type	L_AES_SEK_ARM32_rcon, %object
+	.size	L_AES_SEK_ARM32_rcon, 40
+	.align	4
+L_AES_SEK_ARM32_rcon:
+	.word	0x1000000
+	.word	0x2000000
+	.word	0x4000000
+	.word	0x8000000
+	.word	0x10000000
+	.word	0x20000000
+	.word	0x40000000
+	.word	0x80000000
+	.word	0x1b000000
+	.word	0x36000000
+	.text
+	.align	4
+	.globl	AES_set_encrypt_key
+	.type	AES_set_encrypt_key, %function
+AES_set_encrypt_key:
+	push	{r4, r5, r6, r7, r8, lr}
+	adr	lr, L_AES_SEK_ARM32_rcon
+	ldr	r8, L_AES_SEK_ARM32_tep
+	cmp	r1, #0x80
+	beq	L_AES_set_encrypt_key_start_128
+	cmp	r1, #0xc0
+	beq	L_AES_set_encrypt_key_start_192
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	r2!, {r4, r5, r6, r7}
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	r2, {r4, r5, r6, r7}
+	sub	r2, r2, #16
+	mov	r12, #6
+L_AES_set_encrypt_key_loop_256:
+	mov	r3, r7
+	mov	r7, #0xff
+	and	r5, r7, r3, lsr #8
+	and	r4, r7, r3
+	and	r6, r7, r3, lsr #16
+	lsr	r3, r3, #24
+	ldrb	r4, [r8, r4, lsl #2]
+	ldrb	r6, [r8, r6, lsl #2]
+	ldrb	r5, [r8, r5, lsl #2]
+	ldrb	r3, [r8, r3, lsl #2]
+	eor	r3, r3, r4, lsl #8
+	eor	r3, r3, r5, lsl #16
+	eor	r3, r3, r6, lsl #24
+	ldm	r2!, {r4, r5, r6, r7}
+	eor	r4, r4, r3
+	ldm	lr!, {r3}
+	eor	r4, r4, r3
+	eor	r5, r5, r4
+	eor	r6, r6, r5
+	eor	r7, r7, r6
+	add	r2, r2, #16
+	stm	r2, {r4, r5, r6, r7}
+	sub	r2, r2, #16
+	mov	r3, r7
+	mov	r7, #0xff
+	and	r4, r7, r3, lsr #8
+	and	r5, r7, r3, lsr #16
+	lsr	r6, r3, #24
+	and	r3, r7, r3
+	ldrb	r4, [r8, r4, lsl #2]
+	ldrb	r6, [r8, r6, lsl #2]
+	ldrb	r5, [r8, r5, lsl #2]
+	ldrb	r3, [r8, r3, lsl #2]
+	eor	r3, r3, r4, lsl #8
+	eor	r3, r3, r5, lsl #16
+	eor	r3, r3, r6, lsl #24
+	ldm	r2!, {r4, r5, r6, r7}
+	eor	r4, r4, r3
+	eor	r5, r5, r4
+	eor	r6, r6, r5
+	eor	r7, r7, r6
+	add	r2, r2, #16
+	stm	r2, {r4, r5, r6, r7}
+	sub	r2, r2, #16
+	subs	r12, r12, #1
+	bne	L_AES_set_encrypt_key_loop_256
+	mov	r3, r7
+	mov	r7, #0xff
+	and	r5, r7, r3, lsr #8
+	and	r4, r7, r3
+	and	r6, r7, r3, lsr #16
+	lsr	r3, r3, #24
+	ldrb	r4, [r8, r4, lsl #2]
+	ldrb	r6, [r8, r6, lsl #2]
+	ldrb	r5, [r8, r5, lsl #2]
+	ldrb	r3, [r8, r3, lsl #2]
+	eor	r3, r3, r4, lsl #8
+	eor	r3, r3, r5, lsl #16
+	eor	r3, r3, r6, lsl #24
+	ldm	r2!, {r4, r5, r6, r7}
+	eor	r4, r4, r3
+	ldm	lr!, {r3}
+	eor	r4, r4, r3
+	eor	r5, r5, r4
+	eor	r6, r6, r5
+	eor	r7, r7, r6
+	add	r2, r2, #16
+	stm	r2, {r4, r5, r6, r7}
+	sub	r2, r2, #16
+	b	L_AES_set_encrypt_key_end
+L_AES_set_encrypt_key_start_192:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r0, [r0, #16]
+	ldr	r1, [r0, #20]
+#else
+	ldrd	r0, r1, [r0, #16]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	rev	r0, r0
+	rev	r1, r1
+	stm	r2, {r4, r5, r6, r7}
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r0, [r2, #16]
+	str	r1, [r2, #20]
+#else
+	strd	r0, r1, [r2, #16]
+#endif
+	mov	r7, r1
+	mov	r12, #7
+L_AES_set_encrypt_key_loop_192:
+	mov	r3, r7
+	mov	r5, #0xff
+	and	r1, r5, r3, lsr #8
+	and	r0, r5, r3
+	and	r4, r5, r3, lsr #16
+	lsr	r3, r3, #24
+	ldrb	r0, [r8, r0, lsl #2]
+	ldrb	r4, [r8, r4, lsl #2]
+	ldrb	r1, [r8, r1, lsl #2]
+	ldrb	r3, [r8, r3, lsl #2]
+	eor	r3, r3, r0, lsl #8
+	eor	r3, r3, r1, lsl #16
+	eor	r3, r3, r4, lsl #24
+	ldm	r2!, {r0, r1, r4, r5, r6, r7}
+	eor	r0, r0, r3
+	ldm	lr!, {r3}
+	eor	r0, r0, r3
+	eor	r1, r1, r0
+	eor	r4, r4, r1
+	eor	r5, r5, r4
+	eor	r6, r6, r5
+	eor	r7, r7, r6
+	stm	r2, {r0, r1, r4, r5, r6, r7}
+	subs	r12, r12, #1
+	bne	L_AES_set_encrypt_key_loop_192
+	mov	r3, r7
+	mov	r5, #0xff
+	and	r1, r5, r3, lsr #8
+	and	r0, r5, r3
+	and	r4, r5, r3, lsr #16
+	lsr	r3, r3, #24
+	ldrb	r0, [r8, r0, lsl #2]
+	ldrb	r4, [r8, r4, lsl #2]
+	ldrb	r1, [r8, r1, lsl #2]
+	ldrb	r3, [r8, r3, lsl #2]
+	eor	r3, r3, r0, lsl #8
+	eor	r3, r3, r1, lsl #16
+	eor	r3, r3, r4, lsl #24
+	ldm	r2!, {r0, r1, r4, r5, r6, r7}
+	eor	r0, r0, r3
+	ldm	lr!, {r3}
+	eor	r0, r0, r3
+	eor	r1, r1, r0
+	eor	r4, r4, r1
+	eor	r5, r5, r4
+	stm	r2, {r0, r1, r4, r5}
+	b	L_AES_set_encrypt_key_end
+L_AES_set_encrypt_key_start_128:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	r2, {r4, r5, r6, r7}
+	mov	r12, #10
+L_AES_set_encrypt_key_loop_128:
+	mov	r3, r7
+	mov	r7, #0xff
+	and	r5, r7, r3, lsr #8
+	and	r4, r7, r3
+	and	r6, r7, r3, lsr #16
+	lsr	r3, r3, #24
+	ldrb	r4, [r8, r4, lsl #2]
+	ldrb	r6, [r8, r6, lsl #2]
+	ldrb	r5, [r8, r5, lsl #2]
+	ldrb	r3, [r8, r3, lsl #2]
+	eor	r3, r3, r4, lsl #8
+	eor	r3, r3, r5, lsl #16
+	eor	r3, r3, r6, lsl #24
+	ldm	r2!, {r4, r5, r6, r7}
+	eor	r4, r4, r3
+	ldm	lr!, {r3}
+	eor	r4, r4, r3
+	eor	r5, r5, r4
+	eor	r6, r6, r5
+	eor	r7, r7, r6
+	stm	r2, {r4, r5, r6, r7}
+	subs	r12, r12, #1
+	bne	L_AES_set_encrypt_key_loop_128
+L_AES_set_encrypt_key_end:
+	pop	{r4, r5, r6, r7, r8, pc}
+	.size	AES_set_encrypt_key,.-AES_set_encrypt_key
+#ifdef HAVE_AES_DECRYPT
+	.text
+	.type	L_AES_IK_ARM32_tep, %object
+	.size	L_AES_IK_ARM32_tep, 4
+	.align	4
+L_AES_IK_ARM32_tep:
+	.word	L_AES_ARM32_te
+	.text
+	.type	L_AES_IK_ARM32_rcon, %object
+	.size	L_AES_IK_ARM32_rcon, 4
+	.align	4
+L_AES_IK_ARM32_rcon:
+	.word	L_AES_ARM32_td
+	.text
+	.align	4
+	.globl	AES_invert_key
+	.type	AES_invert_key, %function
+AES_invert_key:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r9, L_AES_IK_ARM32_tep
+	ldr	r10, L_AES_IK_ARM32_rcon
+	add	r8, r0, r1, lsl #4
+	mov	r11, r1
+L_AES_invert_key_loop:
+	ldm	r0, {r2, r3, r12, lr}
+	ldm	r8, {r4, r5, r6, r7}
+	stm	r8, {r2, r3, r12, lr}
+	stm	r0!, {r4, r5, r6, r7}
+	subs	r11, r11, #2
+	sub	r8, r8, #16
+	bne	L_AES_invert_key_loop
+	sub	r0, r0, r1, lsl #3
+	add	r0, r0, #16
+	sub	r11, r1, #1
+	mov	r1, #0xff
+L_AES_invert_key_mix_loop:
+	ldm	r0, {r2, r3, r12, lr}
+	lsr	r4, r2, #24
+	and	r7, r1, r2
+	and	r8, r1, r2, lsr #16
+	and	r6, r1, r2, lsr #8
+	ldrb	r4, [r9, r4, lsl #2]
+	ldrb	r7, [r9, r7, lsl #2]
+	ldrb	r8, [r9, r8, lsl #2]
+	ldrb	r6, [r9, r6, lsl #2]
+	ldr	r4, [r10, r4, lsl #2]
+	ldr	r7, [r10, r7, lsl #2]
+	ldr	r8, [r10, r8, lsl #2]
+	ldr	r6, [r10, r6, lsl #2]
+	eor	r8, r8, r4, ror #24
+	eor	r8, r8, r7, ror #16
+	eor	r8, r8, r6, ror #8
+	str	r8, [r0], #4
+	lsr	r4, r3, #24
+	and	r7, r1, r3
+	and	r8, r1, r3, lsr #16
+	and	r6, r1, r3, lsr #8
+	ldrb	r4, [r9, r4, lsl #2]
+	ldrb	r7, [r9, r7, lsl #2]
+	ldrb	r8, [r9, r8, lsl #2]
+	ldrb	r6, [r9, r6, lsl #2]
+	ldr	r4, [r10, r4, lsl #2]
+	ldr	r7, [r10, r7, lsl #2]
+	ldr	r8, [r10, r8, lsl #2]
+	ldr	r6, [r10, r6, lsl #2]
+	eor	r8, r8, r4, ror #24
+	eor	r8, r8, r7, ror #16
+	eor	r8, r8, r6, ror #8
+	str	r8, [r0], #4
+	lsr	r4, r12, #24
+	and	r7, r1, r12
+	and	r8, r1, r12, lsr #16
+	and	r6, r1, r12, lsr #8
+	ldrb	r4, [r9, r4, lsl #2]
+	ldrb	r7, [r9, r7, lsl #2]
+	ldrb	r8, [r9, r8, lsl #2]
+	ldrb	r6, [r9, r6, lsl #2]
+	ldr	r4, [r10, r4, lsl #2]
+	ldr	r7, [r10, r7, lsl #2]
+	ldr	r8, [r10, r8, lsl #2]
+	ldr	r6, [r10, r6, lsl #2]
+	eor	r8, r8, r4, ror #24
+	eor	r8, r8, r7, ror #16
+	eor	r8, r8, r6, ror #8
+	str	r8, [r0], #4
+	lsr	r4, lr, #24
+	and	r7, r1, lr
+	and	r8, r1, lr, lsr #16
+	and	r6, r1, lr, lsr #8
+	ldrb	r4, [r9, r4, lsl #2]
+	ldrb	r7, [r9, r7, lsl #2]
+	ldrb	r8, [r9, r8, lsl #2]
+	ldrb	r6, [r9, r6, lsl #2]
+	ldr	r4, [r10, r4, lsl #2]
+	ldr	r7, [r10, r7, lsl #2]
+	ldr	r8, [r10, r8, lsl #2]
+	ldr	r6, [r10, r6, lsl #2]
+	eor	r8, r8, r4, ror #24
+	eor	r8, r8, r7, ror #16
+	eor	r8, r8, r6, ror #8
+	str	r8, [r0], #4
+	subs	r11, r11, #1
+	bne	L_AES_invert_key_mix_loop
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_invert_key,.-AES_invert_key
+#endif /* HAVE_AES_DECRYPT */
+#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
+	.text
+	.align	4
+	.globl	AES_encrypt_block
+	.type	AES_encrypt_block, %function
+AES_encrypt_block:
+L_AES_encrypt_block_14:
+	push	{r2, lr}
+	ldr	lr, [sp, #12]
+	mov	r2, #6
+	b	L_AES_encrypt_block_nr
+L_AES_encrypt_block_12:
+	push	{r2, lr}
+	ldr	lr, [sp, #12]
+	mov	r2, #5
+	b	L_AES_encrypt_block_nr
+L_AES_encrypt_block_10:
+	push	{r2, lr}
+	ldr	lr, [sp, #12]
+	mov	r2, #4
+L_AES_encrypt_block_nr:
+	lsr	r11, r4, #24
+	and	r1, r12, r7
+	and	r8, r12, r5, lsr #16
+	and	r0, r12, r6, lsr #8
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	ldr	r8, [lr, r8, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	and	r9, r12, r6, lsr #16
+	eor	r8, r8, r11, ror #24
+	lsr	r11, r5, #24
+	eor	r8, r8, r0, ror #8
+	and	r0, r12, r7, lsr #8
+	eor	r8, r8, r1, ror #16
+	and	r1, r12, r4
+	ldr	r9, [lr, r9, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r10, r12, r7, lsr #16
+	eor	r9, r9, r11, ror #24
+	lsr	r11, r6, #24
+	eor	r9, r9, r0, ror #8
+	and	r0, r12, r4, lsr #8
+	eor	r9, r9, r1, ror #16
+	and	r1, r12, r5
+	ldr	r10, [lr, r10, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r6, r12, r6
+	eor	r10, r10, r11, ror #24
+	and	r11, r12, r4, lsr #16
+	eor	r10, r10, r0, ror #8
+	lsr	r0, r7, #24
+	eor	r10, r10, r1, ror #16
+	and	r1, r12, r5, lsr #8
+	ldr	r6, [lr, r6, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r6, ror #24
+	ldm	r3!, {r4, r5, r6, r7}
+	eor	r11, r11, r0, ror #24
+	eor	r11, r11, r1, ror #8
+	#   XOR in Key Schedule
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r7, r8, #24
+	and	r1, r12, r11
+	and	r4, r12, r9, lsr #16
+	and	r0, r12, r10, lsr #8
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	ldr	r4, [lr, r4, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	and	r5, r12, r10, lsr #16
+	eor	r4, r4, r7, ror #24
+	lsr	r7, r9, #24
+	eor	r4, r4, r0, ror #8
+	and	r0, r12, r11, lsr #8
+	eor	r4, r4, r1, ror #16
+	and	r1, r12, r8
+	ldr	r5, [lr, r5, lsl #2]
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r6, r12, r11, lsr #16
+	eor	r5, r5, r7, ror #24
+	lsr	r7, r10, #24
+	eor	r5, r5, r0, ror #8
+	and	r0, r12, r8, lsr #8
+	eor	r5, r5, r1, ror #16
+	and	r1, r12, r9
+	ldr	r6, [lr, r6, lsl #2]
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r10, r12, r10
+	eor	r6, r6, r7, ror #24
+	and	r7, r12, r8, lsr #16
+	eor	r6, r6, r0, ror #8
+	lsr	r0, r11, #24
+	eor	r6, r6, r1, ror #16
+	and	r1, r12, r9, lsr #8
+	ldr	r10, [lr, r10, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r10, ror #24
+	ldm	r3!, {r8, r9, r10, r11}
+	eor	r7, r7, r0, ror #24
+	eor	r7, r7, r1, ror #8
+	#   XOR in Key Schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	subs	r2, r2, #1
+	bne	L_AES_encrypt_block_nr
+	lsr	r11, r4, #24
+	and	r1, r12, r7
+	and	r8, r12, r5, lsr #16
+	and	r0, r12, r6, lsr #8
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	ldr	r8, [lr, r8, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	and	r9, r12, r6, lsr #16
+	eor	r8, r8, r11, ror #24
+	lsr	r11, r5, #24
+	eor	r8, r8, r0, ror #8
+	and	r0, r12, r7, lsr #8
+	eor	r8, r8, r1, ror #16
+	and	r1, r12, r4
+	ldr	r9, [lr, r9, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r10, r12, r7, lsr #16
+	eor	r9, r9, r11, ror #24
+	lsr	r11, r6, #24
+	eor	r9, r9, r0, ror #8
+	and	r0, r12, r4, lsr #8
+	eor	r9, r9, r1, ror #16
+	and	r1, r12, r5
+	ldr	r10, [lr, r10, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r6, r12, r6
+	eor	r10, r10, r11, ror #24
+	and	r11, r12, r4, lsr #16
+	eor	r10, r10, r0, ror #8
+	lsr	r0, r7, #24
+	eor	r10, r10, r1, ror #16
+	and	r1, r12, r5, lsr #8
+	ldr	r6, [lr, r6, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r6, ror #24
+	ldm	r3!, {r4, r5, r6, r7}
+	eor	r11, r11, r0, ror #24
+	eor	r11, r11, r1, ror #8
+	#   XOR in Key Schedule
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r7, r12, r10, lsr #8
+	lsr	r1, r8, #24
+	and	r4, r12, r11
+	and	r0, r12, r9, lsr #16
+	ldrb	r7, [lr, r7, lsl #2]
+	ldrb	r1, [lr, r1, lsl #2]
+	ldrb	r4, [lr, r4, lsl #2]
+	ldrb	r0, [lr, r0, lsl #2]
+	and	r5, r12, r8
+	eor	r4, r4, r7, lsl #8
+	and	r7, r12, r11, lsr #8
+	eor	r4, r4, r0, lsl #16
+	and	r0, r12, r10, lsr #16
+	eor	r4, r4, r1, lsl #24
+	lsr	r1, r9, #24
+	ldrb	r7, [lr, r7, lsl #2]
+	ldrb	r1, [lr, r1, lsl #2]
+	ldrb	r5, [lr, r5, lsl #2]
+	ldrb	r0, [lr, r0, lsl #2]
+	and	r6, r12, r9
+	eor	r5, r5, r7, lsl #8
+	and	r7, r12, r8, lsr #8
+	eor	r5, r5, r0, lsl #16
+	and	r0, r12, r11, lsr #16
+	eor	r5, r5, r1, lsl #24
+	lsr	r1, r10, #24
+	ldrb	r7, [lr, r7, lsl #2]
+	ldrb	r1, [lr, r1, lsl #2]
+	ldrb	r6, [lr, r6, lsl #2]
+	ldrb	r0, [lr, r0, lsl #2]
+	lsr	r11, r11, #24
+	eor	r6, r6, r7, lsl #8
+	and	r7, r12, r10
+	eor	r6, r6, r0, lsl #16
+	and	r0, r12, r9, lsr #8
+	eor	r6, r6, r1, lsl #24
+	and	r1, r12, r8, lsr #16
+	ldrb	r11, [lr, r11, lsl #2]
+	ldrb	r0, [lr, r0, lsl #2]
+	ldrb	r7, [lr, r7, lsl #2]
+	ldrb	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r11, lsl #16
+	ldm	r3, {r8, r9, r10, r11}
+	eor	r7, r7, r0, lsl #8
+	eor	r7, r7, r1, lsl #16
+	#   XOR in Key Schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	str	lr, [sp, #12]
+	pop	{r2, lr}
+	bx	lr
+	bx	lr
+	.size	AES_encrypt_block,.-AES_encrypt_block
+#if defined(HAVE_AESCCM) || defined(HAVE_AESGCM) || defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
+	.text
+	.type	L_AES_ARM32_tep, %object
+	.size	L_AES_ARM32_tep, 4
+	.align	4
+L_AES_ARM32_tep:
+	.word	L_AES_ARM32_te
+	.text
+	.align	4
+	.globl	AES_ECB_encrypt
+	.type	AES_ECB_encrypt, %function
+AES_ECB_encrypt:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r12, [sp, #36]
+	ldr	lr, L_AES_ARM32_tep
+	cmp	r12, #10
+	beq	L_AES_ECB_encrypt_start_block_128
+	cmp	r12, #12
+	beq	L_AES_ECB_encrypt_start_block_192
+	mov	r12, #0xff
+L_AES_ECB_encrypt_loop_block_256:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	push	{r0, r1}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_ECB_encrypt_loop_block_256
+	b	L_AES_ECB_encrypt_end
+L_AES_ECB_encrypt_start_block_192:
+	mov	r12, #0xff
+L_AES_ECB_encrypt_loop_block_192:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	push	{r0, r1}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_ECB_encrypt_loop_block_192
+	b	L_AES_ECB_encrypt_end
+L_AES_ECB_encrypt_start_block_128:
+	mov	r12, #0xff
+L_AES_ECB_encrypt_loop_block_128:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	push	{r0, r1}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_ECB_encrypt_loop_block_128
+L_AES_ECB_encrypt_end:
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_ECB_encrypt,.-AES_ECB_encrypt
+#endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
+#ifdef HAVE_AES_CBC
+	.text
+	.type	L_AES_CBC_ARM32_tep, %object
+	.size	L_AES_CBC_ARM32_tep, 4
+	.align	4
+L_AES_CBC_ARM32_tep:
+	.word	L_AES_ARM32_te
+	.text
+	.align	4
+	.globl	AES_CBC_encrypt
+	.type	AES_CBC_encrypt, %function
+AES_CBC_encrypt:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r12, [sp, #36]
+	ldr	lr, [sp, #40]
+	ldm	lr, {r4, r5, r6, r7}
+	push	{lr}
+	ldr	lr, L_AES_CBC_ARM32_tep
+	cmp	r12, #10
+	beq	L_AES_CBC_encrypt_start_block_128
+	cmp	r12, #12
+	beq	L_AES_CBC_encrypt_start_block_192
+	mov	r12, #0xff
+L_AES_CBC_encrypt_loop_block_256:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	push	{r0, r1}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CBC_encrypt_loop_block_256
+	b	L_AES_CBC_encrypt_end
+L_AES_CBC_encrypt_start_block_192:
+	mov	r12, #0xff
+L_AES_CBC_encrypt_loop_block_192:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	push	{r0, r1}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CBC_encrypt_loop_block_192
+	b	L_AES_CBC_encrypt_end
+L_AES_CBC_encrypt_start_block_128:
+	mov	r12, #0xff
+L_AES_CBC_encrypt_loop_block_128:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	push	{r0, r1}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CBC_encrypt_loop_block_128
+L_AES_CBC_encrypt_end:
+	pop	{lr}
+	stm	lr, {r4, r5, r6, r7}
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_CBC_encrypt,.-AES_CBC_encrypt
+#endif /* HAVE_AES_CBC */
+#ifdef WOLFSSL_AES_COUNTER
+	.text
+	.type	L_AES_CTR_ARM32_tep, %object
+	.size	L_AES_CTR_ARM32_tep, 4
+	.align	4
+L_AES_CTR_ARM32_tep:
+	.word	L_AES_ARM32_te
+	.text
+	.align	4
+	.globl	AES_CTR_encrypt
+	.type	AES_CTR_encrypt, %function
+AES_CTR_encrypt:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r12, [sp, #36]
+	ldr	lr, [sp, #40]
+	ldm	lr, {r4, r5, r6, r7}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	lr, {r4, r5, r6, r7}
+	push	{lr}
+	ldr	lr, L_AES_CTR_ARM32_tep
+	cmp	r12, #10
+	beq	L_AES_CTR_encrypt_start_block_128
+	cmp	r12, #12
+	beq	L_AES_CTR_encrypt_start_block_192
+	mov	r12, #0xff
+L_AES_CTR_encrypt_loop_block_256:
+	push	{r0, r1}
+	ldr	r0, [sp, #8]
+	adds	r11, r7, #1
+	adcs	r10, r6, #0
+	adcs	r9, r5, #0
+	adc	r8, r4, #0
+	stm	r0, {r8, r9, r10, r11}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r8
+	eor	r5, r9
+	eor	r6, r10
+	eor	r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	ldr	r8, [sp]
+	ldm	r8, {r4, r5, r6, r7}
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CTR_encrypt_loop_block_256
+	b	L_AES_CTR_encrypt_end
+L_AES_CTR_encrypt_start_block_192:
+	mov	r12, #0xff
+L_AES_CTR_encrypt_loop_block_192:
+	push	{r0, r1}
+	ldr	r0, [sp, #8]
+	adds	r11, r7, #1
+	adcs	r10, r6, #0
+	adcs	r9, r5, #0
+	adc	r8, r4, #0
+	stm	r0, {r8, r9, r10, r11}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r8
+	eor	r5, r9
+	eor	r6, r10
+	eor	r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	ldr	r8, [sp]
+	ldm	r8, {r4, r5, r6, r7}
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CTR_encrypt_loop_block_192
+	b	L_AES_CTR_encrypt_end
+L_AES_CTR_encrypt_start_block_128:
+	mov	r12, #0xff
+L_AES_CTR_encrypt_loop_block_128:
+	push	{r0, r1}
+	ldr	r0, [sp, #8]
+	adds	r11, r7, #1
+	adcs	r10, r6, #0
+	adcs	r9, r5, #0
+	adc	r8, r4, #0
+	stm	r0, {r8, r9, r10, r11}
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r8
+	eor	r5, r9
+	eor	r6, r10
+	eor	r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	ldr	r8, [sp]
+	ldm	r8, {r4, r5, r6, r7}
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CTR_encrypt_loop_block_128
+L_AES_CTR_encrypt_end:
+	pop	{lr}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	lr, {r4, r5, r6, r7}
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_CTR_encrypt,.-AES_CTR_encrypt
+#endif /* WOLFSSL_AES_COUNTER */
+#endif /* HAVE_AESCCM || HAVE_AESGCM || WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
+#ifdef HAVE_AES_DECRYPT
+#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER) || defined(HAVE_AES_CBC)
+	.text
+	.type	L_AES_ARM32_td4p, %object
+	.size	L_AES_ARM32_td4p, 4
+	.align	4
+L_AES_ARM32_td4p:
+	.word	L_AES_ARM32_td4
+	.text
+	.align	4
+	.globl	AES_decrypt_block
+	.type	AES_decrypt_block, %function
+AES_decrypt_block:
+L_AES_decrypt_block_14:
+	push	{lr}
+	ldr	lr, [sp, #8]
+	mov	r12, #6
+	b	L_AES_decrypt_block_nr
+L_AES_decrypt_block_12:
+	push	{lr}
+	ldr	lr, [sp, #8]
+	mov	r12, #5
+	b	L_AES_decrypt_block_nr
+L_AES_decrypt_block_10:
+	push	{lr}
+	ldr	lr, [sp, #8]
+	mov	r12, #4
+L_AES_decrypt_block_nr:
+	lsr	r11, r4, #24
+	and	r1, r2, r5
+	and	r8, r2, r7, lsr #16
+	and	r0, r2, r6, lsr #8
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	ldr	r8, [lr, r8, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	and	r9, r2, r4, lsr #16
+	eor	r8, r8, r11, ror #24
+	lsr	r11, r5, #24
+	eor	r8, r8, r0, ror #8
+	and	r0, r2, r7, lsr #8
+	eor	r8, r8, r1, ror #16
+	and	r1, r2, r6
+	ldr	r9, [lr, r9, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r10, r2, r5, lsr #16
+	eor	r9, r9, r11, ror #24
+	lsr	r11, r6, #24
+	eor	r9, r9, r0, ror #8
+	and	r0, r2, r4, lsr #8
+	eor	r9, r9, r1, ror #16
+	and	r1, r2, r7
+	ldr	r10, [lr, r10, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r4, r2, r4
+	eor	r10, r10, r11, ror #24
+	and	r11, r2, r6, lsr #16
+	eor	r10, r10, r0, ror #8
+	lsr	r0, r7, #24
+	eor	r10, r10, r1, ror #16
+	and	r1, r2, r5, lsr #8
+	ldr	r4, [lr, r4, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r4, ror #24
+	ldm	r3!, {r4, r5, r6, r7}
+	eor	r11, r11, r1, ror #8
+	eor	r11, r11, r0, ror #24
+	#   XOR in Key Schedule
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r7, r8, #24
+	and	r1, r2, r9
+	and	r4, r2, r11, lsr #16
+	and	r0, r2, r10, lsr #8
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	ldr	r4, [lr, r4, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	and	r5, r2, r8, lsr #16
+	eor	r4, r4, r7, ror #24
+	lsr	r7, r9, #24
+	eor	r4, r4, r0, ror #8
+	and	r0, r2, r11, lsr #8
+	eor	r4, r4, r1, ror #16
+	and	r1, r2, r10
+	ldr	r5, [lr, r5, lsl #2]
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r6, r2, r9, lsr #16
+	eor	r5, r5, r7, ror #24
+	lsr	r7, r10, #24
+	eor	r5, r5, r0, ror #8
+	and	r0, r2, r8, lsr #8
+	eor	r5, r5, r1, ror #16
+	and	r1, r2, r11
+	ldr	r6, [lr, r6, lsl #2]
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r8, r2, r8
+	eor	r6, r6, r7, ror #24
+	and	r7, r2, r10, lsr #16
+	eor	r6, r6, r0, ror #8
+	lsr	r0, r11, #24
+	eor	r6, r6, r1, ror #16
+	and	r1, r2, r9, lsr #8
+	ldr	r8, [lr, r8, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r7, [lr, r7, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r8, ror #24
+	ldm	r3!, {r8, r9, r10, r11}
+	eor	r7, r7, r1, ror #8
+	eor	r7, r7, r0, ror #24
+	#   XOR in Key Schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	subs	r12, r12, #1
+	bne	L_AES_decrypt_block_nr
+	lsr	r11, r4, #24
+	and	r1, r2, r5
+	and	r8, r2, r7, lsr #16
+	and	r0, r2, r6, lsr #8
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	ldr	r8, [lr, r8, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	and	r9, r2, r4, lsr #16
+	eor	r8, r8, r11, ror #24
+	lsr	r11, r5, #24
+	eor	r8, r8, r0, ror #8
+	and	r0, r2, r7, lsr #8
+	eor	r8, r8, r1, ror #16
+	and	r1, r2, r6
+	ldr	r9, [lr, r9, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r10, r2, r5, lsr #16
+	eor	r9, r9, r11, ror #24
+	lsr	r11, r6, #24
+	eor	r9, r9, r0, ror #8
+	and	r0, r2, r4, lsr #8
+	eor	r9, r9, r1, ror #16
+	and	r1, r2, r7
+	ldr	r10, [lr, r10, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	and	r4, r2, r4
+	eor	r10, r10, r11, ror #24
+	and	r11, r2, r6, lsr #16
+	eor	r10, r10, r0, ror #8
+	lsr	r0, r7, #24
+	eor	r10, r10, r1, ror #16
+	and	r1, r2, r5, lsr #8
+	ldr	r4, [lr, r4, lsl #2]
+	ldr	r0, [lr, r0, lsl #2]
+	ldr	r11, [lr, r11, lsl #2]
+	ldr	r1, [lr, r1, lsl #2]
+	eor	r0, r0, r4, ror #24
+	ldm	r3!, {r4, r5, r6, r7}
+	eor	r11, r11, r1, ror #8
+	eor	r11, r11, r0, ror #24
+	#   XOR in Key Schedule
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	ldr	r12, L_AES_ARM32_td4p
+	and	r7, r2, r10, lsr #8
+	lsr	r1, r8, #24
+	and	r4, r2, r9
+	and	r0, r2, r11, lsr #16
+	ldrb	r7, [r12, r7]
+	ldrb	r1, [r12, r1]
+	ldrb	r4, [r12, r4]
+	ldrb	r0, [r12, r0]
+	and	r5, r2, r10
+	eor	r4, r4, r7, lsl #8
+	and	r7, r2, r11, lsr #8
+	eor	r4, r4, r0, lsl #16
+	and	r0, r2, r8, lsr #16
+	eor	r4, r4, r1, lsl #24
+	lsr	r1, r9, #24
+	ldrb	r7, [r12, r7]
+	ldrb	r1, [r12, r1]
+	ldrb	r5, [r12, r5]
+	ldrb	r0, [r12, r0]
+	and	r6, r2, r11
+	eor	r5, r5, r7, lsl #8
+	and	r7, r2, r8, lsr #8
+	eor	r5, r5, r0, lsl #16
+	and	r0, r2, r9, lsr #16
+	eor	r5, r5, r1, lsl #24
+	lsr	r1, r10, #24
+	ldrb	r7, [r12, r7]
+	ldrb	r1, [r12, r1]
+	ldrb	r6, [r12, r6]
+	ldrb	r0, [r12, r0]
+	lsr	r11, r11, #24
+	eor	r6, r6, r7, lsl #8
+	and	r7, r2, r8
+	eor	r6, r6, r0, lsl #16
+	and	r0, r2, r9, lsr #8
+	eor	r6, r6, r1, lsl #24
+	and	r1, r2, r10, lsr #16
+	ldrb	r11, [r12, r11]
+	ldrb	r0, [r12, r0]
+	ldrb	r7, [r12, r7]
+	ldrb	r1, [r12, r1]
+	eor	r0, r0, r11, lsl #16
+	ldm	r3, {r8, r9, r10, r11}
+	eor	r7, r7, r0, lsl #8
+	eor	r7, r7, r1, lsl #16
+	#   XOR in Key Schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	str	lr, [sp, #8]
+	pop	{lr}
+	bx	lr
+	bx	lr
+	.size	AES_decrypt_block,.-AES_decrypt_block
+#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
+	.text
+	.type	L_AES_ARM32_tdp, %object
+	.size	L_AES_ARM32_tdp, 4
+	.align	4
+L_AES_ARM32_tdp:
+	.word	L_AES_ARM32_td
+	.text
+	.align	4
+	.globl	AES_ECB_decrypt
+	.type	AES_ECB_decrypt, %function
+AES_ECB_decrypt:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r12, [sp, #36]
+	mov	r8, r12
+	ldr	lr, L_AES_ARM32_tdp
+	cmp	r8, #10
+	beq	L_AES_ECB_decrypt_start_block_128
+	cmp	r8, #12
+	beq	L_AES_ECB_decrypt_start_block_192
+L_AES_ECB_decrypt_loop_block_256:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_ECB_decrypt_loop_block_256
+	b	L_AES_ECB_decrypt_end
+L_AES_ECB_decrypt_start_block_192:
+L_AES_ECB_decrypt_loop_block_192:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_ECB_decrypt_loop_block_192
+	b	L_AES_ECB_decrypt_end
+L_AES_ECB_decrypt_start_block_128:
+L_AES_ECB_decrypt_loop_block_128:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_ECB_decrypt_loop_block_128
+L_AES_ECB_decrypt_end:
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_ECB_decrypt,.-AES_ECB_decrypt
+#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER */
+#ifdef HAVE_AES_CBC
+	.text
+	.type	L_AES_CBC_ARM32_tdp, %object
+	.size	L_AES_CBC_ARM32_tdp, 4
+	.align	4
+L_AES_CBC_ARM32_tdp:
+	.word	L_AES_ARM32_td
+	.text
+	.align	4
+	.globl	AES_CBC_decrypt
+	.type	AES_CBC_decrypt, %function
+AES_CBC_decrypt:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r12, [sp, #36]
+	ldr	lr, [sp, #40]
+	push	{lr}
+	mov	r8, r12
+	ldr	lr, L_AES_CBC_ARM32_tdp
+	cmp	r8, #10
+	beq	L_AES_CBC_decrypt_start_block_128
+	cmp	r8, #12
+	beq	L_AES_CBC_decrypt_start_block_192
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	ldr	r11, [sp]
+	ldm	r11, {r8, r9, r10, r11}
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	beq	L_AES_CBC_decrypt_end
+L_AES_CBC_decrypt_loop_block_256:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #-16]
+	ldr	r9, [r0, #-12]
+#else
+	ldrd	r8, r9, [r0, #-16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #-8]
+	ldr	r11, [r0, #-4]
+#else
+	ldrd	r10, r11, [r0, #-8]
+#endif
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CBC_decrypt_loop_block_256
+	b	L_AES_CBC_decrypt_end
+L_AES_CBC_decrypt_start_block_192:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	ldr	r11, [sp]
+	ldm	r11, {r8, r9, r10, r11}
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	beq	L_AES_CBC_decrypt_end
+L_AES_CBC_decrypt_loop_block_192:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #-16]
+	ldr	r9, [r0, #-12]
+#else
+	ldrd	r8, r9, [r0, #-16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #-8]
+	ldr	r11, [r0, #-4]
+#else
+	ldrd	r10, r11, [r0, #-8]
+#endif
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CBC_decrypt_loop_block_192
+	b	L_AES_CBC_decrypt_end
+L_AES_CBC_decrypt_start_block_128:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	ldr	r11, [sp]
+	ldm	r11, {r8, r9, r10, r11}
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	beq	L_AES_CBC_decrypt_end
+L_AES_CBC_decrypt_loop_block_128:
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	push	{r0, r1, r2}
+	mov	r2, #0xff
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_decrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1, r2}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #-16]
+	ldr	r9, [r0, #-12]
+#else
+	ldrd	r8, r9, [r0, #-16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #-8]
+	ldr	r11, [r0, #-4]
+#else
+	ldrd	r10, r11, [r0, #-8]
+#endif
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_CBC_decrypt_loop_block_128
+L_AES_CBC_decrypt_end:
+	pop	{lr}
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #-16]
+	ldr	r9, [r0, #-12]
+#else
+	ldrd	r8, r9, [r0, #-16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #-8]
+	ldr	r11, [r0, #-4]
+#else
+	ldrd	r10, r11, [r0, #-8]
+#endif
+	stm	lr, {r8, r9, r10, r11}
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_CBC_decrypt,.-AES_CBC_decrypt
+#endif /* HAVE_AES_CBC */
+#endif /* WOLFSSL_AES_DIRECT || WOLFSSL_AES_COUNTER || HAVE_AES_CBC */
+#endif /* HAVE_AES_DECRYPT */
+#ifdef HAVE_AESGCM
+	.text
+	.type	L_GCM_gmult_len_r, %object
+	.size	L_GCM_gmult_len_r, 64
+	.align	4
+L_GCM_gmult_len_r:
+	.word	0x0
+	.word	0x1c200000
+	.word	0x38400000
+	.word	0x24600000
+	.word	0x70800000
+	.word	0x6ca00000
+	.word	0x48c00000
+	.word	0x54e00000
+	.word	0xe1000000
+	.word	0xfd200000
+	.word	0xd9400000
+	.word	0xc5600000
+	.word	0x91800000
+	.word	0x8da00000
+	.word	0xa9c00000
+	.word	0xb5e00000
+	.text
+	.align	4
+	.globl	GCM_gmult_len
+	.type	GCM_gmult_len, %function
+GCM_gmult_len:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	adr	lr, L_GCM_gmult_len_r
+L_GCM_gmult_len_start_block:
+	push	{r3}
+	ldr	r12, [r0, #12]
+	ldr	r3, [r2, #12]
+	eor	r12, r12, r3
+	lsr	r3, r12, #24
+	and	r3, r3, #15
+	add	r3, r1, r3, lsl #4
+	ldm	r3, {r8, r9, r10, r11}
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #28
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #16
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #20
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #8
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #12
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	and	r4, r12, #15
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #4
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	ldr	r12, [r0, #8]
+	ldr	r3, [r2, #8]
+	eor	r12, r12, r3
+	lsr	r3, r12, #24
+	and	r3, r3, #15
+	add	r3, r1, r3, lsl #4
+	ldm	r3, {r4, r5, r6, r7}
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #28
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #16
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #20
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #8
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #12
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	and	r4, r12, #15
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #4
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	ldr	r12, [r0, #4]
+	ldr	r3, [r2, #4]
+	eor	r12, r12, r3
+	lsr	r3, r12, #24
+	and	r3, r3, #15
+	add	r3, r1, r3, lsl #4
+	ldm	r3, {r4, r5, r6, r7}
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #28
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #16
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #20
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #8
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #12
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	and	r4, r12, #15
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #4
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	ldr	r12, [r0]
+	ldr	r3, [r2]
+	eor	r12, r12, r3
+	lsr	r3, r12, #24
+	and	r3, r3, #15
+	add	r3, r1, r3, lsl #4
+	ldm	r3, {r4, r5, r6, r7}
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #28
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #16
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #20
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #8
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #12
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	and	r4, r12, #15
+	eor	r11, r11, r10, lsl #28
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	lsr	r6, r10, #4
+	and	r3, r11, #15
+	lsr	r11, r11, #4
+	lsr	r4, r12, #4
+	eor	r11, r11, r10, lsl #28
+	and	r4, r4, #15
+	ldr	r3, [lr, r3, lsl #2]
+	add	r4, r1, r4, lsl #4
+	eor	r10, r6, r9, lsl #28
+	lsr	r9, r9, #4
+	ldm	r4, {r4, r5, r6, r7}
+	eor	r9, r9, r8, lsl #28
+	eor	r8, r3, r8, lsr #4
+	eor	r8, r8, r4
+	eor	r9, r9, r5
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	rev	r8, r8
+	rev	r9, r9
+	rev	r10, r10
+	rev	r11, r11
+	stm	r0, {r8, r9, r10, r11}
+	pop	{r3}
+	subs	r3, r3, #16
+	add	r2, r2, #16
+	bne	L_GCM_gmult_len_start_block
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	GCM_gmult_len,.-GCM_gmult_len
+	.text
+	.type	L_AES_GCM_ARM32_tep, %object
+	.size	L_AES_GCM_ARM32_tep, 4
+	.align	4
+L_AES_GCM_ARM32_tep:
+	.word	L_AES_ARM32_te
+	.text
+	.align	4
+	.globl	AES_GCM_encrypt
+	.type	AES_GCM_encrypt, %function
+AES_GCM_encrypt:
+	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
+	ldr	r12, [sp, #36]
+	ldr	lr, [sp, #40]
+	ldm	lr, {r4, r5, r6, r7}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	lr, {r4, r5, r6, r7}
+	push	{lr}
+	ldr	lr, L_AES_GCM_ARM32_tep
+	cmp	r12, #10
+	beq	L_AES_GCM_encrypt_start_block_128
+	cmp	r12, #12
+	beq	L_AES_GCM_encrypt_start_block_192
+	mov	r12, #0xff
+L_AES_GCM_encrypt_loop_block_256:
+	push	{r0, r1}
+	ldr	r0, [sp, #8]
+	add	r7, r7, #1
+	str	r7, [r0, #12]
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_14
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r8
+	eor	r5, r9
+	eor	r6, r10
+	eor	r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	ldr	r8, [sp]
+	ldm	r8, {r4, r5, r6, r7}
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_GCM_encrypt_loop_block_256
+	b	L_AES_GCM_encrypt_end
+L_AES_GCM_encrypt_start_block_192:
+	mov	r12, #0xff
+L_AES_GCM_encrypt_loop_block_192:
+	push	{r0, r1}
+	ldr	r0, [sp, #8]
+	add	r7, r7, #1
+	str	r7, [r0, #12]
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_12
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r8
+	eor	r5, r9
+	eor	r6, r10
+	eor	r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	ldr	r8, [sp]
+	ldm	r8, {r4, r5, r6, r7}
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_GCM_encrypt_loop_block_192
+	b	L_AES_GCM_encrypt_end
+L_AES_GCM_encrypt_start_block_128:
+	mov	r12, #0xff
+L_AES_GCM_encrypt_loop_block_128:
+	push	{r0, r1}
+	ldr	r0, [sp, #8]
+	add	r7, r7, #1
+	str	r7, [r0, #12]
+	push	{r3, lr}
+	ldm	r3!, {r8, r9, r10, r11}
+	# Round: 0 - XOR in key schedule
+	eor	r4, r4, r8
+	eor	r5, r5, r9
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+	bl	L_AES_encrypt_block_10
+	pop	{r3, lr}
+	pop	{r0, r1}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
+#else
+	ldrd	r10, r11, [r0, #8]
+#endif
+	eor	r4, r8
+	eor	r5, r9
+	eor	r6, r10
+	eor	r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r1]
+	str	r5, [r1, #4]
+#else
+	strd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r1, #8]
+	str	r7, [r1, #12]
+#else
+	strd	r6, r7, [r1, #8]
+#endif
+	ldr	r8, [sp]
+	ldm	r8, {r4, r5, r6, r7}
+	subs	r2, r2, #16
+	add	r0, r0, #16
+	add	r1, r1, #16
+	bne	L_AES_GCM_encrypt_loop_block_128
+L_AES_GCM_encrypt_end:
+	pop	{lr}
+	rev	r4, r4
+	rev	r5, r5
+	rev	r6, r6
+	rev	r7, r7
+	stm	lr, {r4, r5, r6, r7}
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	AES_GCM_encrypt,.-AES_GCM_encrypt
+#endif /* HAVE_AESGCM */
+#endif /* !NO_AES */
+#endif /* !__aarch64__ */
+#endif /* WOLFSSL_ARMASM */
+
+#if defined(__linux__) && defined(__ELF__)
+.section	.note.GNU-stack,"",%progbits
+#endif
diff --git a/wolfcrypt/src/port/arm/armv8-32-curve25519.S b/wolfcrypt/src/port/arm/armv8-32-curve25519.S
index a266995e9..8f8e84884 100644
--- a/wolfcrypt/src/port/arm/armv8-32-curve25519.S
+++ b/wolfcrypt/src/port/arm/armv8-32-curve25519.S
@@ -31,2408 +31,2410 @@
 #ifdef HAVE_CURVE25519
 
 	.text
-	.align	2
+	.align	4
 	.globl	fe_init
 	.type	fe_init, %function
 fe_init:
 	bx	lr
 	.size	fe_init,.-fe_init
 	.text
-	.align	2
+	.align	4
 	.globl	fe_frombytes
 	.type	fe_frombytes, %function
 fe_frombytes:
-	push	{r4, r5, r6, r7, lr}
+	push	{r4, r5, r6, r7, r8, r9}
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r2, [r1]
 	ldr	r3, [r1, #4]
 #else
-	ldrd  r2, r3, [r1]
+	ldrd	r2, r3, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #8]
-	ldr	lr, [r1, #12]
+	ldr	r4, [r1, #8]
+	ldr	r5, [r1, #12]
 #else
-	ldrd  r12, lr, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #16]
-	ldr	r5, [r1, #20]
+	ldr	r6, [r1, #16]
+	ldr	r7, [r1, #20]
 #else
-	ldrd  r4, r5, [r1, #16]
+	ldrd	r6, r7, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #24]
-	ldr	r7, [r1, #28]
+	ldr	r8, [r1, #24]
+	ldr	r9, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r8, r9, [r1, #24]
 #endif
-	and	r7, r7, #0x7fffffff
+	and	r9, r9, #0x7fffffff
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r2, [r0]
 	str	r3, [r0, #4]
 #else
-	strd  r2, r3, [r0]
+	strd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
 #else
-	strd  r12, lr, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #16]
-	str	r5, [r0, #20]
+	str	r6, [r0, #16]
+	str	r7, [r0, #20]
 #else
-	strd  r4, r5, [r0, #16]
+	strd	r6, r7, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #24]
-	str	r7, [r0, #28]
+	str	r8, [r0, #24]
+	str	r9, [r0, #28]
 #else
-	strd  r6, r7, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
-	pop	{r4, r5, r6, r7, pc}
+	pop	{r4, r5, r6, r7, r8, pc}
 	.size	fe_frombytes,.-fe_frombytes
 	.text
-	.align	2
+	.align	4
 	.globl	fe_tobytes
 	.type	fe_tobytes, %function
 fe_tobytes:
-	push	{r4, r5, r6, r7, r8, lr}
+	push	{r4, r5, r6, r7, r8, r9}
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r2, [r1]
 	ldr	r3, [r1, #4]
 #else
-	ldrd  r2, r3, [r1]
+	ldrd	r2, r3, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #8]
-	ldr	lr, [r1, #12]
+	ldr	r4, [r1, #8]
+	ldr	r5, [r1, #12]
 #else
-	ldrd  r12, lr, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #16]
-	ldr	r5, [r1, #20]
+	ldr	r6, [r1, #16]
+	ldr	r7, [r1, #20]
 #else
-	ldrd  r4, r5, [r1, #16]
+	ldrd	r6, r7, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #24]
-	ldr	r7, [r1, #28]
+	ldr	r8, [r1, #24]
+	ldr	r9, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r8, r9, [r1, #24]
 #endif
-	adds	r8, r2, #19
-	adcs	r8, r3, #0
-	adcs	r8, r12, #0
-	adcs	r8, lr, #0
-	adcs	r8, r4, #0
-	adcs	r8, r5, #0
-	adcs	r8, r6, #0
-	adc	r8, r7, #0
-	asr	r8, r8, #31
-	and	r8, r8, #19
-	adds	r2, r2, r8
+	adds	r12, r2, #19
+	adcs	r12, r3, #0
+	adcs	r12, r4, #0
+	adcs	r12, r5, #0
+	adcs	r12, r6, #0
+	adcs	r12, r7, #0
+	adcs	r12, r8, #0
+	adc	r12, r9, #0
+	asr	r12, r12, #31
+	and	r12, r12, #19
+	adds	r2, r2, r12
 	adcs	r3, r3, #0
-	adcs	r12, r12, #0
-	adcs	lr, lr, #0
 	adcs	r4, r4, #0
 	adcs	r5, r5, #0
 	adcs	r6, r6, #0
-	adc	r7, r7, #0
-	and	r7, r7, #0x7fffffff
+	adcs	r7, r7, #0
+	adcs	r8, r8, #0
+	adc	r9, r9, #0
+	and	r9, r9, #0x7fffffff
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r2, [r0]
 	str	r3, [r0, #4]
 #else
-	strd  r2, r3, [r0]
+	strd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
 #else
-	strd  r12, lr, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #16]
-	str	r5, [r0, #20]
+	str	r6, [r0, #16]
+	str	r7, [r0, #20]
 #else
-	strd  r4, r5, [r0, #16]
+	strd	r6, r7, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #24]
-	str	r7, [r0, #28]
+	str	r8, [r0, #24]
+	str	r9, [r0, #28]
 #else
-	strd  r6, r7, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	pop	{r4, r5, r6, r7, r8, pc}
 	.size	fe_tobytes,.-fe_tobytes
 	.text
-	.align	2
+	.align	4
 	.globl	fe_1
 	.type	fe_1, %function
 fe_1:
 	# Set one
 	mov	r2, #1
-	mov	r1, #0
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r2, [r0]
-	str	r1, [r0, #4]
-#else
-	strd  r2, r1, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0, #8]
-	str	r1, [r0, #12]
-#else
-	strd  r1, r1, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0, #16]
-	str	r1, [r0, #20]
-#else
-	strd  r1, r1, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0, #24]
-	str	r1, [r0, #28]
-#else
-	strd  r1, r1, [r0, #24]
-#endif
-	bx	lr
-	.size	fe_1,.-fe_1
-	.text
-	.align	2
-	.globl	fe_0
-	.type	fe_0, %function
-fe_0:
-	# Set zero
-	mov	r1, #0
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0]
-	str	r1, [r0, #4]
-#else
-	strd  r1, r1, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0, #8]
-	str	r1, [r0, #12]
-#else
-	strd  r1, r1, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0, #16]
-	str	r1, [r0, #20]
-#else
-	strd  r1, r1, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r1, [r0, #24]
-	str	r1, [r0, #28]
-#else
-	strd  r1, r1, [r0, #24]
-#endif
-	bx	lr
-	.size	fe_0,.-fe_0
-	.text
-	.align	2
-	.globl	fe_copy
-	.type	fe_copy, %function
-fe_copy:
-	push	{lr}
-	# Copy
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r2, [r1]
-	ldr	r3, [r1, #4]
-#else
-	ldrd  r2, r3, [r1]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #8]
-	ldr	lr, [r1, #12]
-#else
-	ldrd  r12, lr, [r1, #8]
-#endif
+	mov	r3, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r2, [r0]
 	str	r3, [r0, #4]
 #else
-	strd  r2, r3, [r0]
+	strd	r2, r3, [r0]
 #endif
+	mov	r2, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
+	str	r2, [r0, #8]
+	str	r3, [r0, #12]
 #else
-	strd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r2, [r1, #16]
-	ldr	r3, [r1, #20]
-#else
-	ldrd  r2, r3, [r1, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #24]
-	ldr	lr, [r1, #28]
-#else
-	ldrd  r12, lr, [r1, #24]
+	strd	r2, r3, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r2, [r0, #16]
 	str	r3, [r0, #20]
 #else
-	strd  r2, r3, [r0, #16]
+	strd	r2, r3, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
+	str	r2, [r0, #24]
+	str	r3, [r0, #28]
 #else
-	strd  r12, lr, [r0, #24]
+	strd	r2, r3, [r0, #24]
 #endif
-	pop	{pc}
+	bx	lr
+	.size	fe_1,.-fe_1
+	.text
+	.align	4
+	.globl	fe_0
+	.type	fe_0, %function
+fe_0:
+	# Set zero
+	mov	r2, #0
+	mov	r3, #0
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r2, [r0]
+	str	r3, [r0, #4]
+#else
+	strd	r2, r3, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r2, [r0, #8]
+	str	r3, [r0, #12]
+#else
+	strd	r2, r3, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r2, [r0, #16]
+	str	r3, [r0, #20]
+#else
+	strd	r2, r3, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r2, [r0, #24]
+	str	r3, [r0, #28]
+#else
+	strd	r2, r3, [r0, #24]
+#endif
+	bx	lr
+	.size	fe_0,.-fe_0
+	.text
+	.align	4
+	.globl	fe_copy
+	.type	fe_copy, %function
+fe_copy:
+	push	{r4, r5}
+	# Copy
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r2, [r1]
+	ldr	r3, [r1, #4]
+#else
+	ldrd	r2, r3, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r1, #8]
+	ldr	r5, [r1, #12]
+#else
+	ldrd	r4, r5, [r1, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r2, [r0]
+	str	r3, [r0, #4]
+#else
+	strd	r2, r3, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r2, [r1, #16]
+	ldr	r3, [r1, #20]
+#else
+	ldrd	r2, r3, [r1, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r1, #24]
+	ldr	r5, [r1, #28]
+#else
+	ldrd	r4, r5, [r1, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r2, [r0, #16]
+	str	r3, [r0, #20]
+#else
+	strd	r2, r3, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	pop	{r4, pc}
 	.size	fe_copy,.-fe_copy
 	.text
-	.align	2
+	.align	4
 	.globl	fe_sub
 	.type	fe_sub, %function
 fe_sub:
 	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1]
-	ldr	lr, [r1, #4]
+	ldr	r4, [r1]
+	ldr	r5, [r1, #4]
 #else
-	ldrd  r12, lr, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #8]
-	ldr	r5, [r1, #12]
+	ldr	r6, [r1, #8]
+	ldr	r7, [r1, #12]
 #else
-	ldrd  r4, r5, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r2]
-	ldr	r7, [r2, #4]
+	ldr	r8, [r2]
+	ldr	r9, [r2, #4]
 #else
-	ldrd  r6, r7, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r2, #8]
-	ldr	r9, [r2, #12]
+	ldr	r10, [r2, #8]
+	ldr	r11, [r2, #12]
 #else
-	ldrd  r8, r9, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
+#endif
+	subs	r8, r4, r8
+	sbcs	r9, r5, r9
+	sbcs	r10, r6, r10
+	sbcs	r11, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0]
+	str	r9, [r0, #4]
+#else
+	strd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r10, [r0, #8]
+	str	r11, [r0, #12]
+#else
+	strd	r10, r11, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r1, #16]
+	ldr	r5, [r1, #20]
+#else
+	ldrd	r4, r5, [r1, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r1, #24]
+	ldr	r7, [r1, #28]
+#else
+	ldrd	r6, r7, [r1, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r2, #16]
+	ldr	r9, [r2, #20]
+#else
+	ldrd	r8, r9, [r2, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r2, #24]
+	ldr	r11, [r2, #28]
+#else
+	ldrd	r10, r11, [r2, #24]
 #endif
-	subs	r6, r12, r6
-	sbcs	r7, lr, r7
 	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0]
-	str	r7, [r0, #4]
-#else
-	strd  r6, r7, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [r0, #8]
-	str	r9, [r0, #12]
-#else
-	strd  r8, r9, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #16]
-	ldr	lr, [r1, #20]
-#else
-	ldrd  r12, lr, [r1, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #24]
-	ldr	r5, [r1, #28]
-#else
-	ldrd  r4, r5, [r1, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r2, #16]
-	ldr	r7, [r2, #20]
-#else
-	ldrd  r6, r7, [r2, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r2, #24]
-	ldr	r9, [r2, #28]
-#else
-	ldrd  r8, r9, [r2, #24]
-#endif
-	sbcs	r6, r12, r6
-	sbcs	r7, lr, r7
-	sbcs	r8, r4, r8
-	sbc	r9, r5, r9
-	mov	r10, #-19
-	asr	r3, r9, #31
+	sbcs	r10, r6, r10
+	sbc	r11, r7, r11
+	mov	r12, #-19
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r10, r3, r10
-	and	r11, r3, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
 #else
-	ldrd  r12, lr, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r12, r12, r10
-	adcs	lr, lr, r3
-	adcs	r4, r4, r3
+	adds	r4, r4, r12
 	adcs	r5, r5, r3
 	adcs	r6, r6, r3
 	adcs	r7, r7, r3
 	adcs	r8, r8, r3
-	adc	r9, r9, r11
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
+	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
+	str	r4, [r0]
+	str	r5, [r0, #4]
 #else
-	strd  r12, lr, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #8]
-	str	r5, [r0, #12]
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #16]
-	str	r7, [r0, #20]
+	str	r8, [r0, #16]
+	str	r9, [r0, #20]
 #else
-	strd  r6, r7, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [r0, #24]
-	str	r9, [r0, #28]
+	str	r10, [r0, #24]
+	str	r11, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_sub,.-fe_sub
 	.text
-	.align	2
+	.align	4
 	.globl	fe_add
 	.type	fe_add, %function
 fe_add:
 	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 	# Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1]
-	ldr	lr, [r1, #4]
+	ldr	r4, [r1]
+	ldr	r5, [r1, #4]
 #else
-	ldrd  r12, lr, [r1]
+	ldrd	r4, r5, [r1]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r1, #8]
+	ldr	r7, [r1, #12]
+#else
+	ldrd	r6, r7, [r1, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r2]
+	ldr	r9, [r2, #4]
+#else
+	ldrd	r8, r9, [r2]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r2, #8]
+	ldr	r11, [r2, #12]
+#else
+	ldrd	r10, r11, [r2, #8]
+#endif
+	adds	r8, r4, r8
+	adcs	r9, r5, r9
+	adcs	r10, r6, r10
+	adcs	r11, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0]
+	str	r9, [r0, #4]
+#else
+	strd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r10, [r0, #8]
+	str	r11, [r0, #12]
+#else
+	strd	r10, r11, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r1, #16]
+	ldr	r5, [r1, #20]
+#else
+	ldrd	r4, r5, [r1, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r1, #24]
+	ldr	r7, [r1, #28]
+#else
+	ldrd	r6, r7, [r1, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r2, #16]
+	ldr	r9, [r2, #20]
+#else
+	ldrd	r8, r9, [r2, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r2, #24]
+	ldr	r11, [r2, #28]
+#else
+	ldrd	r10, r11, [r2, #24]
+#endif
+	adcs	r8, r4, r8
+	adcs	r9, r5, r9
+	adcs	r10, r6, r10
+	adc	r11, r7, r11
+	mov	r12, #-19
+	asr	r3, r11, #31
+	#   Mask the modulus
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
+	#   Sub modulus (if overflow)
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
+	sbc	r11, r11, lr
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
+#else
+	strd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #16]
+	str	r9, [r0, #20]
+#else
+	strd	r8, r9, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r10, [r0, #24]
+	str	r11, [r0, #28]
+#else
+	strd	r10, r11, [r0, #24]
+#endif
+	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
+	.size	fe_add,.-fe_add
+	.text
+	.align	4
+	.globl	fe_neg
+	.type	fe_neg, %function
+fe_neg:
+	push	{r4, r5, lr}
+	mov	lr, #-1
+	mov	r12, #-19
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r2, [r1]
+	ldr	r3, [r1, #4]
+#else
+	ldrd	r2, r3, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r4, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
+	subs	r2, r12, r2
+	sbcs	r3, lr, r3
+	sbcs	r4, lr, r4
+	sbcs	r5, lr, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r2]
-	ldr	r7, [r2, #4]
+	str	r2, [r0]
+	str	r3, [r0, #4]
 #else
-	ldrd  r6, r7, [r2]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r2, #8]
-	ldr	r9, [r2, #12]
-#else
-	ldrd  r8, r9, [r2, #8]
-#endif
-	adds	r6, r12, r6
-	adcs	r7, lr, r7
-	adcs	r8, r4, r8
-	adcs	r9, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0]
-	str	r7, [r0, #4]
-#else
-	strd  r6, r7, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [r0, #8]
-	str	r9, [r0, #12]
-#else
-	strd  r8, r9, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #16]
-	ldr	lr, [r1, #20]
-#else
-	ldrd  r12, lr, [r1, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #24]
-	ldr	r5, [r1, #28]
-#else
-	ldrd  r4, r5, [r1, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r2, #16]
-	ldr	r7, [r2, #20]
-#else
-	ldrd  r6, r7, [r2, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r2, #24]
-	ldr	r9, [r2, #28]
-#else
-	ldrd  r8, r9, [r2, #24]
-#endif
-	adcs	r6, r12, r6
-	adcs	r7, lr, r7
-	adcs	r8, r4, r8
-	adc	r9, r5, r9
-	mov	r10, #-19
-	asr	r3, r9, #31
-	#   Mask the modulus
-	and	r10, r3, r10
-	and	r11, r3, #0x7fffffff
-	#   Sub modulus (if overflow)
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-	subs	r12, r12, r10
-	sbcs	lr, lr, r3
-	sbcs	r4, r4, r3
-	sbcs	r5, r5, r3
-	sbcs	r6, r6, r3
-	sbcs	r7, r7, r3
-	sbcs	r8, r8, r3
-	sbc	r9, r9, r11
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
+	strd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #16]
-	str	r7, [r0, #20]
+	mov	r12, #0x7fffff
+	lsl	r12, r12, #8
+	add	r12, r12, #0xff
 #else
-	strd  r6, r7, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [r0, #24]
-	str	r9, [r0, #28]
-#else
-	strd  r8, r9, [r0, #24]
-#endif
-	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
-	.size	fe_add,.-fe_add
-	.text
-	.align	2
-	.globl	fe_neg
-	.type	fe_neg, %function
-fe_neg:
-	push	{r4, r5, lr}
-	mov	r5, #-1
-	mov	r4, #-19
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r2, [r1]
-	ldr	r3, [r1, #4]
-#else
-	ldrd  r2, r3, [r1]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #8]
-	ldr	lr, [r1, #12]
-#else
-	ldrd  r12, lr, [r1, #8]
-#endif
-	subs	r2, r4, r2
-	sbcs	r3, r5, r3
-	sbcs	r12, r5, r12
-	sbcs	lr, r5, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r2, [r0]
-	str	r3, [r0, #4]
-#else
-	strd  r2, r3, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r4, #0x7fffff
-	lsl	r4, r4, #8
-	add	r4, r4, #0xff
-#else
-	mov	r4, #0x7fffffff
+	mov	r12, #0x7fffffff
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r2, [r1, #16]
 	ldr	r3, [r1, #20]
 #else
-	ldrd  r2, r3, [r1, #16]
+	ldrd	r2, r3, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #24]
-	ldr	lr, [r1, #28]
+	ldr	r4, [r1, #24]
+	ldr	r5, [r1, #28]
 #else
-	ldrd  r12, lr, [r1, #24]
+	ldrd	r4, r5, [r1, #24]
 #endif
-	sbcs	r2, r5, r2
-	sbcs	r3, r5, r3
-	sbcs	r12, r5, r12
-	sbc	lr, r4, lr
+	sbcs	r2, lr, r2
+	sbcs	r3, lr, r3
+	sbcs	r4, lr, r4
+	sbc	r5, r12, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r2, [r0, #16]
 	str	r3, [r0, #20]
 #else
-	strd  r2, r3, [r0, #16]
+	strd	r2, r3, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
 #else
-	strd  r12, lr, [r0, #24]
+	strd	r4, r5, [r0, #24]
 #endif
 	pop	{r4, r5, pc}
 	.size	fe_neg,.-fe_neg
 	.text
-	.align	2
+	.align	4
 	.globl	fe_isnonzero
 	.type	fe_isnonzero, %function
 fe_isnonzero:
-	push	{r4, r5, r6, r7, r8, lr}
+	push	{r4, r5, r6, r7, r8, r9}
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r2, [r0]
 	ldr	r3, [r0, #4]
 #else
-	ldrd  r2, r3, [r0]
+	ldrd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
 #else
-	ldrd  r12, lr, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r8, r9, [r0, #24]
 #endif
 	adds	r1, r2, #19
 	adcs	r1, r3, #0
-	adcs	r1, r12, #0
-	adcs	r1, lr, #0
 	adcs	r1, r4, #0
 	adcs	r1, r5, #0
 	adcs	r1, r6, #0
-	adc	r1, r7, #0
+	adcs	r1, r7, #0
+	adcs	r1, r8, #0
+	adc	r1, r9, #0
 	asr	r1, r1, #31
 	and	r1, r1, #19
 	adds	r2, r2, r1
 	adcs	r3, r3, #0
-	adcs	r12, r12, #0
-	adcs	lr, lr, #0
 	adcs	r4, r4, #0
 	adcs	r5, r5, #0
 	adcs	r6, r6, #0
-	adc	r7, r7, #0
-	and	r7, r7, #0x7fffffff
+	adcs	r7, r7, #0
+	adcs	r8, r8, #0
+	adc	r9, r9, #0
+	and	r9, r9, #0x7fffffff
 	orr	r2, r2, r3
-	orr	r12, r12, lr
 	orr	r4, r4, r5
 	orr	r6, r6, r7
-	orr	r12, r12, r4
-	orr	r2, r2, r6
-	orr	r0, r2, r12
+	orr	r8, r8, r9
+	orr	r4, r4, r6
+	orr	r2, r2, r8
+	orr	r0, r2, r4
 	pop	{r4, r5, r6, r7, r8, pc}
 	.size	fe_isnonzero,.-fe_isnonzero
 	.text
-	.align	2
+	.align	4
 	.globl	fe_isnegative
 	.type	fe_isnegative, %function
 fe_isnegative:
-	push	{lr}
+	push	{r4, r5}
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r2, [r0]
 	ldr	r3, [r0, #4]
 #else
-	ldrd  r2, r3, [r0]
+	ldrd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
 #else
-	ldrd  r12, lr, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 	adds	r1, r2, #19
 	adcs	r1, r3, #0
-	adcs	r1, r12, #0
-	adcs	r1, lr, #0
+	adcs	r1, r4, #0
+	adcs	r1, r5, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r2, [r0, #16]
 	ldr	r3, [r0, #20]
 #else
-	ldrd  r2, r3, [r0, #16]
+	ldrd	r2, r3, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
 #else
-	ldrd  r12, lr, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
 	adcs	r1, r2, #0
 	adcs	r1, r3, #0
-	adcs	r1, r12, #0
+	adcs	r1, r4, #0
 	ldr	r2, [r0]
-	adc	r1, lr, #0
+	adc	r1, r5, #0
 	and	r0, r2, #1
 	lsr	r1, r1, #31
 	eor	r0, r0, r1
-	pop	{pc}
+	pop	{r4, pc}
 	.size	fe_isnegative,.-fe_isnegative
 	.text
-	.align	2
+	.align	4
 	.globl	fe_cmov_table
 	.type	fe_cmov_table, %function
 fe_cmov_table:
 	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 	sxtb	r2, r2
-	sbfx	r7, r2, #7, #1
-	eor	r10, r2, r7
-	sub	r10, r10, r7
-	mov	r3, #1
-	mov	r12, #0
-	mov	lr, #1
+	sbfx	r3, r2, #7, #1
+	eor	r12, r2, r3
+	sub	r12, r12, r3
+	mov	r4, #1
+	mov	r5, #0
+	mov	r6, #1
+	mov	r7, #0
+	mov	r8, #0
+	mov	r9, #0
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #31
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #30
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #29
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #28
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #27
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #26
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #25
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	add	r1, r1, #0x60
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
+#else
+	mov	r3, #0x80000000
+#endif
+	ror	r3, r3, #24
+	ror	r3, r3, r12
+	asr	r3, r3, #31
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1]
+	ldr	r11, [r1, #4]
+#else
+	ldrd	r10, r11, [r1]
+#endif
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #32]
+	ldr	r11, [r1, #36]
+#else
+	ldrd	r10, r11, [r1, #32]
+#endif
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [r1, #64]
+	ldr	r11, [r1, #68]
+#else
+	ldrd	r10, r11, [r1, #64]
+#endif
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
+	sub	r1, r1, #0x2a0
+	mov	r10, #-19
+	mov	r11, #-1
+	subs	r10, r10, r8
+	sbcs	r11, r11, r9
+	sbc	lr, lr, lr
+	asr	r12, r2, #31
+	eor	r3, r4, r6
+	and	r3, r3, r12
+	eor	r4, r4, r3
+	eor	r6, r6, r3
+	eor	r3, r5, r7
+	and	r3, r3, r12
+	eor	r5, r5, r3
+	eor	r7, r7, r3
+	eor	r10, r10, r8
+	and	r10, r10, r12
+	eor	r8, r8, r10
+	eor	r11, r11, r9
+	and	r11, r11, r12
+	eor	r9, r9, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #32]
+	str	r7, [r0, #36]
+#else
+	strd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #64]
+	str	r9, [r0, #68]
+#else
+	strd	r8, r9, [r0, #64]
+#endif
+	sbfx	r3, r2, #7, #1
+	eor	r12, r2, r3
+	sub	r12, r12, r3
 	mov	r4, #0
 	mov	r5, #0
 	mov	r6, #0
+	mov	r7, #0
+	mov	r8, #0
+	mov	r9, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #31
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #31
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #30
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #30
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #29
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #29
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #28
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #28
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #27
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #27
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #26
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #26
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #25
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #25
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #24
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #24
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1]
-	ldr	r9, [r1, #4]
+	ldr	r10, [r1, #8]
+	ldr	r11, [r1, #12]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #32]
-	ldr	r9, [r1, #36]
+	ldr	r10, [r1, #40]
+	ldr	r11, [r1, #44]
 #else
-	ldrd  r8, r9, [r1, #32]
+	ldrd	r10, r11, [r1, #40]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #64]
-	ldr	r9, [r1, #68]
+	ldr	r10, [r1, #72]
+	ldr	r11, [r1, #76]
 #else
-	ldrd  r8, r9, [r1, #64]
+	ldrd	r10, r11, [r1, #72]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	sub	r1, r1, #0x2a0
-	mov	r8, #-19
-	mov	r9, #-1
-	subs	r8, r8, r5
-	sbcs	r9, r9, r6
-	sbc	r11, r11, r11
-	asr	r10, r2, #31
-	eor	r7, r3, lr
-	and	r7, r7, r10
-	eor	r3, r3, r7
-	eor	lr, lr, r7
-	eor	r7, r12, r4
-	and	r7, r7, r10
-	eor	r12, r12, r7
-	eor	r4, r4, r7
-	eor	r8, r8, r5
-	and	r8, r8, r10
-	eor	r5, r5, r8
-	eor	r9, r9, r6
-	and	r9, r9, r10
-	eor	r6, r6, r9
+	mov	r10, #-1
+	mov	r11, #-1
+	rsbs	lr, lr, #0
+	sbcs	r10, r10, r8
+	sbcs	r11, r11, r9
+	sbc	lr, lr, lr
+	asr	r12, r2, #31
+	eor	r3, r4, r6
+	and	r3, r3, r12
+	eor	r4, r4, r3
+	eor	r6, r6, r3
+	eor	r3, r5, r7
+	and	r3, r3, r12
+	eor	r5, r5, r3
+	eor	r7, r7, r3
+	eor	r10, r10, r8
+	and	r10, r10, r12
+	eor	r8, r8, r10
+	eor	r11, r11, r9
+	and	r11, r11, r12
+	eor	r9, r9, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
-	str	r12, [r0, #4]
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
 #else
-	strd  r3, r12, [r0]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	lr, [r0, #32]
-	str	r4, [r0, #36]
+	str	r6, [r0, #40]
+	str	r7, [r0, #44]
 #else
-	strd  lr, r4, [r0, #32]
+	strd	r6, r7, [r0, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r5, [r0, #64]
-	str	r6, [r0, #68]
+	str	r8, [r0, #72]
+	str	r9, [r0, #76]
 #else
-	strd  r5, r6, [r0, #64]
+	strd	r8, r9, [r0, #72]
 #endif
-	sbfx	r7, r2, #7, #1
-	eor	r10, r2, r7
-	sub	r10, r10, r7
-	mov	r3, #0
-	mov	r12, #0
-	mov	lr, #0
+	sbfx	r3, r2, #7, #1
+	eor	r12, r2, r3
+	sub	r12, r12, r3
 	mov	r4, #0
 	mov	r5, #0
 	mov	r6, #0
+	mov	r7, #0
+	mov	r8, #0
+	mov	r9, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #31
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #31
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #30
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #30
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #29
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #29
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #28
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #28
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #27
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #27
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #26
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #26
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #25
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #25
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #24
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #24
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #8]
-	ldr	r9, [r1, #12]
+	ldr	r10, [r1, #16]
+	ldr	r11, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #8]
+	ldrd	r10, r11, [r1, #16]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #40]
-	ldr	r9, [r1, #44]
+	ldr	r10, [r1, #48]
+	ldr	r11, [r1, #52]
 #else
-	ldrd  r8, r9, [r1, #40]
+	ldrd	r10, r11, [r1, #48]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #72]
-	ldr	r9, [r1, #76]
+	ldr	r10, [r1, #80]
+	ldr	r11, [r1, #84]
 #else
-	ldrd  r8, r9, [r1, #72]
+	ldrd	r10, r11, [r1, #80]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	sub	r1, r1, #0x2a0
-	mov	r8, #-1
-	mov	r9, #-1
-	rsbs	r11, r11, #0
-	sbcs	r8, r8, r5
-	sbcs	r9, r9, r6
-	sbc	r11, r11, r11
-	asr	r10, r2, #31
-	eor	r7, r3, lr
-	and	r7, r7, r10
-	eor	r3, r3, r7
-	eor	lr, lr, r7
-	eor	r7, r12, r4
-	and	r7, r7, r10
-	eor	r12, r12, r7
-	eor	r4, r4, r7
-	eor	r8, r8, r5
-	and	r8, r8, r10
-	eor	r5, r5, r8
-	eor	r9, r9, r6
-	and	r9, r9, r10
-	eor	r6, r6, r9
+	mov	r10, #-1
+	mov	r11, #-1
+	rsbs	lr, lr, #0
+	sbcs	r10, r10, r8
+	sbcs	r11, r11, r9
+	sbc	lr, lr, lr
+	asr	r12, r2, #31
+	eor	r3, r4, r6
+	and	r3, r3, r12
+	eor	r4, r4, r3
+	eor	r6, r6, r3
+	eor	r3, r5, r7
+	and	r3, r3, r12
+	eor	r5, r5, r3
+	eor	r7, r7, r3
+	eor	r10, r10, r8
+	and	r10, r10, r12
+	eor	r8, r8, r10
+	eor	r11, r11, r9
+	and	r11, r11, r12
+	eor	r9, r9, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
-	str	r12, [r0, #12]
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
 #else
-	strd  r3, r12, [r0, #8]
+	strd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	lr, [r0, #40]
-	str	r4, [r0, #44]
+	str	r6, [r0, #48]
+	str	r7, [r0, #52]
 #else
-	strd  lr, r4, [r0, #40]
+	strd	r6, r7, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r5, [r0, #72]
-	str	r6, [r0, #76]
+	str	r8, [r0, #80]
+	str	r9, [r0, #84]
 #else
-	strd  r5, r6, [r0, #72]
+	strd	r8, r9, [r0, #80]
 #endif
-	sbfx	r7, r2, #7, #1
-	eor	r10, r2, r7
-	sub	r10, r10, r7
-	mov	r3, #0
-	mov	r12, #0
-	mov	lr, #0
+	sbfx	r3, r2, #7, #1
+	eor	r12, r2, r3
+	sub	r12, r12, r3
 	mov	r4, #0
 	mov	r5, #0
 	mov	r6, #0
+	mov	r7, #0
+	mov	r8, #0
+	mov	r9, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #31
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #31
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #30
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #30
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #29
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #29
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #28
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #28
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #27
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #27
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #26
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #26
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #25
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #25
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	add	r1, r1, #0x60
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
+	mov	r3, #0x800000
+	lsl	r3, r3, #8
+	add	r3, r3, #0x0
 #else
-	mov	r7, #0x80000000
+	mov	r3, #0x80000000
 #endif
-	ror	r7, r7, #24
-	ror	r7, r7, r10
-	asr	r7, r7, #31
+	ror	r3, r3, #24
+	ror	r3, r3, r12
+	asr	r3, r3, #31
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #16]
-	ldr	r9, [r1, #20]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r4, r4, r10
+	eor	r5, r5, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #48]
-	ldr	r9, [r1, #52]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #48]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r6, r6, r10
+	eor	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #80]
-	ldr	r9, [r1, #84]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #80]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
+	eor	r10, r10, r8
+	eor	r11, r11, r9
+	and	r10, r10, r3
+	and	r11, r11, r3
+	eor	r8, r8, r10
+	eor	r9, r9, r11
 	sub	r1, r1, #0x2a0
-	mov	r8, #-1
-	mov	r9, #-1
-	rsbs	r11, r11, #0
-	sbcs	r8, r8, r5
-	sbcs	r9, r9, r6
-	sbc	r11, r11, r11
-	asr	r10, r2, #31
-	eor	r7, r3, lr
-	and	r7, r7, r10
-	eor	r3, r3, r7
-	eor	lr, lr, r7
-	eor	r7, r12, r4
-	and	r7, r7, r10
-	eor	r12, r12, r7
-	eor	r4, r4, r7
-	eor	r8, r8, r5
-	and	r8, r8, r10
-	eor	r5, r5, r8
-	eor	r9, r9, r6
-	and	r9, r9, r10
-	eor	r6, r6, r9
+	mov	r10, #-1
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
-	str	r12, [r0, #20]
+	mov	r11, #0x7fffff
+	lsl	r11, r11, #8
+	add	r11, r11, #0xff
 #else
-	strd  r3, r12, [r0, #16]
+	mov	r11, #0x7fffffff
+#endif
+	rsbs	lr, lr, #0
+	sbcs	r10, r10, r8
+	sbc	r11, r11, r9
+	asr	r12, r2, #31
+	eor	r3, r4, r6
+	and	r3, r3, r12
+	eor	r4, r4, r3
+	eor	r6, r6, r3
+	eor	r3, r5, r7
+	and	r3, r3, r12
+	eor	r5, r5, r3
+	eor	r7, r7, r3
+	eor	r10, r10, r8
+	and	r10, r10, r12
+	eor	r8, r8, r10
+	eor	r11, r11, r9
+	and	r11, r11, r12
+	eor	r9, r9, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	lr, [r0, #48]
-	str	r4, [r0, #52]
+	str	r6, [r0, #56]
+	str	r7, [r0, #60]
 #else
-	strd  lr, r4, [r0, #48]
+	strd	r6, r7, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r5, [r0, #80]
-	str	r6, [r0, #84]
+	str	r8, [r0, #88]
+	str	r9, [r0, #92]
 #else
-	strd  r5, r6, [r0, #80]
-#endif
-	sbfx	r7, r2, #7, #1
-	eor	r10, r2, r7
-	sub	r10, r10, r7
-	mov	r3, #0
-	mov	r12, #0
-	mov	lr, #0
-	mov	r4, #0
-	mov	r5, #0
-	mov	r6, #0
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #31
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #30
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #29
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #28
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #27
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #26
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #25
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	add	r1, r1, #0x60
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r7, #0x800000
-	lsl	r7, r7, #8
-	add	r7, r7, #0x0
-#else
-	mov	r7, #0x80000000
-#endif
-	ror	r7, r7, #24
-	ror	r7, r7, r10
-	asr	r7, r7, #31
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
-#else
-	ldrd  r8, r9, [r1, #24]
-#endif
-	eor	r8, r8, r3
-	eor	r9, r9, r12
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r3, r3, r8
-	eor	r12, r12, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
-#else
-	ldrd  r8, r9, [r1, #56]
-#endif
-	eor	r8, r8, lr
-	eor	r9, r9, r4
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	lr, lr, r8
-	eor	r4, r4, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
-#else
-	ldrd  r8, r9, [r1, #88]
-#endif
-	eor	r8, r8, r5
-	eor	r9, r9, r6
-	and	r8, r8, r7
-	and	r9, r9, r7
-	eor	r5, r5, r8
-	eor	r6, r6, r9
-	sub	r1, r1, #0x2a0
-	mov	r8, #-1
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	mov	r9, #0x7fffff
-	lsl	r9, r9, #8
-	add	r9, r9, #0xff
-#else
-	mov	r9, #0x7fffffff
-#endif
-	rsbs	r11, r11, #0
-	sbcs	r8, r8, r5
-	sbc	r9, r9, r6
-	asr	r10, r2, #31
-	eor	r7, r3, lr
-	and	r7, r7, r10
-	eor	r3, r3, r7
-	eor	lr, lr, r7
-	eor	r7, r12, r4
-	and	r7, r7, r10
-	eor	r12, r12, r7
-	eor	r4, r4, r7
-	eor	r8, r8, r5
-	and	r8, r8, r10
-	eor	r5, r5, r8
-	eor	r9, r9, r6
-	and	r9, r9, r10
-	eor	r6, r6, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #24]
-	str	r12, [r0, #28]
-#else
-	strd  r3, r12, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	lr, [r0, #56]
-	str	r4, [r0, #60]
-#else
-	strd  lr, r4, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r5, [r0, #88]
-	str	r6, [r0, #92]
-#else
-	strd  r5, r6, [r0, #88]
+	strd	r8, r9, [r0, #88]
 #endif
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_cmov_table,.-fe_cmov_table
 	.text
-	.align	2
+	.align	4
 	.globl	fe_mul
 	.type	fe_mul, %function
 fe_mul:
@@ -2857,25 +2859,25 @@ fe_mul:
 	ldr	r4, [sp]
 	ldr	r5, [sp, #4]
 #else
-	ldrd  r4, r5, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #8]
 	ldr	r7, [sp, #12]
 #else
-	ldrd  r6, r7, [sp, #8]
+	ldrd	r6, r7, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #16]
 	ldr	r9, [sp, #20]
 #else
-	ldrd  r8, r9, [sp, #16]
+	ldrd	r8, r9, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #24]
 	ldr	r11, [sp, #28]
 #else
-	ldrd  r10, r11, [sp, #24]
+	ldrd	r10, r11, [sp, #24]
 #endif
 	lsr	r3, r11, #31
 	and	r11, r11, #0x7fffffff
@@ -2977,31 +2979,31 @@ fe_mul:
 	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	add	sp, sp, #0x40
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_mul,.-fe_mul
 	.text
-	.align	2
+	.align	4
 	.globl	fe_sq
 	.type	fe_sq, %function
 fe_sq:
@@ -3318,25 +3320,25 @@ fe_sq:
 	ldr	r4, [sp]
 	ldr	r5, [sp, #4]
 #else
-	ldrd  r4, r5, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #8]
 	ldr	r7, [sp, #12]
 #else
-	ldrd  r6, r7, [sp, #8]
+	ldrd	r6, r7, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #16]
 	ldr	r9, [sp, #20]
 #else
-	ldrd  r8, r9, [sp, #16]
+	ldrd	r8, r9, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #24]
 	ldr	r11, [sp, #28]
 #else
-	ldrd  r10, r11, [sp, #24]
+	ldrd	r10, r11, [sp, #24]
 #endif
 	lsr	r2, r11, #31
 	and	r11, r11, #0x7fffffff
@@ -3438,31 +3440,31 @@ fe_sq:
 	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	add	sp, sp, #0x40
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_sq,.-fe_sq
 	.text
-	.align	2
+	.align	4
 	.globl	fe_mul121666
 	.type	fe_mul121666, %function
 fe_mul121666:
@@ -3472,25 +3474,25 @@ fe_mul121666:
 	ldr	r2, [r1]
 	ldr	r3, [r1, #4]
 #else
-	ldrd  r2, r3, [r1]
+	ldrd	r2, r3, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r4, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #16]
 	ldr	r7, [r1, #20]
 #else
-	ldrd  r6, r7, [r1, #16]
+	ldrd	r6, r7, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1, #24]
 	ldr	r9, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #24]
+	ldrd	r8, r9, [r1, #24]
 #endif
 	movw	lr, #0xdb42
 	movt	lr, #1
@@ -3533,30 +3535,30 @@ fe_mul121666:
 	str	r2, [r0]
 	str	r3, [r0, #4]
 #else
-	strd  r2, r3, [r0]
+	strd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #16]
 	str	r7, [r0, #20]
 #else
-	strd  r6, r7, [r0, #16]
+	strd	r6, r7, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
 	.size	fe_mul121666,.-fe_mul121666
 	.text
-	.align	2
+	.align	4
 	.globl	fe_sq2
 	.type	fe_sq2, %function
 fe_sq2:
@@ -3873,25 +3875,25 @@ fe_sq2:
 	ldr	r4, [sp]
 	ldr	r5, [sp, #4]
 #else
-	ldrd  r4, r5, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #8]
 	ldr	r7, [sp, #12]
 #else
-	ldrd  r6, r7, [sp, #8]
+	ldrd	r6, r7, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #16]
 	ldr	r9, [sp, #20]
 #else
-	ldrd  r8, r9, [sp, #16]
+	ldrd	r8, r9, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #24]
 	ldr	r11, [sp, #28]
 #else
-	ldrd  r10, r11, [sp, #24]
+	ldrd	r10, r11, [sp, #24]
 #endif
 	lsr	r2, r11, #30
 	lsl	r11, r11, #1
@@ -4008,31 +4010,31 @@ fe_sq2:
 	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	add	sp, sp, #0x40
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_sq2,.-fe_sq2
 	.text
-	.align	2
+	.align	4
 	.globl	fe_invert
 	.type	fe_invert, %function
 fe_invert:
@@ -4182,7 +4184,7 @@ L_fe_invert8:
 	pop	{r4, pc}
 	.size	fe_invert,.-fe_invert
 	.text
-	.align	2
+	.align	4
 	.globl	curve25519
 	.type	curve25519, %function
 curve25519:
@@ -4194,133 +4196,136 @@ curve25519:
 	mov	r1, #0
 	str	r1, [sp, #172]
 	# Set one
-	mov	r11, #1
+	mov	r10, #1
+	mov	r11, #0
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r10, [r0]
+	str	r11, [r0, #4]
+#else
+	strd	r10, r11, [r0]
+#endif
 	mov	r10, #0
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r11, [r0]
-	str	r10, [r0, #4]
-#else
-	strd  r11, r10, [r0]
-#endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
-	str	r10, [r0, #12]
+	str	r11, [r0, #12]
 #else
-	strd  r10, r10, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #16]
-	str	r10, [r0, #20]
+	str	r11, [r0, #20]
 #else
-	strd  r10, r10, [r0, #16]
+	strd	r10, r11, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
-	str	r10, [r0, #28]
+	str	r11, [r0, #28]
 #else
-	strd  r10, r10, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	# Set zero
 	mov	r10, #0
+	mov	r11, #0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp]
-	str	r10, [sp, #4]
+	str	r11, [sp, #4]
 #else
-	strd  r10, r10, [sp]
+	strd	r10, r11, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #8]
-	str	r10, [sp, #12]
+	str	r11, [sp, #12]
 #else
-	strd  r10, r10, [sp, #8]
+	strd	r10, r11, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #16]
-	str	r10, [sp, #20]
+	str	r11, [sp, #20]
 #else
-	strd  r10, r10, [sp, #16]
+	strd	r10, r11, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #24]
-	str	r10, [sp, #28]
+	str	r11, [sp, #28]
 #else
-	strd  r10, r10, [sp, #24]
+	strd	r10, r11, [sp, #24]
 #endif
 	# Set one
-	mov	r11, #1
+	mov	r10, #1
+	mov	r11, #0
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r10, [sp, #32]
+	str	r11, [sp, #36]
+#else
+	strd	r10, r11, [sp, #32]
+#endif
 	mov	r10, #0
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r11, [sp, #32]
-	str	r10, [sp, #36]
-#else
-	strd  r11, r10, [sp, #32]
-#endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #40]
-	str	r10, [sp, #44]
+	str	r11, [sp, #44]
 #else
-	strd  r10, r10, [sp, #40]
+	strd	r10, r11, [sp, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #48]
-	str	r10, [sp, #52]
+	str	r11, [sp, #52]
 #else
-	strd  r10, r10, [sp, #48]
+	strd	r10, r11, [sp, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #56]
-	str	r10, [sp, #60]
+	str	r11, [sp, #60]
 #else
-	strd  r10, r10, [sp, #56]
+	strd	r10, r11, [sp, #56]
 #endif
 	# Copy
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r4, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r2, #8]
 	ldr	r7, [r2, #12]
 #else
-	ldrd  r6, r7, [r2, #8]
+	ldrd	r6, r7, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [sp, #64]
 	str	r5, [sp, #68]
 #else
-	strd  r4, r5, [sp, #64]
+	strd	r4, r5, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #72]
 	str	r7, [sp, #76]
 #else
-	strd  r6, r7, [sp, #72]
+	strd	r6, r7, [sp, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r4, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r2, #24]
 	ldr	r7, [r2, #28]
 #else
-	ldrd  r6, r7, [r2, #24]
+	ldrd	r6, r7, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [sp, #80]
 	str	r5, [sp, #84]
 #else
-	strd  r4, r5, [sp, #80]
+	strd	r4, r5, [sp, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #88]
 	str	r7, [sp, #92]
 #else
-	strd  r6, r7, [sp, #88]
+	strd	r6, r7, [sp, #88]
 #endif
 	mov	r1, #30
 	str	r1, [sp, #180]
@@ -4344,13 +4349,13 @@ L_curve25519_bits:
 	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r4, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #64]
 	ldr	r7, [sp, #68]
 #else
-	ldrd  r6, r7, [sp, #64]
+	ldrd	r6, r7, [sp, #64]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4364,25 +4369,25 @@ L_curve25519_bits:
 	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #64]
 	str	r7, [sp, #68]
 #else
-	strd  r6, r7, [sp, #64]
+	strd	r6, r7, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #72]
 	ldr	r7, [sp, #76]
 #else
-	ldrd  r6, r7, [sp, #72]
+	ldrd	r6, r7, [sp, #72]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4396,25 +4401,25 @@ L_curve25519_bits:
 	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #72]
 	str	r7, [sp, #76]
 #else
-	strd  r6, r7, [sp, #72]
+	strd	r6, r7, [sp, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #80]
 	ldr	r7, [sp, #84]
 #else
-	ldrd  r6, r7, [sp, #80]
+	ldrd	r6, r7, [sp, #80]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4428,25 +4433,25 @@ L_curve25519_bits:
 	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r4, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #80]
 	str	r7, [sp, #84]
 #else
-	strd  r6, r7, [sp, #80]
+	strd	r6, r7, [sp, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #24]
 	ldr	r5, [r0, #28]
 #else
-	ldrd  r4, r5, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #88]
 	ldr	r7, [sp, #92]
 #else
-	ldrd  r6, r7, [sp, #88]
+	ldrd	r6, r7, [sp, #88]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4460,13 +4465,13 @@ L_curve25519_bits:
 	str	r4, [r0, #24]
 	str	r5, [r0, #28]
 #else
-	strd  r4, r5, [r0, #24]
+	strd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #88]
 	str	r7, [sp, #92]
 #else
-	strd  r6, r7, [sp, #88]
+	strd	r6, r7, [sp, #88]
 #endif
 	ldr	r1, [sp, #172]
 	# Conditional Swap
@@ -4475,13 +4480,13 @@ L_curve25519_bits:
 	ldr	r4, [sp]
 	ldr	r5, [sp, #4]
 #else
-	ldrd  r4, r5, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #32]
 	ldr	r7, [sp, #36]
 #else
-	ldrd  r6, r7, [sp, #32]
+	ldrd	r6, r7, [sp, #32]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4495,25 +4500,25 @@ L_curve25519_bits:
 	str	r4, [sp]
 	str	r5, [sp, #4]
 #else
-	strd  r4, r5, [sp]
+	strd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #32]
 	str	r7, [sp, #36]
 #else
-	strd  r6, r7, [sp, #32]
+	strd	r6, r7, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #8]
 	ldr	r5, [sp, #12]
 #else
-	ldrd  r4, r5, [sp, #8]
+	ldrd	r4, r5, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #40]
 	ldr	r7, [sp, #44]
 #else
-	ldrd  r6, r7, [sp, #40]
+	ldrd	r6, r7, [sp, #40]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4527,25 +4532,25 @@ L_curve25519_bits:
 	str	r4, [sp, #8]
 	str	r5, [sp, #12]
 #else
-	strd  r4, r5, [sp, #8]
+	strd	r4, r5, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #40]
 	str	r7, [sp, #44]
 #else
-	strd  r6, r7, [sp, #40]
+	strd	r6, r7, [sp, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #16]
 	ldr	r5, [sp, #20]
 #else
-	ldrd  r4, r5, [sp, #16]
+	ldrd	r4, r5, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #48]
 	ldr	r7, [sp, #52]
 #else
-	ldrd  r6, r7, [sp, #48]
+	ldrd	r6, r7, [sp, #48]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4559,25 +4564,25 @@ L_curve25519_bits:
 	str	r4, [sp, #16]
 	str	r5, [sp, #20]
 #else
-	strd  r4, r5, [sp, #16]
+	strd	r4, r5, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #48]
 	str	r7, [sp, #52]
 #else
-	strd  r6, r7, [sp, #48]
+	strd	r6, r7, [sp, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #24]
 	ldr	r5, [sp, #28]
 #else
-	ldrd  r4, r5, [sp, #24]
+	ldrd	r4, r5, [sp, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #56]
 	ldr	r7, [sp, #60]
 #else
-	ldrd  r6, r7, [sp, #56]
+	ldrd	r6, r7, [sp, #56]
 #endif
 	eor	r8, r4, r6
 	eor	r9, r5, r7
@@ -4591,13 +4596,13 @@ L_curve25519_bits:
 	str	r4, [sp, #24]
 	str	r5, [sp, #28]
 #else
-	strd  r4, r5, [sp, #24]
+	strd	r4, r5, [sp, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #56]
 	str	r7, [sp, #60]
 #else
-	strd  r6, r7, [sp, #56]
+	strd	r6, r7, [sp, #56]
 #endif
 	ldr	r1, [sp, #184]
 	str	r1, [sp, #172]
@@ -4607,13 +4612,13 @@ L_curve25519_bits:
 	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r4, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp]
 	ldr	r7, [sp, #4]
 #else
-	ldrd  r6, r7, [sp]
+	ldrd	r6, r7, [sp]
 #endif
 	adds	r8, r4, r6
 	mov	r3, #0
@@ -4623,7 +4628,7 @@ L_curve25519_bits:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
 	subs	r10, r4, r6
@@ -4634,20 +4639,20 @@ L_curve25519_bits:
 	str	r10, [sp, #128]
 	str	r11, [sp, #132]
 #else
-	strd  r10, r11, [sp, #128]
+	strd	r10, r11, [sp, #128]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #8]
 	ldr	r7, [sp, #12]
 #else
-	ldrd  r6, r7, [sp, #8]
+	ldrd	r6, r7, [sp, #8]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -4658,7 +4663,7 @@ L_curve25519_bits:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	r12, r12, #-1
@@ -4670,20 +4675,20 @@ L_curve25519_bits:
 	str	r10, [sp, #136]
 	str	r11, [sp, #140]
 #else
-	strd  r10, r11, [sp, #136]
+	strd	r10, r11, [sp, #136]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #16]
 	ldr	r7, [sp, #20]
 #else
-	ldrd  r6, r7, [sp, #16]
+	ldrd	r6, r7, [sp, #16]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -4694,7 +4699,7 @@ L_curve25519_bits:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	r12, r12, #-1
@@ -4706,20 +4711,20 @@ L_curve25519_bits:
 	str	r10, [sp, #144]
 	str	r11, [sp, #148]
 #else
-	strd  r10, r11, [sp, #144]
+	strd	r10, r11, [sp, #144]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #24]
 	ldr	r5, [r0, #28]
 #else
-	ldrd  r4, r5, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #24]
 	ldr	r7, [sp, #28]
 #else
-	ldrd  r6, r7, [sp, #24]
+	ldrd	r6, r7, [sp, #24]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -4738,7 +4743,7 @@ L_curve25519_bits:
 	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r4, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 	subs	r4, r4, r3
 	sbcs	r5, r5, r2
@@ -4746,13 +4751,13 @@ L_curve25519_bits:
 	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 	sbcs	r4, r4, r2
 	sbcs	r5, r5, r2
@@ -4760,13 +4765,13 @@ L_curve25519_bits:
 	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 	sbcs	r4, r4, r2
 	sbcs	r5, r5, r2
@@ -4774,7 +4779,7 @@ L_curve25519_bits:
 	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r4, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
 	sbcs	r8, r8, r2
 	sbc	r9, r9, r12
@@ -4782,7 +4787,7 @@ L_curve25519_bits:
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r3, #-19
 	asr	r2, r11, #31
@@ -4794,7 +4799,7 @@ L_curve25519_bits:
 	ldr	r4, [sp, #128]
 	ldr	r5, [sp, #132]
 #else
-	ldrd  r4, r5, [sp, #128]
+	ldrd	r4, r5, [sp, #128]
 #endif
 	adds	r4, r4, r3
 	adcs	r5, r5, r2
@@ -4802,13 +4807,13 @@ L_curve25519_bits:
 	str	r4, [sp, #128]
 	str	r5, [sp, #132]
 #else
-	strd  r4, r5, [sp, #128]
+	strd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #136]
 	ldr	r5, [sp, #140]
 #else
-	ldrd  r4, r5, [sp, #136]
+	ldrd	r4, r5, [sp, #136]
 #endif
 	adcs	r4, r4, r2
 	adcs	r5, r5, r2
@@ -4816,13 +4821,13 @@ L_curve25519_bits:
 	str	r4, [sp, #136]
 	str	r5, [sp, #140]
 #else
-	strd  r4, r5, [sp, #136]
+	strd	r4, r5, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #144]
 	ldr	r5, [sp, #148]
 #else
-	ldrd  r4, r5, [sp, #144]
+	ldrd	r4, r5, [sp, #144]
 #endif
 	adcs	r4, r4, r2
 	adcs	r5, r5, r2
@@ -4830,7 +4835,7 @@ L_curve25519_bits:
 	str	r4, [sp, #144]
 	str	r5, [sp, #148]
 #else
-	strd  r4, r5, [sp, #144]
+	strd	r4, r5, [sp, #144]
 #endif
 	adcs	r10, r10, r2
 	adc	r11, r11, r12
@@ -4838,7 +4843,7 @@ L_curve25519_bits:
 	str	r10, [sp, #152]
 	str	r11, [sp, #156]
 #else
-	strd  r10, r11, [sp, #152]
+	strd	r10, r11, [sp, #152]
 #endif
 	# Add-Sub
 	#  Add
@@ -4846,13 +4851,13 @@ L_curve25519_bits:
 	ldr	r4, [sp, #64]
 	ldr	r5, [sp, #68]
 #else
-	ldrd  r4, r5, [sp, #64]
+	ldrd	r4, r5, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #32]
 	ldr	r7, [sp, #36]
 #else
-	ldrd  r6, r7, [sp, #32]
+	ldrd	r6, r7, [sp, #32]
 #endif
 	adds	r8, r4, r6
 	mov	r3, #0
@@ -4862,7 +4867,7 @@ L_curve25519_bits:
 	str	r8, [sp]
 	str	r9, [sp, #4]
 #else
-	strd  r8, r9, [sp]
+	strd	r8, r9, [sp]
 #endif
 	#  Sub
 	subs	r10, r4, r6
@@ -4873,20 +4878,20 @@ L_curve25519_bits:
 	str	r10, [sp, #96]
 	str	r11, [sp, #100]
 #else
-	strd  r10, r11, [sp, #96]
+	strd	r10, r11, [sp, #96]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #72]
 	ldr	r5, [sp, #76]
 #else
-	ldrd  r4, r5, [sp, #72]
+	ldrd	r4, r5, [sp, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #40]
 	ldr	r7, [sp, #44]
 #else
-	ldrd  r6, r7, [sp, #40]
+	ldrd	r6, r7, [sp, #40]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -4897,7 +4902,7 @@ L_curve25519_bits:
 	str	r8, [sp, #8]
 	str	r9, [sp, #12]
 #else
-	strd  r8, r9, [sp, #8]
+	strd	r8, r9, [sp, #8]
 #endif
 	#  Sub
 	adds	r12, r12, #-1
@@ -4909,20 +4914,20 @@ L_curve25519_bits:
 	str	r10, [sp, #104]
 	str	r11, [sp, #108]
 #else
-	strd  r10, r11, [sp, #104]
+	strd	r10, r11, [sp, #104]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #80]
 	ldr	r5, [sp, #84]
 #else
-	ldrd  r4, r5, [sp, #80]
+	ldrd	r4, r5, [sp, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #48]
 	ldr	r7, [sp, #52]
 #else
-	ldrd  r6, r7, [sp, #48]
+	ldrd	r6, r7, [sp, #48]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -4933,7 +4938,7 @@ L_curve25519_bits:
 	str	r8, [sp, #16]
 	str	r9, [sp, #20]
 #else
-	strd  r8, r9, [sp, #16]
+	strd	r8, r9, [sp, #16]
 #endif
 	#  Sub
 	adds	r12, r12, #-1
@@ -4945,20 +4950,20 @@ L_curve25519_bits:
 	str	r10, [sp, #112]
 	str	r11, [sp, #116]
 #else
-	strd  r10, r11, [sp, #112]
+	strd	r10, r11, [sp, #112]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #88]
 	ldr	r5, [sp, #92]
 #else
-	ldrd  r4, r5, [sp, #88]
+	ldrd	r4, r5, [sp, #88]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #56]
 	ldr	r7, [sp, #60]
 #else
-	ldrd  r6, r7, [sp, #56]
+	ldrd	r6, r7, [sp, #56]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -4977,7 +4982,7 @@ L_curve25519_bits:
 	ldr	r4, [sp]
 	ldr	r5, [sp, #4]
 #else
-	ldrd  r4, r5, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 	subs	r4, r4, r3
 	sbcs	r5, r5, r2
@@ -4985,13 +4990,13 @@ L_curve25519_bits:
 	str	r4, [sp]
 	str	r5, [sp, #4]
 #else
-	strd  r4, r5, [sp]
+	strd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #8]
 	ldr	r5, [sp, #12]
 #else
-	ldrd  r4, r5, [sp, #8]
+	ldrd	r4, r5, [sp, #8]
 #endif
 	sbcs	r4, r4, r2
 	sbcs	r5, r5, r2
@@ -4999,13 +5004,13 @@ L_curve25519_bits:
 	str	r4, [sp, #8]
 	str	r5, [sp, #12]
 #else
-	strd  r4, r5, [sp, #8]
+	strd	r4, r5, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #16]
 	ldr	r5, [sp, #20]
 #else
-	ldrd  r4, r5, [sp, #16]
+	ldrd	r4, r5, [sp, #16]
 #endif
 	sbcs	r4, r4, r2
 	sbcs	r5, r5, r2
@@ -5013,7 +5018,7 @@ L_curve25519_bits:
 	str	r4, [sp, #16]
 	str	r5, [sp, #20]
 #else
-	strd  r4, r5, [sp, #16]
+	strd	r4, r5, [sp, #16]
 #endif
 	sbcs	r8, r8, r2
 	sbc	r9, r9, r12
@@ -5021,7 +5026,7 @@ L_curve25519_bits:
 	str	r8, [sp, #24]
 	str	r9, [sp, #28]
 #else
-	strd  r8, r9, [sp, #24]
+	strd	r8, r9, [sp, #24]
 #endif
 	mov	r3, #-19
 	asr	r2, r11, #31
@@ -5033,7 +5038,7 @@ L_curve25519_bits:
 	ldr	r4, [sp, #96]
 	ldr	r5, [sp, #100]
 #else
-	ldrd  r4, r5, [sp, #96]
+	ldrd	r4, r5, [sp, #96]
 #endif
 	adds	r4, r4, r3
 	adcs	r5, r5, r2
@@ -5041,13 +5046,13 @@ L_curve25519_bits:
 	str	r4, [sp, #96]
 	str	r5, [sp, #100]
 #else
-	strd  r4, r5, [sp, #96]
+	strd	r4, r5, [sp, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #104]
 	ldr	r5, [sp, #108]
 #else
-	ldrd  r4, r5, [sp, #104]
+	ldrd	r4, r5, [sp, #104]
 #endif
 	adcs	r4, r4, r2
 	adcs	r5, r5, r2
@@ -5055,13 +5060,13 @@ L_curve25519_bits:
 	str	r4, [sp, #104]
 	str	r5, [sp, #108]
 #else
-	strd  r4, r5, [sp, #104]
+	strd	r4, r5, [sp, #104]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #112]
 	ldr	r5, [sp, #116]
 #else
-	ldrd  r4, r5, [sp, #112]
+	ldrd	r4, r5, [sp, #112]
 #endif
 	adcs	r4, r4, r2
 	adcs	r5, r5, r2
@@ -5069,7 +5074,7 @@ L_curve25519_bits:
 	str	r4, [sp, #112]
 	str	r5, [sp, #116]
 #else
-	strd  r4, r5, [sp, #112]
+	strd	r4, r5, [sp, #112]
 #endif
 	adcs	r10, r10, r2
 	adc	r11, r11, r12
@@ -5077,7 +5082,7 @@ L_curve25519_bits:
 	str	r10, [sp, #120]
 	str	r11, [sp, #124]
 #else
-	strd  r10, r11, [sp, #120]
+	strd	r10, r11, [sp, #120]
 #endif
 	ldr	r2, [sp, #160]
 	add	r1, sp, #0x60
@@ -5099,13 +5104,13 @@ L_curve25519_bits:
 	ldr	r4, [sp, #32]
 	ldr	r5, [sp, #36]
 #else
-	ldrd  r4, r5, [sp, #32]
+	ldrd	r4, r5, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp]
 	ldr	r7, [sp, #4]
 #else
-	ldrd  r6, r7, [sp]
+	ldrd	r6, r7, [sp]
 #endif
 	adds	r8, r4, r6
 	mov	r3, #0
@@ -5115,7 +5120,7 @@ L_curve25519_bits:
 	str	r8, [sp, #64]
 	str	r9, [sp, #68]
 #else
-	strd  r8, r9, [sp, #64]
+	strd	r8, r9, [sp, #64]
 #endif
 	#  Sub
 	subs	r10, r4, r6
@@ -5126,20 +5131,20 @@ L_curve25519_bits:
 	str	r10, [sp]
 	str	r11, [sp, #4]
 #else
-	strd  r10, r11, [sp]
+	strd	r10, r11, [sp]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #40]
 	ldr	r5, [sp, #44]
 #else
-	ldrd  r4, r5, [sp, #40]
+	ldrd	r4, r5, [sp, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #8]
 	ldr	r7, [sp, #12]
 #else
-	ldrd  r6, r7, [sp, #8]
+	ldrd	r6, r7, [sp, #8]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -5150,7 +5155,7 @@ L_curve25519_bits:
 	str	r8, [sp, #72]
 	str	r9, [sp, #76]
 #else
-	strd  r8, r9, [sp, #72]
+	strd	r8, r9, [sp, #72]
 #endif
 	#  Sub
 	adds	r12, r12, #-1
@@ -5162,20 +5167,20 @@ L_curve25519_bits:
 	str	r10, [sp, #8]
 	str	r11, [sp, #12]
 #else
-	strd  r10, r11, [sp, #8]
+	strd	r10, r11, [sp, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #48]
 	ldr	r5, [sp, #52]
 #else
-	ldrd  r4, r5, [sp, #48]
+	ldrd	r4, r5, [sp, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #16]
 	ldr	r7, [sp, #20]
 #else
-	ldrd  r6, r7, [sp, #16]
+	ldrd	r6, r7, [sp, #16]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -5186,7 +5191,7 @@ L_curve25519_bits:
 	str	r8, [sp, #80]
 	str	r9, [sp, #84]
 #else
-	strd  r8, r9, [sp, #80]
+	strd	r8, r9, [sp, #80]
 #endif
 	#  Sub
 	adds	r12, r12, #-1
@@ -5198,20 +5203,20 @@ L_curve25519_bits:
 	str	r10, [sp, #16]
 	str	r11, [sp, #20]
 #else
-	strd  r10, r11, [sp, #16]
+	strd	r10, r11, [sp, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #56]
 	ldr	r5, [sp, #60]
 #else
-	ldrd  r4, r5, [sp, #56]
+	ldrd	r4, r5, [sp, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #24]
 	ldr	r7, [sp, #28]
 #else
-	ldrd  r6, r7, [sp, #24]
+	ldrd	r6, r7, [sp, #24]
 #endif
 	adds	r3, r3, #-1
 	adcs	r8, r4, r6
@@ -5230,7 +5235,7 @@ L_curve25519_bits:
 	ldr	r4, [sp, #64]
 	ldr	r5, [sp, #68]
 #else
-	ldrd  r4, r5, [sp, #64]
+	ldrd	r4, r5, [sp, #64]
 #endif
 	subs	r4, r4, r3
 	sbcs	r5, r5, r2
@@ -5238,13 +5243,13 @@ L_curve25519_bits:
 	str	r4, [sp, #64]
 	str	r5, [sp, #68]
 #else
-	strd  r4, r5, [sp, #64]
+	strd	r4, r5, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #72]
 	ldr	r5, [sp, #76]
 #else
-	ldrd  r4, r5, [sp, #72]
+	ldrd	r4, r5, [sp, #72]
 #endif
 	sbcs	r4, r4, r2
 	sbcs	r5, r5, r2
@@ -5252,13 +5257,13 @@ L_curve25519_bits:
 	str	r4, [sp, #72]
 	str	r5, [sp, #76]
 #else
-	strd  r4, r5, [sp, #72]
+	strd	r4, r5, [sp, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #80]
 	ldr	r5, [sp, #84]
 #else
-	ldrd  r4, r5, [sp, #80]
+	ldrd	r4, r5, [sp, #80]
 #endif
 	sbcs	r4, r4, r2
 	sbcs	r5, r5, r2
@@ -5266,7 +5271,7 @@ L_curve25519_bits:
 	str	r4, [sp, #80]
 	str	r5, [sp, #84]
 #else
-	strd  r4, r5, [sp, #80]
+	strd	r4, r5, [sp, #80]
 #endif
 	sbcs	r8, r8, r2
 	sbc	r9, r9, r12
@@ -5274,7 +5279,7 @@ L_curve25519_bits:
 	str	r8, [sp, #88]
 	str	r9, [sp, #92]
 #else
-	strd  r8, r9, [sp, #88]
+	strd	r8, r9, [sp, #88]
 #endif
 	mov	r3, #-19
 	asr	r2, r11, #31
@@ -5286,7 +5291,7 @@ L_curve25519_bits:
 	ldr	r4, [sp]
 	ldr	r5, [sp, #4]
 #else
-	ldrd  r4, r5, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 	adds	r4, r4, r3
 	adcs	r5, r5, r2
@@ -5294,13 +5299,13 @@ L_curve25519_bits:
 	str	r4, [sp]
 	str	r5, [sp, #4]
 #else
-	strd  r4, r5, [sp]
+	strd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #8]
 	ldr	r5, [sp, #12]
 #else
-	ldrd  r4, r5, [sp, #8]
+	ldrd	r4, r5, [sp, #8]
 #endif
 	adcs	r4, r4, r2
 	adcs	r5, r5, r2
@@ -5308,13 +5313,13 @@ L_curve25519_bits:
 	str	r4, [sp, #8]
 	str	r5, [sp, #12]
 #else
-	strd  r4, r5, [sp, #8]
+	strd	r4, r5, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #16]
 	ldr	r5, [sp, #20]
 #else
-	ldrd  r4, r5, [sp, #16]
+	ldrd	r4, r5, [sp, #16]
 #endif
 	adcs	r4, r4, r2
 	adcs	r5, r5, r2
@@ -5322,7 +5327,7 @@ L_curve25519_bits:
 	str	r4, [sp, #16]
 	str	r5, [sp, #20]
 #else
-	strd  r4, r5, [sp, #16]
+	strd	r4, r5, [sp, #16]
 #endif
 	adcs	r10, r10, r2
 	adc	r11, r11, r12
@@ -5330,7 +5335,7 @@ L_curve25519_bits:
 	str	r10, [sp, #24]
 	str	r11, [sp, #28]
 #else
-	strd  r10, r11, [sp, #24]
+	strd	r10, r11, [sp, #24]
 #endif
 	add	r2, sp, #0x60
 	add	r1, sp, #0x80
@@ -5341,25 +5346,25 @@ L_curve25519_bits:
 	ldr	r4, [sp, #128]
 	ldr	r5, [sp, #132]
 #else
-	ldrd  r4, r5, [sp, #128]
+	ldrd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #136]
 	ldr	r7, [sp, #140]
 #else
-	ldrd  r6, r7, [sp, #136]
+	ldrd	r6, r7, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #96]
 	ldr	r9, [sp, #100]
 #else
-	ldrd  r8, r9, [sp, #96]
+	ldrd	r8, r9, [sp, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #104]
 	ldr	r11, [sp, #108]
 #else
-	ldrd  r10, r11, [sp, #104]
+	ldrd	r10, r11, [sp, #104]
 #endif
 	subs	r8, r4, r8
 	sbcs	r9, r5, r9
@@ -5369,37 +5374,37 @@ L_curve25519_bits:
 	str	r8, [sp, #128]
 	str	r9, [sp, #132]
 #else
-	strd  r8, r9, [sp, #128]
+	strd	r8, r9, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #136]
 	str	r11, [sp, #140]
 #else
-	strd  r10, r11, [sp, #136]
+	strd	r10, r11, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #144]
 	ldr	r5, [sp, #148]
 #else
-	ldrd  r4, r5, [sp, #144]
+	ldrd	r4, r5, [sp, #144]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #152]
 	ldr	r7, [sp, #156]
 #else
-	ldrd  r6, r7, [sp, #152]
+	ldrd	r6, r7, [sp, #152]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #112]
 	ldr	r9, [sp, #116]
 #else
-	ldrd  r8, r9, [sp, #112]
+	ldrd	r8, r9, [sp, #112]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #120]
 	ldr	r11, [sp, #124]
 #else
-	ldrd  r10, r11, [sp, #120]
+	ldrd	r10, r11, [sp, #120]
 #endif
 	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
@@ -5415,13 +5420,13 @@ L_curve25519_bits:
 	ldr	r4, [sp, #128]
 	ldr	r5, [sp, #132]
 #else
-	ldrd  r4, r5, [sp, #128]
+	ldrd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #136]
 	ldr	r7, [sp, #140]
 #else
-	ldrd  r6, r7, [sp, #136]
+	ldrd	r6, r7, [sp, #136]
 #endif
 	adds	r4, r4, r3
 	adcs	r5, r5, r2
@@ -5435,25 +5440,25 @@ L_curve25519_bits:
 	str	r4, [sp, #128]
 	str	r5, [sp, #132]
 #else
-	strd  r4, r5, [sp, #128]
+	strd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #136]
 	str	r7, [sp, #140]
 #else
-	strd  r6, r7, [sp, #136]
+	strd	r6, r7, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [sp, #144]
 	str	r9, [sp, #148]
 #else
-	strd  r8, r9, [sp, #144]
+	strd	r8, r9, [sp, #144]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #152]
 	str	r11, [sp, #156]
 #else
-	strd  r10, r11, [sp, #152]
+	strd	r10, r11, [sp, #152]
 #endif
 	add	r1, sp, #0
 	add	r0, sp, #0
@@ -5463,25 +5468,25 @@ L_curve25519_bits:
 	ldr	r4, [sp, #128]
 	ldr	r5, [sp, #132]
 #else
-	ldrd  r4, r5, [sp, #128]
+	ldrd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #136]
 	ldr	r7, [sp, #140]
 #else
-	ldrd  r6, r7, [sp, #136]
+	ldrd	r6, r7, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #144]
 	ldr	r9, [sp, #148]
 #else
-	ldrd  r8, r9, [sp, #144]
+	ldrd	r8, r9, [sp, #144]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #152]
 	ldr	r11, [sp, #156]
 #else
-	ldrd  r10, r11, [sp, #152]
+	ldrd	r10, r11, [sp, #152]
 #endif
 	movw	r12, #0xdb42
 	movt	r12, #1
@@ -5524,25 +5529,25 @@ L_curve25519_bits:
 	str	r4, [sp, #32]
 	str	r5, [sp, #36]
 #else
-	strd  r4, r5, [sp, #32]
+	strd	r4, r5, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #40]
 	str	r7, [sp, #44]
 #else
-	strd  r6, r7, [sp, #40]
+	strd	r6, r7, [sp, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [sp, #48]
 	str	r9, [sp, #52]
 #else
-	strd  r8, r9, [sp, #48]
+	strd	r8, r9, [sp, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #56]
 	str	r11, [sp, #60]
 #else
-	strd  r10, r11, [sp, #56]
+	strd	r10, r11, [sp, #56]
 #endif
 	add	r1, sp, #0x40
 	add	r0, sp, #0x40
@@ -5552,25 +5557,25 @@ L_curve25519_bits:
 	ldr	r4, [sp, #96]
 	ldr	r5, [sp, #100]
 #else
-	ldrd  r4, r5, [sp, #96]
+	ldrd	r4, r5, [sp, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #104]
 	ldr	r7, [sp, #108]
 #else
-	ldrd  r6, r7, [sp, #104]
+	ldrd	r6, r7, [sp, #104]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #32]
 	ldr	r9, [sp, #36]
 #else
-	ldrd  r8, r9, [sp, #32]
+	ldrd	r8, r9, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #40]
 	ldr	r11, [sp, #44]
 #else
-	ldrd  r10, r11, [sp, #40]
+	ldrd	r10, r11, [sp, #40]
 #endif
 	adds	r8, r4, r8
 	adcs	r9, r5, r9
@@ -5580,37 +5585,37 @@ L_curve25519_bits:
 	str	r8, [sp, #96]
 	str	r9, [sp, #100]
 #else
-	strd  r8, r9, [sp, #96]
+	strd	r8, r9, [sp, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #104]
 	str	r11, [sp, #108]
 #else
-	strd  r10, r11, [sp, #104]
+	strd	r10, r11, [sp, #104]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [sp, #112]
 	ldr	r5, [sp, #116]
 #else
-	ldrd  r4, r5, [sp, #112]
+	ldrd	r4, r5, [sp, #112]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #120]
 	ldr	r7, [sp, #124]
 #else
-	ldrd  r6, r7, [sp, #120]
+	ldrd	r6, r7, [sp, #120]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [sp, #48]
 	ldr	r9, [sp, #52]
 #else
-	ldrd  r8, r9, [sp, #48]
+	ldrd	r8, r9, [sp, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [sp, #56]
 	ldr	r11, [sp, #60]
 #else
-	ldrd  r10, r11, [sp, #56]
+	ldrd	r10, r11, [sp, #56]
 #endif
 	adcs	r8, r4, r8
 	adcs	r9, r5, r9
@@ -5626,13 +5631,13 @@ L_curve25519_bits:
 	ldr	r4, [sp, #96]
 	ldr	r5, [sp, #100]
 #else
-	ldrd  r4, r5, [sp, #96]
+	ldrd	r4, r5, [sp, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [sp, #104]
 	ldr	r7, [sp, #108]
 #else
-	ldrd  r6, r7, [sp, #104]
+	ldrd	r6, r7, [sp, #104]
 #endif
 	subs	r4, r4, r3
 	sbcs	r5, r5, r2
@@ -5646,25 +5651,25 @@ L_curve25519_bits:
 	str	r4, [sp, #96]
 	str	r5, [sp, #100]
 #else
-	strd  r4, r5, [sp, #96]
+	strd	r4, r5, [sp, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [sp, #104]
 	str	r7, [sp, #108]
 #else
-	strd  r6, r7, [sp, #104]
+	strd	r6, r7, [sp, #104]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [sp, #112]
 	str	r9, [sp, #116]
 #else
-	strd  r8, r9, [sp, #112]
+	strd	r8, r9, [sp, #112]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [sp, #120]
 	str	r11, [sp, #124]
 #else
-	strd  r10, r11, [sp, #120]
+	strd	r10, r11, [sp, #120]
 #endif
 	add	r2, sp, #0
 	ldr	r1, [sp, #168]
@@ -5829,7 +5834,7 @@ L_curve25519_inv_8:
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	curve25519,.-curve25519
 	.text
-	.align	2
+	.align	4
 	.globl	fe_pow22523
 	.type	fe_pow22523, %function
 fe_pow22523:
@@ -5979,7 +5984,7 @@ L_fe_pow22523_8:
 	pop	{r4, pc}
 	.size	fe_pow22523,.-fe_pow22523
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_to_p2
 	.type	fe_ge_to_p2, %function
 fe_ge_to_p2:
@@ -6005,7 +6010,7 @@ fe_ge_to_p2:
 	pop	{pc}
 	.size	fe_ge_to_p2,.-fe_ge_to_p2
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_to_p3
 	.type	fe_ge_to_p3, %function
 fe_ge_to_p3:
@@ -6035,7 +6040,7 @@ fe_ge_to_p3:
 	pop	{pc}
 	.size	fe_ge_to_p3,.-fe_ge_to_p3
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_dbl
 	.type	fe_ge_dbl, %function
 fe_ge_dbl:
@@ -6056,30 +6061,30 @@ fe_ge_dbl:
 	ldr	r2, [sp, #56]
 	# Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	adds	r8, r3, r8
+	adds	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adcs	r11, r7, r11
@@ -6087,91 +6092,91 @@ fe_ge_dbl:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	adcs	r8, r3, r8
+	adcs	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r1, [sp, #4]
 	ldr	r0, [sp, #12]
@@ -6182,18 +6187,18 @@ fe_ge_dbl:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r2]
 	ldr	r7, [r2, #4]
 #else
-	ldrd  r6, r7, [r2]
+	ldrd	r6, r7, [r2]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -6201,10 +6206,10 @@ fe_ge_dbl:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -6212,23 +6217,23 @@ fe_ge_dbl:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r2, #8]
 	ldr	r7, [r2, #12]
 #else
-	ldrd  r6, r7, [r2, #8]
+	ldrd	r6, r7, [r2, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -6236,11 +6241,11 @@ fe_ge_dbl:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -6248,23 +6253,23 @@ fe_ge_dbl:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r2, #16]
 	ldr	r7, [r2, #20]
 #else
-	ldrd  r6, r7, [r2, #16]
+	ldrd	r6, r7, [r2, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -6272,11 +6277,11 @@ fe_ge_dbl:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -6284,169 +6289,169 @@ fe_ge_dbl:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #24]
+	ldr	r4, [r1, #24]
 	ldr	r5, [r1, #28]
 #else
-	ldrd  r3, r5, [r1, #24]
+	ldrd	r4, r5, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r2, #24]
 	ldr	r7, [r2, #28]
 #else
-	ldrd  r6, r7, [r2, #24]
+	ldrd	r6, r7, [r2, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	ldr	r0, [sp]
 	ldr	r1, [sp, #12]
 	ldr	r2, [sp, #4]
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	subs	r8, r3, r8
+	subs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbcs	r11, r7, r11
@@ -6454,91 +6459,91 @@ fe_ge_dbl:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	sbcs	r8, r3, r8
+	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
-	adcs	r6, r6, r4
-	adcs	r7, r7, r4
-	adcs	r8, r8, r4
-	adcs	r9, r9, r4
-	adcs	r10, r10, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
+	adcs	r6, r6, r3
+	adcs	r7, r7, r3
+	adcs	r8, r8, r3
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r1, [sp, #60]
 	ldr	r0, [sp, #12]
@@ -6547,30 +6552,30 @@ fe_ge_dbl:
 	ldr	r1, [sp, #8]
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1]
 	ldr	r9, [r1, #4]
 #else
-	ldrd  r8, r9, [r1]
+	ldrd	r8, r9, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r1, #8]
 	ldr	r11, [r1, #12]
 #else
-	ldrd  r10, r11, [r1, #8]
+	ldrd	r10, r11, [r1, #8]
 #endif
-	subs	r8, r3, r8
+	subs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbcs	r11, r7, r11
@@ -6578,97 +6583,97 @@ fe_ge_dbl:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1, #16]
 	ldr	r9, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r1, #24]
 	ldr	r11, [r1, #28]
 #else
-	ldrd  r10, r11, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	sbcs	r8, r3, r8
+	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
-	adcs	r6, r6, r4
-	adcs	r7, r7, r4
-	adcs	r8, r8, r4
-	adcs	r9, r9, r4
-	adcs	r10, r10, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
+	adcs	r6, r6, r3
+	adcs	r7, r7, r3
+	adcs	r8, r8, r3
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	add	sp, sp, #16
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_ge_dbl,.-fe_ge_dbl
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_madd
 	.type	fe_ge_madd, %function
 fe_ge_madd:
@@ -6683,30 +6688,30 @@ fe_ge_madd:
 	ldr	r2, [sp, #68]
 	# Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	adds	r8, r3, r8
+	adds	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adcs	r11, r7, r11
@@ -6714,121 +6719,121 @@ fe_ge_madd:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	adcs	r8, r3, r8
+	adcs	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #4]
 	ldr	r1, [sp, #72]
 	ldr	r2, [sp, #68]
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	subs	r8, r3, r8
+	subs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbcs	r11, r7, r11
@@ -6836,91 +6841,91 @@ fe_ge_madd:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	sbcs	r8, r3, r8
+	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
-	adcs	r6, r6, r4
-	adcs	r7, r7, r4
-	adcs	r8, r8, r4
-	adcs	r9, r9, r4
-	adcs	r10, r10, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
+	adcs	r6, r6, r3
+	adcs	r7, r7, r3
+	adcs	r8, r8, r3
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r2, [sp, #88]
 	ldr	r1, [sp]
@@ -6940,18 +6945,18 @@ fe_ge_madd:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2]
+	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r3, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r6, r7, [r0]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -6959,10 +6964,10 @@ fe_ge_madd:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -6970,23 +6975,23 @@ fe_ge_madd:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #8]
+	ldr	r4, [r2, #8]
 	ldr	r5, [r2, #12]
 #else
-	ldrd  r3, r5, [r2, #8]
+	ldrd	r4, r5, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -6994,11 +6999,11 @@ fe_ge_madd:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7006,23 +7011,23 @@ fe_ge_madd:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #16]
+	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r3, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7030,11 +7035,11 @@ fe_ge_madd:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7042,168 +7047,168 @@ fe_ge_madd:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #24]
+	ldr	r4, [r2, #24]
 	ldr	r5, [r2, #28]
 #else
-	ldrd  r3, r5, [r2, #24]
+	ldrd	r4, r5, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	ldr	r0, [sp, #8]
 	ldr	r1, [sp, #76]
 	# Double
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1, #16]
 	ldr	r9, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r1, #24]
 	ldr	r11, [r1, #28]
 #else
-	ldrd  r10, r11, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	adds	r3, r3, r3
+	adds	r4, r4, r4
 	adcs	r5, r5, r5
 	adcs	r6, r6, r6
 	adcs	r7, r7, r7
@@ -7212,60 +7217,60 @@ fe_ge_madd:
 	adcs	r10, r10, r10
 	adc	r11, r11, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #8]
 	ldr	r1, [sp, #12]
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1]
 	ldr	r7, [r1, #4]
 #else
-	ldrd  r6, r7, [r1]
+	ldrd	r6, r7, [r1]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7273,10 +7278,10 @@ fe_ge_madd:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7284,23 +7289,23 @@ fe_ge_madd:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7308,11 +7313,11 @@ fe_ge_madd:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7320,23 +7325,23 @@ fe_ge_madd:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #16]
 	ldr	r7, [r1, #20]
 #else
-	ldrd  r6, r7, [r1, #16]
+	ldrd	r6, r7, [r1, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7344,11 +7349,11 @@ fe_ge_madd:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7356,145 +7361,145 @@ fe_ge_madd:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #24]
+	ldr	r4, [r0, #24]
 	ldr	r5, [r0, #28]
 #else
-	ldrd  r3, r5, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	add	sp, sp, #32
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_ge_madd,.-fe_ge_madd
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_msub
 	.type	fe_ge_msub, %function
 fe_ge_msub:
@@ -7509,30 +7514,30 @@ fe_ge_msub:
 	ldr	r2, [sp, #68]
 	# Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	adds	r8, r3, r8
+	adds	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adcs	r11, r7, r11
@@ -7540,121 +7545,121 @@ fe_ge_msub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	adcs	r8, r3, r8
+	adcs	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #4]
 	ldr	r1, [sp, #72]
 	ldr	r2, [sp, #68]
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	subs	r8, r3, r8
+	subs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbcs	r11, r7, r11
@@ -7662,91 +7667,91 @@ fe_ge_msub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	sbcs	r8, r3, r8
+	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
-	adcs	r6, r6, r4
-	adcs	r7, r7, r4
-	adcs	r8, r8, r4
-	adcs	r9, r9, r4
-	adcs	r10, r10, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
+	adcs	r6, r6, r3
+	adcs	r7, r7, r3
+	adcs	r8, r8, r3
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r2, [sp, #92]
 	ldr	r1, [sp]
@@ -7766,18 +7771,18 @@ fe_ge_msub:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2]
+	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r3, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r6, r7, [r0]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7785,10 +7790,10 @@ fe_ge_msub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7796,23 +7801,23 @@ fe_ge_msub:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #8]
+	ldr	r4, [r2, #8]
 	ldr	r5, [r2, #12]
 #else
-	ldrd  r3, r5, [r2, #8]
+	ldrd	r4, r5, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7820,11 +7825,11 @@ fe_ge_msub:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7832,23 +7837,23 @@ fe_ge_msub:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #16]
+	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r3, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -7856,11 +7861,11 @@ fe_ge_msub:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -7868,168 +7873,168 @@ fe_ge_msub:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #24]
+	ldr	r4, [r2, #24]
 	ldr	r5, [r2, #28]
 #else
-	ldrd  r3, r5, [r2, #24]
+	ldrd	r4, r5, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	ldr	r0, [sp, #8]
 	ldr	r1, [sp, #76]
 	# Double
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1, #16]
 	ldr	r9, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r1, #24]
 	ldr	r11, [r1, #28]
 #else
-	ldrd  r10, r11, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	adds	r3, r3, r3
+	adds	r4, r4, r4
 	adcs	r5, r5, r5
 	adcs	r6, r6, r6
 	adcs	r7, r7, r7
@@ -8038,60 +8043,60 @@ fe_ge_msub:
 	adcs	r10, r10, r10
 	adc	r11, r11, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #12]
 	ldr	r1, [sp, #8]
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r6, r7, [r0]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8099,10 +8104,10 @@ fe_ge_msub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8110,23 +8115,23 @@ fe_ge_msub:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8134,11 +8139,11 @@ fe_ge_msub:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8146,23 +8151,23 @@ fe_ge_msub:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8170,11 +8175,11 @@ fe_ge_msub:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8182,145 +8187,145 @@ fe_ge_msub:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #24]
+	ldr	r4, [r1, #24]
 	ldr	r5, [r1, #28]
 #else
-	ldrd  r3, r5, [r1, #24]
+	ldrd	r4, r5, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	add	sp, sp, #32
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_ge_msub,.-fe_ge_msub
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_add
 	.type	fe_ge_add, %function
 fe_ge_add:
@@ -8335,30 +8340,30 @@ fe_ge_add:
 	ldr	r2, [sp, #132]
 	# Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	adds	r8, r3, r8
+	adds	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adcs	r11, r7, r11
@@ -8366,121 +8371,121 @@ fe_ge_add:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	adcs	r8, r3, r8
+	adcs	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #4]
 	ldr	r1, [sp, #136]
 	ldr	r2, [sp, #132]
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	subs	r8, r3, r8
+	subs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbcs	r11, r7, r11
@@ -8488,91 +8493,91 @@ fe_ge_add:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	sbcs	r8, r3, r8
+	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
-	adcs	r6, r6, r4
-	adcs	r7, r7, r4
-	adcs	r8, r8, r4
-	adcs	r9, r9, r4
-	adcs	r10, r10, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
+	adcs	r6, r6, r3
+	adcs	r7, r7, r3
+	adcs	r8, r8, r3
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r2, [sp, #156]
 	ldr	r1, [sp]
@@ -8594,30 +8599,30 @@ fe_ge_add:
 	ldr	r1, [sp]
 	# Double
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1, #16]
 	ldr	r9, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r1, #24]
 	ldr	r11, [r1, #28]
 #else
-	ldrd  r10, r11, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	adds	r3, r3, r3
+	adds	r4, r4, r4
 	adcs	r5, r5, r5
 	adcs	r6, r6, r6
 	adcs	r7, r7, r7
@@ -8626,42 +8631,42 @@ fe_ge_add:
 	adcs	r10, r10, r10
 	adc	r11, r11, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #4]
 	ldr	r1, [sp]
@@ -8669,18 +8674,18 @@ fe_ge_add:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2]
+	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r3, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r6, r7, [r0]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8688,10 +8693,10 @@ fe_ge_add:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8699,23 +8704,23 @@ fe_ge_add:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #8]
+	ldr	r4, [r2, #8]
 	ldr	r5, [r2, #12]
 #else
-	ldrd  r3, r5, [r2, #8]
+	ldrd	r4, r5, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8723,11 +8728,11 @@ fe_ge_add:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8735,23 +8740,23 @@ fe_ge_add:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #16]
+	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r3, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8759,11 +8764,11 @@ fe_ge_add:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8771,139 +8776,139 @@ fe_ge_add:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #24]
+	ldr	r4, [r2, #24]
 	ldr	r5, [r2, #28]
 #else
-	ldrd  r3, r5, [r2, #24]
+	ldrd	r4, r5, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	ldr	r0, [sp, #8]
 	ldr	r1, [sp, #12]
@@ -8911,18 +8916,18 @@ fe_ge_add:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2]
+	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r3, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1]
 	ldr	r7, [r1, #4]
 #else
-	ldrd  r6, r7, [r1]
+	ldrd	r6, r7, [r1]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8930,10 +8935,10 @@ fe_ge_add:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8941,23 +8946,23 @@ fe_ge_add:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #8]
+	ldr	r4, [r2, #8]
 	ldr	r5, [r2, #12]
 #else
-	ldrd  r3, r5, [r2, #8]
+	ldrd	r4, r5, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -8965,11 +8970,11 @@ fe_ge_add:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -8977,23 +8982,23 @@ fe_ge_add:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #16]
+	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r3, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #16]
 	ldr	r7, [r1, #20]
 #else
-	ldrd  r6, r7, [r1, #16]
+	ldrd	r6, r7, [r1, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9001,11 +9006,11 @@ fe_ge_add:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9013,145 +9018,145 @@ fe_ge_add:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #24]
+	ldr	r4, [r2, #24]
 	ldr	r5, [r2, #28]
 #else
-	ldrd  r3, r5, [r2, #24]
+	ldrd	r4, r5, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	add	sp, sp, #0x60
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 	.size	fe_ge_add,.-fe_ge_add
 	.text
-	.align	2
+	.align	4
 	.globl	fe_ge_sub
 	.type	fe_ge_sub, %function
 fe_ge_sub:
@@ -9166,30 +9171,30 @@ fe_ge_sub:
 	ldr	r2, [sp, #132]
 	# Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	adds	r8, r3, r8
+	adds	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adcs	r11, r7, r11
@@ -9197,121 +9202,121 @@ fe_ge_sub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	adcs	r8, r3, r8
+	adcs	r8, r4, r8
 	adcs	r9, r5, r9
 	adcs	r10, r6, r10
 	adc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #4]
 	ldr	r1, [sp, #136]
 	ldr	r2, [sp, #132]
 	# Sub
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2]
 	ldr	r9, [r2, #4]
 #else
-	ldrd  r8, r9, [r2]
+	ldrd	r8, r9, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #8]
 	ldr	r11, [r2, #12]
 #else
-	ldrd  r10, r11, [r2, #8]
+	ldrd	r10, r11, [r2, #8]
 #endif
-	subs	r8, r3, r8
+	subs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbcs	r11, r7, r11
@@ -9319,91 +9324,91 @@ fe_ge_sub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #8]
 	str	r11, [r0, #12]
 #else
-	strd  r10, r11, [r0, #8]
+	strd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #24]
 	ldr	r7, [r1, #28]
 #else
-	ldrd  r6, r7, [r1, #24]
+	ldrd	r6, r7, [r1, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r2, #16]
 	ldr	r9, [r2, #20]
 #else
-	ldrd  r8, r9, [r2, #16]
+	ldrd	r8, r9, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r2, #24]
 	ldr	r11, [r2, #28]
 #else
-	ldrd  r10, r11, [r2, #24]
+	ldrd	r10, r11, [r2, #24]
 #endif
-	sbcs	r8, r3, r8
+	sbcs	r8, r4, r8
 	sbcs	r9, r5, r9
 	sbcs	r10, r6, r10
 	sbc	r11, r7, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
-	adcs	r6, r6, r4
-	adcs	r7, r7, r4
-	adcs	r8, r8, r4
-	adcs	r9, r9, r4
-	adcs	r10, r10, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
+	adcs	r6, r6, r3
+	adcs	r7, r7, r3
+	adcs	r8, r8, r3
+	adcs	r9, r9, r3
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r2, [sp, #160]
 	ldr	r1, [sp]
@@ -9425,30 +9430,30 @@ fe_ge_sub:
 	ldr	r1, [sp]
 	# Double
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r1, #8]
 	ldr	r7, [r1, #12]
 #else
-	ldrd  r6, r7, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r1, #16]
 	ldr	r9, [r1, #20]
 #else
-	ldrd  r8, r9, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r10, [r1, #24]
 	ldr	r11, [r1, #28]
 #else
-	ldrd  r10, r11, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	adds	r3, r3, r3
+	adds	r4, r4, r4
 	adcs	r5, r5, r5
 	adcs	r6, r6, r6
 	adcs	r7, r7, r7
@@ -9457,42 +9462,42 @@ fe_ge_sub:
 	adcs	r10, r10, r10
 	adc	r11, r11, r11
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
-	sbcs	r6, r6, r4
-	sbcs	r7, r7, r4
-	sbcs	r8, r8, r4
-	sbcs	r9, r9, r4
-	sbcs	r10, r10, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
+	sbcs	r6, r6, r3
+	sbcs	r7, r7, r3
+	sbcs	r8, r8, r3
+	sbcs	r9, r9, r3
+	sbcs	r10, r10, r3
 	sbc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r0, #24]
 	str	r11, [r0, #28]
 #else
-	strd  r10, r11, [r0, #24]
+	strd	r10, r11, [r0, #24]
 #endif
 	ldr	r0, [sp, #4]
 	ldr	r1, [sp]
@@ -9500,18 +9505,18 @@ fe_ge_sub:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2]
+	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r3, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r6, r7, [r0]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9519,10 +9524,10 @@ fe_ge_sub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9530,23 +9535,23 @@ fe_ge_sub:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #8]
+	ldr	r4, [r2, #8]
 	ldr	r5, [r2, #12]
 #else
-	ldrd  r3, r5, [r2, #8]
+	ldrd	r4, r5, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9554,11 +9559,11 @@ fe_ge_sub:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9566,23 +9571,23 @@ fe_ge_sub:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #16]
+	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r3, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9590,11 +9595,11 @@ fe_ge_sub:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9602,139 +9607,139 @@ fe_ge_sub:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #24]
+	ldr	r4, [r2, #24]
 	ldr	r5, [r2, #28]
 #else
-	ldrd  r3, r5, [r2, #24]
+	ldrd	r4, r5, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	ldr	r0, [sp, #12]
 	ldr	r1, [sp, #8]
@@ -9742,18 +9747,18 @@ fe_ge_sub:
 	# Add-Sub
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2]
+	ldr	r4, [r2]
 	ldr	r5, [r2, #4]
 #else
-	ldrd  r3, r5, [r2]
+	ldrd	r4, r5, [r2]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r6, r7, [r0]
 #endif
-	adds	r8, r3, r6
+	adds	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9761,10 +9766,10 @@ fe_ge_sub:
 	str	r8, [r0]
 	str	r9, [r0, #4]
 #else
-	strd  r8, r9, [r0]
+	strd	r8, r9, [r0]
 #endif
 	#  Sub
-	subs	r10, r3, r6
+	subs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9772,23 +9777,23 @@ fe_ge_sub:
 	str	r10, [r1]
 	str	r11, [r1, #4]
 #else
-	strd  r10, r11, [r1]
+	strd	r10, r11, [r1]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #8]
+	ldr	r4, [r2, #8]
 	ldr	r5, [r2, #12]
 #else
-	ldrd  r3, r5, [r2, #8]
+	ldrd	r4, r5, [r2, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9796,11 +9801,11 @@ fe_ge_sub:
 	str	r8, [r0, #8]
 	str	r9, [r0, #12]
 #else
-	strd  r8, r9, [r0, #8]
+	strd	r8, r9, [r0, #8]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9808,23 +9813,23 @@ fe_ge_sub:
 	str	r10, [r1, #8]
 	str	r11, [r1, #12]
 #else
-	strd  r10, r11, [r1, #8]
+	strd	r10, r11, [r1, #8]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #16]
+	ldr	r4, [r2, #16]
 	ldr	r5, [r2, #20]
 #else
-	ldrd  r3, r5, [r2, #16]
+	ldrd	r4, r5, [r2, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	mov	r12, #0
 	adcs	r9, r5, r7
 	adc	r12, r12, #0
@@ -9832,11 +9837,11 @@ fe_ge_sub:
 	str	r8, [r0, #16]
 	str	r9, [r0, #20]
 #else
-	strd  r8, r9, [r0, #16]
+	strd	r8, r9, [r0, #16]
 #endif
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	mov	lr, #0
 	sbcs	r11, r5, r7
 	adc	lr, lr, #0
@@ -9844,139 +9849,139 @@ fe_ge_sub:
 	str	r10, [r1, #16]
 	str	r11, [r1, #20]
 #else
-	strd  r10, r11, [r1, #16]
+	strd	r10, r11, [r1, #16]
 #endif
 	#  Add
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r2, #24]
+	ldr	r4, [r2, #24]
 	ldr	r5, [r2, #28]
 #else
-	ldrd  r3, r5, [r2, #24]
+	ldrd	r4, r5, [r2, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 	adds	r12, r12, #-1
-	adcs	r8, r3, r6
+	adcs	r8, r4, r6
 	adc	r9, r5, r7
 	#  Sub
 	adds	lr, lr, #-1
-	sbcs	r10, r3, r6
+	sbcs	r10, r4, r6
 	sbc	r11, r5, r7
 	mov	r12, #-19
-	asr	r4, r9, #31
+	asr	r3, r9, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Sub modulus (if overflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0]
+	ldr	r4, [r0]
 	ldr	r5, [r0, #4]
 #else
-	ldrd  r3, r5, [r0]
+	ldrd	r4, r5, [r0]
 #endif
-	subs	r3, r3, r12
-	sbcs	r5, r5, r4
+	subs	r4, r4, r12
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0]
+	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r3, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #8]
+	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r3, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #8]
+	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r3, r5, [r0, #8]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r0, #16]
+	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r3, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	sbcs	r3, r3, r4
-	sbcs	r5, r5, r4
+	sbcs	r4, r4, r3
+	sbcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r0, #16]
+	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r3, r5, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
-	sbcs	r8, r8, r4
+	sbcs	r8, r8, r3
 	sbc	r9, r9, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r8, [r0, #24]
 	str	r9, [r0, #28]
 #else
-	strd  r8, r9, [r0, #24]
+	strd	r8, r9, [r0, #24]
 #endif
 	mov	r12, #-19
-	asr	r4, r11, #31
+	asr	r3, r11, #31
 	#   Mask the modulus
-	and	r12, r4, r12
-	and	lr, r4, #0x7fffffff
+	and	r12, r3, r12
+	and	lr, r3, #0x7fffffff
 	#   Add modulus (if underflow)
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1]
+	ldr	r4, [r1]
 	ldr	r5, [r1, #4]
 #else
-	ldrd  r3, r5, [r1]
+	ldrd	r4, r5, [r1]
 #endif
-	adds	r3, r3, r12
-	adcs	r5, r5, r4
+	adds	r4, r4, r12
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1]
+	str	r4, [r1]
 	str	r5, [r1, #4]
 #else
-	strd  r3, r5, [r1]
+	strd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #8]
+	ldr	r4, [r1, #8]
 	ldr	r5, [r1, #12]
 #else
-	ldrd  r3, r5, [r1, #8]
+	ldrd	r4, r5, [r1, #8]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #8]
+	str	r4, [r1, #8]
 	str	r5, [r1, #12]
 #else
-	strd  r3, r5, [r1, #8]
+	strd	r4, r5, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r3, [r1, #16]
+	ldr	r4, [r1, #16]
 	ldr	r5, [r1, #20]
 #else
-	ldrd  r3, r5, [r1, #16]
+	ldrd	r4, r5, [r1, #16]
 #endif
-	adcs	r3, r3, r4
-	adcs	r5, r5, r4
+	adcs	r4, r4, r3
+	adcs	r5, r5, r3
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r3, [r1, #16]
+	str	r4, [r1, #16]
 	str	r5, [r1, #20]
 #else
-	strd  r3, r5, [r1, #16]
+	strd	r4, r5, [r1, #16]
 #endif
-	adcs	r10, r10, r4
+	adcs	r10, r10, r3
 	adc	r11, r11, lr
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r10, [r1, #24]
 	str	r11, [r1, #28]
 #else
-	strd  r10, r11, [r1, #24]
+	strd	r10, r11, [r1, #24]
 #endif
 	add	sp, sp, #0x60
 	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
diff --git a/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c b/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c
index 4600aece9..8b2a58518 100644
--- a/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c
+++ b/wolfcrypt/src/port/arm/armv8-32-curve25519_c.c
@@ -61,24 +61,24 @@ void fe_frombytes(fe out_p, const unsigned char* in_p)
         "ldrd	r2, r3, [%[in]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[in], #8]\n\t"
-        "ldr	lr, [%[in], #12]\n\t"
+        "ldr	r4, [%[in], #8]\n\t"
+        "ldr	r5, [%[in], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[in], #8]\n\t"
+        "ldrd	r4, r5, [%[in], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[in], #16]\n\t"
-        "ldr	r5, [%[in], #20]\n\t"
+        "ldr	r6, [%[in], #16]\n\t"
+        "ldr	r7, [%[in], #20]\n\t"
 #else
-        "ldrd	r4, r5, [%[in], #16]\n\t"
+        "ldrd	r6, r7, [%[in], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[in], #24]\n\t"
-        "ldr	r7, [%[in], #28]\n\t"
+        "ldr	r8, [%[in], #24]\n\t"
+        "ldr	r9, [%[in], #28]\n\t"
 #else
-        "ldrd	r6, r7, [%[in], #24]\n\t"
+        "ldrd	r8, r9, [%[in], #24]\n\t"
 #endif
-        "and	r7, r7, #0x7fffffff\n\t"
+        "and	r9, r9, #0x7fffffff\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[out]]\n\t"
         "str	r3, [%[out], #4]\n\t"
@@ -86,26 +86,26 @@ void fe_frombytes(fe out_p, const unsigned char* in_p)
         "strd	r2, r3, [%[out]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[out], #8]\n\t"
-        "str	lr, [%[out], #12]\n\t"
+        "str	r4, [%[out], #8]\n\t"
+        "str	r5, [%[out], #12]\n\t"
 #else
-        "strd	r12, lr, [%[out], #8]\n\t"
+        "strd	r4, r5, [%[out], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[out], #16]\n\t"
-        "str	r5, [%[out], #20]\n\t"
+        "str	r6, [%[out], #16]\n\t"
+        "str	r7, [%[out], #20]\n\t"
 #else
-        "strd	r4, r5, [%[out], #16]\n\t"
+        "strd	r6, r7, [%[out], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[out], #24]\n\t"
-        "str	r7, [%[out], #28]\n\t"
+        "str	r8, [%[out], #24]\n\t"
+        "str	r9, [%[out], #28]\n\t"
 #else
-        "strd	r6, r7, [%[out], #24]\n\t"
+        "strd	r8, r9, [%[out], #24]\n\t"
 #endif
         : [out] "+r" (out), [in] "+r" (in)
         :
-        : "memory", "r2", "r3", "r12", "lr", "r4", "r5", "r6", "r7"
+        : "memory", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9"
     );
 }
 
@@ -122,42 +122,42 @@ void fe_tobytes(unsigned char* out_p, const fe n_p)
         "ldrd	r2, r3, [%[n]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[n], #8]\n\t"
-        "ldr	lr, [%[n], #12]\n\t"
+        "ldr	r4, [%[n], #8]\n\t"
+        "ldr	r5, [%[n], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[n], #8]\n\t"
+        "ldrd	r4, r5, [%[n], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[n], #16]\n\t"
-        "ldr	r5, [%[n], #20]\n\t"
+        "ldr	r6, [%[n], #16]\n\t"
+        "ldr	r7, [%[n], #20]\n\t"
 #else
-        "ldrd	r4, r5, [%[n], #16]\n\t"
+        "ldrd	r6, r7, [%[n], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[n], #24]\n\t"
-        "ldr	r7, [%[n], #28]\n\t"
+        "ldr	r8, [%[n], #24]\n\t"
+        "ldr	r9, [%[n], #28]\n\t"
 #else
-        "ldrd	r6, r7, [%[n], #24]\n\t"
+        "ldrd	r8, r9, [%[n], #24]\n\t"
 #endif
-        "adds	r8, r2, #19\n\t"
-        "adcs	r8, r3, #0\n\t"
-        "adcs	r8, r12, #0\n\t"
-        "adcs	r8, lr, #0\n\t"
-        "adcs	r8, r4, #0\n\t"
-        "adcs	r8, r5, #0\n\t"
-        "adcs	r8, r6, #0\n\t"
-        "adc	r8, r7, #0\n\t"
-        "asr	r8, r8, #31\n\t"
-        "and	r8, r8, #19\n\t"
-        "adds	r2, r2, r8\n\t"
+        "adds	r12, r2, #19\n\t"
+        "adcs	r12, r3, #0\n\t"
+        "adcs	r12, r4, #0\n\t"
+        "adcs	r12, r5, #0\n\t"
+        "adcs	r12, r6, #0\n\t"
+        "adcs	r12, r7, #0\n\t"
+        "adcs	r12, r8, #0\n\t"
+        "adc	r12, r9, #0\n\t"
+        "asr	r12, r12, #31\n\t"
+        "and	r12, r12, #19\n\t"
+        "adds	r2, r2, r12\n\t"
         "adcs	r3, r3, #0\n\t"
-        "adcs	r12, r12, #0\n\t"
-        "adcs	lr, lr, #0\n\t"
         "adcs	r4, r4, #0\n\t"
         "adcs	r5, r5, #0\n\t"
         "adcs	r6, r6, #0\n\t"
-        "adc	r7, r7, #0\n\t"
-        "and	r7, r7, #0x7fffffff\n\t"
+        "adcs	r7, r7, #0\n\t"
+        "adcs	r8, r8, #0\n\t"
+        "adc	r9, r9, #0\n\t"
+        "and	r9, r9, #0x7fffffff\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[out]]\n\t"
         "str	r3, [%[out], #4]\n\t"
@@ -165,26 +165,26 @@ void fe_tobytes(unsigned char* out_p, const fe n_p)
         "strd	r2, r3, [%[out]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[out], #8]\n\t"
-        "str	lr, [%[out], #12]\n\t"
+        "str	r4, [%[out], #8]\n\t"
+        "str	r5, [%[out], #12]\n\t"
 #else
-        "strd	r12, lr, [%[out], #8]\n\t"
+        "strd	r4, r5, [%[out], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[out], #16]\n\t"
-        "str	r5, [%[out], #20]\n\t"
+        "str	r6, [%[out], #16]\n\t"
+        "str	r7, [%[out], #20]\n\t"
 #else
-        "strd	r4, r5, [%[out], #16]\n\t"
+        "strd	r6, r7, [%[out], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[out], #24]\n\t"
-        "str	r7, [%[out], #28]\n\t"
+        "str	r8, [%[out], #24]\n\t"
+        "str	r9, [%[out], #28]\n\t"
 #else
-        "strd	r6, r7, [%[out], #24]\n\t"
+        "strd	r8, r9, [%[out], #24]\n\t"
 #endif
         : [out] "+r" (out), [n] "+r" (n)
         :
-        : "memory", "r2", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8"
+        : "memory", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12"
     );
 }
 
@@ -195,34 +195,35 @@ void fe_1(fe n_p)
     __asm__ __volatile__ (
         /* Set one */
         "mov	r2, #1\n\t"
-        "mov	r1, #0\n\t"
+        "mov	r3, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[n]]\n\t"
-        "str	r1, [%[n], #4]\n\t"
+        "str	r3, [%[n], #4]\n\t"
 #else
-        "strd	r2, r1, [%[n]]\n\t"
+        "strd	r2, r3, [%[n]]\n\t"
+#endif
+        "mov	r2, #0\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r2, [%[n], #8]\n\t"
+        "str	r3, [%[n], #12]\n\t"
+#else
+        "strd	r2, r3, [%[n], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n], #8]\n\t"
-        "str	r1, [%[n], #12]\n\t"
+        "str	r2, [%[n], #16]\n\t"
+        "str	r3, [%[n], #20]\n\t"
 #else
-        "strd	r1, r1, [%[n], #8]\n\t"
+        "strd	r2, r3, [%[n], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n], #16]\n\t"
-        "str	r1, [%[n], #20]\n\t"
+        "str	r2, [%[n], #24]\n\t"
+        "str	r3, [%[n], #28]\n\t"
 #else
-        "strd	r1, r1, [%[n], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n], #24]\n\t"
-        "str	r1, [%[n], #28]\n\t"
-#else
-        "strd	r1, r1, [%[n], #24]\n\t"
+        "strd	r2, r3, [%[n], #24]\n\t"
 #endif
         : [n] "+r" (n)
         :
-        : "memory", "r1", "r2"
+        : "memory", "r2", "r3"
     );
 }
 
@@ -232,34 +233,35 @@ void fe_0(fe n_p)
 
     __asm__ __volatile__ (
         /* Set zero */
-        "mov	r1, #0\n\t"
+        "mov	r2, #0\n\t"
+        "mov	r3, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n]]\n\t"
-        "str	r1, [%[n], #4]\n\t"
+        "str	r2, [%[n]]\n\t"
+        "str	r3, [%[n], #4]\n\t"
 #else
-        "strd	r1, r1, [%[n]]\n\t"
+        "strd	r2, r3, [%[n]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n], #8]\n\t"
-        "str	r1, [%[n], #12]\n\t"
+        "str	r2, [%[n], #8]\n\t"
+        "str	r3, [%[n], #12]\n\t"
 #else
-        "strd	r1, r1, [%[n], #8]\n\t"
+        "strd	r2, r3, [%[n], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n], #16]\n\t"
-        "str	r1, [%[n], #20]\n\t"
+        "str	r2, [%[n], #16]\n\t"
+        "str	r3, [%[n], #20]\n\t"
 #else
-        "strd	r1, r1, [%[n], #16]\n\t"
+        "strd	r2, r3, [%[n], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r1, [%[n], #24]\n\t"
-        "str	r1, [%[n], #28]\n\t"
+        "str	r2, [%[n], #24]\n\t"
+        "str	r3, [%[n], #28]\n\t"
 #else
-        "strd	r1, r1, [%[n], #24]\n\t"
+        "strd	r2, r3, [%[n], #24]\n\t"
 #endif
         : [n] "+r" (n)
         :
-        : "memory", "r1"
+        : "memory", "r2", "r3"
     );
 }
 
@@ -277,10 +279,10 @@ void fe_copy(fe r_p, const fe a_p)
         "ldrd	r2, r3, [%[a]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #8]\n\t"
-        "ldr	lr, [%[a], #12]\n\t"
+        "ldr	r4, [%[a], #8]\n\t"
+        "ldr	r5, [%[a], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #8]\n\t"
+        "ldrd	r4, r5, [%[a], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[r]]\n\t"
@@ -289,10 +291,10 @@ void fe_copy(fe r_p, const fe a_p)
         "strd	r2, r3, [%[r]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[r], #8]\n\t"
-        "str	lr, [%[r], #12]\n\t"
+        "str	r4, [%[r], #8]\n\t"
+        "str	r5, [%[r], #12]\n\t"
 #else
-        "strd	r12, lr, [%[r], #8]\n\t"
+        "strd	r4, r5, [%[r], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r2, [%[a], #16]\n\t"
@@ -301,10 +303,10 @@ void fe_copy(fe r_p, const fe a_p)
         "ldrd	r2, r3, [%[a], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #24]\n\t"
-        "ldr	lr, [%[a], #28]\n\t"
+        "ldr	r4, [%[a], #24]\n\t"
+        "ldr	r5, [%[a], #28]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #24]\n\t"
+        "ldrd	r4, r5, [%[a], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[r], #16]\n\t"
@@ -313,14 +315,14 @@ void fe_copy(fe r_p, const fe a_p)
         "strd	r2, r3, [%[r], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[r], #24]\n\t"
-        "str	lr, [%[r], #28]\n\t"
+        "str	r4, [%[r], #24]\n\t"
+        "str	r5, [%[r], #28]\n\t"
 #else
-        "strd	r12, lr, [%[r], #24]\n\t"
+        "strd	r4, r5, [%[r], #24]\n\t"
 #endif
         : [r] "+r" (r), [a] "+r" (a)
         :
-        : "memory", "r2", "r3", "r12", "lr"
+        : "memory", "r2", "r3", "r4", "r5"
     );
 }
 
@@ -333,126 +335,126 @@ void fe_sub(fe r_p, const fe a_p, const fe b_p)
     __asm__ __volatile__ (
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a]]\n\t"
-        "ldr	lr, [%[a], #4]\n\t"
+        "ldr	r4, [%[a]]\n\t"
+        "ldr	r5, [%[a], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[a]]\n\t"
+        "ldrd	r4, r5, [%[a]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[a], #8]\n\t"
-        "ldr	r5, [%[a], #12]\n\t"
+        "ldr	r6, [%[a], #8]\n\t"
+        "ldr	r7, [%[a], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[a], #8]\n\t"
+        "ldrd	r6, r7, [%[a], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[b]]\n\t"
-        "ldr	r7, [%[b], #4]\n\t"
+        "ldr	r8, [%[b]]\n\t"
+        "ldr	r9, [%[b], #4]\n\t"
 #else
-        "ldrd	r6, r7, [%[b]]\n\t"
+        "ldrd	r8, r9, [%[b]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[b], #8]\n\t"
-        "ldr	r9, [%[b], #12]\n\t"
+        "ldr	r10, [%[b], #8]\n\t"
+        "ldr	r11, [%[b], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[b], #8]\n\t"
+        "ldrd	r10, r11, [%[b], #8]\n\t"
+#endif
+        "subs	r8, r4, r8\n\t"
+        "sbcs	r9, r5, r9\n\t"
+        "sbcs	r10, r6, r10\n\t"
+        "sbcs	r11, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[r]]\n\t"
+        "str	r9, [%[r], #4]\n\t"
+#else
+        "strd	r8, r9, [%[r]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r10, [%[r], #8]\n\t"
+        "str	r11, [%[r], #12]\n\t"
+#else
+        "strd	r10, r11, [%[r], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[a], #16]\n\t"
+        "ldr	r5, [%[a], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[a], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[a], #24]\n\t"
+        "ldr	r7, [%[a], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[a], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[b], #16]\n\t"
+        "ldr	r9, [%[b], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[b], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[b], #24]\n\t"
+        "ldr	r11, [%[b], #28]\n\t"
+#else
+        "ldrd	r10, r11, [%[b], #24]\n\t"
 #endif
-        "subs	r6, r12, r6\n\t"
-        "sbcs	r7, lr, r7\n\t"
         "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[r]]\n\t"
-        "str	r7, [%[r], #4]\n\t"
-#else
-        "strd	r6, r7, [%[r]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [%[r], #8]\n\t"
-        "str	r9, [%[r], #12]\n\t"
-#else
-        "strd	r8, r9, [%[r], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #16]\n\t"
-        "ldr	lr, [%[a], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[a], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[a], #24]\n\t"
-        "ldr	r5, [%[a], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[a], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[b], #16]\n\t"
-        "ldr	r7, [%[b], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[b], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[b], #24]\n\t"
-        "ldr	r9, [%[b], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[b], #24]\n\t"
-#endif
-        "sbcs	r6, r12, r6\n\t"
-        "sbcs	r7, lr, r7\n\t"
-        "sbcs	r8, r4, r8\n\t"
-        "sbc	r9, r5, r9\n\t"
-        "mov	r10, #-19\n\t"
-        "asr	r3, r9, #31\n\t"
+        "sbcs	r10, r6, r10\n\t"
+        "sbc	r11, r7, r11\n\t"
+        "mov	r12, #-19\n\t"
+        "asr	r3, r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r10, r3, r10\n\t"
-        "and	r11, r3, #0x7fffffff\n\t"
+        "and	r12, r3, r12\n\t"
+        "and	lr, r3, #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[r]]\n\t"
-        "ldr	lr, [%[r], #4]\n\t"
+        "ldr	r4, [%[r]]\n\t"
+        "ldr	r5, [%[r], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[r]]\n\t"
+        "ldrd	r4, r5, [%[r]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[r], #8]\n\t"
-        "ldr	r5, [%[r], #12]\n\t"
+        "ldr	r6, [%[r], #8]\n\t"
+        "ldr	r7, [%[r], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[r], #8]\n\t"
+        "ldrd	r6, r7, [%[r], #8]\n\t"
 #endif
-        "adds	r12, r12, r10\n\t"
-        "adcs	lr, lr, r3\n\t"
-        "adcs	r4, r4, r3\n\t"
+        "adds	r4, r4, r12\n\t"
         "adcs	r5, r5, r3\n\t"
         "adcs	r6, r6, r3\n\t"
         "adcs	r7, r7, r3\n\t"
         "adcs	r8, r8, r3\n\t"
-        "adc	r9, r9, r11\n\t"
+        "adcs	r9, r9, r3\n\t"
+        "adcs	r10, r10, r3\n\t"
+        "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[r]]\n\t"
-        "str	lr, [%[r], #4]\n\t"
+        "str	r4, [%[r]]\n\t"
+        "str	r5, [%[r], #4]\n\t"
 #else
-        "strd	r12, lr, [%[r]]\n\t"
+        "strd	r4, r5, [%[r]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[r], #8]\n\t"
-        "str	r5, [%[r], #12]\n\t"
+        "str	r6, [%[r], #8]\n\t"
+        "str	r7, [%[r], #12]\n\t"
 #else
-        "strd	r4, r5, [%[r], #8]\n\t"
+        "strd	r6, r7, [%[r], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[r], #16]\n\t"
-        "str	r7, [%[r], #20]\n\t"
+        "str	r8, [%[r], #16]\n\t"
+        "str	r9, [%[r], #20]\n\t"
 #else
-        "strd	r6, r7, [%[r], #16]\n\t"
+        "strd	r8, r9, [%[r], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [%[r], #24]\n\t"
-        "str	r9, [%[r], #28]\n\t"
+        "str	r10, [%[r], #24]\n\t"
+        "str	r11, [%[r], #28]\n\t"
 #else
-        "strd	r8, r9, [%[r], #24]\n\t"
+        "strd	r10, r11, [%[r], #24]\n\t"
 #endif
         : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b)
         :
-        : "memory", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
 }
 
@@ -465,126 +467,126 @@ void fe_add(fe r_p, const fe a_p, const fe b_p)
     __asm__ __volatile__ (
         /* Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a]]\n\t"
-        "ldr	lr, [%[a], #4]\n\t"
+        "ldr	r4, [%[a]]\n\t"
+        "ldr	r5, [%[a], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[a]]\n\t"
+        "ldrd	r4, r5, [%[a]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[a], #8]\n\t"
-        "ldr	r5, [%[a], #12]\n\t"
+        "ldr	r6, [%[a], #8]\n\t"
+        "ldr	r7, [%[a], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[a], #8]\n\t"
+        "ldrd	r6, r7, [%[a], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[b]]\n\t"
-        "ldr	r7, [%[b], #4]\n\t"
+        "ldr	r8, [%[b]]\n\t"
+        "ldr	r9, [%[b], #4]\n\t"
 #else
-        "ldrd	r6, r7, [%[b]]\n\t"
+        "ldrd	r8, r9, [%[b]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[b], #8]\n\t"
-        "ldr	r9, [%[b], #12]\n\t"
+        "ldr	r10, [%[b], #8]\n\t"
+        "ldr	r11, [%[b], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[b], #8]\n\t"
+        "ldrd	r10, r11, [%[b], #8]\n\t"
+#endif
+        "adds	r8, r4, r8\n\t"
+        "adcs	r9, r5, r9\n\t"
+        "adcs	r10, r6, r10\n\t"
+        "adcs	r11, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[r]]\n\t"
+        "str	r9, [%[r], #4]\n\t"
+#else
+        "strd	r8, r9, [%[r]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r10, [%[r], #8]\n\t"
+        "str	r11, [%[r], #12]\n\t"
+#else
+        "strd	r10, r11, [%[r], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[a], #16]\n\t"
+        "ldr	r5, [%[a], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[a], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[a], #24]\n\t"
+        "ldr	r7, [%[a], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[a], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[b], #16]\n\t"
+        "ldr	r9, [%[b], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[b], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[b], #24]\n\t"
+        "ldr	r11, [%[b], #28]\n\t"
+#else
+        "ldrd	r10, r11, [%[b], #24]\n\t"
 #endif
-        "adds	r6, r12, r6\n\t"
-        "adcs	r7, lr, r7\n\t"
         "adcs	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[r]]\n\t"
-        "str	r7, [%[r], #4]\n\t"
-#else
-        "strd	r6, r7, [%[r]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [%[r], #8]\n\t"
-        "str	r9, [%[r], #12]\n\t"
-#else
-        "strd	r8, r9, [%[r], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #16]\n\t"
-        "ldr	lr, [%[a], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[a], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[a], #24]\n\t"
-        "ldr	r5, [%[a], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[a], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[b], #16]\n\t"
-        "ldr	r7, [%[b], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[b], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[b], #24]\n\t"
-        "ldr	r9, [%[b], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[b], #24]\n\t"
-#endif
-        "adcs	r6, r12, r6\n\t"
-        "adcs	r7, lr, r7\n\t"
-        "adcs	r8, r4, r8\n\t"
-        "adc	r9, r5, r9\n\t"
-        "mov	r10, #-19\n\t"
-        "asr	r3, r9, #31\n\t"
+        "adcs	r10, r6, r10\n\t"
+        "adc	r11, r7, r11\n\t"
+        "mov	r12, #-19\n\t"
+        "asr	r3, r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r10, r3, r10\n\t"
-        "and	r11, r3, #0x7fffffff\n\t"
+        "and	r12, r3, r12\n\t"
+        "and	lr, r3, #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[r]]\n\t"
-        "ldr	lr, [%[r], #4]\n\t"
+        "ldr	r4, [%[r]]\n\t"
+        "ldr	r5, [%[r], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[r]]\n\t"
+        "ldrd	r4, r5, [%[r]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[r], #8]\n\t"
-        "ldr	r5, [%[r], #12]\n\t"
+        "ldr	r6, [%[r], #8]\n\t"
+        "ldr	r7, [%[r], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[r], #8]\n\t"
+        "ldrd	r6, r7, [%[r], #8]\n\t"
 #endif
-        "subs	r12, r12, r10\n\t"
-        "sbcs	lr, lr, r3\n\t"
-        "sbcs	r4, r4, r3\n\t"
+        "subs	r4, r4, r12\n\t"
         "sbcs	r5, r5, r3\n\t"
         "sbcs	r6, r6, r3\n\t"
         "sbcs	r7, r7, r3\n\t"
         "sbcs	r8, r8, r3\n\t"
-        "sbc	r9, r9, r11\n\t"
+        "sbcs	r9, r9, r3\n\t"
+        "sbcs	r10, r10, r3\n\t"
+        "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[r]]\n\t"
-        "str	lr, [%[r], #4]\n\t"
+        "str	r4, [%[r]]\n\t"
+        "str	r5, [%[r], #4]\n\t"
 #else
-        "strd	r12, lr, [%[r]]\n\t"
+        "strd	r4, r5, [%[r]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[r], #8]\n\t"
-        "str	r5, [%[r], #12]\n\t"
+        "str	r6, [%[r], #8]\n\t"
+        "str	r7, [%[r], #12]\n\t"
 #else
-        "strd	r4, r5, [%[r], #8]\n\t"
+        "strd	r6, r7, [%[r], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[r], #16]\n\t"
-        "str	r7, [%[r], #20]\n\t"
+        "str	r8, [%[r], #16]\n\t"
+        "str	r9, [%[r], #20]\n\t"
 #else
-        "strd	r6, r7, [%[r], #16]\n\t"
+        "strd	r8, r9, [%[r], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [%[r], #24]\n\t"
-        "str	r9, [%[r], #28]\n\t"
+        "str	r10, [%[r], #24]\n\t"
+        "str	r11, [%[r], #28]\n\t"
 #else
-        "strd	r8, r9, [%[r], #24]\n\t"
+        "strd	r10, r11, [%[r], #24]\n\t"
 #endif
         : [r] "+r" (r), [a] "+r" (a), [b] "+r" (b)
         :
-        : "memory", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
 }
 
@@ -594,8 +596,8 @@ void fe_neg(fe r_p, const fe a_p)
     register const fe a asm ("r1") = a_p;
 
     __asm__ __volatile__ (
-        "mov	r5, #-1\n\t"
-        "mov	r4, #-19\n\t"
+        "mov	lr, #-1\n\t"
+        "mov	r12, #-19\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r2, [%[a]]\n\t"
         "ldr	r3, [%[a], #4]\n\t"
@@ -603,15 +605,15 @@ void fe_neg(fe r_p, const fe a_p)
         "ldrd	r2, r3, [%[a]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #8]\n\t"
-        "ldr	lr, [%[a], #12]\n\t"
+        "ldr	r4, [%[a], #8]\n\t"
+        "ldr	r5, [%[a], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #8]\n\t"
+        "ldrd	r4, r5, [%[a], #8]\n\t"
 #endif
-        "subs	r2, r4, r2\n\t"
-        "sbcs	r3, r5, r3\n\t"
-        "sbcs	r12, r5, r12\n\t"
-        "sbcs	lr, r5, lr\n\t"
+        "subs	r2, r12, r2\n\t"
+        "sbcs	r3, lr, r3\n\t"
+        "sbcs	r4, lr, r4\n\t"
+        "sbcs	r5, lr, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[r]]\n\t"
         "str	r3, [%[r], #4]\n\t"
@@ -619,17 +621,17 @@ void fe_neg(fe r_p, const fe a_p)
         "strd	r2, r3, [%[r]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[r], #8]\n\t"
-        "str	lr, [%[r], #12]\n\t"
+        "str	r4, [%[r], #8]\n\t"
+        "str	r5, [%[r], #12]\n\t"
 #else
-        "strd	r12, lr, [%[r], #8]\n\t"
+        "strd	r4, r5, [%[r], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r4, #0x7fffff\n\t"
-        "lsl	r4, r4, #8\n\t"
-        "add	r4, r4, #0xff\n\t"
+        "mov	r12, #0x7fffff\n\t"
+        "lsl	r12, r12, #8\n\t"
+        "add	r12, r12, #0xff\n\t"
 #else
-        "mov	r4, #0x7fffffff\n\t"
+        "mov	r12, #0x7fffffff\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r2, [%[a], #16]\n\t"
@@ -638,15 +640,15 @@ void fe_neg(fe r_p, const fe a_p)
         "ldrd	r2, r3, [%[a], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #24]\n\t"
-        "ldr	lr, [%[a], #28]\n\t"
+        "ldr	r4, [%[a], #24]\n\t"
+        "ldr	r5, [%[a], #28]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #24]\n\t"
+        "ldrd	r4, r5, [%[a], #24]\n\t"
 #endif
-        "sbcs	r2, r5, r2\n\t"
-        "sbcs	r3, r5, r3\n\t"
-        "sbcs	r12, r5, r12\n\t"
-        "sbc	lr, r4, lr\n\t"
+        "sbcs	r2, lr, r2\n\t"
+        "sbcs	r3, lr, r3\n\t"
+        "sbcs	r4, lr, r4\n\t"
+        "sbc	r5, r12, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r2, [%[r], #16]\n\t"
         "str	r3, [%[r], #20]\n\t"
@@ -654,14 +656,14 @@ void fe_neg(fe r_p, const fe a_p)
         "strd	r2, r3, [%[r], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[r], #24]\n\t"
-        "str	lr, [%[r], #28]\n\t"
+        "str	r4, [%[r], #24]\n\t"
+        "str	r5, [%[r], #28]\n\t"
 #else
-        "strd	r12, lr, [%[r], #24]\n\t"
+        "strd	r4, r5, [%[r], #24]\n\t"
 #endif
         : [r] "+r" (r), [a] "+r" (a)
         :
-        : "memory", "r2", "r3", "r12", "lr", "r4", "r5"
+        : "memory", "r2", "r3", "r4", "r5", "r12", "lr"
     );
 }
 
@@ -677,52 +679,52 @@ int fe_isnonzero(const fe a_p)
         "ldrd	r2, r3, [%[a]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #8]\n\t"
-        "ldr	lr, [%[a], #12]\n\t"
+        "ldr	r4, [%[a], #8]\n\t"
+        "ldr	r5, [%[a], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #8]\n\t"
+        "ldrd	r4, r5, [%[a], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[a], #16]\n\t"
-        "ldr	r5, [%[a], #20]\n\t"
+        "ldr	r6, [%[a], #16]\n\t"
+        "ldr	r7, [%[a], #20]\n\t"
 #else
-        "ldrd	r4, r5, [%[a], #16]\n\t"
+        "ldrd	r6, r7, [%[a], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[a], #24]\n\t"
-        "ldr	r7, [%[a], #28]\n\t"
+        "ldr	r8, [%[a], #24]\n\t"
+        "ldr	r9, [%[a], #28]\n\t"
 #else
-        "ldrd	r6, r7, [%[a], #24]\n\t"
+        "ldrd	r8, r9, [%[a], #24]\n\t"
 #endif
         "adds	r1, r2, #19\n\t"
         "adcs	r1, r3, #0\n\t"
-        "adcs	r1, r12, #0\n\t"
-        "adcs	r1, lr, #0\n\t"
         "adcs	r1, r4, #0\n\t"
         "adcs	r1, r5, #0\n\t"
         "adcs	r1, r6, #0\n\t"
-        "adc	r1, r7, #0\n\t"
+        "adcs	r1, r7, #0\n\t"
+        "adcs	r1, r8, #0\n\t"
+        "adc	r1, r9, #0\n\t"
         "asr	r1, r1, #31\n\t"
         "and	r1, r1, #19\n\t"
         "adds	r2, r2, r1\n\t"
         "adcs	r3, r3, #0\n\t"
-        "adcs	r12, r12, #0\n\t"
-        "adcs	lr, lr, #0\n\t"
         "adcs	r4, r4, #0\n\t"
         "adcs	r5, r5, #0\n\t"
         "adcs	r6, r6, #0\n\t"
-        "adc	r7, r7, #0\n\t"
-        "and	r7, r7, #0x7fffffff\n\t"
+        "adcs	r7, r7, #0\n\t"
+        "adcs	r8, r8, #0\n\t"
+        "adc	r9, r9, #0\n\t"
+        "and	r9, r9, #0x7fffffff\n\t"
         "orr	r2, r2, r3\n\t"
-        "orr	r12, r12, lr\n\t"
         "orr	r4, r4, r5\n\t"
         "orr	r6, r6, r7\n\t"
-        "orr	r12, r12, r4\n\t"
-        "orr	r2, r2, r6\n\t"
-        "orr	%[a], r2, r12\n\t"
+        "orr	r8, r8, r9\n\t"
+        "orr	r4, r4, r6\n\t"
+        "orr	r2, r2, r8\n\t"
+        "orr	%[a], r2, r4\n\t"
         : [a] "+r" (a)
         :
-        : "memory", "r1", "r2", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8"
+        : "memory", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12"
     );
     return (uint32_t)(size_t)a;
 }
@@ -739,15 +741,15 @@ int fe_isnegative(const fe a_p)
         "ldrd	r2, r3, [%[a]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #8]\n\t"
-        "ldr	lr, [%[a], #12]\n\t"
+        "ldr	r4, [%[a], #8]\n\t"
+        "ldr	r5, [%[a], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #8]\n\t"
+        "ldrd	r4, r5, [%[a], #8]\n\t"
 #endif
         "adds	r1, r2, #19\n\t"
         "adcs	r1, r3, #0\n\t"
-        "adcs	r1, r12, #0\n\t"
-        "adcs	r1, lr, #0\n\t"
+        "adcs	r1, r4, #0\n\t"
+        "adcs	r1, r5, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r2, [%[a], #16]\n\t"
         "ldr	r3, [%[a], #20]\n\t"
@@ -755,22 +757,22 @@ int fe_isnegative(const fe a_p)
         "ldrd	r2, r3, [%[a], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[a], #24]\n\t"
-        "ldr	lr, [%[a], #28]\n\t"
+        "ldr	r4, [%[a], #24]\n\t"
+        "ldr	r5, [%[a], #28]\n\t"
 #else
-        "ldrd	r12, lr, [%[a], #24]\n\t"
+        "ldrd	r4, r5, [%[a], #24]\n\t"
 #endif
         "adcs	r1, r2, #0\n\t"
         "adcs	r1, r3, #0\n\t"
-        "adcs	r1, r12, #0\n\t"
+        "adcs	r1, r4, #0\n\t"
         "ldr	r2, [%[a]]\n\t"
-        "adc	r1, lr, #0\n\t"
+        "adc	r1, r5, #0\n\t"
         "and	%[a], r2, #1\n\t"
         "lsr	r1, r1, #31\n\t"
         "eor	%[a], %[a], r1\n\t"
         : [a] "+r" (a)
         :
-        : "memory", "r1", "r2", "r3", "r12", "lr"
+        : "memory", "r1", "r2", "r3", "r4", "r5"
     );
     return (uint32_t)(size_t)a;
 }
@@ -783,1709 +785,1709 @@ void fe_cmov_table(fe* r_p, fe* base_p, signed char b_p)
 
     __asm__ __volatile__ (
         "sxtb	%[b], %[b]\n\t"
-        "sbfx	r7, %[b], #7, #1\n\t"
-        "eor	r10, %[b], r7\n\t"
-        "sub	r10, r10, r7\n\t"
-        "mov	r3, #1\n\t"
-        "mov	r12, #0\n\t"
-        "mov	lr, #1\n\t"
+        "sbfx	r3, %[b], #7, #1\n\t"
+        "eor	r12, %[b], r3\n\t"
+        "sub	r12, r12, r3\n\t"
+        "mov	r4, #1\n\t"
+        "mov	r5, #0\n\t"
+        "mov	r6, #1\n\t"
+        "mov	r7, #0\n\t"
+        "mov	r8, #0\n\t"
+        "mov	r9, #0\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #31\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #30\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #29\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #28\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #27\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #26\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #25\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "add	%[base], %[base], #0x60\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
+#else
+        "mov	r3, #0x80000000\n\t"
+#endif
+        "ror	r3, r3, #24\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base]]\n\t"
+        "ldr	r11, [%[base], #4]\n\t"
+#else
+        "ldrd	r10, r11, [%[base]]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #32]\n\t"
+        "ldr	r11, [%[base], #36]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #32]\n\t"
+#endif
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[base], #64]\n\t"
+        "ldr	r11, [%[base], #68]\n\t"
+#else
+        "ldrd	r10, r11, [%[base], #64]\n\t"
+#endif
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
+        "sub	%[base], %[base], #0x2a0\n\t"
+        "mov	r10, #-19\n\t"
+        "mov	r11, #-1\n\t"
+        "subs	r10, r10, r8\n\t"
+        "sbcs	r11, r11, r9\n\t"
+        "sbc	lr, lr, lr\n\t"
+        "asr	r12, %[b], #31\n\t"
+        "eor	r3, r4, r6\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r4, r4, r3\n\t"
+        "eor	r6, r6, r3\n\t"
+        "eor	r3, r5, r7\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r5, r5, r3\n\t"
+        "eor	r7, r7, r3\n\t"
+        "eor	r10, r10, r8\n\t"
+        "and	r10, r10, r12\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r11, r11, r12\n\t"
+        "eor	r9, r9, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[r]]\n\t"
+        "str	r5, [%[r], #4]\n\t"
+#else
+        "strd	r4, r5, [%[r]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[r], #32]\n\t"
+        "str	r7, [%[r], #36]\n\t"
+#else
+        "strd	r6, r7, [%[r], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[r], #64]\n\t"
+        "str	r9, [%[r], #68]\n\t"
+#else
+        "strd	r8, r9, [%[r], #64]\n\t"
+#endif
+        "sbfx	r3, %[b], #7, #1\n\t"
+        "eor	r12, %[b], r3\n\t"
+        "sub	r12, r12, r3\n\t"
         "mov	r4, #0\n\t"
         "mov	r5, #0\n\t"
         "mov	r6, #0\n\t"
+        "mov	r7, #0\n\t"
+        "mov	r8, #0\n\t"
+        "mov	r9, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #31\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #31\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #30\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #30\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #29\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #29\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #28\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #28\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #27\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #27\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #26\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #26\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #25\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #25\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #24\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #24\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base]]\n\t"
-        "ldr	r9, [%[base], #4]\n\t"
+        "ldr	r10, [%[base], #8]\n\t"
+        "ldr	r11, [%[base], #12]\n\t"
 #else
-        "ldrd	r8, r9, [%[base]]\n\t"
+        "ldrd	r10, r11, [%[base], #8]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #32]\n\t"
-        "ldr	r9, [%[base], #36]\n\t"
+        "ldr	r10, [%[base], #40]\n\t"
+        "ldr	r11, [%[base], #44]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #32]\n\t"
+        "ldrd	r10, r11, [%[base], #40]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #64]\n\t"
-        "ldr	r9, [%[base], #68]\n\t"
+        "ldr	r10, [%[base], #72]\n\t"
+        "ldr	r11, [%[base], #76]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #64]\n\t"
+        "ldrd	r10, r11, [%[base], #72]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "sub	%[base], %[base], #0x2a0\n\t"
-        "mov	r8, #-19\n\t"
-        "mov	r9, #-1\n\t"
-        "subs	r8, r8, r5\n\t"
-        "sbcs	r9, r9, r6\n\t"
-        "sbc	r11, r11, r11\n\t"
-        "asr	r10, %[b], #31\n\t"
-        "eor	r7, r3, lr\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r3, r3, r7\n\t"
-        "eor	lr, lr, r7\n\t"
-        "eor	r7, r12, r4\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r12, r12, r7\n\t"
-        "eor	r4, r4, r7\n\t"
-        "eor	r8, r8, r5\n\t"
-        "and	r8, r8, r10\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r9, r9, r10\n\t"
-        "eor	r6, r6, r9\n\t"
+        "mov	r10, #-1\n\t"
+        "mov	r11, #-1\n\t"
+        "rsbs	lr, lr, #0\n\t"
+        "sbcs	r10, r10, r8\n\t"
+        "sbcs	r11, r11, r9\n\t"
+        "sbc	lr, lr, lr\n\t"
+        "asr	r12, %[b], #31\n\t"
+        "eor	r3, r4, r6\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r4, r4, r3\n\t"
+        "eor	r6, r6, r3\n\t"
+        "eor	r3, r5, r7\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r5, r5, r3\n\t"
+        "eor	r7, r7, r3\n\t"
+        "eor	r10, r10, r8\n\t"
+        "and	r10, r10, r12\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r11, r11, r12\n\t"
+        "eor	r9, r9, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r3, [%[r]]\n\t"
-        "str	r12, [%[r], #4]\n\t"
+        "str	r4, [%[r], #8]\n\t"
+        "str	r5, [%[r], #12]\n\t"
 #else
-        "strd	r3, r12, [%[r]]\n\t"
+        "strd	r4, r5, [%[r], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	lr, [%[r], #32]\n\t"
-        "str	r4, [%[r], #36]\n\t"
+        "str	r6, [%[r], #40]\n\t"
+        "str	r7, [%[r], #44]\n\t"
 #else
-        "strd	lr, r4, [%[r], #32]\n\t"
+        "strd	r6, r7, [%[r], #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r5, [%[r], #64]\n\t"
-        "str	r6, [%[r], #68]\n\t"
+        "str	r8, [%[r], #72]\n\t"
+        "str	r9, [%[r], #76]\n\t"
 #else
-        "strd	r5, r6, [%[r], #64]\n\t"
+        "strd	r8, r9, [%[r], #72]\n\t"
 #endif
-        "sbfx	r7, %[b], #7, #1\n\t"
-        "eor	r10, %[b], r7\n\t"
-        "sub	r10, r10, r7\n\t"
-        "mov	r3, #0\n\t"
-        "mov	r12, #0\n\t"
-        "mov	lr, #0\n\t"
+        "sbfx	r3, %[b], #7, #1\n\t"
+        "eor	r12, %[b], r3\n\t"
+        "sub	r12, r12, r3\n\t"
         "mov	r4, #0\n\t"
         "mov	r5, #0\n\t"
         "mov	r6, #0\n\t"
+        "mov	r7, #0\n\t"
+        "mov	r8, #0\n\t"
+        "mov	r9, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #31\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #31\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #30\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #30\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #29\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #29\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #28\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #28\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #27\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #27\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #26\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #26\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #25\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #25\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #24\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #24\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #8]\n\t"
-        "ldr	r9, [%[base], #12]\n\t"
+        "ldr	r10, [%[base], #16]\n\t"
+        "ldr	r11, [%[base], #20]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #8]\n\t"
+        "ldrd	r10, r11, [%[base], #16]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #40]\n\t"
-        "ldr	r9, [%[base], #44]\n\t"
+        "ldr	r10, [%[base], #48]\n\t"
+        "ldr	r11, [%[base], #52]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #40]\n\t"
+        "ldrd	r10, r11, [%[base], #48]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #72]\n\t"
-        "ldr	r9, [%[base], #76]\n\t"
+        "ldr	r10, [%[base], #80]\n\t"
+        "ldr	r11, [%[base], #84]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #72]\n\t"
+        "ldrd	r10, r11, [%[base], #80]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "sub	%[base], %[base], #0x2a0\n\t"
-        "mov	r8, #-1\n\t"
-        "mov	r9, #-1\n\t"
-        "rsbs	r11, r11, #0\n\t"
-        "sbcs	r8, r8, r5\n\t"
-        "sbcs	r9, r9, r6\n\t"
-        "sbc	r11, r11, r11\n\t"
-        "asr	r10, %[b], #31\n\t"
-        "eor	r7, r3, lr\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r3, r3, r7\n\t"
-        "eor	lr, lr, r7\n\t"
-        "eor	r7, r12, r4\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r12, r12, r7\n\t"
-        "eor	r4, r4, r7\n\t"
-        "eor	r8, r8, r5\n\t"
-        "and	r8, r8, r10\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r9, r9, r10\n\t"
-        "eor	r6, r6, r9\n\t"
+        "mov	r10, #-1\n\t"
+        "mov	r11, #-1\n\t"
+        "rsbs	lr, lr, #0\n\t"
+        "sbcs	r10, r10, r8\n\t"
+        "sbcs	r11, r11, r9\n\t"
+        "sbc	lr, lr, lr\n\t"
+        "asr	r12, %[b], #31\n\t"
+        "eor	r3, r4, r6\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r4, r4, r3\n\t"
+        "eor	r6, r6, r3\n\t"
+        "eor	r3, r5, r7\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r5, r5, r3\n\t"
+        "eor	r7, r7, r3\n\t"
+        "eor	r10, r10, r8\n\t"
+        "and	r10, r10, r12\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r11, r11, r12\n\t"
+        "eor	r9, r9, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r3, [%[r], #8]\n\t"
-        "str	r12, [%[r], #12]\n\t"
+        "str	r4, [%[r], #16]\n\t"
+        "str	r5, [%[r], #20]\n\t"
 #else
-        "strd	r3, r12, [%[r], #8]\n\t"
+        "strd	r4, r5, [%[r], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	lr, [%[r], #40]\n\t"
-        "str	r4, [%[r], #44]\n\t"
+        "str	r6, [%[r], #48]\n\t"
+        "str	r7, [%[r], #52]\n\t"
 #else
-        "strd	lr, r4, [%[r], #40]\n\t"
+        "strd	r6, r7, [%[r], #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r5, [%[r], #72]\n\t"
-        "str	r6, [%[r], #76]\n\t"
+        "str	r8, [%[r], #80]\n\t"
+        "str	r9, [%[r], #84]\n\t"
 #else
-        "strd	r5, r6, [%[r], #72]\n\t"
+        "strd	r8, r9, [%[r], #80]\n\t"
 #endif
-        "sbfx	r7, %[b], #7, #1\n\t"
-        "eor	r10, %[b], r7\n\t"
-        "sub	r10, r10, r7\n\t"
-        "mov	r3, #0\n\t"
-        "mov	r12, #0\n\t"
-        "mov	lr, #0\n\t"
+        "sbfx	r3, %[b], #7, #1\n\t"
+        "eor	r12, %[b], r3\n\t"
+        "sub	r12, r12, r3\n\t"
         "mov	r4, #0\n\t"
         "mov	r5, #0\n\t"
         "mov	r6, #0\n\t"
+        "mov	r7, #0\n\t"
+        "mov	r8, #0\n\t"
+        "mov	r9, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #31\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #31\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #30\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #30\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #29\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #29\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #28\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #28\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #27\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #27\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #26\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #26\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #25\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #25\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "add	%[base], %[base], #0x60\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
+        "mov	r3, #0x800000\n\t"
+        "lsl	r3, r3, #8\n\t"
+        "add	r3, r3, #0x0\n\t"
 #else
-        "mov	r7, #0x80000000\n\t"
+        "mov	r3, #0x80000000\n\t"
 #endif
-        "ror	r7, r7, #24\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
+        "ror	r3, r3, #24\n\t"
+        "ror	r3, r3, r12\n\t"
+        "asr	r3, r3, #31\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #16]\n\t"
-        "ldr	r9, [%[base], #20]\n\t"
+        "ldr	r10, [%[base], #24]\n\t"
+        "ldr	r11, [%[base], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #16]\n\t"
+        "ldrd	r10, r11, [%[base], #24]\n\t"
 #endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r4, r4, r10\n\t"
+        "eor	r5, r5, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #48]\n\t"
-        "ldr	r9, [%[base], #52]\n\t"
+        "ldr	r10, [%[base], #56]\n\t"
+        "ldr	r11, [%[base], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #48]\n\t"
+        "ldrd	r10, r11, [%[base], #56]\n\t"
 #endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r6, r6, r10\n\t"
+        "eor	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #80]\n\t"
-        "ldr	r9, [%[base], #84]\n\t"
+        "ldr	r10, [%[base], #88]\n\t"
+        "ldr	r11, [%[base], #92]\n\t"
 #else
-        "ldrd	r8, r9, [%[base], #80]\n\t"
+        "ldrd	r10, r11, [%[base], #88]\n\t"
 #endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
+        "eor	r10, r10, r8\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r10, r10, r3\n\t"
+        "and	r11, r11, r3\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r9, r9, r11\n\t"
         "sub	%[base], %[base], #0x2a0\n\t"
-        "mov	r8, #-1\n\t"
-        "mov	r9, #-1\n\t"
-        "rsbs	r11, r11, #0\n\t"
-        "sbcs	r8, r8, r5\n\t"
-        "sbcs	r9, r9, r6\n\t"
-        "sbc	r11, r11, r11\n\t"
-        "asr	r10, %[b], #31\n\t"
-        "eor	r7, r3, lr\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r3, r3, r7\n\t"
-        "eor	lr, lr, r7\n\t"
-        "eor	r7, r12, r4\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r12, r12, r7\n\t"
-        "eor	r4, r4, r7\n\t"
-        "eor	r8, r8, r5\n\t"
-        "and	r8, r8, r10\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r9, r9, r10\n\t"
-        "eor	r6, r6, r9\n\t"
+        "mov	r10, #-1\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r3, [%[r], #16]\n\t"
-        "str	r12, [%[r], #20]\n\t"
+        "mov	r11, #0x7fffff\n\t"
+        "lsl	r11, r11, #8\n\t"
+        "add	r11, r11, #0xff\n\t"
 #else
-        "strd	r3, r12, [%[r], #16]\n\t"
+        "mov	r11, #0x7fffffff\n\t"
+#endif
+        "rsbs	lr, lr, #0\n\t"
+        "sbcs	r10, r10, r8\n\t"
+        "sbc	r11, r11, r9\n\t"
+        "asr	r12, %[b], #31\n\t"
+        "eor	r3, r4, r6\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r4, r4, r3\n\t"
+        "eor	r6, r6, r3\n\t"
+        "eor	r3, r5, r7\n\t"
+        "and	r3, r3, r12\n\t"
+        "eor	r5, r5, r3\n\t"
+        "eor	r7, r7, r3\n\t"
+        "eor	r10, r10, r8\n\t"
+        "and	r10, r10, r12\n\t"
+        "eor	r8, r8, r10\n\t"
+        "eor	r11, r11, r9\n\t"
+        "and	r11, r11, r12\n\t"
+        "eor	r9, r9, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[r], #24]\n\t"
+        "str	r5, [%[r], #28]\n\t"
+#else
+        "strd	r4, r5, [%[r], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	lr, [%[r], #48]\n\t"
-        "str	r4, [%[r], #52]\n\t"
+        "str	r6, [%[r], #56]\n\t"
+        "str	r7, [%[r], #60]\n\t"
 #else
-        "strd	lr, r4, [%[r], #48]\n\t"
+        "strd	r6, r7, [%[r], #56]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r5, [%[r], #80]\n\t"
-        "str	r6, [%[r], #84]\n\t"
+        "str	r8, [%[r], #88]\n\t"
+        "str	r9, [%[r], #92]\n\t"
 #else
-        "strd	r5, r6, [%[r], #80]\n\t"
-#endif
-        "sbfx	r7, %[b], #7, #1\n\t"
-        "eor	r10, %[b], r7\n\t"
-        "sub	r10, r10, r7\n\t"
-        "mov	r3, #0\n\t"
-        "mov	r12, #0\n\t"
-        "mov	lr, #0\n\t"
-        "mov	r4, #0\n\t"
-        "mov	r5, #0\n\t"
-        "mov	r6, #0\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #31\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #30\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #29\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #28\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #27\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #26\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #25\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "add	%[base], %[base], #0x60\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r7, #0x800000\n\t"
-        "lsl	r7, r7, #8\n\t"
-        "add	r7, r7, #0x0\n\t"
-#else
-        "mov	r7, #0x80000000\n\t"
-#endif
-        "ror	r7, r7, #24\n\t"
-        "ror	r7, r7, r10\n\t"
-        "asr	r7, r7, #31\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #24]\n\t"
-        "ldr	r9, [%[base], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #24]\n\t"
-#endif
-        "eor	r8, r8, r3\n\t"
-        "eor	r9, r9, r12\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r3, r3, r8\n\t"
-        "eor	r12, r12, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #56]\n\t"
-        "ldr	r9, [%[base], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #56]\n\t"
-#endif
-        "eor	r8, r8, lr\n\t"
-        "eor	r9, r9, r4\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	lr, lr, r8\n\t"
-        "eor	r4, r4, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[base], #88]\n\t"
-        "ldr	r9, [%[base], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[base], #88]\n\t"
-#endif
-        "eor	r8, r8, r5\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r8, r8, r7\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r6, r6, r9\n\t"
-        "sub	%[base], %[base], #0x2a0\n\t"
-        "mov	r8, #-1\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "mov	r9, #0x7fffff\n\t"
-        "lsl	r9, r9, #8\n\t"
-        "add	r9, r9, #0xff\n\t"
-#else
-        "mov	r9, #0x7fffffff\n\t"
-#endif
-        "rsbs	r11, r11, #0\n\t"
-        "sbcs	r8, r8, r5\n\t"
-        "sbc	r9, r9, r6\n\t"
-        "asr	r10, %[b], #31\n\t"
-        "eor	r7, r3, lr\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r3, r3, r7\n\t"
-        "eor	lr, lr, r7\n\t"
-        "eor	r7, r12, r4\n\t"
-        "and	r7, r7, r10\n\t"
-        "eor	r12, r12, r7\n\t"
-        "eor	r4, r4, r7\n\t"
-        "eor	r8, r8, r5\n\t"
-        "and	r8, r8, r10\n\t"
-        "eor	r5, r5, r8\n\t"
-        "eor	r9, r9, r6\n\t"
-        "and	r9, r9, r10\n\t"
-        "eor	r6, r6, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r3, [%[r], #24]\n\t"
-        "str	r12, [%[r], #28]\n\t"
-#else
-        "strd	r3, r12, [%[r], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	lr, [%[r], #56]\n\t"
-        "str	r4, [%[r], #60]\n\t"
-#else
-        "strd	lr, r4, [%[r], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r5, [%[r], #88]\n\t"
-        "str	r6, [%[r], #92]\n\t"
-#else
-        "strd	r5, r6, [%[r], #88]\n\t"
+        "strd	r8, r9, [%[r], #88]\n\t"
 #endif
         : [r] "+r" (r), [base] "+r" (base), [b] "+r" (b)
         :
-        : "memory", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r4", "r5", "r6", "r7", "r8", "r9", "r3", "r10", "r11", "r12", "lr"
     );
 }
 
@@ -3622,7 +3624,7 @@ void fe_mul121666(fe r_p, fe a_p)
 #endif
         : [r] "+r" (r), [a] "+r" (a)
         :
-        : "memory", "r2", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10"
+        : "memory", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12", "lr", "r10"
     );
 }
 
@@ -4282,84 +4284,87 @@ int curve25519(byte* r_p, const byte* n_p, const byte* a_p)
         "mov	%[n], #0\n\t"
         "str	%[n], [sp, #172]\n\t"
         /* Set one */
-        "mov	r11, #1\n\t"
+        "mov	r10, #1\n\t"
+        "mov	r11, #0\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r10, [%[r]]\n\t"
+        "str	r11, [%[r], #4]\n\t"
+#else
+        "strd	r10, r11, [%[r]]\n\t"
+#endif
         "mov	r10, #0\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r11, [%[r]]\n\t"
-        "str	r10, [%[r], #4]\n\t"
-#else
-        "strd	r11, r10, [%[r]]\n\t"
-#endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [%[r], #8]\n\t"
-        "str	r10, [%[r], #12]\n\t"
+        "str	r11, [%[r], #12]\n\t"
 #else
-        "strd	r10, r10, [%[r], #8]\n\t"
+        "strd	r10, r11, [%[r], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [%[r], #16]\n\t"
-        "str	r10, [%[r], #20]\n\t"
+        "str	r11, [%[r], #20]\n\t"
 #else
-        "strd	r10, r10, [%[r], #16]\n\t"
+        "strd	r10, r11, [%[r], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [%[r], #24]\n\t"
-        "str	r10, [%[r], #28]\n\t"
+        "str	r11, [%[r], #28]\n\t"
 #else
-        "strd	r10, r10, [%[r], #24]\n\t"
+        "strd	r10, r11, [%[r], #24]\n\t"
 #endif
         /* Set zero */
         "mov	r10, #0\n\t"
+        "mov	r11, #0\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp]\n\t"
-        "str	r10, [sp, #4]\n\t"
+        "str	r11, [sp, #4]\n\t"
 #else
-        "strd	r10, r10, [sp]\n\t"
+        "strd	r10, r11, [sp]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp, #8]\n\t"
-        "str	r10, [sp, #12]\n\t"
+        "str	r11, [sp, #12]\n\t"
 #else
-        "strd	r10, r10, [sp, #8]\n\t"
+        "strd	r10, r11, [sp, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp, #16]\n\t"
-        "str	r10, [sp, #20]\n\t"
+        "str	r11, [sp, #20]\n\t"
 #else
-        "strd	r10, r10, [sp, #16]\n\t"
+        "strd	r10, r11, [sp, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp, #24]\n\t"
-        "str	r10, [sp, #28]\n\t"
+        "str	r11, [sp, #28]\n\t"
 #else
-        "strd	r10, r10, [sp, #24]\n\t"
+        "strd	r10, r11, [sp, #24]\n\t"
 #endif
         /* Set one */
-        "mov	r11, #1\n\t"
+        "mov	r10, #1\n\t"
+        "mov	r11, #0\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r10, [sp, #32]\n\t"
+        "str	r11, [sp, #36]\n\t"
+#else
+        "strd	r10, r11, [sp, #32]\n\t"
+#endif
         "mov	r10, #0\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r11, [sp, #32]\n\t"
-        "str	r10, [sp, #36]\n\t"
-#else
-        "strd	r11, r10, [sp, #32]\n\t"
-#endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp, #40]\n\t"
-        "str	r10, [sp, #44]\n\t"
+        "str	r11, [sp, #44]\n\t"
 #else
-        "strd	r10, r10, [sp, #40]\n\t"
+        "strd	r10, r11, [sp, #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp, #48]\n\t"
-        "str	r10, [sp, #52]\n\t"
+        "str	r11, [sp, #52]\n\t"
 #else
-        "strd	r10, r10, [sp, #48]\n\t"
+        "strd	r10, r11, [sp, #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [sp, #56]\n\t"
-        "str	r10, [sp, #60]\n\t"
+        "str	r11, [sp, #60]\n\t"
 #else
-        "strd	r10, r10, [sp, #56]\n\t"
+        "strd	r10, r11, [sp, #56]\n\t"
 #endif
         /* Copy */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
@@ -6126,9 +6131,9 @@ void fe_ge_to_p2(fe rx_p, fe ry_p, fe rz_p, const fe px_p, const fe py_p, const
         :
         : "memory", "lr"
     );
-    (void)py;
-    (void)pz;
-    (void)pt;
+    (void)py_p;
+    (void)pz_p;
+    (void)pt_p;
 }
 
 void fe_ge_to_p3(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p, const fe pz_p, const fe pt_p)
@@ -6169,10 +6174,10 @@ void fe_ge_to_p3(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_
         :
         : "memory", "lr"
     );
-    (void)px;
-    (void)py;
-    (void)pz;
-    (void)pt;
+    (void)px_p;
+    (void)py_p;
+    (void)pz_p;
+    (void)pt_p;
 }
 
 void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p, const fe pz_p)
@@ -6202,10 +6207,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r2, [sp, #56]\n\t"
         /* Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -6225,7 +6230,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "adds	r8, %[rt], r8\n\t"
+        "adds	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adcs	r11, r7, r11\n\t"
@@ -6242,10 +6247,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -6265,21 +6270,21 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "adcs	r8, %[rt], r8\n\t"
+        "adcs	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -6287,19 +6292,19 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -6328,10 +6333,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r2]\n\t"
@@ -6339,7 +6344,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r2]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -6350,7 +6355,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -6362,10 +6367,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r2, #8]\n\t"
@@ -6374,7 +6379,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r2, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -6386,7 +6391,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -6398,10 +6403,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r2, #16]\n\t"
@@ -6410,7 +6415,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r2, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -6422,7 +6427,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -6434,10 +6439,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #24]\n\t"
+        "ldr	r4, [r1, #24]\n\t"
         "ldr	r5, [r1, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #24]\n\t"
+        "ldrd	r4, r5, [r1, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r2, #24]\n\t"
@@ -6446,61 +6451,61 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r2, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -6509,54 +6514,54 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -6569,10 +6574,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r2, [sp, #4]\n\t"
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -6592,7 +6597,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "subs	r8, %[rt], r8\n\t"
+        "subs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbcs	r11, r7, r11\n\t"
@@ -6609,10 +6614,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -6632,21 +6637,21 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "sbcs	r8, %[rt], r8\n\t"
+        "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -6654,19 +6659,19 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
-        "adcs	r6, r6, r4\n\t"
-        "adcs	r7, r7, r4\n\t"
-        "adcs	r8, r8, r4\n\t"
-        "adcs	r9, r9, r4\n\t"
-        "adcs	r10, r10, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
+        "adcs	r6, r6, %[rt]\n\t"
+        "adcs	r7, r7, %[rt]\n\t"
+        "adcs	r8, r8, %[rt]\n\t"
+        "adcs	r9, r9, %[rt]\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -6693,10 +6698,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r1, [sp, #8]\n\t"
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -6716,7 +6721,7 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r1, #8]\n\t"
 #endif
-        "subs	r8, %[rt], r8\n\t"
+        "subs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbcs	r11, r7, r11\n\t"
@@ -6733,10 +6738,10 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -6756,21 +6761,21 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r1, #24]\n\t"
 #endif
-        "sbcs	r8, %[rt], r8\n\t"
+        "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -6778,19 +6783,19 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
-        "adcs	r6, r6, r4\n\t"
-        "adcs	r7, r7, r4\n\t"
-        "adcs	r8, r8, r4\n\t"
-        "adcs	r9, r9, r4\n\t"
-        "adcs	r10, r10, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
+        "adcs	r6, r6, %[rt]\n\t"
+        "adcs	r7, r7, %[rt]\n\t"
+        "adcs	r8, r8, %[rt]\n\t"
+        "adcs	r9, r9, %[rt]\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -6813,11 +6818,11 @@ void fe_ge_dbl(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "add	sp, sp, #16\n\t"
         : [rx] "+r" (rx), [ry] "+r" (ry), [rz] "+r" (rz), [rt] "+r" (rt)
         :
-        : "memory", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
-    (void)px;
-    (void)py;
-    (void)pz;
+    (void)px_p;
+    (void)py_p;
+    (void)pz_p;
 }
 
 void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p, const fe pz_p, const fe pt_p, const fe qxy2d_p, const fe qyplusx_p, const fe qyminusx_p)
@@ -6845,10 +6850,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldr	r2, [sp, #68]\n\t"
         /* Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -6868,7 +6873,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "adds	r8, %[rt], r8\n\t"
+        "adds	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adcs	r11, r7, r11\n\t"
@@ -6885,10 +6890,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -6908,21 +6913,21 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "adcs	r8, %[rt], r8\n\t"
+        "adcs	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -6930,19 +6935,19 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -6967,10 +6972,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldr	r2, [sp, #68]\n\t"
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -6990,7 +6995,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "subs	r8, %[rt], r8\n\t"
+        "subs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbcs	r11, r7, r11\n\t"
@@ -7007,10 +7012,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -7030,21 +7035,21 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "sbcs	r8, %[rt], r8\n\t"
+        "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -7052,19 +7057,19 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
-        "adcs	r6, r6, r4\n\t"
-        "adcs	r7, r7, r4\n\t"
-        "adcs	r8, r8, r4\n\t"
-        "adcs	r9, r9, r4\n\t"
-        "adcs	r10, r10, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
+        "adcs	r6, r6, %[rt]\n\t"
+        "adcs	r7, r7, %[rt]\n\t"
+        "adcs	r8, r8, %[rt]\n\t"
+        "adcs	r9, r9, %[rt]\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -7102,10 +7107,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2]\n\t"
+        "ldr	r4, [r2]\n\t"
         "ldr	r5, [r2, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2]\n\t"
+        "ldrd	r4, r5, [r2]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0]\n\t"
@@ -7113,7 +7118,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7124,7 +7129,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7136,10 +7141,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #8]\n\t"
+        "ldr	r4, [r2, #8]\n\t"
         "ldr	r5, [r2, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #8]\n\t"
+        "ldrd	r4, r5, [r2, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -7148,7 +7153,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7160,7 +7165,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7172,10 +7177,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #16]\n\t"
+        "ldr	r4, [r2, #16]\n\t"
         "ldr	r5, [r2, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #16]\n\t"
+        "ldrd	r4, r5, [r2, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #16]\n\t"
@@ -7184,7 +7189,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7196,7 +7201,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7208,10 +7213,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #24]\n\t"
+        "ldr	r4, [r2, #24]\n\t"
         "ldr	r5, [r2, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #24]\n\t"
+        "ldrd	r4, r5, [r2, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -7220,61 +7225,61 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -7283,54 +7288,54 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -7342,10 +7347,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldr	r1, [sp, #76]\n\t"
         /* Double */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -7365,7 +7370,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r1, #24]\n\t"
 #endif
-        "adds	%[rt], %[rt], %[rt]\n\t"
+        "adds	r4, r4, r4\n\t"
         "adcs	r5, r5, r5\n\t"
         "adcs	r6, r6, r6\n\t"
         "adcs	r7, r7, r7\n\t"
@@ -7374,24 +7379,24 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "adcs	r10, r10, r10\n\t"
         "adc	r11, r11, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -7416,10 +7421,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1]\n\t"
@@ -7427,7 +7432,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r1]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7438,7 +7443,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7450,10 +7455,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -7462,7 +7467,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r1, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7474,7 +7479,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7486,10 +7491,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #16]\n\t"
@@ -7498,7 +7503,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r1, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7510,7 +7515,7 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7522,10 +7527,10 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #24]\n\t"
+        "ldr	r4, [r0, #24]\n\t"
         "ldr	r5, [r0, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #24]\n\t"
+        "ldrd	r4, r5, [r0, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -7534,61 +7539,61 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r1, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -7597,54 +7602,54 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -7655,15 +7660,15 @@ void fe_ge_madd(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "add	sp, sp, #32\n\t"
         : [rx] "+r" (rx), [ry] "+r" (ry), [rz] "+r" (rz), [rt] "+r" (rt)
         :
-        : "memory", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
-    (void)px;
-    (void)py;
-    (void)pz;
-    (void)pt;
-    (void)qxy2d;
-    (void)qyplusx;
-    (void)qyminusx;
+    (void)px_p;
+    (void)py_p;
+    (void)pz_p;
+    (void)pt_p;
+    (void)qxy2d_p;
+    (void)qyplusx_p;
+    (void)qyminusx_p;
 }
 
 void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p, const fe pz_p, const fe pt_p, const fe qxy2d_p, const fe qyplusx_p, const fe qyminusx_p)
@@ -7691,10 +7696,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldr	r2, [sp, #68]\n\t"
         /* Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -7714,7 +7719,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "adds	r8, %[rt], r8\n\t"
+        "adds	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adcs	r11, r7, r11\n\t"
@@ -7731,10 +7736,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -7754,21 +7759,21 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "adcs	r8, %[rt], r8\n\t"
+        "adcs	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -7776,19 +7781,19 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -7813,10 +7818,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldr	r2, [sp, #68]\n\t"
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -7836,7 +7841,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "subs	r8, %[rt], r8\n\t"
+        "subs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbcs	r11, r7, r11\n\t"
@@ -7853,10 +7858,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -7876,21 +7881,21 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "sbcs	r8, %[rt], r8\n\t"
+        "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -7898,19 +7903,19 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
-        "adcs	r6, r6, r4\n\t"
-        "adcs	r7, r7, r4\n\t"
-        "adcs	r8, r8, r4\n\t"
-        "adcs	r9, r9, r4\n\t"
-        "adcs	r10, r10, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
+        "adcs	r6, r6, %[rt]\n\t"
+        "adcs	r7, r7, %[rt]\n\t"
+        "adcs	r8, r8, %[rt]\n\t"
+        "adcs	r9, r9, %[rt]\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -7948,10 +7953,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2]\n\t"
+        "ldr	r4, [r2]\n\t"
         "ldr	r5, [r2, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2]\n\t"
+        "ldrd	r4, r5, [r2]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0]\n\t"
@@ -7959,7 +7964,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -7970,7 +7975,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -7982,10 +7987,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #8]\n\t"
+        "ldr	r4, [r2, #8]\n\t"
         "ldr	r5, [r2, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #8]\n\t"
+        "ldrd	r4, r5, [r2, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -7994,7 +7999,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8006,7 +8011,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8018,10 +8023,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #16]\n\t"
+        "ldr	r4, [r2, #16]\n\t"
         "ldr	r5, [r2, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #16]\n\t"
+        "ldrd	r4, r5, [r2, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #16]\n\t"
@@ -8030,7 +8035,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8042,7 +8047,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8054,10 +8059,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #24]\n\t"
+        "ldr	r4, [r2, #24]\n\t"
         "ldr	r5, [r2, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #24]\n\t"
+        "ldrd	r4, r5, [r2, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -8066,61 +8071,61 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -8129,54 +8134,54 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -8188,10 +8193,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldr	r1, [sp, #76]\n\t"
         /* Double */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -8211,7 +8216,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r10, r11, [r1, #24]\n\t"
 #endif
-        "adds	%[rt], %[rt], %[rt]\n\t"
+        "adds	r4, r4, r4\n\t"
         "adcs	r5, r5, r5\n\t"
         "adcs	r6, r6, r6\n\t"
         "adcs	r7, r7, r7\n\t"
@@ -8220,24 +8225,24 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "adcs	r10, r10, r10\n\t"
         "adc	r11, r11, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -8262,10 +8267,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0]\n\t"
@@ -8273,7 +8278,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #else
         "ldrd	r6, r7, [r0]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8284,7 +8289,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8296,10 +8301,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -8308,7 +8313,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8320,7 +8325,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8332,10 +8337,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #16]\n\t"
@@ -8344,7 +8349,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8356,7 +8361,7 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8368,10 +8373,10 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #24]\n\t"
+        "ldr	r4, [r1, #24]\n\t"
         "ldr	r5, [r1, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #24]\n\t"
+        "ldrd	r4, r5, [r1, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -8380,61 +8385,61 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "ldrd	r6, r7, [r0, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -8443,54 +8448,54 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -8501,15 +8506,15 @@ void fe_ge_msub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p
         "add	sp, sp, #32\n\t"
         : [rx] "+r" (rx), [ry] "+r" (ry), [rz] "+r" (rz), [rt] "+r" (rt)
         :
-        : "memory", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
-    (void)px;
-    (void)py;
-    (void)pz;
-    (void)pt;
-    (void)qxy2d;
-    (void)qyplusx;
-    (void)qyminusx;
+    (void)px_p;
+    (void)py_p;
+    (void)pz_p;
+    (void)pt_p;
+    (void)qxy2d_p;
+    (void)qyplusx_p;
+    (void)qyminusx_p;
 }
 
 void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p, const fe pz_p, const fe pt_p, const fe qz_p, const fe qt2d_p, const fe qyplusx_p, const fe qyminusx_p)
@@ -8538,10 +8543,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r2, [sp, #132]\n\t"
         /* Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -8561,7 +8566,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "adds	r8, %[rt], r8\n\t"
+        "adds	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adcs	r11, r7, r11\n\t"
@@ -8578,10 +8583,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -8601,21 +8606,21 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "adcs	r8, %[rt], r8\n\t"
+        "adcs	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -8623,19 +8628,19 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -8660,10 +8665,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r2, [sp, #132]\n\t"
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -8683,7 +8688,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "subs	r8, %[rt], r8\n\t"
+        "subs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbcs	r11, r7, r11\n\t"
@@ -8700,10 +8705,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -8723,21 +8728,21 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "sbcs	r8, %[rt], r8\n\t"
+        "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -8745,19 +8750,19 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
-        "adcs	r6, r6, r4\n\t"
-        "adcs	r7, r7, r4\n\t"
-        "adcs	r8, r8, r4\n\t"
-        "adcs	r9, r9, r4\n\t"
-        "adcs	r10, r10, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
+        "adcs	r6, r6, %[rt]\n\t"
+        "adcs	r7, r7, %[rt]\n\t"
+        "adcs	r8, r8, %[rt]\n\t"
+        "adcs	r9, r9, %[rt]\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -8797,10 +8802,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r1, [sp]\n\t"
         /* Double */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -8820,7 +8825,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r1, #24]\n\t"
 #endif
-        "adds	%[rt], %[rt], %[rt]\n\t"
+        "adds	r4, r4, r4\n\t"
         "adcs	r5, r5, r5\n\t"
         "adcs	r6, r6, r6\n\t"
         "adcs	r7, r7, r7\n\t"
@@ -8829,24 +8834,24 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "adcs	r10, r10, r10\n\t"
         "adc	r11, r11, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -8872,10 +8877,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2]\n\t"
+        "ldr	r4, [r2]\n\t"
         "ldr	r5, [r2, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2]\n\t"
+        "ldrd	r4, r5, [r2]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0]\n\t"
@@ -8883,7 +8888,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8894,7 +8899,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8906,10 +8911,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #8]\n\t"
+        "ldr	r4, [r2, #8]\n\t"
         "ldr	r5, [r2, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #8]\n\t"
+        "ldrd	r4, r5, [r2, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -8918,7 +8923,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8930,7 +8935,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8942,10 +8947,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #16]\n\t"
+        "ldr	r4, [r2, #16]\n\t"
         "ldr	r5, [r2, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #16]\n\t"
+        "ldrd	r4, r5, [r2, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #16]\n\t"
@@ -8954,7 +8959,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -8966,7 +8971,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -8978,10 +8983,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #24]\n\t"
+        "ldr	r4, [r2, #24]\n\t"
         "ldr	r5, [r2, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #24]\n\t"
+        "ldrd	r4, r5, [r2, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -8990,61 +8995,61 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -9053,54 +9058,54 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -9114,10 +9119,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2]\n\t"
+        "ldr	r4, [r2]\n\t"
         "ldr	r5, [r2, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2]\n\t"
+        "ldrd	r4, r5, [r2]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1]\n\t"
@@ -9125,7 +9130,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r1]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9136,7 +9141,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -9148,10 +9153,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #8]\n\t"
+        "ldr	r4, [r2, #8]\n\t"
         "ldr	r5, [r2, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #8]\n\t"
+        "ldrd	r4, r5, [r2, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -9160,7 +9165,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r1, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9172,7 +9177,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -9184,10 +9189,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #16]\n\t"
+        "ldr	r4, [r2, #16]\n\t"
         "ldr	r5, [r2, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #16]\n\t"
+        "ldrd	r4, r5, [r2, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #16]\n\t"
@@ -9196,7 +9201,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r1, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9208,7 +9213,7 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -9220,10 +9225,10 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #24]\n\t"
+        "ldr	r4, [r2, #24]\n\t"
         "ldr	r5, [r2, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #24]\n\t"
+        "ldrd	r4, r5, [r2, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -9232,61 +9237,61 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r1, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -9295,54 +9300,54 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -9353,16 +9358,16 @@ void fe_ge_add(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "add	sp, sp, #0x60\n\t"
         : [rx] "+r" (rx), [ry] "+r" (ry), [rz] "+r" (rz), [rt] "+r" (rt)
         :
-        : "memory", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
-    (void)px;
-    (void)py;
-    (void)pz;
-    (void)pt;
-    (void)qz;
-    (void)qt2d;
-    (void)qyplusx;
-    (void)qyminusx;
+    (void)px_p;
+    (void)py_p;
+    (void)pz_p;
+    (void)pt_p;
+    (void)qz_p;
+    (void)qt2d_p;
+    (void)qyplusx_p;
+    (void)qyminusx_p;
 }
 
 void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p, const fe pz_p, const fe pt_p, const fe qz_p, const fe qt2d_p, const fe qyplusx_p, const fe qyminusx_p)
@@ -9391,10 +9396,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r2, [sp, #132]\n\t"
         /* Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -9414,7 +9419,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "adds	r8, %[rt], r8\n\t"
+        "adds	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adcs	r11, r7, r11\n\t"
@@ -9431,10 +9436,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -9454,21 +9459,21 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "adcs	r8, %[rt], r8\n\t"
+        "adcs	r8, r4, r8\n\t"
         "adcs	r9, r5, r9\n\t"
         "adcs	r10, r6, r10\n\t"
         "adc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -9476,19 +9481,19 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -9513,10 +9518,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r2, [sp, #132]\n\t"
         /* Sub */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -9536,7 +9541,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #8]\n\t"
 #endif
-        "subs	r8, %[rt], r8\n\t"
+        "subs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbcs	r11, r7, r11\n\t"
@@ -9553,10 +9558,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r10, r11, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #24]\n\t"
@@ -9576,21 +9581,21 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r2, #24]\n\t"
 #endif
-        "sbcs	r8, %[rt], r8\n\t"
+        "sbcs	r8, r4, r8\n\t"
         "sbcs	r9, r5, r9\n\t"
         "sbcs	r10, r6, r10\n\t"
         "sbc	r11, r7, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -9598,19 +9603,19 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
-        "adcs	r6, r6, r4\n\t"
-        "adcs	r7, r7, r4\n\t"
-        "adcs	r8, r8, r4\n\t"
-        "adcs	r9, r9, r4\n\t"
-        "adcs	r10, r10, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
+        "adcs	r6, r6, %[rt]\n\t"
+        "adcs	r7, r7, %[rt]\n\t"
+        "adcs	r8, r8, %[rt]\n\t"
+        "adcs	r9, r9, %[rt]\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -9650,10 +9655,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldr	r1, [sp]\n\t"
         /* Double */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r1, #8]\n\t"
@@ -9673,7 +9678,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r10, r11, [r1, #24]\n\t"
 #endif
-        "adds	%[rt], %[rt], %[rt]\n\t"
+        "adds	r4, r4, r4\n\t"
         "adcs	r5, r5, r5\n\t"
         "adcs	r6, r6, r6\n\t"
         "adcs	r7, r7, r7\n\t"
@@ -9682,24 +9687,24 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "adcs	r10, r10, r10\n\t"
         "adc	r11, r11, r11\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
-        "sbcs	r6, r6, r4\n\t"
-        "sbcs	r7, r7, r4\n\t"
-        "sbcs	r8, r8, r4\n\t"
-        "sbcs	r9, r9, r4\n\t"
-        "sbcs	r10, r10, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
+        "sbcs	r6, r6, %[rt]\n\t"
+        "sbcs	r7, r7, %[rt]\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
+        "sbcs	r9, r9, %[rt]\n\t"
+        "sbcs	r10, r10, %[rt]\n\t"
         "sbc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [r0, #8]\n\t"
@@ -9725,10 +9730,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2]\n\t"
+        "ldr	r4, [r2]\n\t"
         "ldr	r5, [r2, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2]\n\t"
+        "ldrd	r4, r5, [r2]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0]\n\t"
@@ -9736,7 +9741,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9747,7 +9752,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -9759,10 +9764,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #8]\n\t"
+        "ldr	r4, [r2, #8]\n\t"
         "ldr	r5, [r2, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #8]\n\t"
+        "ldrd	r4, r5, [r2, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -9771,7 +9776,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9783,7 +9788,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -9795,10 +9800,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #16]\n\t"
+        "ldr	r4, [r2, #16]\n\t"
         "ldr	r5, [r2, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #16]\n\t"
+        "ldrd	r4, r5, [r2, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #16]\n\t"
@@ -9807,7 +9812,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9819,7 +9824,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -9831,10 +9836,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #24]\n\t"
+        "ldr	r4, [r2, #24]\n\t"
         "ldr	r5, [r2, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #24]\n\t"
+        "ldrd	r4, r5, [r2, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -9843,61 +9848,61 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -9906,54 +9911,54 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -9967,10 +9972,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         /* Add-Sub */
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2]\n\t"
+        "ldr	r4, [r2]\n\t"
         "ldr	r5, [r2, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2]\n\t"
+        "ldrd	r4, r5, [r2]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0]\n\t"
@@ -9978,7 +9983,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #else
         "ldrd	r6, r7, [r0]\n\t"
 #endif
-        "adds	r8, %[rt], r6\n\t"
+        "adds	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -9989,7 +9994,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0]\n\t"
 #endif
         /*  Sub */
-        "subs	r10, %[rt], r6\n\t"
+        "subs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -10001,10 +10006,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #8]\n\t"
+        "ldr	r4, [r2, #8]\n\t"
         "ldr	r5, [r2, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #8]\n\t"
+        "ldrd	r4, r5, [r2, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #8]\n\t"
@@ -10013,7 +10018,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #8]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -10025,7 +10030,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -10037,10 +10042,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #16]\n\t"
+        "ldr	r4, [r2, #16]\n\t"
         "ldr	r5, [r2, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #16]\n\t"
+        "ldrd	r4, r5, [r2, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #16]\n\t"
@@ -10049,7 +10054,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #16]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "mov	r12, #0\n\t"
         "adcs	r9, r5, r7\n\t"
         "adc	r12, r12, #0\n\t"
@@ -10061,7 +10066,7 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "mov	lr, #0\n\t"
         "sbcs	r11, r5, r7\n\t"
         "adc	lr, lr, #0\n\t"
@@ -10073,10 +10078,10 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
 #endif
         /*  Add */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r2, #24]\n\t"
+        "ldr	r4, [r2, #24]\n\t"
         "ldr	r5, [r2, #28]\n\t"
 #else
-        "ldrd	%[rt], r5, [r2, #24]\n\t"
+        "ldrd	r4, r5, [r2, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [r0, #24]\n\t"
@@ -10085,61 +10090,61 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "ldrd	r6, r7, [r0, #24]\n\t"
 #endif
         "adds	r12, r12, #-1\n\t"
-        "adcs	r8, %[rt], r6\n\t"
+        "adcs	r8, r4, r6\n\t"
         "adc	r9, r5, r7\n\t"
         /*  Sub */
         "adds	lr, lr, #-1\n\t"
-        "sbcs	r10, %[rt], r6\n\t"
+        "sbcs	r10, r4, r6\n\t"
         "sbc	r11, r5, r7\n\t"
         "mov	r12, #-19\n\t"
-        "asr	r4, r9, #31\n\t"
+        "asr	%[rt], r9, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Sub modulus (if overflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0]\n\t"
+        "ldr	r4, [r0]\n\t"
         "ldr	r5, [r0, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0]\n\t"
+        "ldrd	r4, r5, [r0]\n\t"
 #endif
-        "subs	%[rt], %[rt], r12\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "subs	r4, r4, r12\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0]\n\t"
+        "str	r4, [r0]\n\t"
         "str	r5, [r0, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r0]\n\t"
+        "strd	r4, r5, [r0]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #8]\n\t"
+        "ldr	r4, [r0, #8]\n\t"
         "ldr	r5, [r0, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #8]\n\t"
+        "ldrd	r4, r5, [r0, #8]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #8]\n\t"
+        "str	r4, [r0, #8]\n\t"
         "str	r5, [r0, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #8]\n\t"
+        "strd	r4, r5, [r0, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r0, #16]\n\t"
+        "ldr	r4, [r0, #16]\n\t"
         "ldr	r5, [r0, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r0, #16]\n\t"
+        "ldrd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	%[rt], %[rt], r4\n\t"
-        "sbcs	r5, r5, r4\n\t"
+        "sbcs	r4, r4, %[rt]\n\t"
+        "sbcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r0, #16]\n\t"
+        "str	r4, [r0, #16]\n\t"
         "str	r5, [r0, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r0, #16]\n\t"
+        "strd	r4, r5, [r0, #16]\n\t"
 #endif
-        "sbcs	r8, r8, r4\n\t"
+        "sbcs	r8, r8, %[rt]\n\t"
         "sbc	r9, r9, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r8, [r0, #24]\n\t"
@@ -10148,54 +10153,54 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "strd	r8, r9, [r0, #24]\n\t"
 #endif
         "mov	r12, #-19\n\t"
-        "asr	r4, r11, #31\n\t"
+        "asr	%[rt], r11, #31\n\t"
         /*   Mask the modulus */
-        "and	r12, r4, r12\n\t"
-        "and	lr, r4, #0x7fffffff\n\t"
+        "and	r12, %[rt], r12\n\t"
+        "and	lr, %[rt], #0x7fffffff\n\t"
         /*   Add modulus (if underflow) */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1]\n\t"
+        "ldr	r4, [r1]\n\t"
         "ldr	r5, [r1, #4]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1]\n\t"
+        "ldrd	r4, r5, [r1]\n\t"
 #endif
-        "adds	%[rt], %[rt], r12\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adds	r4, r4, r12\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1]\n\t"
+        "str	r4, [r1]\n\t"
         "str	r5, [r1, #4]\n\t"
 #else
-        "strd	%[rt], r5, [r1]\n\t"
+        "strd	r4, r5, [r1]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #8]\n\t"
+        "ldr	r4, [r1, #8]\n\t"
         "ldr	r5, [r1, #12]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #8]\n\t"
+        "ldrd	r4, r5, [r1, #8]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #8]\n\t"
+        "str	r4, [r1, #8]\n\t"
         "str	r5, [r1, #12]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #8]\n\t"
+        "strd	r4, r5, [r1, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	%[rt], [r1, #16]\n\t"
+        "ldr	r4, [r1, #16]\n\t"
         "ldr	r5, [r1, #20]\n\t"
 #else
-        "ldrd	%[rt], r5, [r1, #16]\n\t"
+        "ldrd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	%[rt], %[rt], r4\n\t"
-        "adcs	r5, r5, r4\n\t"
+        "adcs	r4, r4, %[rt]\n\t"
+        "adcs	r5, r5, %[rt]\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	%[rt], [r1, #16]\n\t"
+        "str	r4, [r1, #16]\n\t"
         "str	r5, [r1, #20]\n\t"
 #else
-        "strd	%[rt], r5, [r1, #16]\n\t"
+        "strd	r4, r5, [r1, #16]\n\t"
 #endif
-        "adcs	r10, r10, r4\n\t"
+        "adcs	r10, r10, %[rt]\n\t"
         "adc	r11, r11, lr\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r10, [r1, #24]\n\t"
@@ -10206,16 +10211,16 @@ void fe_ge_sub(fe rx_p, fe ry_p, fe rz_p, fe rt_p, const fe px_p, const fe py_p,
         "add	sp, sp, #0x60\n\t"
         : [rx] "+r" (rx), [ry] "+r" (ry), [rz] "+r" (rz), [rt] "+r" (rt)
         :
-        : "memory", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11"
+        : "memory", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "lr"
     );
-    (void)px;
-    (void)py;
-    (void)pz;
-    (void)pt;
-    (void)qz;
-    (void)qt2d;
-    (void)qyplusx;
-    (void)qyminusx;
+    (void)px_p;
+    (void)py_p;
+    (void)pz_p;
+    (void)pt_p;
+    (void)qz_p;
+    (void)qt2d_p;
+    (void)qyplusx_p;
+    (void)qyminusx_p;
 }
 
 
diff --git a/wolfcrypt/src/port/arm/armv8-32-sha256-asm.S b/wolfcrypt/src/port/arm/armv8-32-sha256-asm.S
index 92b9cce83..2a4268414 100644
--- a/wolfcrypt/src/port/arm/armv8-32-sha256-asm.S
+++ b/wolfcrypt/src/port/arm/armv8-32-sha256-asm.S
@@ -33,7 +33,7 @@
 	.text
 	.type	L_SHA256_transform_len_k, %object
 	.size	L_SHA256_transform_len_k, 256
-	.align	3
+	.align	4
 L_SHA256_transform_len_k:
 	.word	0x428a2f98
 	.word	0x71374491
@@ -100,1554 +100,1554 @@ L_SHA256_transform_len_k:
 	.word	0xbef9a3f7
 	.word	0xc67178f2
 	.text
-	.align	2
+	.align	4
 	.globl	Transform_Sha256_Len
 	.type	Transform_Sha256_Len, %function
 Transform_Sha256_Len:
-	push	{r4, r5, r6, r7, r8, r9, r10, lr}
+	push	{r4, r5, r6, r7, r8, r9, r10, r11}
 	sub	sp, sp, #0xc0
 	adr	r3, L_SHA256_transform_len_k
 	# Copy digest to add in at end
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
 #else
-	ldrd  r12, lr, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r0, #24]
-	ldr	r9, [r0, #28]
+	ldr	r10, [r0, #24]
+	ldr	r11, [r0, #28]
 #else
-	ldrd  r8, r9, [r0, #24]
+	ldrd	r10, r11, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #64]
-	str	lr, [sp, #68]
+	str	r4, [sp, #64]
+	str	r5, [sp, #68]
 #else
-	strd  r12, lr, [sp, #64]
+	strd	r4, r5, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #72]
-	str	r5, [sp, #76]
+	str	r6, [sp, #72]
+	str	r7, [sp, #76]
 #else
-	strd  r4, r5, [sp, #72]
+	strd	r6, r7, [sp, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [sp, #80]
-	str	r7, [sp, #84]
+	str	r8, [sp, #80]
+	str	r9, [sp, #84]
 #else
-	strd  r6, r7, [sp, #80]
+	strd	r8, r9, [sp, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [sp, #88]
-	str	r9, [sp, #92]
+	str	r10, [sp, #88]
+	str	r11, [sp, #92]
 #else
-	strd  r8, r9, [sp, #88]
+	strd	r10, r11, [sp, #88]
 #endif
 	# Start of loop processing a block
 L_SHA256_transform_len_begin:
 	# Load, Reverse and Store W - 64 bytes
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1]
-	ldr	lr, [r1, #4]
+	ldr	r4, [r1]
+	ldr	r5, [r1, #4]
 #else
-	ldrd  r12, lr, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #8]
-	ldr	r5, [r1, #12]
+	ldr	r6, [r1, #8]
+	ldr	r7, [r1, #12]
 #else
-	ldrd  r4, r5, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #16]
-	ldr	r7, [r1, #20]
+	ldr	r8, [r1, #16]
+	ldr	r9, [r1, #20]
 #else
-	ldrd  r6, r7, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	rev	r12, r12
-	rev	lr, lr
 	rev	r4, r4
 	rev	r5, r5
 	rev	r6, r6
 	rev	r7, r7
 	rev	r8, r8
 	rev	r9, r9
+	rev	r10, r10
+	rev	r11, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp]
-	str	lr, [sp, #4]
+	str	r4, [sp]
+	str	r5, [sp, #4]
 #else
-	strd  r12, lr, [sp]
+	strd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #8]
-	str	r5, [sp, #12]
+	str	r6, [sp, #8]
+	str	r7, [sp, #12]
 #else
-	strd  r4, r5, [sp, #8]
+	strd	r6, r7, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [sp, #16]
-	str	r7, [sp, #20]
+	str	r8, [sp, #16]
+	str	r9, [sp, #20]
 #else
-	strd  r6, r7, [sp, #16]
+	strd	r8, r9, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [sp, #24]
-	str	r9, [sp, #28]
+	str	r10, [sp, #24]
+	str	r11, [sp, #28]
 #else
-	strd  r8, r9, [sp, #24]
+	strd	r10, r11, [sp, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #32]
-	ldr	lr, [r1, #36]
+	ldr	r4, [r1, #32]
+	ldr	r5, [r1, #36]
 #else
-	ldrd  r12, lr, [r1, #32]
+	ldrd	r4, r5, [r1, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #40]
-	ldr	r5, [r1, #44]
+	ldr	r6, [r1, #40]
+	ldr	r7, [r1, #44]
 #else
-	ldrd  r4, r5, [r1, #40]
+	ldrd	r6, r7, [r1, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #48]
-	ldr	r7, [r1, #52]
+	ldr	r8, [r1, #48]
+	ldr	r9, [r1, #52]
 #else
-	ldrd  r6, r7, [r1, #48]
+	ldrd	r8, r9, [r1, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #56]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	rev	r12, r12
-	rev	lr, lr
 	rev	r4, r4
 	rev	r5, r5
 	rev	r6, r6
 	rev	r7, r7
 	rev	r8, r8
 	rev	r9, r9
+	rev	r10, r10
+	rev	r11, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #32]
-	str	lr, [sp, #36]
+	str	r4, [sp, #32]
+	str	r5, [sp, #36]
 #else
-	strd  r12, lr, [sp, #32]
+	strd	r4, r5, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #40]
-	str	r5, [sp, #44]
+	str	r6, [sp, #40]
+	str	r7, [sp, #44]
 #else
-	strd  r4, r5, [sp, #40]
+	strd	r6, r7, [sp, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [sp, #48]
-	str	r7, [sp, #52]
+	str	r8, [sp, #48]
+	str	r9, [sp, #52]
 #else
-	strd  r6, r7, [sp, #48]
+	strd	r8, r9, [sp, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [sp, #56]
-	str	r9, [sp, #60]
+	str	r10, [sp, #56]
+	str	r11, [sp, #60]
 #else
-	strd  r8, r9, [sp, #56]
+	strd	r10, r11, [sp, #56]
 #endif
-	ldr	r9, [r0, #4]
-	ldr	r12, [r0, #8]
-	eor	r9, r9, r12
-	mov	r10, #3
+	ldr	r11, [r0, #4]
+	ldr	r4, [r0, #8]
+	eor	r11, r11, r4
+	mov	r12, #3
 	# Start of 16 rounds
 L_SHA256_transform_len_start:
 	# Round 0
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r7, [r0, #28]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp]
-	ldr	r4, [r3]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r6, [r0, #12]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #12]
-	str	r7, [r0, #28]
-	# Calc new W[0]
-	ldr	r4, [sp, #56]
-	ldr	r5, [sp, #36]
-	ldr	r6, [sp, #4]
-	ldr	r7, [sp]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp]
-	# Round 1
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r7, [r0, #24]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #4]
-	ldr	r4, [r3, #4]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-	ldr	r6, [r0, #8]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #8]
-	str	r7, [r0, #24]
-	# Calc new W[1]
-	ldr	r4, [sp, #60]
-	ldr	r5, [sp, #40]
-	ldr	r6, [sp, #8]
-	ldr	r7, [sp, #4]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #4]
-	# Round 2
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
-	ldr	r5, [r0, #16]
-	ldr	r7, [r0, #20]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #8]
-	ldr	r4, [r3, #8]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
-	ldr	r5, [r0]
-	ldr	r6, [r0, #4]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #4]
-	str	r7, [r0, #20]
-	# Calc new W[2]
-	ldr	r4, [sp]
-	ldr	r5, [sp, #44]
-	ldr	r6, [sp, #12]
-	ldr	r7, [sp, #8]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #8]
-	# Round 3
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-	ldr	r7, [r0, #16]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #12]
-	ldr	r4, [r3, #12]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r6, [r0]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0]
-	str	r7, [r0, #16]
-	# Calc new W[3]
-	ldr	r4, [sp, #4]
-	ldr	r5, [sp, #48]
-	ldr	r6, [sp, #16]
-	ldr	r7, [sp, #12]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #12]
-	# Round 4
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r7, [r0, #12]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #16]
-	ldr	r4, [r3, #16]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r6, [r0, #28]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #28]
-	str	r7, [r0, #12]
-	# Calc new W[4]
-	ldr	r4, [sp, #8]
-	ldr	r5, [sp, #52]
-	ldr	r6, [sp, #20]
-	ldr	r7, [sp, #16]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #16]
-	# Round 5
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-	ldr	r7, [r0, #8]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #20]
-	ldr	r4, [r3, #20]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r6, [r0, #24]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #24]
-	str	r7, [r0, #8]
-	# Calc new W[5]
-	ldr	r4, [sp, #12]
-	ldr	r5, [sp, #56]
-	ldr	r6, [sp, #24]
-	ldr	r7, [sp, #20]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #20]
-	# Round 6
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
-	ldr	r5, [r0]
-	ldr	r7, [r0, #4]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #24]
-	ldr	r4, [r3, #24]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
 	ldr	r5, [r0, #16]
 	ldr	r6, [r0, #20]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #20]
-	str	r7, [r0, #4]
-	# Calc new W[6]
-	ldr	r4, [sp, #16]
-	ldr	r5, [sp, #60]
-	ldr	r6, [sp, #28]
-	ldr	r7, [sp, #24]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #24]
-	# Round 7
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r7, [r0]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #28]
-	ldr	r4, [r3, #28]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-	ldr	r6, [r0, #16]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #16]
-	str	r7, [r0]
-	# Calc new W[7]
-	ldr	r4, [sp, #20]
+	ldr	r7, [r0, #24]
+	ldr	r9, [r0, #28]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
 	ldr	r5, [sp]
-	ldr	r6, [sp, #32]
-	ldr	r7, [sp, #28]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #28]
-	# Round 8
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r7, [r0, #28]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #32]
-	ldr	r4, [r3, #32]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r6, [r0, #12]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #12]
-	str	r7, [r0, #28]
-	# Calc new W[8]
-	ldr	r4, [sp, #24]
-	ldr	r5, [sp, #4]
-	ldr	r6, [sp, #36]
-	ldr	r7, [sp, #32]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #32]
-	# Round 9
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r7, [r0, #24]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #36]
-	ldr	r4, [r3, #36]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-	ldr	r6, [r0, #8]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #8]
-	str	r7, [r0, #24]
-	# Calc new W[9]
-	ldr	r4, [sp, #28]
-	ldr	r5, [sp, #8]
-	ldr	r6, [sp, #40]
-	ldr	r7, [sp, #36]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #36]
-	# Round 10
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
-	ldr	r5, [r0, #16]
-	ldr	r7, [r0, #20]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #40]
-	ldr	r4, [r3, #40]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
+	ldr	r6, [r3]
+	add	r9, r9, r5
+	add	r9, r9, r6
 	ldr	r5, [r0]
 	ldr	r6, [r0, #4]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #4]
-	str	r7, [r0, #20]
-	# Calc new W[10]
-	ldr	r4, [sp, #32]
-	ldr	r5, [sp, #12]
-	ldr	r6, [sp, #44]
-	ldr	r7, [sp, #40]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #40]
-	# Round 11
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-	ldr	r7, [r0, #16]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #44]
-	ldr	r4, [r3, #44]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r6, [r0]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0]
-	str	r7, [r0, #16]
-	# Calc new W[11]
-	ldr	r4, [sp, #36]
-	ldr	r5, [sp, #16]
-	ldr	r6, [sp, #48]
-	ldr	r7, [sp, #44]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #44]
-	# Round 12
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r7, [r0, #12]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #48]
-	ldr	r4, [r3, #48]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r6, [r0, #28]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #28]
-	str	r7, [r0, #12]
-	# Calc new W[12]
-	ldr	r4, [sp, #40]
-	ldr	r5, [sp, #20]
-	ldr	r6, [sp, #52]
-	ldr	r7, [sp, #48]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #48]
-	# Round 13
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
 	ldr	r7, [r0, #8]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #52]
-	ldr	r4, [r3, #52]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r6, [r0, #24]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #24]
-	str	r7, [r0, #8]
-	# Calc new W[13]
-	ldr	r4, [sp, #44]
-	ldr	r5, [sp, #24]
+	ldr	r8, [r0, #12]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #12]
+	str	r9, [r0, #28]
+	# Calc new W[0]
 	ldr	r6, [sp, #56]
-	ldr	r7, [sp, #52]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #52]
-	# Round 14
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
-	ldr	r5, [r0]
-	ldr	r7, [r0, #4]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #56]
-	ldr	r4, [r3, #56]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
-	ldr	r5, [r0, #16]
-	ldr	r6, [r0, #20]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #20]
-	str	r7, [r0, #4]
-	# Calc new W[14]
-	ldr	r4, [sp, #48]
-	ldr	r5, [sp, #28]
-	ldr	r6, [sp, #60]
-	ldr	r7, [sp, #56]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #56]
-	# Round 15
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r7, [r0]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #60]
-	ldr	r4, [r3, #60]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
+	ldr	r7, [sp, #36]
+	ldr	r8, [sp, #4]
+	ldr	r9, [sp]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp]
+	# Round 1
 	ldr	r5, [r0, #12]
 	ldr	r6, [r0, #16]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #16]
-	str	r7, [r0]
-	# Calc new W[15]
-	ldr	r4, [sp, #52]
-	ldr	r5, [sp, #32]
+	ldr	r7, [r0, #20]
+	ldr	r9, [r0, #24]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #4]
+	ldr	r6, [r3, #4]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r8, [r0, #8]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #8]
+	str	r9, [r0, #24]
+	# Calc new W[1]
+	ldr	r6, [sp, #60]
+	ldr	r7, [sp, #40]
+	ldr	r8, [sp, #8]
+	ldr	r9, [sp, #4]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #4]
+	# Round 2
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r9, [r0, #20]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #8]
+	ldr	r6, [r3, #8]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r8, [r0, #4]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #4]
+	str	r9, [r0, #20]
+	# Calc new W[2]
 	ldr	r6, [sp]
+	ldr	r7, [sp, #44]
+	ldr	r8, [sp, #12]
+	ldr	r9, [sp, #8]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #8]
+	# Round 3
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r9, [r0, #16]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #12]
+	ldr	r6, [r3, #12]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r8, [r0]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0]
+	str	r9, [r0, #16]
+	# Calc new W[3]
+	ldr	r6, [sp, #4]
+	ldr	r7, [sp, #48]
+	ldr	r8, [sp, #16]
+	ldr	r9, [sp, #12]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #12]
+	# Round 4
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r9, [r0, #12]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #16]
+	ldr	r6, [r3, #16]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #16]
+	ldr	r6, [r0, #20]
+	ldr	r7, [r0, #24]
+	ldr	r8, [r0, #28]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #28]
+	str	r9, [r0, #12]
+	# Calc new W[4]
+	ldr	r6, [sp, #8]
+	ldr	r7, [sp, #52]
+	ldr	r8, [sp, #20]
+	ldr	r9, [sp, #16]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #16]
+	# Round 5
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r9, [r0, #8]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #20]
+	ldr	r6, [r3, #20]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+	ldr	r8, [r0, #24]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #24]
+	str	r9, [r0, #8]
+	# Calc new W[5]
+	ldr	r6, [sp, #12]
+	ldr	r7, [sp, #56]
+	ldr	r8, [sp, #24]
+	ldr	r9, [sp, #20]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #20]
+	# Round 6
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r9, [r0, #4]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #24]
+	ldr	r6, [r3, #24]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r8, [r0, #20]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #20]
+	str	r9, [r0, #4]
+	# Calc new W[6]
+	ldr	r6, [sp, #16]
 	ldr	r7, [sp, #60]
-	ror	r12, r4, #17
-	ror	lr, r6, #7
-	eor	r12, r12, r4, ror #19
-	eor	lr, lr, r6, ror #18
-	eor	r12, r12, r4, lsr #10
-	eor	lr, lr, r6, lsr #3
-	add	r7, r7, r5
-	add	r12, r12, lr
-	add	r7, r7, r12
-	str	r7, [sp, #60]
+	ldr	r8, [sp, #28]
+	ldr	r9, [sp, #24]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #24]
+	# Round 7
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r9, [r0]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #28]
+	ldr	r6, [r3, #28]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r8, [r0, #16]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #16]
+	str	r9, [r0]
+	# Calc new W[7]
+	ldr	r6, [sp, #20]
+	ldr	r7, [sp]
+	ldr	r8, [sp, #32]
+	ldr	r9, [sp, #28]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #28]
+	# Round 8
+	ldr	r5, [r0, #16]
+	ldr	r6, [r0, #20]
+	ldr	r7, [r0, #24]
+	ldr	r9, [r0, #28]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #32]
+	ldr	r6, [r3, #32]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r8, [r0, #12]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #12]
+	str	r9, [r0, #28]
+	# Calc new W[8]
+	ldr	r6, [sp, #24]
+	ldr	r7, [sp, #4]
+	ldr	r8, [sp, #36]
+	ldr	r9, [sp, #32]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #32]
+	# Round 9
+	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+	ldr	r9, [r0, #24]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #36]
+	ldr	r6, [r3, #36]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r8, [r0, #8]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #8]
+	str	r9, [r0, #24]
+	# Calc new W[9]
+	ldr	r6, [sp, #28]
+	ldr	r7, [sp, #8]
+	ldr	r8, [sp, #40]
+	ldr	r9, [sp, #36]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #36]
+	# Round 10
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r9, [r0, #20]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #40]
+	ldr	r6, [r3, #40]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r8, [r0, #4]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #4]
+	str	r9, [r0, #20]
+	# Calc new W[10]
+	ldr	r6, [sp, #32]
+	ldr	r7, [sp, #12]
+	ldr	r8, [sp, #44]
+	ldr	r9, [sp, #40]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #40]
+	# Round 11
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r9, [r0, #16]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #44]
+	ldr	r6, [r3, #44]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r8, [r0]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0]
+	str	r9, [r0, #16]
+	# Calc new W[11]
+	ldr	r6, [sp, #36]
+	ldr	r7, [sp, #16]
+	ldr	r8, [sp, #48]
+	ldr	r9, [sp, #44]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #44]
+	# Round 12
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r9, [r0, #12]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #48]
+	ldr	r6, [r3, #48]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #16]
+	ldr	r6, [r0, #20]
+	ldr	r7, [r0, #24]
+	ldr	r8, [r0, #28]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #28]
+	str	r9, [r0, #12]
+	# Calc new W[12]
+	ldr	r6, [sp, #40]
+	ldr	r7, [sp, #20]
+	ldr	r8, [sp, #52]
+	ldr	r9, [sp, #48]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #48]
+	# Round 13
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r9, [r0, #8]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #52]
+	ldr	r6, [r3, #52]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+	ldr	r8, [r0, #24]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #24]
+	str	r9, [r0, #8]
+	# Calc new W[13]
+	ldr	r6, [sp, #44]
+	ldr	r7, [sp, #24]
+	ldr	r8, [sp, #56]
+	ldr	r9, [sp, #52]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #52]
+	# Round 14
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r9, [r0, #4]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #56]
+	ldr	r6, [r3, #56]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r8, [r0, #20]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #20]
+	str	r9, [r0, #4]
+	# Calc new W[14]
+	ldr	r6, [sp, #48]
+	ldr	r7, [sp, #28]
+	ldr	r8, [sp, #60]
+	ldr	r9, [sp, #56]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #56]
+	# Round 15
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r9, [r0]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #60]
+	ldr	r6, [r3, #60]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r8, [r0, #16]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #16]
+	str	r9, [r0]
+	# Calc new W[15]
+	ldr	r6, [sp, #52]
+	ldr	r7, [sp, #32]
+	ldr	r8, [sp]
+	ldr	r9, [sp, #60]
+	ror	r4, r6, #17
+	ror	r5, r8, #7
+	eor	r4, r4, r6, ror #19
+	eor	r5, r5, r8, ror #18
+	eor	r4, r4, r6, lsr #10
+	eor	r5, r5, r8, lsr #3
+	add	r9, r9, r7
+	add	r4, r4, r5
+	add	r9, r9, r4
+	str	r9, [sp, #60]
 	add	r3, r3, #0x40
-	subs	r10, r10, #1
+	subs	r12, r12, #1
 	bne	L_SHA256_transform_len_start
 	# Round 0
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r7, [r0, #28]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp]
-	ldr	r4, [r3]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r6, [r0, #12]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #12]
-	str	r7, [r0, #28]
+	ldr	r5, [r0, #16]
+	ldr	r6, [r0, #20]
+	ldr	r7, [r0, #24]
+	ldr	r9, [r0, #28]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp]
+	ldr	r6, [r3]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r8, [r0, #12]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #12]
+	str	r9, [r0, #28]
 	# Round 1
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r7, [r0, #24]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #4]
-	ldr	r4, [r3, #4]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-	ldr	r6, [r0, #8]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #8]
-	str	r7, [r0, #24]
-	# Round 2
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
-	ldr	r5, [r0, #16]
-	ldr	r7, [r0, #20]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #8]
-	ldr	r4, [r3, #8]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
-	ldr	r5, [r0]
-	ldr	r6, [r0, #4]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #4]
-	str	r7, [r0, #20]
-	# Round 3
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-	ldr	r7, [r0, #16]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #12]
-	ldr	r4, [r3, #12]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r6, [r0]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0]
-	str	r7, [r0, #16]
-	# Round 4
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r7, [r0, #12]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #16]
-	ldr	r4, [r3, #16]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r6, [r0, #28]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #28]
-	str	r7, [r0, #12]
-	# Round 5
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-	ldr	r7, [r0, #8]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #20]
-	ldr	r4, [r3, #20]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r6, [r0, #24]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #24]
-	str	r7, [r0, #8]
-	# Round 6
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
-	ldr	r5, [r0]
-	ldr	r7, [r0, #4]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #24]
-	ldr	r4, [r3, #24]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
-	ldr	r5, [r0, #16]
-	ldr	r6, [r0, #20]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #20]
-	str	r7, [r0, #4]
-	# Round 7
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r7, [r0]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #28]
-	ldr	r4, [r3, #28]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 	ldr	r6, [r0, #16]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #16]
-	str	r7, [r0]
-	# Round 8
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
-	ldr	r5, [r0, #24]
-	ldr	r7, [r0, #28]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #32]
-	ldr	r4, [r3, #32]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
+	ldr	r7, [r0, #20]
+	ldr	r9, [r0, #24]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #4]
+	ldr	r6, [r3, #4]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r8, [r0, #8]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #8]
+	str	r9, [r0, #24]
+	# Round 2
 	ldr	r5, [r0, #8]
 	ldr	r6, [r0, #12]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #12]
-	str	r7, [r0, #28]
-	# Round 9
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-	ldr	r7, [r0, #24]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #36]
-	ldr	r4, [r3, #36]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-	ldr	r6, [r0, #8]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #8]
-	str	r7, [r0, #24]
-	# Round 10
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
-	ldr	r5, [r0, #16]
-	ldr	r7, [r0, #20]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #40]
-	ldr	r4, [r3, #40]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
-	ldr	r5, [r0]
-	ldr	r6, [r0, #4]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #4]
-	str	r7, [r0, #20]
-	# Round 11
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
 	ldr	r7, [r0, #16]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #44]
-	ldr	r4, [r3, #44]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-	ldr	r6, [r0]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0]
-	str	r7, [r0, #16]
-	# Round 12
-	ldr	lr, [r0]
-	ldr	r4, [r0, #4]
-	ldr	r5, [r0, #8]
-	ldr	r7, [r0, #12]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #48]
-	ldr	r4, [r3, #48]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #16]
-	ldr	r4, [r0, #20]
+	ldr	r9, [r0, #20]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #8]
+	ldr	r6, [r3, #8]
+	add	r9, r9, r5
+	add	r9, r9, r6
 	ldr	r5, [r0, #24]
 	ldr	r6, [r0, #28]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #28]
-	str	r7, [r0, #12]
-	# Round 13
-	ldr	lr, [r0, #28]
-	ldr	r4, [r0]
+	ldr	r7, [r0]
+	ldr	r8, [r0, #4]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #4]
+	str	r9, [r0, #20]
+	# Round 3
 	ldr	r5, [r0, #4]
-	ldr	r7, [r0, #8]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #52]
-	ldr	r4, [r3, #52]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #12]
-	ldr	r4, [r0, #16]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r9, [r0, #16]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #12]
+	ldr	r6, [r3, #12]
+	add	r9, r9, r5
+	add	r9, r9, r6
 	ldr	r5, [r0, #20]
 	ldr	r6, [r0, #24]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #24]
-	str	r7, [r0, #8]
-	# Round 14
-	ldr	lr, [r0, #24]
-	ldr	r4, [r0, #28]
+	ldr	r7, [r0, #28]
+	ldr	r8, [r0]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0]
+	str	r9, [r0, #16]
+	# Round 4
 	ldr	r5, [r0]
-	ldr	r7, [r0, #4]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #56]
-	ldr	r4, [r3, #56]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #8]
-	ldr	r4, [r0, #12]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r9, [r0, #12]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #16]
+	ldr	r6, [r3, #16]
+	add	r9, r9, r5
+	add	r9, r9, r6
 	ldr	r5, [r0, #16]
 	ldr	r6, [r0, #20]
-	ror	r12, lr, #2
-	eor	r8, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r9, r9, r8
-	eor	r12, r12, lr, ror #22
-	eor	r9, r9, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r9
-	str	r6, [r0, #20]
-	str	r7, [r0, #4]
-	# Round 15
-	ldr	lr, [r0, #20]
-	ldr	r4, [r0, #24]
+	ldr	r7, [r0, #24]
+	ldr	r8, [r0, #28]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #28]
+	str	r9, [r0, #12]
+	# Round 5
 	ldr	r5, [r0, #28]
-	ldr	r7, [r0]
-	ror	r12, lr, #6
-	eor	r4, r4, r5
-	eor	r12, r12, lr, ror #11
-	and	r4, r4, lr
-	eor	r12, r12, lr, ror #25
-	eor	r4, r4, r5
-	add	r7, r7, r12
-	add	r7, r7, r4
-	ldr	lr, [sp, #60]
-	ldr	r4, [r3, #60]
-	add	r7, r7, lr
-	add	r7, r7, r4
-	ldr	lr, [r0, #4]
-	ldr	r4, [r0, #8]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r9, [r0, #8]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #20]
+	ldr	r6, [r3, #20]
+	add	r9, r9, r5
+	add	r9, r9, r6
 	ldr	r5, [r0, #12]
 	ldr	r6, [r0, #16]
-	ror	r12, lr, #2
-	eor	r9, lr, r4
-	eor	r12, r12, lr, ror #13
-	and	r8, r8, r9
-	eor	r12, r12, lr, ror #22
-	eor	r8, r8, r4
-	add	r6, r6, r7
-	add	r7, r7, r12
-	add	r7, r7, r8
-	str	r6, [r0, #16]
-	str	r7, [r0]
+	ldr	r7, [r0, #20]
+	ldr	r8, [r0, #24]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #24]
+	str	r9, [r0, #8]
+	# Round 6
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r9, [r0, #4]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #24]
+	ldr	r6, [r3, #24]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r8, [r0, #20]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #20]
+	str	r9, [r0, #4]
+	# Round 7
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r9, [r0]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #28]
+	ldr	r6, [r3, #28]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r8, [r0, #16]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #16]
+	str	r9, [r0]
+	# Round 8
+	ldr	r5, [r0, #16]
+	ldr	r6, [r0, #20]
+	ldr	r7, [r0, #24]
+	ldr	r9, [r0, #28]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #32]
+	ldr	r6, [r3, #32]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r8, [r0, #12]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #12]
+	str	r9, [r0, #28]
+	# Round 9
+	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+	ldr	r9, [r0, #24]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #36]
+	ldr	r6, [r3, #36]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r8, [r0, #8]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #8]
+	str	r9, [r0, #24]
+	# Round 10
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r9, [r0, #20]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #40]
+	ldr	r6, [r3, #40]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r8, [r0, #4]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #4]
+	str	r9, [r0, #20]
+	# Round 11
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r9, [r0, #16]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #44]
+	ldr	r6, [r3, #44]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r8, [r0]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0]
+	str	r9, [r0, #16]
+	# Round 12
+	ldr	r5, [r0]
+	ldr	r6, [r0, #4]
+	ldr	r7, [r0, #8]
+	ldr	r9, [r0, #12]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #48]
+	ldr	r6, [r3, #48]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #16]
+	ldr	r6, [r0, #20]
+	ldr	r7, [r0, #24]
+	ldr	r8, [r0, #28]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #28]
+	str	r9, [r0, #12]
+	# Round 13
+	ldr	r5, [r0, #28]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+	ldr	r9, [r0, #8]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #52]
+	ldr	r6, [r3, #52]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+	ldr	r8, [r0, #24]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #24]
+	str	r9, [r0, #8]
+	# Round 14
+	ldr	r5, [r0, #24]
+	ldr	r6, [r0, #28]
+	ldr	r7, [r0]
+	ldr	r9, [r0, #4]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #56]
+	ldr	r6, [r3, #56]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #8]
+	ldr	r6, [r0, #12]
+	ldr	r7, [r0, #16]
+	ldr	r8, [r0, #20]
+	ror	r4, r5, #2
+	eor	r10, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r11, r11, r10
+	eor	r4, r4, r5, ror #22
+	eor	r11, r11, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r11
+	str	r8, [r0, #20]
+	str	r9, [r0, #4]
+	# Round 15
+	ldr	r5, [r0, #20]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+	ldr	r9, [r0]
+	ror	r4, r5, #6
+	eor	r6, r6, r7
+	eor	r4, r4, r5, ror #11
+	and	r6, r6, r5
+	eor	r4, r4, r5, ror #25
+	eor	r6, r6, r7
+	add	r9, r9, r4
+	add	r9, r9, r6
+	ldr	r5, [sp, #60]
+	ldr	r6, [r3, #60]
+	add	r9, r9, r5
+	add	r9, r9, r6
+	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+	ldr	r8, [r0, #16]
+	ror	r4, r5, #2
+	eor	r11, r5, r6
+	eor	r4, r4, r5, ror #13
+	and	r10, r10, r11
+	eor	r4, r4, r5, ror #22
+	eor	r10, r10, r6
+	add	r8, r8, r9
+	add	r9, r9, r4
+	add	r9, r9, r10
+	str	r8, [r0, #16]
+	str	r9, [r0]
 	# Add in digest from start
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
 #else
-	ldrd  r12, lr, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #64]
-	ldr	r7, [sp, #68]
+	ldr	r8, [sp, #64]
+	ldr	r9, [sp, #68]
 #else
-	ldrd  r6, r7, [sp, #64]
+	ldrd	r8, r9, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [sp, #72]
-	ldr	r9, [sp, #76]
+	ldr	r10, [sp, #72]
+	ldr	r11, [sp, #76]
 #else
-	ldrd  r8, r9, [sp, #72]
+	ldrd	r10, r11, [sp, #72]
 #endif
-	add	r12, r12, r6
-	add	lr, lr, r7
 	add	r4, r4, r8
 	add	r5, r5, r9
+	add	r6, r6, r10
+	add	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
+	str	r4, [r0]
+	str	r5, [r0, #4]
 #else
-	strd  r12, lr, [r0]
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #8]
-	str	r5, [r0, #12]
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #64]
-	str	lr, [sp, #68]
+	str	r4, [sp, #64]
+	str	r5, [sp, #68]
 #else
-	strd  r12, lr, [sp, #64]
+	strd	r4, r5, [sp, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #72]
-	str	r5, [sp, #76]
+	str	r6, [sp, #72]
+	str	r7, [sp, #76]
 #else
-	strd  r4, r5, [sp, #72]
+	strd	r6, r7, [sp, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
 #else
-	ldrd  r12, lr, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
 #else
-	ldrd  r4, r5, [r0, #24]
+	ldrd	r6, r7, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #80]
-	ldr	r7, [sp, #84]
+	ldr	r8, [sp, #80]
+	ldr	r9, [sp, #84]
 #else
-	ldrd  r6, r7, [sp, #80]
+	ldrd	r8, r9, [sp, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [sp, #88]
-	ldr	r9, [sp, #92]
+	ldr	r10, [sp, #88]
+	ldr	r11, [sp, #92]
 #else
-	ldrd  r8, r9, [sp, #88]
+	ldrd	r10, r11, [sp, #88]
 #endif
-	add	r12, r12, r6
-	add	lr, lr, r7
 	add	r4, r4, r8
 	add	r5, r5, r9
+	add	r6, r6, r10
+	add	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
 #else
-	strd  r12, lr, [r0, #16]
+	strd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #24]
-	str	r5, [r0, #28]
+	str	r6, [r0, #24]
+	str	r7, [r0, #28]
 #else
-	strd  r4, r5, [r0, #24]
+	strd	r6, r7, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #80]
-	str	lr, [sp, #84]
+	str	r4, [sp, #80]
+	str	r5, [sp, #84]
 #else
-	strd  r12, lr, [sp, #80]
+	strd	r4, r5, [sp, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #88]
-	str	r5, [sp, #92]
+	str	r6, [sp, #88]
+	str	r7, [sp, #92]
 #else
-	strd  r4, r5, [sp, #88]
+	strd	r6, r7, [sp, #88]
 #endif
 	subs	r2, r2, #0x40
 	sub	r3, r3, #0xc0
@@ -1661,7 +1661,7 @@ L_SHA256_transform_len_start:
 	.text
 	.type	L_SHA256_transform_neon_len_k, %object
 	.size	L_SHA256_transform_neon_len_k, 256
-	.align	3
+	.align	4
 L_SHA256_transform_neon_len_k:
 	.word	0x428a2f98
 	.word	0x71374491
@@ -1728,7 +1728,7 @@ L_SHA256_transform_neon_len_k:
 	.word	0xbef9a3f7
 	.word	0xc67178f2
 	.text
-	.align	2
+	.align	4
 	.fpu	neon
 	.globl	Transform_Sha256_Len
 	.type	Transform_Sha256_Len, %function
@@ -1740,7 +1740,7 @@ Transform_Sha256_Len:
 	str	r0, [sp]
 	str	r1, [sp, #4]
 #else
-	strd  r0, r1, [sp]
+	strd	r0, r1, [sp]
 #endif
 	str	r2, [sp, #8]
 	adr	r12, L_SHA256_transform_neon_len_k
@@ -1749,25 +1749,25 @@ Transform_Sha256_Len:
 	ldr	r2, [r0]
 	ldr	r3, [r0, #4]
 #else
-	ldrd  r2, r3, [r0]
+	ldrd	r2, r3, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #8]
 	ldr	r5, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #16]
 	ldr	r7, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r6, r7, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r8, [r0, #24]
 	ldr	r9, [r0, #28]
 #else
-	ldrd  r8, r9, [r0, #24]
+	ldrd	r8, r9, [r0, #24]
 #endif
 	# Start of loop processing a block
 L_SHA256_transform_neon_len_begin:
@@ -2698,7 +2698,7 @@ L_SHA256_transform_neon_len_start:
 	ldr	r0, [r10]
 	ldr	r1, [r10, #4]
 #else
-	ldrd  r0, r1, [r10]
+	ldrd	r0, r1, [r10]
 #endif
 	add	r2, r2, r0
 	add	r3, r3, r1
@@ -2706,13 +2706,13 @@ L_SHA256_transform_neon_len_start:
 	str	r2, [r10]
 	str	r3, [r10, #4]
 #else
-	strd  r2, r3, [r10]
+	strd	r2, r3, [r10]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r0, [r10, #8]
 	ldr	r1, [r10, #12]
 #else
-	ldrd  r0, r1, [r10, #8]
+	ldrd	r0, r1, [r10, #8]
 #endif
 	add	r4, r4, r0
 	add	r5, r5, r1
@@ -2720,13 +2720,13 @@ L_SHA256_transform_neon_len_start:
 	str	r4, [r10, #8]
 	str	r5, [r10, #12]
 #else
-	strd  r4, r5, [r10, #8]
+	strd	r4, r5, [r10, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r0, [r10, #16]
 	ldr	r1, [r10, #20]
 #else
-	ldrd  r0, r1, [r10, #16]
+	ldrd	r0, r1, [r10, #16]
 #endif
 	add	r6, r6, r0
 	add	r7, r7, r1
@@ -2734,13 +2734,13 @@ L_SHA256_transform_neon_len_start:
 	str	r6, [r10, #16]
 	str	r7, [r10, #20]
 #else
-	strd  r6, r7, [r10, #16]
+	strd	r6, r7, [r10, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r0, [r10, #24]
 	ldr	r1, [r10, #28]
 #else
-	ldrd  r0, r1, [r10, #24]
+	ldrd	r0, r1, [r10, #24]
 #endif
 	add	r8, r8, r0
 	add	r9, r9, r1
@@ -2748,7 +2748,7 @@ L_SHA256_transform_neon_len_start:
 	str	r8, [r10, #24]
 	str	r9, [r10, #28]
 #else
-	strd  r8, r9, [r10, #24]
+	strd	r8, r9, [r10, #24]
 #endif
 	ldr	r10, [sp, #8]
 	ldr	r1, [sp, #4]
diff --git a/wolfcrypt/src/port/arm/armv8-32-sha256-asm_c.c b/wolfcrypt/src/port/arm/armv8-32-sha256-asm_c.c
index 5d6981e15..9f14244a4 100644
--- a/wolfcrypt/src/port/arm/armv8-32-sha256-asm_c.c
+++ b/wolfcrypt/src/port/arm/armv8-32-sha256-asm_c.c
@@ -116,1547 +116,1547 @@ void Transform_Sha256_Len(wc_Sha256* sha256_p, const byte* data_p, word32 len_p)
         "mov	r3, %[L_SHA256_transform_len_k]\n\t"
         /* Copy digest to add in at end */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha256]]\n\t"
-        "ldr	lr, [%[sha256], #4]\n\t"
+        "ldr	r4, [%[sha256]]\n\t"
+        "ldr	r5, [%[sha256], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha256]]\n\t"
+        "ldrd	r4, r5, [%[sha256]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha256], #8]\n\t"
+        "ldrd	r6, r7, [%[sha256], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha256], #16]\n\t"
-        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r8, [%[sha256], #16]\n\t"
+        "ldr	r9, [%[sha256], #20]\n\t"
 #else
-        "ldrd	r6, r7, [%[sha256], #16]\n\t"
+        "ldrd	r8, r9, [%[sha256], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[sha256], #24]\n\t"
-        "ldr	r9, [%[sha256], #28]\n\t"
+        "ldr	r10, [%[sha256], #24]\n\t"
+        "ldr	r11, [%[sha256], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[sha256], #24]\n\t"
+        "ldrd	r10, r11, [%[sha256], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #64]\n\t"
-        "str	lr, [sp, #68]\n\t"
+        "str	r4, [sp, #64]\n\t"
+        "str	r5, [sp, #68]\n\t"
 #else
-        "strd	r12, lr, [sp, #64]\n\t"
+        "strd	r4, r5, [sp, #64]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #72]\n\t"
-        "str	r5, [sp, #76]\n\t"
+        "str	r6, [sp, #72]\n\t"
+        "str	r7, [sp, #76]\n\t"
 #else
-        "strd	r4, r5, [sp, #72]\n\t"
+        "strd	r6, r7, [sp, #72]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [sp, #80]\n\t"
-        "str	r7, [sp, #84]\n\t"
+        "str	r8, [sp, #80]\n\t"
+        "str	r9, [sp, #84]\n\t"
 #else
-        "strd	r6, r7, [sp, #80]\n\t"
+        "strd	r8, r9, [sp, #80]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [sp, #88]\n\t"
-        "str	r9, [sp, #92]\n\t"
+        "str	r10, [sp, #88]\n\t"
+        "str	r11, [sp, #92]\n\t"
 #else
-        "strd	r8, r9, [sp, #88]\n\t"
+        "strd	r10, r11, [sp, #88]\n\t"
 #endif
         /* Start of loop processing a block */
         "\n"
     "L_SHA256_transform_len_begin_%=: \n\t"
         /* Load, Reverse and Store W - 64 bytes */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[data]]\n\t"
-        "ldr	lr, [%[data], #4]\n\t"
+        "ldr	r4, [%[data]]\n\t"
+        "ldr	r5, [%[data], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[data]]\n\t"
+        "ldrd	r4, r5, [%[data]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[data], #8]\n\t"
-        "ldr	r5, [%[data], #12]\n\t"
+        "ldr	r6, [%[data], #8]\n\t"
+        "ldr	r7, [%[data], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[data], #8]\n\t"
+        "ldrd	r6, r7, [%[data], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[data], #16]\n\t"
-        "ldr	r7, [%[data], #20]\n\t"
+        "ldr	r8, [%[data], #16]\n\t"
+        "ldr	r9, [%[data], #20]\n\t"
 #else
-        "ldrd	r6, r7, [%[data], #16]\n\t"
+        "ldrd	r8, r9, [%[data], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[data], #24]\n\t"
-        "ldr	r9, [%[data], #28]\n\t"
+        "ldr	r10, [%[data], #24]\n\t"
+        "ldr	r11, [%[data], #28]\n\t"
 #else
-        "ldrd	r8, r9, [%[data], #24]\n\t"
+        "ldrd	r10, r11, [%[data], #24]\n\t"
 #endif
-        "rev	r12, r12\n\t"
-        "rev	lr, lr\n\t"
         "rev	r4, r4\n\t"
         "rev	r5, r5\n\t"
         "rev	r6, r6\n\t"
         "rev	r7, r7\n\t"
         "rev	r8, r8\n\t"
         "rev	r9, r9\n\t"
+        "rev	r10, r10\n\t"
+        "rev	r11, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp]\n\t"
-        "str	lr, [sp, #4]\n\t"
+        "str	r4, [sp]\n\t"
+        "str	r5, [sp, #4]\n\t"
 #else
-        "strd	r12, lr, [sp]\n\t"
+        "strd	r4, r5, [sp]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #8]\n\t"
-        "str	r5, [sp, #12]\n\t"
+        "str	r6, [sp, #8]\n\t"
+        "str	r7, [sp, #12]\n\t"
 #else
-        "strd	r4, r5, [sp, #8]\n\t"
+        "strd	r6, r7, [sp, #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [sp, #16]\n\t"
-        "str	r7, [sp, #20]\n\t"
+        "str	r8, [sp, #16]\n\t"
+        "str	r9, [sp, #20]\n\t"
 #else
-        "strd	r6, r7, [sp, #16]\n\t"
+        "strd	r8, r9, [sp, #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [sp, #24]\n\t"
-        "str	r9, [sp, #28]\n\t"
+        "str	r10, [sp, #24]\n\t"
+        "str	r11, [sp, #28]\n\t"
 #else
-        "strd	r8, r9, [sp, #24]\n\t"
+        "strd	r10, r11, [sp, #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[data], #32]\n\t"
-        "ldr	lr, [%[data], #36]\n\t"
+        "ldr	r4, [%[data], #32]\n\t"
+        "ldr	r5, [%[data], #36]\n\t"
 #else
-        "ldrd	r12, lr, [%[data], #32]\n\t"
+        "ldrd	r4, r5, [%[data], #32]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[data], #40]\n\t"
-        "ldr	r5, [%[data], #44]\n\t"
+        "ldr	r6, [%[data], #40]\n\t"
+        "ldr	r7, [%[data], #44]\n\t"
 #else
-        "ldrd	r4, r5, [%[data], #40]\n\t"
+        "ldrd	r6, r7, [%[data], #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[data], #48]\n\t"
-        "ldr	r7, [%[data], #52]\n\t"
+        "ldr	r8, [%[data], #48]\n\t"
+        "ldr	r9, [%[data], #52]\n\t"
 #else
-        "ldrd	r6, r7, [%[data], #48]\n\t"
+        "ldrd	r8, r9, [%[data], #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[data], #56]\n\t"
-        "ldr	r9, [%[data], #60]\n\t"
+        "ldr	r10, [%[data], #56]\n\t"
+        "ldr	r11, [%[data], #60]\n\t"
 #else
-        "ldrd	r8, r9, [%[data], #56]\n\t"
+        "ldrd	r10, r11, [%[data], #56]\n\t"
 #endif
-        "rev	r12, r12\n\t"
-        "rev	lr, lr\n\t"
         "rev	r4, r4\n\t"
         "rev	r5, r5\n\t"
         "rev	r6, r6\n\t"
         "rev	r7, r7\n\t"
         "rev	r8, r8\n\t"
         "rev	r9, r9\n\t"
+        "rev	r10, r10\n\t"
+        "rev	r11, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #32]\n\t"
-        "str	lr, [sp, #36]\n\t"
+        "str	r4, [sp, #32]\n\t"
+        "str	r5, [sp, #36]\n\t"
 #else
-        "strd	r12, lr, [sp, #32]\n\t"
+        "strd	r4, r5, [sp, #32]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #40]\n\t"
-        "str	r5, [sp, #44]\n\t"
+        "str	r6, [sp, #40]\n\t"
+        "str	r7, [sp, #44]\n\t"
 #else
-        "strd	r4, r5, [sp, #40]\n\t"
+        "strd	r6, r7, [sp, #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [sp, #48]\n\t"
-        "str	r7, [sp, #52]\n\t"
+        "str	r8, [sp, #48]\n\t"
+        "str	r9, [sp, #52]\n\t"
 #else
-        "strd	r6, r7, [sp, #48]\n\t"
+        "strd	r8, r9, [sp, #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [sp, #56]\n\t"
-        "str	r9, [sp, #60]\n\t"
+        "str	r10, [sp, #56]\n\t"
+        "str	r11, [sp, #60]\n\t"
 #else
-        "strd	r8, r9, [sp, #56]\n\t"
+        "strd	r10, r11, [sp, #56]\n\t"
 #endif
-        "ldr	r9, [%[sha256], #4]\n\t"
-        "ldr	r12, [%[sha256], #8]\n\t"
-        "eor	r9, r9, r12\n\t"
-        "mov	r10, #3\n\t"
+        "ldr	r11, [%[sha256], #4]\n\t"
+        "ldr	r4, [%[sha256], #8]\n\t"
+        "eor	r11, r11, r4\n\t"
+        "mov	r12, #3\n\t"
         /* Start of 16 rounds */
         "\n"
     "L_SHA256_transform_len_start_%=: \n\t"
         /* Round 0 */
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r7, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp]\n\t"
-        "ldr	r4, [r3]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r6, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #12]\n\t"
-        "str	r7, [%[sha256], #28]\n\t"
-        /* Calc new W[0] */
-        "ldr	r4, [sp, #56]\n\t"
-        "ldr	r5, [sp, #36]\n\t"
-        "ldr	r6, [sp, #4]\n\t"
-        "ldr	r7, [sp]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp]\n\t"
-        /* Round 1 */
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r7, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #4]\n\t"
-        "ldr	r4, [r3, #4]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r6, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #8]\n\t"
-        "str	r7, [%[sha256], #24]\n\t"
-        /* Calc new W[1] */
-        "ldr	r4, [sp, #60]\n\t"
-        "ldr	r5, [sp, #40]\n\t"
-        "ldr	r6, [sp, #8]\n\t"
-        "ldr	r7, [sp, #4]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #4]\n\t"
-        /* Round 2 */
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
-        "ldr	r5, [%[sha256], #16]\n\t"
-        "ldr	r7, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #8]\n\t"
-        "ldr	r4, [r3, #8]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
-        "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r6, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #4]\n\t"
-        "str	r7, [%[sha256], #20]\n\t"
-        /* Calc new W[2] */
-        "ldr	r4, [sp]\n\t"
-        "ldr	r5, [sp, #44]\n\t"
-        "ldr	r6, [sp, #12]\n\t"
-        "ldr	r7, [sp, #8]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #8]\n\t"
-        /* Round 3 */
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
-        "ldr	r7, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #12]\n\t"
-        "ldr	r4, [r3, #12]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r6, [%[sha256]]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256]]\n\t"
-        "str	r7, [%[sha256], #16]\n\t"
-        /* Calc new W[3] */
-        "ldr	r4, [sp, #4]\n\t"
-        "ldr	r5, [sp, #48]\n\t"
-        "ldr	r6, [sp, #16]\n\t"
-        "ldr	r7, [sp, #12]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #12]\n\t"
-        /* Round 4 */
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r7, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #16]\n\t"
-        "ldr	r4, [r3, #16]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r6, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #28]\n\t"
-        "str	r7, [%[sha256], #12]\n\t"
-        /* Calc new W[4] */
-        "ldr	r4, [sp, #8]\n\t"
-        "ldr	r5, [sp, #52]\n\t"
-        "ldr	r6, [sp, #20]\n\t"
-        "ldr	r7, [sp, #16]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #16]\n\t"
-        /* Round 5 */
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r7, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #20]\n\t"
-        "ldr	r4, [r3, #20]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r6, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #24]\n\t"
-        "str	r7, [%[sha256], #8]\n\t"
-        /* Calc new W[5] */
-        "ldr	r4, [sp, #12]\n\t"
-        "ldr	r5, [sp, #56]\n\t"
-        "ldr	r6, [sp, #24]\n\t"
-        "ldr	r7, [sp, #20]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #20]\n\t"
-        /* Round 6 */
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
-        "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r7, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #24]\n\t"
-        "ldr	r4, [r3, #24]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
         "ldr	r5, [%[sha256], #16]\n\t"
         "ldr	r6, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #20]\n\t"
-        "str	r7, [%[sha256], #4]\n\t"
-        /* Calc new W[6] */
-        "ldr	r4, [sp, #16]\n\t"
-        "ldr	r5, [sp, #60]\n\t"
-        "ldr	r6, [sp, #28]\n\t"
-        "ldr	r7, [sp, #24]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #24]\n\t"
-        /* Round 7 */
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r7, [%[sha256]]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #28]\n\t"
-        "ldr	r4, [r3, #28]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
-        "ldr	r6, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #16]\n\t"
-        "str	r7, [%[sha256]]\n\t"
-        /* Calc new W[7] */
-        "ldr	r4, [sp, #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r9, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
         "ldr	r5, [sp]\n\t"
-        "ldr	r6, [sp, #32]\n\t"
-        "ldr	r7, [sp, #28]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #28]\n\t"
-        /* Round 8 */
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r7, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #32]\n\t"
-        "ldr	r4, [r3, #32]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r6, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #12]\n\t"
-        "str	r7, [%[sha256], #28]\n\t"
-        /* Calc new W[8] */
-        "ldr	r4, [sp, #24]\n\t"
-        "ldr	r5, [sp, #4]\n\t"
-        "ldr	r6, [sp, #36]\n\t"
-        "ldr	r7, [sp, #32]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #32]\n\t"
-        /* Round 9 */
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r7, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #36]\n\t"
-        "ldr	r4, [r3, #36]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r6, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #8]\n\t"
-        "str	r7, [%[sha256], #24]\n\t"
-        /* Calc new W[9] */
-        "ldr	r4, [sp, #28]\n\t"
-        "ldr	r5, [sp, #8]\n\t"
-        "ldr	r6, [sp, #40]\n\t"
-        "ldr	r7, [sp, #36]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #36]\n\t"
-        /* Round 10 */
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
-        "ldr	r5, [%[sha256], #16]\n\t"
-        "ldr	r7, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #40]\n\t"
-        "ldr	r4, [r3, #40]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
+        "ldr	r6, [r3]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
         "ldr	r5, [%[sha256]]\n\t"
         "ldr	r6, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #4]\n\t"
-        "str	r7, [%[sha256], #20]\n\t"
-        /* Calc new W[10] */
-        "ldr	r4, [sp, #32]\n\t"
-        "ldr	r5, [sp, #12]\n\t"
-        "ldr	r6, [sp, #44]\n\t"
-        "ldr	r7, [sp, #40]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #40]\n\t"
-        /* Round 11 */
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
-        "ldr	r7, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #44]\n\t"
-        "ldr	r4, [r3, #44]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r6, [%[sha256]]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256]]\n\t"
-        "str	r7, [%[sha256], #16]\n\t"
-        /* Calc new W[11] */
-        "ldr	r4, [sp, #36]\n\t"
-        "ldr	r5, [sp, #16]\n\t"
-        "ldr	r6, [sp, #48]\n\t"
-        "ldr	r7, [sp, #44]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #44]\n\t"
-        /* Round 12 */
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r7, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #48]\n\t"
-        "ldr	r4, [r3, #48]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r6, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #28]\n\t"
-        "str	r7, [%[sha256], #12]\n\t"
-        /* Calc new W[12] */
-        "ldr	r4, [sp, #40]\n\t"
-        "ldr	r5, [sp, #20]\n\t"
-        "ldr	r6, [sp, #52]\n\t"
-        "ldr	r7, [sp, #48]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #48]\n\t"
-        /* Round 13 */
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
         "ldr	r7, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #52]\n\t"
-        "ldr	r4, [r3, #52]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r6, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #24]\n\t"
-        "str	r7, [%[sha256], #8]\n\t"
-        /* Calc new W[13] */
-        "ldr	r4, [sp, #44]\n\t"
-        "ldr	r5, [sp, #24]\n\t"
+        "ldr	r8, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #12]\n\t"
+        "str	r9, [%[sha256], #28]\n\t"
+        /* Calc new W[0] */
         "ldr	r6, [sp, #56]\n\t"
-        "ldr	r7, [sp, #52]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #52]\n\t"
-        /* Round 14 */
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
-        "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r7, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #56]\n\t"
-        "ldr	r4, [r3, #56]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
-        "ldr	r5, [%[sha256], #16]\n\t"
-        "ldr	r6, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #20]\n\t"
-        "str	r7, [%[sha256], #4]\n\t"
-        /* Calc new W[14] */
-        "ldr	r4, [sp, #48]\n\t"
-        "ldr	r5, [sp, #28]\n\t"
-        "ldr	r6, [sp, #60]\n\t"
-        "ldr	r7, [sp, #56]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #56]\n\t"
-        /* Round 15 */
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r7, [%[sha256]]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #60]\n\t"
-        "ldr	r4, [r3, #60]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
+        "ldr	r7, [sp, #36]\n\t"
+        "ldr	r8, [sp, #4]\n\t"
+        "ldr	r9, [sp]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp]\n\t"
+        /* Round 1 */
         "ldr	r5, [%[sha256], #12]\n\t"
         "ldr	r6, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #16]\n\t"
-        "str	r7, [%[sha256]]\n\t"
-        /* Calc new W[15] */
-        "ldr	r4, [sp, #52]\n\t"
-        "ldr	r5, [sp, #32]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r9, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #4]\n\t"
+        "ldr	r6, [r3, #4]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r8, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #8]\n\t"
+        "str	r9, [%[sha256], #24]\n\t"
+        /* Calc new W[1] */
+        "ldr	r6, [sp, #60]\n\t"
+        "ldr	r7, [sp, #40]\n\t"
+        "ldr	r8, [sp, #8]\n\t"
+        "ldr	r9, [sp, #4]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #4]\n\t"
+        /* Round 2 */
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r9, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #8]\n\t"
+        "ldr	r6, [r3, #8]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r8, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #4]\n\t"
+        "str	r9, [%[sha256], #20]\n\t"
+        /* Calc new W[2] */
         "ldr	r6, [sp]\n\t"
+        "ldr	r7, [sp, #44]\n\t"
+        "ldr	r8, [sp, #12]\n\t"
+        "ldr	r9, [sp, #8]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #8]\n\t"
+        /* Round 3 */
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r9, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #12]\n\t"
+        "ldr	r6, [r3, #12]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r8, [%[sha256]]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256]]\n\t"
+        "str	r9, [%[sha256], #16]\n\t"
+        /* Calc new W[3] */
+        "ldr	r6, [sp, #4]\n\t"
+        "ldr	r7, [sp, #48]\n\t"
+        "ldr	r8, [sp, #16]\n\t"
+        "ldr	r9, [sp, #12]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #12]\n\t"
+        /* Round 4 */
+        "ldr	r5, [%[sha256]]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r9, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #16]\n\t"
+        "ldr	r6, [r3, #16]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r8, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #28]\n\t"
+        "str	r9, [%[sha256], #12]\n\t"
+        /* Calc new W[4] */
+        "ldr	r6, [sp, #8]\n\t"
+        "ldr	r7, [sp, #52]\n\t"
+        "ldr	r8, [sp, #20]\n\t"
+        "ldr	r9, [sp, #16]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #16]\n\t"
+        /* Round 5 */
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r9, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #20]\n\t"
+        "ldr	r6, [r3, #20]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #16]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r8, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #24]\n\t"
+        "str	r9, [%[sha256], #8]\n\t"
+        /* Calc new W[5] */
+        "ldr	r6, [sp, #12]\n\t"
+        "ldr	r7, [sp, #56]\n\t"
+        "ldr	r8, [sp, #24]\n\t"
+        "ldr	r9, [sp, #20]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #20]\n\t"
+        /* Round 6 */
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r9, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #24]\n\t"
+        "ldr	r6, [r3, #24]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r8, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #20]\n\t"
+        "str	r9, [%[sha256], #4]\n\t"
+        /* Calc new W[6] */
+        "ldr	r6, [sp, #16]\n\t"
         "ldr	r7, [sp, #60]\n\t"
-        "ror	r12, r4, #17\n\t"
-        "ror	lr, r6, #7\n\t"
-        "eor	r12, r12, r4, ror #19\n\t"
-        "eor	lr, lr, r6, ror #18\n\t"
-        "eor	r12, r12, r4, lsr #10\n\t"
-        "eor	lr, lr, r6, lsr #3\n\t"
-        "add	r7, r7, r5\n\t"
-        "add	r12, r12, lr\n\t"
-        "add	r7, r7, r12\n\t"
-        "str	r7, [sp, #60]\n\t"
+        "ldr	r8, [sp, #28]\n\t"
+        "ldr	r9, [sp, #24]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #24]\n\t"
+        /* Round 7 */
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r9, [%[sha256]]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #28]\n\t"
+        "ldr	r6, [r3, #28]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r8, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #16]\n\t"
+        "str	r9, [%[sha256]]\n\t"
+        /* Calc new W[7] */
+        "ldr	r6, [sp, #20]\n\t"
+        "ldr	r7, [sp]\n\t"
+        "ldr	r8, [sp, #32]\n\t"
+        "ldr	r9, [sp, #28]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #28]\n\t"
+        /* Round 8 */
+        "ldr	r5, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r9, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #32]\n\t"
+        "ldr	r6, [r3, #32]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256]]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r8, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #12]\n\t"
+        "str	r9, [%[sha256], #28]\n\t"
+        /* Calc new W[8] */
+        "ldr	r6, [sp, #24]\n\t"
+        "ldr	r7, [sp, #4]\n\t"
+        "ldr	r8, [sp, #36]\n\t"
+        "ldr	r9, [sp, #32]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #32]\n\t"
+        /* Round 9 */
+        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #16]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r9, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #36]\n\t"
+        "ldr	r6, [r3, #36]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r8, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #8]\n\t"
+        "str	r9, [%[sha256], #24]\n\t"
+        /* Calc new W[9] */
+        "ldr	r6, [sp, #28]\n\t"
+        "ldr	r7, [sp, #8]\n\t"
+        "ldr	r8, [sp, #40]\n\t"
+        "ldr	r9, [sp, #36]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #36]\n\t"
+        /* Round 10 */
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r9, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #40]\n\t"
+        "ldr	r6, [r3, #40]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r8, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #4]\n\t"
+        "str	r9, [%[sha256], #20]\n\t"
+        /* Calc new W[10] */
+        "ldr	r6, [sp, #32]\n\t"
+        "ldr	r7, [sp, #12]\n\t"
+        "ldr	r8, [sp, #44]\n\t"
+        "ldr	r9, [sp, #40]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #40]\n\t"
+        /* Round 11 */
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r9, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #44]\n\t"
+        "ldr	r6, [r3, #44]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r8, [%[sha256]]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256]]\n\t"
+        "str	r9, [%[sha256], #16]\n\t"
+        /* Calc new W[11] */
+        "ldr	r6, [sp, #36]\n\t"
+        "ldr	r7, [sp, #16]\n\t"
+        "ldr	r8, [sp, #48]\n\t"
+        "ldr	r9, [sp, #44]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #44]\n\t"
+        /* Round 12 */
+        "ldr	r5, [%[sha256]]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r9, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #48]\n\t"
+        "ldr	r6, [r3, #48]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r8, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #28]\n\t"
+        "str	r9, [%[sha256], #12]\n\t"
+        /* Calc new W[12] */
+        "ldr	r6, [sp, #40]\n\t"
+        "ldr	r7, [sp, #20]\n\t"
+        "ldr	r8, [sp, #52]\n\t"
+        "ldr	r9, [sp, #48]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #48]\n\t"
+        /* Round 13 */
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r9, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #52]\n\t"
+        "ldr	r6, [r3, #52]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #16]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r8, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #24]\n\t"
+        "str	r9, [%[sha256], #8]\n\t"
+        /* Calc new W[13] */
+        "ldr	r6, [sp, #44]\n\t"
+        "ldr	r7, [sp, #24]\n\t"
+        "ldr	r8, [sp, #56]\n\t"
+        "ldr	r9, [sp, #52]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #52]\n\t"
+        /* Round 14 */
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r9, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #56]\n\t"
+        "ldr	r6, [r3, #56]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r8, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #20]\n\t"
+        "str	r9, [%[sha256], #4]\n\t"
+        /* Calc new W[14] */
+        "ldr	r6, [sp, #48]\n\t"
+        "ldr	r7, [sp, #28]\n\t"
+        "ldr	r8, [sp, #60]\n\t"
+        "ldr	r9, [sp, #56]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #56]\n\t"
+        /* Round 15 */
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r9, [%[sha256]]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #60]\n\t"
+        "ldr	r6, [r3, #60]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r8, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #16]\n\t"
+        "str	r9, [%[sha256]]\n\t"
+        /* Calc new W[15] */
+        "ldr	r6, [sp, #52]\n\t"
+        "ldr	r7, [sp, #32]\n\t"
+        "ldr	r8, [sp]\n\t"
+        "ldr	r9, [sp, #60]\n\t"
+        "ror	r4, r6, #17\n\t"
+        "ror	r5, r8, #7\n\t"
+        "eor	r4, r4, r6, ror #19\n\t"
+        "eor	r5, r5, r8, ror #18\n\t"
+        "eor	r4, r4, r6, lsr #10\n\t"
+        "eor	r5, r5, r8, lsr #3\n\t"
+        "add	r9, r9, r7\n\t"
+        "add	r4, r4, r5\n\t"
+        "add	r9, r9, r4\n\t"
+        "str	r9, [sp, #60]\n\t"
         "add	r3, r3, #0x40\n\t"
-        "subs	r10, r10, #1\n\t"
+        "subs	r12, r12, #1\n\t"
         "bne	L_SHA256_transform_len_start_%=\n\t"
         /* Round 0 */
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r7, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp]\n\t"
-        "ldr	r4, [r3]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r6, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #12]\n\t"
-        "str	r7, [%[sha256], #28]\n\t"
+        "ldr	r5, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r9, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp]\n\t"
+        "ldr	r6, [r3]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256]]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r8, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #12]\n\t"
+        "str	r9, [%[sha256], #28]\n\t"
         /* Round 1 */
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r7, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #4]\n\t"
-        "ldr	r4, [r3, #4]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r6, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #8]\n\t"
-        "str	r7, [%[sha256], #24]\n\t"
-        /* Round 2 */
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
-        "ldr	r5, [%[sha256], #16]\n\t"
-        "ldr	r7, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #8]\n\t"
-        "ldr	r4, [r3, #8]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
-        "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r6, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #4]\n\t"
-        "str	r7, [%[sha256], #20]\n\t"
-        /* Round 3 */
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
-        "ldr	r7, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #12]\n\t"
-        "ldr	r4, [r3, #12]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r6, [%[sha256]]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256]]\n\t"
-        "str	r7, [%[sha256], #16]\n\t"
-        /* Round 4 */
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r7, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #16]\n\t"
-        "ldr	r4, [r3, #16]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r6, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #28]\n\t"
-        "str	r7, [%[sha256], #12]\n\t"
-        /* Round 5 */
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r7, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #20]\n\t"
-        "ldr	r4, [r3, #20]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r6, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #24]\n\t"
-        "str	r7, [%[sha256], #8]\n\t"
-        /* Round 6 */
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
-        "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r7, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #24]\n\t"
-        "ldr	r4, [r3, #24]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
-        "ldr	r5, [%[sha256], #16]\n\t"
-        "ldr	r6, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #20]\n\t"
-        "str	r7, [%[sha256], #4]\n\t"
-        /* Round 7 */
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r7, [%[sha256]]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #28]\n\t"
-        "ldr	r4, [r3, #28]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
         "ldr	r5, [%[sha256], #12]\n\t"
         "ldr	r6, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #16]\n\t"
-        "str	r7, [%[sha256]]\n\t"
-        /* Round 8 */
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
-        "ldr	r5, [%[sha256], #24]\n\t"
-        "ldr	r7, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #32]\n\t"
-        "ldr	r4, [r3, #32]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r9, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #4]\n\t"
+        "ldr	r6, [r3, #4]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r8, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #8]\n\t"
+        "str	r9, [%[sha256], #24]\n\t"
+        /* Round 2 */
         "ldr	r5, [%[sha256], #8]\n\t"
         "ldr	r6, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #12]\n\t"
-        "str	r7, [%[sha256], #28]\n\t"
-        /* Round 9 */
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
-        "ldr	r5, [%[sha256], #20]\n\t"
-        "ldr	r7, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #36]\n\t"
-        "ldr	r4, [r3, #36]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
-        "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r6, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #8]\n\t"
-        "str	r7, [%[sha256], #24]\n\t"
-        /* Round 10 */
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
-        "ldr	r5, [%[sha256], #16]\n\t"
-        "ldr	r7, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #40]\n\t"
-        "ldr	r4, [r3, #40]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
-        "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r6, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #4]\n\t"
-        "str	r7, [%[sha256], #20]\n\t"
-        /* Round 11 */
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
         "ldr	r7, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #44]\n\t"
-        "ldr	r4, [r3, #44]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r6, [%[sha256]]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256]]\n\t"
-        "str	r7, [%[sha256], #16]\n\t"
-        /* Round 12 */
-        "ldr	lr, [%[sha256]]\n\t"
-        "ldr	r4, [%[sha256], #4]\n\t"
-        "ldr	r5, [%[sha256], #8]\n\t"
-        "ldr	r7, [%[sha256], #12]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #48]\n\t"
-        "ldr	r4, [r3, #48]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #16]\n\t"
-        "ldr	r4, [%[sha256], #20]\n\t"
+        "ldr	r9, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #8]\n\t"
+        "ldr	r6, [r3, #8]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
         "ldr	r5, [%[sha256], #24]\n\t"
         "ldr	r6, [%[sha256], #28]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #28]\n\t"
-        "str	r7, [%[sha256], #12]\n\t"
-        /* Round 13 */
-        "ldr	lr, [%[sha256], #28]\n\t"
-        "ldr	r4, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r8, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #4]\n\t"
+        "str	r9, [%[sha256], #20]\n\t"
+        /* Round 3 */
         "ldr	r5, [%[sha256], #4]\n\t"
-        "ldr	r7, [%[sha256], #8]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #52]\n\t"
-        "ldr	r4, [r3, #52]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #12]\n\t"
-        "ldr	r4, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r9, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #12]\n\t"
+        "ldr	r6, [r3, #12]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
         "ldr	r5, [%[sha256], #20]\n\t"
         "ldr	r6, [%[sha256], #24]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #24]\n\t"
-        "str	r7, [%[sha256], #8]\n\t"
-        /* Round 14 */
-        "ldr	lr, [%[sha256], #24]\n\t"
-        "ldr	r4, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r8, [%[sha256]]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256]]\n\t"
+        "str	r9, [%[sha256], #16]\n\t"
+        /* Round 4 */
         "ldr	r5, [%[sha256]]\n\t"
-        "ldr	r7, [%[sha256], #4]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #56]\n\t"
-        "ldr	r4, [r3, #56]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #8]\n\t"
-        "ldr	r4, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r9, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #16]\n\t"
+        "ldr	r6, [r3, #16]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
         "ldr	r5, [%[sha256], #16]\n\t"
         "ldr	r6, [%[sha256], #20]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r8, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r9, r9, r8\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r9, r9, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r9\n\t"
-        "str	r6, [%[sha256], #20]\n\t"
-        "str	r7, [%[sha256], #4]\n\t"
-        /* Round 15 */
-        "ldr	lr, [%[sha256], #20]\n\t"
-        "ldr	r4, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r8, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #28]\n\t"
+        "str	r9, [%[sha256], #12]\n\t"
+        /* Round 5 */
         "ldr	r5, [%[sha256], #28]\n\t"
-        "ldr	r7, [%[sha256]]\n\t"
-        "ror	r12, lr, #6\n\t"
-        "eor	r4, r4, r5\n\t"
-        "eor	r12, r12, lr, ror #11\n\t"
-        "and	r4, r4, lr\n\t"
-        "eor	r12, r12, lr, ror #25\n\t"
-        "eor	r4, r4, r5\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [sp, #60]\n\t"
-        "ldr	r4, [r3, #60]\n\t"
-        "add	r7, r7, lr\n\t"
-        "add	r7, r7, r4\n\t"
-        "ldr	lr, [%[sha256], #4]\n\t"
-        "ldr	r4, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r9, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #20]\n\t"
+        "ldr	r6, [r3, #20]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
         "ldr	r5, [%[sha256], #12]\n\t"
         "ldr	r6, [%[sha256], #16]\n\t"
-        "ror	r12, lr, #2\n\t"
-        "eor	r9, lr, r4\n\t"
-        "eor	r12, r12, lr, ror #13\n\t"
-        "and	r8, r8, r9\n\t"
-        "eor	r12, r12, lr, ror #22\n\t"
-        "eor	r8, r8, r4\n\t"
-        "add	r6, r6, r7\n\t"
-        "add	r7, r7, r12\n\t"
-        "add	r7, r7, r8\n\t"
-        "str	r6, [%[sha256], #16]\n\t"
-        "str	r7, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r8, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #24]\n\t"
+        "str	r9, [%[sha256], #8]\n\t"
+        /* Round 6 */
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r9, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #24]\n\t"
+        "ldr	r6, [r3, #24]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r8, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #20]\n\t"
+        "str	r9, [%[sha256], #4]\n\t"
+        /* Round 7 */
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r9, [%[sha256]]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #28]\n\t"
+        "ldr	r6, [r3, #28]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r8, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #16]\n\t"
+        "str	r9, [%[sha256]]\n\t"
+        /* Round 8 */
+        "ldr	r5, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r9, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #32]\n\t"
+        "ldr	r6, [r3, #32]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256]]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r8, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #12]\n\t"
+        "str	r9, [%[sha256], #28]\n\t"
+        /* Round 9 */
+        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #16]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r9, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #36]\n\t"
+        "ldr	r6, [r3, #36]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r8, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #8]\n\t"
+        "str	r9, [%[sha256], #24]\n\t"
+        /* Round 10 */
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r9, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #40]\n\t"
+        "ldr	r6, [r3, #40]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r8, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #4]\n\t"
+        "str	r9, [%[sha256], #20]\n\t"
+        /* Round 11 */
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r9, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #44]\n\t"
+        "ldr	r6, [r3, #44]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r8, [%[sha256]]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256]]\n\t"
+        "str	r9, [%[sha256], #16]\n\t"
+        /* Round 12 */
+        "ldr	r5, [%[sha256]]\n\t"
+        "ldr	r6, [%[sha256], #4]\n\t"
+        "ldr	r7, [%[sha256], #8]\n\t"
+        "ldr	r9, [%[sha256], #12]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #48]\n\t"
+        "ldr	r6, [r3, #48]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #16]\n\t"
+        "ldr	r6, [%[sha256], #20]\n\t"
+        "ldr	r7, [%[sha256], #24]\n\t"
+        "ldr	r8, [%[sha256], #28]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #28]\n\t"
+        "str	r9, [%[sha256], #12]\n\t"
+        /* Round 13 */
+        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256]]\n\t"
+        "ldr	r7, [%[sha256], #4]\n\t"
+        "ldr	r9, [%[sha256], #8]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #52]\n\t"
+        "ldr	r6, [r3, #52]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #16]\n\t"
+        "ldr	r7, [%[sha256], #20]\n\t"
+        "ldr	r8, [%[sha256], #24]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #24]\n\t"
+        "str	r9, [%[sha256], #8]\n\t"
+        /* Round 14 */
+        "ldr	r5, [%[sha256], #24]\n\t"
+        "ldr	r6, [%[sha256], #28]\n\t"
+        "ldr	r7, [%[sha256]]\n\t"
+        "ldr	r9, [%[sha256], #4]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #56]\n\t"
+        "ldr	r6, [r3, #56]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #8]\n\t"
+        "ldr	r6, [%[sha256], #12]\n\t"
+        "ldr	r7, [%[sha256], #16]\n\t"
+        "ldr	r8, [%[sha256], #20]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r10, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r11, r11, r10\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r11, r11, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r11\n\t"
+        "str	r8, [%[sha256], #20]\n\t"
+        "str	r9, [%[sha256], #4]\n\t"
+        /* Round 15 */
+        "ldr	r5, [%[sha256], #20]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
+        "ldr	r9, [%[sha256]]\n\t"
+        "ror	r4, r5, #6\n\t"
+        "eor	r6, r6, r7\n\t"
+        "eor	r4, r4, r5, ror #11\n\t"
+        "and	r6, r6, r5\n\t"
+        "eor	r4, r4, r5, ror #25\n\t"
+        "eor	r6, r6, r7\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [sp, #60]\n\t"
+        "ldr	r6, [r3, #60]\n\t"
+        "add	r9, r9, r5\n\t"
+        "add	r9, r9, r6\n\t"
+        "ldr	r5, [%[sha256], #4]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
+        "ldr	r8, [%[sha256], #16]\n\t"
+        "ror	r4, r5, #2\n\t"
+        "eor	r11, r5, r6\n\t"
+        "eor	r4, r4, r5, ror #13\n\t"
+        "and	r10, r10, r11\n\t"
+        "eor	r4, r4, r5, ror #22\n\t"
+        "eor	r10, r10, r6\n\t"
+        "add	r8, r8, r9\n\t"
+        "add	r9, r9, r4\n\t"
+        "add	r9, r9, r10\n\t"
+        "str	r8, [%[sha256], #16]\n\t"
+        "str	r9, [%[sha256]]\n\t"
         /* Add in digest from start */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha256]]\n\t"
-        "ldr	lr, [%[sha256], #4]\n\t"
+        "ldr	r4, [%[sha256]]\n\t"
+        "ldr	r5, [%[sha256], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha256]]\n\t"
+        "ldrd	r4, r5, [%[sha256]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha256], #8]\n\t"
-        "ldr	r5, [%[sha256], #12]\n\t"
+        "ldr	r6, [%[sha256], #8]\n\t"
+        "ldr	r7, [%[sha256], #12]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha256], #8]\n\t"
+        "ldrd	r6, r7, [%[sha256], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #64]\n\t"
-        "ldr	r7, [sp, #68]\n\t"
+        "ldr	r8, [sp, #64]\n\t"
+        "ldr	r9, [sp, #68]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #64]\n\t"
+        "ldrd	r8, r9, [sp, #64]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [sp, #72]\n\t"
-        "ldr	r9, [sp, #76]\n\t"
+        "ldr	r10, [sp, #72]\n\t"
+        "ldr	r11, [sp, #76]\n\t"
 #else
-        "ldrd	r8, r9, [sp, #72]\n\t"
+        "ldrd	r10, r11, [sp, #72]\n\t"
 #endif
-        "add	r12, r12, r6\n\t"
-        "add	lr, lr, r7\n\t"
         "add	r4, r4, r8\n\t"
         "add	r5, r5, r9\n\t"
+        "add	r6, r6, r10\n\t"
+        "add	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha256]]\n\t"
-        "str	lr, [%[sha256], #4]\n\t"
+        "str	r4, [%[sha256]]\n\t"
+        "str	r5, [%[sha256], #4]\n\t"
 #else
-        "strd	r12, lr, [%[sha256]]\n\t"
+        "strd	r4, r5, [%[sha256]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha256], #8]\n\t"
-        "str	r5, [%[sha256], #12]\n\t"
+        "str	r6, [%[sha256], #8]\n\t"
+        "str	r7, [%[sha256], #12]\n\t"
 #else
-        "strd	r4, r5, [%[sha256], #8]\n\t"
+        "strd	r6, r7, [%[sha256], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #64]\n\t"
-        "str	lr, [sp, #68]\n\t"
+        "str	r4, [sp, #64]\n\t"
+        "str	r5, [sp, #68]\n\t"
 #else
-        "strd	r12, lr, [sp, #64]\n\t"
+        "strd	r4, r5, [sp, #64]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #72]\n\t"
-        "str	r5, [sp, #76]\n\t"
+        "str	r6, [sp, #72]\n\t"
+        "str	r7, [sp, #76]\n\t"
 #else
-        "strd	r4, r5, [sp, #72]\n\t"
+        "strd	r6, r7, [sp, #72]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha256], #16]\n\t"
-        "ldr	lr, [%[sha256], #20]\n\t"
+        "ldr	r4, [%[sha256], #16]\n\t"
+        "ldr	r5, [%[sha256], #20]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha256], #16]\n\t"
+        "ldrd	r4, r5, [%[sha256], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha256], #24]\n\t"
-        "ldr	r5, [%[sha256], #28]\n\t"
+        "ldr	r6, [%[sha256], #24]\n\t"
+        "ldr	r7, [%[sha256], #28]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha256], #24]\n\t"
+        "ldrd	r6, r7, [%[sha256], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #80]\n\t"
-        "ldr	r7, [sp, #84]\n\t"
+        "ldr	r8, [sp, #80]\n\t"
+        "ldr	r9, [sp, #84]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #80]\n\t"
+        "ldrd	r8, r9, [sp, #80]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [sp, #88]\n\t"
-        "ldr	r9, [sp, #92]\n\t"
+        "ldr	r10, [sp, #88]\n\t"
+        "ldr	r11, [sp, #92]\n\t"
 #else
-        "ldrd	r8, r9, [sp, #88]\n\t"
+        "ldrd	r10, r11, [sp, #88]\n\t"
 #endif
-        "add	r12, r12, r6\n\t"
-        "add	lr, lr, r7\n\t"
         "add	r4, r4, r8\n\t"
         "add	r5, r5, r9\n\t"
+        "add	r6, r6, r10\n\t"
+        "add	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha256], #16]\n\t"
-        "str	lr, [%[sha256], #20]\n\t"
+        "str	r4, [%[sha256], #16]\n\t"
+        "str	r5, [%[sha256], #20]\n\t"
 #else
-        "strd	r12, lr, [%[sha256], #16]\n\t"
+        "strd	r4, r5, [%[sha256], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha256], #24]\n\t"
-        "str	r5, [%[sha256], #28]\n\t"
+        "str	r6, [%[sha256], #24]\n\t"
+        "str	r7, [%[sha256], #28]\n\t"
 #else
-        "strd	r4, r5, [%[sha256], #24]\n\t"
+        "strd	r6, r7, [%[sha256], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #80]\n\t"
-        "str	lr, [sp, #84]\n\t"
+        "str	r4, [sp, #80]\n\t"
+        "str	r5, [sp, #84]\n\t"
 #else
-        "strd	r12, lr, [sp, #80]\n\t"
+        "strd	r4, r5, [sp, #80]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #88]\n\t"
-        "str	r5, [sp, #92]\n\t"
+        "str	r6, [sp, #88]\n\t"
+        "str	r7, [sp, #92]\n\t"
 #else
-        "strd	r4, r5, [sp, #88]\n\t"
+        "strd	r6, r7, [sp, #88]\n\t"
 #endif
         "subs	%[len], %[len], #0x40\n\t"
         "sub	r3, r3, #0xc0\n\t"
@@ -1665,7 +1665,7 @@ void Transform_Sha256_Len(wc_Sha256* sha256_p, const byte* data_p, word32 len_p)
         "add	sp, sp, #0xc0\n\t"
         : [sha256] "+r" (sha256), [data] "+r" (data), [len] "+r" (len)
         : [L_SHA256_transform_len_k] "r" (L_SHA256_transform_len_k)
-        : "memory", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10"
+        : "memory", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12"
     );
 }
 
@@ -2774,7 +2774,7 @@ void Transform_Sha256_Len(wc_Sha256* sha256_p, const byte* data_p, word32 len_p)
         "add	sp, sp, #24\n\t"
         : [sha256] "+r" (sha256), [data] "+r" (data), [len] "+r" (len)
         : [L_SHA256_transform_neon_len_k] "r" (L_SHA256_transform_neon_len_k)
-        : "memory", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11"
+        : "memory", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r12", "lr", "r10", "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11"
     );
 }
 
diff --git a/wolfcrypt/src/port/arm/armv8-32-sha512-asm.S b/wolfcrypt/src/port/arm/armv8-32-sha512-asm.S
index 2a731b92d..20cbe4d6a 100644
--- a/wolfcrypt/src/port/arm/armv8-32-sha512-asm.S
+++ b/wolfcrypt/src/port/arm/armv8-32-sha512-asm.S
@@ -33,7 +33,7 @@
 	.text
 	.type	L_SHA512_transform_len_k, %object
 	.size	L_SHA512_transform_len_k, 640
-	.align	3
+	.align	4
 L_SHA512_transform_len_k:
 	.word	0xd728ae22
 	.word	0x428a2f98
@@ -196,7366 +196,7366 @@ L_SHA512_transform_len_k:
 	.word	0x4a475817
 	.word	0x6c44198c
 	.text
-	.align	2
+	.align	4
 	.globl	Transform_Sha512_Len
 	.type	Transform_Sha512_Len, %function
 Transform_Sha512_Len:
-	push	{r4, r5, r6, r7, r8, r9, r10, lr}
+	push	{r4, r5, r6, r7, r8, r9, r10, r11}
 	sub	sp, sp, #0xc0
 	adr	r3, L_SHA512_transform_len_k
 	# Copy digest to add in at end
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
 #else
-	ldrd  r12, lr, [r0]
+	ldrd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
 #else
-	ldrd  r6, r7, [r0, #16]
+	ldrd	r8, r9, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r0, #24]
-	ldr	r9, [r0, #28]
+	ldr	r10, [r0, #24]
+	ldr	r11, [r0, #28]
 #else
-	ldrd  r8, r9, [r0, #24]
+	ldrd	r10, r11, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #128]
-	str	lr, [sp, #132]
+	str	r4, [sp, #128]
+	str	r5, [sp, #132]
 #else
-	strd  r12, lr, [sp, #128]
+	strd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #136]
-	str	r5, [sp, #140]
+	str	r6, [sp, #136]
+	str	r7, [sp, #140]
 #else
-	strd  r4, r5, [sp, #136]
+	strd	r6, r7, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [sp, #144]
-	str	r7, [sp, #148]
+	str	r8, [sp, #144]
+	str	r9, [sp, #148]
 #else
-	strd  r6, r7, [sp, #144]
+	strd	r8, r9, [sp, #144]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [sp, #152]
-	str	r9, [sp, #156]
+	str	r10, [sp, #152]
+	str	r11, [sp, #156]
 #else
-	strd  r8, r9, [sp, #152]
+	strd	r10, r11, [sp, #152]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
 #else
-	ldrd  r12, lr, [r0, #32]
+	ldrd	r4, r5, [r0, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
 #else
-	ldrd  r4, r5, [r0, #40]
+	ldrd	r6, r7, [r0, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
 #else
-	ldrd  r6, r7, [r0, #48]
+	ldrd	r8, r9, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r0, #56]
-	ldr	r9, [r0, #60]
+	ldr	r10, [r0, #56]
+	ldr	r11, [r0, #60]
 #else
-	ldrd  r8, r9, [r0, #56]
+	ldrd	r10, r11, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #160]
-	str	lr, [sp, #164]
+	str	r4, [sp, #160]
+	str	r5, [sp, #164]
 #else
-	strd  r12, lr, [sp, #160]
+	strd	r4, r5, [sp, #160]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #168]
-	str	r5, [sp, #172]
+	str	r6, [sp, #168]
+	str	r7, [sp, #172]
 #else
-	strd  r4, r5, [sp, #168]
+	strd	r6, r7, [sp, #168]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [sp, #176]
-	str	r7, [sp, #180]
+	str	r8, [sp, #176]
+	str	r9, [sp, #180]
 #else
-	strd  r6, r7, [sp, #176]
+	strd	r8, r9, [sp, #176]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r8, [sp, #184]
-	str	r9, [sp, #188]
+	str	r10, [sp, #184]
+	str	r11, [sp, #188]
 #else
-	strd  r8, r9, [sp, #184]
+	strd	r10, r11, [sp, #184]
 #endif
 	# Start of loop processing a block
 L_SHA512_transform_len_begin:
 	# Load, Reverse and Store W
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1]
-	ldr	lr, [r1, #4]
+	ldr	r4, [r1]
+	ldr	r5, [r1, #4]
 #else
-	ldrd  r12, lr, [r1]
+	ldrd	r4, r5, [r1]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #8]
-	ldr	r5, [r1, #12]
+	ldr	r6, [r1, #8]
+	ldr	r7, [r1, #12]
 #else
-	ldrd  r4, r5, [r1, #8]
+	ldrd	r6, r7, [r1, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #16]
-	ldr	r7, [r1, #20]
+	ldr	r8, [r1, #16]
+	ldr	r9, [r1, #20]
 #else
-	ldrd  r6, r7, [r1, #16]
+	ldrd	r8, r9, [r1, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #24]
-	ldr	r9, [r1, #28]
+	ldr	r10, [r1, #24]
+	ldr	r11, [r1, #28]
 #else
-	ldrd  r8, r9, [r1, #24]
+	ldrd	r10, r11, [r1, #24]
 #endif
-	rev	r12, r12
-	rev	lr, lr
 	rev	r4, r4
 	rev	r5, r5
 	rev	r6, r6
 	rev	r7, r7
 	rev	r8, r8
 	rev	r9, r9
-	str	lr, [sp]
-	str	r12, [sp, #4]
-	str	r5, [sp, #8]
-	str	r4, [sp, #12]
-	str	r7, [sp, #16]
-	str	r6, [sp, #20]
-	str	r9, [sp, #24]
-	str	r8, [sp, #28]
+	rev	r10, r10
+	rev	r11, r11
+	str	r5, [sp]
+	str	r4, [sp, #4]
+	str	r7, [sp, #8]
+	str	r6, [sp, #12]
+	str	r9, [sp, #16]
+	str	r8, [sp, #20]
+	str	r11, [sp, #24]
+	str	r10, [sp, #28]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #32]
-	ldr	lr, [r1, #36]
+	ldr	r4, [r1, #32]
+	ldr	r5, [r1, #36]
 #else
-	ldrd  r12, lr, [r1, #32]
+	ldrd	r4, r5, [r1, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #40]
-	ldr	r5, [r1, #44]
+	ldr	r6, [r1, #40]
+	ldr	r7, [r1, #44]
 #else
-	ldrd  r4, r5, [r1, #40]
+	ldrd	r6, r7, [r1, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #48]
-	ldr	r7, [r1, #52]
+	ldr	r8, [r1, #48]
+	ldr	r9, [r1, #52]
 #else
-	ldrd  r6, r7, [r1, #48]
+	ldrd	r8, r9, [r1, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #56]
-	ldr	r9, [r1, #60]
+	ldr	r10, [r1, #56]
+	ldr	r11, [r1, #60]
 #else
-	ldrd  r8, r9, [r1, #56]
+	ldrd	r10, r11, [r1, #56]
 #endif
-	rev	r12, r12
-	rev	lr, lr
 	rev	r4, r4
 	rev	r5, r5
 	rev	r6, r6
 	rev	r7, r7
 	rev	r8, r8
 	rev	r9, r9
-	str	lr, [sp, #32]
-	str	r12, [sp, #36]
-	str	r5, [sp, #40]
-	str	r4, [sp, #44]
-	str	r7, [sp, #48]
-	str	r6, [sp, #52]
-	str	r9, [sp, #56]
-	str	r8, [sp, #60]
+	rev	r10, r10
+	rev	r11, r11
+	str	r5, [sp, #32]
+	str	r4, [sp, #36]
+	str	r7, [sp, #40]
+	str	r6, [sp, #44]
+	str	r9, [sp, #48]
+	str	r8, [sp, #52]
+	str	r11, [sp, #56]
+	str	r10, [sp, #60]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #64]
-	ldr	lr, [r1, #68]
+	ldr	r4, [r1, #64]
+	ldr	r5, [r1, #68]
 #else
-	ldrd  r12, lr, [r1, #64]
+	ldrd	r4, r5, [r1, #64]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #72]
-	ldr	r5, [r1, #76]
+	ldr	r6, [r1, #72]
+	ldr	r7, [r1, #76]
 #else
-	ldrd  r4, r5, [r1, #72]
+	ldrd	r6, r7, [r1, #72]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #80]
-	ldr	r7, [r1, #84]
+	ldr	r8, [r1, #80]
+	ldr	r9, [r1, #84]
 #else
-	ldrd  r6, r7, [r1, #80]
+	ldrd	r8, r9, [r1, #80]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #88]
-	ldr	r9, [r1, #92]
+	ldr	r10, [r1, #88]
+	ldr	r11, [r1, #92]
 #else
-	ldrd  r8, r9, [r1, #88]
+	ldrd	r10, r11, [r1, #88]
 #endif
-	rev	r12, r12
-	rev	lr, lr
 	rev	r4, r4
 	rev	r5, r5
 	rev	r6, r6
 	rev	r7, r7
 	rev	r8, r8
 	rev	r9, r9
-	str	lr, [sp, #64]
-	str	r12, [sp, #68]
-	str	r5, [sp, #72]
-	str	r4, [sp, #76]
-	str	r7, [sp, #80]
-	str	r6, [sp, #84]
-	str	r9, [sp, #88]
-	str	r8, [sp, #92]
+	rev	r10, r10
+	rev	r11, r11
+	str	r5, [sp, #64]
+	str	r4, [sp, #68]
+	str	r7, [sp, #72]
+	str	r6, [sp, #76]
+	str	r9, [sp, #80]
+	str	r8, [sp, #84]
+	str	r11, [sp, #88]
+	str	r10, [sp, #92]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r1, #96]
-	ldr	lr, [r1, #100]
+	ldr	r4, [r1, #96]
+	ldr	r5, [r1, #100]
 #else
-	ldrd  r12, lr, [r1, #96]
+	ldrd	r4, r5, [r1, #96]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r1, #104]
-	ldr	r5, [r1, #108]
+	ldr	r6, [r1, #104]
+	ldr	r7, [r1, #108]
 #else
-	ldrd  r4, r5, [r1, #104]
+	ldrd	r6, r7, [r1, #104]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r1, #112]
-	ldr	r7, [r1, #116]
+	ldr	r8, [r1, #112]
+	ldr	r9, [r1, #116]
 #else
-	ldrd  r6, r7, [r1, #112]
+	ldrd	r8, r9, [r1, #112]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r1, #120]
-	ldr	r9, [r1, #124]
+	ldr	r10, [r1, #120]
+	ldr	r11, [r1, #124]
 #else
-	ldrd  r8, r9, [r1, #120]
+	ldrd	r10, r11, [r1, #120]
 #endif
-	rev	r12, r12
-	rev	lr, lr
 	rev	r4, r4
 	rev	r5, r5
 	rev	r6, r6
 	rev	r7, r7
 	rev	r8, r8
 	rev	r9, r9
-	str	lr, [sp, #96]
-	str	r12, [sp, #100]
-	str	r5, [sp, #104]
-	str	r4, [sp, #108]
-	str	r7, [sp, #112]
-	str	r6, [sp, #116]
-	str	r9, [sp, #120]
-	str	r8, [sp, #124]
+	rev	r10, r10
+	rev	r11, r11
+	str	r5, [sp, #96]
+	str	r4, [sp, #100]
+	str	r7, [sp, #104]
+	str	r6, [sp, #108]
+	str	r9, [sp, #112]
+	str	r8, [sp, #116]
+	str	r11, [sp, #120]
+	str	r10, [sp, #124]
 	# Pre-calc: b ^ c
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [r0, #8]
-	ldr	r9, [r0, #12]
+	ldr	r10, [r0, #8]
+	ldr	r11, [r0, #12]
 #else
-	ldrd  r8, r9, [r0, #8]
+	ldrd	r10, r11, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
 #else
-	ldrd  r12, lr, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-	eor	r8, r8, r12
-	eor	r9, r9, lr
-	mov	r10, #4
+	eor	r10, r10, r4
+	eor	r11, r11, r5
+	mov	r12, #4
 	# Start of 16 rounds
 L_SHA512_transform_len_start:
 	# Round 0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
 #else
-	ldrd  r12, lr, [r0, #32]
+	ldrd	r4, r5, [r0, #32]
 #endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp]
-	ldr	r7, [sp, #4]
-#else
-	ldrd  r6, r7, [sp]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3]
-	ldr	r5, [r3, #4]
-#else
-	ldrd  r4, r5, [r3]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #24]
-	str	r7, [r0, #28]
-#else
-	strd  r6, r7, [r0, #24]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #56]
 	ldr	r5, [r0, #60]
 #else
-	ldrd  r4, r5, [r0, #56]
+	ldrd	r4, r5, [r0, #56]
 #endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #56]
 	str	r5, [r0, #60]
 #else
-	strd  r4, r5, [r0, #56]
+	strd	r4, r5, [r0, #56]
 #endif
-	mov	r8, r6
-	mov	r9, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp]
+	ldr	r9, [sp, #4]
+#else
+	ldrd	r8, r9, [sp]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3]
+	ldr	r7, [r3, #4]
+#else
+	ldrd	r6, r7, [r3]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #24]
+	str	r9, [r0, #28]
+#else
+	strd	r8, r9, [r0, #24]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #56]
+	str	r7, [r0, #60]
+#else
+	strd	r6, r7, [r0, #56]
+#endif
+	mov	r10, r8
+	mov	r11, r9
 	# Calc new W[0]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #112]
-	ldr	lr, [sp, #116]
+	ldr	r4, [sp, #112]
+	ldr	r5, [sp, #116]
 #else
-	ldrd  r12, lr, [sp, #112]
+	ldrd	r4, r5, [sp, #112]
 #endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp]
-	ldr	lr, [sp, #4]
+	ldr	r4, [sp]
+	ldr	r5, [sp, #4]
 #else
-	ldrd  r12, lr, [sp]
+	ldrd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #72]
-	ldr	r7, [sp, #76]
+	ldr	r8, [sp, #72]
+	ldr	r9, [sp, #76]
 #else
-	ldrd  r6, r7, [sp, #72]
+	ldrd	r8, r9, [sp, #72]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp]
-	str	lr, [sp, #4]
+	str	r4, [sp]
+	str	r5, [sp, #4]
 #else
-	strd  r12, lr, [sp]
+	strd	r4, r5, [sp]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #8]
-	ldr	lr, [sp, #12]
+	ldr	r4, [sp, #8]
+	ldr	r5, [sp, #12]
 #else
-	ldrd  r12, lr, [sp, #8]
+	ldrd	r4, r5, [sp, #8]
 #endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp]
-	ldr	lr, [sp, #4]
+	ldr	r4, [sp]
+	ldr	r5, [sp, #4]
 #else
-	ldrd  r12, lr, [sp]
+	ldrd	r4, r5, [sp]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp]
-	str	lr, [sp, #4]
+	str	r4, [sp]
+	str	r5, [sp, #4]
 #else
-	strd  r12, lr, [sp]
+	strd	r4, r5, [sp]
 #endif
 	# Round 1
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
 #else
-	ldrd  r12, lr, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #8]
-	ldr	r7, [sp, #12]
-#else
-	ldrd  r6, r7, [sp, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #8]
-	ldr	r5, [r3, #12]
-#else
-	ldrd  r4, r5, [r3, #8]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #16]
-	str	r7, [r0, #20]
-#else
-	strd  r6, r7, [r0, #16]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #48]
 	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r0, #48]
+	ldrd	r4, r5, [r0, #48]
 #endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #48]
 	str	r5, [r0, #52]
 #else
-	strd  r4, r5, [r0, #48]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[1]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #120]
-	ldr	lr, [sp, #124]
-#else
-	ldrd  r12, lr, [sp, #120]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #8]
-	ldr	lr, [sp, #12]
-#else
-	ldrd  r12, lr, [sp, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #80]
-	ldr	r7, [sp, #84]
-#else
-	ldrd  r6, r7, [sp, #80]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #8]
-	str	lr, [sp, #12]
-#else
-	strd  r12, lr, [sp, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #16]
-	ldr	lr, [sp, #20]
-#else
-	ldrd  r12, lr, [sp, #16]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #8]
-	ldr	lr, [sp, #12]
-#else
-	ldrd  r12, lr, [sp, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #8]
-	str	lr, [sp, #12]
-#else
-	strd  r12, lr, [sp, #8]
-#endif
-	# Round 2
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
+	strd	r4, r5, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #24]
 	ldr	r5, [r0, #28]
 #else
-	ldrd  r4, r5, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #32]
 	ldr	r7, [r0, #36]
 #else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
+	ldrd	r6, r7, [r0, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #16]
-	ldr	r7, [sp, #20]
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
 #else
-	ldrd  r6, r7, [sp, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #16]
-	ldr	r5, [r3, #20]
-#else
-	ldrd  r4, r5, [r3, #16]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #8]
-	str	r7, [r0, #12]
-#else
-	strd  r6, r7, [r0, #8]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #40]
-	str	r5, [r0, #44]
-#else
-	strd  r4, r5, [r0, #40]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[2]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp]
-	ldr	lr, [sp, #4]
-#else
-	ldrd  r12, lr, [sp]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #16]
-	ldr	lr, [sp, #20]
-#else
-	ldrd  r12, lr, [sp, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #88]
-	ldr	r7, [sp, #92]
-#else
-	ldrd  r6, r7, [sp, #88]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #16]
-	str	lr, [sp, #20]
-#else
-	strd  r12, lr, [sp, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #24]
-	ldr	lr, [sp, #28]
-#else
-	ldrd  r12, lr, [sp, #24]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #16]
-	ldr	lr, [sp, #20]
-#else
-	ldrd  r12, lr, [sp, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #16]
-	str	lr, [sp, #20]
-#else
-	strd  r12, lr, [sp, #16]
-#endif
-	# Round 3
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #24]
-	ldr	r7, [sp, #28]
-#else
-	ldrd  r6, r7, [sp, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #24]
-	ldr	r5, [r3, #28]
-#else
-	ldrd  r4, r5, [r3, #24]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0]
-	str	r7, [r0, #4]
-#else
-	strd  r6, r7, [r0]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
+	ldrd	r8, r9, [r0, #40]
 #endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #48]
 	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r0, #48]
+	ldrd	r4, r5, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
+	ldr	r8, [sp, #8]
+	ldr	r9, [sp, #12]
 #else
-	strd  r12, lr, [r0, #32]
+	ldrd	r8, r9, [sp, #8]
 #endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
+	ldr	r6, [r3, #8]
+	ldr	r7, [r3, #12]
 #else
-	ldrd  r4, r5, [r0, #32]
+	ldrd	r6, r7, [r3, #8]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #32]
-	str	r5, [r0, #36]
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
 #else
-	strd  r4, r5, [r0, #32]
+	ldrd	r8, r9, [r0, #16]
 #endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[3]
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #8]
-	ldr	lr, [sp, #12]
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
 #else
-	ldrd  r12, lr, [sp, #8]
+	strd	r4, r5, [r0, #48]
 #endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
+	adds	r8, r8, r4
+	adc	r9, r9, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #24]
-	ldr	lr, [sp, #28]
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
 #else
-	ldrd  r12, lr, [sp, #24]
+	ldrd	r4, r5, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #96]
-	ldr	r7, [sp, #100]
+	str	r8, [r0, #16]
+	str	r9, [r0, #20]
 #else
-	ldrd  r6, r7, [sp, #96]
+	strd	r8, r9, [r0, #16]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #24]
-	str	lr, [sp, #28]
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
 #else
-	strd  r12, lr, [sp, #24]
+	ldrd	r4, r5, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #32]
-	ldr	lr, [sp, #36]
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
 #else
-	ldrd  r12, lr, [sp, #32]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #24]
-	ldr	lr, [sp, #28]
-#else
-	ldrd  r12, lr, [sp, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #24]
-	str	lr, [sp, #28]
-#else
-	strd  r12, lr, [sp, #24]
-#endif
-	# Round 4
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
+	ldrd	r6, r7, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
 #else
-	ldrd  r12, lr, [r0]
+	strd	r4, r5, [r0, #48]
 #endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #32]
-	ldr	r7, [sp, #36]
-#else
-	ldrd  r6, r7, [sp, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #32]
-	ldr	r5, [r3, #36]
-#else
-	ldrd  r4, r5, [r3, #32]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #56]
-	str	r7, [r0, #60]
-#else
-	strd  r6, r7, [r0, #56]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #24]
-	str	r5, [r0, #28]
-#else
-	strd  r4, r5, [r0, #24]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[4]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #16]
-	ldr	lr, [sp, #20]
-#else
-	ldrd  r12, lr, [sp, #16]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #32]
-	ldr	lr, [sp, #36]
-#else
-	ldrd  r12, lr, [sp, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #104]
-	ldr	r7, [sp, #108]
-#else
-	ldrd  r6, r7, [sp, #104]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #32]
-	str	lr, [sp, #36]
-#else
-	strd  r12, lr, [sp, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #40]
-	ldr	lr, [sp, #44]
-#else
-	ldrd  r12, lr, [sp, #40]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #32]
-	ldr	lr, [sp, #36]
-#else
-	ldrd  r12, lr, [sp, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #32]
-	str	lr, [sp, #36]
-#else
-	strd  r12, lr, [sp, #32]
-#endif
-	# Round 5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #40]
-	ldr	r7, [sp, #44]
-#else
-	ldrd  r6, r7, [sp, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #40]
-	ldr	r5, [r3, #44]
-#else
-	ldrd  r4, r5, [r3, #40]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #48]
 	ldr	r7, [r0, #52]
 #else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
+	ldrd	r6, r7, [r0, #48]
 #endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #48]
 	str	r7, [r0, #52]
 #else
-	strd  r6, r7, [r0, #48]
+	strd	r6, r7, [r0, #48]
 #endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[1]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
+	ldr	r4, [sp, #120]
+	ldr	r5, [sp, #124]
 #else
-	ldrd  r12, lr, [r0, #16]
+	ldrd	r4, r5, [sp, #120]
 #endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
+	ldr	r4, [sp, #8]
+	ldr	r5, [sp, #12]
 #else
-	ldrd  r6, r7, [r0, #24]
+	ldrd	r4, r5, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
+	ldr	r8, [sp, #80]
+	ldr	r9, [sp, #84]
 #else
-	ldrd  r4, r5, [r0, #32]
+	ldrd	r8, r9, [sp, #80]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #8]
+	str	r5, [sp, #12]
+#else
+	strd	r4, r5, [sp, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
+	ldr	r4, [sp, #16]
+	ldr	r5, [sp, #20]
 #else
-	strd  r12, lr, [r0, #16]
+	ldrd	r4, r5, [sp, #16]
 #endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #8]
+	ldr	r5, [sp, #12]
+#else
+	ldrd	r4, r5, [sp, #8]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #8]
+	str	r5, [sp, #12]
+#else
+	strd	r4, r5, [sp, #8]
+#endif
+	# Round 2
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #16]
+	ldr	r9, [sp, #20]
+#else
+	ldrd	r8, r9, [sp, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #16]
+	ldr	r7, [r3, #20]
+#else
+	ldrd	r6, r7, [r3, #16]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #16]
-	str	r5, [r0, #20]
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
 #else
-	strd  r4, r5, [r0, #16]
+	ldrd	r8, r9, [r0, #8]
 #endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[5]
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #24]
-	ldr	lr, [sp, #28]
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
 #else
-	ldrd  r12, lr, [sp, #24]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #40]
-	ldr	lr, [sp, #44]
-#else
-	ldrd  r12, lr, [sp, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #112]
-	ldr	r7, [sp, #116]
-#else
-	ldrd  r6, r7, [sp, #112]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #40]
-	str	lr, [sp, #44]
-#else
-	strd  r12, lr, [sp, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #48]
-	ldr	lr, [sp, #52]
-#else
-	ldrd  r12, lr, [sp, #48]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #40]
-	ldr	lr, [sp, #44]
-#else
-	ldrd  r12, lr, [sp, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #40]
-	str	lr, [sp, #44]
-#else
-	strd  r12, lr, [sp, #40]
-#endif
-	# Round 6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #48]
-	ldr	r7, [sp, #52]
-#else
-	ldrd  r6, r7, [sp, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #48]
-	ldr	r5, [r3, #52]
-#else
-	ldrd  r4, r5, [r3, #48]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #40]
-	str	r7, [r0, #44]
-#else
-	strd  r6, r7, [r0, #40]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #8]
-	str	r5, [r0, #12]
-#else
-	strd  r4, r5, [r0, #8]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[6]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #32]
-	ldr	lr, [sp, #36]
-#else
-	ldrd  r12, lr, [sp, #32]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #48]
-	ldr	lr, [sp, #52]
-#else
-	ldrd  r12, lr, [sp, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #120]
-	ldr	r7, [sp, #124]
-#else
-	ldrd  r6, r7, [sp, #120]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #48]
-	str	lr, [sp, #52]
-#else
-	strd  r12, lr, [sp, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #56]
-	ldr	lr, [sp, #60]
-#else
-	ldrd  r12, lr, [sp, #56]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #48]
-	ldr	lr, [sp, #52]
-#else
-	ldrd  r12, lr, [sp, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #48]
-	str	lr, [sp, #52]
-#else
-	strd  r12, lr, [sp, #48]
-#endif
-	# Round 7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
+	strd	r4, r5, [r0, #40]
 #endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #48]
 	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r0, #48]
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #8]
+	str	r9, [r0, #12]
+#else
+	strd	r8, r9, [r0, #8]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #56]
 	ldr	r7, [r0, #60]
 #else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
+	ldrd	r6, r7, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #56]
-	ldr	r7, [sp, #60]
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
 #else
-	ldrd  r6, r7, [sp, #56]
+	strd	r4, r5, [r0, #40]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #56]
-	ldr	r5, [r3, #60]
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
 #else
-	ldrd  r4, r5, [r3, #56]
+	ldrd	r6, r7, [r0, #40]
 #endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
+	adds	r6, r6, r10
+	adc	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
+	str	r6, [r0, #40]
+	str	r7, [r0, #44]
 #else
-	ldrd  r6, r7, [r0, #32]
+	strd	r6, r7, [r0, #40]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[2]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
+	ldr	r4, [sp]
+	ldr	r5, [sp, #4]
 #else
-	strd  r12, lr, [r0]
+	ldrd	r4, r5, [sp]
 #endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
+	ldr	r4, [sp, #16]
+	ldr	r5, [sp, #20]
 #else
-	ldrd  r12, lr, [r0, #8]
+	ldrd	r4, r5, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #32]
-	str	r7, [r0, #36]
+	ldr	r8, [sp, #88]
+	ldr	r9, [sp, #92]
 #else
-	strd  r6, r7, [r0, #32]
+	ldrd	r8, r9, [sp, #88]
 #endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	str	r4, [sp, #16]
+	str	r5, [sp, #20]
 #else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
+	strd	r4, r5, [sp, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
+	ldr	r4, [sp, #24]
+	ldr	r5, [sp, #28]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [sp, #24]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #16]
+	ldr	r5, [sp, #20]
+#else
+	ldrd	r4, r5, [sp, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #16]
+	str	r5, [sp, #20]
+#else
+	strd	r4, r5, [sp, #16]
+#endif
+	# Round 3
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
 #else
-	strd  r12, lr, [r0]
+	ldrd	r4, r5, [r0, #8]
 #endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
 #else
-	ldrd  r4, r5, [r0]
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #24]
+	ldr	r9, [sp, #28]
+#else
+	ldrd	r8, r9, [sp, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #24]
+	ldr	r7, [r3, #28]
+#else
+	ldrd	r6, r7, [r3, #24]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0]
-	str	r5, [r0, #4]
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	ldrd	r8, r9, [r0]
 #endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[7]
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #40]
-	ldr	lr, [sp, #44]
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
 #else
-	ldrd  r12, lr, [sp, #40]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #56]
-	ldr	lr, [sp, #60]
-#else
-	ldrd  r12, lr, [sp, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp]
-	ldr	r7, [sp, #4]
-#else
-	ldrd  r6, r7, [sp]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #56]
-	str	lr, [sp, #60]
-#else
-	strd  r12, lr, [sp, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #64]
-	ldr	lr, [sp, #68]
-#else
-	ldrd  r12, lr, [sp, #64]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #56]
-	ldr	lr, [sp, #60]
-#else
-	ldrd  r12, lr, [sp, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #56]
-	str	lr, [sp, #60]
-#else
-	strd  r12, lr, [sp, #56]
-#endif
-	# Round 8
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
+	strd	r4, r5, [r0, #32]
 #endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #40]
 	ldr	r5, [r0, #44]
 #else
-	ldrd  r4, r5, [r0, #40]
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0]
+	str	r9, [r0, #4]
+#else
+	strd	r8, r9, [r0]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #48]
 	ldr	r7, [r0, #52]
 #else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
+	ldrd	r6, r7, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #64]
-	ldr	r7, [sp, #68]
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
 #else
-	ldrd  r6, r7, [sp, #64]
+	strd	r4, r5, [r0, #32]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #64]
-	ldr	r5, [r3, #68]
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
 #else
-	ldrd  r4, r5, [r3, #64]
+	ldrd	r6, r7, [r0, #32]
 #endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #32]
+	str	r7, [r0, #36]
+#else
+	strd	r6, r7, [r0, #32]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[3]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #8]
+	ldr	r5, [sp, #12]
+#else
+	ldrd	r4, r5, [sp, #8]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #24]
+	ldr	r5, [sp, #28]
+#else
+	ldrd	r4, r5, [sp, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #96]
+	ldr	r9, [sp, #100]
+#else
+	ldrd	r8, r9, [sp, #96]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #24]
+	str	r5, [sp, #28]
+#else
+	strd	r4, r5, [sp, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #32]
+	ldr	r5, [sp, #36]
+#else
+	ldrd	r4, r5, [sp, #32]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #24]
+	ldr	r5, [sp, #28]
+#else
+	ldrd	r4, r5, [sp, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #24]
+	str	r5, [sp, #28]
+#else
+	strd	r4, r5, [sp, #24]
+#endif
+	# Round 4
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #32]
+	ldr	r9, [sp, #36]
+#else
+	ldrd	r8, r9, [sp, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #32]
+	ldr	r7, [r3, #36]
+#else
+	ldrd	r6, r7, [r3, #32]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #56]
+	str	r9, [r0, #60]
+#else
+	strd	r8, r9, [r0, #56]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
+	ldrd	r6, r7, [r0, #24]
 #endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #24]
 	str	r7, [r0, #28]
 #else
-	strd  r6, r7, [r0, #24]
+	strd	r6, r7, [r0, #24]
 #endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[4]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
+	ldr	r4, [sp, #16]
+	ldr	r5, [sp, #20]
 #else
-	ldrd  r12, lr, [r0, #56]
+	ldrd	r4, r5, [sp, #16]
 #endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
+	ldr	r4, [sp, #32]
+	ldr	r5, [sp, #36]
 #else
-	ldrd  r6, r7, [r0]
+	ldrd	r4, r5, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	ldr	r8, [sp, #104]
+	ldr	r9, [sp, #108]
 #else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r8, r9, [sp, #104]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #32]
+	str	r5, [sp, #36]
+#else
+	strd	r4, r5, [sp, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
+	ldr	r4, [sp, #40]
+	ldr	r5, [sp, #44]
 #else
-	strd  r12, lr, [r0, #56]
+	ldrd	r4, r5, [sp, #40]
 #endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #32]
+	ldr	r5, [sp, #36]
+#else
+	ldrd	r4, r5, [sp, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #32]
+	str	r5, [sp, #36]
+#else
+	strd	r4, r5, [sp, #32]
+#endif
+	# Round 5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #56]
 	ldr	r5, [r0, #60]
 #else
-	ldrd  r4, r5, [r0, #56]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #56]
-	str	r5, [r0, #60]
-#else
-	strd  r4, r5, [r0, #56]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[8]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #48]
-	ldr	lr, [sp, #52]
-#else
-	ldrd  r12, lr, [sp, #48]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #64]
-	ldr	lr, [sp, #68]
-#else
-	ldrd  r12, lr, [sp, #64]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #8]
-	ldr	r7, [sp, #12]
-#else
-	ldrd  r6, r7, [sp, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #64]
-	str	lr, [sp, #68]
-#else
-	strd  r12, lr, [sp, #64]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #72]
-	ldr	lr, [sp, #76]
-#else
-	ldrd  r12, lr, [sp, #72]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #64]
-	ldr	lr, [sp, #68]
-#else
-	ldrd  r12, lr, [sp, #64]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #64]
-	str	lr, [sp, #68]
-#else
-	strd  r12, lr, [sp, #64]
-#endif
-	# Round 9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #72]
-	ldr	r7, [sp, #76]
-#else
-	ldrd  r6, r7, [sp, #72]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #72]
-	ldr	r5, [r3, #76]
-#else
-	ldrd  r4, r5, [r3, #72]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #16]
-	str	r7, [r0, #20]
-#else
-	strd  r6, r7, [r0, #16]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #48]
-	ldr	r5, [r0, #52]
-#else
-	ldrd  r4, r5, [r0, #48]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #48]
-	str	r5, [r0, #52]
-#else
-	strd  r4, r5, [r0, #48]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[9]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #56]
-	ldr	lr, [sp, #60]
-#else
-	ldrd  r12, lr, [sp, #56]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #72]
-	ldr	lr, [sp, #76]
-#else
-	ldrd  r12, lr, [sp, #72]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #16]
-	ldr	r7, [sp, #20]
-#else
-	ldrd  r6, r7, [sp, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #72]
-	str	lr, [sp, #76]
-#else
-	strd  r12, lr, [sp, #72]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #80]
-	ldr	lr, [sp, #84]
-#else
-	ldrd  r12, lr, [sp, #80]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #72]
-	ldr	lr, [sp, #76]
-#else
-	ldrd  r12, lr, [sp, #72]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #72]
-	str	lr, [sp, #76]
-#else
-	strd  r12, lr, [sp, #72]
-#endif
-	# Round 10
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #80]
-	ldr	r7, [sp, #84]
-#else
-	ldrd  r6, r7, [sp, #80]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #80]
-	ldr	r5, [r3, #84]
-#else
-	ldrd  r4, r5, [r3, #80]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #8]
-	str	r7, [r0, #12]
-#else
-	strd  r6, r7, [r0, #8]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #40]
-	str	r5, [r0, #44]
-#else
-	strd  r4, r5, [r0, #40]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[10]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #64]
-	ldr	lr, [sp, #68]
-#else
-	ldrd  r12, lr, [sp, #64]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #80]
-	ldr	lr, [sp, #84]
-#else
-	ldrd  r12, lr, [sp, #80]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #24]
-	ldr	r7, [sp, #28]
-#else
-	ldrd  r6, r7, [sp, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #80]
-	str	lr, [sp, #84]
-#else
-	strd  r12, lr, [sp, #80]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #88]
-	ldr	lr, [sp, #92]
-#else
-	ldrd  r12, lr, [sp, #88]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #80]
-	ldr	lr, [sp, #84]
-#else
-	ldrd  r12, lr, [sp, #80]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #80]
-	str	lr, [sp, #84]
-#else
-	strd  r12, lr, [sp, #80]
-#endif
-	# Round 11
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
+	ldrd	r4, r5, [r0, #56]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #88]
-	ldr	r7, [sp, #92]
-#else
-	ldrd  r6, r7, [sp, #88]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #88]
-	ldr	r5, [r3, #92]
-#else
-	ldrd  r4, r5, [r3, #88]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0]
-	str	r7, [r0, #4]
-#else
-	strd  r6, r7, [r0]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #48]
-	ldr	r5, [r0, #52]
-#else
-	ldrd  r4, r5, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #32]
-	str	r5, [r0, #36]
-#else
-	strd  r4, r5, [r0, #32]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[11]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #72]
-	ldr	lr, [sp, #76]
-#else
-	ldrd  r12, lr, [sp, #72]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #88]
-	ldr	lr, [sp, #92]
-#else
-	ldrd  r12, lr, [sp, #88]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #32]
-	ldr	r7, [sp, #36]
-#else
-	ldrd  r6, r7, [sp, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #88]
-	str	lr, [sp, #92]
-#else
-	strd  r12, lr, [sp, #88]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #96]
-	ldr	lr, [sp, #100]
-#else
-	ldrd  r12, lr, [sp, #96]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #88]
-	ldr	lr, [sp, #92]
-#else
-	ldrd  r12, lr, [sp, #88]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #88]
-	str	lr, [sp, #92]
-#else
-	strd  r12, lr, [sp, #88]
-#endif
-	# Round 12
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #96]
-	ldr	r7, [sp, #100]
-#else
-	ldrd  r6, r7, [sp, #96]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #96]
-	ldr	r5, [r3, #100]
-#else
-	ldrd  r4, r5, [r3, #96]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #56]
-	str	r7, [r0, #60]
-#else
-	strd  r6, r7, [r0, #56]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #24]
-	str	r5, [r0, #28]
-#else
-	strd  r4, r5, [r0, #24]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[12]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #80]
-	ldr	lr, [sp, #84]
-#else
-	ldrd  r12, lr, [sp, #80]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #96]
-	ldr	lr, [sp, #100]
-#else
-	ldrd  r12, lr, [sp, #96]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #40]
-	ldr	r7, [sp, #44]
-#else
-	ldrd  r6, r7, [sp, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #96]
-	str	lr, [sp, #100]
-#else
-	strd  r12, lr, [sp, #96]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #104]
-	ldr	lr, [sp, #108]
-#else
-	ldrd  r12, lr, [sp, #104]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #96]
-	ldr	lr, [sp, #100]
-#else
-	ldrd  r12, lr, [sp, #96]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #96]
-	str	lr, [sp, #100]
-#else
-	strd  r12, lr, [sp, #96]
-#endif
-	# Round 13
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #104]
-	ldr	r7, [sp, #108]
-#else
-	ldrd  r6, r7, [sp, #104]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #104]
-	ldr	r5, [r3, #108]
-#else
-	ldrd  r4, r5, [r3, #104]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #48]
-	str	r7, [r0, #52]
-#else
-	strd  r6, r7, [r0, #48]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r4, r5, [r0, #16]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[13]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #88]
-	ldr	lr, [sp, #92]
-#else
-	ldrd  r12, lr, [sp, #88]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #104]
-	ldr	lr, [sp, #108]
-#else
-	ldrd  r12, lr, [sp, #104]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #48]
-	ldr	r7, [sp, #52]
-#else
-	ldrd  r6, r7, [sp, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #104]
-	str	lr, [sp, #108]
-#else
-	strd  r12, lr, [sp, #104]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #112]
-	ldr	lr, [sp, #116]
-#else
-	ldrd  r12, lr, [sp, #112]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #104]
-	ldr	lr, [sp, #108]
-#else
-	ldrd  r12, lr, [sp, #104]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #104]
-	str	lr, [sp, #108]
-#else
-	strd  r12, lr, [sp, #104]
-#endif
-	# Round 14
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
+	strd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #56]
 	ldr	r5, [r0, #60]
 #else
-	ldrd  r4, r5, [r0, #56]
+	ldrd	r4, r5, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0]
 	ldr	r7, [r0, #4]
 #else
-	ldrd  r6, r7, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
+	ldrd	r6, r7, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #112]
-	ldr	r7, [sp, #116]
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
 #else
-	ldrd  r6, r7, [sp, #112]
+	ldrd	r8, r9, [r0, #8]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #112]
-	ldr	r5, [r3, #116]
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r3, #112]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #40]
-	str	r7, [r0, #44]
+	ldr	r8, [sp, #40]
+	ldr	r9, [sp, #44]
 #else
-	strd  r6, r7, [r0, #40]
+	ldrd	r8, r9, [sp, #40]
 #endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
+	ldr	r6, [r3, #40]
+	ldr	r7, [r3, #44]
 #else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
+	ldrd	r6, r7, [r3, #40]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #48]
+	str	r9, [r0, #52]
+#else
+	strd	r8, r9, [r0, #48]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #16]
+	str	r7, [r0, #20]
+#else
+	strd	r6, r7, [r0, #16]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[5]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #24]
+	ldr	r5, [sp, #28]
+#else
+	ldrd	r4, r5, [sp, #24]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #40]
+	ldr	r5, [sp, #44]
+#else
+	ldrd	r4, r5, [sp, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #112]
+	ldr	r9, [sp, #116]
+#else
+	ldrd	r8, r9, [sp, #112]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #40]
+	str	r5, [sp, #44]
+#else
+	strd	r4, r5, [sp, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #48]
+	ldr	r5, [sp, #52]
+#else
+	ldrd	r4, r5, [sp, #48]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #40]
+	ldr	r5, [sp, #44]
+#else
+	ldrd	r4, r5, [sp, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #40]
+	str	r5, [sp, #44]
+#else
+	strd	r4, r5, [sp, #40]
+#endif
+	# Round 6
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #8]
 	str	r5, [r0, #12]
 #else
-	strd  r4, r5, [r0, #8]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Calc new W[14]
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #96]
-	ldr	lr, [sp, #100]
-#else
-	ldrd  r12, lr, [sp, #96]
-#endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #112]
-	ldr	lr, [sp, #116]
-#else
-	ldrd  r12, lr, [sp, #112]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #56]
-	ldr	r7, [sp, #60]
-#else
-	ldrd  r6, r7, [sp, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #112]
-	str	lr, [sp, #116]
-#else
-	strd  r12, lr, [sp, #112]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #120]
-	ldr	lr, [sp, #124]
-#else
-	ldrd  r12, lr, [sp, #120]
-#endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #112]
-	ldr	lr, [sp, #116]
-#else
-	ldrd  r12, lr, [sp, #112]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #112]
-	str	lr, [sp, #116]
-#else
-	strd  r12, lr, [sp, #112]
-#endif
-	# Round 15
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
+	strd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #48]
 	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r0, #48]
+	ldrd	r4, r5, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #56]
 	ldr	r7, [r0, #60]
 #else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
+	ldrd	r6, r7, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #120]
-	ldr	r7, [sp, #124]
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
 #else
-	ldrd  r6, r7, [sp, #120]
+	ldrd	r8, r9, [r0]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #120]
-	ldr	r5, [r3, #124]
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
 #else
-	ldrd  r4, r5, [r3, #120]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
+	ldrd	r4, r5, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #32]
-	str	r7, [r0, #36]
+	ldr	r8, [sp, #48]
+	ldr	r9, [sp, #52]
 #else
-	strd  r6, r7, [r0, #32]
+	ldrd	r8, r9, [sp, #48]
 #endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
+	ldr	r6, [r3, #48]
+	ldr	r7, [r3, #52]
 #else
-	ldrd  r12, lr, [r0]
+	ldrd	r6, r7, [r3, #48]
 #endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #40]
+	str	r9, [r0, #44]
+#else
+	strd	r8, r9, [r0, #40]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
+#else
+	strd	r6, r7, [r0, #8]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[6]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #32]
+	ldr	r5, [sp, #36]
+#else
+	ldrd	r4, r5, [sp, #32]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #48]
+	ldr	r5, [sp, #52]
+#else
+	ldrd	r4, r5, [sp, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #120]
+	ldr	r9, [sp, #124]
+#else
+	ldrd	r8, r9, [sp, #120]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #48]
+	str	r5, [sp, #52]
+#else
+	strd	r4, r5, [sp, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #56]
+	ldr	r5, [sp, #60]
+#else
+	ldrd	r4, r5, [sp, #56]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #48]
+	ldr	r5, [sp, #52]
+#else
+	ldrd	r4, r5, [sp, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #48]
+	str	r5, [sp, #52]
+#else
+	strd	r4, r5, [sp, #48]
+#endif
+	# Round 7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #56]
+	ldr	r9, [sp, #60]
+#else
+	ldrd	r8, r9, [sp, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #56]
+	ldr	r7, [r3, #60]
+#else
+	ldrd	r6, r7, [r3, #56]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #32]
+	str	r9, [r0, #36]
+#else
+	strd	r8, r9, [r0, #32]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0]
+	str	r7, [r0, #4]
+#else
+	strd	r6, r7, [r0]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[7]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #40]
+	ldr	r5, [sp, #44]
+#else
+	ldrd	r4, r5, [sp, #40]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #56]
+	ldr	r5, [sp, #60]
+#else
+	ldrd	r4, r5, [sp, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp]
+	ldr	r9, [sp, #4]
+#else
+	ldrd	r8, r9, [sp]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #56]
+	str	r5, [sp, #60]
+#else
+	strd	r4, r5, [sp, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #64]
+	ldr	r5, [sp, #68]
+#else
+	ldrd	r4, r5, [sp, #64]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #56]
+	ldr	r5, [sp, #60]
+#else
+	ldrd	r4, r5, [sp, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #56]
+	str	r5, [sp, #60]
+#else
+	strd	r4, r5, [sp, #56]
+#endif
+	# Round 8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #64]
+	ldr	r9, [sp, #68]
+#else
+	ldrd	r8, r9, [sp, #64]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #64]
+	ldr	r7, [r3, #68]
+#else
+	ldrd	r6, r7, [r3, #64]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #24]
+	str	r9, [r0, #28]
+#else
+	strd	r8, r9, [r0, #24]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #56]
+	str	r7, [r0, #60]
+#else
+	strd	r6, r7, [r0, #56]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[8]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #48]
+	ldr	r5, [sp, #52]
+#else
+	ldrd	r4, r5, [sp, #48]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #64]
+	ldr	r5, [sp, #68]
+#else
+	ldrd	r4, r5, [sp, #64]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #8]
+	ldr	r9, [sp, #12]
+#else
+	ldrd	r8, r9, [sp, #8]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #64]
+	str	r5, [sp, #68]
+#else
+	strd	r4, r5, [sp, #64]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #72]
+	ldr	r5, [sp, #76]
+#else
+	ldrd	r4, r5, [sp, #72]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #64]
+	ldr	r5, [sp, #68]
+#else
+	ldrd	r4, r5, [sp, #64]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #64]
+	str	r5, [sp, #68]
+#else
+	strd	r4, r5, [sp, #64]
+#endif
+	# Round 9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #72]
+	ldr	r9, [sp, #76]
+#else
+	ldrd	r8, r9, [sp, #72]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #72]
+	ldr	r7, [r3, #76]
+#else
+	ldrd	r6, r7, [r3, #72]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #16]
+	str	r9, [r0, #20]
+#else
+	strd	r8, r9, [r0, #16]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #48]
+	str	r7, [r0, #52]
+#else
+	strd	r6, r7, [r0, #48]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[9]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #56]
+	ldr	r5, [sp, #60]
+#else
+	ldrd	r4, r5, [sp, #56]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #72]
+	ldr	r5, [sp, #76]
+#else
+	ldrd	r4, r5, [sp, #72]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #16]
+	ldr	r9, [sp, #20]
+#else
+	ldrd	r8, r9, [sp, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #72]
+	str	r5, [sp, #76]
+#else
+	strd	r4, r5, [sp, #72]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #80]
+	ldr	r5, [sp, #84]
+#else
+	ldrd	r4, r5, [sp, #80]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #72]
+	ldr	r5, [sp, #76]
+#else
+	ldrd	r4, r5, [sp, #72]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #72]
+	str	r5, [sp, #76]
+#else
+	strd	r4, r5, [sp, #72]
+#endif
+	# Round 10
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
 #else
-	strd  r12, lr, [r0]
+	ldrd	r6, r7, [r0, #24]
 #endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
 #else
-	ldrd  r4, r5, [r0]
+	ldrd	r8, r9, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #80]
+	ldr	r9, [sp, #84]
+#else
+	ldrd	r8, r9, [sp, #80]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #80]
+	ldr	r7, [r3, #84]
+#else
+	ldrd	r6, r7, [r3, #80]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #8]
+	str	r9, [r0, #12]
+#else
+	strd	r8, r9, [r0, #8]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #40]
+	str	r7, [r0, #44]
+#else
+	strd	r6, r7, [r0, #40]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[10]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #64]
+	ldr	r5, [sp, #68]
+#else
+	ldrd	r4, r5, [sp, #64]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #80]
+	ldr	r5, [sp, #84]
+#else
+	ldrd	r4, r5, [sp, #80]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #24]
+	ldr	r9, [sp, #28]
+#else
+	ldrd	r8, r9, [sp, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #80]
+	str	r5, [sp, #84]
+#else
+	strd	r4, r5, [sp, #80]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #88]
+	ldr	r5, [sp, #92]
+#else
+	ldrd	r4, r5, [sp, #88]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #80]
+	ldr	r5, [sp, #84]
+#else
+	ldrd	r4, r5, [sp, #80]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #80]
+	str	r5, [sp, #84]
+#else
+	strd	r4, r5, [sp, #80]
+#endif
+	# Round 11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #88]
+	ldr	r9, [sp, #92]
+#else
+	ldrd	r8, r9, [sp, #88]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #88]
+	ldr	r7, [r3, #92]
+#else
+	ldrd	r6, r7, [r3, #88]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0]
+	str	r9, [r0, #4]
+#else
+	strd	r8, r9, [r0]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #32]
+	str	r7, [r0, #36]
+#else
+	strd	r6, r7, [r0, #32]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[11]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #72]
+	ldr	r5, [sp, #76]
+#else
+	ldrd	r4, r5, [sp, #72]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #88]
+	ldr	r5, [sp, #92]
+#else
+	ldrd	r4, r5, [sp, #88]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #32]
+	ldr	r9, [sp, #36]
+#else
+	ldrd	r8, r9, [sp, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #88]
+	str	r5, [sp, #92]
+#else
+	strd	r4, r5, [sp, #88]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #96]
+	ldr	r5, [sp, #100]
+#else
+	ldrd	r4, r5, [sp, #96]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #88]
+	ldr	r5, [sp, #92]
+#else
+	ldrd	r4, r5, [sp, #88]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #88]
+	str	r5, [sp, #92]
+#else
+	strd	r4, r5, [sp, #88]
+#endif
+	# Round 12
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #96]
+	ldr	r9, [sp, #100]
+#else
+	ldrd	r8, r9, [sp, #96]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #96]
+	ldr	r7, [r3, #100]
+#else
+	ldrd	r6, r7, [r3, #96]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #56]
+	str	r9, [r0, #60]
+#else
+	strd	r8, r9, [r0, #56]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #24]
+	str	r7, [r0, #28]
+#else
+	strd	r6, r7, [r0, #24]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[12]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #80]
+	ldr	r5, [sp, #84]
+#else
+	ldrd	r4, r5, [sp, #80]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #96]
+	ldr	r5, [sp, #100]
+#else
+	ldrd	r4, r5, [sp, #96]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #40]
+	ldr	r9, [sp, #44]
+#else
+	ldrd	r8, r9, [sp, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #96]
+	str	r5, [sp, #100]
+#else
+	strd	r4, r5, [sp, #96]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #104]
+	ldr	r5, [sp, #108]
+#else
+	ldrd	r4, r5, [sp, #104]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #96]
+	ldr	r5, [sp, #100]
+#else
+	ldrd	r4, r5, [sp, #96]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #96]
+	str	r5, [sp, #100]
+#else
+	strd	r4, r5, [sp, #96]
+#endif
+	# Round 13
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #104]
+	ldr	r9, [sp, #108]
+#else
+	ldrd	r8, r9, [sp, #104]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #104]
+	ldr	r7, [r3, #108]
+#else
+	ldrd	r6, r7, [r3, #104]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #48]
+	str	r9, [r0, #52]
+#else
+	strd	r8, r9, [r0, #48]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #16]
+	str	r7, [r0, #20]
+#else
+	strd	r6, r7, [r0, #16]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[13]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #88]
+	ldr	r5, [sp, #92]
+#else
+	ldrd	r4, r5, [sp, #88]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #104]
+	ldr	r5, [sp, #108]
+#else
+	ldrd	r4, r5, [sp, #104]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #48]
+	ldr	r9, [sp, #52]
+#else
+	ldrd	r8, r9, [sp, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #104]
+	str	r5, [sp, #108]
+#else
+	strd	r4, r5, [sp, #104]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #112]
+	ldr	r5, [sp, #116]
+#else
+	ldrd	r4, r5, [sp, #112]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #104]
+	ldr	r5, [sp, #108]
+#else
+	ldrd	r4, r5, [sp, #104]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #104]
+	str	r5, [sp, #108]
+#else
+	strd	r4, r5, [sp, #104]
+#endif
+	# Round 14
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #112]
+	ldr	r9, [sp, #116]
+#else
+	ldrd	r8, r9, [sp, #112]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #112]
+	ldr	r7, [r3, #116]
+#else
+	ldrd	r6, r7, [r3, #112]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #40]
+	str	r9, [r0, #44]
+#else
+	strd	r8, r9, [r0, #40]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
+#else
+	strd	r6, r7, [r0, #8]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Calc new W[14]
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #96]
+	ldr	r5, [sp, #100]
+#else
+	ldrd	r4, r5, [sp, #96]
+#endif
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #112]
+	ldr	r5, [sp, #116]
+#else
+	ldrd	r4, r5, [sp, #112]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #56]
+	ldr	r9, [sp, #60]
+#else
+	ldrd	r8, r9, [sp, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #112]
+	str	r5, [sp, #116]
+#else
+	strd	r4, r5, [sp, #112]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #120]
+	ldr	r5, [sp, #124]
+#else
+	ldrd	r4, r5, [sp, #120]
+#endif
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [sp, #112]
+	ldr	r5, [sp, #116]
+#else
+	ldrd	r4, r5, [sp, #112]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [sp, #112]
+	str	r5, [sp, #116]
+#else
+	strd	r4, r5, [sp, #112]
+#endif
+	# Round 15
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0]
 	str	r5, [r0, #4]
 #else
-	strd  r4, r5, [r0]
+	strd	r4, r5, [r0]
 #endif
-	mov	r8, r6
-	mov	r9, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #120]
+	ldr	r9, [sp, #124]
+#else
+	ldrd	r8, r9, [sp, #120]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #120]
+	ldr	r7, [r3, #124]
+#else
+	ldrd	r6, r7, [r3, #120]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #32]
+	str	r9, [r0, #36]
+#else
+	strd	r8, r9, [r0, #32]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0]
+	str	r7, [r0, #4]
+#else
+	strd	r6, r7, [r0]
+#endif
+	mov	r10, r8
+	mov	r11, r9
 	# Calc new W[15]
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #104]
-	ldr	lr, [sp, #108]
+	ldr	r4, [sp, #104]
+	ldr	r5, [sp, #108]
 #else
-	ldrd  r12, lr, [sp, #104]
+	ldrd	r4, r5, [sp, #104]
 #endif
-	lsrs	r4, r12, #19
-	lsrs	r5, lr, #19
-	orr	r5, r5, r12, lsl #13
-	orr	r4, r4, lr, lsl #13
-	lsls	r6, r12, #3
-	lsls	r7, lr, #3
-	orr	r7, r7, r12, lsr #29
-	orr	r6, r6, lr, lsr #29
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #6
-	lsrs	r7, lr, #6
-	orr	r6, r6, lr, lsl #26
-	eor	r5, r5, r7
-	eor	r4, r4, r6
+	lsrs	r6, r4, #19
+	lsrs	r7, r5, #19
+	orr	r7, r7, r4, lsl #13
+	orr	r6, r6, r5, lsl #13
+	lsls	r8, r4, #3
+	lsls	r9, r5, #3
+	orr	r9, r9, r4, lsr #29
+	orr	r8, r8, r5, lsr #29
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #6
+	lsrs	r9, r5, #6
+	orr	r8, r8, r5, lsl #26
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #120]
-	ldr	lr, [sp, #124]
+	ldr	r4, [sp, #120]
+	ldr	r5, [sp, #124]
 #else
-	ldrd  r12, lr, [sp, #120]
+	ldrd	r4, r5, [sp, #120]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #64]
-	ldr	r7, [sp, #68]
+	ldr	r8, [sp, #64]
+	ldr	r9, [sp, #68]
 #else
-	ldrd  r6, r7, [sp, #64]
+	ldrd	r8, r9, [sp, #64]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-	adds	r12, r12, r6
-	adc	lr, lr, r7
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+	adds	r4, r4, r8
+	adc	r5, r5, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #120]
-	str	lr, [sp, #124]
+	str	r4, [sp, #120]
+	str	r5, [sp, #124]
 #else
-	strd  r12, lr, [sp, #120]
+	strd	r4, r5, [sp, #120]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp]
-	ldr	lr, [sp, #4]
+	ldr	r4, [sp]
+	ldr	r5, [sp, #4]
 #else
-	ldrd  r12, lr, [sp]
+	ldrd	r4, r5, [sp]
 #endif
-	lsrs	r4, r12, #1
-	lsrs	r5, lr, #1
-	orr	r5, r5, r12, lsl #31
-	orr	r4, r4, lr, lsl #31
-	lsrs	r6, r12, #8
-	lsrs	r7, lr, #8
-	orr	r7, r7, r12, lsl #24
-	orr	r6, r6, lr, lsl #24
-	eor	r5, r5, r7
-	eor	r4, r4, r6
-	lsrs	r6, r12, #7
-	lsrs	r7, lr, #7
-	orr	r6, r6, lr, lsl #25
-	eor	r5, r5, r7
-	eor	r4, r4, r6
+	lsrs	r6, r4, #1
+	lsrs	r7, r5, #1
+	orr	r7, r7, r4, lsl #31
+	orr	r6, r6, r5, lsl #31
+	lsrs	r8, r4, #8
+	lsrs	r9, r5, #8
+	orr	r9, r9, r4, lsl #24
+	orr	r8, r8, r5, lsl #24
+	eor	r7, r7, r9
+	eor	r6, r6, r8
+	lsrs	r8, r4, #7
+	lsrs	r9, r5, #7
+	orr	r8, r8, r5, lsl #25
+	eor	r7, r7, r9
+	eor	r6, r6, r8
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [sp, #120]
-	ldr	lr, [sp, #124]
+	ldr	r4, [sp, #120]
+	ldr	r5, [sp, #124]
 #else
-	ldrd  r12, lr, [sp, #120]
+	ldrd	r4, r5, [sp, #120]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #120]
-	str	lr, [sp, #124]
+	str	r4, [sp, #120]
+	str	r5, [sp, #124]
 #else
-	strd  r12, lr, [sp, #120]
+	strd	r4, r5, [sp, #120]
 #endif
 	add	r3, r3, #0x80
-	subs	r10, r10, #1
+	subs	r12, r12, #1
 	bne	L_SHA512_transform_len_start
 	# Round 0
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
 #else
-	ldrd  r12, lr, [r0, #32]
+	ldrd	r4, r5, [r0, #32]
 #endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp]
-	ldr	r7, [sp, #4]
-#else
-	ldrd  r6, r7, [sp]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3]
-	ldr	r5, [r3, #4]
-#else
-	ldrd  r4, r5, [r3]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #24]
-	str	r7, [r0, #28]
-#else
-	strd  r6, r7, [r0, #24]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #56]
 	ldr	r5, [r0, #60]
 #else
-	ldrd  r4, r5, [r0, #56]
+	ldrd	r4, r5, [r0, #56]
 #endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #56]
 	str	r5, [r0, #60]
 #else
-	strd  r4, r5, [r0, #56]
+	strd	r4, r5, [r0, #56]
 #endif
-	mov	r8, r6
-	mov	r9, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp]
+	ldr	r9, [sp, #4]
+#else
+	ldrd	r8, r9, [sp]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3]
+	ldr	r7, [r3, #4]
+#else
+	ldrd	r6, r7, [r3]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #24]
+	str	r9, [r0, #28]
+#else
+	strd	r8, r9, [r0, #24]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #56]
+	str	r7, [r0, #60]
+#else
+	strd	r6, r7, [r0, #56]
+#endif
+	mov	r10, r8
+	mov	r11, r9
 	# Round 1
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
 #else
-	ldrd  r12, lr, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #8]
-	ldr	r7, [sp, #12]
-#else
-	ldrd  r6, r7, [sp, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #8]
-	ldr	r5, [r3, #12]
-#else
-	ldrd  r4, r5, [r3, #8]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #16]
-	str	r7, [r0, #20]
-#else
-	strd  r6, r7, [r0, #16]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #48]
 	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r0, #48]
+	ldrd	r4, r5, [r0, #48]
 #endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #48]
 	str	r5, [r0, #52]
 #else
-	strd  r4, r5, [r0, #48]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 2
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
+	strd	r4, r5, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #24]
 	ldr	r5, [r0, #28]
 #else
-	ldrd  r4, r5, [r0, #24]
+	ldrd	r4, r5, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #32]
 	ldr	r7, [r0, #36]
 #else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
+	ldrd	r6, r7, [r0, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #16]
-	ldr	r7, [sp, #20]
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
 #else
-	ldrd  r6, r7, [sp, #16]
+	ldrd	r8, r9, [r0, #40]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #16]
-	ldr	r5, [r3, #20]
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r3, #16]
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #8]
+	ldr	r9, [sp, #12]
+#else
+	ldrd	r8, r9, [sp, #8]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #8]
+	ldr	r7, [r3, #12]
+#else
+	ldrd	r6, r7, [r3, #8]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #16]
+	str	r9, [r0, #20]
+#else
+	strd	r8, r9, [r0, #16]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #48]
+	str	r7, [r0, #52]
+#else
+	strd	r6, r7, [r0, #48]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 2
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #16]
+	ldr	r9, [sp, #20]
+#else
+	ldrd	r8, r9, [sp, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #16]
+	ldr	r7, [r3, #20]
+#else
+	ldrd	r6, r7, [r3, #16]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #8]
+	str	r9, [r0, #12]
+#else
+	strd	r8, r9, [r0, #8]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #40]
+	str	r7, [r0, #44]
+#else
+	strd	r6, r7, [r0, #40]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 3
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #24]
+	ldr	r9, [sp, #28]
+#else
+	ldrd	r8, r9, [sp, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #24]
+	ldr	r7, [r3, #28]
+#else
+	ldrd	r6, r7, [r3, #24]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0]
+	str	r9, [r0, #4]
+#else
+	strd	r8, r9, [r0]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #32]
+	str	r7, [r0, #36]
+#else
+	strd	r6, r7, [r0, #32]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 4
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
 #endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #8]
 	ldr	r7, [r0, #12]
 #else
-	ldrd  r6, r7, [r0, #8]
+	ldrd	r6, r7, [r0, #8]
 #endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
 #else
-	strd  r12, lr, [r0, #40]
+	ldrd	r8, r9, [r0, #16]
 #endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
 #else
-	ldrd  r12, lr, [r0, #48]
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #32]
+	ldr	r9, [sp, #36]
+#else
+	ldrd	r8, r9, [sp, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #32]
+	ldr	r7, [r3, #36]
+#else
+	ldrd	r6, r7, [r3, #32]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #56]
+	str	r9, [r0, #60]
+#else
+	strd	r8, r9, [r0, #56]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #24]
+	str	r7, [r0, #28]
+#else
+	strd	r6, r7, [r0, #24]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #40]
+	ldr	r9, [sp, #44]
+#else
+	ldrd	r8, r9, [sp, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #40]
+	ldr	r7, [r3, #44]
+#else
+	ldrd	r6, r7, [r3, #40]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #48]
+	str	r9, [r0, #52]
+#else
+	strd	r8, r9, [r0, #48]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #16]
+	str	r7, [r0, #20]
+#else
+	strd	r6, r7, [r0, #16]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 6
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #48]
+	ldr	r9, [sp, #52]
+#else
+	ldrd	r8, r9, [sp, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #48]
+	ldr	r7, [r3, #52]
+#else
+	ldrd	r6, r7, [r3, #48]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #40]
+	str	r9, [r0, #44]
+#else
+	strd	r8, r9, [r0, #40]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
+#else
+	strd	r6, r7, [r0, #8]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #56]
+	ldr	r9, [sp, #60]
+#else
+	ldrd	r8, r9, [sp, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #56]
+	ldr	r7, [r3, #60]
+#else
+	ldrd	r6, r7, [r3, #56]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #32]
+	str	r9, [r0, #36]
+#else
+	strd	r8, r9, [r0, #32]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0]
+	str	r7, [r0, #4]
+#else
+	strd	r6, r7, [r0]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 8
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #64]
+	ldr	r9, [sp, #68]
+#else
+	ldrd	r8, r9, [sp, #64]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #64]
+	ldr	r7, [r3, #68]
+#else
+	ldrd	r6, r7, [r3, #64]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #24]
+	str	r9, [r0, #28]
+#else
+	strd	r8, r9, [r0, #24]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #56]
+	str	r5, [r0, #60]
+#else
+	strd	r4, r5, [r0, #56]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #56]
+	str	r7, [r0, #60]
+#else
+	strd	r6, r7, [r0, #56]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #72]
+	ldr	r9, [sp, #76]
+#else
+	ldrd	r8, r9, [sp, #72]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #72]
+	ldr	r7, [r3, #76]
+#else
+	ldrd	r6, r7, [r3, #72]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #16]
+	str	r9, [r0, #20]
+#else
+	strd	r8, r9, [r0, #16]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
+#else
+	strd	r4, r5, [r0, #48]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #48]
+	str	r7, [r0, #52]
+#else
+	strd	r6, r7, [r0, #48]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 10
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #80]
+	ldr	r9, [sp, #84]
+#else
+	ldrd	r8, r9, [sp, #80]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #80]
+	ldr	r7, [r3, #84]
+#else
+	ldrd	r6, r7, [r3, #80]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #8]
+	str	r9, [r0, #12]
+#else
+	strd	r8, r9, [r0, #8]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #40]
+	str	r5, [r0, #44]
+#else
+	strd	r4, r5, [r0, #40]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #40]
+	str	r7, [r0, #44]
+#else
+	strd	r6, r7, [r0, #40]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #88]
+	ldr	r9, [sp, #92]
+#else
+	ldrd	r8, r9, [sp, #88]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #88]
+	ldr	r7, [r3, #92]
+#else
+	ldrd	r6, r7, [r3, #88]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0]
+	str	r9, [r0, #4]
+#else
+	strd	r8, r9, [r0]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #32]
+	str	r5, [r0, #36]
+#else
+	strd	r4, r5, [r0, #32]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #32]
+	str	r7, [r0, #36]
+#else
+	strd	r6, r7, [r0, #32]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 12
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #96]
+	ldr	r9, [sp, #100]
+#else
+	ldrd	r8, r9, [sp, #96]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #96]
+	ldr	r7, [r3, #100]
+#else
+	ldrd	r6, r7, [r3, #96]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #32]
+	ldr	r5, [r0, #36]
+#else
+	ldrd	r4, r5, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #56]
+	str	r9, [r0, #60]
+#else
+	strd	r8, r9, [r0, #56]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #40]
+	ldr	r7, [r0, #44]
+#else
+	ldrd	r6, r7, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #24]
+	str	r5, [r0, #28]
+#else
+	strd	r4, r5, [r0, #24]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #24]
+	str	r7, [r0, #28]
+#else
+	strd	r6, r7, [r0, #24]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 13
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #56]
+	ldr	r5, [r0, #60]
+#else
+	ldrd	r4, r5, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #104]
+	ldr	r9, [sp, #108]
+#else
+	ldrd	r8, r9, [sp, #104]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #104]
+	ldr	r7, [r3, #108]
+#else
+	ldrd	r6, r7, [r3, #104]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #48]
+	ldr	r9, [r0, #52]
+#else
+	ldrd	r8, r9, [r0, #48]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #24]
+	ldr	r5, [r0, #28]
+#else
+	ldrd	r4, r5, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #48]
+	str	r9, [r0, #52]
+#else
+	strd	r8, r9, [r0, #48]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #24]
+	ldr	r9, [r0, #28]
+#else
+	ldrd	r8, r9, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #32]
+	ldr	r7, [r0, #36]
+#else
+	ldrd	r6, r7, [r0, #32]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #16]
+	str	r5, [r0, #20]
+#else
+	strd	r4, r5, [r0, #16]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #16]
+	str	r7, [r0, #20]
+#else
+	strd	r6, r7, [r0, #16]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 14
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #48]
+	ldr	r5, [r0, #52]
+#else
+	ldrd	r4, r5, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #56]
+	ldr	r7, [r0, #60]
+#else
+	ldrd	r6, r7, [r0, #56]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0]
+	ldr	r9, [r0, #4]
+#else
+	ldrd	r8, r9, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #112]
+	ldr	r9, [sp, #116]
+#else
+	ldrd	r8, r9, [sp, #112]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #112]
+	ldr	r7, [r3, #116]
+#else
+	ldrd	r6, r7, [r3, #112]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #40]
+	ldr	r9, [r0, #44]
+#else
+	ldrd	r8, r9, [r0, #40]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #16]
+	ldr	r5, [r0, #20]
+#else
+	ldrd	r4, r5, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #40]
+	str	r9, [r0, #44]
+#else
+	strd	r8, r9, [r0, #40]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #16]
+	ldr	r9, [r0, #20]
+#else
+	ldrd	r8, r9, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #24]
+	ldr	r7, [r0, #28]
+#else
+	ldrd	r6, r7, [r0, #24]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0, #8]
+	str	r5, [r0, #12]
+#else
+	strd	r4, r5, [r0, #8]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0, #8]
+	str	r7, [r0, #12]
+#else
+	strd	r6, r7, [r0, #8]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Round 15
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+	lsrs	r6, r4, #14
+	lsrs	r7, r5, #14
+	orr	r7, r7, r4, lsl #18
+	orr	r6, r6, r5, lsl #18
+	lsrs	r8, r4, #18
+	lsrs	r9, r5, #18
+	orr	r9, r9, r4, lsl #14
+	orr	r8, r8, r5, lsl #14
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #23
+	lsls	r9, r5, #23
+	orr	r9, r9, r4, lsr #9
+	orr	r8, r8, r5, lsr #9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #40]
+	ldr	r5, [r0, #44]
+#else
+	ldrd	r4, r5, [r0, #40]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #48]
+	ldr	r7, [r0, #52]
+#else
+	ldrd	r6, r7, [r0, #48]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #56]
+	ldr	r9, [r0, #60]
+#else
+	ldrd	r8, r9, [r0, #56]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	and	r6, r6, r4
+	and	r7, r7, r5
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #120]
+	ldr	r9, [sp, #124]
+#else
+	ldrd	r8, r9, [sp, #120]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r3, #120]
+	ldr	r7, [r3, #124]
+#else
+	ldrd	r6, r7, [r3, #120]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #32]
+	ldr	r9, [r0, #36]
+#else
+	ldrd	r8, r9, [r0, #32]
+#endif
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	adds	r8, r8, r4
+	adc	r9, r9, r5
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0, #8]
+	ldr	r5, [r0, #12]
+#else
+	ldrd	r4, r5, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r8, [r0, #32]
+	str	r9, [r0, #36]
+#else
+	strd	r8, r9, [r0, #32]
+#endif
+	lsrs	r6, r4, #28
+	lsrs	r7, r5, #28
+	orr	r7, r7, r4, lsl #4
+	orr	r6, r6, r5, lsl #4
+	lsls	r8, r4, #30
+	lsls	r9, r5, #30
+	orr	r9, r9, r4, lsr #2
+	orr	r8, r8, r5, lsr #2
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	lsls	r8, r4, #25
+	lsls	r9, r5, #25
+	orr	r9, r9, r4, lsr #7
+	orr	r8, r8, r5, lsr #7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+	eor	r6, r6, r8
+	eor	r7, r7, r9
+	adds	r4, r4, r6
+	adc	r5, r5, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [r0, #8]
+	ldr	r9, [r0, #12]
+#else
+	ldrd	r8, r9, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #16]
+	ldr	r7, [r0, #20]
+#else
+	ldrd	r6, r7, [r0, #16]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
+#endif
+	eor	r8, r8, r6
+	eor	r9, r9, r7
+	and	r10, r10, r8
+	and	r11, r11, r9
+	eor	r10, r10, r6
+	eor	r11, r11, r7
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0]
+	ldr	r7, [r0, #4]
+#else
+	ldrd	r6, r7, [r0]
+#endif
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r6, [r0]
+	str	r7, [r0, #4]
+#else
+	strd	r6, r7, [r0]
+#endif
+	mov	r10, r8
+	mov	r11, r9
+	# Add in digest from start
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r4, [r0]
+	ldr	r5, [r0, #4]
+#else
+	ldrd	r4, r5, [r0]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r6, [r0, #8]
+	ldr	r7, [r0, #12]
+#else
+	ldrd	r6, r7, [r0, #8]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r8, [sp, #128]
+	ldr	r9, [sp, #132]
+#else
+	ldrd	r8, r9, [sp, #128]
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	ldr	r10, [sp, #136]
+	ldr	r11, [sp, #140]
+#else
+	ldrd	r10, r11, [sp, #136]
+#endif
+	adds	r4, r4, r8
+	adc	r5, r5, r9
+	adds	r6, r6, r10
+	adc	r7, r7, r11
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+	str	r4, [r0]
+	str	r5, [r0, #4]
+#else
+	strd	r4, r5, [r0]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #8]
 	str	r7, [r0, #12]
 #else
-	strd  r6, r7, [r0, #8]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
+	strd	r6, r7, [r0, #8]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
+	str	r4, [sp, #128]
+	str	r5, [sp, #132]
 #else
-	ldrd  r4, r5, [r0, #56]
+	strd	r4, r5, [sp, #128]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
+	str	r6, [sp, #136]
+	str	r7, [sp, #140]
 #else
-	strd  r12, lr, [r0, #40]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #40]
-	str	r5, [r0, #44]
-#else
-	strd  r4, r5, [r0, #40]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 3
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
+	strd	r6, r7, [sp, #136]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #16]
 	ldr	r5, [r0, #20]
 #else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #24]
 	ldr	r7, [r0, #28]
 #else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
+	ldrd	r6, r7, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #24]
-	ldr	r7, [sp, #28]
+	ldr	r8, [sp, #144]
+	ldr	r9, [sp, #148]
 #else
-	ldrd  r6, r7, [sp, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #24]
-	ldr	r5, [r3, #28]
-#else
-	ldrd  r4, r5, [r3, #24]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
+	ldrd	r8, r9, [sp, #144]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0]
-	str	r7, [r0, #4]
+	ldr	r10, [sp, #152]
+	ldr	r11, [sp, #156]
 #else
-	strd  r6, r7, [r0]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #48]
-	ldr	r5, [r0, #52]
-#else
-	ldrd  r4, r5, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #32]
-	str	r5, [r0, #36]
-#else
-	strd  r4, r5, [r0, #32]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 4
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #32]
-	ldr	r7, [sp, #36]
-#else
-	ldrd  r6, r7, [sp, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #32]
-	ldr	r5, [r3, #36]
-#else
-	ldrd  r4, r5, [r3, #32]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #56]
-	str	r7, [r0, #60]
-#else
-	strd  r6, r7, [r0, #56]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #24]
-	str	r5, [r0, #28]
-#else
-	strd  r4, r5, [r0, #24]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #40]
-	ldr	r7, [sp, #44]
-#else
-	ldrd  r6, r7, [sp, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #40]
-	ldr	r5, [r3, #44]
-#else
-	ldrd  r4, r5, [r3, #40]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #48]
-	str	r7, [r0, #52]
-#else
-	strd  r6, r7, [r0, #48]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
+	ldrd	r10, r11, [sp, #152]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
+	adds	r6, r6, r10
+	adc	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #16]
 	str	r5, [r0, #20]
 #else
-	strd  r4, r5, [r0, #16]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 6
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #48]
-	ldr	r7, [sp, #52]
-#else
-	ldrd  r6, r7, [sp, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #48]
-	ldr	r5, [r3, #52]
-#else
-	ldrd  r4, r5, [r3, #48]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #40]
-	str	r7, [r0, #44]
-#else
-	strd  r6, r7, [r0, #40]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #8]
-	str	r5, [r0, #12]
-#else
-	strd  r4, r5, [r0, #8]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #48]
-	ldr	r5, [r0, #52]
-#else
-	ldrd  r4, r5, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #56]
-	ldr	r7, [sp, #60]
-#else
-	ldrd  r6, r7, [sp, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #56]
-	ldr	r5, [r3, #60]
-#else
-	ldrd  r4, r5, [r3, #56]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #32]
-	str	r7, [r0, #36]
-#else
-	strd  r6, r7, [r0, #32]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0]
-	str	r5, [r0, #4]
-#else
-	strd  r4, r5, [r0]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 8
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #64]
-	ldr	r7, [sp, #68]
-#else
-	ldrd  r6, r7, [sp, #64]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #64]
-	ldr	r5, [r3, #68]
-#else
-	ldrd  r4, r5, [r3, #64]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
-#else
-	strd  r12, lr, [r0, #56]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
+	strd	r4, r5, [r0, #16]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #24]
 	str	r7, [r0, #28]
 #else
-	strd  r6, r7, [r0, #24]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
+	strd	r6, r7, [r0, #24]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	str	r4, [sp, #144]
+	str	r5, [sp, #148]
 #else
-	ldrd  r4, r5, [r0, #8]
+	strd	r4, r5, [sp, #144]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #56]
-	str	lr, [r0, #60]
+	str	r6, [sp, #152]
+	str	r7, [sp, #156]
 #else
-	strd  r12, lr, [r0, #56]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #56]
-	str	r5, [r0, #60]
-#else
-	strd  r4, r5, [r0, #56]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
+	strd	r6, r7, [sp, #152]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #32]
 	ldr	r5, [r0, #36]
 #else
-	ldrd  r4, r5, [r0, #32]
+	ldrd	r4, r5, [r0, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #40]
 	ldr	r7, [r0, #44]
 #else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
+	ldrd	r6, r7, [r0, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #72]
-	ldr	r7, [sp, #76]
+	ldr	r8, [sp, #160]
+	ldr	r9, [sp, #164]
 #else
-	ldrd  r6, r7, [sp, #72]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #72]
-	ldr	r5, [r3, #76]
-#else
-	ldrd  r4, r5, [r3, #72]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
+	ldrd	r8, r9, [sp, #160]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #16]
-	str	r7, [r0, #20]
+	ldr	r10, [sp, #168]
+	ldr	r11, [sp, #172]
 #else
-	strd  r6, r7, [r0, #16]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #48]
-	ldr	r5, [r0, #52]
-#else
-	ldrd  r4, r5, [r0, #48]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #48]
-	str	r5, [r0, #52]
-#else
-	strd  r4, r5, [r0, #48]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 10
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #80]
-	ldr	r7, [sp, #84]
-#else
-	ldrd  r6, r7, [sp, #80]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #80]
-	ldr	r5, [r3, #84]
-#else
-	ldrd  r4, r5, [r3, #80]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #8]
-	str	r7, [r0, #12]
-#else
-	strd  r6, r7, [r0, #8]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #40]
-	str	lr, [r0, #44]
-#else
-	strd  r12, lr, [r0, #40]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #40]
-	str	r5, [r0, #44]
-#else
-	strd  r4, r5, [r0, #40]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 11
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #88]
-	ldr	r7, [sp, #92]
-#else
-	ldrd  r6, r7, [sp, #88]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #88]
-	ldr	r5, [r3, #92]
-#else
-	ldrd  r4, r5, [r3, #88]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0]
-	str	r7, [r0, #4]
-#else
-	strd  r6, r7, [r0]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #48]
-	ldr	r5, [r0, #52]
-#else
-	ldrd  r4, r5, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
+	ldrd	r10, r11, [sp, #168]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
+	adds	r6, r6, r10
+	adc	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r4, [r0, #32]
 	str	r5, [r0, #36]
 #else
-	strd  r4, r5, [r0, #32]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 12
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #96]
-	ldr	r7, [sp, #100]
-#else
-	ldrd  r6, r7, [sp, #96]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #96]
-	ldr	r5, [r3, #100]
-#else
-	ldrd  r4, r5, [r3, #96]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #56]
-	ldr	r7, [r0, #60]
-#else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #56]
-	str	r7, [r0, #60]
-#else
-	strd  r6, r7, [r0, #56]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #24]
-	str	lr, [r0, #28]
-#else
-	strd  r12, lr, [r0, #24]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #24]
-	str	r5, [r0, #28]
-#else
-	strd  r4, r5, [r0, #24]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 13
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #56]
-	ldr	lr, [r0, #60]
-#else
-	ldrd  r12, lr, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #104]
-	ldr	r7, [sp, #108]
-#else
-	ldrd  r6, r7, [sp, #104]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #104]
-	ldr	r5, [r3, #108]
-#else
-	ldrd  r4, r5, [r3, #104]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #48]
-	ldr	r7, [r0, #52]
-#else
-	ldrd  r6, r7, [r0, #48]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #24]
-	ldr	lr, [r0, #28]
-#else
-	ldrd  r12, lr, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #48]
-	str	r7, [r0, #52]
-#else
-	strd  r6, r7, [r0, #48]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #24]
-	ldr	r7, [r0, #28]
-#else
-	ldrd  r6, r7, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #32]
-	ldr	r5, [r0, #36]
-#else
-	ldrd  r4, r5, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #16]
-	str	r5, [r0, #20]
-#else
-	strd  r4, r5, [r0, #16]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 14
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0]
-	ldr	r7, [r0, #4]
-#else
-	ldrd  r6, r7, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #112]
-	ldr	r7, [sp, #116]
-#else
-	ldrd  r6, r7, [sp, #112]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #112]
-	ldr	r5, [r3, #116]
-#else
-	ldrd  r4, r5, [r3, #112]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #40]
-	ldr	r7, [r0, #44]
-#else
-	ldrd  r6, r7, [r0, #40]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
-#else
-	strd  r12, lr, [r0, #8]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
+	strd	r4, r5, [r0, #32]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	str	r6, [r0, #40]
 	str	r7, [r0, #44]
 #else
-	strd  r6, r7, [r0, #40]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #16]
-	ldr	r7, [r0, #20]
-#else
-	ldrd  r6, r7, [r0, #16]
+	strd	r6, r7, [r0, #40]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
+	str	r4, [sp, #160]
+	str	r5, [sp, #164]
 #else
-	ldrd  r4, r5, [r0, #24]
+	strd	r4, r5, [sp, #160]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #8]
-	str	lr, [r0, #12]
+	str	r6, [sp, #168]
+	str	r7, [sp, #172]
 #else
-	strd  r12, lr, [r0, #8]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
-#else
-	ldrd  r4, r5, [r0, #8]
-#endif
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #8]
-	str	r5, [r0, #12]
-#else
-	strd  r4, r5, [r0, #8]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Round 15
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
-#endif
-	lsrs	r4, r12, #14
-	lsrs	r5, lr, #14
-	orr	r5, r5, r12, lsl #18
-	orr	r4, r4, lr, lsl #18
-	lsrs	r6, r12, #18
-	lsrs	r7, lr, #18
-	orr	r7, r7, r12, lsl #14
-	orr	r6, r6, lr, lsl #14
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #23
-	lsls	r7, lr, #23
-	orr	r7, r7, r12, lsr #9
-	orr	r6, r6, lr, lsr #9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #40]
-	ldr	lr, [r0, #44]
-#else
-	ldrd  r12, lr, [r0, #40]
+	strd	r6, r7, [sp, #168]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r4, [r0, #48]
 	ldr	r5, [r0, #52]
 #else
-	ldrd  r4, r5, [r0, #48]
+	ldrd	r4, r5, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
 	ldr	r6, [r0, #56]
 	ldr	r7, [r0, #60]
 #else
-	ldrd  r6, r7, [r0, #56]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	and	r4, r4, r12
-	and	r5, r5, lr
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
+	ldrd	r6, r7, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #120]
-	ldr	r7, [sp, #124]
+	ldr	r8, [sp, #176]
+	ldr	r9, [sp, #180]
 #else
-	ldrd  r6, r7, [sp, #120]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r3, #120]
-	ldr	r5, [r3, #124]
-#else
-	ldrd  r4, r5, [r3, #120]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #32]
-	ldr	r7, [r0, #36]
-#else
-	ldrd  r6, r7, [r0, #32]
-#endif
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-	adds	r6, r6, r12
-	adc	r7, r7, lr
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #8]
-	ldr	lr, [r0, #12]
-#else
-	ldrd  r12, lr, [r0, #8]
+	ldrd	r8, r9, [sp, #176]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r6, [r0, #32]
-	str	r7, [r0, #36]
+	ldr	r10, [sp, #184]
+	ldr	r11, [sp, #188]
 #else
-	strd  r6, r7, [r0, #32]
-#endif
-	lsrs	r4, r12, #28
-	lsrs	r5, lr, #28
-	orr	r5, r5, r12, lsl #4
-	orr	r4, r4, lr, lsl #4
-	lsls	r6, r12, #30
-	lsls	r7, lr, #30
-	orr	r7, r7, r12, lsr #2
-	orr	r6, r6, lr, lsr #2
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	lsls	r6, r12, #25
-	lsls	r7, lr, #25
-	orr	r7, r7, r12, lsr #7
-	orr	r6, r6, lr, lsr #7
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
-#endif
-	eor	r4, r4, r6
-	eor	r5, r5, r7
-	adds	r12, r12, r4
-	adc	lr, lr, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [r0, #8]
-	ldr	r7, [r0, #12]
-#else
-	ldrd  r6, r7, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #16]
-	ldr	r5, [r0, #20]
-#else
-	ldrd  r4, r5, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-	eor	r6, r6, r4
-	eor	r7, r7, r5
-	and	r8, r8, r6
-	and	r9, r9, r7
-	eor	r8, r8, r4
-	eor	r9, r9, r5
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0]
-	ldr	r5, [r0, #4]
-#else
-	ldrd  r4, r5, [r0]
+	ldrd	r10, r11, [sp, #184]
 #endif
 	adds	r4, r4, r8
 	adc	r5, r5, r9
+	adds	r6, r6, r10
+	adc	r7, r7, r11
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0]
-	str	r5, [r0, #4]
+	str	r4, [r0, #48]
+	str	r5, [r0, #52]
 #else
-	strd  r4, r5, [r0]
-#endif
-	mov	r8, r6
-	mov	r9, r7
-	# Add in digest from start
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0]
-	ldr	lr, [r0, #4]
-#else
-	ldrd  r12, lr, [r0]
+	strd	r4, r5, [r0, #48]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #8]
-	ldr	r5, [r0, #12]
+	str	r6, [r0, #56]
+	str	r7, [r0, #60]
 #else
-	ldrd  r4, r5, [r0, #8]
+	strd	r6, r7, [r0, #56]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #128]
-	ldr	r7, [sp, #132]
+	str	r4, [sp, #176]
+	str	r5, [sp, #180]
 #else
-	ldrd  r6, r7, [sp, #128]
+	strd	r4, r5, [sp, #176]
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [sp, #136]
-	ldr	r9, [sp, #140]
+	str	r6, [sp, #184]
+	str	r7, [sp, #188]
 #else
-	ldrd  r8, r9, [sp, #136]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0]
-	str	lr, [r0, #4]
-#else
-	strd  r12, lr, [r0]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #8]
-	str	r5, [r0, #12]
-#else
-	strd  r4, r5, [r0, #8]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #128]
-	str	lr, [sp, #132]
-#else
-	strd  r12, lr, [sp, #128]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #136]
-	str	r5, [sp, #140]
-#else
-	strd  r4, r5, [sp, #136]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #16]
-	ldr	lr, [r0, #20]
-#else
-	ldrd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #24]
-	ldr	r5, [r0, #28]
-#else
-	ldrd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #144]
-	ldr	r7, [sp, #148]
-#else
-	ldrd  r6, r7, [sp, #144]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [sp, #152]
-	ldr	r9, [sp, #156]
-#else
-	ldrd  r8, r9, [sp, #152]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #16]
-	str	lr, [r0, #20]
-#else
-	strd  r12, lr, [r0, #16]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #24]
-	str	r5, [r0, #28]
-#else
-	strd  r4, r5, [r0, #24]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #144]
-	str	lr, [sp, #148]
-#else
-	strd  r12, lr, [sp, #144]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #152]
-	str	r5, [sp, #156]
-#else
-	strd  r4, r5, [sp, #152]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #32]
-	ldr	lr, [r0, #36]
-#else
-	ldrd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #40]
-	ldr	r5, [r0, #44]
-#else
-	ldrd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #160]
-	ldr	r7, [sp, #164]
-#else
-	ldrd  r6, r7, [sp, #160]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [sp, #168]
-	ldr	r9, [sp, #172]
-#else
-	ldrd  r8, r9, [sp, #168]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #32]
-	str	lr, [r0, #36]
-#else
-	strd  r12, lr, [r0, #32]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #40]
-	str	r5, [r0, #44]
-#else
-	strd  r4, r5, [r0, #40]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #160]
-	str	lr, [sp, #164]
-#else
-	strd  r12, lr, [sp, #160]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #168]
-	str	r5, [sp, #172]
-#else
-	strd  r4, r5, [sp, #168]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r12, [r0, #48]
-	ldr	lr, [r0, #52]
-#else
-	ldrd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r4, [r0, #56]
-	ldr	r5, [r0, #60]
-#else
-	ldrd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r6, [sp, #176]
-	ldr	r7, [sp, #180]
-#else
-	ldrd  r6, r7, [sp, #176]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	ldr	r8, [sp, #184]
-	ldr	r9, [sp, #188]
-#else
-	ldrd  r8, r9, [sp, #184]
-#endif
-	adds	r12, r12, r6
-	adc	lr, lr, r7
-	adds	r4, r4, r8
-	adc	r5, r5, r9
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [r0, #48]
-	str	lr, [r0, #52]
-#else
-	strd  r12, lr, [r0, #48]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [r0, #56]
-	str	r5, [r0, #60]
-#else
-	strd  r4, r5, [r0, #56]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r12, [sp, #176]
-	str	lr, [sp, #180]
-#else
-	strd  r12, lr, [sp, #176]
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-	str	r4, [sp, #184]
-	str	r5, [sp, #188]
-#else
-	strd  r4, r5, [sp, #184]
+	strd	r6, r7, [sp, #184]
 #endif
 	subs	r2, r2, #0x80
 	sub	r3, r3, #0x200
@@ -7570,7 +7570,7 @@ L_SHA512_transform_len_start:
 	.text
 	.type	L_SHA512_transform_neon_len_k, %object
 	.size	L_SHA512_transform_neon_len_k, 640
-	.align	3
+	.align	4
 L_SHA512_transform_neon_len_k:
 	.word	0xd728ae22
 	.word	0x428a2f98
@@ -7733,7 +7733,7 @@ L_SHA512_transform_neon_len_k:
 	.word	0x4a475817
 	.word	0x6c44198c
 	.text
-	.align	2
+	.align	4
 	.fpu	neon
 	.globl	Transform_Sha512_Len
 	.type	Transform_Sha512_Len, %function
diff --git a/wolfcrypt/src/port/arm/armv8-32-sha512-asm_c.c b/wolfcrypt/src/port/arm/armv8-32-sha512-asm_c.c
index 2ba4e96e6..3075c70c0 100644
--- a/wolfcrypt/src/port/arm/armv8-32-sha512-asm_c.c
+++ b/wolfcrypt/src/port/arm/armv8-32-sha512-asm_c.c
@@ -132,10 +132,1082 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "mov	r3, %[L_SHA512_transform_len_k]\n\t"
         /* Copy digest to add in at end */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[sha512], #24]\n\t"
+        "ldr	r11, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r10, r11, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #128]\n\t"
+        "str	r5, [sp, #132]\n\t"
+#else
+        "strd	r4, r5, [sp, #128]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [sp, #136]\n\t"
+        "str	r7, [sp, #140]\n\t"
+#else
+        "strd	r6, r7, [sp, #136]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [sp, #144]\n\t"
+        "str	r9, [sp, #148]\n\t"
+#else
+        "strd	r8, r9, [sp, #144]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r10, [sp, #152]\n\t"
+        "str	r11, [sp, #156]\n\t"
+#else
+        "strd	r10, r11, [sp, #152]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[sha512], #56]\n\t"
+        "ldr	r11, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r10, r11, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #160]\n\t"
+        "str	r5, [sp, #164]\n\t"
+#else
+        "strd	r4, r5, [sp, #160]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [sp, #168]\n\t"
+        "str	r7, [sp, #172]\n\t"
+#else
+        "strd	r6, r7, [sp, #168]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [sp, #176]\n\t"
+        "str	r9, [sp, #180]\n\t"
+#else
+        "strd	r8, r9, [sp, #176]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r10, [sp, #184]\n\t"
+        "str	r11, [sp, #188]\n\t"
+#else
+        "strd	r10, r11, [sp, #184]\n\t"
+#endif
+        /* Start of loop processing a block */
+        "\n"
+    "L_SHA512_transform_len_begin_%=: \n\t"
+        /* Load, Reverse and Store W */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[data]]\n\t"
+        "ldr	r5, [%[data], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[data]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[data], #8]\n\t"
+        "ldr	r7, [%[data], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[data], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[data], #16]\n\t"
+        "ldr	r9, [%[data], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[data], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[data], #24]\n\t"
+        "ldr	r11, [%[data], #28]\n\t"
+#else
+        "ldrd	r10, r11, [%[data], #24]\n\t"
+#endif
+        "rev	r4, r4\n\t"
+        "rev	r5, r5\n\t"
+        "rev	r6, r6\n\t"
+        "rev	r7, r7\n\t"
+        "rev	r8, r8\n\t"
+        "rev	r9, r9\n\t"
+        "rev	r10, r10\n\t"
+        "rev	r11, r11\n\t"
+        "str	r5, [sp]\n\t"
+        "str	r4, [sp, #4]\n\t"
+        "str	r7, [sp, #8]\n\t"
+        "str	r6, [sp, #12]\n\t"
+        "str	r9, [sp, #16]\n\t"
+        "str	r8, [sp, #20]\n\t"
+        "str	r11, [sp, #24]\n\t"
+        "str	r10, [sp, #28]\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[data], #32]\n\t"
+        "ldr	r5, [%[data], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[data], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[data], #40]\n\t"
+        "ldr	r7, [%[data], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[data], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[data], #48]\n\t"
+        "ldr	r9, [%[data], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[data], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[data], #56]\n\t"
+        "ldr	r11, [%[data], #60]\n\t"
+#else
+        "ldrd	r10, r11, [%[data], #56]\n\t"
+#endif
+        "rev	r4, r4\n\t"
+        "rev	r5, r5\n\t"
+        "rev	r6, r6\n\t"
+        "rev	r7, r7\n\t"
+        "rev	r8, r8\n\t"
+        "rev	r9, r9\n\t"
+        "rev	r10, r10\n\t"
+        "rev	r11, r11\n\t"
+        "str	r5, [sp, #32]\n\t"
+        "str	r4, [sp, #36]\n\t"
+        "str	r7, [sp, #40]\n\t"
+        "str	r6, [sp, #44]\n\t"
+        "str	r9, [sp, #48]\n\t"
+        "str	r8, [sp, #52]\n\t"
+        "str	r11, [sp, #56]\n\t"
+        "str	r10, [sp, #60]\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[data], #64]\n\t"
+        "ldr	r5, [%[data], #68]\n\t"
+#else
+        "ldrd	r4, r5, [%[data], #64]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[data], #72]\n\t"
+        "ldr	r7, [%[data], #76]\n\t"
+#else
+        "ldrd	r6, r7, [%[data], #72]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[data], #80]\n\t"
+        "ldr	r9, [%[data], #84]\n\t"
+#else
+        "ldrd	r8, r9, [%[data], #80]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[data], #88]\n\t"
+        "ldr	r11, [%[data], #92]\n\t"
+#else
+        "ldrd	r10, r11, [%[data], #88]\n\t"
+#endif
+        "rev	r4, r4\n\t"
+        "rev	r5, r5\n\t"
+        "rev	r6, r6\n\t"
+        "rev	r7, r7\n\t"
+        "rev	r8, r8\n\t"
+        "rev	r9, r9\n\t"
+        "rev	r10, r10\n\t"
+        "rev	r11, r11\n\t"
+        "str	r5, [sp, #64]\n\t"
+        "str	r4, [sp, #68]\n\t"
+        "str	r7, [sp, #72]\n\t"
+        "str	r6, [sp, #76]\n\t"
+        "str	r9, [sp, #80]\n\t"
+        "str	r8, [sp, #84]\n\t"
+        "str	r11, [sp, #88]\n\t"
+        "str	r10, [sp, #92]\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[data], #96]\n\t"
+        "ldr	r5, [%[data], #100]\n\t"
+#else
+        "ldrd	r4, r5, [%[data], #96]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[data], #104]\n\t"
+        "ldr	r7, [%[data], #108]\n\t"
+#else
+        "ldrd	r6, r7, [%[data], #104]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[data], #112]\n\t"
+        "ldr	r9, [%[data], #116]\n\t"
+#else
+        "ldrd	r8, r9, [%[data], #112]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[data], #120]\n\t"
+        "ldr	r11, [%[data], #124]\n\t"
+#else
+        "ldrd	r10, r11, [%[data], #120]\n\t"
+#endif
+        "rev	r4, r4\n\t"
+        "rev	r5, r5\n\t"
+        "rev	r6, r6\n\t"
+        "rev	r7, r7\n\t"
+        "rev	r8, r8\n\t"
+        "rev	r9, r9\n\t"
+        "rev	r10, r10\n\t"
+        "rev	r11, r11\n\t"
+        "str	r5, [sp, #96]\n\t"
+        "str	r4, [sp, #100]\n\t"
+        "str	r7, [sp, #104]\n\t"
+        "str	r6, [sp, #108]\n\t"
+        "str	r9, [sp, #112]\n\t"
+        "str	r8, [sp, #116]\n\t"
+        "str	r11, [sp, #120]\n\t"
+        "str	r10, [sp, #124]\n\t"
+        /* Pre-calc: b ^ c */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [%[sha512], #8]\n\t"
+        "ldr	r11, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r10, r11, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r10, r10, r4\n\t"
+        "eor	r11, r11, r5\n\t"
+        "mov	r12, #4\n\t"
+        /* Start of 16 rounds */
+        "\n"
+    "L_SHA512_transform_len_start_%=: \n\t"
+        /* Round 0 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp]\n\t"
+        "ldr	r9, [sp, #4]\n\t"
+#else
+        "ldrd	r8, r9, [sp]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3]\n\t"
+        "ldr	r7, [r3, #4]\n\t"
+#else
+        "ldrd	r6, r7, [r3]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #24]\n\t"
+        "str	r9, [%[sha512], #28]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #56]\n\t"
+        "str	r7, [%[sha512], #60]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[0] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #112]\n\t"
+        "ldr	r5, [sp, #116]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #112]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp]\n\t"
+        "ldr	r5, [sp, #4]\n\t"
+#else
+        "ldrd	r4, r5, [sp]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #72]\n\t"
+        "ldr	r9, [sp, #76]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #72]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp]\n\t"
+        "str	r5, [sp, #4]\n\t"
+#else
+        "strd	r4, r5, [sp]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #8]\n\t"
+        "ldr	r5, [sp, #12]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #8]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp]\n\t"
+        "ldr	r5, [sp, #4]\n\t"
+#else
+        "ldrd	r4, r5, [sp]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp]\n\t"
+        "str	r5, [sp, #4]\n\t"
+#else
+        "strd	r4, r5, [sp]\n\t"
+#endif
+        /* Round 1 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #8]\n\t"
+        "ldr	r9, [sp, #12]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #8]\n\t"
+        "ldr	r7, [r3, #12]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #8]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #16]\n\t"
+        "str	r9, [%[sha512], #20]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #48]\n\t"
+        "str	r7, [%[sha512], #52]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[1] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #120]\n\t"
+        "ldr	r5, [sp, #124]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #120]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #8]\n\t"
+        "ldr	r5, [sp, #12]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #80]\n\t"
+        "ldr	r9, [sp, #84]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #80]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #8]\n\t"
+        "str	r5, [sp, #12]\n\t"
+#else
+        "strd	r4, r5, [sp, #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #16]\n\t"
+        "ldr	r5, [sp, #20]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #16]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #8]\n\t"
+        "ldr	r5, [sp, #12]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #8]\n\t"
+        "str	r5, [sp, #12]\n\t"
+#else
+        "strd	r4, r5, [sp, #8]\n\t"
+#endif
+        /* Round 2 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #16]\n\t"
+        "ldr	r9, [sp, #20]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #16]\n\t"
+        "ldr	r7, [r3, #20]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #16]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #8]\n\t"
+        "str	r9, [%[sha512], #12]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #40]\n\t"
+        "str	r7, [%[sha512], #44]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[2] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp]\n\t"
+        "ldr	r5, [sp, #4]\n\t"
+#else
+        "ldrd	r4, r5, [sp]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #16]\n\t"
+        "ldr	r5, [sp, #20]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #88]\n\t"
+        "ldr	r9, [sp, #92]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #88]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #16]\n\t"
+        "str	r5, [sp, #20]\n\t"
+#else
+        "strd	r4, r5, [sp, #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #24]\n\t"
+        "ldr	r5, [sp, #28]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #24]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #16]\n\t"
+        "ldr	r5, [sp, #20]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #16]\n\t"
+        "str	r5, [sp, #20]\n\t"
+#else
+        "strd	r4, r5, [sp, #16]\n\t"
+#endif
+        /* Round 3 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #8]\n\t"
@@ -155,35 +1227,1003 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r8, r9, [%[sha512], #24]\n\t"
 #endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #128]\n\t"
-        "str	lr, [sp, #132]\n\t"
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
 #else
-        "strd	r12, lr, [sp, #128]\n\t"
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #136]\n\t"
-        "str	r5, [sp, #140]\n\t"
+        "ldr	r8, [sp, #24]\n\t"
+        "ldr	r9, [sp, #28]\n\t"
 #else
-        "strd	r4, r5, [sp, #136]\n\t"
+        "ldrd	r8, r9, [sp, #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #24]\n\t"
+        "ldr	r7, [r3, #28]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #24]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [sp, #144]\n\t"
-        "str	r7, [sp, #148]\n\t"
+        "str	r8, [%[sha512]]\n\t"
+        "str	r9, [%[sha512], #4]\n\t"
 #else
-        "strd	r6, r7, [sp, #144]\n\t"
+        "strd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [sp, #152]\n\t"
-        "str	r9, [sp, #156]\n\t"
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
 #else
-        "strd	r8, r9, [sp, #152]\n\t"
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #32]\n\t"
+        "str	r7, [%[sha512], #36]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[3] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #8]\n\t"
+        "ldr	r5, [sp, #12]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #8]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #24]\n\t"
+        "ldr	r5, [sp, #28]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #96]\n\t"
+        "ldr	r9, [sp, #100]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #96]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #24]\n\t"
+        "str	r5, [sp, #28]\n\t"
+#else
+        "strd	r4, r5, [sp, #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #32]\n\t"
+        "ldr	r5, [sp, #36]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #32]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #24]\n\t"
+        "ldr	r5, [sp, #28]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #24]\n\t"
+        "str	r5, [sp, #28]\n\t"
+#else
+        "strd	r4, r5, [sp, #24]\n\t"
+#endif
+        /* Round 4 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #32]\n\t"
+        "ldr	r9, [sp, #36]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #32]\n\t"
+        "ldr	r7, [r3, #36]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #32]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #56]\n\t"
+        "str	r9, [%[sha512], #60]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #24]\n\t"
+        "str	r7, [%[sha512], #28]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[4] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #16]\n\t"
+        "ldr	r5, [sp, #20]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #16]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #32]\n\t"
+        "ldr	r5, [sp, #36]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #104]\n\t"
+        "ldr	r9, [sp, #108]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #104]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #32]\n\t"
+        "str	r5, [sp, #36]\n\t"
+#else
+        "strd	r4, r5, [sp, #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #40]\n\t"
+        "ldr	r5, [sp, #44]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #40]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #32]\n\t"
+        "ldr	r5, [sp, #36]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #32]\n\t"
+        "str	r5, [sp, #36]\n\t"
+#else
+        "strd	r4, r5, [sp, #32]\n\t"
+#endif
+        /* Round 5 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #40]\n\t"
+        "ldr	r9, [sp, #44]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #40]\n\t"
+        "ldr	r7, [r3, #44]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #40]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #48]\n\t"
+        "str	r9, [%[sha512], #52]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #16]\n\t"
+        "str	r7, [%[sha512], #20]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[5] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #24]\n\t"
+        "ldr	r5, [sp, #28]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #24]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #40]\n\t"
+        "ldr	r5, [sp, #44]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #112]\n\t"
+        "ldr	r9, [sp, #116]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #112]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #40]\n\t"
+        "str	r5, [sp, #44]\n\t"
+#else
+        "strd	r4, r5, [sp, #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #48]\n\t"
+        "ldr	r5, [sp, #52]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #48]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #40]\n\t"
+        "ldr	r5, [sp, #44]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #40]\n\t"
+        "str	r5, [sp, #44]\n\t"
+#else
+        "strd	r4, r5, [sp, #40]\n\t"
+#endif
+        /* Round 6 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #48]\n\t"
+        "ldr	r9, [sp, #52]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #48]\n\t"
+        "ldr	r7, [r3, #52]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #48]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #40]\n\t"
+        "str	r9, [%[sha512], #44]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #8]\n\t"
+        "str	r7, [%[sha512], #12]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[6] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #32]\n\t"
+        "ldr	r5, [sp, #36]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #32]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #48]\n\t"
+        "ldr	r5, [sp, #52]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #120]\n\t"
+        "ldr	r9, [sp, #124]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #120]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #48]\n\t"
+        "str	r5, [sp, #52]\n\t"
+#else
+        "strd	r4, r5, [sp, #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #56]\n\t"
+        "ldr	r5, [sp, #60]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #56]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #48]\n\t"
+        "ldr	r5, [sp, #52]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #48]\n\t"
+        "str	r5, [sp, #52]\n\t"
+#else
+        "strd	r4, r5, [sp, #48]\n\t"
+#endif
+        /* Round 7 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #40]\n\t"
@@ -203,2541 +2243,241 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r8, r9, [%[sha512], #56]\n\t"
 #endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #160]\n\t"
-        "str	lr, [sp, #164]\n\t"
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
 #else
-        "strd	r12, lr, [sp, #160]\n\t"
+        "ldrd	r4, r5, [%[sha512]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #168]\n\t"
-        "str	r5, [sp, #172]\n\t"
+        "ldr	r8, [sp, #56]\n\t"
+        "ldr	r9, [sp, #60]\n\t"
 #else
-        "strd	r4, r5, [sp, #168]\n\t"
+        "ldrd	r8, r9, [sp, #56]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #56]\n\t"
+        "ldr	r7, [r3, #60]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #56]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [sp, #176]\n\t"
-        "str	r7, [sp, #180]\n\t"
+        "str	r8, [%[sha512], #32]\n\t"
+        "str	r9, [%[sha512], #36]\n\t"
 #else
-        "strd	r6, r7, [sp, #176]\n\t"
+        "strd	r8, r9, [%[sha512], #32]\n\t"
 #endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r8, [sp, #184]\n\t"
-        "str	r9, [sp, #188]\n\t"
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
 #else
-        "strd	r8, r9, [sp, #184]\n\t"
+        "ldrd	r4, r5, [%[sha512]]\n\t"
 #endif
-        /* Start of loop processing a block */
-        "\n"
-    "L_SHA512_transform_len_begin_%=: \n\t"
-        /* Load, Reverse and Store W */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[data]]\n\t"
-        "ldr	lr, [%[data], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[data]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[data], #8]\n\t"
-        "ldr	r5, [%[data], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[data], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[data], #16]\n\t"
-        "ldr	r7, [%[data], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[data], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[data], #24]\n\t"
-        "ldr	r9, [%[data], #28]\n\t"
-#else
-        "ldrd	r8, r9, [%[data], #24]\n\t"
-#endif
-        "rev	r12, r12\n\t"
-        "rev	lr, lr\n\t"
-        "rev	r4, r4\n\t"
-        "rev	r5, r5\n\t"
-        "rev	r6, r6\n\t"
-        "rev	r7, r7\n\t"
-        "rev	r8, r8\n\t"
-        "rev	r9, r9\n\t"
-        "str	lr, [sp]\n\t"
-        "str	r12, [sp, #4]\n\t"
-        "str	r5, [sp, #8]\n\t"
-        "str	r4, [sp, #12]\n\t"
-        "str	r7, [sp, #16]\n\t"
-        "str	r6, [sp, #20]\n\t"
-        "str	r9, [sp, #24]\n\t"
-        "str	r8, [sp, #28]\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[data], #32]\n\t"
-        "ldr	lr, [%[data], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[data], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[data], #40]\n\t"
-        "ldr	r5, [%[data], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[data], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[data], #48]\n\t"
-        "ldr	r7, [%[data], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[data], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[data], #56]\n\t"
-        "ldr	r9, [%[data], #60]\n\t"
-#else
-        "ldrd	r8, r9, [%[data], #56]\n\t"
-#endif
-        "rev	r12, r12\n\t"
-        "rev	lr, lr\n\t"
-        "rev	r4, r4\n\t"
-        "rev	r5, r5\n\t"
-        "rev	r6, r6\n\t"
-        "rev	r7, r7\n\t"
-        "rev	r8, r8\n\t"
-        "rev	r9, r9\n\t"
-        "str	lr, [sp, #32]\n\t"
-        "str	r12, [sp, #36]\n\t"
-        "str	r5, [sp, #40]\n\t"
-        "str	r4, [sp, #44]\n\t"
-        "str	r7, [sp, #48]\n\t"
-        "str	r6, [sp, #52]\n\t"
-        "str	r9, [sp, #56]\n\t"
-        "str	r8, [sp, #60]\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[data], #64]\n\t"
-        "ldr	lr, [%[data], #68]\n\t"
-#else
-        "ldrd	r12, lr, [%[data], #64]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[data], #72]\n\t"
-        "ldr	r5, [%[data], #76]\n\t"
-#else
-        "ldrd	r4, r5, [%[data], #72]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[data], #80]\n\t"
-        "ldr	r7, [%[data], #84]\n\t"
-#else
-        "ldrd	r6, r7, [%[data], #80]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[data], #88]\n\t"
-        "ldr	r9, [%[data], #92]\n\t"
-#else
-        "ldrd	r8, r9, [%[data], #88]\n\t"
-#endif
-        "rev	r12, r12\n\t"
-        "rev	lr, lr\n\t"
-        "rev	r4, r4\n\t"
-        "rev	r5, r5\n\t"
-        "rev	r6, r6\n\t"
-        "rev	r7, r7\n\t"
-        "rev	r8, r8\n\t"
-        "rev	r9, r9\n\t"
-        "str	lr, [sp, #64]\n\t"
-        "str	r12, [sp, #68]\n\t"
-        "str	r5, [sp, #72]\n\t"
-        "str	r4, [sp, #76]\n\t"
-        "str	r7, [sp, #80]\n\t"
-        "str	r6, [sp, #84]\n\t"
-        "str	r9, [sp, #88]\n\t"
-        "str	r8, [sp, #92]\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[data], #96]\n\t"
-        "ldr	lr, [%[data], #100]\n\t"
-#else
-        "ldrd	r12, lr, [%[data], #96]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[data], #104]\n\t"
-        "ldr	r5, [%[data], #108]\n\t"
-#else
-        "ldrd	r4, r5, [%[data], #104]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[data], #112]\n\t"
-        "ldr	r7, [%[data], #116]\n\t"
-#else
-        "ldrd	r6, r7, [%[data], #112]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [%[data], #120]\n\t"
-        "ldr	r9, [%[data], #124]\n\t"
-#else
-        "ldrd	r8, r9, [%[data], #120]\n\t"
-#endif
-        "rev	r12, r12\n\t"
-        "rev	lr, lr\n\t"
-        "rev	r4, r4\n\t"
-        "rev	r5, r5\n\t"
-        "rev	r6, r6\n\t"
-        "rev	r7, r7\n\t"
-        "rev	r8, r8\n\t"
-        "rev	r9, r9\n\t"
-        "str	lr, [sp, #96]\n\t"
-        "str	r12, [sp, #100]\n\t"
-        "str	r5, [sp, #104]\n\t"
-        "str	r4, [sp, #108]\n\t"
-        "str	r7, [sp, #112]\n\t"
-        "str	r6, [sp, #116]\n\t"
-        "str	r9, [sp, #120]\n\t"
-        "str	r8, [sp, #124]\n\t"
-        /* Pre-calc: b ^ c */
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r8, [%[sha512], #8]\n\t"
         "ldr	r9, [%[sha512], #12]\n\t"
 #else
         "ldrd	r8, r9, [%[sha512], #8]\n\t"
 #endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r8, r8, r12\n\t"
-        "eor	r9, r9, lr\n\t"
-        "mov	r10, #4\n\t"
-        /* Start of 16 rounds */
-        "\n"
-    "L_SHA512_transform_len_start_%=: \n\t"
-        /* Round 0 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp]\n\t"
-        "ldr	r7, [sp, #4]\n\t"
-#else
-        "ldrd	r6, r7, [sp]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3]\n\t"
-        "ldr	r5, [r3, #4]\n\t"
-#else
-        "ldrd	r4, r5, [r3]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #24]\n\t"
-        "str	r7, [%[sha512], #28]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #56]\n\t"
-        "str	r5, [%[sha512], #60]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[0] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #112]\n\t"
-        "ldr	lr, [sp, #116]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #112]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp]\n\t"
-        "ldr	lr, [sp, #4]\n\t"
-#else
-        "ldrd	r12, lr, [sp]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #72]\n\t"
-        "ldr	r7, [sp, #76]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #72]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp]\n\t"
-        "str	lr, [sp, #4]\n\t"
-#else
-        "strd	r12, lr, [sp]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #8]\n\t"
-        "ldr	lr, [sp, #12]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #8]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp]\n\t"
-        "ldr	lr, [sp, #4]\n\t"
-#else
-        "ldrd	r12, lr, [sp]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp]\n\t"
-        "str	lr, [sp, #4]\n\t"
-#else
-        "strd	r12, lr, [sp]\n\t"
-#endif
-        /* Round 1 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #8]\n\t"
-        "ldr	r7, [sp, #12]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #8]\n\t"
-        "ldr	r5, [r3, #12]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #8]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [%[sha512], #16]\n\t"
         "ldr	r7, [%[sha512], #20]\n\t"
 #else
         "ldrd	r6, r7, [%[sha512], #16]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #16]\n\t"
-        "str	r7, [%[sha512], #20]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #48]\n\t"
-        "str	r5, [%[sha512], #52]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[1] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #120]\n\t"
-        "ldr	lr, [sp, #124]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #120]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #8]\n\t"
-        "ldr	lr, [sp, #12]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #80]\n\t"
-        "ldr	r7, [sp, #84]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #80]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #8]\n\t"
-        "str	lr, [sp, #12]\n\t"
-#else
-        "strd	r12, lr, [sp, #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #16]\n\t"
-        "ldr	lr, [sp, #20]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #16]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #8]\n\t"
-        "ldr	lr, [sp, #12]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #8]\n\t"
-        "str	lr, [sp, #12]\n\t"
-#else
-        "strd	r12, lr, [sp, #8]\n\t"
-#endif
-        /* Round 2 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #16]\n\t"
-        "ldr	r7, [sp, #20]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #16]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #16]\n\t"
-        "ldr	r5, [r3, #20]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #16]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #8]\n\t"
-        "str	r7, [%[sha512], #12]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #40]\n\t"
-        "str	r5, [%[sha512], #44]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[2] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp]\n\t"
-        "ldr	lr, [sp, #4]\n\t"
-#else
-        "ldrd	r12, lr, [sp]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #16]\n\t"
-        "ldr	lr, [sp, #20]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #88]\n\t"
-        "ldr	r7, [sp, #92]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #88]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #16]\n\t"
-        "str	lr, [sp, #20]\n\t"
-#else
-        "strd	r12, lr, [sp, #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #24]\n\t"
-        "ldr	lr, [sp, #28]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #24]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #16]\n\t"
-        "ldr	lr, [sp, #20]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #16]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #16]\n\t"
-        "str	lr, [sp, #20]\n\t"
-#else
-        "strd	r12, lr, [sp, #16]\n\t"
-#endif
-        /* Round 3 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #24]\n\t"
-        "ldr	r7, [sp, #28]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #24]\n\t"
-        "ldr	r5, [r3, #28]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #24]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512]]\n\t"
-        "str	r7, [%[sha512], #4]\n\t"
-#else
-        "strd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #32]\n\t"
-        "str	r5, [%[sha512], #36]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[3] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #8]\n\t"
-        "ldr	lr, [sp, #12]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #8]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #24]\n\t"
-        "ldr	lr, [sp, #28]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #96]\n\t"
-        "ldr	r7, [sp, #100]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #96]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #24]\n\t"
-        "str	lr, [sp, #28]\n\t"
-#else
-        "strd	r12, lr, [sp, #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #32]\n\t"
-        "ldr	lr, [sp, #36]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #32]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #24]\n\t"
-        "ldr	lr, [sp, #28]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #24]\n\t"
-        "str	lr, [sp, #28]\n\t"
-#else
-        "strd	r12, lr, [sp, #24]\n\t"
-#endif
-        /* Round 4 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #32]\n\t"
-        "ldr	r7, [sp, #36]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #32]\n\t"
-        "ldr	r5, [r3, #36]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #32]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #56]\n\t"
-        "str	r7, [%[sha512], #60]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #24]\n\t"
-        "str	r5, [%[sha512], #28]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[4] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #16]\n\t"
-        "ldr	lr, [sp, #20]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #16]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #32]\n\t"
-        "ldr	lr, [sp, #36]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #104]\n\t"
-        "ldr	r7, [sp, #108]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #104]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #32]\n\t"
-        "str	lr, [sp, #36]\n\t"
-#else
-        "strd	r12, lr, [sp, #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #40]\n\t"
-        "ldr	lr, [sp, #44]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #40]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #32]\n\t"
-        "ldr	lr, [sp, #36]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #32]\n\t"
-        "str	lr, [sp, #36]\n\t"
-#else
-        "strd	r12, lr, [sp, #32]\n\t"
-#endif
-        /* Round 5 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #40]\n\t"
-        "ldr	r7, [sp, #44]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #40]\n\t"
-        "ldr	r5, [r3, #44]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #40]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #48]\n\t"
-        "str	r7, [%[sha512], #52]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #16]\n\t"
-        "str	r5, [%[sha512], #20]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[5] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #24]\n\t"
-        "ldr	lr, [sp, #28]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #24]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #40]\n\t"
-        "ldr	lr, [sp, #44]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #112]\n\t"
-        "ldr	r7, [sp, #116]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #112]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #40]\n\t"
-        "str	lr, [sp, #44]\n\t"
-#else
-        "strd	r12, lr, [sp, #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #48]\n\t"
-        "ldr	lr, [sp, #52]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #48]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #40]\n\t"
-        "ldr	lr, [sp, #44]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #40]\n\t"
-        "str	lr, [sp, #44]\n\t"
-#else
-        "strd	r12, lr, [sp, #40]\n\t"
-#endif
-        /* Round 6 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #48]\n\t"
-        "ldr	r7, [sp, #52]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #48]\n\t"
-        "ldr	r5, [r3, #52]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #48]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #40]\n\t"
-        "str	r7, [%[sha512], #44]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #8]\n\t"
-        "str	r5, [%[sha512], #12]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[6] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #32]\n\t"
-        "ldr	lr, [sp, #36]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #32]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #48]\n\t"
-        "ldr	lr, [sp, #52]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #120]\n\t"
-        "ldr	r7, [sp, #124]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #120]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #48]\n\t"
-        "str	lr, [sp, #52]\n\t"
-#else
-        "strd	r12, lr, [sp, #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #56]\n\t"
-        "ldr	lr, [sp, #60]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #56]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #48]\n\t"
-        "ldr	lr, [sp, #52]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #48]\n\t"
-        "str	lr, [sp, #52]\n\t"
-#else
-        "strd	r12, lr, [sp, #48]\n\t"
-#endif
-        /* Round 7 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #56]\n\t"
-        "ldr	r7, [sp, #60]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #56]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #56]\n\t"
-        "ldr	r5, [r3, #60]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #56]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #32]\n\t"
-        "str	r7, [%[sha512], #36]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512]]\n\t"
         "str	r5, [%[sha512], #4]\n\t"
 #else
         "strd	r4, r5, [%[sha512]]\n\t"
 #endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512]]\n\t"
+        "str	r7, [%[sha512], #4]\n\t"
+#else
+        "strd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
         /* Calc new W[7] */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #40]\n\t"
-        "ldr	lr, [sp, #44]\n\t"
+        "ldr	r4, [sp, #40]\n\t"
+        "ldr	r5, [sp, #44]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #40]\n\t"
+        "ldrd	r4, r5, [sp, #40]\n\t"
 #endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #56]\n\t"
-        "ldr	lr, [sp, #60]\n\t"
+        "ldr	r4, [sp, #56]\n\t"
+        "ldr	r5, [sp, #60]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #56]\n\t"
+        "ldrd	r4, r5, [sp, #56]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp]\n\t"
-        "ldr	r7, [sp, #4]\n\t"
+        "ldr	r8, [sp]\n\t"
+        "ldr	r9, [sp, #4]\n\t"
 #else
-        "ldrd	r6, r7, [sp]\n\t"
+        "ldrd	r8, r9, [sp]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #56]\n\t"
-        "str	lr, [sp, #60]\n\t"
+        "str	r4, [sp, #56]\n\t"
+        "str	r5, [sp, #60]\n\t"
 #else
-        "strd	r12, lr, [sp, #56]\n\t"
+        "strd	r4, r5, [sp, #56]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #64]\n\t"
-        "ldr	lr, [sp, #68]\n\t"
+        "ldr	r4, [sp, #64]\n\t"
+        "ldr	r5, [sp, #68]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #64]\n\t"
+        "ldrd	r4, r5, [sp, #64]\n\t"
 #endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #56]\n\t"
-        "ldr	lr, [sp, #60]\n\t"
+        "ldr	r4, [sp, #56]\n\t"
+        "ldr	r5, [sp, #60]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #56]\n\t"
+        "ldrd	r4, r5, [sp, #56]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #56]\n\t"
-        "str	lr, [sp, #60]\n\t"
+        "str	r4, [sp, #56]\n\t"
+        "str	r5, [sp, #60]\n\t"
 #else
-        "strd	r12, lr, [sp, #56]\n\t"
+        "strd	r4, r5, [sp, #56]\n\t"
 #endif
         /* Round 8 */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
 #endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #64]\n\t"
-        "ldr	r7, [sp, #68]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #64]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #64]\n\t"
-        "ldr	r5, [r3, #68]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #64]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #24]\n\t"
-        "str	r7, [%[sha512], #28]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #56]\n\t"
         "ldr	r5, [%[sha512], #60]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512], #56]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #56]\n\t"
         "str	r5, [%[sha512], #60]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[8] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #48]\n\t"
-        "ldr	lr, [sp, #52]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #48]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #64]\n\t"
-        "ldr	lr, [sp, #68]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #64]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #8]\n\t"
-        "ldr	r7, [sp, #12]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #64]\n\t"
-        "str	lr, [sp, #68]\n\t"
-#else
-        "strd	r12, lr, [sp, #64]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #72]\n\t"
-        "ldr	lr, [sp, #76]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #72]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #64]\n\t"
-        "ldr	lr, [sp, #68]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #64]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #64]\n\t"
-        "str	lr, [sp, #68]\n\t"
-#else
-        "strd	r12, lr, [sp, #64]\n\t"
-#endif
-        /* Round 9 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #32]\n\t"
@@ -2751,346 +2491,18 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #40]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #72]\n\t"
-        "ldr	r7, [sp, #76]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #72]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #72]\n\t"
-        "ldr	r5, [r3, #76]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #72]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #16]\n\t"
-        "str	r7, [%[sha512], #20]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #48]\n\t"
-        "str	r5, [%[sha512], #52]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[9] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #56]\n\t"
-        "ldr	lr, [sp, #60]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #56]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #72]\n\t"
-        "ldr	lr, [sp, #76]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #72]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #16]\n\t"
-        "ldr	r7, [sp, #20]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #16]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #72]\n\t"
-        "str	lr, [sp, #76]\n\t"
-#else
-        "strd	r12, lr, [sp, #72]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #80]\n\t"
-        "ldr	lr, [sp, #84]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #80]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #72]\n\t"
-        "ldr	lr, [sp, #76]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #72]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #72]\n\t"
-        "str	lr, [sp, #76]\n\t"
-#else
-        "strd	r12, lr, [sp, #72]\n\t"
-#endif
-        /* Round 10 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #80]\n\t"
-        "ldr	r7, [sp, #84]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #80]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #80]\n\t"
-        "ldr	r5, [r3, #84]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #80]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #8]\n\t"
-        "str	r7, [%[sha512], #12]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
 #endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #56]\n\t"
         "ldr	r5, [%[sha512], #60]\n\t"
@@ -3098,507 +2510,507 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "ldrd	r4, r5, [%[sha512], #56]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
+        "ldr	r8, [sp, #64]\n\t"
+        "ldr	r9, [sp, #68]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
+        "ldrd	r8, r9, [sp, #64]\n\t"
 #endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
+        "ldr	r6, [r3, #64]\n\t"
+        "ldr	r7, [r3, #68]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+        "ldrd	r6, r7, [r3, #64]\n\t"
 #endif
         "adds	r4, r4, r8\n\t"
         "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #40]\n\t"
-        "str	r5, [%[sha512], #44]\n\t"
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
 #else
-        "strd	r4, r5, [%[sha512], #40]\n\t"
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
 #endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[10] */
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #64]\n\t"
-        "ldr	lr, [sp, #68]\n\t"
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #64]\n\t"
+        "strd	r4, r5, [%[sha512], #56]\n\t"
 #endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #80]\n\t"
-        "ldr	lr, [sp, #84]\n\t"
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #80]\n\t"
+        "ldrd	r4, r5, [%[sha512]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #24]\n\t"
-        "ldr	r7, [sp, #28]\n\t"
+        "str	r8, [%[sha512], #24]\n\t"
+        "str	r9, [%[sha512], #28]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #24]\n\t"
+        "strd	r8, r9, [%[sha512], #24]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #80]\n\t"
-        "str	lr, [sp, #84]\n\t"
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
 #else
-        "strd	r12, lr, [sp, #80]\n\t"
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #88]\n\t"
-        "ldr	lr, [sp, #92]\n\t"
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #88]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #80]\n\t"
-        "ldr	lr, [sp, #84]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #80]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #80]\n\t"
-        "str	lr, [sp, #84]\n\t"
-#else
-        "strd	r12, lr, [sp, #80]\n\t"
-#endif
-        /* Round 11 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
+        "strd	r4, r5, [%[sha512], #56]\n\t"
 #endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #88]\n\t"
-        "ldr	r7, [sp, #92]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #88]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #88]\n\t"
-        "ldr	r5, [r3, #92]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #88]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512]]\n\t"
-        "str	r7, [%[sha512], #4]\n\t"
-#else
-        "strd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #32]\n\t"
-        "str	r5, [%[sha512], #36]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[11] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #72]\n\t"
-        "ldr	lr, [sp, #76]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #72]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #88]\n\t"
-        "ldr	lr, [sp, #92]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #88]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #32]\n\t"
-        "ldr	r7, [sp, #36]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #88]\n\t"
-        "str	lr, [sp, #92]\n\t"
-#else
-        "strd	r12, lr, [sp, #88]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #96]\n\t"
-        "ldr	lr, [sp, #100]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #96]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #88]\n\t"
-        "ldr	lr, [sp, #92]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #88]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #88]\n\t"
-        "str	lr, [sp, #92]\n\t"
-#else
-        "strd	r12, lr, [sp, #88]\n\t"
-#endif
-        /* Round 12 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #96]\n\t"
-        "ldr	r7, [sp, #100]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #96]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #96]\n\t"
-        "ldr	r5, [r3, #100]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #96]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [%[sha512], #56]\n\t"
         "ldr	r7, [%[sha512], #60]\n\t"
 #else
         "ldrd	r6, r7, [%[sha512], #56]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [%[sha512], #56]\n\t"
         "str	r7, [%[sha512], #60]\n\t"
 #else
         "strd	r6, r7, [%[sha512], #56]\n\t"
 #endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[8] */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
+        "ldr	r4, [sp, #48]\n\t"
+        "ldr	r5, [sp, #52]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
+        "ldrd	r4, r5, [sp, #48]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #64]\n\t"
+        "ldr	r5, [sp, #68]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #64]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #8]\n\t"
+        "ldr	r9, [sp, #12]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #64]\n\t"
+        "str	r5, [sp, #68]\n\t"
+#else
+        "strd	r4, r5, [sp, #64]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #72]\n\t"
+        "ldr	r5, [sp, #76]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #72]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #64]\n\t"
+        "ldr	r5, [sp, #68]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #64]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #64]\n\t"
+        "str	r5, [sp, #68]\n\t"
+#else
+        "strd	r4, r5, [sp, #64]\n\t"
+#endif
+        /* Round 9 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [%[sha512], #32]\n\t"
         "ldr	r7, [%[sha512], #36]\n\t"
 #else
         "ldrd	r6, r7, [%[sha512], #32]\n\t"
 #endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #72]\n\t"
+        "ldr	r9, [sp, #76]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #72]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #72]\n\t"
+        "ldr	r7, [r3, #76]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #72]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #16]\n\t"
+        "str	r9, [%[sha512], #20]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #48]\n\t"
+        "str	r7, [%[sha512], #52]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[9] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #56]\n\t"
+        "ldr	r5, [sp, #60]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #56]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #72]\n\t"
+        "ldr	r5, [sp, #76]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #72]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #16]\n\t"
+        "ldr	r9, [sp, #20]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #72]\n\t"
+        "str	r5, [sp, #76]\n\t"
+#else
+        "strd	r4, r5, [sp, #72]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #80]\n\t"
+        "ldr	r5, [sp, #84]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #80]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #72]\n\t"
+        "ldr	r5, [sp, #76]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #72]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #72]\n\t"
+        "str	r5, [sp, #76]\n\t"
+#else
+        "strd	r4, r5, [sp, #72]\n\t"
+#endif
+        /* Round 10 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #40]\n\t"
         "ldr	r5, [%[sha512], #44]\n\t"
@@ -3606,154 +3018,482 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "ldrd	r4, r5, [%[sha512], #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
+        "ldr	r8, [sp, #80]\n\t"
+        "ldr	r9, [sp, #84]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
+        "ldrd	r8, r9, [sp, #80]\n\t"
 #endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #80]\n\t"
+        "ldr	r7, [r3, #84]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #80]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #8]\n\t"
+        "str	r9, [%[sha512], #12]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #40]\n\t"
+        "str	r7, [%[sha512], #44]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[10] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #64]\n\t"
+        "ldr	r5, [sp, #68]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #64]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #80]\n\t"
+        "ldr	r5, [sp, #84]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #80]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #24]\n\t"
+        "ldr	r9, [sp, #28]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #80]\n\t"
+        "str	r5, [sp, #84]\n\t"
+#else
+        "strd	r4, r5, [sp, #80]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #88]\n\t"
+        "ldr	r5, [sp, #92]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #88]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #80]\n\t"
+        "ldr	r5, [sp, #84]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #80]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #80]\n\t"
+        "str	r5, [sp, #84]\n\t"
+#else
+        "strd	r4, r5, [sp, #80]\n\t"
+#endif
+        /* Round 11 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #88]\n\t"
+        "ldr	r9, [sp, #92]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #88]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #88]\n\t"
+        "ldr	r7, [r3, #92]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #88]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512]]\n\t"
+        "str	r9, [%[sha512], #4]\n\t"
+#else
+        "strd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #32]\n\t"
+        "str	r7, [%[sha512], #36]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[11] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #72]\n\t"
+        "ldr	r5, [sp, #76]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #72]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #88]\n\t"
+        "ldr	r5, [sp, #92]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #88]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #32]\n\t"
+        "ldr	r9, [sp, #36]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #88]\n\t"
+        "str	r5, [sp, #92]\n\t"
+#else
+        "strd	r4, r5, [sp, #88]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #96]\n\t"
+        "ldr	r5, [sp, #100]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #96]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #88]\n\t"
+        "ldr	r5, [sp, #92]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #88]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #88]\n\t"
+        "str	r5, [sp, #92]\n\t"
+#else
+        "strd	r4, r5, [sp, #88]\n\t"
+#endif
+        /* Round 12 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #24]\n\t"
         "ldr	r5, [%[sha512], #28]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512], #24]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #24]\n\t"
         "str	r5, [%[sha512], #28]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[12] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #80]\n\t"
-        "ldr	lr, [sp, #84]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #80]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #96]\n\t"
-        "ldr	lr, [sp, #100]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #96]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #40]\n\t"
-        "ldr	r7, [sp, #44]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #96]\n\t"
-        "str	lr, [sp, #100]\n\t"
-#else
-        "strd	r12, lr, [sp, #96]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #104]\n\t"
-        "ldr	lr, [sp, #108]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #104]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #96]\n\t"
-        "ldr	lr, [sp, #100]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #96]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #96]\n\t"
-        "str	lr, [sp, #100]\n\t"
-#else
-        "strd	r12, lr, [sp, #96]\n\t"
-#endif
-        /* Round 13 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512]]\n\t"
@@ -3767,92 +3507,56 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #8]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #104]\n\t"
-        "ldr	r7, [sp, #108]\n\t"
+        "ldr	r8, [sp, #96]\n\t"
+        "ldr	r9, [sp, #100]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #104]\n\t"
+        "ldrd	r8, r9, [sp, #96]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #104]\n\t"
-        "ldr	r5, [r3, #108]\n\t"
+        "ldr	r6, [r3, #96]\n\t"
+        "ldr	r7, [r3, #100]\n\t"
 #else
-        "ldrd	r4, r5, [r3, #104]\n\t"
+        "ldrd	r6, r7, [r3, #96]\n\t"
 #endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
 #else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #48]\n\t"
-        "str	r7, [%[sha512], #52]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+        "strd	r4, r5, [%[sha512], #24]\n\t"
 #endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #32]\n\t"
         "ldr	r5, [%[sha512], #36]\n\t"
@@ -3860,154 +3564,190 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "ldrd	r4, r5, [%[sha512], #32]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
+        "str	r8, [%[sha512], #56]\n\t"
+        "str	r9, [%[sha512], #60]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
+        "strd	r8, r9, [%[sha512], #56]\n\t"
 #endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #24]\n\t"
+        "str	r7, [%[sha512], #28]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[12] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #80]\n\t"
+        "ldr	r5, [sp, #84]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #80]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #96]\n\t"
+        "ldr	r5, [sp, #100]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #96]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #40]\n\t"
+        "ldr	r9, [sp, #44]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #96]\n\t"
+        "str	r5, [sp, #100]\n\t"
+#else
+        "strd	r4, r5, [sp, #96]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #104]\n\t"
+        "ldr	r5, [sp, #108]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #104]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #96]\n\t"
+        "ldr	r5, [sp, #100]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #96]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #96]\n\t"
+        "str	r5, [sp, #100]\n\t"
+#else
+        "strd	r4, r5, [sp, #96]\n\t"
+#endif
+        /* Round 13 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #16]\n\t"
         "ldr	r5, [%[sha512], #20]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512], #16]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #16]\n\t"
         "str	r5, [%[sha512], #20]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[13] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #88]\n\t"
-        "ldr	lr, [sp, #92]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #88]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #104]\n\t"
-        "ldr	lr, [sp, #108]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #104]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #48]\n\t"
-        "ldr	r7, [sp, #52]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #104]\n\t"
-        "str	lr, [sp, #108]\n\t"
-#else
-        "strd	r12, lr, [sp, #104]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #112]\n\t"
-        "ldr	lr, [sp, #116]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #112]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #104]\n\t"
-        "ldr	lr, [sp, #108]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #104]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #104]\n\t"
-        "str	lr, [sp, #108]\n\t"
-#else
-        "strd	r12, lr, [sp, #104]\n\t"
-#endif
-        /* Round 14 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #56]\n\t"
@@ -4021,92 +3761,56 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512]]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #112]\n\t"
-        "ldr	r7, [sp, #116]\n\t"
+        "ldr	r8, [sp, #104]\n\t"
+        "ldr	r9, [sp, #108]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #112]\n\t"
+        "ldrd	r8, r9, [sp, #104]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #112]\n\t"
-        "ldr	r5, [r3, #116]\n\t"
+        "ldr	r6, [r3, #104]\n\t"
+        "ldr	r7, [r3, #108]\n\t"
 #else
-        "ldrd	r4, r5, [r3, #112]\n\t"
+        "ldrd	r6, r7, [r3, #104]\n\t"
 #endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
 #else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #40]\n\t"
-        "str	r7, [%[sha512], #44]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+        "strd	r4, r5, [%[sha512], #16]\n\t"
 #endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #24]\n\t"
         "ldr	r5, [%[sha512], #28]\n\t"
@@ -4114,154 +3818,190 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "ldrd	r4, r5, [%[sha512], #24]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
+        "str	r8, [%[sha512], #48]\n\t"
+        "str	r9, [%[sha512], #52]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
+        "strd	r8, r9, [%[sha512], #48]\n\t"
 #endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #16]\n\t"
+        "str	r7, [%[sha512], #20]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[13] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #88]\n\t"
+        "ldr	r5, [sp, #92]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #88]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #104]\n\t"
+        "ldr	r5, [sp, #108]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #104]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #48]\n\t"
+        "ldr	r9, [sp, #52]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #104]\n\t"
+        "str	r5, [sp, #108]\n\t"
+#else
+        "strd	r4, r5, [sp, #104]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #112]\n\t"
+        "ldr	r5, [sp, #116]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #112]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #104]\n\t"
+        "ldr	r5, [sp, #108]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #104]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #104]\n\t"
+        "str	r5, [sp, #108]\n\t"
+#else
+        "strd	r4, r5, [sp, #104]\n\t"
+#endif
+        /* Round 14 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #8]\n\t"
         "ldr	r5, [%[sha512], #12]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512], #8]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #8]\n\t"
         "str	r5, [%[sha512], #12]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Calc new W[14] */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #96]\n\t"
-        "ldr	lr, [sp, #100]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #96]\n\t"
-#endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #112]\n\t"
-        "ldr	lr, [sp, #116]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #112]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #56]\n\t"
-        "ldr	r7, [sp, #60]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #56]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #112]\n\t"
-        "str	lr, [sp, #116]\n\t"
-#else
-        "strd	r12, lr, [sp, #112]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #120]\n\t"
-        "ldr	lr, [sp, #124]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #120]\n\t"
-#endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #112]\n\t"
-        "ldr	lr, [sp, #116]\n\t"
-#else
-        "ldrd	r12, lr, [sp, #112]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #112]\n\t"
-        "str	lr, [sp, #116]\n\t"
-#else
-        "strd	r12, lr, [sp, #112]\n\t"
-#endif
-        /* Round 15 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #48]\n\t"
@@ -4275,92 +4015,56 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #56]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #120]\n\t"
-        "ldr	r7, [sp, #124]\n\t"
+        "ldr	r8, [sp, #112]\n\t"
+        "ldr	r9, [sp, #116]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #120]\n\t"
+        "ldrd	r8, r9, [sp, #112]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #120]\n\t"
-        "ldr	r5, [r3, #124]\n\t"
+        "ldr	r6, [r3, #112]\n\t"
+        "ldr	r7, [r3, #116]\n\t"
 #else
-        "ldrd	r4, r5, [r3, #120]\n\t"
+        "ldrd	r6, r7, [r3, #112]\n\t"
 #endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
 #else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
 #else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #32]\n\t"
-        "str	r7, [%[sha512], #36]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+        "strd	r4, r5, [%[sha512], #8]\n\t"
 #endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #16]\n\t"
         "ldr	r5, [%[sha512], #20]\n\t"
@@ -4368,507 +4072,622 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "ldrd	r4, r5, [%[sha512], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
+        "str	r8, [%[sha512], #40]\n\t"
+        "str	r9, [%[sha512], #44]\n\t"
 #else
-        "strd	r12, lr, [%[sha512]]\n\t"
+        "strd	r8, r9, [%[sha512], #40]\n\t"
 #endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #8]\n\t"
+        "str	r7, [%[sha512], #12]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Calc new W[14] */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #96]\n\t"
+        "ldr	r5, [sp, #100]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #96]\n\t"
+#endif
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #112]\n\t"
+        "ldr	r5, [sp, #116]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #112]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #56]\n\t"
+        "ldr	r9, [sp, #60]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #56]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #112]\n\t"
+        "str	r5, [sp, #116]\n\t"
+#else
+        "strd	r4, r5, [sp, #112]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #120]\n\t"
+        "ldr	r5, [sp, #124]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #120]\n\t"
+#endif
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [sp, #112]\n\t"
+        "ldr	r5, [sp, #116]\n\t"
+#else
+        "ldrd	r4, r5, [sp, #112]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [sp, #112]\n\t"
+        "str	r5, [sp, #116]\n\t"
+#else
+        "strd	r4, r5, [sp, #112]\n\t"
+#endif
+        /* Round 15 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512]]\n\t"
         "ldr	r5, [%[sha512], #4]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512]]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512]]\n\t"
         "str	r5, [%[sha512], #4]\n\t"
 #else
         "strd	r4, r5, [%[sha512]]\n\t"
 #endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #120]\n\t"
+        "ldr	r9, [sp, #124]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #120]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #120]\n\t"
+        "ldr	r7, [r3, #124]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #120]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #32]\n\t"
+        "str	r9, [%[sha512], #36]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512]]\n\t"
+        "str	r7, [%[sha512], #4]\n\t"
+#else
+        "strd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
         /* Calc new W[15] */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #104]\n\t"
-        "ldr	lr, [sp, #108]\n\t"
+        "ldr	r4, [sp, #104]\n\t"
+        "ldr	r5, [sp, #108]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #104]\n\t"
+        "ldrd	r4, r5, [sp, #104]\n\t"
 #endif
-        "lsrs	r4, r12, #19\n\t"
-        "lsrs	r5, lr, #19\n\t"
-        "orr	r5, r5, r12, lsl #13\n\t"
-        "orr	r4, r4, lr, lsl #13\n\t"
-        "lsls	r6, r12, #3\n\t"
-        "lsls	r7, lr, #3\n\t"
-        "orr	r7, r7, r12, lsr #29\n\t"
-        "orr	r6, r6, lr, lsr #29\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #6\n\t"
-        "lsrs	r7, lr, #6\n\t"
-        "orr	r6, r6, lr, lsl #26\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
+        "lsrs	r6, r4, #19\n\t"
+        "lsrs	r7, r5, #19\n\t"
+        "orr	r7, r7, r4, lsl #13\n\t"
+        "orr	r6, r6, r5, lsl #13\n\t"
+        "lsls	r8, r4, #3\n\t"
+        "lsls	r9, r5, #3\n\t"
+        "orr	r9, r9, r4, lsr #29\n\t"
+        "orr	r8, r8, r5, lsr #29\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #6\n\t"
+        "lsrs	r9, r5, #6\n\t"
+        "orr	r8, r8, r5, lsl #26\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #120]\n\t"
-        "ldr	lr, [sp, #124]\n\t"
+        "ldr	r4, [sp, #120]\n\t"
+        "ldr	r5, [sp, #124]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #120]\n\t"
+        "ldrd	r4, r5, [sp, #120]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #64]\n\t"
-        "ldr	r7, [sp, #68]\n\t"
+        "ldr	r8, [sp, #64]\n\t"
+        "ldr	r9, [sp, #68]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #64]\n\t"
+        "ldrd	r8, r9, [sp, #64]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #120]\n\t"
-        "str	lr, [sp, #124]\n\t"
+        "str	r4, [sp, #120]\n\t"
+        "str	r5, [sp, #124]\n\t"
 #else
-        "strd	r12, lr, [sp, #120]\n\t"
+        "strd	r4, r5, [sp, #120]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp]\n\t"
-        "ldr	lr, [sp, #4]\n\t"
+        "ldr	r4, [sp]\n\t"
+        "ldr	r5, [sp, #4]\n\t"
 #else
-        "ldrd	r12, lr, [sp]\n\t"
+        "ldrd	r4, r5, [sp]\n\t"
 #endif
-        "lsrs	r4, r12, #1\n\t"
-        "lsrs	r5, lr, #1\n\t"
-        "orr	r5, r5, r12, lsl #31\n\t"
-        "orr	r4, r4, lr, lsl #31\n\t"
-        "lsrs	r6, r12, #8\n\t"
-        "lsrs	r7, lr, #8\n\t"
-        "orr	r7, r7, r12, lsl #24\n\t"
-        "orr	r6, r6, lr, lsl #24\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
-        "lsrs	r6, r12, #7\n\t"
-        "lsrs	r7, lr, #7\n\t"
-        "orr	r6, r6, lr, lsl #25\n\t"
-        "eor	r5, r5, r7\n\t"
-        "eor	r4, r4, r6\n\t"
+        "lsrs	r6, r4, #1\n\t"
+        "lsrs	r7, r5, #1\n\t"
+        "orr	r7, r7, r4, lsl #31\n\t"
+        "orr	r6, r6, r5, lsl #31\n\t"
+        "lsrs	r8, r4, #8\n\t"
+        "lsrs	r9, r5, #8\n\t"
+        "orr	r9, r9, r4, lsl #24\n\t"
+        "orr	r8, r8, r5, lsl #24\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "lsrs	r8, r4, #7\n\t"
+        "lsrs	r9, r5, #7\n\t"
+        "orr	r8, r8, r5, lsl #25\n\t"
+        "eor	r7, r7, r9\n\t"
+        "eor	r6, r6, r8\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [sp, #120]\n\t"
-        "ldr	lr, [sp, #124]\n\t"
+        "ldr	r4, [sp, #120]\n\t"
+        "ldr	r5, [sp, #124]\n\t"
 #else
-        "ldrd	r12, lr, [sp, #120]\n\t"
+        "ldrd	r4, r5, [sp, #120]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #120]\n\t"
-        "str	lr, [sp, #124]\n\t"
+        "str	r4, [sp, #120]\n\t"
+        "str	r5, [sp, #124]\n\t"
 #else
-        "strd	r12, lr, [sp, #120]\n\t"
+        "strd	r4, r5, [sp, #120]\n\t"
 #endif
         "add	r3, r3, #0x80\n\t"
-        "subs	r10, r10, #1\n\t"
+        "subs	r12, r12, #1\n\t"
         "bne	L_SHA512_transform_len_start_%=\n\t"
         /* Round 0 */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
 #endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp]\n\t"
-        "ldr	r7, [sp, #4]\n\t"
-#else
-        "ldrd	r6, r7, [sp]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3]\n\t"
-        "ldr	r5, [r3, #4]\n\t"
-#else
-        "ldrd	r4, r5, [r3]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #24]\n\t"
-        "str	r7, [%[sha512], #28]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #56]\n\t"
         "ldr	r5, [%[sha512], #60]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512], #56]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #56]\n\t"
         "str	r5, [%[sha512], #60]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #56]\n\t"
 #endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp]\n\t"
+        "ldr	r9, [sp, #4]\n\t"
+#else
+        "ldrd	r8, r9, [sp]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3]\n\t"
+        "ldr	r7, [r3, #4]\n\t"
+#else
+        "ldrd	r6, r7, [r3]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #24]\n\t"
+        "str	r9, [%[sha512], #28]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #56]\n\t"
+        "str	r7, [%[sha512], #60]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
         /* Round 1 */
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
 #endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #8]\n\t"
-        "ldr	r7, [sp, #12]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #8]\n\t"
-        "ldr	r5, [r3, #12]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #8]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #16]\n\t"
-        "str	r7, [%[sha512], #20]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #48]\n\t"
         "ldr	r5, [%[sha512], #52]\n\t"
 #else
         "ldrd	r4, r5, [%[sha512], #48]\n\t"
 #endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #48]\n\t"
         "str	r5, [%[sha512], #52]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 2 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #24]\n\t"
@@ -4882,55 +4701,2616 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #32]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #16]\n\t"
-        "ldr	r7, [sp, #20]\n\t"
+        "ldr	r8, [sp, #8]\n\t"
+        "ldr	r9, [sp, #12]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #16]\n\t"
+        "ldrd	r8, r9, [sp, #8]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #16]\n\t"
-        "ldr	r5, [r3, #20]\n\t"
+        "ldr	r6, [r3, #8]\n\t"
+        "ldr	r7, [r3, #12]\n\t"
 #else
-        "ldrd	r4, r5, [r3, #16]\n\t"
+        "ldrd	r6, r7, [r3, #8]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #16]\n\t"
+        "str	r9, [%[sha512], #20]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #48]\n\t"
+        "str	r7, [%[sha512], #52]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 2 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #16]\n\t"
+        "ldr	r9, [sp, #20]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #16]\n\t"
+        "ldr	r7, [r3, #20]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #16]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #8]\n\t"
+        "str	r9, [%[sha512], #12]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #40]\n\t"
+        "str	r7, [%[sha512], #44]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 3 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #24]\n\t"
+        "ldr	r9, [sp, #28]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #24]\n\t"
+        "ldr	r7, [r3, #28]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #24]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512]]\n\t"
+        "str	r9, [%[sha512], #4]\n\t"
+#else
+        "strd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #32]\n\t"
+        "str	r7, [%[sha512], #36]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 4 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
 #endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r6, [%[sha512], #8]\n\t"
         "ldr	r7, [%[sha512], #12]\n\t"
 #else
         "ldrd	r6, r7, [%[sha512], #8]\n\t"
 #endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
 #else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
 #endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #32]\n\t"
+        "ldr	r9, [sp, #36]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #32]\n\t"
+        "ldr	r7, [r3, #36]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #32]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #56]\n\t"
+        "str	r9, [%[sha512], #60]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #24]\n\t"
+        "str	r7, [%[sha512], #28]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 5 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #40]\n\t"
+        "ldr	r9, [sp, #44]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #40]\n\t"
+        "ldr	r7, [r3, #44]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #40]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #48]\n\t"
+        "str	r9, [%[sha512], #52]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #16]\n\t"
+        "str	r7, [%[sha512], #20]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 6 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #48]\n\t"
+        "ldr	r9, [sp, #52]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #48]\n\t"
+        "ldr	r7, [r3, #52]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #48]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #40]\n\t"
+        "str	r9, [%[sha512], #44]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #8]\n\t"
+        "str	r7, [%[sha512], #12]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 7 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #56]\n\t"
+        "ldr	r9, [sp, #60]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #56]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #56]\n\t"
+        "ldr	r7, [r3, #60]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #56]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #32]\n\t"
+        "str	r9, [%[sha512], #36]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512]]\n\t"
+        "str	r7, [%[sha512], #4]\n\t"
+#else
+        "strd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 8 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #64]\n\t"
+        "ldr	r9, [sp, #68]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #64]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #64]\n\t"
+        "ldr	r7, [r3, #68]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #64]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #24]\n\t"
+        "str	r9, [%[sha512], #28]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #56]\n\t"
+        "str	r5, [%[sha512], #60]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #56]\n\t"
+        "str	r7, [%[sha512], #60]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 9 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #72]\n\t"
+        "ldr	r9, [sp, #76]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #72]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #72]\n\t"
+        "ldr	r7, [r3, #76]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #72]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #16]\n\t"
+        "str	r9, [%[sha512], #20]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #48]\n\t"
+        "str	r7, [%[sha512], #52]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 10 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #80]\n\t"
+        "ldr	r9, [sp, #84]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #80]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #80]\n\t"
+        "ldr	r7, [r3, #84]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #80]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #8]\n\t"
+        "str	r9, [%[sha512], #12]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #40]\n\t"
+        "str	r5, [%[sha512], #44]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #40]\n\t"
+        "str	r7, [%[sha512], #44]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 11 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #88]\n\t"
+        "ldr	r9, [sp, #92]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #88]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #88]\n\t"
+        "ldr	r7, [r3, #92]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #88]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512]]\n\t"
+        "str	r9, [%[sha512], #4]\n\t"
+#else
+        "strd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #32]\n\t"
+        "str	r5, [%[sha512], #36]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #32]\n\t"
+        "str	r7, [%[sha512], #36]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 12 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #96]\n\t"
+        "ldr	r9, [sp, #100]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #96]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #96]\n\t"
+        "ldr	r7, [r3, #100]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #96]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #32]\n\t"
+        "ldr	r5, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #56]\n\t"
+        "str	r9, [%[sha512], #60]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #40]\n\t"
+        "ldr	r7, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #24]\n\t"
+        "str	r5, [%[sha512], #28]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #24]\n\t"
+        "str	r7, [%[sha512], #28]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 13 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #56]\n\t"
+        "ldr	r5, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #104]\n\t"
+        "ldr	r9, [sp, #108]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #104]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #104]\n\t"
+        "ldr	r7, [r3, #108]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #104]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #48]\n\t"
+        "ldr	r9, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #24]\n\t"
+        "ldr	r5, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #48]\n\t"
+        "str	r9, [%[sha512], #52]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #24]\n\t"
+        "ldr	r9, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #32]\n\t"
+        "ldr	r7, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #32]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #16]\n\t"
+        "str	r5, [%[sha512], #20]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #16]\n\t"
+        "str	r7, [%[sha512], #20]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 14 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #48]\n\t"
+        "ldr	r5, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #56]\n\t"
+        "ldr	r7, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #56]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512]]\n\t"
+        "ldr	r9, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #112]\n\t"
+        "ldr	r9, [sp, #116]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #112]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #112]\n\t"
+        "ldr	r7, [r3, #116]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #112]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #40]\n\t"
+        "ldr	r9, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #16]\n\t"
+        "ldr	r5, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #40]\n\t"
+        "str	r9, [%[sha512], #44]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #16]\n\t"
+        "ldr	r9, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #24]\n\t"
+        "ldr	r7, [%[sha512], #28]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #24]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512], #8]\n\t"
+        "str	r5, [%[sha512], #12]\n\t"
+#else
+        "strd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512], #8]\n\t"
+        "str	r7, [%[sha512], #12]\n\t"
+#else
+        "strd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Round 15 */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+        "lsrs	r6, r4, #14\n\t"
+        "lsrs	r7, r5, #14\n\t"
+        "orr	r7, r7, r4, lsl #18\n\t"
+        "orr	r6, r6, r5, lsl #18\n\t"
+        "lsrs	r8, r4, #18\n\t"
+        "lsrs	r9, r5, #18\n\t"
+        "orr	r9, r9, r4, lsl #14\n\t"
+        "orr	r8, r8, r5, lsl #14\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #23\n\t"
+        "lsls	r9, r5, #23\n\t"
+        "orr	r9, r9, r4, lsr #9\n\t"
+        "orr	r8, r8, r5, lsr #9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #40]\n\t"
+        "ldr	r5, [%[sha512], #44]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #40]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #48]\n\t"
+        "ldr	r7, [%[sha512], #52]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #56]\n\t"
+        "ldr	r9, [%[sha512], #60]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #56]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "and	r6, r6, r4\n\t"
+        "and	r7, r7, r5\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #120]\n\t"
+        "ldr	r9, [sp, #124]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #120]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [r3, #120]\n\t"
+        "ldr	r7, [r3, #124]\n\t"
+#else
+        "ldrd	r6, r7, [r3, #120]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #32]\n\t"
+        "ldr	r9, [%[sha512], #36]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "adds	r8, r8, r4\n\t"
+        "adc	r9, r9, r5\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512], #8]\n\t"
+        "ldr	r5, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r8, [%[sha512], #32]\n\t"
+        "str	r9, [%[sha512], #36]\n\t"
+#else
+        "strd	r8, r9, [%[sha512], #32]\n\t"
+#endif
+        "lsrs	r6, r4, #28\n\t"
+        "lsrs	r7, r5, #28\n\t"
+        "orr	r7, r7, r4, lsl #4\n\t"
+        "orr	r6, r6, r5, lsl #4\n\t"
+        "lsls	r8, r4, #30\n\t"
+        "lsls	r9, r5, #30\n\t"
+        "orr	r9, r9, r4, lsr #2\n\t"
+        "orr	r8, r8, r5, lsr #2\n\t"
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "lsls	r8, r4, #25\n\t"
+        "lsls	r9, r5, #25\n\t"
+        "orr	r9, r9, r4, lsr #7\n\t"
+        "orr	r8, r8, r5, lsr #7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r6, r6, r8\n\t"
+        "eor	r7, r7, r9\n\t"
+        "adds	r4, r4, r6\n\t"
+        "adc	r5, r5, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [%[sha512], #8]\n\t"
+        "ldr	r9, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r8, r9, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #16]\n\t"
+        "ldr	r7, [%[sha512], #20]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
+#endif
+        "eor	r8, r8, r6\n\t"
+        "eor	r9, r9, r7\n\t"
+        "and	r10, r10, r8\n\t"
+        "and	r11, r11, r9\n\t"
+        "eor	r10, r10, r6\n\t"
+        "eor	r11, r11, r7\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512]]\n\t"
+        "ldr	r7, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r6, [%[sha512]]\n\t"
+        "str	r7, [%[sha512], #4]\n\t"
+#else
+        "strd	r6, r7, [%[sha512]]\n\t"
+#endif
+        "mov	r10, r8\n\t"
+        "mov	r11, r9\n\t"
+        /* Add in digest from start */
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r4, [%[sha512]]\n\t"
+        "ldr	r5, [%[sha512], #4]\n\t"
+#else
+        "ldrd	r4, r5, [%[sha512]]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r6, [%[sha512], #8]\n\t"
+        "ldr	r7, [%[sha512], #12]\n\t"
+#else
+        "ldrd	r6, r7, [%[sha512], #8]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r8, [sp, #128]\n\t"
+        "ldr	r9, [sp, #132]\n\t"
+#else
+        "ldrd	r8, r9, [sp, #128]\n\t"
+#endif
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "ldr	r10, [sp, #136]\n\t"
+        "ldr	r11, [sp, #140]\n\t"
+#else
+        "ldrd	r10, r11, [sp, #136]\n\t"
+#endif
+        "adds	r4, r4, r8\n\t"
+        "adc	r5, r5, r9\n\t"
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
+#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
+        "str	r4, [%[sha512]]\n\t"
+        "str	r5, [%[sha512], #4]\n\t"
+#else
+        "strd	r4, r5, [%[sha512]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [%[sha512], #8]\n\t"
@@ -4938,112 +7318,17 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "strd	r6, r7, [%[sha512], #8]\n\t"
 #endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
+        "str	r4, [sp, #128]\n\t"
+        "str	r5, [sp, #132]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
+        "strd	r4, r5, [sp, #128]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
+        "str	r6, [sp, #136]\n\t"
+        "str	r7, [sp, #140]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #40]\n\t"
-        "str	r5, [%[sha512], #44]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 3 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
+        "strd	r6, r7, [sp, #136]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #16]\n\t"
@@ -5057,930 +7342,27 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #24]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
+        "ldr	r8, [sp, #144]\n\t"
+        "ldr	r9, [sp, #148]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
+        "ldrd	r8, r9, [sp, #144]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #24]\n\t"
-        "ldr	r7, [sp, #28]\n\t"
+        "ldr	r10, [sp, #152]\n\t"
+        "ldr	r11, [sp, #156]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #24]\n\t"
-        "ldr	r5, [r3, #28]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #24]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512]]\n\t"
-        "str	r7, [%[sha512], #4]\n\t"
-#else
-        "strd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #32]\n\t"
-        "str	r5, [%[sha512], #36]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 4 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #32]\n\t"
-        "ldr	r7, [sp, #36]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #32]\n\t"
-        "ldr	r5, [r3, #36]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #32]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #56]\n\t"
-        "str	r7, [%[sha512], #60]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #24]\n\t"
-        "str	r5, [%[sha512], #28]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 5 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #40]\n\t"
-        "ldr	r7, [sp, #44]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #40]\n\t"
-        "ldr	r5, [r3, #44]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #40]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #48]\n\t"
-        "str	r7, [%[sha512], #52]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
+        "ldrd	r10, r11, [sp, #152]\n\t"
 #endif
         "adds	r4, r4, r8\n\t"
         "adc	r5, r5, r9\n\t"
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #16]\n\t"
         "str	r5, [%[sha512], #20]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 6 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #48]\n\t"
-        "ldr	r7, [sp, #52]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #48]\n\t"
-        "ldr	r5, [r3, #52]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #48]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #40]\n\t"
-        "str	r7, [%[sha512], #44]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #8]\n\t"
-        "str	r5, [%[sha512], #12]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 7 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #56]\n\t"
-        "ldr	r7, [sp, #60]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #56]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #56]\n\t"
-        "ldr	r5, [r3, #60]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #56]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #32]\n\t"
-        "str	r7, [%[sha512], #36]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512]]\n\t"
-        "str	r5, [%[sha512], #4]\n\t"
-#else
-        "strd	r4, r5, [%[sha512]]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 8 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #64]\n\t"
-        "ldr	r7, [sp, #68]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #64]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #64]\n\t"
-        "ldr	r5, [r3, #68]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #64]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [%[sha512], #24]\n\t"
@@ -5988,112 +7370,17 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "strd	r6, r7, [%[sha512], #24]\n\t"
 #endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
+        "str	r4, [sp, #144]\n\t"
+        "str	r5, [sp, #148]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
+        "strd	r4, r5, [sp, #144]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
+        "str	r6, [sp, #152]\n\t"
+        "str	r7, [sp, #156]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #56]\n\t"
-        "str	lr, [%[sha512], #60]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #56]\n\t"
-        "str	r5, [%[sha512], #60]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 9 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
+        "strd	r6, r7, [sp, #152]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #32]\n\t"
@@ -6107,930 +7394,27 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #40]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
+        "ldr	r8, [sp, #160]\n\t"
+        "ldr	r9, [sp, #164]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
+        "ldrd	r8, r9, [sp, #160]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #72]\n\t"
-        "ldr	r7, [sp, #76]\n\t"
+        "ldr	r10, [sp, #168]\n\t"
+        "ldr	r11, [sp, #172]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #72]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #72]\n\t"
-        "ldr	r5, [r3, #76]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #72]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #16]\n\t"
-        "str	r7, [%[sha512], #20]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #48]\n\t"
-        "str	r5, [%[sha512], #52]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 10 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #80]\n\t"
-        "ldr	r7, [sp, #84]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #80]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #80]\n\t"
-        "ldr	r5, [r3, #84]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #80]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #8]\n\t"
-        "str	r7, [%[sha512], #12]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #40]\n\t"
-        "str	lr, [%[sha512], #44]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #40]\n\t"
-        "str	r5, [%[sha512], #44]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 11 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #88]\n\t"
-        "ldr	r7, [sp, #92]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #88]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #88]\n\t"
-        "ldr	r5, [r3, #92]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #88]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512]]\n\t"
-        "str	r7, [%[sha512], #4]\n\t"
-#else
-        "strd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #48]\n\t"
-        "ldr	r5, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
+        "ldrd	r10, r11, [sp, #168]\n\t"
 #endif
         "adds	r4, r4, r8\n\t"
         "adc	r5, r5, r9\n\t"
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r4, [%[sha512], #32]\n\t"
         "str	r5, [%[sha512], #36]\n\t"
 #else
         "strd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 12 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #96]\n\t"
-        "ldr	r7, [sp, #100]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #96]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #96]\n\t"
-        "ldr	r5, [r3, #100]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #96]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #56]\n\t"
-        "ldr	r7, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #56]\n\t"
-        "str	r7, [%[sha512], #60]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #24]\n\t"
-        "str	lr, [%[sha512], #28]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #24]\n\t"
-        "str	r5, [%[sha512], #28]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 13 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #56]\n\t"
-        "ldr	lr, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #104]\n\t"
-        "ldr	r7, [sp, #108]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #104]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #104]\n\t"
-        "ldr	r5, [r3, #108]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #104]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #48]\n\t"
-        "ldr	r7, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #24]\n\t"
-        "ldr	lr, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #48]\n\t"
-        "str	r7, [%[sha512], #52]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #24]\n\t"
-        "ldr	r7, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #32]\n\t"
-        "ldr	r5, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #16]\n\t"
-        "str	r5, [%[sha512], #20]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 14 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512]]\n\t"
-        "ldr	r7, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #112]\n\t"
-        "ldr	r7, [sp, #116]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #112]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #112]\n\t"
-        "ldr	r5, [r3, #116]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #112]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #40]\n\t"
-        "ldr	r7, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #40]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "str	r6, [%[sha512], #40]\n\t"
@@ -7038,112 +7422,17 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "strd	r6, r7, [%[sha512], #40]\n\t"
 #endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
+        "str	r4, [sp, #160]\n\t"
+        "str	r5, [sp, #164]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #16]\n\t"
-        "ldr	r7, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #16]\n\t"
+        "strd	r4, r5, [sp, #160]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
+        "str	r6, [sp, #168]\n\t"
+        "str	r7, [sp, #172]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #8]\n\t"
-        "str	lr, [%[sha512], #12]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #8]\n\t"
-        "str	r5, [%[sha512], #12]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Round 15 */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
-#endif
-        "lsrs	r4, r12, #14\n\t"
-        "lsrs	r5, lr, #14\n\t"
-        "orr	r5, r5, r12, lsl #18\n\t"
-        "orr	r4, r4, lr, lsl #18\n\t"
-        "lsrs	r6, r12, #18\n\t"
-        "lsrs	r7, lr, #18\n\t"
-        "orr	r7, r7, r12, lsl #14\n\t"
-        "orr	r6, r6, lr, lsl #14\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #23\n\t"
-        "lsls	r7, lr, #23\n\t"
-        "orr	r7, r7, r12, lsr #9\n\t"
-        "orr	r6, r6, lr, lsr #9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #40]\n\t"
-        "ldr	lr, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #40]\n\t"
+        "strd	r6, r7, [sp, #168]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
         "ldr	r4, [%[sha512], #48]\n\t"
@@ -7157,334 +7446,45 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
 #else
         "ldrd	r6, r7, [%[sha512], #56]\n\t"
 #endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "and	r4, r4, r12\n\t"
-        "and	r5, r5, lr\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
+        "ldr	r8, [sp, #176]\n\t"
+        "ldr	r9, [sp, #180]\n\t"
 #else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
+        "ldrd	r8, r9, [sp, #176]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #120]\n\t"
-        "ldr	r7, [sp, #124]\n\t"
+        "ldr	r10, [sp, #184]\n\t"
+        "ldr	r11, [sp, #188]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #120]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [r3, #120]\n\t"
-        "ldr	r5, [r3, #124]\n\t"
-#else
-        "ldrd	r4, r5, [r3, #120]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #32]\n\t"
-        "ldr	r7, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "adds	r6, r6, r12\n\t"
-        "adc	r7, r7, lr\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #8]\n\t"
-        "ldr	lr, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r6, [%[sha512], #32]\n\t"
-        "str	r7, [%[sha512], #36]\n\t"
-#else
-        "strd	r6, r7, [%[sha512], #32]\n\t"
-#endif
-        "lsrs	r4, r12, #28\n\t"
-        "lsrs	r5, lr, #28\n\t"
-        "orr	r5, r5, r12, lsl #4\n\t"
-        "orr	r4, r4, lr, lsl #4\n\t"
-        "lsls	r6, r12, #30\n\t"
-        "lsls	r7, lr, #30\n\t"
-        "orr	r7, r7, r12, lsr #2\n\t"
-        "orr	r6, r6, lr, lsr #2\n\t"
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "lsls	r6, r12, #25\n\t"
-        "lsls	r7, lr, #25\n\t"
-        "orr	r7, r7, r12, lsr #7\n\t"
-        "orr	r6, r6, lr, lsr #7\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r4, r4, r6\n\t"
-        "eor	r5, r5, r7\n\t"
-        "adds	r12, r12, r4\n\t"
-        "adc	lr, lr, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [%[sha512], #8]\n\t"
-        "ldr	r7, [%[sha512], #12]\n\t"
-#else
-        "ldrd	r6, r7, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #16]\n\t"
-        "ldr	r5, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-        "eor	r6, r6, r4\n\t"
-        "eor	r7, r7, r5\n\t"
-        "and	r8, r8, r6\n\t"
-        "and	r9, r9, r7\n\t"
-        "eor	r8, r8, r4\n\t"
-        "eor	r9, r9, r5\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512]]\n\t"
-        "ldr	r5, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512]]\n\t"
+        "ldrd	r10, r11, [sp, #184]\n\t"
 #endif
         "adds	r4, r4, r8\n\t"
         "adc	r5, r5, r9\n\t"
+        "adds	r6, r6, r10\n\t"
+        "adc	r7, r7, r11\n\t"
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512]]\n\t"
-        "str	r5, [%[sha512], #4]\n\t"
+        "str	r4, [%[sha512], #48]\n\t"
+        "str	r5, [%[sha512], #52]\n\t"
 #else
-        "strd	r4, r5, [%[sha512]]\n\t"
-#endif
-        "mov	r8, r6\n\t"
-        "mov	r9, r7\n\t"
-        /* Add in digest from start */
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512]]\n\t"
-        "ldr	lr, [%[sha512], #4]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512]]\n\t"
+        "strd	r4, r5, [%[sha512], #48]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #8]\n\t"
-        "ldr	r5, [%[sha512], #12]\n\t"
+        "str	r6, [%[sha512], #56]\n\t"
+        "str	r7, [%[sha512], #60]\n\t"
 #else
-        "ldrd	r4, r5, [%[sha512], #8]\n\t"
+        "strd	r6, r7, [%[sha512], #56]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #128]\n\t"
-        "ldr	r7, [sp, #132]\n\t"
+        "str	r4, [sp, #176]\n\t"
+        "str	r5, [sp, #180]\n\t"
 #else
-        "ldrd	r6, r7, [sp, #128]\n\t"
+        "strd	r4, r5, [sp, #176]\n\t"
 #endif
 #if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [sp, #136]\n\t"
-        "ldr	r9, [sp, #140]\n\t"
+        "str	r6, [sp, #184]\n\t"
+        "str	r7, [sp, #188]\n\t"
 #else
-        "ldrd	r8, r9, [sp, #136]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512]]\n\t"
-        "str	lr, [%[sha512], #4]\n\t"
-#else
-        "strd	r12, lr, [%[sha512]]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #8]\n\t"
-        "str	r5, [%[sha512], #12]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #8]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #128]\n\t"
-        "str	lr, [sp, #132]\n\t"
-#else
-        "strd	r12, lr, [sp, #128]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #136]\n\t"
-        "str	r5, [sp, #140]\n\t"
-#else
-        "strd	r4, r5, [sp, #136]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #16]\n\t"
-        "ldr	lr, [%[sha512], #20]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #24]\n\t"
-        "ldr	r5, [%[sha512], #28]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #144]\n\t"
-        "ldr	r7, [sp, #148]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #144]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [sp, #152]\n\t"
-        "ldr	r9, [sp, #156]\n\t"
-#else
-        "ldrd	r8, r9, [sp, #152]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #16]\n\t"
-        "str	lr, [%[sha512], #20]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #16]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #24]\n\t"
-        "str	r5, [%[sha512], #28]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #24]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #144]\n\t"
-        "str	lr, [sp, #148]\n\t"
-#else
-        "strd	r12, lr, [sp, #144]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #152]\n\t"
-        "str	r5, [sp, #156]\n\t"
-#else
-        "strd	r4, r5, [sp, #152]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #32]\n\t"
-        "ldr	lr, [%[sha512], #36]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #40]\n\t"
-        "ldr	r5, [%[sha512], #44]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #160]\n\t"
-        "ldr	r7, [sp, #164]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #160]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [sp, #168]\n\t"
-        "ldr	r9, [sp, #172]\n\t"
-#else
-        "ldrd	r8, r9, [sp, #168]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #32]\n\t"
-        "str	lr, [%[sha512], #36]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #32]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #40]\n\t"
-        "str	r5, [%[sha512], #44]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #40]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #160]\n\t"
-        "str	lr, [sp, #164]\n\t"
-#else
-        "strd	r12, lr, [sp, #160]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #168]\n\t"
-        "str	r5, [sp, #172]\n\t"
-#else
-        "strd	r4, r5, [sp, #168]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r12, [%[sha512], #48]\n\t"
-        "ldr	lr, [%[sha512], #52]\n\t"
-#else
-        "ldrd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r4, [%[sha512], #56]\n\t"
-        "ldr	r5, [%[sha512], #60]\n\t"
-#else
-        "ldrd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r6, [sp, #176]\n\t"
-        "ldr	r7, [sp, #180]\n\t"
-#else
-        "ldrd	r6, r7, [sp, #176]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "ldr	r8, [sp, #184]\n\t"
-        "ldr	r9, [sp, #188]\n\t"
-#else
-        "ldrd	r8, r9, [sp, #184]\n\t"
-#endif
-        "adds	r12, r12, r6\n\t"
-        "adc	lr, lr, r7\n\t"
-        "adds	r4, r4, r8\n\t"
-        "adc	r5, r5, r9\n\t"
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [%[sha512], #48]\n\t"
-        "str	lr, [%[sha512], #52]\n\t"
-#else
-        "strd	r12, lr, [%[sha512], #48]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [%[sha512], #56]\n\t"
-        "str	r5, [%[sha512], #60]\n\t"
-#else
-        "strd	r4, r5, [%[sha512], #56]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r12, [sp, #176]\n\t"
-        "str	lr, [sp, #180]\n\t"
-#else
-        "strd	r12, lr, [sp, #176]\n\t"
-#endif
-#if defined(WOLFSSL_SP_ARM_ARCH) && (WOLFSSL_SP_ARM_ARCH < 7)
-        "str	r4, [sp, #184]\n\t"
-        "str	r5, [sp, #188]\n\t"
-#else
-        "strd	r4, r5, [sp, #184]\n\t"
+        "strd	r6, r7, [sp, #184]\n\t"
 #endif
         "subs	%[len], %[len], #0x80\n\t"
         "sub	r3, r3, #0x200\n\t"
@@ -7494,7 +7494,7 @@ void Transform_Sha512_Len(wc_Sha512* sha512_p, const byte* data_p, word32 len_p)
         "add	sp, sp, #0xc0\n\t"
         : [sha512] "+r" (sha512), [data] "+r" (data), [len] "+r" (len)
         : [L_SHA512_transform_len_k] "r" (L_SHA512_transform_len_k)
-        : "memory", "r3", "r12", "lr", "r4", "r5", "r6", "r7", "r8", "r9", "r10"
+        : "memory", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12"
     );
 }
 
diff --git a/wolfcrypt/src/port/arm/armv8-aes.c b/wolfcrypt/src/port/arm/armv8-aes.c
index 49e78606f..c90bdab76 100644
--- a/wolfcrypt/src/port/arm/armv8-aes.c
+++ b/wolfcrypt/src/port/arm/armv8-aes.c
@@ -32,8 +32,8 @@
 
 #include <wolfssl/wolfcrypt/settings.h>
 
-#if !defined(NO_AES) && defined(WOLFSSL_ARMASM) && \
-    !defined(WOLFSSL_ARMASM_NO_HW_CRYPTO)
+#if !defined(NO_AES) && defined(WOLFSSL_ARMASM)
+#ifndef WOLFSSL_ARMASM_NO_HW_CRYPTO
 
 #ifdef HAVE_FIPS
 #undef HAVE_FIPS
@@ -5458,4 +5458,847 @@ int wc_AesGcmSetKey(Aes* aes, const byte* key, word32 len)
         }
     #endif /* HAVE_AES_DECRYPT */
 #endif /* WOLFSSL_AES_DIRECT */
+#else
+#include <wolfssl/wolfcrypt/logging.h>
+#include <wolfssl/wolfcrypt/error-crypt.h>
+#include <wolfssl/wolfcrypt/aes.h>
+#ifdef NO_INLINE
+    #include <wolfssl/wolfcrypt/misc.h>
+#else
+    #define WOLFSSL_MISC_INCLUDED
+    #include <wolfcrypt/src/misc.c>
+#endif
+
+extern void AES_set_encrypt_key(const unsigned char* key, word32 len,
+    unsigned char* ks);
+extern void AES_invert_key(unsigned char* ks, word32 rounds);
+extern void AES_ECB_encrypt(const unsigned char* in, unsigned char* out,
+    unsigned long len, const unsigned char* ks, int nr);
+extern void AES_ECB_decrypt(const unsigned char* in, unsigned char* out,
+    unsigned long len, const unsigned char* ks, int nr);
+extern void AES_CBC_encrypt(const unsigned char* in, unsigned char* out,
+    unsigned long len, const unsigned char* ks, int nr, unsigned char* iv);
+extern void AES_CBC_decrypt(const unsigned char* in, unsigned char* out,
+    unsigned long len, const unsigned char* ks, int nr, unsigned char* iv);
+extern void AES_CTR_encrypt(const unsigned char* in, unsigned char* out,
+    unsigned long len, const unsigned char* ks, int nr, unsigned char* ctr);
+extern void GCM_gmult_len(byte* x, const byte m[32][AES_BLOCK_SIZE],
+    const unsigned char* data, unsigned long len);
+extern void AES_GCM_encrypt(const unsigned char* in, unsigned char* out,
+    unsigned long len, const unsigned char* ks, int nr, unsigned char* ctr);
+
+int wc_AesSetKey(Aes* aes, const byte* userKey, word32 keylen,
+            const byte* iv, int dir)
+{
+#if defined(AES_MAX_KEY_SIZE)
+    const word32 max_key_len = (AES_MAX_KEY_SIZE / 8);
+#endif
+
+    if (((keylen != 16) && (keylen != 24) && (keylen != 32)) ||
+           (aes == NULL) || (userKey == NULL)) {
+        return BAD_FUNC_ARG;
+    }
+
+#if defined(AES_MAX_KEY_SIZE)
+    /* Check key length */
+    if (keylen > max_key_len) {
+        return BAD_FUNC_ARG;
+    }
+#endif
+
+#ifdef WOLFSSL_AES_COUNTER
+    aes->left = 0;
+#endif /* WOLFSSL_AES_COUNTER */
+
+    aes->keylen = keylen;
+    aes->rounds = keylen/4 + 6;
+
+    AES_set_encrypt_key(userKey, keylen * 8, (byte*)aes->key);
+#ifdef HAVE_AES_DECRYPT
+    if (dir == AES_DECRYPTION) {
+        AES_invert_key((byte*)aes->key, aes->rounds);
+    }
+#else
+    (void)dir;
+#endif
+
+    return wc_AesSetIV(aes, iv);
+}
+
+#if defined(WOLFSSL_AES_DIRECT) || defined(WOLFSSL_AES_COUNTER)
+int wc_AesSetKeyDirect(Aes* aes, const byte* userKey, word32 keylen,
+    const byte* iv, int dir)
+{
+    return wc_AesSetKey(aes, userKey, keylen, iv, dir);
+}
+#endif
+
+/* wc_AesSetIV is shared between software and hardware */
+int wc_AesSetIV(Aes* aes, const byte* iv)
+{
+    if (aes == NULL)
+        return BAD_FUNC_ARG;
+
+    if (iv)
+        XMEMCPY(aes->reg, iv, AES_BLOCK_SIZE);
+    else
+        XMEMSET(aes->reg,  0, AES_BLOCK_SIZE);
+
+    return 0;
+}
+
+#if defined(HAVE_AESCCM) || defined(WOLFSSL_AES_DIRECT)
+static int wc_AesEncrypt(Aes* aes, const byte* inBlock, byte* outBlock)
+{
+    if (aes->rounds != 10 && aes->rounds != 12 && aes->rounds != 14) {
+        WOLFSSL_ERROR_VERBOSE(KEYUSAGE_E);
+        return KEYUSAGE_E;
+    }
+
+    AES_ECB_encrypt(inBlock, outBlock, AES_BLOCK_SIZE,
+        (const unsigned char*)aes->key, aes->rounds);
+    return 0;
+}
+#endif
+
+#if defined(HAVE_AES_DECRYPT) && defined(WOLFSSL_AES_DIRECT)
+static int wc_AesDecrypt(Aes* aes, const byte* inBlock, byte* outBlock)
+{
+    if (aes->rounds != 10 && aes->rounds != 12 && aes->rounds != 14) {
+        WOLFSSL_ERROR_VERBOSE(KEYUSAGE_E);
+        return KEYUSAGE_E;
+    }
+
+    AES_ECB_decrypt(inBlock, outBlock, AES_BLOCK_SIZE,
+        (const unsigned char*)aes->key, aes->rounds);
+    return 0;
+}
+#endif
+
+/* AES-DIRECT */
+#if defined(WOLFSSL_AES_DIRECT)
+/* Allow direct access to one block encrypt */
+int wc_AesEncryptDirect(Aes* aes, byte* out, const byte* in)
+{
+    if (aes == NULL || out == NULL || in == NULL) {
+        WOLFSSL_MSG("Invalid input to wc_AesEncryptDirect");
+        return BAD_FUNC_ARG;
+    }
+    return wc_AesEncrypt(aes, in, out);
+}
+
+#ifdef HAVE_AES_DECRYPT
+/* Allow direct access to one block decrypt */
+int wc_AesDecryptDirect(Aes* aes, byte* out, const byte* in)
+{
+    if (aes == NULL || out == NULL || in == NULL) {
+        WOLFSSL_MSG("Invalid input to wc_AesDecryptDirect");
+        return BAD_FUNC_ARG;
+    }
+    return wc_AesDecrypt(aes, in, out);
+}
+#endif /* HAVE_AES_DECRYPT */
+#endif /* WOLFSSL_AES_DIRECT */
+
+#ifdef HAVE_AES_CBC
+int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{
+    if (aes == NULL || out == NULL || in == NULL) {
+        return BAD_FUNC_ARG;
+    }
+
+    if (aes->rounds != 10 && aes->rounds != 12 && aes->rounds != 14) {
+        WOLFSSL_ERROR_VERBOSE(KEYUSAGE_E);
+        return KEYUSAGE_E;
+    }
+
+    if (sz == 0) {
+        return 0;
+    }
+
+    AES_CBC_encrypt(in, out, sz, (const unsigned char*)aes->key, aes->rounds,
+        (unsigned char*)aes->reg);
+
+    return 0;
+}
+
+#ifdef HAVE_AES_DECRYPT
+int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{
+    if (aes == NULL || out == NULL || in == NULL) {
+        return BAD_FUNC_ARG;
+    }
+
+    if (aes->rounds != 10 && aes->rounds != 12 && aes->rounds != 14) {
+        WOLFSSL_ERROR_VERBOSE(KEYUSAGE_E);
+        return KEYUSAGE_E;
+    }
+
+    if (sz == 0) {
+        return 0;
+    }
+
+    AES_CBC_decrypt(in, out, sz, (const unsigned char*)aes->key, aes->rounds,
+        (unsigned char*)aes->reg);
+
+    return 0;
+}
+#endif
+#endif
+
+#ifdef WOLFSSL_AES_COUNTER
+int wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
+{
+    byte* tmp;
+    word32 numBlocks;
+
+    if (aes == NULL || out == NULL || in == NULL) {
+        return BAD_FUNC_ARG;
+    }
+
+    if (aes->rounds != 10 && aes->rounds != 12 && aes->rounds != 14) {
+        WOLFSSL_ERROR_VERBOSE(KEYUSAGE_E);
+        return KEYUSAGE_E;
+    }
+
+    tmp = (byte*)aes->tmp + AES_BLOCK_SIZE - aes->left;
+    /* consume any unused bytes left in aes->tmp */
+    while ((aes->left != 0) && (sz != 0)) {
+       *(out++) = *(in++) ^ *(tmp++);
+       aes->left--;
+       sz--;
+    }
+
+    /* do as many block size ops as possible */
+    numBlocks = sz / AES_BLOCK_SIZE;
+    if (numBlocks > 0) {
+        AES_CTR_encrypt(in, out, numBlocks * AES_BLOCK_SIZE, (byte*)aes->key,
+            aes->rounds, (byte*)aes->reg);
+
+        sz  -= numBlocks * AES_BLOCK_SIZE;
+        out += numBlocks * AES_BLOCK_SIZE;
+        in  += numBlocks * AES_BLOCK_SIZE;
+    }
+
+    /* handle non block size remaining */
+    if (sz) {
+        byte zeros[AES_BLOCK_SIZE] = { 0, 0, 0, 0, 0, 0, 0, 0,
+                                       0, 0, 0, 0, 0, 0, 0, 0 };
+
+        AES_CTR_encrypt(zeros, (byte*)aes->tmp, AES_BLOCK_SIZE, (byte*)aes->key,
+            aes->rounds, (byte*)aes->reg);
+
+        aes->left = AES_BLOCK_SIZE;
+        tmp = (byte*)aes->tmp;
+
+        while (sz--) {
+            *(out++) = *(in++) ^ *(tmp++);
+            aes->left--;
+        }
+    }
+    return 0;
+}
+#endif
+
+#ifdef HAVE_AESCCM
+/* Software version of AES-CCM from wolfcrypt/src/aes.c
+ * Gets some speed up from hardware acceleration of wc_AesEncrypt */
+
+static void roll_x(Aes* aes, const byte* in, word32 inSz, byte* out)
+{
+    /* process the bulk of the data */
+    while (inSz >= AES_BLOCK_SIZE) {
+        xorbuf(out, in, AES_BLOCK_SIZE);
+        in += AES_BLOCK_SIZE;
+        inSz -= AES_BLOCK_SIZE;
+
+        wc_AesEncrypt(aes, out, out);
+    }
+
+    /* process remainder of the data */
+    if (inSz > 0) {
+        xorbuf(out, in, inSz);
+        wc_AesEncrypt(aes, out, out);
+    }
+}
+
+
+static void roll_auth(Aes* aes, const byte* in, word32 inSz, byte* out)
+{
+    word32 authLenSz;
+    word32 remainder;
+
+    /* encode the length in */
+    if (inSz <= 0xFEFF) {
+        authLenSz = 2;
+        out[0] ^= ((inSz & 0xFF00) >> 8);
+        out[1] ^=  (inSz & 0x00FF);
+    }
+    else if (inSz <= 0xFFFFFFFF) {
+        authLenSz = 6;
+        out[0] ^= 0xFF; out[1] ^= 0xFE;
+        out[2] ^= ((inSz & 0xFF000000) >> 24);
+        out[3] ^= ((inSz & 0x00FF0000) >> 16);
+        out[4] ^= ((inSz & 0x0000FF00) >>  8);
+        out[5] ^=  (inSz & 0x000000FF);
+    }
+    /* Note, the protocol handles auth data up to 2^64, but we are
+     * using 32-bit sizes right now, so the bigger data isn't handled
+     * else if (inSz <= 0xFFFFFFFFFFFFFFFF) {} */
+    else
+        return;
+
+    /* start fill out the rest of the first block */
+    remainder = AES_BLOCK_SIZE - authLenSz;
+    if (inSz >= remainder) {
+        /* plenty of bulk data to fill the remainder of this block */
+        xorbuf(out + authLenSz, in, remainder);
+        inSz -= remainder;
+        in += remainder;
+    }
+    else {
+        /* not enough bulk data, copy what is available, and pad zero */
+        xorbuf(out + authLenSz, in, inSz);
+        inSz = 0;
+    }
+    wc_AesEncrypt(aes, out, out);
+
+    if (inSz > 0)
+        roll_x(aes, in, inSz, out);
+}
+
+
+static WC_INLINE void AesCcmCtrInc(byte* B, word32 lenSz)
+{
+    word32 i;
+
+    for (i = 0; i < lenSz; i++) {
+        if (++B[AES_BLOCK_SIZE - 1 - i] != 0) return;
+    }
+}
+
+
+/* return 0 on success */
+int wc_AesCcmEncrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                   const byte* nonce, word32 nonceSz,
+                   byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    byte A[AES_BLOCK_SIZE];
+    byte B[AES_BLOCK_SIZE];
+    byte lenSz;
+    word32 i;
+    byte mask     = 0xFF;
+    word32 wordSz = (word32)sizeof(word32);
+
+    /* sanity check on arguments */
+    if (aes == NULL || out == NULL || in == NULL || nonce == NULL
+            || authTag == NULL || nonceSz < 7 || nonceSz > 13)
+        return BAD_FUNC_ARG;
+
+    if (wc_AesCcmCheckTagSize(authTagSz) != 0) {
+        return BAD_FUNC_ARG;
+    }
+
+    XMEMCPY(B+1, nonce, nonceSz);
+    lenSz = AES_BLOCK_SIZE - 1 - (byte)nonceSz;
+    B[0] = (authInSz > 0 ? 64 : 0)
+         + (8 * (((byte)authTagSz - 2) / 2))
+         + (lenSz - 1);
+    for (i = 0; i < lenSz; i++) {
+        if (mask && i >= wordSz)
+            mask = 0x00;
+        B[AES_BLOCK_SIZE - 1 - i] = (inSz >> ((8 * i) & mask)) & mask;
+    }
+
+    wc_AesEncrypt(aes, B, A);
+
+    if (authInSz > 0)
+        roll_auth(aes, authIn, authInSz, A);
+    if (inSz > 0)
+        roll_x(aes, in, inSz, A);
+    XMEMCPY(authTag, A, authTagSz);
+
+    B[0] = lenSz - 1;
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    wc_AesEncrypt(aes, B, A);
+    xorbuf(authTag, A, authTagSz);
+
+    B[15] = 1;
+    while (inSz >= AES_BLOCK_SIZE) {
+        wc_AesEncrypt(aes, B, A);
+        xorbuf(A, in, AES_BLOCK_SIZE);
+        XMEMCPY(out, A, AES_BLOCK_SIZE);
+
+        AesCcmCtrInc(B, lenSz);
+        inSz -= AES_BLOCK_SIZE;
+        in += AES_BLOCK_SIZE;
+        out += AES_BLOCK_SIZE;
+    }
+    if (inSz > 0) {
+        wc_AesEncrypt(aes, B, A);
+        xorbuf(A, in, inSz);
+        XMEMCPY(out, A, inSz);
+    }
+
+    ForceZero(A, AES_BLOCK_SIZE);
+    ForceZero(B, AES_BLOCK_SIZE);
+
+    return 0;
+}
+
+#ifdef HAVE_AES_DECRYPT
+int  wc_AesCcmDecrypt(Aes* aes, byte* out, const byte* in, word32 inSz,
+                   const byte* nonce, word32 nonceSz,
+                   const byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    byte A[AES_BLOCK_SIZE];
+    byte B[AES_BLOCK_SIZE];
+    byte* o;
+    byte lenSz;
+    word32 i, oSz;
+    int result = 0;
+    byte mask     = 0xFF;
+    word32 wordSz = (word32)sizeof(word32);
+
+    /* sanity check on arguments */
+    if (aes == NULL || out == NULL || in == NULL || nonce == NULL
+            || authTag == NULL || nonceSz < 7 || nonceSz > 13)
+        return BAD_FUNC_ARG;
+
+    if (wc_AesCcmCheckTagSize(authTagSz) != 0) {
+        return BAD_FUNC_ARG;
+    }
+
+    o = out;
+    oSz = inSz;
+    XMEMCPY(B+1, nonce, nonceSz);
+    lenSz = AES_BLOCK_SIZE - 1 - (byte)nonceSz;
+
+    B[0] = lenSz - 1;
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    B[15] = 1;
+
+    while (oSz >= AES_BLOCK_SIZE) {
+        wc_AesEncrypt(aes, B, A);
+        xorbuf(A, in, AES_BLOCK_SIZE);
+        XMEMCPY(o, A, AES_BLOCK_SIZE);
+
+        AesCcmCtrInc(B, lenSz);
+        oSz -= AES_BLOCK_SIZE;
+        in += AES_BLOCK_SIZE;
+        o += AES_BLOCK_SIZE;
+    }
+    if (inSz > 0) {
+        wc_AesEncrypt(aes, B, A);
+        xorbuf(A, in, oSz);
+        XMEMCPY(o, A, oSz);
+    }
+
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    wc_AesEncrypt(aes, B, A);
+
+    o = out;
+    oSz = inSz;
+
+    B[0] = (authInSz > 0 ? 64 : 0)
+         + (8 * (((byte)authTagSz - 2) / 2))
+         + (lenSz - 1);
+    for (i = 0; i < lenSz; i++) {
+        if (mask && i >= wordSz)
+            mask = 0x00;
+        B[AES_BLOCK_SIZE - 1 - i] = (inSz >> ((8 * i) & mask)) & mask;
+    }
+
+    wc_AesEncrypt(aes, B, A);
+
+    if (authInSz > 0)
+        roll_auth(aes, authIn, authInSz, A);
+    if (inSz > 0)
+        roll_x(aes, o, oSz, A);
+
+    B[0] = lenSz - 1;
+    for (i = 0; i < lenSz; i++)
+        B[AES_BLOCK_SIZE - 1 - i] = 0;
+    wc_AesEncrypt(aes, B, B);
+    xorbuf(A, B, authTagSz);
+
+    if (ConstantCompare(A, authTag, authTagSz) != 0) {
+        /* If the authTag check fails, don't keep the decrypted data.
+         * Unfortunately, you need the decrypted data to calculate the
+         * check value. */
+        XMEMSET(out, 0, inSz);
+        result = AES_CCM_AUTH_E;
+    }
+
+    ForceZero(A, AES_BLOCK_SIZE);
+    ForceZero(B, AES_BLOCK_SIZE);
+    o = NULL;
+
+    return result;
+}
+#endif /* HAVE_AES_DECRYPT */
+#endif /* HAVE_AESCCM */
+
+#ifdef HAVE_AESGCM
+static WC_INLINE void RIGHTSHIFTX(byte* x)
+{
+    int i;
+    int carryIn = 0;
+    byte borrow = (0x00 - (x[15] & 0x01)) & 0xE1;
+
+    for (i = 0; i < AES_BLOCK_SIZE; i++) {
+        int carryOut = (x[i] & 0x01) << 7;
+        x[i] = (byte) ((x[i] >> 1) | carryIn);
+        carryIn = carryOut;
+    }
+    x[0] ^= borrow;
+}
+
+static void GenerateM0(Aes* aes)
+{
+    int i;
+    byte (*m)[AES_BLOCK_SIZE] = aes->M0;
+
+    /* 0 times -> 0x0 */
+    XMEMSET(m[0x0], 0, AES_BLOCK_SIZE);
+    /* 1 times -> 0x8 */
+    XMEMCPY(m[0x8], aes->H, AES_BLOCK_SIZE);
+    /* 2 times -> 0x4 */
+    XMEMCPY(m[0x4], m[0x8], AES_BLOCK_SIZE);
+    RIGHTSHIFTX(m[0x4]);
+    /* 4 times -> 0x2 */
+    XMEMCPY(m[0x2], m[0x4], AES_BLOCK_SIZE);
+    RIGHTSHIFTX(m[0x2]);
+    /* 8 times -> 0x1 */
+    XMEMCPY(m[0x1], m[0x2], AES_BLOCK_SIZE);
+    RIGHTSHIFTX(m[0x1]);
+
+    /* 0x3 */
+    XMEMCPY(m[0x3], m[0x2], AES_BLOCK_SIZE);
+    xorbuf (m[0x3], m[0x1], AES_BLOCK_SIZE);
+
+    /* 0x5 -> 0x7 */
+    XMEMCPY(m[0x5], m[0x4], AES_BLOCK_SIZE);
+    xorbuf (m[0x5], m[0x1], AES_BLOCK_SIZE);
+    XMEMCPY(m[0x6], m[0x4], AES_BLOCK_SIZE);
+    xorbuf (m[0x6], m[0x2], AES_BLOCK_SIZE);
+    XMEMCPY(m[0x7], m[0x4], AES_BLOCK_SIZE);
+    xorbuf (m[0x7], m[0x3], AES_BLOCK_SIZE);
+
+    /* 0x9 -> 0xf */
+    XMEMCPY(m[0x9], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0x9], m[0x1], AES_BLOCK_SIZE);
+    XMEMCPY(m[0xa], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0xa], m[0x2], AES_BLOCK_SIZE);
+    XMEMCPY(m[0xb], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0xb], m[0x3], AES_BLOCK_SIZE);
+    XMEMCPY(m[0xc], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0xc], m[0x4], AES_BLOCK_SIZE);
+    XMEMCPY(m[0xd], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0xd], m[0x5], AES_BLOCK_SIZE);
+    XMEMCPY(m[0xe], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0xe], m[0x6], AES_BLOCK_SIZE);
+    XMEMCPY(m[0xf], m[0x8], AES_BLOCK_SIZE);
+    xorbuf (m[0xf], m[0x7], AES_BLOCK_SIZE);
+
+    for (i = 0; i < 16; i++) {
+        word32* m32 = (word32*)aes->M0[i];
+        m32[0] = ByteReverseWord32(m32[0]);
+        m32[1] = ByteReverseWord32(m32[1]);
+        m32[2] = ByteReverseWord32(m32[2]);
+        m32[3] = ByteReverseWord32(m32[3]);
+    }
+}
+
+int wc_AesGcmSetKey(Aes* aes, const byte* key, word32 len)
+{
+    int  ret;
+    byte iv[AES_BLOCK_SIZE];
+
+    if (aes == NULL) {
+        return BAD_FUNC_ARG;
+    }
+
+    if ((len != 16) && (len != 24) && (len != 32)) {
+        return BAD_FUNC_ARG;
+    }
+
+    XMEMSET(iv, 0, AES_BLOCK_SIZE);
+    ret = wc_AesSetKey(aes, key, len, iv, AES_ENCRYPTION);
+    
+    if (ret == 0) {
+        AES_ECB_encrypt(iv, aes->H, AES_BLOCK_SIZE,
+            (const unsigned char*)aes->key, aes->rounds);
+        GenerateM0(aes);
+    }
+
+    return ret;
+}
+
+static WC_INLINE void IncrementGcmCounter(byte* inOutCtr)
+{
+    int i;
+
+    /* in network byte order so start at end and work back */
+    for (i = AES_BLOCK_SIZE - 1; i >= AES_BLOCK_SIZE - CTR_SZ; i--) {
+        if (++inOutCtr[i])  /* we're done unless we overflow */
+            return;
+    }
+}
+
+static WC_INLINE void FlattenSzInBits(byte* buf, word32 sz)
+{
+    /* Multiply the sz by 8 */
+    word32 szHi = (sz >> (8*sizeof(sz) - 3));
+    sz <<= 3;
+
+    /* copy over the words of the sz into the destination buffer */
+    buf[0] = (szHi >> 24) & 0xff;
+    buf[1] = (szHi >> 16) & 0xff;
+    buf[2] = (szHi >>  8) & 0xff;
+    buf[3] = szHi & 0xff;
+    buf[4] = (sz >> 24) & 0xff;
+    buf[5] = (sz >> 16) & 0xff;
+    buf[6] = (sz >>  8) & 0xff;
+    buf[7] = sz & 0xff;
+}
+
+static void gcm_ghash_arm32(Aes* aes, const byte* a, word32 aSz, const byte* c,
+    word32 cSz, byte* s, word32 sSz)
+{
+    byte x[AES_BLOCK_SIZE];
+    byte scratch[AES_BLOCK_SIZE];
+    word32 blocks, partial;
+
+    if (aes == NULL) {
+        return;
+    }
+
+    XMEMSET(x, 0, AES_BLOCK_SIZE);
+
+    /* Hash in A, the Additional Authentication Data */
+    if (aSz != 0 && a != NULL) {
+        blocks = aSz / AES_BLOCK_SIZE;
+        partial = aSz % AES_BLOCK_SIZE;
+        if (blocks > 0) {
+            GCM_gmult_len(x, aes->M0, a, blocks * AES_BLOCK_SIZE);
+            a += blocks * AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, a, partial);
+            GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+        }
+    }
+
+    /* Hash in C, the Ciphertext */
+    if (cSz != 0 && c != NULL) {
+        blocks = cSz / AES_BLOCK_SIZE;
+        partial = cSz % AES_BLOCK_SIZE;
+        if (blocks > 0) {
+            GCM_gmult_len(x, aes->M0, c, blocks * AES_BLOCK_SIZE);
+            c += blocks * AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, c, partial);
+            GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+        }
+    }
+
+    /* Hash in the lengths of A and C in bits */
+    FlattenSzInBits(&scratch[0], aSz);
+    FlattenSzInBits(&scratch[8], cSz);
+    GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+
+    /* Copy the result into s. */
+    XMEMCPY(s, x, sSz);
+}
+
+int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+                   const byte* iv, word32 ivSz,
+                   byte* authTag, word32 authTagSz,
+                   const byte* authIn, word32 authInSz)
+{
+    word32 blocks;
+    word32 partial;
+    byte counter[AES_BLOCK_SIZE];
+    byte initialCounter[AES_BLOCK_SIZE];
+    byte x[AES_BLOCK_SIZE];
+    byte scratch[AES_BLOCK_SIZE];
+
+    /* sanity checks */
+    if (aes == NULL || (iv == NULL && ivSz > 0) || (authTag == NULL) ||
+            (authIn == NULL && authInSz > 0) || (ivSz == 0)) {
+        WOLFSSL_MSG("a NULL parameter passed in when size is larger than 0");
+        return BAD_FUNC_ARG;
+    }
+
+    if (authTagSz < WOLFSSL_MIN_AUTH_TAG_SZ || authTagSz > AES_BLOCK_SIZE) {
+        WOLFSSL_MSG("GcmEncrypt authTagSz error");
+        return BAD_FUNC_ARG;
+    }
+
+    if (aes->rounds != 10 && aes->rounds != 12 && aes->rounds != 14) {
+        WOLFSSL_ERROR_VERBOSE(KEYUSAGE_E);
+        return KEYUSAGE_E;
+    }
+
+    XMEMSET(initialCounter, 0, AES_BLOCK_SIZE);
+    if (ivSz == GCM_NONCE_MID_SZ) {
+        XMEMCPY(initialCounter, iv, ivSz);
+        initialCounter[AES_BLOCK_SIZE - 1] = 1;
+    }
+    else {
+        gcm_ghash_arm32(aes, NULL, 0, iv, ivSz, initialCounter, AES_BLOCK_SIZE);
+    }
+    XMEMCPY(counter, initialCounter, AES_BLOCK_SIZE);
+
+    /* Hash in the Additional Authentication Data */
+    XMEMSET(x, 0, AES_BLOCK_SIZE);
+    if (authInSz != 0 && authIn != NULL) {
+        blocks = authInSz / AES_BLOCK_SIZE;
+        partial = authInSz % AES_BLOCK_SIZE;
+        if (blocks > 0) {
+            GCM_gmult_len(x, aes->M0, authIn, blocks * AES_BLOCK_SIZE);
+            authIn += blocks * AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, authIn, partial);
+            GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+        }
+    }
+
+    /* do as many blocks as possible */
+    blocks = sz / AES_BLOCK_SIZE;
+    partial = sz % AES_BLOCK_SIZE;
+    if (blocks > 0) {
+        AES_GCM_encrypt(in, out, blocks * AES_BLOCK_SIZE,
+            (const unsigned char*)aes->key, aes->rounds, counter);
+        GCM_gmult_len(x, aes->M0, out, blocks * AES_BLOCK_SIZE);
+        in += blocks * AES_BLOCK_SIZE;
+        out += blocks * AES_BLOCK_SIZE;
+    }
+
+    /* take care of partial block sizes leftover */
+    if (partial != 0) {
+        AES_GCM_encrypt(in, scratch, AES_BLOCK_SIZE,
+            (const unsigned char*)aes->key, aes->rounds, counter);
+        XMEMCPY(out, scratch, partial);
+
+        XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+        XMEMCPY(scratch, out, partial);
+        GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+    }
+
+    /* Hash in the lengths of A and C in bits */
+    XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+    FlattenSzInBits(&scratch[0], authInSz);
+    FlattenSzInBits(&scratch[8], sz);
+    GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+    if (authTagSz > AES_BLOCK_SIZE) {
+        XMEMCPY(authTag, x, AES_BLOCK_SIZE);
+    }
+    else {
+        /* authTagSz can be smaller than AES_BLOCK_SIZE */
+        XMEMCPY(authTag, x, authTagSz);
+    }
+
+    /* Auth tag calculation. */
+    AES_ECB_encrypt(initialCounter, scratch, AES_BLOCK_SIZE,
+        (const unsigned char*)aes->key, aes->rounds);
+    xorbuf(authTag, scratch, authTagSz);
+
+    return 0;
+}
+
+int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
+    const byte* iv, word32 ivSz, const byte* authTag, word32 authTagSz,
+    const byte* authIn, word32 authInSz)
+{
+    word32 blocks;
+    word32 partial;
+    byte counter[AES_BLOCK_SIZE];
+    byte initialCounter[AES_BLOCK_SIZE];
+    byte scratch[AES_BLOCK_SIZE];
+    byte x[AES_BLOCK_SIZE];
+
+    /* sanity checks */
+    if (aes == NULL || iv == NULL || (sz != 0 && (in == NULL || out == NULL)) ||
+        authTag == NULL || authTagSz > AES_BLOCK_SIZE || authTagSz == 0 ||
+        ivSz == 0) {
+        WOLFSSL_MSG("a NULL parameter passed in when size is larger than 0");
+        return BAD_FUNC_ARG;
+    }
+
+    XMEMSET(initialCounter, 0, AES_BLOCK_SIZE);
+    if (ivSz == GCM_NONCE_MID_SZ) {
+        XMEMCPY(initialCounter, iv, ivSz);
+        initialCounter[AES_BLOCK_SIZE - 1] = 1;
+    }
+    else {
+        gcm_ghash_arm32(aes, NULL, 0, iv, ivSz, initialCounter, AES_BLOCK_SIZE);
+    }
+    XMEMCPY(counter, initialCounter, AES_BLOCK_SIZE);
+
+    XMEMSET(x, 0, AES_BLOCK_SIZE);
+    /* Hash in the Additional Authentication Data */
+    if (authInSz != 0 && authIn != NULL) {
+        blocks = authInSz / AES_BLOCK_SIZE;
+        partial = authInSz % AES_BLOCK_SIZE;
+        if (blocks > 0) {
+            GCM_gmult_len(x, aes->M0, authIn, blocks * AES_BLOCK_SIZE);
+            authIn += blocks * AES_BLOCK_SIZE;
+        }
+        if (partial != 0) {
+            XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+            XMEMCPY(scratch, authIn, partial);
+            GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+        }
+    }
+
+    blocks = sz / AES_BLOCK_SIZE;
+    partial = sz % AES_BLOCK_SIZE;
+    /* do as many blocks as possible */
+    if (blocks > 0) {
+        GCM_gmult_len(x, aes->M0, in, blocks * AES_BLOCK_SIZE);
+
+        AES_GCM_encrypt(in, out, blocks * AES_BLOCK_SIZE,
+            (const unsigned char*)aes->key, aes->rounds, counter);
+        in += blocks * AES_BLOCK_SIZE;
+        out += blocks * AES_BLOCK_SIZE;
+    }
+    if (partial != 0) {
+        XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+        XMEMCPY(scratch, in, partial);
+        GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+
+        AES_GCM_encrypt(in, scratch, AES_BLOCK_SIZE,
+            (const unsigned char*)aes->key, aes->rounds, counter);
+        XMEMCPY(out, scratch, partial);
+    }
+
+    XMEMSET(scratch, 0, AES_BLOCK_SIZE);
+    FlattenSzInBits(&scratch[0], authInSz);
+    FlattenSzInBits(&scratch[8], sz);
+    GCM_gmult_len(x, aes->M0, scratch, AES_BLOCK_SIZE);
+    AES_ECB_encrypt(initialCounter, scratch, AES_BLOCK_SIZE,
+        (const unsigned char*)aes->key, aes->rounds);
+    xorbuf(x, scratch, authTagSz);
+    if (authTag != NULL) {
+        if (ConstantCompare(authTag, x, authTagSz) != 0) {
+            return AES_GCM_AUTH_E;
+        }
+    }
+
+    return 0;
+}
+#endif /* HAVE_AESGCM */
+#endif /* !WOLFSSL_ARMASM_NO_HW_CRYPTO */
 #endif /* !NO_AES && WOLFSSL_ARMASM */
diff --git a/wolfcrypt/src/port/arm/armv8-chacha.c b/wolfcrypt/src/port/arm/armv8-chacha.c
index edd51e726..59c030aaf 100644
--- a/wolfcrypt/src/port/arm/armv8-chacha.c
+++ b/wolfcrypt/src/port/arm/armv8-chacha.c
@@ -989,11 +989,11 @@ static WC_INLINE int wc_Chacha_encrypt_256(const word32 input[CHACHA_CHUNK_WORDS
         "VMOV d4, r8, r9 \n\t"
         "STRD r10, r11, [sp, #4*10] \n\t"
         "VMOV d5, r10, r11 \n\t"
-#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 8)
-        "LDR r11, [r14, #4*14] \n\t"
-        "LDR r10, [r14, #4*15] \n\t"
+#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
+        "LDR r10, [r14, #4*14] \n\t"
+        "LDR r11, [r14, #4*15] \n\t"
 #else
-        "LDRD r11, r10, [r14, #4*14] \n\t"
+        "LDRD r10, r11, [r14, #4*14] \n\t"
 #endif
         "VMOV q4, q0 \n\t"
         "VMOV q5, q1 \n\t"
@@ -1003,10 +1003,11 @@ static WC_INLINE int wc_Chacha_encrypt_256(const word32 input[CHACHA_CHUNK_WORDS
         "VMOV q10, q2 \n\t"
         // r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
         //  0  1  2  3  4  5  6  7  8  9  15  14  12
-        "VMOV d7, r11, r10 \n\t"
-        "STR r10, [sp, #4*15] \n\t"
-        "VMOV d15, r11, r10 \n\t"
-        "VMOV d23, r11, r10 \n\t"
+        "VMOV d7, r10, r11 \n\t"
+        "STR r11, [sp, #4*15] \n\t"
+        "VMOV d15, r10, r11 \n\t"
+        "VMOV d23, r10, r11 \n\t"
+        "MOV r11, r10 \n\t"
         "MOV r10, r12 \n\t"
         "MOV r12, r11 \n\t"
         "LDR r11, [r14, #4*13] \n\t"