diff --git a/IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s b/IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s deleted file mode 100644 index 6fdb7ab708..0000000000 --- a/IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s +++ /dev/null @@ -1,338 +0,0 @@ -;/*********************************************************************** -; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $ -; * -; * Project: LPC43xx CMSIS Package -; * -; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx -; * Device Series. -; * -; * Copyright(C) 2011, NXP Semiconductor -; * All rights reserved. -; * -; * modified by KEIL -; *********************************************************************** -; * Software that is described herein is for illustrative purposes only -; * which provides customers with programming information regarding the -; * products. This software is supplied "AS IS" without any warranties. -; * NXP Semiconductors assumes no responsibility or liability for the -; * use of the software, conveys no license or title under any patent, -; * copyright, or mask work right to the product. NXP Semiconductors -; * reserves the right to make changes in the software without -; * notification. NXP Semiconductors also make no representation or -; * warranty that such application will be suitable for the specified -; * use without further testing or modification. -; **********************************************************************/ - -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00003000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x0000a000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - -Sign_Value EQU 0x5A5A5A5A - -__Vectors DCD __initial_sp ; 0 Top of Stack - DCD Reset_Handler ; 1 Reset Handler - DCD NMI_Handler ; 2 NMI Handler - DCD HardFault_Handler ; 3 Hard Fault Handler - DCD MemManage_Handler ; 4 MPU Fault Handler - DCD BusFault_Handler ; 5 Bus Fault Handler - DCD UsageFault_Handler ; 6 Usage Fault Handler - DCD Sign_Value ; 7 Reserved - DCD 0 ; 8 Reserved - DCD 0 ; 9 Reserved - DCD 0 ; 10 Reserved - DCD SVC_Handler ; 11 SVCall Handler - DCD DebugMon_Handler ; 12 Debug Monitor Handler - DCD 0 ; 13 Reserved - DCD PendSV_Handler ; 14 PendSV Handler - DCD SysTick_Handler ; 15 SysTick Handler - - ; External Interrupts - DCD DAC_IRQHandler ; 16 D/A Converter - DCD M0CORE_IRQHandler ; 17 M0 Core - DCD DMA_IRQHandler ; 18 General Purpose DMA - DCD EZH_IRQHandler ; 19 EZH/EDM - DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon - DCD ETH_IRQHandler ; 21 Ethernet - DCD SDIO_IRQHandler ; 22 SD/MMC - DCD LCD_IRQHandler ; 23 LCD - DCD USB0_IRQHandler ; 24 USB0 - DCD USB1_IRQHandler ; 25 USB1 - DCD SCT_IRQHandler ; 26 State Configurable Timer - DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer - DCD TIMER0_IRQHandler ; 28 Timer0 - DCD TIMER1_IRQHandler ; 29 Timer1 - DCD TIMER2_IRQHandler ; 30 Timer2 - DCD TIMER3_IRQHandler ; 31 Timer3 - DCD MCPWM_IRQHandler ; 32 Motor Control PWM - DCD ADC0_IRQHandler ; 33 A/D Converter 0 - DCD I2C0_IRQHandler ; 34 I2C0 - DCD I2C1_IRQHandler ; 35 I2C1 - DCD SPI_IRQHandler ; 36 SPI - DCD ADC1_IRQHandler ; 37 A/D Converter 1 - DCD SSP0_IRQHandler ; 38 SSP0 - DCD SSP1_IRQHandler ; 39 SSP1 - DCD UART0_IRQHandler ; 40 UART0 - DCD UART1_IRQHandler ; 41 UART1 - DCD UART2_IRQHandler ; 42 UART2 - DCD UART3_IRQHandler ; 43 UART3 - DCD I2S0_IRQHandler ; 44 I2S0 - DCD I2S1_IRQHandler ; 45 I2S1 - DCD SPIFI_IRQHandler ; 46 SPI Flash Interface - DCD SGPIO_IRQHandler ; 47 SGPIO - DCD GPIO0_IRQHandler ; 48 GPIO0 - DCD GPIO1_IRQHandler ; 49 GPIO1 - DCD GPIO2_IRQHandler ; 50 GPIO2 - DCD GPIO3_IRQHandler ; 51 GPIO3 - DCD GPIO4_IRQHandler ; 52 GPIO4 - DCD GPIO5_IRQHandler ; 53 GPIO5 - DCD GPIO6_IRQHandler ; 54 GPIO6 - DCD GPIO7_IRQHandler ; 55 GPIO7 - DCD GINT0_IRQHandler ; 56 GINT0 - DCD GINT1_IRQHandler ; 57 GINT1 - DCD EVRT_IRQHandler ; 58 Event Router - DCD CAN1_IRQHandler ; 59 C_CAN1 - DCD 0 ; 60 Reserved - DCD VADC_IRQHandler ; 61 VADC - DCD ATIMER_IRQHandler ; 62 ATIMER - DCD RTC_IRQHandler ; 63 RTC - DCD 0 ; 64 Reserved - DCD WDT_IRQHandler ; 65 WDT - DCD M0s_IRQHandler ; 66 M0s - DCD CAN0_IRQHandler ; 67 C_CAN0 - DCD QEI_IRQHandler ; 68 QEI - - -;CRP address at offset 0x2FC relative to the BOOT Bank address - IF :LNOT::DEF:NO_CRP - SPACE (0x2FC - (. - __Vectors)) -; EXPORT CRP_Key -CRP_Key DCD 0xFFFFFFFF -; 0xFFFFFFFF => CRP Disabled -; 0x12345678 => CRP Level 1 -; 0x87654321 => CRP Level 2 -; 0x43218765 => CRP Level 3 (ARE YOU SURE?) -; 0x4E697370 => NO ISP (ARE YOU SURE?) - ENDIF - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT DAC_IRQHandler [WEAK] - EXPORT M0CORE_IRQHandler [WEAK] - EXPORT DMA_IRQHandler [WEAK] - EXPORT EZH_IRQHandler [WEAK] - EXPORT FLASH_EEPROM_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USB1_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT RIT_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler [WEAK] - EXPORT MCPWM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT SSP0_IRQHandler [WEAK] - EXPORT SSP1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT UART3_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT I2S1_IRQHandler [WEAK] - EXPORT SPIFI_IRQHandler [WEAK] - EXPORT SGPIO_IRQHandler [WEAK] - EXPORT GPIO0_IRQHandler [WEAK] - EXPORT GPIO1_IRQHandler [WEAK] - EXPORT GPIO2_IRQHandler [WEAK] - EXPORT GPIO3_IRQHandler [WEAK] - EXPORT GPIO4_IRQHandler [WEAK] - EXPORT GPIO5_IRQHandler [WEAK] - EXPORT GPIO6_IRQHandler [WEAK] - EXPORT GPIO7_IRQHandler [WEAK] - EXPORT GINT0_IRQHandler [WEAK] - EXPORT GINT1_IRQHandler [WEAK] - EXPORT EVRT_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] - EXPORT VADC_IRQHandler [WEAK] - EXPORT ATIMER_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT M0s_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT QEI_IRQHandler [WEAK] - -DAC_IRQHandler -M0CORE_IRQHandler -DMA_IRQHandler -EZH_IRQHandler -FLASH_EEPROM_IRQHandler -ETH_IRQHandler -SDIO_IRQHandler -LCD_IRQHandler -USB0_IRQHandler -USB1_IRQHandler -SCT_IRQHandler -RIT_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -TIMER3_IRQHandler -MCPWM_IRQHandler -ADC0_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI_IRQHandler -ADC1_IRQHandler -SSP0_IRQHandler -SSP1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -I2S0_IRQHandler -I2S1_IRQHandler -SPIFI_IRQHandler -SGPIO_IRQHandler -GPIO0_IRQHandler -GPIO1_IRQHandler -GPIO2_IRQHandler -GPIO3_IRQHandler -GPIO4_IRQHandler -GPIO5_IRQHandler -GPIO6_IRQHandler -GPIO7_IRQHandler -GINT0_IRQHandler -GINT1_IRQHandler -EVRT_IRQHandler -CAN1_IRQHandler -VADC_IRQHandler -ATIMER_IRQHandler -RTC_IRQHandler -WDT_IRQHandler -M0s_IRQHandler -CAN0_IRQHandler -QEI_IRQHandler - - B . - - ENDP - - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - - END diff --git a/IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini b/IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini deleted file mode 100644 index 5f72e1102c..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini +++ /dev/null @@ -1,22 +0,0 @@ -/******************************************************************************/ -/* Dbg_Flash.ini Initialization File for Debugging from Internal */ -/* Flash for NXP LPC18xx/LPC43xx */ -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2005-2012 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - -FUNC void Per_Reset (void) { - // Reset peripherals: LCD, USB0, USB1, DMA, SDIO, ETHERNET - _WDWORD(0x40053100, 0x005F0000); // Issue reset - _sleep_(1); -} - -Per_Reset(); // Reset some peripherals - -KILL BUTTON * // Kill all buttons -DEFINE BUTTON "Reset Peripherals", "Per_Reset()" // Create peripheral reset button - diff --git a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c deleted file mode 100644 index 9a162ba881..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c +++ /dev/null @@ -1,401 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - FlashFS - *---------------------------------------------------------------------------- - * Name: FILE_CONFIG.C - * Purpose: Configuration of RL FlashFS by user - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// File System -// ============== -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define N_FILES 6 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACNT 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CADR 0x60000000 - -// -// CPU Clock Frequency [Hz]<0-1000000000> -// Define the CPU Clock frequency used for -// flash programming and erasing. -#define CPU_CLK 180000000 - -// -// Flash Drive -// ============== -// Enable Embedded Flash Drive [F:] -#define FL0_EN 0 - -// Base address <0x0-0xFFFFF000:0x1000> -// Define the target device Base address -// Default: 0x80000000 -#define FL0_BADR 0x80000000 - -// Device Size <0x4000-0xFFFFF000:0x4000> -// Define the size of Flash device in bytes -// Default: 0x100000 (1MB) -#define FL0_SIZE 0x0200000 - -// Content of Erased Memory <0=>0x00 <0xFF=>0xFF -// Define the initial value for erased Flash data -// Default: 0xFF -#define FL0_INITV 0xFF - -// Device Description file -// Specify a file name with a relative path -// Default: FS_FlashDev.h -#define FL0_HFILE "FS_FlashDev.h" - -// Default Drive [F:] -// Used when Drive letter not specified -#define FL0_DEF 1 - -// -// SPI Flash Drive -// ================== -// Enable SPI Flash Drive [S:] -#define SF0_EN 0 - -// Device Size <0x10000-0xFFFFF000:0x8000> -// Define the size of SPI Flash device in bytes -// Default: 0x100000 (1MB) -#define SF0_SIZE 0x0200000 - -// Content of Erased Memory <0=>0x00 <0xFF=>0xFF -// Define the initial value for erased Flash data -// Default: 0xFF -#define SF0_INITV 0xFF - -// Device Description file -// Specify a file name with a relative path -// Default: FS_SPI_FlashDev.h -#define SF0_HFILE "FS_SPI_FlashDev.h" - -// Default Drive [S:] -// Used when Drive letter not specified -#define SF0_DEF 0 - -// -// RAM Drive -// ============ -// Enable Embedded RAM Drive [R:] -#define RAM0_EN 0 - -// Device Size <0x4000-0xFFFFF000:0x4000> -// Define the size of RAM device in bytes -// Default: 0x40000 -#define RAM0_SIZE 0x004000 - -// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 -// Define number of virtual sectors for RAM device -// Default: 32 -#define RAM0_NSECT 64 - -// Relocate Device Buffer -// Locate RAM Device Buffer at a specific address. -// If not enabled, the linker selects base address. -#define RAM0_RELOC 1 - -// Base address <0x0-0xFFFFF000:0x1000> -// Define the target device Base address. -// Default: 0x81000000 -#define RAM0_BADR 0x81010000 - -// -// Default Drive [R:] -// Used when Drive letter not specified -#define RAM0_DEF 0 - -// -// Memory Card Drive 0 -// ====================== -// Enable Memory Card Drive [M0:] -#define MC0_EN 1 - -// Bus Mode <0=>SD-Native <1=>SPI -// Define Memory Card bus interface mode. -// SD-Native mode needs MCI peripheral. -// SPI mode uses SD Card in SPI mode. -#define MC0_SPI 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define MC0_CASZ 4 - -// Relocate Cache Buffer -// Locate Cache Buffer at a specific address. -// Some devices like NXP LPC23xx require a Cache buffer -// for DMA transfer located at specific address. -#define MC0_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -// For LPC23xx/24xx devices this is USB RAM -// starting at 0x7FD00000. -#define MC0_CADR 0x7FD00000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define MC0_FSJ 0 - -// Default Drive [M0:] -// Used when Drive letter not specified -#define MC0_DEF 1 - -// -// Memory Card Drive 1 -// ====================== -// Enable Memory Card Drive [M1:] -#define MC1_EN 0 - -// Bus Mode <0=>SD-Native <1=>SPI -// Define Memory Card bus interface mode. -// SD-Native mode needs MCI peripheral. -// SPI mode uses SD Card in SPI mode. -#define MC1_SPI 1 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define MC1_CASZ 0 - -// Relocate Cache Buffer -// Locate Cache Buffer at a specific address. -// Some devices like NXP LPC23xx require a Cache buffer -// for DMA transfer located at specific address. -#define MC1_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -// For LPC23xx/24xx devices this is USB RAM -// starting at 0x7FD00000. -#define MC1_CADR 0x7FD00000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define MC1_FSJ 0 - -// Default Drive [M1:] -// Used when Drive letter not specified -#define MC1_DEF 0 - -// -// USB Flash Drive 0 -// ==================== -// Enable USB Flash Drive [U0:] -#define USB0_EN 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define USB0_CASZ 8 - -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define USB0_FSJ 0 - -// Default Drive [U0:] -// Used when Drive letter not specified -#define USB0_DEF 0 - -// -// USB Flash Drive 1 -// ==================== -// Enable USB Flash Drive [U1:] -#define USB1_EN 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define USB1_CASZ 8 - -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define USB1_FSJ 0 - -// Default Drive [U1:] -// Used when Drive letter not specified -#define USB1_DEF 0 - -// -// NAND Flash Drive 0 -// =================== -// Enable NAND Flash Drive [N0:] -#define NAND0_EN 0 - -// Page size <528=> 512 + 16 bytes -// <2112=>2048 + 64 bytes -// <4224=>4096 + 128 bytes -// <8448=>8192 + 256 bytes -// Define program Page size in bytes (User + Spare area). -#define NAND0_PGSZ 2112 - -// Block Size <8=>8 pages <16=>16 pages <32=>32 pages -// <64=>64 pages <128=>128 pages <256=>256 pages -// Define number of pages in a block. -#define NAND0_PGCNT 64 - -// Device Size [blocks] <512-32768> -// Define number of blocks in NAND Flash device. -#define NAND0_BLCNT 4096 - -// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages -// <8=>8 pages <16=>16 pages <32=>32 pages -// Define number of cached Pages. -// Default: 4 pages -#define NAND0_CAPG 2 - -// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks -// <8=>8 blocks <16=>16 blocks <32=>32 blocks -// <64=>64 blocks <128=>128 blocks <256=>256 blocks -// Define number of indexed Flash Blocks. -// Increase this number for better performance. -// Default: 16 blocks -#define NAND0_CABL 16 - -// Software ECC <0=>None <1=>Hamming (SLC) -// Enable software ECC calculation only, -// if not supported by hardware. -#define NAND0_SWECC 1 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define NAND0_CASZ 4 - -// Relocate Cache Buffers -// Use this option to locate Cache buffers -// at specific address in RAM or SDRAM. -#define NAND0_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define base address for Cache Buffers. -#define NAND0_CADR 0x80000000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define NAND0_FSJ 0 - -// Default Drive [N0:] -// Used when Drive letter not specified -#define NAND0_DEF 0 - -// -// NAND Flash Drive 1 -// =================== -// Enable NAND Flash Drive [N1:] -#define NAND1_EN 0 - -// Page size <528=> 512 + 16 bytes -// <2112=>2048 + 64 bytes -// <4224=>4096 + 128 bytes -// <8448=>8192 + 256 bytes -// Define program Page size in bytes (User + Spare area). -#define NAND1_PGSZ 2112 - -// Block Size <8=>8 pages <16=>16 pages <32=>32 pages -// <64=>64 pages <128=>128 pages <256=>256 pages -// Define number of pages in a block. -#define NAND1_PGCNT 32 - -// Device Size [blocks] <512-32768> -// Define number of blocks in NAND Flash device. -#define NAND1_BLCNT 512 - -// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages -// <8=>8 pages <16=>16 pages <32=>32 pages -// Define number of cached Pages. -// Default: 4 pages -#define NAND1_CAPG 4 - -// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks -// <8=>8 blocks <16=>16 blocks <32=>32 blocks -// <64=>64 blocks <128=>128 blocks <256=>256 blocks -// Define number of indexed Flash Blocks. -// Increase this number for better performance. -// Default: 16 blocks -#define NAND1_CABL 16 - -// Software ECC <0=>None <1=>Hamming (SLC) -// Enable software ECC calculation only, -// if not supported by hardware. -#define NAND1_SWECC 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define NAND1_CASZ 4 - -// Relocate Cache Buffers -// Use this option to locate Cache buffers -// at specific address in RAM or SDRAM. -#define NAND1_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define base address for Cache Buffers. -#define NAND1_CADR 0x80000000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define NAND1_FSJ 0 - -// Default Drive [N1:] -// Used when Drive letter not specified -#define NAND1_DEF 0 - -// - -//------------- <<< end of configuration section >>> ----------------------- - -#ifndef __NO_FILE_LIB_C -#include -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/MDK-ARM/config/Net_Config.c b/IDE/MDK-ARM/MDK-ARM/config/Net_Config.c deleted file mode 100644 index dc09223087..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/Net_Config.c +++ /dev/null @@ -1,892 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - TCPnet - *---------------------------------------------------------------------------- - * Name: NET_CONFIG.C - * Purpose: Configuration of RL TCPnet by user. - * Rev.: V4.60 - *---------------------------------------------------------------------------- - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// System Definitions -// ===================== -// Global TCPnet System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "mcb2300" -#define LHOST_NAME "mcb2300" - -// Memory Pool size <1500-64000:4><#/4> -// This is the size of a memory pool in bytes. Buffers for -// TCPnet packets are allocated from this memory pool. -// Default: 8000 bytes -#define MEM_SIZE 4000 - -// Tick Timer interval <10=> 10 ms <20=> 20 ms <25=> 25 ms -// <40=> 40 ms <50=> 50 ms <100=> 100 ms -// <200=> 200 ms -// System Tick Timer interval for software timers -// Default: 100 ms -#define TICK_INTERVAL 10 - -// -// Ethernet Network Interface -// ============================= -// Enable or disable Ethernet Network Interface -#define ETH_ENABLE 1 - -// MAC Address -// ============== -// Local Ethernet MAC Address -// Value FF:FF:FF:FF:FF:FF is not allowed. -// It is an ethernet Broadcast MAC address. -// Address byte 1 <0x00-0xff:2> -// LSB is an ethernet Multicast bit. -// Must be 0 for local MAC address. -// Default: 0x00 -#define _MAC1 0x30 - -// Address byte 2 <0x00-0xff> -// Default: 0x30 -#define _MAC2 0x06 - -// Address byte 3 <0x00-0xff> -// Default: 0x6C -#define _MAC3 0x6C - -// Address byte 4 <0x00-0xff> -// Default: 0x00 -#define _MAC4 0x00 - -// Address byte 5 <0x00-0xff> -// Default: 0x00 -#define _MAC5 0x00 - -// Address byte 6 <0x00-0xff> -// Default: 0x01 -#define _MAC6 0x01 - -// -// IP Address -// ============= -// Local Static IP Address -// Value 255.255.255.255 is not allowed. -// It is a Broadcast IP address. -// Address byte 1 <0-255> -// Default: 192 -#define _IP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define _IP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define _IP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define _IP4 100 - -// -// Subnet mask -// ============== -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define _MSK1 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define _MSK2 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define _MSK3 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define _MSK4 0 - -// -// Default Gateway -// ================== -// Default Gateway IP Address -// Address byte 1 <0-255> -// Default: 192 -#define _GW1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define _GW2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define _GW3 0 - -// Address byte 4 <0-255> -// Default: 254 -#define _GW4 254 - -// -// Primary DNS Server -// ===================== -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define _pDNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define _pDNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define _pDNS3 2 - -// Address byte 4 <0-255> -// Default: 129 -#define _pDNS4 129 - -// -// Secondary DNS Server -// ======================= -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define _sDNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define _sDNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define _sDNS3 2 - -// Address byte 4 <0-255> -// Default: 130 -#define _sDNS4 130 - -// -// ARP Definitions -// ================== -// Address Resolution Protocol Definitions -// Cache Table size <5-100> -// Number of cached hardware/IP addresses -// Default: 10 -#define ARP_TABSIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for a cached hardware/IP addresses -// Default: 150 -#define ARP_TIMEOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ARP_MAXRETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ARP_RESEND 10 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ARP_NOTIFY 1 - -// -// IGMP Group Management -// ======================== -// Enable or disable Internet Group Management Protocol -#define IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define IGMP_TABSIZE 5 - -// -// NetBIOS Name Service -// ======================= -// When this option is enabled, the embedded host can be -// accessed by his name on the local LAN using NBNS protocol. -// You need to modify also the number of UDP Sockets, -// because NBNS protocol uses one UDP socket to run. -#define NBNS_ENABLE 0 - -// Dynamic Host Configuration -// ============================= -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -// You need to modify also the number of UDP Sockets, -// because DHCP protocol uses one UDP socket to run. -#define DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define DHCP_BOOTF 1 - -// -// - -// PPP Network Interface -// ======================== -// Enable or disable PPP Network Interface -#define PPP_ENABLE 0 - -// IP Address -// ============= -// Local Static IP Address -// Address byte 1 <0-255> -// Default: 192 -#define _IP1P 192 - -// Address byte 2 <0-255> -// Default: 168 -#define _IP2P 168 - -// Address byte 3 <0-255> -// Default: 125 -#define _IP3P 125 - -// Address byte 4 <0-255> -// Default: 1 -#define _IP4P 1 - -// -// Subnet mask -// ============== -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define _MSK1P 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define _MSK2P 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define _MSK3P 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define _MSK4P 0 - -// -// Primary DNS Server -// ===================== -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define _pDNS1P 194 - -// Address byte 2 <0-255> -// Default: 25 -#define _pDNS2P 25 - -// Address byte 3 <0-255> -// Default: 2 -#define _pDNS3P 2 - -// Address byte 4 <0-255> -// Default: 129 -#define _pDNS4P 129 - -// -// Secondary DNS Server -// ======================= -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define _sDNS1P 194 - -// Address byte 2 <0-255> -// Default: 25 -#define _sDNS2P 25 - -// Address byte 3 <0-255> -// Default: 2 -#define _sDNS3P 2 - -// Address byte 4 <0-255> -// Default: 130 -#define _sDNS4P 130 - -// -// Logon Authentication -// ======================= -// Enable or disable user authentication -#define PPP_AUTHEN 1 - -// Unsecured password (PAP) -// Allow or use Password Authentication Protocol. -#define PPP_PAPEN 1 - -// Secured password (CHAP-MD5) -// Request or use Challenge Handshake Authentication -// Protocol with MD5 digest algorithm. -#define PPP_CHAPEN 1 - -// -// Obtain Client IP address automatically -// ========================================= -// This option only applies when PPP Dial-up is used to dial -// to remote PPP Server. If checked, network connection -// dynamically obtains an IP address from remote PPP Server. -#define PPP_GETIP 1 - -// Use Default Gateway on remote Network -// ======================================== -// This option only applies when both Ethernet and PPP Dial-up -// are used. If checked, data that cannot be sent to local LAN -// is forwarded to Dial-up network instead. -#define PPP_DEFGW 1 - -// Async Control Character Map <0x0-0xffffffff> -// A bit-map of control characters 0-31, which are -// transmitted escaped as a 2 byte sequence. -// For XON/XOFF set this value to: 0x000A 0000 -// Default: 0x00000000 -#define PPP_ACCM 0x00000000 - -// LCP Echo Interval in seconds <0-3600> -// If no frames are received within this interval, PPP sends an -// Echo Request and expects an Echo Response from the peer. -// If the response is not received, the link is terminated. -// A value of 0 disables the LCP Echo test. -// Default: 30 -#define PPP_ECHOTOUT 30 - -// Number of Retries <0-20> -// How many times PPP will try to retransmit data -// before giving up. Increase this value for links -// with low baud rates or high latency. -// Default: 3 -#define PPP_MAXRETRY 3 - -// Retry Timeout in seconds <1-10> -// If no response received within this time frame, -// PPP module will try to resend the data again. -// Default: 2 -#define PPP_RETRYTOUT 2 - -// -// SLIP Network Interface -// ======================== -// Enable or disable SLIP Network Interface -#define SLIP_ENABLE 0 - -// IP Address -// ============= -// Local Static IP Address -// Address byte 1 <0-255> -// Default: 192 -#define _IP1S 192 - -// Address byte 2 <0-255> -// Default: 168 -#define _IP2S 168 - -// Address byte 3 <0-255> -// Default: 225 -#define _IP3S 225 - -// Address byte 4 <0-255> -// Default: 1 -#define _IP4S 1 - -// -// Subnet mask -// ============== -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define _MSK1S 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define _MSK2S 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define _MSK3S 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define _MSK4S 0 - -// -// Primary DNS Server -// ===================== -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define _pDNS1S 194 - -// Address byte 2 <0-255> -// Default: 25 -#define _pDNS2S 25 - -// Address byte 3 <0-255> -// Default: 2 -#define _pDNS3S 2 - -// Address byte 4 <0-255> -// Default: 129 -#define _pDNS4S 129 - -// -// Secondary DNS Server -// ======================= -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define _sDNS1S 194 - -// Address byte 2 <0-255> -// Default: 25 -#define _sDNS2S 25 - -// Address byte 3 <0-255> -// Default: 2 -#define _sDNS3S 2 - -// Address byte 4 <0-255> -// Default: 130 -#define _sDNS4S 130 - -// -// Use Default Gateway on remote Network -// ======================================== -// This option only applies when both Ethernet and SLIP Dial-up -// are used. If checked, data that cannot be sent to local LAN -// is forwarded to Dial-up network instead. -#define SLIP_DEFGW 1 - -// -// UDP Sockets -// ============== -// Enable or disable UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUMSOCKS 20 - -// -// TCP Sockets -// ============== -// Enable or disable TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 5 -#define TCP_NUMSOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low_throughput networks. -// Default: 5 -#define TCP_MAXRETRY 20 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRYTOUT 4 - -// Default Connect Timeout in seconds <1-600> -// Default TCP Socket Keep Alive timeout. When it expires -// with no TCP data frame send, TCP Connection is closed. -// Default: 120 -#define TCP_DEFTOUT 120 - -// Maximum Segment Size <536-1460> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1460 -#define TCP_MAXSEGSZ 1460 - -/* TCP fixed timeouts */ -#define TCP_INIT_RETRY_TOUT 1 /* TCP initial Retransmit period in sec. */ -#define TCP_SYN_RETRY_TOUT 2 /* TCP SYN frame retransmit period in sec. */ -#define TCP_CONRETRY 7 /* Number of retries to establish a conn. */ - -// -// HTTP Server -// ============== -// Enable or disable HTTP Server -#define HTTP_ENABLE 0 - -// Number of HTTP Sessions <1-10> -// Number of simultaneously active HTTP Sessions. -// Default: 3 -#define HTTP_NUMSESS 3 - -// Port Number <1-65535> -// Listening port number. -// Default: 80 -#define HTTP_PORTNUM 80 - -// Server-Id header -// This value is optional. If specified, it overrides -// the default HTTP Server header from the library. -// Default: "" -#define HTTP_SRVID "" - -// Enable User Authentication -// When enabled, the user will have to authenticate -// himself by username and password before accessing -// any page on this Embedded WEB server. -#define HTTP_ENAUTH 1 - -// Authentication Realm -// Default: "Embedded WEB Server" -#define HTTP_AUTHREALM "Embedded WEB Server" - -// Authentication Username -// Default: "admin" -#define HTTP_AUTHUSER "admin" - -// Authentication Password -// Default: "" -#define HTTP_AUTHPASSW "" - -// -// -// Telnet Server -// ================ -// Enable or disable Telnet Server -#define TNET_ENABLE 0 - -// Number of Telnet Connections <1-10> -// Number of simultaneously active Telnet Connections. -// Default: 1 -#define TNET_NUMSESS 1 - -// Port Number <1-65535> -// Listening port number. -// Default: 23 -#define TNET_PORTNUM 23 - -// Idle Connection Timeout in seconds <0-3600> -// When timeout expires, the connection is closed. -// A value of 0 disables disconnection on timeout. -// Default: 120 -#define TNET_IDLETOUT 120 - -// Disable Echo -// When disabled, the server will not echo -// characters it receives. -// Default: Not disabled -#define TNET_NOECHO 0 - -// Enable User Authentication -// When enabled, the user will have to authenticate -// himself by username and password before access -// to the system is allowed. -#define TNET_ENAUTH 1 - -// Authentication Username -// Default: "admin" -#define TNET_AUTHUSER "admin" - -// Authentication Password -// Default: "" -#define TNET_AUTHPASSW "" - -// -// -// TFTP Server -// ============== -// Enable or disable TFTP Server -#define TFTP_ENABLE 0 - -// Number of TFTP Sessions <1-10> -// Number of simultaneously active TFTP Sessions -// Default: 1 -#define TFTP_NUMSESS 1 - -// Port Number <1-65535> -// Listening port number. -// Default: 69 -#define TFTP_PORTNUM 69 - -// Enable Firewall Support -// Use the same Port Number to receive -// requests and send answers to clients. -// Default: Not Enabled -#define TFTP_ENFWALL 0 - -// Inactive Session Timeout in seconds <5-120> -// When timeout expires TFTP Session is closed. -// Default: 15 -#define TFTP_DEFTOUT 15 - -// Number of Retries <1-10> -// How many times TFTP Server will try to -// retransmit the data before giving up. -// Default: 4 -#define TFTP_MAXRETRY 4 - -// -// TFTP Client -// ============== -// Enable or disable TFTP Client -#define TFTPC_ENABLE 0 - -// Block Size <128=>128 <256=>256 <512=>512 -// <1024=>1024 <1428=>1428 -// Size of transfer block in bytes. -// Default: 512 -#define TFTPC_BLOCKSZ 512 - -// Number of Retries <1-10> -// How many times TFTP Client will try to -// retransmit the data before giving up. -// Default: 4 -#define TFTPC_MAXRETRY 4 - -// Retry Timeout <2=>200 ms <5=>500 ms <10=>1 sec -// <20=>2 sec <50=>5 sec <100=>10 sec -// If data frame not acknowledged within this time frame, -// TFTP Client will try to resend the data again. -// Default: 500 ms -#define TFTPC_RETRYTO 5 - -// -// FTP Server -// ============== -// Enable or disable FTP Server -#define FTP_ENABLE 0 - -// Number of FTP Sessions <1-10> -// Number of simultaneously active FTP Sessions -// Default: 1 -#define FTP_NUMSESS 1 - -// Port Number <1-65535> -// Listening port number. -// Default: 21 -#define FTP_PORTNUM 21 - -// Welcome Message -// This value is optional. If specified, -// it overrides the default welcome message. -// Default: "" -#define FTP_WELMSG "" - -// Idle Session Timeout in seconds <0-3600> -// When timeout expires, the connection is closed. -// A value of 0 disables disconnection on timeout. -// Default: 120 -#define FTP_IDLETOUT 120 - -// Enable User Authentication -// When enabled, the user will have to authenticate -// himself by username and password before access -// to the system is allowed. -#define FTP_ENAUTH 1 - -// Authentication Username -// Default: "admin" -#define FTP_AUTHUSER "admin" - -// Authentication Password -// Default: "" -#define FTP_AUTHPASSW "" - -// -// -// FTP Client -// ============= -// Enable or disable FTP Client -#define FTPC_ENABLE 0 - -// Response Timeout in seconds <1-120> -// This is a time for FTP Client to wait for a response from -// the Server. If timeout expires, Client aborts operation. -// Default: 10 -#define FTPC_DEFTOUT 10 - -// Passive mode (PASV) -// The client initiates a data connection to the server. -// Default: Not passive (Active) -#define FTPC_PASVMODE 0 - -// -// DNS Client -// ============= -// Enable or disable DNS Client -#define DNS_ENABLE 1 - -// Cache Table size <5-100> -// Number of cached DNS host names/IP addresses -// Default: 20 -#define DNS_TABSIZE 20 - -// -// SMTP Client -// ============== -// Enable or disable SMTP Client -#define SMTP_ENABLE 0 - -// Response Timeout in seconds <5-120> -// This is a time for SMTP Client to wait for a response from -// SMTP Server. If timeout expires, Client aborts operation. -// Default: 20 -#define SMTP_DEFTOUT 20 - -// -// SNMP Agent -// ============= -// Enable or disable SNMP Agent -#define SNMP_ENABLE 0 - -// Community Name -// Defines where an SNMP message is destined for. -// Default: "public" -#define SNMP_COMMUNITY "public" - -// Port Number <1-65535> -// Listening port number. -// Default: 161 -#define SNMP_PORTNUM 161 - -// Trap Port Number <1-65535> -// Port number for Trap operations. -// Default: 162 -#define SNMP_TRAPPORT 162 - -// Trap Server -// ============== -// Trap Server IP Address -// Address byte 1 <0-255> -// Default: 192 -#define SNMP_TRAPIP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define SNMP_TRAPIP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define SNMP_TRAPIP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define SNMP_TRAPIP4 100 - -// -// -// BSD Socket Interface -// ======================= -// Enable or disable Berkeley Socket Programming Interface -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUMSOCKS 10 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SRVSOCKS 2 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RCVTOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_GETHOSTEN 1 - -// -//------------- <<< end of configuration section >>> ----------------------- - -/*---------------------------------------------------------------------------- - * Fatal Error Handler - *---------------------------------------------------------------------------*/ - -void sys_error (ERROR_CODE code) { - /* This function is called when a fatal error is encountered. The normal */ - /* program execution is not possible anymore. Add your crytical error .*/ - /* handler code here. */ - - switch (code) { - case ERR_MEM_ALLOC: - /* Out of memory. */ - break; - - case ERR_MEM_FREE: - /* Trying to release non existing memory block. */ - break; - - case ERR_MEM_CORRUPT: - /* Memory Link pointer is Corrupted. */ - /* More data written than the size of allocated mem block. */ - break; - - case ERR_MEM_LOCK: - /* Locked Memory management function (alloc/free) re-entered. */ - /* RTX multithread protection malfunctioning, not implemented */ - /* or interrupt disable is not functioning correctly. */ - break; - - case ERR_UDP_ALLOC: - /* Out of UDP Sockets. */ - break; - - case ERR_TCP_ALLOC: - /* Out of TCP Sockets. */ - break; - - case ERR_TCP_STATE: - /* TCP State machine in undefined state. */ - break; - } - - /* End-less loop */ - while (1); -} - -/*---------------------------------------------------------------------------- - * TCPnet Config Functions - *---------------------------------------------------------------------------*/ - -#define __NET_CONFIG__ - -#include - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/MDK-ARM/config/Net_Debug.c b/IDE/MDK-ARM/MDK-ARM/config/Net_Debug.c deleted file mode 100644 index f7a5c9af02..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/Net_Debug.c +++ /dev/null @@ -1,139 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - TCPnet - *---------------------------------------------------------------------------- - * Name: NET_DEBUG.C - * Purpose: Debug Module - * Rev.: V4.60 - *---------------------------------------------------------------------------- - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- - -// Print Time Stamp -// =================== -// Enable printing the time-info in debug messages -#define DBG_TIME 1 - -// TCPnet Debug Definitions -// =========================== -// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Memory debug messages -#define DBG_MEM 1 - -// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Ethernet debug messages -#define DBG_ETH 1 - -// PPP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off PPP debug messages -#define DBG_PPP 0 - -// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SLIP debug messages -#define DBG_SLIP 0 - -// ARP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ARP debug messages -#define DBG_ARP 1 - -// IP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IP debug messages -#define DBG_IP 1 - -// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ICMP debug messages -#define DBG_ICMP 1 - -// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IGMP debug messages -#define DBG_IGMP 1 - -// UDP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off UDP debug messages -#define DBG_UDP 1 - -// TCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TCP debug messages -#define DBG_TCP 2 - -// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off NetBIOS Name Service debug messages -#define DBG_NBNS 1 - -// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Host Configuration debug messages -#define DBG_DHCP 2 - -// DNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Domain Name Service debug messages -#define DBG_DNS 1 - -// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Management debug messages -#define DBG_SNMP 1 - -// BSD Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off BSD Interface debug messages -#define DBG_BSD 2 - -// -// Application Debug Definitions -// ================================ -// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Web Server debug messages -#define DBG_HTTP 1 - -// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Server debug messages -#define DBG_FTP 1 - -// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Client debug messages -#define DBG_FTPC 1 - -// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Telnet Server debug messages -#define DBG_TNET 1 - -// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Server debug messages -#define DBG_TFTP 1 - -// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Client debug messages -#define DBG_TFTPC 1 - -// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SMTP Client debug messages -#define DBG_SMTP 1 - -// - -//------------- <<< end of configuration section >>> ----------------------- - - -/*--------------------------- init_debug ------------------------------------*/ - -void init_debug (void) { - /* Add your code to initialize the Debug output. This is usually the */ - /* serial interface. The function is called at TCPnet system startup. */ - /* You may need to customize also the 'putchar()' function. */ - -} - - -/*---------------------------------------------------------------------------- - * TCPnet Debug Functions - *---------------------------------------------------------------------------*/ - -#define __NET_DEBUG__ - -#include - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c b/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c deleted file mode 100644 index a03892045b..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c +++ /dev/null @@ -1,205 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_CONFIG.C - * Purpose: Configuration of RTX Kernel for Cortex-M - * Rev.: V4.60 - *---------------------------------------------------------------------------- - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Task Configuration -// ===================== -// -// Number of concurrent running tasks <0-250> -// Define max. number of tasks that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 6 -#endif - -// Number of tasks with user-provided stack <0-250> -// Define the number of tasks that will use a bigger stack. -// The memory space for the stack is provided by the user. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 2 -#endif - -// Task stack size [bytes] <20-4096:8><#/4> -// Set the stack size for tasks which is assigned by the system. -// Default: 512 -#ifndef OS_STKSIZE - #define OS_STKSIZE 499 -#endif - -// Check for the stack overflow -// =============================== -// Include the stack checking code for a stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Run in privileged mode -// ========================= -// Run all Tasks in privileged mode. -// Default: Unprivileged -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// -// Tick Timer Configuration -// ============================= -// Hardware timer <0=> Core SysTick <1=> Peripheral Timer -// Define the on-chip timer used as a time-base for RTX. -// Default: Core SysTick -#ifndef OS_TIMER - #define OS_TIMER 0 -#endif - -// Timer clock value [Hz] <1-1000000000> -// Set the timer clock value for selected timer. -// Default: 6000000 (6MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 120000000 -#endif - -// Timer tick value [us] <1-1000000> -// Set the timer tick value for selected timer. -// Default: 10000 (10ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// Round-Robin Task switching -// ============================= -// Enable Round-Robin Task switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Define how long a task will execute before a task switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// Number of user timers <0-250> -// Define max. number of user timers that will run at the same time. -// Default: 0 (User timers disabled) -#ifndef OS_TIMERCNT - #define OS_TIMERCNT 1 -#endif - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the iterrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -__task void os_idle_demon (void) { - /* The idle demon is a system task, running when no other task is ready */ - /* to run. The 'os_xxx' function calls are not allowed from this task. */ - - for (;;) { - /* HERE: include optional user code to be executed when no task runs.*/ - } -} - -/*--------------------------- os_tick_init ----------------------------------*/ - -#if (OS_TIMER != 0) -int os_tick_init (void) { - /* Initialize hardware timer as system tick timer. */ - /* ... */ - return (-1); /* Return IRQ number of timer (0..239) */ -} -#endif - -/*--------------------------- os_tick_irqack --------------------------------*/ - -#if (OS_TIMER != 0) -void os_tick_irqack (void) { - /* Acknowledge timer interrupt. */ - /* ... */ -} -#endif - -/*--------------------------- os_tmr_call -----------------------------------*/ - -void os_tmr_call (U16 info) { - /* This function is called when the user timer has expired. Parameter */ - /* 'info' holds the value, defined when the timer was created. */ - - /* HERE: include optional user code to be executed on timeout. */ -} - - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (U32 err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/MDK-ARM/config/STM32_SWO.ini b/IDE/MDK-ARM/MDK-ARM/config/STM32_SWO.ini deleted file mode 100644 index c6512217a9..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2005-2009 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK-ARM/MDK-ARM/config/startup_stm32f2xx.s b/IDE/MDK-ARM/MDK-ARM/config/startup_stm32f2xx.s deleted file mode 100644 index c31ce19915..0000000000 --- a/IDE/MDK-ARM/MDK-ARM/config/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00001000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00009000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Conf/config-Crypt.h b/IDE/MDK5-ARM/Conf/config-Crypt.h new file mode 100644 index 0000000000..a11c3ef24c --- /dev/null +++ b/IDE/MDK5-ARM/Conf/config-Crypt.h @@ -0,0 +1,185 @@ +/* config-FS.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +// <<< Use Configuration Wizard in Context Menu >>> + +// wolfCrypt Configuration + +// Cert/Key Strage +// Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes) +#define MDK_CONF_CERT_BUFF 0 +#if MDK_CONF_CERT_BUFF== 1 +#define USE_CERT_BUFFERS_1024 +#elif MDK_CONF_CERT_BUFF == 2 +#define USE_CERT_BUFFERS_2048 +#endif +// + +// Crypt Algrithm + +// MD5, SHA, SHA-256, AES, RC4, ASN, RSA +// + +// MD2 +#define MDK_CONF_MD2 0 +#if MDK_CONF_MD2 == 1 +#define CYASSL_MD2 +#endif +// +// MD4 +#define MDK_CONF_MD4 1 +#if MDK_CONF_MD4 == 0 +#define NO_MD4 +#endif +// +// SHA-384 +// This has to be with SHA512 +#define MDK_CONF_SHA384 0 +#if MDK_CONF_SHA384 == 1 +#define CYASSL_SHA384 +#endif +// +// SHA-512 +#define MDK_CONF_SHA512 0 +#if MDK_CONF_SHA512 == 1 +#define CYASSL_SHA512 +#endif +// +// RIPEMD +#define MDK_CONF_RIPEMD 0 +#if MDK_CONF_RIPEMD == 1 +#define CYASSL_RIPEMD +#endif +// +// HMAC +#define MDK_CONF_HMAC 1 +#if MDK_CONF_HMAC == 0 +#define NO_HMAC +#endif +// +// HC128 +#define MDK_CONF_HC128 0 +#if MDK_CONF_HC128 == 1 +#define HAVE_HC128 +#endif +// +// RABBIT +#define MDK_CONF_RABBIT 1 +#if MDK_CONF_RABBI == 0 +#define NO_RABBIT +#endif +// + +// AEAD +#define MDK_CONF_AEAD 0 +#if MDK_CONF_AEAD == 1 +#define HAVE_AEAD +#endif +// +// DES3 +#define MDK_CONF_DES3 1 +#if MDK_CONF_DES3 == 0 +#define NO_DES3 +#endif +// +// CAMELLIA +#define MDK_CONF_CAMELLIA 0 +#if MDK_CONF_CAMELLIA == 1 +#define HAVE_CAMELLIA +#endif +// + +// DH +// need this for CYASSL_SERVER, OPENSSL_EXTRA +#define MDK_CONF_DH 1 +#if MDK_CONF_DH == 0 +#define NO_DH +#endif +// +// DSA +#define MDK_CONF_DSA 1 +#if MDK_CONF_DSA == 0 +#define NO_DSA +#endif +// +// PWDBASED +#define MDK_CONF_PWDBASED 1 +#if MDK_CONF_PWDBASED == 0 +#define NO_PWDBASED +#endif +// + +// ECC +#define MDK_CONF_ECC 0 +#if MDK_CONF_ECC == 1 +#define HAVE_ECC +#endif +// +// PSK +#define MDK_CONF_PSK 1 +#if MDK_CONF_PSK == 0 +#define NO_PSK +#endif +// +// AESCCM (Turn off Hardware Crypt) +#define MDK_CONF_AESCCM 0 +#if MDK_CONF_AESCCM == 1 +#define HAVE_AESCCM +#endif +// +// AESGCM (Turn off Hardware Crypt) +#define MDK_CONF_AESGCM 0 +#if MDK_CONF_AESGCM == 1 +#define HAVE_AESGCM +#define BUILD_AESGCM +#endif +// +// NTRU (need License, "crypto_ntru.h") +#define MDK_CONF_NTRU 0 +#if MDK_CONF_NTRU == 1 +#define HAVE_NTRU +#endif +// +// + +// Hardware Crypt (See document for usage) +// Hardware RNG +#define MDK_CONF_STM32F2_RNG 0 +#if MDK_CONF_STM32F2_RNG == 1 +#define STM32F2_RNG +#else + +#endif +// +// Hardware Crypt +#define MDK_CONF_STM32F2_CRYPTO 0 +#if MDK_CONF_STM32F2_CRYPTO == 1 +#define STM32F2_CRYPTO +#endif +// + +// + + + +// +// <<< end of configuration section >>> diff --git a/IDE/MDK5-ARM/Conf/config-CyaSSL.h b/IDE/MDK5-ARM/Conf/config-CyaSSL.h new file mode 100644 index 0000000000..02ba94bd4c --- /dev/null +++ b/IDE/MDK5-ARM/Conf/config-CyaSSL.h @@ -0,0 +1,144 @@ +/* config-RTX-TCP-FS.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/**** CyaSSL for KEIL-RL Configuration ****/ + +#define __CORTEX_M3__ +#define CYASSL_MDK_ARM +#define NO_WRITEV +#define NO_CYASSL_DIR +#define NO_MAIN_DRIVER + + +#define CYASSL_DER_LOAD +#define HAVE_NULL_CIPHER + +#define HAVE_KEIL_RTX +#define CYASSL_CMSIS_RTOS +#define CYASSL_KEIL_TCP_NET + + +// <<< Use Configuration Wizard in Context Menu >>> +// CyaSSL Configuration + +// SSL (Included by default) +// + +// TLS +#define MDK_CONF_TLS 1 +#if MDK_CONF_TLS == 0 +#define NO_TLS +#endif +// + +// CRL +#define MDK_CONF_DER_LOAD 0 +#if MDK_CONF_DER_LOAD == 1 +#define CYASSL_DER_LOAD +#endif +// +// OpenSSL Extra +#define MDK_CONF_OPENSSL_EXTRA 1 +#if MDK_CONF_OPENSSL_EXTRA == 1 +#define OPENSSL_EXTRA +#endif +// +// + +// Cert/Key Generation +// CertGen +#define MDK_CONF_CERT_GEN 0 +#if MDK_CONF_CERT_GEN == 1 +#define CYASSL_CERT_GEN +#endif +// +// KeyGen +#define MDK_CONF_KEY_GEN 0 +#if MDK_CONF_KEY_GEN == 1 +#define CYASSL_KEY_GEN +#endif +// +// + +// Others + +// Inline +#define MDK_CONF_INLINE 0 +#if MDK_CONF_INLINE == 0 +#define NO_INLINE +#endif +// +// Debug +// Debug Message +#define MDK_CONF_DebugMessage 0 +#if MDK_CONF_DebugMessage == 1 +#define DEBUG_CYASSL +#endif +// +// Check malloc +#define MDK_CONF_CheckMalloc 1 +#if MDK_CONF_CheckMalloc == 1 +#define CYASSL_MALLOC_CHECK +#endif +// + + +// +// ErrNo.h +#define MDK_CONF_ErrNo 0 +#if MDK_CONF_ErrNo == 1 +#define HAVE_ERRNO +#endif +// +// Error Strings +#define MDK_CONF_ErrorStrings 1 +#if MDK_CONF_ErrorStrings == 0 +#define NO_ERROR_STRINGS +#endif +// +// zlib (need "zlib.h") +#define MDK_CONF_LIBZ 0 +#if MDK_CONF_LIBZ == 1 +#define HAVE_LIBZ +#endif +// +// CAVIUM (need CAVIUM headers) +#define MDK_CONF_CAVIUM 0 +#if MDK_CONF_CAVIUM == 1 +#define HAVE_CAVIUM +#endif +// +// Small Stack +#define MDK_CONF_SmallStack 1 +#if MDK_CONF_SmallStack == 0 +#define NO_CYASSL_SMALL_STACK +#endif +// +// Use Fast Math +#define MDK_CONF_FASTMATH 0 +#if MDK_CONF_FASTMATH == 1 +#define USE_FAST_MATH +#endif +// +// + +// <<< end of configuration section >>> diff --git a/IDE/MDK5-ARM/Docs/CyaSSL-License.txt b/IDE/MDK5-ARM/Docs/CyaSSL-License.txt deleted file mode 100644 index 3a01f34204..0000000000 --- a/IDE/MDK5-ARM/Docs/CyaSSL-License.txt +++ /dev/null @@ -1,292 +0,0 @@ -LICENSE AGREEMENT - -The wolfSSL source code is subject to the U.S. Export Administration -Regulations and other U.S. law, and may not be exported or re-exported to -certain countries (currently Afghanistan, Cuba, Iran, Iraq, Libya, North -Korea, Sudan and Syria) or to persons or entities prohibited from receiving -U.S. exports (including Denied Parties, entities on the Bureau of Export -Administration Entity List, and Specially Designated Nationals). - ---- - - GNU GENERAL PUBLIC LICENSE - Version 2, June 1991 - - Copyright (C) 1989, 1991 Free Software Foundation, Inc., - 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - Everyone is permitted to copy and distribute verbatim copies - of this license document, but changing it is not allowed. - - Preamble - - The licenses for most software are designed to take away your -freedom to share and change it. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR -REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, -INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING -OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED -TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY -YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER -PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE -POSSIBILITY OF SUCH DAMAGES. - - END OF TERMS AND CONDITIONS - diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.h b/IDE/MDK5-ARM/Inc/cert_data.h similarity index 100% rename from IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.h rename to IDE/MDK5-ARM/Inc/cert_data.h diff --git a/IDE/MDK5-ARM/Inc/config.h b/IDE/MDK5-ARM/Inc/config.h new file mode 100644 index 0000000000..8cf08b1b45 --- /dev/null +++ b/IDE/MDK5-ARM/Inc/config.h @@ -0,0 +1,62 @@ +/* config.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#define __CORTEX_M3__ +#define CYASSL_MDK_ARM +#define CYASSL_MDK5 +#define CYASSL_CMSIS_RTOS + +#define NO_WRITEV +#define NO_CYASSL_DIR +#define BENCH_EMBEDDED + +#define CYASSL_DER_LOAD +#define HAVE_NULL_CIPHER +#define NO_MAIN_DRIVER + +#if defined(MDK_CONF_CYASSL) +#define CYASSL_MDK_SHELL +#include "config-Crypt.h" +#include "config-CyaSSL.h" +#elif defined(MDK_CONF_SimpleClient) +#include "config-Crypt.h" +#include "config-CyaSSL.h" +#elif defined(MDK_CONF_SimpleServer) +#include "config-Crypt.h" +#include "config-CyaSSL.h" +#elif defined(MDK_CONF_EchoClient) +#include "config-Crypt.h" +#include "config-CyaSSL.h" +#elif defined(MDK_CONF_EchoServer) +#include "config-Crypt.h" +#include "config-CyaSSL.h" +#elif defined(MDK_CONF_Benchmark) +#define SINGLE_THREADED +#define NO_INLINE +#include "config-Crypt.h" +#elif defined(MDK_CONF_CryptTest) +#define SINGLE_THREADED +#define NO_INLINE +#include "config-Crypt.h" + +#endif + + diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h b/IDE/MDK5-ARM/Inc/cyassl_MDK_ARM.h similarity index 100% rename from IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h rename to IDE/MDK5-ARM/Inc/cyassl_MDK_ARM.h diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt b/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt index e19c56403e..b929f9bc91 100644 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt @@ -1,7 +1,7 @@ This program is a simple benchmark of wolfCrypt library. In order to run this benchmark, copy -{PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +{PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. For benchmark configuration, refer config-Crypt.h. diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx index 8882715860..d5106490f7 100644 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx @@ -76,13 +76,30 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL - -REMAP -MPU + -REMAP -MPU DCM.DLL -pCM3 SARMCM3.DLL - -REMAP -MPU + -MPU TCM.DLL -pCM3 @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,7 +135,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -143,7 +162,7 @@ 0 UL2CM3 - UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F2xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.FLM) @@ -169,7 +188,7 @@ 0 1 0 - 1 + 0 0 0 1 @@ -209,8 +228,8 @@ 0 0 0 - 0 - 0 + 40 + 62 0 .\main.c main.c @@ -223,7 +242,7 @@ 1 0 0 - 32 + 0 0 0 0 @@ -249,14 +268,30 @@ 0 0 0 - 0 - 0 + 1 + 1 0 .\RTE\wolfSSL\config-Crypt.h config-Crypt.h 0 0 + + 2 + 4 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\RTE\wolfSSL\settings.h + settings.h + 0 + 0 + @@ -267,14 +302,14 @@ 0 3 - 4 + 5 5 0 0 0 0 - 1 - 1 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -284,27 +319,11 @@ - ::CMSIS - 0 + Devices + 1 0 0 - 1 - - 4 - 5 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib - RTX_CM3.lib - 1 - 0 - + 0 4 6 @@ -316,21 +335,13 @@ 0 0 0 - RTE\CMSIS\RTX_Conf_CM.c - RTX_Conf_CM.c - 1 + .\time-CortexM3-4.c + time-CortexM3-4.c + 0 0 - - - - ::Device - 0 - 0 - 0 - 1 - 5 + 4 7 1 0 @@ -340,11 +351,19 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 + .\time-dummy.c + time-dummy.c + 0 0 + + + + ::CMSIS + 1 + 0 + 0 + 1 5 8 @@ -353,18 +372,18 @@ 0 0 0 - 0 - 0 + 205 + 218 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c + RTE\CMSIS\RTX_Conf_CM.c + RTX_Conf_CM.c 1 0 5 9 - 5 + 4 0 0 0 @@ -372,21 +391,45 @@ 0 0 0 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + RTX_CM3.lib + 1 + 0 + + + + + ::Device + 1 + 0 + 0 + 1 + + 6 + 10 + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 RTE\Device\STM32F207IG\RTE_Device.h RTE_Device.h 1 0 - 5 - 10 + 6 + 11 2 0 0 0 0 - 0 - 0 + 166 + 179 0 RTE\Device\STM32F207IG\startup_stm32f2xx.s startup_stm32f2xx.s @@ -394,8 +437,8 @@ 0 - 5 - 11 + 6 + 12 1 0 0 @@ -409,6 +452,38 @@ 1 0 + + 6 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c + 1 + 0 + + + 6 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c + 1 + 0 + @@ -418,8 +493,8 @@ 0 1 - 6 - 12 + 7 + 15 1 0 0 @@ -428,7 +503,7 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c MCI_STM32F2xx.c 1 0 @@ -442,24 +517,8 @@ 0 1 - 7 - 13 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib - 1 - 0 - - - 7 - 14 + 8 + 16 1 0 0 @@ -474,8 +533,8 @@ 0 - 7 - 15 + 8 + 17 5 0 0 @@ -489,6 +548,22 @@ 1 0 + + 8 + 18 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib + 1 + 0 + @@ -498,8 +573,24 @@ 0 1 - 8 - 16 + 9 + 19 + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + RTE\wolfSSL\config-Crypt.h + config-Crypt.h + 1 + 0 + + + 9 + 20 5 0 0 @@ -508,77 +599,13 @@ 0 0 0 - RTE\wolfSSL\config-Crypt.h - config-Crypt.h + RTE\wolfSSL\settings.h + settings.h 1 0 - 8 - 17 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 8 - 18 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c - ssl-dummy.c - 1 - 0 - - - 8 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 8 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 8 + 9 21 1 0 @@ -588,13 +615,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c - arc4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c 1 0 - 8 + 9 22 1 0 @@ -604,13 +631,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c - asm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\ssl-dummy.c + ssl-dummy.c 1 0 - 8 + 9 23 1 0 @@ -620,13 +647,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c - asn.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c 1 0 - 8 + 9 24 1 0 @@ -636,13 +663,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c - blake2b.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c 1 0 - 8 + 9 25 1 0 @@ -652,13 +679,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c - camellia.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c 1 0 - 8 + 9 26 1 0 @@ -668,13 +695,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c - coding.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c 1 0 - 8 + 9 27 1 0 @@ -684,13 +711,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c - compress.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c 1 0 - 8 + 9 28 1 0 @@ -700,13 +727,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c - des3.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c 1 0 - 8 + 9 29 1 0 @@ -716,13 +743,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c - dh.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c 1 0 - 8 + 9 30 1 0 @@ -732,13 +759,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c - dsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c 1 0 - 8 + 9 31 1 0 @@ -748,13 +775,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c - ecc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c 1 0 - 8 + 9 32 1 0 @@ -764,13 +791,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c 1 0 - 8 + 9 33 1 0 @@ -780,13 +807,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c - error.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c 1 0 - 8 + 9 34 1 0 @@ -796,13 +823,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c - hc128.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c 1 0 - 8 + 9 35 1 0 @@ -812,13 +839,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c - hmac.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c 1 0 - 8 + 9 36 1 0 @@ -828,13 +855,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c - integer.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c 1 0 - 8 + 9 37 1 0 @@ -844,13 +871,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c - logging.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c 1 0 - 8 + 9 38 1 0 @@ -860,13 +887,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c - md2.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c 1 0 - 8 + 9 39 1 0 @@ -876,13 +903,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c - md4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c 1 0 - 8 + 9 40 1 0 @@ -892,13 +919,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c - md5.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c 1 0 - 8 + 9 41 1 0 @@ -908,13 +935,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c - memory.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c 1 0 - 8 + 9 42 1 0 @@ -924,13 +951,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c - misc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c 1 0 - 8 + 9 43 1 0 @@ -940,13 +967,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c - port.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c 1 0 - 8 + 9 44 1 0 @@ -956,13 +983,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c 1 0 - 8 + 9 45 1 0 @@ -972,13 +999,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c - rabbit.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c 1 0 - 8 + 9 46 1 0 @@ -988,13 +1015,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c - random.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c 1 0 - 8 + 9 47 1 0 @@ -1004,13 +1031,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c - ripemd.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c 1 0 - 8 + 9 48 1 0 @@ -1020,13 +1047,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c - rsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c 1 0 - 8 + 9 49 1 0 @@ -1036,13 +1063,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c - sha.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c 1 0 - 8 + 9 50 1 0 @@ -1052,13 +1079,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c - sha256.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c 1 0 - 8 + 9 51 1 0 @@ -1068,13 +1095,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c - sha512.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c 1 0 - 8 + 9 52 1 0 @@ -1084,7 +1111,55 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 9 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 9 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 9 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c tfm.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx index 1c54758bc4..47b0e21aa2 100644 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx @@ -102,11 +102,11 @@ SARMCM3.DLL - -REMAP -MPU + -REMAP -MPU DCM.DLL -pCM3 SARMCM3.DLL - -REMAP -MPU + -MPU TCM.DLL -pCM3 @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,9 +355,11 @@ 0 0 0 + 0 + 0 - HAVE_CONFIG_H MDK_CONF_Benchmark CYASSL_STM32F2xx + HAVE_CONFIG_H MDK_CONF_Benchmark @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -418,6 +424,11 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + settings.h + 5 + .\RTE\wolfSSL\settings.h + @@ -431,33 +442,38 @@ - ::CMSIS + Devices - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + time-CortexM3-4.c + 1 + .\time-CortexM3-4.c + + time-dummy.c + 1 + .\time-dummy.c + + + + + ::CMSIS + RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -473,6 +489,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -481,18 +507,13 @@ MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -503,6 +524,11 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + @@ -513,185 +539,185 @@ 5 RTE\wolfSSL\config-Crypt.h + + settings.h + 5 + RTE\wolfSSL\settings.h + cyassl_MDK_ARM.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c ssl-dummy.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c - - - time-STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\ssl-dummy.c aes.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c arc4.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c asm.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c asn.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c blake2b.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c camellia.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c coding.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c compress.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c des3.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c dh.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c dsa.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c ecc.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c ecc_fp.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c error.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c hc128.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c hmac.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c integer.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c logging.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c md2.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c md4.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c md5.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c memory.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c misc.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c port.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c pwdbased.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c rabbit.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c random.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c ripemd.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c rsa.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c sha.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c sha256.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c sha512.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c tfm.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c @@ -701,13 +727,13 @@ - + - + @@ -721,20 +747,20 @@ - - + + - - + + - - + + @@ -763,20 +789,14 @@ - - + + - - - - - - - - + + @@ -785,8 +805,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -897,20 +917,28 @@ - + RTE\wolfSSL\config-Crypt.h - - + + RTE\wolfSSL\config.h - - + + + + RTE\wolfSSL\settings.h + + + + + + diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index af8fdc4d57..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 6 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 50 -#endif - -// Main Thread stack size [bytes] <64-10000:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 1500 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 0 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 0 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-4096:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 2648e44d43..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 0 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index eae6859ddb..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00009000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h deleted file mode 100644 index aa51462ab1..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h +++ /dev/null @@ -1,19 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'CryptBenchmark' - * Target: 'CryptBenchmark' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..a506755ff0 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/wolfSSL/settings.h @@ -0,0 +1,667 @@ +/* settings.h + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using PIC32MZ Crypto Engine */ +/* #define CYASSL_MICROCHIP_PIC32MZ */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + +/* Uncomment next line if using LwIP native TCP socket settings */ +/* #define HAVE_LWIP_NATIVE */ + +/* Uncomment next line if building for EROAD */ +/* #define CYASSL_EROAD */ + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef CYASSL_USER_SETTINGS + #include +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */ + #define CYASSL_LWIP + #define NO_WRITEV + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_FILESYSTEM +#endif + +#ifdef MICROCHIP_PIC32 + /* #define CYASSL_MICROCHIP_PIC32MZ */ + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef CYASSL_MICROCHIP_PIC32MZ + #define CYASSL_PIC32MZ_CE + #define CYASSL_PIC32MZ_CRYPT + #define HAVE_AES_ENGINE + #define CYASSL_PIC32MZ_RNG + /* #define CYASSL_PIC32MZ_HASH */ + #define CYASSL_AES_COUNTER + #define HAVE_AESGCM + #define NO_BIG_INT + +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "system/system_services.h" + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define CYASSL_USER_IO + #define NO_FILESYSTEM + #define NO_CERT + #define USE_CERT_BUFFERS_1024 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define HAVE_ECC + #define NO_SESSION_CACHE + #define CYASSL_CMSIS_RTOS +#endif + + +#ifdef CYASSL_EROAD + #define FREESCALE_MQX + #define FREESCALE_MMCAU + #define SINGLE_THREADED + #define NO_STDIO_FILESYSTEM + #define CYASSL_LEANPSK + #define HAVE_NULL_CIPHER + #define NO_OLD_TLS + #define NO_ASN + #define NO_BIG_INT + #define NO_RSA + #define NO_DSA + #define NO_DH + #define NO_CERTS + #define NO_PWDBASED + #define NO_DES3 + #define NO_MD4 + #define NO_RC4 + #define NO_MD5 + #define NO_SESSION_CACHE + #define NO_MAIN_DRIVER +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) && !defined(CYASSL_EROAD) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c index 50351fafa5..2cccd362a3 100644 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c @@ -85,6 +85,7 @@ void bench_rabbit(void); void bench_aes(int); void bench_aesgcm(void); void bench_aesccm(void); +void bench_aesctr(void); void bench_camellia(void); void bench_md5(void); @@ -155,6 +156,11 @@ int benchmark_test(void *args) #ifdef HAVE_AESGCM bench_aesgcm(); #endif + +#ifdef CYASSL_AES_COUNTER + bench_aesctr(); +#endif + #ifdef HAVE_AESCCM bench_aesccm(); #endif @@ -219,23 +225,31 @@ int benchmark_test(void *args) #ifdef BENCH_EMBEDDED -const int numBlocks = 25; /* how many kB/megs to test (en/de)cryption */ -const char blockType[] = "kB"; /* used in printf output */ -const int times = 1; /* public key iterations */ +enum BenchmarkBounds { + numBlocks = 25, /* how many kB to test (en/de)cryption */ + ntimes = 1, + genTimes = 5, /* public key iterations */ + agreeTimes = 5 +}; +static const char blockType[] = "kB"; /* used in printf output */ #else -const int numBlocks = 5; -const char blockType[] = "megs"; -const int times = 100; +enum BenchmarkBounds { + numBlocks = 5, /* how many megs to test (en/de)cryption */ + ntimes = 100, + genTimes = 100, + agreeTimes = 100 +}; +static const char blockType[] = "megs"; /* used in printf output */ #endif -const byte key[] = +static const byte key[] = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 }; -const byte iv[] = +static const byte iv[] = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, @@ -246,11 +260,11 @@ const byte iv[] = /* use kB instead of mB for embedded benchmarking */ #ifdef BENCH_EMBEDDED -byte plain [1024]; -byte cipher[1024]; +static byte plain [1024]; +static byte cipher[1024]; #else -byte plain [1024*1024]; -byte cipher[1024*1024]; +static byte plain [1024*1024]; +static byte cipher[1024*1024]; #endif @@ -260,13 +274,20 @@ void bench_aes(int show) Aes enc; double start, total, persec; int i; + int ret; #ifdef HAVE_CAVIUM - if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) + if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) { printf("aes init cavium failed\n"); + return; + } #endif - AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION); + ret = AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION); + if (ret != 0) { + printf("AesSetKey failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -281,7 +302,7 @@ void bench_aes(int show) #endif if (show) - printf("AES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("AES %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); #ifdef HAVE_CAVIUM AesFreeCavium(&enc); @@ -290,8 +311,10 @@ void bench_aes(int show) #endif -byte additional[13]; -byte tag[16]; +#if defined(HAVE_AESGCM) || defined(HAVE_AESCCM) + static byte additional[13]; + static byte tag[16]; +#endif #ifdef HAVE_AESGCM @@ -316,11 +339,38 @@ void bench_aesgcm(void) persec = persec / 1024; #endif - printf("AES-GCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("AES-GCM %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif +#ifdef CYASSL_AES_COUNTER +void bench_aesctr(void) +{ + Aes enc; + double start, total, persec; + int i; + + AesSetKeyDirect(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesCtrEncrypt(&enc, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("AES-CTR %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + #ifdef HAVE_AESCCM void bench_aesccm(void) @@ -344,7 +394,7 @@ void bench_aesccm(void) persec = persec / 1024; #endif - printf("AES-CCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("AES-CCM %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -355,9 +405,13 @@ void bench_camellia(void) { Camellia cam; double start, total, persec; - int i; + int i, ret; - CamelliaSetKey(&cam, key, 16, iv); + ret = CamelliaSetKey(&cam, key, 16, iv); + if (ret != 0) { + printf("CamelliaSetKey failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -371,7 +425,7 @@ void bench_camellia(void) persec = persec / 1024; #endif - printf("Camellia %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("Camellia %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -382,13 +436,17 @@ void bench_des(void) { Des3 enc; double start, total, persec; - int i; + int i, ret; #ifdef HAVE_CAVIUM if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) printf("des3 init cavium failed\n"); #endif - Des3_SetKey(&enc, key, iv, DES_ENCRYPTION); + ret = Des3_SetKey(&enc, key, iv, DES_ENCRYPTION); + if (ret != 0) { + printf("Des3_SetKey failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -402,7 +460,7 @@ void bench_des(void) persec = persec / 1024; #endif - printf("3DES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("3DES %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); #ifdef HAVE_CAVIUM Des3_FreeCavium(&enc); @@ -436,7 +494,7 @@ void bench_arc4(void) persec = persec / 1024; #endif - printf("ARC4 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("ARC4 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); #ifdef HAVE_CAVIUM Arc4FreeCavium(&enc); @@ -465,7 +523,7 @@ void bench_hc128(void) persec = persec / 1024; #endif - printf("HC128 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("HC128 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* HAVE_HC128 */ @@ -491,7 +549,7 @@ void bench_rabbit(void) persec = persec / 1024; #endif - printf("RABBIT %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("RABBIT %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* NO_RABBIT */ @@ -520,7 +578,7 @@ void bench_md5(void) persec = persec / 1024; #endif - printf("MD5 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("MD5 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* NO_MD5 */ @@ -532,9 +590,13 @@ void bench_sha(void) Sha hash; byte digest[SHA_DIGEST_SIZE]; double start, total, persec; - int i; + int i, ret; - InitSha(&hash); + ret = InitSha(&hash); + if (ret != 0) { + printf("InitSha failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -549,7 +611,7 @@ void bench_sha(void) persec = persec / 1024; #endif - printf("SHA %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("SHA %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* NO_SHA */ @@ -561,15 +623,28 @@ void bench_sha256(void) Sha256 hash; byte digest[SHA256_DIGEST_SIZE]; double start, total, persec; - int i; + int i, ret; - InitSha256(&hash); + ret = InitSha256(&hash); + if (ret != 0) { + printf("InitSha256 failed, ret = %d\n", ret); + return; + } start = current_time(1); - for(i = 0; i < numBlocks; i++) - Sha256Update(&hash, plain, sizeof(plain)); + for(i = 0; i < numBlocks; i++) { + ret = Sha256Update(&hash, plain, sizeof(plain)); + if (ret != 0) { + printf("Sha256Update failed, ret = %d\n", ret); + return; + } + } - Sha256Final(&hash, digest); + ret = Sha256Final(&hash, digest); + if (ret != 0) { + printf("Sha256Final failed, ret = %d\n", ret); + return; + } total = current_time(0) - start; persec = 1 / total * numBlocks; @@ -578,7 +653,7 @@ void bench_sha256(void) persec = persec / 1024; #endif - printf("SHA-256 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("SHA-256 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -589,15 +664,28 @@ void bench_sha512(void) Sha512 hash; byte digest[SHA512_DIGEST_SIZE]; double start, total, persec; - int i; + int i, ret; - InitSha512(&hash); + ret = InitSha512(&hash); + if (ret != 0) { + printf("InitSha512 failed, ret = %d\n", ret); + return; + } start = current_time(1); - for(i = 0; i < numBlocks; i++) - Sha512Update(&hash, plain, sizeof(plain)); - - Sha512Final(&hash, digest); + for(i = 0; i < numBlocks; i++) { + ret = Sha512Update(&hash, plain, sizeof(plain)); + if (ret != 0) { + printf("Sha512Update failed, ret = %d\n", ret); + return; + } + } + + ret = Sha512Final(&hash, digest); + if (ret != 0) { + printf("Sha512Final failed, ret = %d\n", ret); + return; + } total = current_time(0) - start; persec = 1 / total * numBlocks; @@ -606,7 +694,7 @@ void bench_sha512(void) persec = persec / 1024; #endif - printf("SHA-512 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("SHA-512 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -634,7 +722,7 @@ void bench_ripemd(void) persec = persec / 1024; #endif - printf("RIPEMD %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("RIPEMD %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -646,15 +734,28 @@ void bench_blake2(void) Blake2b b2b; byte digest[64]; double start, total, persec; - int i; + int i, ret; - InitBlake2b(&b2b, 64); + ret = InitBlake2b(&b2b, 64); + if (ret != 0) { + printf("InitBlake2b failed, ret = %d\n", ret); + return; + } start = current_time(1); - for(i = 0; i < numBlocks; i++) - Blake2bUpdate(&b2b, plain, sizeof(plain)); + for(i = 0; i < numBlocks; i++) { + ret = Blake2bUpdate(&b2b, plain, sizeof(plain)); + if (ret != 0) { + printf("Blake2bUpdate failed, ret = %d\n", ret); + return; + } + } - Blake2bFinal(&b2b, digest, 64); + ret = Blake2bFinal(&b2b, digest, 64); + if (ret != 0) { + printf("Blake2bFinal failed, ret = %d\n", ret); + return; + } total = current_time(0) - start; persec = 1 / total * numBlocks; @@ -663,7 +764,7 @@ void bench_blake2(void) persec = persec / 1024; #endif - printf("BLAKE2b %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("BLAKE2b %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -671,7 +772,7 @@ void bench_blake2(void) #if !defined(NO_RSA) || !defined(NO_DH) \ || defined(CYASSL_KEYGEN) || defined(HAVE_ECC) -RNG rng; +static RNG rng; #endif #ifndef NO_RSA @@ -680,7 +781,7 @@ RNG rng; #if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && \ defined(CYASSL_MDK_SHELL) static char *certRSAname = "certs/rsa2048.der" ; -void set_Bench_RSA_File(char * cert) { certRSAname = cert ; } +static void set_Bench_RSA_File(char * cert) { certRSAname = cert ; } /* set by shell command */ #elif defined(CYASSL_MDK_SHELL) /* nothing */ @@ -733,20 +834,24 @@ void bench_rsa(void) printf("InitRNG failed\n"); return; } - InitRsaKey(&rsaKey, 0); + ret = InitRsaKey(&rsaKey, 0); + if (ret < 0) { + printf("InitRsaKey failed\n"); + return; + } ret = RsaPrivateKeyDecode(tmp, &idx, &rsaKey, (word32)bytes); start = current_time(1); - for (i = 0; i < times; i++) + for (i = 0; i < ntimes; i++) ret = RsaPublicEncrypt(message,len,enc,sizeof(enc), &rsaKey, &rng); total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("RSA %d encryption took %6.2f milliseconds, avg over %d" - " iterations\n", rsaKeySz, milliEach, times); + printf("RSA %d encryption took %6.3f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, ntimes); if (ret < 0) { printf("Rsa Public Encrypt failed\n"); @@ -755,17 +860,17 @@ void bench_rsa(void) start = current_time(1); - for (i = 0; i < times; i++) { + for (i = 0; i < ntimes; i++) { byte out[512]; /* for up to 4096 bit */ RsaPrivateDecrypt(enc, (word32)ret, out, sizeof(out), &rsaKey); } total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("RSA %d decryption took %6.2f milliseconds, avg over %d" - " iterations\n", rsaKeySz, milliEach, times); + printf("RSA %d decryption took %6.3f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, ntimes); FreeRsaKey(&rsaKey); #ifdef HAVE_CAVIUM @@ -794,7 +899,7 @@ void bench_dh(void) int i, ret; byte tmp[1024]; size_t bytes; - word32 idx = 0, pubSz, privSz, pubSz2, privSz2, agreeSz; + word32 idx = 0, pubSz, privSz = 0, pubSz2, privSz2, agreeSz; byte pub[256]; /* for 2048 bit */ byte priv[256]; /* for 2048 bit */ @@ -843,28 +948,28 @@ void bench_dh(void) start = current_time(1); - for (i = 0; i < times; i++) + for (i = 0; i < ntimes; i++) DhGenerateKeyPair(&dhKey, &rng, priv, &privSz, pub, &pubSz); total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("DH %d key generation %6.2f milliseconds, avg over %d" - " iterations\n", dhKeySz, milliEach, times); + printf("DH %d key generation %6.3f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, ntimes); DhGenerateKeyPair(&dhKey, &rng, priv2, &privSz2, pub2, &pubSz2); start = current_time(1); - for (i = 0; i < times; i++) + for (i = 0; i < ntimes; i++) DhAgree(&dhKey, agree, &agreeSz, priv, privSz, pub2, pubSz2); total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("DH %d key agreement %6.2f milliseconds, avg over %d" - " iterations\n", dhKeySz, milliEach, times); + printf("DH %d key agreement %6.3f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, ntimes); #if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) fclose(file); @@ -879,7 +984,6 @@ void bench_rsaKeyGen(void) RsaKey genKey; double start, total, each, milliEach; int i; - const int genTimes = 5; /* 1024 bit */ start = current_time(1); @@ -894,7 +998,7 @@ void bench_rsaKeyGen(void) each = total / genTimes; /* per second */ milliEach = each * 1000; /* millisconds */ printf("\n"); - printf("RSA 1024 key generation %6.2f milliseconds, avg over %d" + printf("RSA 1024 key generation %6.3f milliseconds, avg over %d" " iterations\n", milliEach, genTimes); /* 2048 bit */ @@ -909,7 +1013,7 @@ void bench_rsaKeyGen(void) total = current_time(0) - start; each = total / genTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("RSA 2048 key generation %6.2f milliseconds, avg over %d" + printf("RSA 2048 key generation %6.3f milliseconds, avg over %d" " iterations\n", milliEach, genTimes); } #endif /* CYASSL_KEY_GEN */ @@ -920,7 +1024,6 @@ void bench_eccKeyGen(void) ecc_key genKey; double start, total, each, milliEach; int i, ret; - const int genTimes = 5; ret = InitRng(&rng); if (ret < 0) { @@ -939,7 +1042,7 @@ void bench_eccKeyGen(void) each = total / genTimes; /* per second */ milliEach = each * 1000; /* millisconds */ printf("\n"); - printf("ECC 256 key generation %6.2f milliseconds, avg over %d" + printf("ECC 256 key generation %6.3f milliseconds, avg over %d" " iterations\n", milliEach, genTimes); } @@ -949,11 +1052,10 @@ void bench_eccKeyAgree(void) ecc_key genKey, genKey2; double start, total, each, milliEach; int i, ret; - const int agreeTimes = 5; byte shared[1024]; byte sig[1024]; byte digest[32]; - word32 x; + word32 x = 0; ecc_init(&genKey); ecc_init(&genKey2); @@ -990,12 +1092,12 @@ void bench_eccKeyAgree(void) total = current_time(0) - start; each = total / agreeTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("EC-DHE key agreement %6.2f milliseconds, avg over %d" + printf("EC-DHE key agreement %6.3f milliseconds, avg over %d" " iterations\n", milliEach, agreeTimes); /* make dummy digest */ for (i = 0; i < (int)sizeof(digest); i++) - digest[i] = i; + digest[i] = (byte)i; start = current_time(1); @@ -1012,7 +1114,7 @@ void bench_eccKeyAgree(void) total = current_time(0) - start; each = total / agreeTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("EC-DSA sign time %6.2f milliseconds, avg over %d" + printf("EC-DSA sign time %6.3f milliseconds, avg over %d" " iterations\n", milliEach, agreeTimes); start = current_time(1); @@ -1029,7 +1131,7 @@ void bench_eccKeyAgree(void) total = current_time(0) - start; each = total / agreeTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("EC-DSA verify time %6.2f milliseconds, avg over %d" + printf("EC-DSA verify time %6.3f milliseconds, avg over %d" " iterations\n", milliEach, agreeTimes); ecc_free(&genKey2); @@ -1045,13 +1147,13 @@ void bench_eccKeyAgree(void) double current_time(int reset) { - (void)reset; - static int init = 0; static LARGE_INTEGER freq; LARGE_INTEGER count; + (void)reset; + if (!init) { QueryPerformanceFrequency(&freq); init = 1; @@ -1063,44 +1165,58 @@ void bench_eccKeyAgree(void) } #elif defined MICROCHIP_PIC32 - - #include + #if defined(CYASSL_MICROCHIP_PIC32MZ) + #define CLOCK 8000000.0 + #else + #include + #define CLOCK 4000000.0 + #endif double current_time(int reset) { - /* NOTE: core timer tick rate = 40 Mhz, 1 tick = 25 ns */ - unsigned int ns; - /* should we reset our timer back to zero? Helps prevent timer - rollover */ - if (reset) { WriteCoreTimer(0); } /* get timer in ns */ - ns = ReadCoreTimer() * 25; + ns = ReadCoreTimer(); /* return seconds as a double */ - return ( ns / 1000000000.0 ); + return ( ns / CLOCK * 2.0); } - + #elif defined CYASSL_MDK_ARM + extern double current_time(int reset) ; + +#elif defined FREERTOS + + double current_time(int reset) + { + (void) reset; + + portTickType tickCount; + + /* tick count == ms, if configTICK_RATE_HZ is set to 1000 */ + tickCount = xTaskGetTickCount(); + return (double)tickCount / 1000; + } + #else #include double current_time(int reset) { - (void) reset; - struct timeval tv; + + (void)reset; + gettimeofday(&tv, 0); return (double)tv.tv_sec + (double)tv.tv_usec / 1000000; } #endif /* _WIN32 */ - diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c index 2786027b1d..a89c9ce130 100644 --- a/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c @@ -62,8 +62,8 @@ int main() { void * arg = NULL ; - init_time() ; init_filesystem (); + printf("=== Start: Crypt Benchmark ===\n") ; benchmark_test(arg) ; printf("=== End: Crypt Benchmark ===\n") ; diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/time-CortexM3-4.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/time-CortexM3-4.c new file mode 100644 index 0000000000..46712b34cd --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/time-CortexM3-4.c @@ -0,0 +1,41 @@ +/* time-STM32F2.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + + +#include +#define DWT ((DWT_Type *) (0xE0001000UL) ) +typedef struct +{ + uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +} DWT_Type; + +extern uint32_t SystemCoreClock ; + +double current_time(int reset) +{ + if(reset) DWT->CYCCNT = 0 ; + return ((double)DWT->CYCCNT/SystemCoreClock) ; +} diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/time-dummy.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/time-dummy.c new file mode 100644 index 0000000000..2525eba38b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/time-dummy.c @@ -0,0 +1,34 @@ +/* time-dummy.c.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + return(&date) ; +} + +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt b/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt index 5d4a8312e4..886be85b85 100644 --- a/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt @@ -1,9 +1,9 @@ This program is a simple test suite of wolfCrypt library. In order to run this test suite, copy -{PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +{PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. -For test configuration, refer config-Crypt.h. +For selecting test crypt algorism options, refer config-Crypt.h. For the hardware crypt on config-Crypt.h, download STSW-STM32062: STM32F2xx standard peripherals library at diff --git a/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx index a7474ba71c..0f4bcddf25 100644 --- a/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx +++ b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx @@ -76,6 +76,23 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL -REMAP -MPU @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,10 +135,15 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL + + 0 + DLGUARM + + 0 DLGTARM @@ -133,12 +157,7 @@ 0 ULP2CM3 - -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm) - - - 0 - DLGUARM - + -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO3 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm) 0 @@ -147,20 +166,6 @@ - - - 1 - 8 - tmp - - - - - 2 - 8 - 0x8004dc8 - - 0 @@ -185,7 +190,7 @@ 0 0 1 - 1 + 0 0 0 0 @@ -209,8 +214,8 @@ 0 0 0 - 0 - 0 + 45 + 65 0 .\main.c main.c @@ -233,6 +238,22 @@ 0 0 + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\cert_data.c + cert_data.c + 0 + 0 + @@ -243,7 +264,7 @@ 0 2 - 3 + 4 5 0 0 @@ -257,24 +278,40 @@ 0 0 - - - - Documentation - 1 - 0 - 0 - 0 - 3 - 4 + 2 + 5 5 0 0 0 0 - 1 - 1 + 0 + 0 + 0 + .\RTE\wolfSSL\settings.h + settings.h + 0 + 0 + + + + + Documentation + 0 + 0 + 0 + 0 + + 3 + 6 + 5 + 0 + 0 + 0 + 0 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -291,7 +328,23 @@ 1 4 - 5 + 7 + 1 + 0 + 0 + 0 + 0 + 212 + 218 + 0 + RTE\CMSIS\RTX_Conf_CM.c + RTX_Conf_CM.c + 1 + 0 + + + 4 + 8 4 0 0 @@ -300,27 +353,11 @@ 0 0 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib RTX_CM3.lib 1 0 - - 4 - 6 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RTE\CMSIS\RTX_Conf_CM.c - RTX_Conf_CM.c - 1 - 0 - @@ -329,38 +366,6 @@ 0 0 1 - - 5 - 7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 - 0 - - - 5 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c - 1 - 0 - 5 9 @@ -385,8 +390,8 @@ 0 0 0 - 0 - 0 + 163 + 169 0 RTE\Device\STM32F207IG\startup_stm32f2xx.s startup_stm32f2xx.s @@ -409,6 +414,38 @@ 1 0 + + 5 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c + 1 + 0 + + + 5 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c + 1 + 0 + @@ -419,7 +456,7 @@ 1 6 - 12 + 14 1 0 0 @@ -428,7 +465,7 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c MCI_STM32F2xx.c 1 0 @@ -443,23 +480,7 @@ 1 7 - 13 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib - 1 - 0 - - - 7 - 14 + 15 1 0 0 @@ -475,7 +496,7 @@ 7 - 15 + 16 5 0 0 @@ -489,6 +510,22 @@ 1 0 + + 7 + 17 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib + 1 + 0 + @@ -497,569 +534,9 @@ 0 0 1 - - 8 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 8 - 17 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c - ssl-dummy.c - 1 - 0 - 8 18 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 8 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 8 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - arc4.c - 1 - 0 - - - 8 - 21 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - asm.c - 1 - 0 - - - 8 - 22 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - asn.c - 1 - 0 - - - 8 - 23 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - blake2b.c - 1 - 0 - - - 8 - 24 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - camellia.c - 1 - 0 - - - 8 - 25 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - coding.c - 1 - 0 - - - 8 - 26 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - compress.c - 1 - 0 - - - 8 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - des3.c - 1 - 0 - - - 8 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - dh.c - 1 - 0 - - - 8 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - dsa.c - 1 - 0 - - - 8 - 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - ecc.c - 1 - 0 - - - 8 - 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c - 1 - 0 - - - 8 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - error.c - 1 - 0 - - - 8 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - hc128.c - 1 - 0 - - - 8 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - hmac.c - 1 - 0 - - - 8 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - integer.c - 1 - 0 - - - 8 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - logging.c - 1 - 0 - - - 8 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - md2.c - 1 - 0 - - - 8 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - md4.c - 1 - 0 - - - 8 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - md5.c - 1 - 0 - - - 8 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - memory.c - 1 - 0 - - - 8 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - misc.c - 1 - 0 - - - 8 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c - 1 - 0 - - - 8 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - rabbit.c - 1 - 0 - - - 8 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - random.c - 1 - 0 - - - 8 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - ripemd.c - 1 - 0 - - - 8 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - rsa.c - 1 - 0 - - - 8 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - sha.c - 1 - 0 - - - 8 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - sha256.c - 1 - 0 - - - 8 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - sha512.c - 1 - 0 - - - 8 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - tfm.c - 1 - 0 - - - 8 - 51 5 0 0 @@ -1075,7 +552,7 @@ 8 - 52 + 19 5 0 0 @@ -1084,8 +561,584 @@ 0 0 0 - RTE\wolfSSL\config.h - config.h + RTE\wolfSSL\settings.h + settings.h + 1 + 0 + + + 8 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c + 1 + 0 + + + 8 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\ssl-dummy.c + ssl-dummy.c + 1 + 0 + + + 8 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c + 1 + 0 + + + 8 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c + 1 + 0 + + + 8 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c + 1 + 0 + + + 8 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c + 1 + 0 + + + 8 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c + 1 + 0 + + + 8 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c + 1 + 0 + + + 8 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c + 1 + 0 + + + 8 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c + 1 + 0 + + + 8 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c + 1 + 0 + + + 8 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c + 1 + 0 + + + 8 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c + 1 + 0 + + + 8 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c + 1 + 0 + + + 8 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c + 1 + 0 + + + 8 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c + 1 + 0 + + + 8 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c + 1 + 0 + + + 8 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c + 1 + 0 + + + 8 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c + 1 + 0 + + + 8 + 39 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c + 1 + 0 + + + 8 + 40 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c + 1 + 0 + + + 8 + 41 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c + 1 + 0 + + + 8 + 42 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c + 1 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c + 1 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c + 1 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c + 1 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.2\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c + time-STM32F2xx.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx index 6db3f16fa0..89b16583db 100644 --- a/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx +++ b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,9 +355,11 @@ 0 0 0 + 0 + 0 - HAVE_CONFIG_H MDK_CONF_CryptTest CYASSL_STM32F2xx __DBG_ITM + HAVE_CONFIG_H MDK_CONF_CryptTest @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -408,6 +414,11 @@ 1 .\test.c + + cert_data.c + 1 + .\cert_data.c + @@ -418,6 +429,11 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + settings.h + 5 + .\RTE\wolfSSL\settings.h + @@ -433,31 +449,21 @@ ::CMSIS - - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib - RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -473,6 +479,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -481,18 +497,13 @@ MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -503,195 +514,205 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + ::wolfSSL - - cyassl_MDK_ARM.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - - - ssl-dummy.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c - - - time-STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - - - aes.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - - - arc4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - - - asm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - - - asn.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - - - blake2b.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - - - camellia.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - - - coding.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - - - compress.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - - - des3.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - - - dh.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - - - dsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - - - ecc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - - - ecc_fp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - - - error.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - - - hc128.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - - - hmac.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - - - integer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - - - logging.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - - - md2.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - - - md4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - - - md5.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - - - memory.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - - - misc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - - - pwdbased.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - - - rabbit.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - - - random.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - - - ripemd.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - - - rsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - - - sha.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - - - sha256.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - - - sha512.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - - - tfm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - config-Crypt.h 5 RTE\wolfSSL\config-Crypt.h - config.h + settings.h 5 - RTE\wolfSSL\config.h + RTE\wolfSSL\settings.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + + + ssl-dummy.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\ssl-dummy.c + + + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + + + time-STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.2\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c @@ -763,20 +784,20 @@ - - + + - - + + - - + + @@ -785,8 +806,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -875,40 +896,46 @@ RTE\Other\config-Crypt.h - - + + RTE\Other\config-FS.h - - + + RTE\Other\config-RTX-TCP-FS.h - - + + RTE\Other\config.h - - + + - + RTE\wolfSSL\config-Crypt.h - - + + - RTE\wolfSSL\config.h - - + RTE\wolfSSL\config.h + + + + + + RTE\wolfSSL\settings.h + + diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index 31dd53c78d..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 6 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 50 -#endif - -// Main Thread stack size [bytes] <64-10000:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 2000 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 0 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 0 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-4096:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 2648e44d43..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 0 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index c31ce19915..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00001000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00009000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h deleted file mode 100644 index 4d1a637200..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h +++ /dev/null @@ -1,19 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'CryptTest' - * Target: 'CryptTest' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..33d41cfdbe --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/wolfSSL/settings.h @@ -0,0 +1,667 @@ +/* settings.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using PIC32MZ Crypto Engine */ +/* #define CYASSL_MICROCHIP_PIC32MZ */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + +/* Uncomment next line if using LwIP native TCP socket settings */ +/* #define HAVE_LWIP_NATIVE */ + +/* Uncomment next line if building for EROAD */ +/* #define CYASSL_EROAD */ + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef CYASSL_USER_SETTINGS + #include +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */ + #define CYASSL_LWIP + #define NO_WRITEV + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_FILESYSTEM +#endif + +#ifdef MICROCHIP_PIC32 + /* #define CYASSL_MICROCHIP_PIC32MZ */ + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef CYASSL_MICROCHIP_PIC32MZ + #define CYASSL_PIC32MZ_CE + #define CYASSL_PIC32MZ_CRYPT + #define HAVE_AES_ENGINE + #define CYASSL_PIC32MZ_RNG + /* #define CYASSL_PIC32MZ_HASH */ + #define CYASSL_AES_COUNTER + #define HAVE_AESGCM + #define NO_BIG_INT + +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "system/system_services.h" + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define CYASSL_USER_IO + #define NO_FILESYSTEM + #define NO_CERT + #define USE_CERT_BUFFERS_1024 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define HAVE_ECC + #define NO_SESSION_CACHE + #define CYASSL_CMSIS_RTOS +#endif + + +#ifdef CYASSL_EROAD + #define FREESCALE_MQX + #define FREESCALE_MMCAU + #define SINGLE_THREADED + #define NO_STDIO_FILESYSTEM + #define CYASSL_LEANPSK + #define HAVE_NULL_CIPHER + #define NO_OLD_TLS + #define NO_ASN + #define NO_BIG_INT + #define NO_RSA + #define NO_DSA + #define NO_DH + #define NO_CERTS + #define NO_PWDBASED + #define NO_DES3 + #define NO_MD4 + #define NO_RC4 + #define NO_MD5 + #define NO_SESSION_CACHE + #define NO_MAIN_DRIVER +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) && !defined(CYASSL_EROAD) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.c b/IDE/MDK5-ARM/Projects/CryptTest/cert_data.c similarity index 100% rename from IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.c rename to IDE/MDK5-ARM/Projects/CryptTest/cert_data.c diff --git a/IDE/MDK5-ARM/Projects/CryptTest/main.c b/IDE/MDK5-ARM/Projects/CryptTest/main.c index 8684553c97..d1940f89b3 100644 --- a/IDE/MDK5-ARM/Projects/CryptTest/main.c +++ b/IDE/MDK5-ARM/Projects/CryptTest/main.c @@ -27,13 +27,15 @@ #include #include "cmsis_os.h" -#include "rl_fs.h" - + #include /*----------------------------------------------------------------------------- * Initialize a Flash Memory Card *----------------------------------------------------------------------------*/ +#if !defined(NO_FILESYSTEM) +#include "rl_fs.h" + static void init_filesystem (void) { int32_t retv; @@ -51,8 +53,9 @@ static void init_filesystem (void) { printf ("Drive M0 initialization failed!\n"); } } +#endif + extern void ctaocrypt_test(void * arg) ; -extern void init_time(void) ; /*----------------------------------------------------------------------------- * mian entry @@ -62,8 +65,10 @@ int main() { void * arg = NULL ; - init_time() ; + #if !defined(NO_FILESYSTEM) init_filesystem (); + #endif + printf("=== Start: Crypt test ===\n") ; ctaocrypt_test(arg) ; printf("=== End: Crypt test ===\n") ; diff --git a/IDE/MDK5-ARM/Projects/CryptTest/test.c b/IDE/MDK5-ARM/Projects/CryptTest/test.c index 44d043b30e..e19675bd9b 100644 --- a/IDE/MDK5-ARM/Projects/CryptTest/test.c +++ b/IDE/MDK5-ARM/Projects/CryptTest/test.c @@ -25,6 +25,10 @@ #include +#ifdef XMALLOC_USER + #include /* we're using malloc / free direct here */ +#endif + #ifndef NO_CRYPT_TEST #ifdef CYASSL_TEST_CERT @@ -54,13 +58,16 @@ #include #ifdef HAVE_ECC #include -#endif +#endif #ifdef HAVE_BLAKE2 #include -#endif +#endif #ifdef HAVE_LIBZ #include #endif +#ifdef HAVE_PKCS7 + #include +#endif #ifdef _MSC_VER /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */ @@ -78,8 +85,8 @@ #if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) /* include test cert and key buffers for use with NO_FILESYSTEM */ #if defined(CYASSL_MDK_ARM) - #include "cert_data.h" - /* use certs_test.c for initial data, so other + #include "cert_data.h" + /* use certs_test.c for initial data, so other commands can share the data. */ #else #include @@ -123,7 +130,7 @@ typedef struct testVector { const char* input; - const char* output; + const char* output; size_t inLen; size_t outLen; } testVector; @@ -164,6 +171,9 @@ int pkcs12_test(void); int pbkdf2_test(void); #ifdef HAVE_ECC int ecc_test(void); + #ifdef HAVE_ECC_ENCRYPT + int ecc_encrypt_test(void); + #endif #endif #ifdef HAVE_BLAKE2 int blake2b_test(void); @@ -171,6 +181,10 @@ int pbkdf2_test(void); #ifdef HAVE_LIBZ int compress_test(void); #endif +#ifdef HAVE_PKCS7 + int pkcs7enveloped_test(void); + int pkcs7signed_test(void); +#endif @@ -211,63 +225,63 @@ void ctaocrypt_test(void* args) #ifndef NO_MD5 - if ( (ret = md5_test()) != 0) + if ( (ret = md5_test()) != 0) err_sys("MD5 test failed!\n", ret); else printf( "MD5 test passed!\n"); #endif #ifdef CYASSL_MD2 - if ( (ret = md2_test()) != 0) + if ( (ret = md2_test()) != 0) err_sys("MD2 test failed!\n", ret); else printf( "MD2 test passed!\n"); #endif #ifndef NO_MD4 - if ( (ret = md4_test()) != 0) + if ( (ret = md4_test()) != 0) err_sys("MD4 test failed!\n", ret); else printf( "MD4 test passed!\n"); #endif #ifndef NO_SHA - if ( (ret = sha_test()) != 0) + if ( (ret = sha_test()) != 0) err_sys("SHA test failed!\n", ret); else printf( "SHA test passed!\n"); #endif #ifndef NO_SHA256 - if ( (ret = sha256_test()) != 0) + if ( (ret = sha256_test()) != 0) err_sys("SHA-256 test failed!\n", ret); else printf( "SHA-256 test passed!\n"); #endif #ifdef CYASSL_SHA384 - if ( (ret = sha384_test()) != 0) + if ( (ret = sha384_test()) != 0) err_sys("SHA-384 test failed!\n", ret); else printf( "SHA-384 test passed!\n"); #endif #ifdef CYASSL_SHA512 - if ( (ret = sha512_test()) != 0) + if ( (ret = sha512_test()) != 0) err_sys("SHA-512 test failed!\n", ret); else printf( "SHA-512 test passed!\n"); #endif #ifdef CYASSL_RIPEMD - if ( (ret = ripemd_test()) != 0) + if ( (ret = ripemd_test()) != 0) err_sys("RIPEMD test failed!\n", ret); else printf( "RIPEMD test passed!\n"); #endif -#ifdef HAVE_BLAKE2 - if ( (ret = blake2b_test()) != 0) +#ifdef HAVE_BLAKE2 + if ( (ret = blake2b_test()) != 0) err_sys("BLAKE2b test failed!\n", ret); else printf( "BLAKE2b test passed!\n"); @@ -275,49 +289,49 @@ void ctaocrypt_test(void* args) #ifndef NO_HMAC #ifndef NO_MD5 - if ( (ret = hmac_md5_test()) != 0) + if ( (ret = hmac_md5_test()) != 0) err_sys("HMAC-MD5 test failed!\n", ret); else printf( "HMAC-MD5 test passed!\n"); #endif #ifndef NO_SHA - if ( (ret = hmac_sha_test()) != 0) + if ( (ret = hmac_sha_test()) != 0) err_sys("HMAC-SHA test failed!\n", ret); else printf( "HMAC-SHA test passed!\n"); #endif #ifndef NO_SHA256 - if ( (ret = hmac_sha256_test()) != 0) + if ( (ret = hmac_sha256_test()) != 0) err_sys("HMAC-SHA256 test failed!\n", ret); else printf( "HMAC-SHA256 test passed!\n"); #endif #ifdef CYASSL_SHA384 - if ( (ret = hmac_sha384_test()) != 0) + if ( (ret = hmac_sha384_test()) != 0) err_sys("HMAC-SHA384 test failed!\n", ret); else printf( "HMAC-SHA384 test passed!\n"); #endif #ifdef CYASSL_SHA512 - if ( (ret = hmac_sha512_test()) != 0) + if ( (ret = hmac_sha512_test()) != 0) err_sys("HMAC-SHA512 test failed!\n", ret); else printf( "HMAC-SHA512 test passed!\n"); #endif - #ifdef HAVE_BLAKE2 - if ( (ret = hmac_blake2b_test()) != 0) + #ifdef HAVE_BLAKE2 + if ( (ret = hmac_blake2b_test()) != 0) err_sys("HMAC-BLAKE2 test failed!\n", ret); else printf( "HMAC-BLAKE2 test passed!\n"); #endif #ifdef HAVE_HKDF - if ( (ret = hkdf_test()) != 0) + if ( (ret = hkdf_test()) != 0) err_sys("HMAC-KDF test failed!\n", ret); else printf( "HMAC-KDF test passed!\n"); @@ -401,54 +415,72 @@ void ctaocrypt_test(void* args) printf( "RANDOM test passed!\n"); #ifndef NO_RSA - if ( (ret = rsa_test()) != 0) + if ( (ret = rsa_test()) != 0) err_sys("RSA test failed!\n", ret); else printf( "RSA test passed!\n"); #endif #ifndef NO_DH - if ( (ret = dh_test()) != 0) + if ( (ret = dh_test()) != 0) err_sys("DH test failed!\n", ret); else printf( "DH test passed!\n"); #endif #ifndef NO_DSA - if ( (ret = dsa_test()) != 0) + if ( (ret = dsa_test()) != 0) err_sys("DSA test failed!\n", ret); else printf( "DSA test passed!\n"); #endif - + #ifndef NO_PWDBASED - if ( (ret = pwdbased_test()) != 0) + if ( (ret = pwdbased_test()) != 0) err_sys("PWDBASED test failed!\n", ret); else printf( "PWDBASED test passed!\n"); #endif - + #ifdef OPENSSL_EXTRA - if ( (ret = openssl_test()) != 0) + if ( (ret = openssl_test()) != 0) err_sys("OPENSSL test failed!\n", ret); else printf( "OPENSSL test passed!\n"); #endif #ifdef HAVE_ECC - if ( (ret = ecc_test()) != 0) + if ( (ret = ecc_test()) != 0) err_sys("ECC test failed!\n", ret); else printf( "ECC test passed!\n"); + #ifdef HAVE_ECC_ENCRYPT + if ( (ret = ecc_encrypt_test()) != 0) + err_sys("ECC Enc test failed!\n", ret); + else + printf( "ECC Enc test passed!\n"); + #endif #endif #ifdef HAVE_LIBZ - if ( (ret = compress_test()) != 0) + if ( (ret = compress_test()) != 0) err_sys("COMPRESS test failed!\n", ret); else printf( "COMPRESS test passed!\n"); #endif +#ifdef HAVE_PKCS7 + if ( (ret = pkcs7enveloped_test()) != 0) + err_sys("PKCS7enveloped test failed!\n", ret); + else + printf( "PKCS7enveloped test passed!\n"); + + if ( (ret = pkcs7signed_test()) != 0) + err_sys("PKCS7signed test failed!\n", ret); + else + printf( "PKCS7signed test passed!\n"); +#endif + ((func_args*)args)->return_code = ret; } @@ -485,7 +517,7 @@ static int OpenNitroxDevice(int dma_mode,int dev_id) func_args args; - + #ifdef HAVE_CAVIUM int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); if (ret != 0) @@ -500,7 +532,7 @@ static int OpenNitroxDevice(int dma_mode,int dev_id) #ifdef HAVE_CAVIUM CspShutdown(CAVIUM_DEV_ID); #endif - + return args.return_code; } @@ -581,7 +613,7 @@ int md2_test() return 0; } -#endif +#endif #ifndef NO_MD5 int md5_test(void) @@ -609,21 +641,21 @@ int md5_test(void) c.output = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00\x7d\xfb\x49\x6c\xca\x67\xe1" "\x3b"; c.inLen = strlen(c.input); - c.outLen = MD5_DIGEST_SIZE; + c.outLen = MD5_DIGEST_SIZE; d.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" "6789"; d.output = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5\xa5\x61\x1c\x2c\x9f\x41\x9d" "\x9f"; d.inLen = strlen(d.input); - d.outLen = MD5_DIGEST_SIZE; + d.outLen = MD5_DIGEST_SIZE; e.input = "1234567890123456789012345678901234567890123456789012345678" "9012345678901234567890"; e.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6" "\x7a"; e.inLen = strlen(e.input); - e.outLen = MD5_DIGEST_SIZE; + e.outLen = MD5_DIGEST_SIZE; test_md5[0] = a; test_md5[1] = b; @@ -658,45 +690,45 @@ int md4_test(void) int times = sizeof(test_md4) / sizeof(testVector), i; a.input = ""; - a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" + a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" "\xc0"; a.inLen = strlen(a.input); a.outLen = MD4_DIGEST_SIZE; b.input = "a"; - b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" + b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" "\x24"; b.inLen = strlen(b.input); - b.outLen = MD4_DIGEST_SIZE; + b.outLen = MD4_DIGEST_SIZE; c.input = "abc"; - c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" + c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" "\x9d"; c.inLen = strlen(c.input); c.outLen = MD4_DIGEST_SIZE; d.input = "message digest"; - d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" + d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" "\x4b"; d.inLen = strlen(d.input); d.outLen = MD4_DIGEST_SIZE; e.input = "abcdefghijklmnopqrstuvwxyz"; - e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" + e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" "\xa9"; e.inLen = strlen(e.input); e.outLen = MD4_DIGEST_SIZE; f.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" "6789"; - f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" + f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" "\xe4"; f.inLen = strlen(f.input); f.outLen = MD4_DIGEST_SIZE; g.input = "1234567890123456789012345678901234567890123456789012345678" "9012345678901234567890"; - g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" + g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" "\x36"; g.inLen = strlen(g.input); g.outLen = MD4_DIGEST_SIZE; @@ -733,6 +765,7 @@ int sha_test(void) testVector a, b, c, d; testVector test_sha[4]; + int ret; int times = sizeof(test_sha) / sizeof(struct testVector), i; a.input = "abc"; @@ -752,7 +785,7 @@ int sha_test(void) c.output = "\x00\x98\xBA\x82\x4B\x5C\x16\x42\x7B\xD7\xA1\x12\x2A\x5A\x44" "\x2A\x25\xEC\x64\x4D"; c.inLen = strlen(c.input); - c.outLen = SHA_DIGEST_SIZE; + c.outLen = SHA_DIGEST_SIZE; d.input = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" @@ -767,7 +800,9 @@ int sha_test(void) test_sha[2] = c; test_sha[3] = d; - InitSha(&sha); + ret = InitSha(&sha); + if (ret != 0) + return -4001; for (i = 0; i < times; ++i) { ShaUpdate(&sha, (byte*)test_sha[i].input, (word32)test_sha[i].inLen); @@ -804,7 +839,7 @@ int ripemd_test(void) b.inLen = strlen(b.input); b.outLen = RIPEMD_DIGEST_SIZE; - c.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; + c.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; c.output = "\x12\xa0\x53\x38\x4a\x9c\x0c\x88\xe4\x05\xa0\x6c\x27\xdc" "\xf4\x9a\xda\x62\xeb\x2b"; c.inLen = strlen(c.input); @@ -813,7 +848,7 @@ int ripemd_test(void) d.input = "12345678901234567890123456789012345678901234567890123456" "789012345678901234567890"; d.output = "\x9b\x75\x2e\x45\x57\x3d\x4b\x39\xf4\xdb\xd3\x32\x3c\xab" - "\x82\xbf\x63\x32\x6b\xfb"; + "\x82\xbf\x63\x32\x6b\xfb"; d.inLen = strlen(d.input); d.outLen = RIPEMD_DIGEST_SIZE; @@ -884,15 +919,23 @@ int blake2b_test(void) Blake2b b2b; byte digest[64]; byte input[64]; - int i; + int i, ret; for (i = 0; i < (int)sizeof(input); i++) input[i] = (byte)i; for (i = 0; i < BLAKE2_TESTS; i++) { - InitBlake2b(&b2b, 64); - Blake2bUpdate(&b2b, input, i); - Blake2bFinal(&b2b, digest, 64); + ret = InitBlake2b(&b2b, 64); + if (ret != 0) + return -4002; + + ret = Blake2bUpdate(&b2b, input, i); + if (ret != 0) + return -4003; + + ret = Blake2bFinal(&b2b, digest, 64); + if (ret != 0) + return -4004; if (memcmp(digest, blake2b_vec[i], 64) != 0) { return -300 - i; @@ -912,6 +955,7 @@ int sha256_test(void) testVector a, b; testVector test_sha[2]; + int ret; int times = sizeof(test_sha) / sizeof(struct testVector), i; a.input = "abc"; @@ -931,11 +975,17 @@ int sha256_test(void) test_sha[0] = a; test_sha[1] = b; - InitSha256(&sha); + ret = InitSha256(&sha); + if (ret != 0) + return -4005; for (i = 0; i < times; ++i) { - Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); - Sha256Final(&sha, hash); + ret = Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + if (ret != 0) + return -4006; + ret = Sha256Final(&sha, hash); + if (ret != 0) + return -4007; if (memcmp(hash, test_sha[i].output, SHA256_DIGEST_SIZE) != 0) return -10 - i; @@ -951,6 +1001,7 @@ int sha512_test(void) { Sha512 sha; byte hash[SHA512_DIGEST_SIZE]; + int ret; testVector a, b; testVector test_sha[2]; @@ -971,18 +1022,25 @@ int sha512_test(void) "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88" "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4" "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b" - "\x87\x4b\xe9\x09"; + "\x87\x4b\xe9\x09"; b.inLen = strlen(b.input); b.outLen = SHA512_DIGEST_SIZE; test_sha[0] = a; test_sha[1] = b; - InitSha512(&sha); + ret = InitSha512(&sha); + if (ret != 0) + return -4009; for (i = 0; i < times; ++i) { - Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); - Sha512Final(&sha, hash); + ret = Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + if (ret != 0) + return -4010; + + ret = Sha512Final(&sha, hash); + if (ret != 0) + return -4011; if (memcmp(hash, test_sha[i].output, SHA512_DIGEST_SIZE) != 0) return -10 - i; @@ -998,6 +1056,7 @@ int sha384_test(void) { Sha384 sha; byte hash[SHA384_DIGEST_SIZE]; + int ret; testVector a, b; testVector test_sha[2]; @@ -1018,16 +1077,23 @@ int sha384_test(void) "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91" "\x74\x60\x39"; b.inLen = strlen(b.input); - b.outLen = SHA384_DIGEST_SIZE; + b.outLen = SHA384_DIGEST_SIZE; test_sha[0] = a; test_sha[1] = b; - InitSha384(&sha); + ret = InitSha384(&sha); + if (ret != 0) + return -4012; for (i = 0; i < times; ++i) { - Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); - Sha384Final(&sha, hash); + ret = Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + if (ret != 0) + return -4013; + + ret = Sha384Final(&sha, hash); + if (ret != 0) + return -4014; if (memcmp(hash, test_sha[i].output, SHA384_DIGEST_SIZE) != 0) return -10 - i; @@ -1054,6 +1120,7 @@ int hmac_md5_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1086,12 +1153,18 @@ int hmac_md5_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20009; + return -20009; #endif - HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i])); + if (ret != 0) + return -4015; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4016; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4017; if (memcmp(hash, test_hmac[i].output, MD5_DIGEST_SIZE) != 0) return -20 - i; @@ -1122,6 +1195,7 @@ int hmac_sha_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1154,12 +1228,18 @@ int hmac_sha_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20010; + return -20010; #endif - HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i])); + if (ret != 0) + return -4018; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4019; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4020; if (memcmp(hash, test_hmac[i].output, SHA_DIGEST_SIZE) != 0) return -20 - i; @@ -1191,6 +1271,7 @@ int hmac_sha256_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1226,12 +1307,18 @@ int hmac_sha256_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20011; + return -20011; #endif - HmacSetKey(&hmac, SHA256, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA256, (byte*)keys[i],(word32)strlen(keys[i])); + if (ret != 0) + return -4021; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4022; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4023; if (memcmp(hash, test_hmac[i].output, SHA256_DIGEST_SIZE) != 0) return -20 - i; @@ -1263,6 +1350,7 @@ int hmac_blake2b_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1298,12 +1386,19 @@ int hmac_blake2b_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20011; + return -20011; #endif - HmacSetKey(&hmac, BLAKE2B_ID, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, BLAKE2B_ID, (byte*)keys[i], + (word32)strlen(keys[i])); + if (ret != 0) + return -4024; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4025; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4026; if (memcmp(hash, test_hmac[i].output, BLAKE2B_256) != 0) return -20 - i; @@ -1335,6 +1430,7 @@ int hmac_sha384_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1369,10 +1465,16 @@ int hmac_sha384_test(void) test_hmac[2] = c; for (i = 0; i < times; ++i) { - HmacSetKey(&hmac, SHA384, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA384, (byte*)keys[i],(word32)strlen(keys[i])); + if (ret != 0) + return -4027; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4028; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4029; if (memcmp(hash, test_hmac[i].output, SHA384_DIGEST_SIZE) != 0) return -20 - i; @@ -1401,6 +1503,7 @@ int hmac_sha512_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1438,10 +1541,16 @@ int hmac_sha512_test(void) test_hmac[2] = c; for (i = 0; i < times; ++i) { - HmacSetKey(&hmac, SHA512, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA512, (byte*)keys[i],(word32)strlen(keys[i])); + if (ret != 0) + return -4030; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4031; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4032; if (memcmp(hash, test_hmac[i].output, SHA512_DIGEST_SIZE) != 0) return -20 - i; @@ -1458,8 +1567,8 @@ int arc4_test(void) byte cipher[16]; byte plain[16]; - const char* keys[] = - { + const char* keys[] = + { "\x01\x23\x45\x67\x89\xab\xcd\xef", "\x01\x23\x45\x67\x89\xab\xcd\xef", "\x00\x00\x00\x00\x00\x00\x00\x00", @@ -1505,9 +1614,9 @@ int arc4_test(void) #ifdef HAVE_CAVIUM if (Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0) - return -20001; + return -20001; if (Arc4InitCavium(&dec, CAVIUM_DEV_ID) != 0) - return -20002; + return -20002; #endif Arc4SetKey(&enc, (byte*)keys[i], keylen); @@ -1540,8 +1649,8 @@ int hc128_test(void) byte cipher[16]; byte plain[16]; - const char* keys[] = - { + const char* keys[] = + { "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x53\xA6\xF9\x4C\x9F\xF2\x45\x98\xEB\x3E\x91\xE4\x37\x8A\xDD", @@ -1592,8 +1701,8 @@ int hc128_test(void) HC128 dec; /* align keys/ivs in plain/cipher buffers */ - memcpy(plain, keys[i], 16); - memcpy(cipher, ivs[i], 16); + memcpy(plain, keys[i], 16); + memcpy(cipher, ivs[i], 16); Hc128_SetKey(&enc, plain, cipher); Hc128_SetKey(&dec, plain, cipher); @@ -1621,8 +1730,8 @@ int rabbit_test(void) byte cipher[16]; byte plain[16]; - const char* keys[] = - { + const char* keys[] = + { "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\xAC\xC3\x51\xDC\xF1\x62\xFC\x3B\xFE\x36\x3D\x2E\x29\x13\x28\x91" @@ -1706,34 +1815,40 @@ int des_test(void) Des enc; Des dec; - const byte key[] = + const byte key[] = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef }; - const byte iv[] = + const byte iv[] = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef }; - const byte verify[] = + const byte verify[] = { 0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8, 0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73, 0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b }; + int ret; + + ret = Des_SetKey(&enc, key, iv, DES_ENCRYPTION); + if (ret != 0) + return -31; - Des_SetKey(&enc, key, iv, DES_ENCRYPTION); Des_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); - Des_SetKey(&dec, key, iv, DES_DECRYPTION); + ret = Des_SetKey(&dec, key, iv, DES_DECRYPTION); + if (ret != 0) + return -32; Des_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); if (memcmp(plain, vector, sizeof(plain))) - return -31; + return -33; if (memcmp(cipher, verify, sizeof(cipher))) - return -32; + return -34; return 0; } @@ -1755,44 +1870,54 @@ int des3_test(void) Des3 enc; Des3 dec; - const byte key3[] = + const byte key3[] = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 }; - const byte iv3[] = + const byte iv3[] = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81 - + }; - const byte verify3[] = + const byte verify3[] = { 0x43,0xa0,0x29,0x7e,0xd1,0x84,0xf8,0x0e, 0x89,0x64,0x84,0x32,0x12,0xd5,0x08,0x98, 0x18,0x94,0x15,0x74,0x87,0x12,0x7d,0xb0 }; + int ret; + #ifdef HAVE_CAVIUM if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) - return -20005; + return -20005; if (Des3_InitCavium(&dec, CAVIUM_DEV_ID) != 0) - return -20006; + return -20006; #endif - Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION); - Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION); - Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); - Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); + ret = Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION); + if (ret != 0) + return -31; + ret = Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION); + if (ret != 0) + return -32; + ret = Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); + if (ret != 0) + return -33; + ret = Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); + if (ret != 0) + return -34; if (memcmp(plain, vector, sizeof(plain))) - return -33; + return -35; if (memcmp(cipher, verify3, sizeof(cipher))) - return -34; + return -36; #ifdef HAVE_CAVIUM Des3_FreeCavium(&enc); @@ -1815,7 +1940,7 @@ int aes_test(void) 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 }; - const byte verify[] = + const byte verify[] = { 0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53, 0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb @@ -1826,18 +1951,27 @@ int aes_test(void) byte cipher[AES_BLOCK_SIZE * 4]; byte plain [AES_BLOCK_SIZE * 4]; + int ret; #ifdef HAVE_CAVIUM if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) - return -20003; + return -20003; if (AesInitCavium(&dec, CAVIUM_DEV_ID) != 0) - return -20004; + return -20004; #endif - AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); - AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION); + ret = AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); + if (ret != 0) + return -1001; + ret = AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION); + if (ret != 0) + return -1002; - AesCbcEncrypt(&enc, cipher, msg, AES_BLOCK_SIZE); - AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE); + ret = AesCbcEncrypt(&enc, cipher, msg, AES_BLOCK_SIZE); + if (ret != 0) + return -1005; + ret = AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE); + if (ret != 0) + return -1006; if (memcmp(plain, msg, AES_BLOCK_SIZE)) return -60; @@ -1851,7 +1985,7 @@ int aes_test(void) #endif #ifdef CYASSL_AES_COUNTER { - const byte ctrKey[] = + const byte ctrKey[] = { 0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6, 0xab,0xf7,0x15,0x88,0x09,0xcf,0x4f,0x3c @@ -1888,6 +2022,12 @@ int aes_test(void) 0x79,0x21,0x70,0xa0,0xf3,0x00,0x9c,0xee }; + const byte oddCipher[] = + { + 0xb9,0xd7,0xcb,0x08,0xb0,0xe1,0x7b,0xa0, + 0xc2 + }; + AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); /* Ctr only uses encrypt, even on key setup */ AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); @@ -1900,6 +2040,30 @@ int aes_test(void) if (memcmp(cipher, ctrCipher, AES_BLOCK_SIZE*4)) return -67; + + /* let's try with just 9 bytes, non block size test */ + AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); + /* Ctr only uses encrypt, even on key setup */ + AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); + + AesCtrEncrypt(&enc, cipher, ctrPlain, 9); + AesCtrEncrypt(&dec, plain, cipher, 9); + + if (memcmp(plain, ctrPlain, 9)) + return -68; + + if (memcmp(cipher, ctrCipher, 9)) + return -69; + + /* and an additional 9 bytes to reuse tmp left buffer */ + AesCtrEncrypt(&enc, cipher, ctrPlain, 9); + AesCtrEncrypt(&dec, plain, cipher, 9); + + if (memcmp(plain, ctrPlain, 9)) + return -70; + + if (memcmp(cipher, oddCipher, 9)) + return -71; } #endif /* CYASSL_AES_COUNTER */ @@ -1914,7 +2078,7 @@ int aes_test(void) const byte niCipher[] = { 0xf3,0xee,0xd1,0xbd,0xb5,0xd2,0xa0,0x3c, - 0x06,0x4b,0x5a,0x7e,0x3d,0xb1,0x81,0xf8 + 0x06,0x4b,0x5a,0x7e,0x3d,0xb1,0x81,0xf8 }; const byte niKey[] = @@ -1922,17 +2086,21 @@ int aes_test(void) 0x60,0x3d,0xeb,0x10,0x15,0xca,0x71,0xbe, 0x2b,0x73,0xae,0xf0,0x85,0x7d,0x77,0x81, 0x1f,0x35,0x2c,0x07,0x3b,0x61,0x08,0xd7, - 0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4 + 0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4 }; XMEMSET(cipher, 0, AES_BLOCK_SIZE); - AesSetKey(&enc, niKey, sizeof(niKey), cipher, AES_ENCRYPTION); + ret = AesSetKey(&enc, niKey, sizeof(niKey), cipher, AES_ENCRYPTION); + if (ret != 0) + return -1003; AesEncryptDirect(&enc, cipher, niPlain); if (XMEMCMP(cipher, niCipher, AES_BLOCK_SIZE) != 0) return -20006; XMEMSET(plain, 0, AES_BLOCK_SIZE); - AesSetKey(&dec, niKey, sizeof(niKey), plain, AES_DECRYPTION); + ret = AesSetKey(&dec, niKey, sizeof(niKey), plain, AES_DECRYPTION); + if (ret != 0) + return -1004; AesDecryptDirect(&dec, plain, niCipher); if (XMEMCMP(plain, niPlain, AES_BLOCK_SIZE) != 0) return -20007; @@ -1965,7 +2133,7 @@ int aesgcm_test(void) 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88 }; - + const byte p[] = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, @@ -1977,14 +2145,14 @@ int aesgcm_test(void) 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39 }; - + const byte a[] = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, 0xab, 0xad, 0xda, 0xd2 }; - + const byte c[] = { 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, @@ -2163,7 +2331,7 @@ int aesccm_test(void) const byte t[] = { - 0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 + 0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 }; byte t2[sizeof(t)]; @@ -2232,7 +2400,7 @@ typedef struct { int camellia_test(void) { /* Camellia ECB Test Plaintext */ - static const byte pte[] = + static const byte pte[] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 @@ -2284,26 +2452,26 @@ int camellia_test(void) static const byte ptc[] = { 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, - 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A }; /* Camellia CBC Test Initialization Vector */ static const byte ivc[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; /* Test 4: Camellia-CBC 128-bit key */ static const byte k4[] = { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, - 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C + 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }; static const byte c4[] = { 0x16, 0x07, 0xCF, 0x49, 0x4B, 0x36, 0xBB, 0xF0, - 0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB + 0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB }; /* Test 5: Camellia-CBC 192-bit key */ @@ -2311,12 +2479,12 @@ int camellia_test(void) { 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, - 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B + 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B }; static const byte c5[] = { 0x2A, 0x48, 0x30, 0xAB, 0x5A, 0xC4, 0xA1, 0xA2, - 0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93 + 0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93 }; /* Test 6: CBC 256-bit key */ @@ -2325,12 +2493,12 @@ int camellia_test(void) 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, - 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 }; static const byte c6[] = { 0xE6, 0xCF, 0xA3, 0x5F, 0xC0, 0x2B, 0x13, 0x4A, - 0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA + 0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA }; byte out[CAMELLIA_BLOCK_SIZE]; @@ -2352,14 +2520,11 @@ int camellia_test(void) {CAM_CBC_DEC, ptc, ivc, c6, k6, sizeof(k6), -125} }; - if ((sizeof(pte) != CAMELLIA_BLOCK_SIZE) || - (sizeof(ptc) != CAMELLIA_BLOCK_SIZE)) - return -113; - testsSz = sizeof(testVectors)/sizeof(test_vector_t); for (i = 0; i < testsSz; i++) { - CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz, - testVectors[i].iv); + if (CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz, + testVectors[i].iv) != 0) + return testVectors[i].errorCode; switch (testVectors[i].type) { case CAM_ECB_ENC: @@ -2398,7 +2563,7 @@ int camellia_test(void) if (CamelliaSetIV(&cam, NULL) != 0 || XMEMCMP(cam.reg, ive, CAMELLIA_BLOCK_SIZE)) return -1; - + /* First parameter should never be null */ if (CamelliaSetIV(NULL, NULL) == 0) return -1; @@ -2429,7 +2594,8 @@ int random_test(void) ret = InitRng(&rng); if (ret != 0) return -39; - RNG_GenerateBlock(&rng, block, sizeof(block)); + ret = RNG_GenerateBlock(&rng, block, sizeof(block)); + if (ret != 0) return -40; return 0; } @@ -2443,21 +2609,14 @@ byte GetEntropy(ENTROPY_CMD cmd, byte* out) { static RNG rng; - if (cmd == INIT) { - int ret = InitRng(&rng); - if (ret == 0) - return 1; - else - return 0; - } + if (cmd == INIT) + return (InitRng(&rng) == 0) ? 1 : 0; if (out == NULL) return 0; - if (cmd == GET_BYTE_OF_ENTROPY) { - RNG_GenerateBlock(&rng, out, 1); - return 1; - } + if (cmd == GET_BYTE_OF_ENTROPY) + return (RNG_GenerateBlock(&rng, out, 1) == 0) ? 1 : 0; if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) { *out = 1; @@ -2478,17 +2637,27 @@ byte GetEntropy(ENTROPY_CMD cmd, byte* out) #ifdef CYASSL_CERT_GEN static const char* caKeyFile = "a:\\certs\\ca-key.der"; static const char* caCertFile = "a:\\certs\\ca-cert.pem"; + #ifdef HAVE_ECC + static const char* eccCaKeyFile = "a:\\certs\\ecc-key.der"; + static const char* eccCaCertFile = "a:\\certs\\server-ecc.pem"; + #endif #endif #elif defined(CYASSL_MKD_SHELL) static char* clientKey = "certs/client-key.der"; static char* clientCert = "certs/client-cert.der"; - void set_clientKey(char *key) { clientKey = key ; } /* set by shell command */ - void set_clientCert(char *cert) { clientCert = cert ; } /* set by shell command */ + void set_clientKey(char *key) { clientKey = key ; } + void set_clientCert(char *cert) { clientCert = cert ; } #ifdef CYASSL_CERT_GEN static char* caKeyFile = "certs/ca-key.der"; static char* caCertFile = "certs/ca-cert.pem"; - void set_caKeyFile (char * key) { caKeyFile = key ; } /* set by shell command */ - void set_caCertFile(char * cert) { caCertFile = cert ; } /* set by shell command */ + void set_caKeyFile (char * key) { caKeyFile = key ; } + void set_caCertFile(char * cert) { caCertFile = cert ; } + #ifdef HAVE_ECC + static const char* eccCaKeyFile = "certs/ecc-key.der"; + static const char* eccCaCertFile = "certs/server-ecc.pem"; + void set_eccCaKeyFile (char * key) { eccCaKeyFile = key ; } + void set_eccCaCertFile(char * cert) { eccCaCertFile = cert ; } + #endif #endif #else static const char* clientKey = "./certs/client-key.der"; @@ -2496,6 +2665,10 @@ byte GetEntropy(ENTROPY_CMD cmd, byte* out) #ifdef CYASSL_CERT_GEN static const char* caKeyFile = "./certs/ca-key.der"; static const char* caCertFile = "./certs/ca-cert.pem"; + #ifdef HAVE_ECC + static const char* eccCaKeyFile = "./certs/ecc-key.der"; + static const char* eccCaCertFile = "./certs/server-ecc.pem"; + #endif #endif #endif #endif @@ -2543,11 +2716,12 @@ int rsa_test(void) bytes = fread(tmp, 1, FOURK_BUF, file); fclose(file); #endif /* USE_CERT_BUFFERS */ - + #ifdef HAVE_CAVIUM RsaInitCavium(&key, CAVIUM_DEV_ID); -#endif - InitRsaKey(&key, 0); +#endif + ret = InitRsaKey(&key, 0); + if (ret != 0) return -39; ret = RsaPrivateKeyDecode(tmp, &idx, &key, (word32)bytes); if (ret != 0) return -41; @@ -2592,7 +2766,7 @@ int rsa_test(void) #ifdef sizeof #undef sizeof -#endif +#endif #ifdef CYASSL_TEST_CERT InitDecodedCert(&cert, tmp, (word32)bytes, 0); @@ -2617,43 +2791,88 @@ int rsa_test(void) FILE* keyFile; FILE* pemFile; - InitRsaKey(&genKey, 0); + ret = InitRsaKey(&genKey, 0); + if (ret != 0) + return -300; ret = MakeRsaKey(&genKey, 1024, 65537, &rng); if (ret != 0) return -301; der = (byte*)malloc(FOURK_BUF); - if (der == NULL) + if (der == NULL) { + FreeRsaKey(&genKey); return -307; + } pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(der); + FreeRsaKey(&genKey); return -308; + } derSz = RsaKeyToDer(&genKey, der, FOURK_BUF); - if (derSz < 0) + if (derSz < 0) { + free(der); + free(pem); return -302; + } keyFile = fopen("./key.der", "wb"); - if (!keyFile) + if (!keyFile) { + free(der); + free(pem); + FreeRsaKey(&genKey); return -303; - ret = (int)fwrite(der, derSz, 1, keyFile); + } + ret = (int)fwrite(der, 1, derSz, keyFile); fclose(keyFile); + if (ret != derSz) { + free(der); + free(pem); + FreeRsaKey(&genKey); + return -313; + } pemSz = DerToPem(der, derSz, pem, FOURK_BUF, PRIVATEKEY_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(der); + free(pem); + FreeRsaKey(&genKey); return -304; + } pemFile = fopen("./key.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(der); + free(pem); + FreeRsaKey(&genKey); return -305; - ret = (int)fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); fclose(pemFile); + if (ret != pemSz) { + free(der); + free(pem); + FreeRsaKey(&genKey); + return -314; + } - InitRsaKey(&derIn, 0); + ret = InitRsaKey(&derIn, 0); + if (ret != 0) { + free(der); + free(pem); + FreeRsaKey(&genKey); + return -3060; + } idx = 0; ret = RsaPrivateKeyDecode(der, &idx, &derIn, derSz); - if (ret != 0) + if (ret != 0) { + free(der); + free(pem); + FreeRsaKey(&derIn); + FreeRsaKey(&genKey); return -306; + } FreeRsaKey(&derIn); FreeRsaKey(&genKey); @@ -2681,8 +2900,10 @@ int rsa_test(void) if (derCert == NULL) return -309; pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(derCert); return -310; + } InitCert(&myCert); @@ -2696,32 +2917,57 @@ int rsa_test(void) myCert.isCA = 1; myCert.sigType = CTC_SHA256wRSA; - certSz = MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng); - if (certSz < 0) + certSz = MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng); + if (certSz < 0) { + free(derCert); + free(pem); return -401; + } #ifdef CYASSL_TEST_CERT InitDecodedCert(&decode, derCert, certSz, 0); ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); - if (ret != 0) + if (ret != 0) { + free(derCert); + free(pem); return -402; + } FreeDecodedCert(&decode); #endif derFile = fopen("./cert.der", "wb"); - if (!derFile) + if (!derFile) { + free(derCert); + free(pem); return -403; - ret = (int)fwrite(derCert, certSz, 1, derFile); + } + ret = (int)fwrite(derCert, 1, certSz, derFile); fclose(derFile); + if (ret != certSz) { + free(derCert); + free(pem); + return -414; + } pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(derCert); + free(pem); return -404; + } pemFile = fopen("./cert.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(derCert); + free(pem); return -405; - ret = (int)fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); fclose(pemFile); + if (ret != pemSz) { + free(derCert); + free(pem); + return -406; + } free(pem); free(derCert); } @@ -2746,20 +2992,35 @@ int rsa_test(void) if (derCert == NULL) return -311; pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(derCert); return -312; + } file3 = fopen(caKeyFile, "rb"); - if (!file3) + if (!file3) { + free(derCert); + free(pem); return -412; + } bytes3 = fread(tmp, 1, FOURK_BUF, file3); fclose(file3); - - InitRsaKey(&caKey, 0); + + ret = InitRsaKey(&caKey, 0); + if (ret != 0) { + free(derCert); + free(pem); + return -411; + } ret = RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3); - if (ret != 0) return -413; + if (ret != 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); + return -413; + } InitCert(&myCert); @@ -2772,46 +3033,224 @@ int rsa_test(void) strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); ret = SetIssuer(&myCert, caCertFile); - if (ret < 0) + if (ret < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -405; + } - certSz = MakeCert(&myCert, derCert, FOURK_BUF, &key, &rng); - if (certSz < 0) + certSz = MakeCert(&myCert, derCert, FOURK_BUF, &key, NULL, &rng); + if (certSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -407; + } certSz = SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF, - &caKey, &rng); - if (certSz < 0) + &caKey, NULL, &rng); + if (certSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -408; + } #ifdef CYASSL_TEST_CERT InitDecodedCert(&decode, derCert, certSz, 0); ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); - if (ret != 0) + if (ret != 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -409; + } FreeDecodedCert(&decode); #endif derFile = fopen("./othercert.der", "wb"); - if (!derFile) + if (!derFile) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -410; - ret = (int)fwrite(derCert, certSz, 1, derFile); + } + ret = (int)fwrite(derCert, 1, certSz, derFile); fclose(derFile); + if (ret != certSz) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); + return -416; + } pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -411; + } pemFile = fopen("./othercert.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -412; - ret = (int)fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); + if (ret != pemSz) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); + return -415; + } fclose(pemFile); free(pem); free(derCert); FreeRsaKey(&caKey); } +#ifdef HAVE_ECC + /* ECC CA style */ + { + ecc_key caKey; + Cert myCert; + byte* derCert; + byte* pem; + FILE* derFile; + FILE* pemFile; + int certSz; + int pemSz; + size_t bytes3; + word32 idx3 = 0; + FILE* file3; +#ifdef CYASSL_TEST_CERT + DecodedCert decode; +#endif + + derCert = (byte*)malloc(FOURK_BUF); + if (derCert == NULL) + return -5311; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) { + free(derCert); + return -5312; + } + + file3 = fopen(eccCaKeyFile, "rb"); + + if (!file3) { + free(derCert); + free(pem); + return -5412; + } + + bytes3 = fread(tmp, 1, FOURK_BUF, file3); + fclose(file3); + + ecc_init(&caKey); + ret = EccPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3); + if (ret != 0) { + free(derCert); + free(pem); + return -5413; + } + + InitCert(&myCert); + myCert.sigType = CTC_SHA256wECDSA; + + strncpy(myCert.subject.country, "US", CTC_NAME_SIZE); + strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE); + strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(myCert.subject.org, "wolfSSL", CTC_NAME_SIZE); + strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(myCert.subject.commonName, "www.wolfssl.com", CTC_NAME_SIZE); + strncpy(myCert.subject.email, "info@wolfssl.com", CTC_NAME_SIZE); + + ret = SetIssuer(&myCert, eccCaCertFile); + if (ret < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5405; + } + + certSz = MakeCert(&myCert, derCert, FOURK_BUF, NULL, &caKey, &rng); + if (certSz < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5407; + } + + certSz = SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF, + NULL, &caKey, &rng); + if (certSz < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5408; + } + +#ifdef CYASSL_TEST_CERT + InitDecodedCert(&decode, derCert, certSz, 0); + ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); + if (ret != 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5409; + } + FreeDecodedCert(&decode); +#endif + + derFile = fopen("./certecc.der", "wb"); + if (!derFile) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5410; + } + ret = (int)fwrite(derCert, 1, certSz, derFile); + fclose(derFile); + if (ret != certSz) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5414; + } + + pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); + if (pemSz < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5411; + } + + pemFile = fopen("./certecc.pem", "wb"); + if (!pemFile) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5412; + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); + if (ret != pemSz) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5415; + } + fclose(pemFile); + free(pem); + free(derCert); + ecc_free(&caKey); + } +#endif /* HAVE_ECC */ #ifdef HAVE_NTRU { RsaKey caKey; @@ -2824,8 +3263,7 @@ int rsa_test(void) FILE* ntruPrivFile; int certSz; int pemSz; - size_t bytes; - word32 idx = 0; + word32 idx3; #ifdef CYASSL_TEST_CERT DecodedCert decode; #endif @@ -2833,8 +3271,10 @@ int rsa_test(void) if (derCert == NULL) return -311; pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(derCert); return -312; + } byte public_key[557]; /* sized for EES401EP2 */ word16 public_key_len; /* no. of octets in public key */ @@ -2846,32 +3286,53 @@ int rsa_test(void) }; word32 rc = crypto_drbg_instantiate(112, pers_str, sizeof(pers_str), GetEntropy, &drbg); - if (rc != DRBG_OK) + if (rc != DRBG_OK) { + free(derCert); + free(pem); return -450; + } rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len, NULL, &private_key_len, NULL); - if (rc != NTRU_OK) + if (rc != NTRU_OK) { + free(derCert); + free(pem); return -451; + } rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len, public_key, &private_key_len, private_key); crypto_drbg_uninstantiate(drbg); - if (rc != NTRU_OK) + if (rc != NTRU_OK) { + free(derCert); + free(pem); return -452; + } caFile = fopen(caKeyFile, "rb"); - if (!caFile) + if (!caFile) { + free(derCert); + free(pem); return -453; + } bytes = fread(tmp, 1, FOURK_BUF, caFile); fclose(caFile); - - InitRsaKey(&caKey, 0); - ret = RsaPrivateKeyDecode(tmp, &idx, &caKey, (word32)bytes); - if (ret != 0) return -454; + + ret = InitRsaKey(&caKey, 0); + if (ret != 0) { + free(derCert); + free(pem); + return -459; + } + ret = RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes); + if (ret != 0) { + free(derCert); + free(pem); + return -454; + } InitCert(&myCert); @@ -2884,59 +3345,187 @@ int rsa_test(void) strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); ret = SetIssuer(&myCert, caCertFile); - if (ret < 0) + if (ret < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -455; + } certSz = MakeNtruCert(&myCert, derCert, FOURK_BUF, public_key, - public_key_len, &rng); - if (certSz < 0) + public_key_len, &rng); + if (certSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -456; + } certSz = SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF, - &caKey, &rng); - if (certSz < 0) + &caKey, NULL, &rng); + FreeRsaKey(&caKey); + if (certSz < 0) { + free(derCert); + free(pem); return -457; + } #ifdef CYASSL_TEST_CERT InitDecodedCert(&decode, derCert, certSz, 0); ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); - if (ret != 0) + if (ret != 0) { + free(derCert); + free(pem); return -458; + } FreeDecodedCert(&decode); #endif derFile = fopen("./ntru-cert.der", "wb"); - if (!derFile) + if (!derFile) { + free(derCert); + free(pem); return -459; - ret = fwrite(derCert, certSz, 1, derFile); + } + ret = (int)fwrite(derCert, 1, certSz, derFile); fclose(derFile); + if (ret != certSz) { + free(derCert); + free(pem); + return -473; + } pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(derCert); + free(pem); return -460; + } pemFile = fopen("./ntru-cert.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(derCert); + free(pem); return -461; - ret = fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); fclose(pemFile); + if (ret != pemSz) { + free(derCert); + free(pem); + return -474; + } ntruPrivFile = fopen("./ntru-key.raw", "wb"); - if (!ntruPrivFile) + if (!ntruPrivFile) { + free(derCert); + free(pem); return -462; - ret = fwrite(private_key, private_key_len, 1, ntruPrivFile); + } + ret = (int)fwrite(private_key, 1, private_key_len, ntruPrivFile); fclose(ntruPrivFile); + if (ret != private_key_len) { + free(pem); + free(derCert); + return -475; + } free(pem); free(derCert); - FreeRsaKey(&caKey); } #endif /* HAVE_NTRU */ +#ifdef CYASSL_CERT_REQ + { + Cert req; + byte* der; + byte* pem; + int derSz; + int pemSz; + FILE* reqFile; + + der = (byte*)malloc(FOURK_BUF); + if (der == NULL) + return -463; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) { + free(der); + return -464; + } + + InitCert(&req); + + req.version = 0; + req.isCA = 1; + strncpy(req.challengePw, "yassl123", CTC_NAME_SIZE); + strncpy(req.subject.country, "US", CTC_NAME_SIZE); + strncpy(req.subject.state, "OR", CTC_NAME_SIZE); + strncpy(req.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(req.subject.org, "yaSSL", CTC_NAME_SIZE); + strncpy(req.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(req.subject.commonName, "www.yassl.com", CTC_NAME_SIZE); + strncpy(req.subject.email, "info@yassl.com", CTC_NAME_SIZE); + req.sigType = CTC_SHA256wRSA; + + derSz = MakeCertReq(&req, der, FOURK_BUF, &key, NULL); + if (derSz < 0) { + free(pem); + free(der); + return -465; + } + + derSz = SignCert(req.bodySz, req.sigType, der, FOURK_BUF, + &key, NULL, &rng); + if (derSz < 0) { + free(pem); + free(der); + return -466; + } + + pemSz = DerToPem(der, derSz, pem, FOURK_BUF, CERTREQ_TYPE); + if (pemSz < 0) { + free(pem); + free(der); + return -467; + } + + reqFile = fopen("./certreq.der", "wb"); + if (!reqFile) { + free(pem); + free(der); + return -468; + } + + ret = (int)fwrite(der, 1, derSz, reqFile); + fclose(reqFile); + if (ret != derSz) { + free(pem); + free(der); + return -471; + } + + reqFile = fopen("./certreq.pem", "wb"); + if (!reqFile) { + free(pem); + free(der); + return -469; + } + ret = (int)fwrite(pem, 1, pemSz, reqFile); + fclose(reqFile); + if (ret != pemSz) { + free(pem); + free(der); + return -470; + } + + free(pem); + free(der); + } +#endif /* CYASSL_CERT_REQ */ #endif /* CYASSL_CERT_GEN */ FreeRsaKey(&key); #ifdef HAVE_CAVIUM RsaFreeCavium(&key); -#endif +#endif free(tmp); return 0; @@ -2970,8 +3559,8 @@ int dh_test(void) DhKey key; DhKey key2; RNG rng; - - + + #ifdef USE_CERT_BUFFERS_1024 XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024); bytes = sizeof_dh_key_der_1024; @@ -2988,8 +3577,8 @@ int dh_test(void) fclose(file); #endif /* USE_CERT_BUFFERS */ - InitDhKey(&key); - InitDhKey(&key2); + InitDhKey(&key); + InitDhKey(&key2); ret = DhKeyDecode(tmp, &idx, &key, bytes); if (ret != 0) return -51; @@ -3002,7 +3591,7 @@ int dh_test(void) ret = InitRng(&rng); if (ret != 0) return -53; - + ret = DhGenerateKeyPair(&key, &rng, priv, &privSz, pub, &pubSz); ret += DhGenerateKeyPair(&key2, &rng, priv2, &privSz2, pub2, &pubSz2); if (ret != 0) @@ -3047,7 +3636,7 @@ int dsa_test(void) byte hash[SHA_DIGEST_SIZE]; byte signature[40]; - + #ifdef USE_CERT_BUFFERS_1024 XMEMCPY(tmp, dsa_key_der_1024, sizeof_dsa_key_der_1024); bytes = sizeof_dsa_key_der_1024; @@ -3063,8 +3652,10 @@ int dsa_test(void) bytes = (word32) fread(tmp, 1, sizeof(tmp), file); fclose(file); #endif /* USE_CERT_BUFFERS */ - - InitSha(&sha); + + ret = InitSha(&sha); + if (ret != 0) + return -4002; ShaUpdate(&sha, tmp, bytes); ShaFinal(&sha, hash); @@ -3081,9 +3672,9 @@ int dsa_test(void) ret = DsaVerify(hash, signature, &key, &answer); if (ret != 0) return -64; if (answer != 1) return -65; - + FreeDsaKey(&key); - + return 0; } @@ -3158,7 +3749,7 @@ int openssl_test(void) e.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b" "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0" "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91" - "\x74\x60\x39"; + "\x74\x60\x39"; e.inLen = strlen(e.input); e.outLen = SHA384_DIGEST_SIZE; @@ -3182,9 +3773,9 @@ int openssl_test(void) "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88" "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4" "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b" - "\x87\x4b\xe9\x09"; + "\x87\x4b\xe9\x09"; f.inLen = strlen(f.input); - f.outLen = SHA512_DIGEST_SIZE; + f.outLen = SHA512_DIGEST_SIZE; EVP_MD_CTX_init(&md_ctx); EVP_DigestInit(&md_ctx, EVP_sha512()); @@ -3200,7 +3791,7 @@ int openssl_test(void) if (RAND_bytes(hash, sizeof(hash)) != 1) return -73; - + c.input = "what do ya want for nothing?"; c.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7" "\x38"; @@ -3222,19 +3813,19 @@ int openssl_test(void) byte plain[24]; byte cipher[24]; - const_DES_cblock key = + const_DES_cblock key = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef }; - DES_cblock iv = + DES_cblock iv = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef }; DES_key_schedule sched; - const byte verify[] = + const byte verify[] = { 0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8, 0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73, @@ -3271,7 +3862,7 @@ int openssl_test(void) 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 }; - const byte verify[] = + const byte verify[] = { 0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53, 0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb @@ -3317,11 +3908,11 @@ int openssl_test(void) int pkcs12_test(void) { const byte passwd[] = { 0x00, 0x73, 0x00, 0x6d, 0x00, 0x65, 0x00, 0x67, - 0x00, 0x00 }; + 0x00, 0x00 }; const byte salt[] = { 0x0a, 0x58, 0xCF, 0x64, 0x53, 0x0d, 0x82, 0x3f }; const byte passwd2[] = { 0x00, 0x71, 0x00, 0x75, 0x00, 0x65, 0x00, 0x65, - 0x00, 0x67, 0x00, 0x00 }; + 0x00, 0x67, 0x00, 0x00 }; const byte salt2[] = { 0x16, 0x82, 0xC0, 0xfC, 0x5b, 0x3f, 0x7e, 0xc5 }; byte derived[64]; @@ -3350,7 +3941,7 @@ int pkcs12_test(void) return -104; iterations = 1000; - ret = PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8, iterations, + ret = PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8, iterations, kLen, SHA, id); if (ret < 0) return -105; @@ -3376,8 +3967,10 @@ int pbkdf2_test(void) }; - PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations, - kLen, SHA); + int ret = PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, + iterations, kLen, SHA); + if (ret != 0) + return ret; if (memcmp(derived, verify, sizeof(verify)) != 0) return -102; @@ -3470,7 +4063,7 @@ int hkdf_test(void) if (memcmp(okm1, res1, L) != 0) return -2002; - + ret = HKDF(SHA, ikm1, 11, salt1, 13, info1, 10, okm1, L); if (ret != 0) return -2003; @@ -3524,6 +4117,10 @@ int ecc_test(void) ecc_init(&pubKey); ret = ecc_make_key(&rng, 32, &userA); + + if (ret != 0) + return -1014; + ret = ecc_make_key(&rng, 32, &userB); if (ret != 0) @@ -3531,10 +4128,13 @@ int ecc_test(void) x = sizeof(sharedA); ret = ecc_shared_secret(&userA, &userB, sharedA, &x); - + + if (ret != 0) + return -1015; + y = sizeof(sharedB); ret = ecc_shared_secret(&userB, &userA, sharedB, &y); - + if (ret != 0) return -1003; @@ -3551,12 +4151,12 @@ int ecc_test(void) ret = ecc_import_x963(exportBuf, x, &pubKey); - if (ret != 0) + if (ret != 0) return -1007; y = sizeof(sharedB); ret = ecc_shared_secret(&userB, &pubKey, sharedB, &y); - + if (ret != 0) return -1008; @@ -3565,11 +4165,14 @@ int ecc_test(void) /* test DSA sign hash */ for (i = 0; i < (int)sizeof(digest); i++) - digest[i] = i; + digest[i] = (byte)i; x = sizeof(sig); ret = ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &userA); - + + if (ret != 0) + return -1016; + verify = 0; ret = ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &userA); @@ -3591,6 +4194,134 @@ int ecc_test(void) return 0; } +#ifdef HAVE_ECC_ENCRYPT + +int ecc_encrypt_test(void) +{ + RNG rng; + int ret; + ecc_key userA, userB; + byte msg[48]; + byte plain[48]; + byte out[80]; + word32 outSz = sizeof(out); + word32 plainSz = sizeof(plain); + int i; + + ret = InitRng(&rng); + if (ret != 0) + return -3001; + + ecc_init(&userA); + ecc_init(&userB); + + ret = ecc_make_key(&rng, 32, &userA); + ret += ecc_make_key(&rng, 32, &userB); + + if (ret != 0) + return -3002; + + for (i = 0; i < 48; i++) + msg[i] = i; + + /* encrypt msg to B */ + ret = ecc_encrypt(&userA, &userB, msg, sizeof(msg), out, &outSz, NULL); + if (ret != 0) + return -3003; + + /* decrypt msg from A */ + ret = ecc_decrypt(&userB, &userA, out, outSz, plain, &plainSz, NULL); + if (ret != 0) + return -3004; + + if (memcmp(plain, msg, sizeof(msg)) != 0) + return -3005; + + + { /* let's verify message exchange works, A is client, B is server */ + ecEncCtx* cliCtx = ecc_ctx_new(REQ_RESP_CLIENT, &rng); + ecEncCtx* srvCtx = ecc_ctx_new(REQ_RESP_SERVER, &rng); + + byte cliSalt[EXCHANGE_SALT_SZ]; + byte srvSalt[EXCHANGE_SALT_SZ]; + const byte* tmpSalt; + + if (cliCtx == NULL || srvCtx == NULL) + return -3006; + + /* get salt to send to peer */ + tmpSalt = ecc_ctx_get_own_salt(cliCtx); + if (tmpSalt == NULL) + return -3007; + memcpy(cliSalt, tmpSalt, EXCHANGE_SALT_SZ); + + tmpSalt = ecc_ctx_get_own_salt(srvCtx); + if (tmpSalt == NULL) + return -3007; + memcpy(srvSalt, tmpSalt, EXCHANGE_SALT_SZ); + + /* in actual use, we'd get the peer's salt over the transport */ + ret = ecc_ctx_set_peer_salt(cliCtx, srvSalt); + ret += ecc_ctx_set_peer_salt(srvCtx, cliSalt); + + if (ret != 0) + return -3008; + + /* get encrypted msg (request) to send to B */ + outSz = sizeof(out); + ret = ecc_encrypt(&userA, &userB, msg, sizeof(msg), out, &outSz,cliCtx); + if (ret != 0) + return -3009; + + /* B decrypts msg (request) from A */ + plainSz = sizeof(plain); + ret = ecc_decrypt(&userB, &userA, out, outSz, plain, &plainSz, srvCtx); + if (ret != 0) + return -3010; + + if (memcmp(plain, msg, sizeof(msg)) != 0) + return -3011; + + { + /* msg2 (response) from B to A */ + byte msg2[48]; + byte plain2[48]; + byte out2[80]; + word32 outSz2 = sizeof(out2); + word32 plainSz2 = sizeof(plain2); + + for (i = 0; i < 48; i++) + msg2[i] = i+48; + + /* get encrypted msg (response) to send to B */ + ret = ecc_encrypt(&userB, &userA, msg2, sizeof(msg2), out2, + &outSz2, srvCtx); + if (ret != 0) + return -3012; + + /* A decrypts msg (response) from B */ + ret = ecc_decrypt(&userA, &userB, out2, outSz2, plain2, &plainSz2, + cliCtx); + if (ret != 0) + return -3013; + + if (memcmp(plain2, msg2, sizeof(msg2)) != 0) + return -3014; + } + + /* cleanup */ + ecc_ctx_free(srvCtx); + ecc_ctx_free(cliCtx); + } + + /* cleanup */ + ecc_free(&userB); + ecc_free(&userA); + + return 0; +} + +#endif /* HAVE_ECC_ENCRYPT */ #endif /* HAVE_ECC */ #ifdef HAVE_LIBZ @@ -3700,7 +4431,7 @@ int compress_test(void) if (ret == 0 && memcmp(d, sample_text, dSz)) ret = -303; - + if (c) free(c); if (d) free(d); @@ -3709,4 +4440,319 @@ int compress_test(void) #endif /* HAVE_LIBZ */ +#ifdef HAVE_PKCS7 + +int pkcs7enveloped_test(void) +{ + int ret = 0; + + int cipher = DES3b; + int envelopedSz, decodedSz; + PKCS7 pkcs7; + byte* cert; + byte* privKey; + byte enveloped[2048]; + byte decoded[2048]; + + size_t certSz; + size_t privKeySz; + FILE* certFile; + FILE* keyFile; + FILE* pkcs7File; + const char* pkcs7OutFile = "pkcs7envelopedData.der"; + + const byte data[] = { /* Hello World */ + 0x48,0x65,0x6c,0x6c,0x6f,0x20,0x57,0x6f, + 0x72,0x6c,0x64 + }; + + /* read client cert and key in DER format */ + cert = (byte*)malloc(FOURK_BUF); + if (cert == NULL) + return -201; + + privKey = (byte*)malloc(FOURK_BUF); + if (privKey == NULL) { + free(cert); + return -202; + } + + certFile = fopen(clientCert, "rb"); + if (!certFile) { + free(cert); + free(privKey); + err_sys("can't open ./certs/client-cert.der, " + "Please run from CyaSSL home dir", -42); + } + + certSz = fread(cert, 1, FOURK_BUF, certFile); + fclose(certFile); + + keyFile = fopen(clientKey, "rb"); + if (!keyFile) { + free(cert); + free(privKey); + err_sys("can't open ./certs/client-key.der, " + "Please run from CyaSSL home dir", -43); + } + + privKeySz = fread(privKey, 1, FOURK_BUF, keyFile); + fclose(keyFile); + + PKCS7_InitWithCert(&pkcs7, cert, (word32)certSz); + pkcs7.content = (byte*)data; + pkcs7.contentSz = (word32)sizeof(data); + pkcs7.contentOID = DATA; + pkcs7.encryptOID = cipher; + pkcs7.privateKey = privKey; + pkcs7.privateKeySz = (word32)privKeySz; + + /* encode envelopedData */ + envelopedSz = PKCS7_EncodeEnvelopedData(&pkcs7, enveloped, + sizeof(enveloped)); + if (envelopedSz <= 0) { + free(cert); + free(privKey); + return -203; + } + + /* decode envelopedData */ + decodedSz = PKCS7_DecodeEnvelopedData(&pkcs7, enveloped, envelopedSz, + decoded, sizeof(decoded)); + if (decodedSz <= 0) { + free(cert); + free(privKey); + return -204; + } + + /* test decode result */ + if (memcmp(decoded, data, sizeof(data)) != 0) { + free(cert); + free(privKey); + return -205; + } + + /* output pkcs7 envelopedData for external testing */ + pkcs7File = fopen(pkcs7OutFile, "wb"); + if (!pkcs7File) { + free(cert); + free(privKey); + return -206; + } + + ret = (int)fwrite(enveloped, envelopedSz, 1, pkcs7File); + fclose(pkcs7File); + + free(cert); + free(privKey); + PKCS7_Free(&pkcs7); + + if (ret > 0) + return 0; + + return ret; +} + +int pkcs7signed_test(void) +{ + int ret = 0; + + FILE* file; + byte* certDer; + byte* keyDer; + byte* out; + char data[] = "Hello World"; + word32 dataSz, outSz, certDerSz, keyDerSz; + PKCS7 msg; + RNG rng; + + byte transIdOid[] = + { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01, + 0x09, 0x07 }; + byte messageTypeOid[] = + { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01, + 0x09, 0x02 }; + byte senderNonceOid[] = + { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01, + 0x09, 0x05 }; + byte transId[(SHA_DIGEST_SIZE + 1) * 2 + 1]; + byte messageType[] = { 0x13, 2, '1', '9' }; + byte senderNonce[PKCS7_NONCE_SZ + 2]; + + PKCS7Attrib attribs[] = + { + { transIdOid, sizeof(transIdOid), + transId, sizeof(transId) - 1 }, /* take off the null */ + { messageTypeOid, sizeof(messageTypeOid), + messageType, sizeof(messageType) }, + { senderNonceOid, sizeof(senderNonceOid), + senderNonce, sizeof(senderNonce) } + }; + + dataSz = (word32) strlen(data); + outSz = FOURK_BUF; + + certDer = (byte*)malloc(FOURK_BUF); + if (certDer == NULL) + return -207; + keyDer = (byte*)malloc(FOURK_BUF); + if (keyDer == NULL) { + free(certDer); + return -208; + } + out = (byte*)malloc(FOURK_BUF); + if (out == NULL) { + free(certDer); + free(keyDer); + return -209; + } + + /* read in DER cert of recipient, into cert of size certSz */ + file = fopen(clientCert, "rb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + err_sys("can't open ./certs/client-cert.der, " + "Please run from CyaSSL home dir", -44); + } + certDerSz = (word32)fread(certDer, 1, FOURK_BUF, file); + fclose(file); + + file = fopen(clientKey, "rb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + err_sys("can't open ./certs/client-key.der, " + "Please run from CyaSSL home dir", -45); + } + keyDerSz = (word32)fread(keyDer, 1, FOURK_BUF, file); + fclose(file); + + ret = InitRng(&rng); + if (ret != 0) { + free(certDer); + free(keyDer); + free(out); + return -210; + } + + senderNonce[0] = 0x04; + senderNonce[1] = PKCS7_NONCE_SZ; + + ret = RNG_GenerateBlock(&rng, &senderNonce[2], PKCS7_NONCE_SZ); + if (ret != 0) { + free(certDer); + free(keyDer); + free(out); + return -211; + } + + PKCS7_InitWithCert(&msg, certDer, certDerSz); + msg.privateKey = keyDer; + msg.privateKeySz = keyDerSz; + msg.content = (byte*)data; + msg.contentSz = dataSz; + msg.hashOID = SHAh; + msg.encryptOID = RSAk; + msg.signedAttribs = attribs; + msg.signedAttribsSz = sizeof(attribs)/sizeof(PKCS7Attrib); + msg.rng = &rng; + { + Sha sha; + byte digest[SHA_DIGEST_SIZE]; + int i,j; + + transId[0] = 0x13; + transId[1] = SHA_DIGEST_SIZE * 2; + + ret = InitSha(&sha); + if (ret != 0) { + free(certDer); + free(keyDer); + free(out); + return -4003; + } + ShaUpdate(&sha, msg.publicKey, msg.publicKeySz); + ShaFinal(&sha, digest); + + for (i = 0, j = 2; i < SHA_DIGEST_SIZE; i++, j += 2) { + snprintf((char*)&transId[j], 3, "%02x", digest[i]); + } + } + ret = PKCS7_EncodeSignedData(&msg, out, outSz); + if (ret < 0) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -212; + } + else + outSz = ret; + + /* write PKCS#7 to output file for more testing */ + file = fopen("./pkcs7signedData.der", "wb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -213; + } + ret = (int)fwrite(out, 1, outSz, file); + fclose(file); + if (ret != (int)outSz) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -218; + } + + PKCS7_Free(&msg); + PKCS7_InitWithCert(&msg, NULL, 0); + + ret = PKCS7_VerifySignedData(&msg, out, outSz); + if (ret < 0) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -214; + } + + if (msg.singleCert == NULL || msg.singleCertSz == 0) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -215; + } + + file = fopen("./pkcs7cert.der", "wb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -216; + } + ret = (int)fwrite(msg.singleCert, 1, msg.singleCertSz, file); + fclose(file); + + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + + if (ret > 0) + return 0; + + return ret; +} + +#endif /* HAVE_PKCS7 */ + #endif /* NO_CRYPT_TEST */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt b/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt index b541cb662c..dde67ce4f7 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt @@ -1,13 +1,12 @@ This program gives wolfCrypt and CyaSSL library demo. In order to run the demo, -Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +Copy {PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. For demo configuration, refer config-Crypt.h and config-CyaSSL.h. After download and start the execution, you can type in commands through the Debug(printf) viewer. -time [-d date][-t time] Set/Get RTC: The time is used for certificate validation. test wolfCrypt Simple test suite benchmark wolfCrypt Simple benchmark server& simple server in background mode @@ -20,9 +19,6 @@ server/client -h help for server/client command === Typical Command Usage Scenario === Starting Shell ->time -d 9/23/2013 ->time -Date: 9/23/2013, Time: 00:38:31 >test MD5 test passed! MD4 test passed! diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx index 4084d9ab17..714391aa76 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx @@ -76,6 +76,23 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL -REMAP -MPU @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,7 +135,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -221,54 +240,6 @@ 0 0 0 - 57 - 80 - 0 - .\main.c - main.c - 0 - 0 - - - 1 - 2 - 1 - 0 - 0 - 13 - 0 - 0 - 0 - 0 - .\shell.c - shell.c - 0 - 0 - - - 1 - 3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\test.c - test.c - 0 - 0 - - - 1 - 4 - 1 - 0 - 0 - 0 - 0 0 0 0 @@ -279,11 +250,11 @@ 1 - 5 + 2 1 0 0 - 0 + 24 0 0 0 @@ -295,11 +266,11 @@ 1 - 6 + 3 1 0 0 - 2 + 10 0 0 0 @@ -311,7 +282,7 @@ 1 - 7 + 4 1 0 0 @@ -327,7 +298,7 @@ 1 - 8 + 5 1 0 0 @@ -343,7 +314,7 @@ 1 - 9 + 6 1 0 0 @@ -357,6 +328,54 @@ 0 0 + + 1 + 7 + 1 + 0 + 0 + 34 + 0 + 0 + 0 + 0 + .\test.c + test.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 72 + 84 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\shell.c + shell.c + 0 + 0 + @@ -397,6 +416,38 @@ 0 0 + + 2 + 12 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\RTE\wolfSSL\settings.h + settings.h + 0 + 0 + + + 2 + 13 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\RTE\Network\Net_Config_ETH_0.h + Net_Config_ETH_0.h + 0 + 0 + @@ -407,14 +458,14 @@ 0 3 - 12 + 14 5 0 0 10 0 - 1 - 32 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -424,30 +475,14 @@ - ::CMSIS - 0 + Devices + 1 0 0 - 1 + 0 4 - 13 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib - RTX_CM3.lib - 1 - 0 - - - 4 - 14 + 15 1 0 0 @@ -456,11 +491,67 @@ 0 0 0 + .\time-CortexM3-4.c + time-CortexM3-4.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\time-dummy.c + time-dummy.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + 5 + 17 + 1 + 0 + 0 + 0 + 0 + 278 + 285 + 0 RTE\CMSIS\RTX_Conf_CM.c RTX_Conf_CM.c 1 0 + + 5 + 18 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + RTX_CM3.lib + 1 + 0 + @@ -470,40 +561,8 @@ 0 1 - 5 - 15 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 - 0 - - - 5 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c - 1 - 0 - - - 5 - 17 + 6 + 19 5 0 0 @@ -518,14 +577,14 @@ 0 - 5 - 18 + 6 + 20 2 0 0 0 0 - 163 + 164 169 0 RTE\Device\STM32F207IG\startup_stm32f2xx.s @@ -533,46 +592,6 @@ 1 0 - - 5 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RTE\Device\STM32F207IG\system_stm32f2xx.c - system_stm32f2xx.c - 1 - 0 - - - - - ::Drivers - 0 - 0 - 0 - 1 - - 6 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c - PHY_ST802RT1.c - 1 - 0 - 6 21 @@ -584,8 +603,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c - EMAC_STM32F2xx.c + RTE\Device\STM32F207IG\system_stm32f2xx.c + system_stm32f2xx.c 1 0 @@ -600,7 +619,79 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c + 1 + 0 + + + 6 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c + 1 + 0 + + + + + ::Drivers + 0 + 0 + 0 + 1 + + 7 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c + PHY_ST802RT1.c + 1 + 0 + + + 7 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c + EMAC_STM32F2xx.c + 1 + 0 + + + 7 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c MCI_STM32F2xx.c 1 0 @@ -614,24 +705,8 @@ 0 1 - 7 - 23 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib - 1 - 0 - - - 7 - 24 + 8 + 27 1 0 0 @@ -646,8 +721,8 @@ 0 - 7 - 25 + 8 + 28 5 0 0 @@ -661,17 +736,9 @@ 1 0 - - - - ::Network - 1 - 0 - 0 - 1 8 - 26 + 29 4 0 0 @@ -680,14 +747,22 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Dbg_CM3_L.lib + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib 1 0 + + + + ::Network + 0 + 0 + 0 + 1 - 8 - 27 + 9 + 30 1 0 0 @@ -702,8 +777,8 @@ 0 - 8 - 28 + 9 + 31 5 0 0 @@ -718,8 +793,8 @@ 0 - 8 - 29 + 9 + 32 5 0 0 @@ -734,8 +809,8 @@ 0 - 8 - 30 + 9 + 33 5 0 0 @@ -750,8 +825,8 @@ 0 - 8 - 31 + 9 + 34 5 0 0 @@ -766,8 +841,8 @@ 0 - 8 - 32 + 9 + 35 5 0 0 @@ -782,8 +857,8 @@ 0 - 8 - 33 + 9 + 36 1 0 0 @@ -797,17 +872,33 @@ 1 0 + + 9 + 37 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + Net_Dbg_CM3_L.lib + 1 + 0 + ::wolfSSL - 1 + 0 0 0 1 - 9 - 34 + 10 + 38 5 0 0 @@ -822,8 +913,8 @@ 0 - 9 - 35 + 10 + 39 5 0 0 @@ -838,73 +929,9 @@ 0 - 9 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 9 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 9 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 9 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c - arc4.c - 1 - 0 - - - 9 + 10 40 - 1 + 5 0 0 0 @@ -912,13 +939,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c - asm.c + RTE\wolfSSL\settings.h + settings.h 1 0 - 9 + 10 41 1 0 @@ -928,13 +955,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c - asn.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c 1 0 - 9 + 10 42 1 0 @@ -944,13 +971,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c - blake2b.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c 1 0 - 9 + 10 43 1 0 @@ -960,13 +987,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c - camellia.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c 1 0 - 9 + 10 44 1 0 @@ -976,13 +1003,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c - coding.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c 1 0 - 9 + 10 45 1 0 @@ -992,13 +1019,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c - compress.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c 1 0 - 9 + 10 46 1 0 @@ -1008,13 +1035,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c - des3.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c 1 0 - 9 + 10 47 1 0 @@ -1024,13 +1051,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c - dh.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c 1 0 - 9 + 10 48 1 0 @@ -1040,13 +1067,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c - dsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c 1 0 - 9 + 10 49 1 0 @@ -1056,13 +1083,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c - ecc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c 1 0 - 9 + 10 50 1 0 @@ -1072,13 +1099,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c 1 0 - 9 + 10 51 1 0 @@ -1088,13 +1115,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c - error.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c 1 0 - 9 + 10 52 1 0 @@ -1104,13 +1131,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c - hc128.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c 1 0 - 9 + 10 53 1 0 @@ -1120,13 +1147,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c - hmac.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c 1 0 - 9 + 10 54 1 0 @@ -1136,13 +1163,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c - integer.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c 1 0 - 9 + 10 55 1 0 @@ -1152,13 +1179,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c - logging.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c 1 0 - 9 + 10 56 1 0 @@ -1168,13 +1195,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c - md2.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c 1 0 - 9 + 10 57 1 0 @@ -1184,13 +1211,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c - md4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c 1 0 - 9 + 10 58 1 0 @@ -1200,13 +1227,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c - md5.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c 1 0 - 9 + 10 59 1 0 @@ -1216,13 +1243,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c - memory.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c 1 0 - 9 + 10 60 1 0 @@ -1232,13 +1259,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c - misc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c 1 0 - 9 + 10 61 1 0 @@ -1248,13 +1275,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c - port.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c 1 0 - 9 + 10 62 1 0 @@ -1264,13 +1291,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c 1 0 - 9 + 10 63 1 0 @@ -1280,13 +1307,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c - rabbit.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c 1 0 - 9 + 10 64 1 0 @@ -1296,13 +1323,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c - random.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c 1 0 - 9 + 10 65 1 0 @@ -1312,13 +1339,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c - ripemd.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c 1 0 - 9 + 10 66 1 0 @@ -1328,13 +1355,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c - rsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c 1 0 - 9 + 10 67 1 0 @@ -1344,13 +1371,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c - sha.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c 1 0 - 9 + 10 68 1 0 @@ -1360,13 +1387,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c - sha256.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c 1 0 - 9 + 10 69 1 0 @@ -1376,13 +1403,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c - sha512.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c 1 0 - 9 + 10 70 1 0 @@ -1392,13 +1419,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c - tfm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c 1 0 - 9 + 10 71 1 0 @@ -1408,13 +1435,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\crl.c - crl.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c 1 0 - 9 + 10 72 1 0 @@ -1424,13 +1451,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\internal.c - internal.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c 1 0 - 9 + 10 73 1 0 @@ -1440,13 +1467,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\io.c - io.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c 1 0 - 9 + 10 74 1 0 @@ -1456,13 +1483,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\keys.c - keys.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + tfm.c 1 0 - 9 + 10 75 1 0 @@ -1472,13 +1499,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ocsp.c - ocsp.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + crl.c 1 0 - 9 + 10 76 1 0 @@ -1488,13 +1515,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\sniffer.c - sniffer.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + internal.c 1 0 - 9 + 10 77 1 0 @@ -1504,13 +1531,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ssl.c - ssl.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + io.c 1 0 - 9 + 10 78 1 0 @@ -1520,7 +1547,71 @@ 0 0 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\tls.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + keys.c + 1 + 0 + + + 10 + 79 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + ocsp.c + 1 + 0 + + + 10 + 80 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + sniffer.c + 1 + 0 + + + 10 + 81 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + ssl.c + 1 + 0 + + + 10 + 82 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c tls.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx index 83d2df29f3..9f4bea3a65 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,6 +355,8 @@ 0 0 0 + 0 + 0 HAVE_CONFIG_H MDK_CONF_CYASSL @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -398,21 +404,6 @@ Source - - main.c - 1 - .\main.c - - - shell.c - 1 - .\shell.c - - - test.c - 1 - .\test.c - benchmark.c 1 @@ -443,6 +434,21 @@ 1 .\cert_data.c + + test.c + 1 + .\test.c + + + main.c + 1 + .\main.c + + + shell.c + 1 + .\shell.c + @@ -458,6 +464,16 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + settings.h + 5 + .\RTE\wolfSSL\settings.h + + + Net_Config_ETH_0.h + 5 + .\RTE\Network\Net_Config_ETH_0.h + @@ -471,33 +487,38 @@ - ::CMSIS + Devices - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + time-CortexM3-4.c + 1 + .\time-CortexM3-4.c + + time-dummy.c + 1 + .\time-dummy.c + + + + + ::CMSIS + RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -513,6 +534,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -521,28 +552,23 @@ PHY_ST802RT1.c 1 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c EMAC_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -553,16 +579,16 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + ::Network - - Net_Dbg_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Config.c 1 @@ -598,6 +624,11 @@ 1 RTE\Network\Net_Debug.c + + Net_Dbg_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + @@ -614,219 +645,219 @@ RTE\wolfSSL\config-CyaSSL.h - cyassl_MDK_ARM.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + settings.h + 5 + RTE\wolfSSL\settings.h - time-STM32F2xx.c + cyassl_MDK_ARM.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c aes.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c arc4.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c asm.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c asn.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c blake2b.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c camellia.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c coding.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c compress.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c des3.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c dh.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c dsa.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c ecc.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c ecc_fp.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c error.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c hc128.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c hmac.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c integer.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c logging.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c md2.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c md4.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c md5.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c memory.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c misc.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c port.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c pwdbased.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c rabbit.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c random.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c ripemd.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c rsa.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c sha.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c sha256.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c sha512.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c tfm.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c crl.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\crl.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c internal.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\internal.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c io.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\io.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c keys.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\keys.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c ocsp.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ocsp.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c sniffer.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\sniffer.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c ssl.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ssl.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c tls.c 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\tls.c + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c @@ -868,20 +899,20 @@ - - + + - - + + - - + + @@ -958,20 +989,14 @@ - - + + - - - - - - - - + + @@ -980,8 +1005,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -1084,38 +1109,46 @@ RTE\Other\config-RTX-TCP-FS.h - - + + RTE\Other\config.h - - + + - + RTE\wolfSSL\config-Crypt.h - - + + - + RTE\wolfSSL\config-CyaSSL.h - - + + RTE\wolfSSL\config.h - - + + + + RTE\wolfSSL\settings.h + + + + + + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index 3ff6766f3c..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 6 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 250 -#endif - -// Main Thread stack size [bytes] <64-4096:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 250 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 2 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 4500 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-64000:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 4a09246f38..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 1 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index 205f9ffbb7..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00001000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x0000F000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c deleted file mode 100644 index 6b9dc8e00d..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c +++ /dev/null @@ -1,153 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Definitions -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "my_host" - -// Memory Pool size <1536-262144:4><#/4> -// This is the size of a memory pool in bytes. Buffers for -// Network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_SIZE 3000 - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP_0 -#include "Net_Config_PPP_0.h" -#endif -#ifdef RTE_Network_Interface_PPP_1 -#include "Net_Config_PPP_1.h" -#endif - -#ifdef RTE_Network_Interface_SLIP_0 -#include "Net_Config_SLIP_0.h" -#endif -#ifdef RTE_Network_Interface_SLIP_1 -#include "Net_Config_SLIP_1.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (ERROR_CODE error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (ERROR_CODE error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case ERR_MEM_ALLOC: - /* Out of memory */ - break; - - case ERR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case ERR_MEM_CORRUPT: - /* Memory Link pointer Corrupted */ - /* More data written than the size of allocated mem block */ - break; - - case ERR_MEM_LOCK: - /* Locked Memory management function (alloc/free) re-entered */ - break; - - case ERR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case ERR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case ERR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index 7d515a5072..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,36 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration BSD Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 10 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 1 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h deleted file mode 100644 index d30b718079..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_DNS_Client.h - * Purpose: Network Configuration DNS Client - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// DNS Client -#define DNS_CLIENT_ENABLE 1 - -// Cache Table size <5-100> -// Number of cached DNS host names/IP addresses -// Default: 20 -#define DNS_CLIENT_TAB_SIZE 20 - -// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index 7be57ad6d5..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,222 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration ETH Interface - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 1 - -// MAC Address -// Local Ethernet MAC Address -// Value FF:FF:FF:FF:FF:FF is not allowed. -// It is an ethernet Broadcast MAC address. -// Address byte 1 <0x00-0xff:2> -// LSB is an ethernet Multicast bit. -// Must be 0 for local MAC address. -// Default: 0x1E -#define ETH0_MAC1 0x1E - -// Address byte 2 <0x00-0xff> -// Default: 0x30 -#define ETH0_MAC2 0x30 - -// Address byte 3 <0x00-0xff> -// Default: 0x6C -#define ETH0_MAC3 0x6C - -// Address byte 4 <0x00-0xff> -// Default: 0xA2 -#define ETH0_MAC4 0xA2 - -// Address byte 5 <0x00-0xff> -// Default: 0x45 -#define ETH0_MAC5 0x45 - -// Address byte 6 <0x00-0xff> -// Default: 0x5E -#define ETH0_MAC6 0x5E -// - -// IP Address -// Local Static IP Address -// Value 255.255.255.255 is not allowed. -// It is a Broadcast IP address. -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_IP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_IP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_IP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define ETH0_IP4 100 -// - -// Subnet mask -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define ETH0_MASK1 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define ETH0_MASK2 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define ETH0_MASK3 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define ETH0_MASK4 0 -// - -// Default Gateway -// Default Gateway IP Address -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_GW1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_GW2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_GW3 0 - -// Address byte 4 <0-255> -// Default: 254 -#define ETH0_GW4 254 -// - -// Primary DNS Server -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_PRI_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_PRI_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_PRI_DNS3 2 - -// Address byte 4 <0-255> -// Default: 129 -#define ETH0_PRI_DNS4 129 -// - -// Secondary DNS Server -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_SEC_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_SEC_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_SEC_DNS3 2 - -// Address byte 4 <0-255> -// Default: 130 -#define ETH0_SEC_DNS4 130 -// - -// ARP Definitions -// Address Resolution Protocol Definitions -// Cache Table size <5-100> -// Number of cached hardware/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for a cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by his name on the local LAN using NBNS protocol. -// You need to modify also the number of UDP Sockets, -// because NBNS protocol uses one UDP socket to run. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -// You need to modify also the number of UDP Sockets, -// because DHCP protocol uses one UDP socket to run. -#define ETH0_DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// - -// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index e659ce9211..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,61 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration TCP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 5 -#define TCP_NUM_SOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low_throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-600> -// Default TCP Socket Keep Alive timeout. When it expires -// with no TCP data frame send, TCP Connection is closed. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1460> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1460 -#define TCP_MAX_SEG_SIZE 1460 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4380 -#define TCP_RECEIVE_WIN_SIZE 4380 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index 55e7f21ba9..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration UDP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-30> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 15 - -// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c deleted file mode 100644 index 735089a409..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c +++ /dev/null @@ -1,125 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Debug.c - * Purpose: Network Debug Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Print Time Stamp -// Enable printing the time-info in debug messages -#define DBG_TIME 1 - -// TCPnet Debug Definitions -// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Memory debug messages -#define DBG_MEM 1 - -// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Ethernet debug messages -#define DBG_ETH 0 - -// PPP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off PPP debug messages -#define DBG_PPP 0 - -// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SLIP debug messages -#define DBG_SLIP 0 - -// ARP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ARP debug messages -#define DBG_ARP 0 - -// IP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IP debug messages -#define DBG_IP 1 - -// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ICMP debug messages -#define DBG_ICMP 1 - -// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IGMP debug messages -#define DBG_IGMP 1 - -// UDP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off UDP debug messages -#define DBG_UDP 1 - -// TCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TCP debug messages -#define DBG_TCP 1 - -// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off NetBIOS Name Service debug messages -#define DBG_NBNS 1 - -// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Host Configuration debug messages -#define DBG_DHCP 1 - -// DNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Domain Name Service debug messages -#define DBG_DNS 1 - -// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Management debug messages -#define DBG_SNMP 1 - -// SNTP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Time debug messages -#define DBG_SNTP 1 - -// BSD Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off BSD Interface debug messages -#define DBG_BSD 1 -// - -// Application Debug Definitions -// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Web Server debug messages -#define DBG_HTTP_SERVER 1 - -// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Server debug messages -#define DBG_FTP_SERVER 1 - -// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Client debug messages -#define DBG_FTP_CLIENT 1 - -// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Telnet Server debug messages -#define DBG_TELNET_SERVER 1 - -// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Server debug messages -#define DBG_TFTP_SERVER 1 - -// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Client debug messages -#define DBG_TFTP_CLIENT 1 - -// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SMTP Client debug messages -#define DBG_SMTP_CLIENT 1 -// - - -#include "net_debug.h" - - -/** - \fn void net_debug_init (void) - \brief Initialize Network Debug Interface. -*/ -void net_debug_init (void) { - /* Add your code to initialize the Debug output. This is usually the */ - /* serial interface. The function is called at TCPnet system startup. */ - /* You may need to customize also the 'putchar()' function. */ - -} diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h deleted file mode 100644 index 07fef4e5e3..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h +++ /dev/null @@ -1,28 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'CyaSSL-Full' - * Target: 'CyaSSL-Full' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ -#define RTE_Network_Core /* Network Core */ - #define RTE_Network_Debug /* Network Debug Version */ -#define RTE_Network_DNS_Client /* Network DNS Client */ -#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ -#define RTE_Network_Socket_BSD /* Network Socket BSD */ -#define RTE_Network_Socket_TCP /* Network Socket TCP */ -#define RTE_Network_Socket_UDP /* Network Socket UDP */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..33d41cfdbe --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/wolfSSL/settings.h @@ -0,0 +1,667 @@ +/* settings.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using PIC32MZ Crypto Engine */ +/* #define CYASSL_MICROCHIP_PIC32MZ */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + +/* Uncomment next line if using LwIP native TCP socket settings */ +/* #define HAVE_LWIP_NATIVE */ + +/* Uncomment next line if building for EROAD */ +/* #define CYASSL_EROAD */ + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef CYASSL_USER_SETTINGS + #include +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */ + #define CYASSL_LWIP + #define NO_WRITEV + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_FILESYSTEM +#endif + +#ifdef MICROCHIP_PIC32 + /* #define CYASSL_MICROCHIP_PIC32MZ */ + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef CYASSL_MICROCHIP_PIC32MZ + #define CYASSL_PIC32MZ_CE + #define CYASSL_PIC32MZ_CRYPT + #define HAVE_AES_ENGINE + #define CYASSL_PIC32MZ_RNG + /* #define CYASSL_PIC32MZ_HASH */ + #define CYASSL_AES_COUNTER + #define HAVE_AESGCM + #define NO_BIG_INT + +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "system/system_services.h" + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define CYASSL_USER_IO + #define NO_FILESYSTEM + #define NO_CERT + #define USE_CERT_BUFFERS_1024 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define HAVE_ECC + #define NO_SESSION_CACHE + #define CYASSL_CMSIS_RTOS +#endif + + +#ifdef CYASSL_EROAD + #define FREESCALE_MQX + #define FREESCALE_MMCAU + #define SINGLE_THREADED + #define NO_STDIO_FILESYSTEM + #define CYASSL_LEANPSK + #define HAVE_NULL_CIPHER + #define NO_OLD_TLS + #define NO_ASN + #define NO_BIG_INT + #define NO_RSA + #define NO_DSA + #define NO_DH + #define NO_CERTS + #define NO_PWDBASED + #define NO_DES3 + #define NO_MD4 + #define NO_RC4 + #define NO_MD5 + #define NO_SESSION_CACHE + #define NO_MAIN_DRIVER +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) && !defined(CYASSL_EROAD) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c index 5e5b14f07c..2cccd362a3 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c @@ -51,9 +51,15 @@ #include "cavium_common.h" #include "cavium_ioctl.h" #endif + +#if defined(CYASSL_MDK_ARM) + extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ; + #define fopen CyaSSL_fopen +#endif + #if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) /* include test cert and key buffers for use with NO_FILESYSTEM */ - #if defined(CYASSL_MDK_ARM) && !defined(SINGLE_THREADED) + #if defined(CYASSL_MDK_ARM) #include "cert_data.h" /* use certs_test.c for initial data, so other commands can share the data. */ #else @@ -61,11 +67,6 @@ #endif #endif -#if defined(CYASSL_MDK_ARM) - #include - extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ; - #define fopen CyaSSL_fopen -#endif #ifdef HAVE_BLAKE2 #include @@ -84,6 +85,7 @@ void bench_rabbit(void); void bench_aes(int); void bench_aesgcm(void); void bench_aesccm(void); +void bench_aesctr(void); void bench_camellia(void); void bench_md5(void); @@ -140,7 +142,7 @@ int benchmark_test(void *args) { #endif - #ifdef HAVE_CAVIUM + #ifdef HAVE_CAVIUM int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); if (ret != 0) { printf("Cavium OpenNitroxDevice failed\n"); @@ -154,6 +156,11 @@ int benchmark_test(void *args) #ifdef HAVE_AESGCM bench_aesgcm(); #endif + +#ifdef CYASSL_AES_COUNTER + bench_aesctr(); +#endif + #ifdef HAVE_AESCCM bench_aesccm(); #endif @@ -218,23 +225,31 @@ int benchmark_test(void *args) #ifdef BENCH_EMBEDDED -const int numBlocks = 25; /* how many kB/megs to test (en/de)cryption */ -const char blockType[] = "kB"; /* used in printf output */ -const int times = 1; /* public key iterations */ +enum BenchmarkBounds { + numBlocks = 25, /* how many kB to test (en/de)cryption */ + ntimes = 1, + genTimes = 5, /* public key iterations */ + agreeTimes = 5 +}; +static const char blockType[] = "kB"; /* used in printf output */ #else -const int numBlocks = 5; -const char blockType[] = "megs"; -const int times = 100; +enum BenchmarkBounds { + numBlocks = 5, /* how many megs to test (en/de)cryption */ + ntimes = 100, + genTimes = 100, + agreeTimes = 100 +}; +static const char blockType[] = "megs"; /* used in printf output */ #endif -const byte key[] = +static const byte key[] = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 }; -const byte iv[] = +static const byte iv[] = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, @@ -245,11 +260,11 @@ const byte iv[] = /* use kB instead of mB for embedded benchmarking */ #ifdef BENCH_EMBEDDED -byte plain [1024]; -byte cipher[1024]; +static byte plain [1024]; +static byte cipher[1024]; #else -byte plain [1024*1024]; -byte cipher[1024*1024]; +static byte plain [1024*1024]; +static byte cipher[1024*1024]; #endif @@ -259,13 +274,20 @@ void bench_aes(int show) Aes enc; double start, total, persec; int i; + int ret; #ifdef HAVE_CAVIUM - if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) + if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) { printf("aes init cavium failed\n"); + return; + } #endif - AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION); + ret = AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION); + if (ret != 0) { + printf("AesSetKey failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -280,7 +302,7 @@ void bench_aes(int show) #endif if (show) - printf("AES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("AES %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); #ifdef HAVE_CAVIUM AesFreeCavium(&enc); @@ -289,8 +311,10 @@ void bench_aes(int show) #endif -byte additional[13]; -byte tag[16]; +#if defined(HAVE_AESGCM) || defined(HAVE_AESCCM) + static byte additional[13]; + static byte tag[16]; +#endif #ifdef HAVE_AESGCM @@ -315,11 +339,38 @@ void bench_aesgcm(void) persec = persec / 1024; #endif - printf("AES-GCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("AES-GCM %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif +#ifdef CYASSL_AES_COUNTER +void bench_aesctr(void) +{ + Aes enc; + double start, total, persec; + int i; + + AesSetKeyDirect(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesCtrEncrypt(&enc, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("AES-CTR %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + #ifdef HAVE_AESCCM void bench_aesccm(void) @@ -343,7 +394,7 @@ void bench_aesccm(void) persec = persec / 1024; #endif - printf("AES-CCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("AES-CCM %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -354,9 +405,13 @@ void bench_camellia(void) { Camellia cam; double start, total, persec; - int i; + int i, ret; - CamelliaSetKey(&cam, key, 16, iv); + ret = CamelliaSetKey(&cam, key, 16, iv); + if (ret != 0) { + printf("CamelliaSetKey failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -370,7 +425,7 @@ void bench_camellia(void) persec = persec / 1024; #endif - printf("Camellia %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("Camellia %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -381,13 +436,17 @@ void bench_des(void) { Des3 enc; double start, total, persec; - int i; + int i, ret; #ifdef HAVE_CAVIUM if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) printf("des3 init cavium failed\n"); #endif - Des3_SetKey(&enc, key, iv, DES_ENCRYPTION); + ret = Des3_SetKey(&enc, key, iv, DES_ENCRYPTION); + if (ret != 0) { + printf("Des3_SetKey failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -401,7 +460,7 @@ void bench_des(void) persec = persec / 1024; #endif - printf("3DES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("3DES %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); #ifdef HAVE_CAVIUM Des3_FreeCavium(&enc); @@ -435,7 +494,7 @@ void bench_arc4(void) persec = persec / 1024; #endif - printf("ARC4 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("ARC4 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); #ifdef HAVE_CAVIUM Arc4FreeCavium(&enc); @@ -464,7 +523,7 @@ void bench_hc128(void) persec = persec / 1024; #endif - printf("HC128 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("HC128 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* HAVE_HC128 */ @@ -490,7 +549,7 @@ void bench_rabbit(void) persec = persec / 1024; #endif - printf("RABBIT %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("RABBIT %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* NO_RABBIT */ @@ -519,7 +578,7 @@ void bench_md5(void) persec = persec / 1024; #endif - printf("MD5 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("MD5 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* NO_MD5 */ @@ -531,9 +590,13 @@ void bench_sha(void) Sha hash; byte digest[SHA_DIGEST_SIZE]; double start, total, persec; - int i; + int i, ret; - InitSha(&hash); + ret = InitSha(&hash); + if (ret != 0) { + printf("InitSha failed, ret = %d\n", ret); + return; + } start = current_time(1); for(i = 0; i < numBlocks; i++) @@ -548,7 +611,7 @@ void bench_sha(void) persec = persec / 1024; #endif - printf("SHA %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("SHA %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif /* NO_SHA */ @@ -560,15 +623,28 @@ void bench_sha256(void) Sha256 hash; byte digest[SHA256_DIGEST_SIZE]; double start, total, persec; - int i; + int i, ret; - InitSha256(&hash); + ret = InitSha256(&hash); + if (ret != 0) { + printf("InitSha256 failed, ret = %d\n", ret); + return; + } start = current_time(1); - for(i = 0; i < numBlocks; i++) - Sha256Update(&hash, plain, sizeof(plain)); + for(i = 0; i < numBlocks; i++) { + ret = Sha256Update(&hash, plain, sizeof(plain)); + if (ret != 0) { + printf("Sha256Update failed, ret = %d\n", ret); + return; + } + } - Sha256Final(&hash, digest); + ret = Sha256Final(&hash, digest); + if (ret != 0) { + printf("Sha256Final failed, ret = %d\n", ret); + return; + } total = current_time(0) - start; persec = 1 / total * numBlocks; @@ -577,7 +653,7 @@ void bench_sha256(void) persec = persec / 1024; #endif - printf("SHA-256 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("SHA-256 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -588,15 +664,28 @@ void bench_sha512(void) Sha512 hash; byte digest[SHA512_DIGEST_SIZE]; double start, total, persec; - int i; + int i, ret; - InitSha512(&hash); + ret = InitSha512(&hash); + if (ret != 0) { + printf("InitSha512 failed, ret = %d\n", ret); + return; + } start = current_time(1); - for(i = 0; i < numBlocks; i++) - Sha512Update(&hash, plain, sizeof(plain)); - - Sha512Final(&hash, digest); + for(i = 0; i < numBlocks; i++) { + ret = Sha512Update(&hash, plain, sizeof(plain)); + if (ret != 0) { + printf("Sha512Update failed, ret = %d\n", ret); + return; + } + } + + ret = Sha512Final(&hash, digest); + if (ret != 0) { + printf("Sha512Final failed, ret = %d\n", ret); + return; + } total = current_time(0) - start; persec = 1 / total * numBlocks; @@ -605,7 +694,7 @@ void bench_sha512(void) persec = persec / 1024; #endif - printf("SHA-512 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("SHA-512 %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -633,7 +722,7 @@ void bench_ripemd(void) persec = persec / 1024; #endif - printf("RIPEMD %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("RIPEMD %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -645,15 +734,28 @@ void bench_blake2(void) Blake2b b2b; byte digest[64]; double start, total, persec; - int i; + int i, ret; - InitBlake2b(&b2b, 64); + ret = InitBlake2b(&b2b, 64); + if (ret != 0) { + printf("InitBlake2b failed, ret = %d\n", ret); + return; + } start = current_time(1); - for(i = 0; i < numBlocks; i++) - Blake2bUpdate(&b2b, plain, sizeof(plain)); + for(i = 0; i < numBlocks; i++) { + ret = Blake2bUpdate(&b2b, plain, sizeof(plain)); + if (ret != 0) { + printf("Blake2bUpdate failed, ret = %d\n", ret); + return; + } + } - Blake2bFinal(&b2b, digest, 64); + ret = Blake2bFinal(&b2b, digest, 64); + if (ret != 0) { + printf("Blake2bFinal failed, ret = %d\n", ret); + return; + } total = current_time(0) - start; persec = 1 / total * numBlocks; @@ -662,7 +764,7 @@ void bench_blake2(void) persec = persec / 1024; #endif - printf("BLAKE2b %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + printf("BLAKE2b %d %s took %5.3f seconds, %7.3f MB/s\n", numBlocks, blockType, total, persec); } #endif @@ -670,7 +772,7 @@ void bench_blake2(void) #if !defined(NO_RSA) || !defined(NO_DH) \ || defined(CYASSL_KEYGEN) || defined(HAVE_ECC) -RNG rng; +static RNG rng; #endif #ifndef NO_RSA @@ -679,7 +781,7 @@ RNG rng; #if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && \ defined(CYASSL_MDK_SHELL) static char *certRSAname = "certs/rsa2048.der" ; -void set_Bench_RSA_File(char * cert) { certRSAname = cert ; } +static void set_Bench_RSA_File(char * cert) { certRSAname = cert ; } /* set by shell command */ #elif defined(CYASSL_MDK_SHELL) /* nothing */ @@ -722,7 +824,7 @@ void bench_rsa(void) fclose(file); #endif /* USE_CERT_BUFFERS */ - + #ifdef HAVE_CAVIUM if (RsaInitCavium(&rsaKey, CAVIUM_DEV_ID) != 0) printf("RSA init cavium failed\n"); @@ -732,20 +834,24 @@ void bench_rsa(void) printf("InitRNG failed\n"); return; } - InitRsaKey(&rsaKey, 0); + ret = InitRsaKey(&rsaKey, 0); + if (ret < 0) { + printf("InitRsaKey failed\n"); + return; + } ret = RsaPrivateKeyDecode(tmp, &idx, &rsaKey, (word32)bytes); start = current_time(1); - for (i = 0; i < times; i++) + for (i = 0; i < ntimes; i++) ret = RsaPublicEncrypt(message,len,enc,sizeof(enc), &rsaKey, &rng); total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("RSA %d encryption took %6.2f milliseconds, avg over %d" - " iterations\n", rsaKeySz, milliEach, times); + printf("RSA %d encryption took %6.3f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, ntimes); if (ret < 0) { printf("Rsa Public Encrypt failed\n"); @@ -754,17 +860,17 @@ void bench_rsa(void) start = current_time(1); - for (i = 0; i < times; i++) { + for (i = 0; i < ntimes; i++) { byte out[512]; /* for up to 4096 bit */ RsaPrivateDecrypt(enc, (word32)ret, out, sizeof(out), &rsaKey); } total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("RSA %d decryption took %6.2f milliseconds, avg over %d" - " iterations\n", rsaKeySz, milliEach, times); + printf("RSA %d decryption took %6.3f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, ntimes); FreeRsaKey(&rsaKey); #ifdef HAVE_CAVIUM @@ -790,10 +896,10 @@ static const char *certDHname = "certs/dh2048.der" ; void bench_dh(void) { - int i; + int i, ret; byte tmp[1024]; size_t bytes; - word32 idx = 0, pubSz, privSz, pubSz2, privSz2, agreeSz; + word32 idx = 0, pubSz, privSz = 0, pubSz2, privSz2, agreeSz; byte pub[256]; /* for 2048 bit */ byte priv[256]; /* for 2048 bit */ @@ -805,7 +911,7 @@ void bench_dh(void) DhKey dhKey; int dhKeySz = 2048; /* used in printf */ - + #ifdef USE_CERT_BUFFERS_1024 XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024); bytes = sizeof_dh_key_der_1024; @@ -821,10 +927,15 @@ void bench_dh(void) return; } + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } bytes = fread(tmp, 1, sizeof(tmp), file); #endif /* USE_CERT_BUFFERS */ - + InitDhKey(&dhKey); bytes = DhKeyDecode(tmp, &idx, &dhKey, (word32)bytes); if (bytes != 0) { @@ -837,28 +948,28 @@ void bench_dh(void) start = current_time(1); - for (i = 0; i < times; i++) + for (i = 0; i < ntimes; i++) DhGenerateKeyPair(&dhKey, &rng, priv, &privSz, pub, &pubSz); total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("DH %d key generation %6.2f milliseconds, avg over %d" - " iterations\n", dhKeySz, milliEach, times); + printf("DH %d key generation %6.3f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, ntimes); DhGenerateKeyPair(&dhKey, &rng, priv2, &privSz2, pub2, &pubSz2); start = current_time(1); - for (i = 0; i < times; i++) + for (i = 0; i < ntimes; i++) DhAgree(&dhKey, agree, &agreeSz, priv, privSz, pub2, pubSz2); total = current_time(0) - start; - each = total / times; /* per second */ + each = total / ntimes; /* per second */ milliEach = each * 1000; /* milliseconds */ - printf("DH %d key agreement %6.2f milliseconds, avg over %d" - " iterations\n", dhKeySz, milliEach, times); + printf("DH %d key agreement %6.3f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, ntimes); #if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) fclose(file); @@ -873,7 +984,6 @@ void bench_rsaKeyGen(void) RsaKey genKey; double start, total, each, milliEach; int i; - const int genTimes = 5; /* 1024 bit */ start = current_time(1); @@ -888,7 +998,7 @@ void bench_rsaKeyGen(void) each = total / genTimes; /* per second */ milliEach = each * 1000; /* millisconds */ printf("\n"); - printf("RSA 1024 key generation %6.2f milliseconds, avg over %d" + printf("RSA 1024 key generation %6.3f milliseconds, avg over %d" " iterations\n", milliEach, genTimes); /* 2048 bit */ @@ -903,7 +1013,7 @@ void bench_rsaKeyGen(void) total = current_time(0) - start; each = total / genTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("RSA 2048 key generation %6.2f milliseconds, avg over %d" + printf("RSA 2048 key generation %6.3f milliseconds, avg over %d" " iterations\n", milliEach, genTimes); } #endif /* CYASSL_KEY_GEN */ @@ -913,9 +1023,13 @@ void bench_eccKeyGen(void) { ecc_key genKey; double start, total, each, milliEach; - int i; - const int genTimes = 5; + int i, ret; + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } /* 256 bit */ start = current_time(1); @@ -928,7 +1042,7 @@ void bench_eccKeyGen(void) each = total / genTimes; /* per second */ milliEach = each * 1000; /* millisconds */ printf("\n"); - printf("ECC 256 key generation %6.2f milliseconds, avg over %d" + printf("ECC 256 key generation %6.3f milliseconds, avg over %d" " iterations\n", milliEach, genTimes); } @@ -938,15 +1052,20 @@ void bench_eccKeyAgree(void) ecc_key genKey, genKey2; double start, total, each, milliEach; int i, ret; - const int agreeTimes = 5; byte shared[1024]; byte sig[1024]; byte digest[32]; - word32 x; + word32 x = 0; ecc_init(&genKey); ecc_init(&genKey2); + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } + ret = ecc_make_key(&rng, 32, &genKey); if (ret != 0) { printf("ecc_make_key failed\n"); @@ -963,31 +1082,56 @@ void bench_eccKeyAgree(void) for(i = 0; i < agreeTimes; i++) { x = sizeof(shared); - ecc_shared_secret(&genKey, &genKey2, shared, &x); + ret = ecc_shared_secret(&genKey, &genKey2, shared, &x); + if (ret != 0) { + printf("ecc_shared_secret failed\n"); + return; + } } total = current_time(0) - start; each = total / agreeTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("EC-DHE key agreement %6.2f milliseconds, avg over %d" + printf("EC-DHE key agreement %6.3f milliseconds, avg over %d" " iterations\n", milliEach, agreeTimes); /* make dummy digest */ for (i = 0; i < (int)sizeof(digest); i++) - digest[i] = i; + digest[i] = (byte)i; start = current_time(1); for(i = 0; i < agreeTimes; i++) { x = sizeof(sig); - ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &genKey); + ret = ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &genKey); + if (ret != 0) { + printf("ecc_sign_hash failed\n"); + return; + } } total = current_time(0) - start; each = total / agreeTimes; /* per second */ milliEach = each * 1000; /* millisconds */ - printf("EC-DSA sign time %6.2f milliseconds, avg over %d" + printf("EC-DSA sign time %6.3f milliseconds, avg over %d" + " iterations\n", milliEach, agreeTimes); + + start = current_time(1); + + for(i = 0; i < agreeTimes; i++) { + int verify = 0; + ret = ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &genKey); + if (ret != 0) { + printf("ecc_verify_hash failed\n"); + return; + } + } + + total = current_time(0) - start; + each = total / agreeTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("EC-DSA verify time %6.3f milliseconds, avg over %d" " iterations\n", milliEach, agreeTimes); ecc_free(&genKey2); @@ -1003,13 +1147,13 @@ void bench_eccKeyAgree(void) double current_time(int reset) { - (void)reset; - static int init = 0; static LARGE_INTEGER freq; LARGE_INTEGER count; + (void)reset; + if (!init) { QueryPerformanceFrequency(&freq); init = 1; @@ -1021,44 +1165,58 @@ void bench_eccKeyAgree(void) } #elif defined MICROCHIP_PIC32 - - #include + #if defined(CYASSL_MICROCHIP_PIC32MZ) + #define CLOCK 8000000.0 + #else + #include + #define CLOCK 4000000.0 + #endif double current_time(int reset) { - /* NOTE: core timer tick rate = 40 Mhz, 1 tick = 25 ns */ - unsigned int ns; - /* should we reset our timer back to zero? Helps prevent timer - rollover */ - if (reset) { WriteCoreTimer(0); } /* get timer in ns */ - ns = ReadCoreTimer() * 25; + ns = ReadCoreTimer(); /* return seconds as a double */ - return ( ns / 1000000000.0 ); + return ( ns / CLOCK * 2.0); } - + #elif defined CYASSL_MDK_ARM + extern double current_time(int reset) ; + +#elif defined FREERTOS + + double current_time(int reset) + { + (void) reset; + + portTickType tickCount; + + /* tick count == ms, if configTICK_RATE_HZ is set to 1000 */ + tickCount = xTaskGetTickCount(); + return (double)tickCount / 1000; + } + #else #include double current_time(int reset) { - (void) reset; - struct timeval tv; + + (void)reset; + gettimeofday(&tv, 0); return (double)tv.tv_sec + (double)tv.tv_usec / 1000000; } #endif /* _WIN32 */ - diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c index e446583e7c..4744f9b723 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c @@ -46,17 +46,9 @@ #endif #include - -#ifdef CYASSL_MDK_SHELL -extern void exit_command(void) ; -#define exit(code) exit_command() -#endif - #include - #include "examples/client/client.h" -#define USE_CYASSL_MEMORY #ifdef CYASSL_CALLBACKS int handShakeCB(HandShakeInfo*); @@ -145,10 +137,33 @@ static void Usage(void) #ifdef SHOW_SIZES printf("-z Print structure sizes\n"); #endif +#ifdef HAVE_SNI printf("-S Use Host Name Indication\n"); +#endif +#ifdef HAVE_MAX_FRAGMENT + printf("-L Use Maximum Fragment Length [1-5]\n"); +#endif +#ifdef HAVE_TRUNCATED_HMAC + printf("-T Use Truncated HMAC\n"); +#endif +#ifdef HAVE_OCSP + printf("-o Perform OCSP lookup on peer certificate\n"); + printf("-O Perform OCSP lookup using as responder\n"); +#endif +#ifdef ATOMIC_USER + printf("-U Atomic User Record Layer Callbacks\n"); +#endif +#ifdef HAVE_PK_CALLBACKS + printf("-P Public Key Callbacks\n"); +#endif } +#ifdef CYASSL_MDK_SHELL + #define exit(code) return(code) +#endif + + THREAD_RETURN CYASSL_THREAD client_test(void* args) { SOCKET_T sockfd = 0; @@ -167,7 +182,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) int input; int msgSz = (int)strlen(msg); - int port = yasslPort; + word16 port = yasslPort; char* host = (char*)yasslIP; char* domain = (char*)"www.yassl.com"; @@ -184,6 +199,8 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) int trackMemory = 0; int useClientCert = 1; int fewerPackets = 0; + int atomicUser = 0; + int pkCallbacks = 0; char* cipherList = NULL; char* verifyCert = (char*)caCert; char* ourCert = (char*)cliCert; @@ -192,6 +209,18 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) #ifdef HAVE_SNI char* sniHostName = NULL; #endif +#ifdef HAVE_MAX_FRAGMENT + byte maxFragment = 0; +#endif +#ifdef HAVE_TRUNCATED_HMAC + byte truncatedHMAC = 0; +#endif + + +#ifdef HAVE_OCSP + int useOcsp = 0; + char* ocspUrl = NULL; +#endif int argc = ((func_args*)args)->argc; char** argv = ((func_args*)args)->argv; @@ -207,8 +236,13 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) (void)session; (void)sslResume; (void)trackMemory; + (void)atomicUser; + (void)pkCallbacks; - while ((ch = mygetopt(argc, argv, "?gdusmNrtfxh:p:v:l:A:c:k:b:zS:")) != -1){ + StackTrap(); + + while ((ch = mygetopt(argc, argv, + "?gdusmNrtfxUPh:p:v:l:A:c:k:b:zS:L:ToO:")) != -1) { switch (ch) { case '?' : Usage(); @@ -248,13 +282,25 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) fewerPackets = 1; break; + case 'U' : + #ifdef ATOMIC_USER + atomicUser = 1; + #endif + break; + + case 'P' : + #ifdef HAVE_PK_CALLBACKS + pkCallbacks = 1; + #endif + break; + case 'h' : host = myoptarg; domain = myoptarg; break; case 'p' : - port = atoi(myoptarg); + port = (word16)atoi(myoptarg); #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API) if (port == 0) err_sys("port number cannot be 0"); @@ -313,6 +359,36 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) #endif break; + case 'L' : + #ifdef HAVE_MAX_FRAGMENT + maxFragment = atoi(myoptarg); + if (maxFragment < CYASSL_MFL_2_9 || + maxFragment > CYASSL_MFL_2_13) { + Usage(); + exit(MY_EX_USAGE); + } + #endif + break; + + case 'T' : + #ifdef HAVE_TRUNCATED_HMAC + truncatedHMAC = 1; + #endif + break; + + case 'o' : + #ifdef HAVE_OCSP + useOcsp = 1; + #endif + break; + + case 'O' : + #ifdef HAVE_OCSP + useOcsp = 1; + ocspUrl = myoptarg; + #endif + break; + default: Usage(); exit(MY_EX_USAGE); @@ -388,7 +464,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) ctx = CyaSSL_CTX_new(method); if (ctx == NULL) err_sys("unable to get ctx"); - + if (cipherList) if (CyaSSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS) err_sys("client can't set cipher list 1"); @@ -421,7 +497,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) useClientCert = 0; } -#ifdef OPENSSL_EXTRA +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); #endif @@ -434,6 +510,18 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) } #endif +#ifdef HAVE_OCSP + if (useOcsp) { + if (ocspUrl != NULL) { + CyaSSL_CTX_SetOCSP_OverrideURL(ctx, ocspUrl); + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE + | CYASSL_OCSP_URL_OVERRIDE); + } + else + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE); + } +#endif + #ifdef USER_CA_CB CyaSSL_CTX_SetCACb(ctx, CaCb); #endif @@ -473,6 +561,16 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) != SSL_SUCCESS) err_sys("UseSNI failed"); #endif +#ifdef HAVE_MAX_FRAGMENT + if (maxFragment) + if (CyaSSL_CTX_UseMaxFragment(ctx, maxFragment) != SSL_SUCCESS) + err_sys("UseMaxFragment failed"); +#endif +#ifdef HAVE_TRUNCATED_HMAC + if (truncatedHMAC) + if (CyaSSL_CTX_UseTruncatedHMAC(ctx) != SSL_SUCCESS) + err_sys("UseTruncatedHMAC failed"); +#endif if (benchmark) { /* time passed in number of connects give average */ @@ -511,9 +609,6 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) ssl = CyaSSL_new(ctx); if (ssl == NULL) err_sys("unable to get SSL object"); - - CyaSSL_set_quiet_shutdown(ssl, 1) ; - if (doDTLS) { SOCKADDR_IN_T addr; build_addr(&addr, host, port, 1); @@ -531,6 +626,14 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) err_sys("can't load crl, check crlfile and date validity"); if (CyaSSL_SetCRL_Cb(ssl, CRL_CallBack) != SSL_SUCCESS) err_sys("can't set crl callback"); +#endif +#ifdef ATOMIC_USER + if (atomicUser) + SetupAtomicUser(ctx, ssl); +#endif +#ifdef HAVE_PK_CALLBACKS + if (pkCallbacks) + SetupPkCallbacks(ctx, ssl); #endif if (matchName && doPeerCheck) CyaSSL_check_domain_name(ssl, domain); @@ -543,7 +646,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) else if (CyaSSL_connect(ssl) != SSL_SUCCESS) { /* see note at top of README */ int err = CyaSSL_get_error(ssl, 0); - char buffer[80]; + char buffer[CYASSL_MAX_ERROR_SZ]; printf("err = %d, %s\n", err, CyaSSL_ERR_error_string(err, buffer)); err_sys("SSL_connect failed"); @@ -559,7 +662,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) if (sendGET) { printf("SSL connect ok, sending GET...\n"); msgSz = 28; - strncpy(msg, "GET / HTTP/1.0\r\n\r\n", msgSz); + strncpy(msg, "GET /index.html HTTP/1.0\r\n\r\n", msgSz); msg[msgSz] = '\0'; } if (CyaSSL_write(ssl, msg, msgSz) != msgSz) @@ -568,32 +671,25 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) input = CyaSSL_read(ssl, reply, sizeof(reply)-1); if (input > 0) { reply[input] = 0; - printf("Server response: %s", reply); + printf("Server response: %s\n", reply); - if (sendGET && (input == (sizeof(reply)-1))) { /* get html */ + if (sendGET) { /* get html */ while (1) { input = CyaSSL_read(ssl, reply, sizeof(reply)-1); if (input > 0) { reply[input] = 0; - printf("%s", reply); - if(input < sizeof(reply)-1) - break ; + printf("%s\n", reply); } else break; } } - printf("\n"); } else if (input < 0) { int readErr = CyaSSL_get_error(ssl, 0); if (readErr != SSL_ERROR_WANT_READ) err_sys("CyaSSL_read failed"); } - -#ifdef CYASSL_CMSIS_RTOS - osDelay(5000) ; -#endif #ifndef NO_SESSION_CACHE if (resumeSession) { @@ -610,6 +706,10 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) if (doDTLS == 0) /* don't send alert after "break" command */ CyaSSL_shutdown(ssl); /* echoserver will interpret as new conn */ +#ifdef ATOMIC_USER + if (atomicUser) + FreeAtomicUser(ssl); +#endif CyaSSL_free(ssl); CloseSocket(sockfd); @@ -711,11 +811,13 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) args.argv = argv; CyaSSL_Init(); -#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) +#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) && !defined(STACK_TRAP) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("client") || CurrentDir("build")) + if (CurrentDir("client")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); #ifdef HAVE_STACK_SIZE StackSizeCheck(&args, client_test); diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c index 3793d6dd1c..24a02febc1 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c @@ -28,18 +28,18 @@ #include #if defined(CYASSL_MDK_ARM) - #include - #include - - #if defined(CYASSL_MDK5) - #include "cmsis_os.h" - #include "rl_fs.h" - #include "rl_net.h" - #else - #include "rtl.h" - #endif - - #include "cyassl_MDK_ARM.h" + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" #endif #include @@ -68,11 +68,11 @@ void echoclient_test(void* args) int sendSz; int argc = 0; char** argv = 0; - int port = yasslPort; + word16 port = yasslPort; ((func_args*)args)->return_code = -1; /* error state */ -#ifndef CYASSL_MDK_ARM +#ifndef CYASSL_MDK_SHELL argc = ((func_args*)args)->argc; argv = ((func_args*)args)->argv; #endif @@ -104,9 +104,6 @@ void echoclient_test(void* args) #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && !defined(CYASSL_MDK_SHELL) port = ((func_args*)args)->signal->port; #endif -#if defined (CYASSL_CALLEE_PORT) - port = CYASSL_CALLEE_PORT ; -#endif #if defined(CYASSL_DTLS) method = DTLSv1_client_method(); @@ -150,7 +147,7 @@ void echoclient_test(void* args) #endif } -#ifdef OPENSSL_EXTRA +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); #endif @@ -159,8 +156,8 @@ void echoclient_test(void* args) #endif ssl = SSL_new(ctx); - CyaSSL_set_quiet_shutdown(ssl, 1) ; - + + if (doDTLS) { SOCKADDR_IN_T addr; build_addr(&addr, yasslIP, port, 1); @@ -221,10 +218,6 @@ void echoclient_test(void* args) #endif } -#ifdef CYASSL_CMSIS_RTOS - osDelay(5000) ; -#endif - #ifdef CYASSL_DTLS strncpy(msg, "break", 6); @@ -270,8 +263,10 @@ void echoclient_test(void* args) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("echoclient") || CurrentDir("build")) + if (CurrentDir("echoclient")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); echoclient_test(&args); CyaSSL_Cleanup(); diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c index 132e4c6d7a..33f6df3df0 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c @@ -26,18 +26,18 @@ #include #if defined(CYASSL_MDK_ARM) - #include - #include + #include + #include - #if defined(CYASSL_MDK5) - #include "cmsis_os.h" - #include "rl_fs.h" - #include "rl_net.h" - #else - #include "rtl.h" - #endif + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif - #include "cyassl_MDK_ARM.h" + #include "cyassl_MDK_ARM.h" #endif #include @@ -56,7 +56,7 @@ #define SVR_COMMAND_SIZE 256 -static void SignalReady(void* args, int port) +static void SignalReady(void* args, word16 port) { #if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__) /* signal ready to tcp_accept */ @@ -84,7 +84,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) int outCreated = 0; int shutDown = 0; int useAnyAddr = 0; - int port = yasslPort; + word16 port = yasslPort; int argc = ((func_args*)args)->argc; char** argv = ((func_args*)args)->argv; @@ -115,7 +115,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) #endif #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \ - !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_ARM) + !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_SHELL) port = 0; #endif #if defined(USE_ANY_ADDR) @@ -133,7 +133,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) ctx = CyaSSL_CTX_new(method); /* CyaSSL_CTX_set_session_cache_mode(ctx, SSL_SESS_CACHE_OFF); */ -#ifdef OPENSSL_EXTRA +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); #endif @@ -226,8 +226,6 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) ssl = CyaSSL_new(ctx); if (ssl == NULL) err_sys("SSL_new failed"); - CyaSSL_set_quiet_shutdown(ssl, 1) ; - CyaSSL_set_fd(ssl, clientfd); #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA) CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM); @@ -313,9 +311,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) SignalReady(args, port); #endif } -#ifdef CYASSL_CMSIS_RTOS - osDelay(5000) ; -#endif + CloseSocket(sockfd); CyaSSL_CTX_free(ctx); @@ -351,8 +347,10 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) #if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("echoserver") || CurrentDir("build")) + if (CurrentDir("echoserver")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); echoserver_test(&args); CyaSSL_Cleanup(); diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c index f1b849135c..dc7941f725 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c @@ -27,7 +27,9 @@ #include #include "cmsis_os.h" +#if !defined(NO_FILESYSTEM) #include "rl_fs.h" +#endif #include "rl_net.h" #include #include "cyassl_MDK_ARM.h" @@ -36,6 +38,7 @@ /*----------------------------------------------------------------------------- * Initialize a Flash Memory Card *----------------------------------------------------------------------------*/ +#if !defined(NO_FILESYSTEM) static void init_filesystem (void) { int32_t retv; @@ -53,6 +56,7 @@ static void init_filesystem (void) { printf ("Drive M0 initialization failed!\n"); } } +#endif /*----------------------------------------------------------------------------- * TCP/IP tasks @@ -79,9 +83,13 @@ char* myoptarg = NULL; int main() { void *arg = NULL ; - init_time() ; + + #if !defined(NO_FILESYSTEM) init_filesystem (); + #endif + net_initialize() ; + osThreadCreate (osThread (tcp_poll), NULL); osDelay(10000) ; /* wait for DHCP */ #if defined(DEBUG_CYASSL) diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c index 28b6e8c949..440dd1d035 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c @@ -31,27 +31,20 @@ #endif #if defined(CYASSL_MDK_ARM) - #include - #include - - #if defined(CYASSL_MDK5) - #include "cmsis_os.h" - #include "rl_fs.h" - #include "rl_net.h" - #else - #include "rtl.h" - #endif - - #include "cyassl_MDK_ARM.h" -#endif + #include + #include + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif #include - -#ifdef CYASSL_MDK_SHELL -extern void exit_command(void) ; -#define exit(code) exit_command() -#endif - #include #include "examples/server/server.h" @@ -137,6 +130,13 @@ static void Usage(void) printf("-f Fewer packets/group messages\n"); printf("-N Use Non-blocking sockets\n"); printf("-S Use Host Name Indication\n"); +#ifdef HAVE_OCSP + printf("-o Perform OCSP lookup on peer certificate\n"); + printf("-O Perform OCSP lookup using as responder\n"); +#endif +#ifdef HAVE_PK_CALLBACKS + printf("-P Public Key Callbacks\n"); +#endif } THREAD_RETURN CYASSL_THREAD server_test(void* args) @@ -153,15 +153,16 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) int idx; int ch; int version = SERVER_DEFAULT_VERSION; - int doCliCertCheck = 1; + int doCliCertCheck = 0; /* = 0 for no Realtime Clock environment */ int useAnyAddr = 0; - int port = yasslPort; + word16 port = yasslPort; int usePsk = 0; int doDTLS = 0; int useNtruKey = 0; int nonBlocking = 0; int trackMemory = 0; int fewerPackets = 0; + int pkCallbacks = 0; char* cipherList = NULL; char* verifyCert = (char*)cliCert; char* ourCert = (char*)svrCert; @@ -173,6 +174,11 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) char* sniHostName = NULL; #endif +#ifdef HAVE_OCSP + int useOcsp = 0; + char* ocspUrl = NULL; +#endif + ((func_args*)args)->return_code = -1; /* error state */ #ifdef NO_RSA @@ -181,8 +187,9 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) ourKey = (char*)eccKey; #endif (void)trackMemory; + (void)pkCallbacks; - while ((ch = mygetopt(argc, argv, "?dbstnNufp:v:l:A:c:k:S:")) != -1) { + while ((ch = mygetopt(argc, argv, "?dbstnNufPp:v:l:A:c:k:S:oO:")) != -1) { switch (ch) { case '?' : Usage(); @@ -218,8 +225,14 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) fewerPackets = 1; break; + case 'P' : + #ifdef HAVE_PK_CALLBACKS + pkCallbacks = 1; + #endif + break; + case 'p' : - port = atoi(myoptarg); + port = (word16)atoi(myoptarg); #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API) if (port == 0) err_sys("port number cannot be 0"); @@ -260,6 +273,19 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) #endif break; + case 'o' : + #ifdef HAVE_OCSP + useOcsp = 1; + #endif + break; + + case 'O' : + #ifdef HAVE_OCSP + useOcsp = 1; + ocspUrl = myoptarg; + #endif + break; + default: Usage(); exit(MY_EX_USAGE); @@ -347,13 +373,13 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) usePsk = 1; #endif -#ifdef OPENSSL_EXTRA - SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); -#endif - if (fewerPackets) CyaSSL_CTX_set_group_messages(ctx); +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) + SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + #if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) if (!usePsk) { if (SSL_CTX_use_certificate_file(ctx, ourCert, SSL_FILETYPE_PEM) @@ -376,8 +402,8 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) if (!useNtruKey && !usePsk) { if (SSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM) != SSL_SUCCESS) - err_sys("can't load server cert file, check file and run from" - " CyaSSL home dir"); + err_sys("can't load server private key file, check file and run " + "from CyaSSL home dir"); } #endif @@ -417,27 +443,38 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) #endif #ifdef HAVE_SNI - if (sniHostName) { + if (sniHostName) if (CyaSSL_CTX_UseSNI(ctx, CYASSL_SNI_HOST_NAME, sniHostName, XSTRLEN(sniHostName)) != SSL_SUCCESS) err_sys("UseSNI failed"); - else - CyaSSL_CTX_SNI_SetOptions(ctx, CYASSL_SNI_HOST_NAME, - CYASSL_SNI_ABORT_ON_MISMATCH); - } #endif ssl = SSL_new(ctx); if (ssl == NULL) err_sys("unable to get SSL"); - CyaSSL_set_quiet_shutdown(ssl, 1) ; + #ifdef HAVE_CRL CyaSSL_EnableCRL(ssl, 0); CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, CYASSL_CRL_MONITOR | CYASSL_CRL_START_MON); CyaSSL_SetCRL_Cb(ssl, CRL_CallBack); #endif - osDelay(5000) ; +#ifdef HAVE_OCSP + if (useOcsp) { + if (ocspUrl != NULL) { + CyaSSL_CTX_SetOCSP_OverrideURL(ctx, ocspUrl); + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE + | CYASSL_OCSP_URL_OVERRIDE); + } + else + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE); + } +#endif +#ifdef HAVE_PK_CALLBACKS + if (pkCallbacks) + SetupPkCallbacks(ctx, ssl); +#endif + tcp_accept(&sockfd, &clientfd, (func_args*)args, port, useAnyAddr, doDTLS); if (!doDTLS) CloseSocket(sockfd); @@ -450,7 +487,7 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) SetDH(ssl); /* repick suites with DHE, higher priority than PSK */ #endif } - osDelay(5000) ; + #ifndef CYASSL_CALLBACKS if (nonBlocking) { CyaSSL_set_using_nonblock(ssl, 1); @@ -458,7 +495,7 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) NonBlockingSSL_Accept(ssl); } else if (SSL_accept(ssl) != SSL_SUCCESS) { int err = SSL_get_error(ssl, 0); - char buffer[80]; + char buffer[CYASSL_MAX_ERROR_SZ]; printf("error = %d, %s\n", err, ERR_error_string(err, buffer)); err_sys("SSL_accept failed"); } @@ -466,7 +503,7 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) NonBlockingSSL_Accept(ssl); #endif showPeer(ssl); - osDelay(5000) ; + idx = SSL_read(ssl, input, sizeof(input)-1); if (idx > 0) { input[idx] = 0; @@ -482,6 +519,10 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) if (SSL_write(ssl, msg, sizeof(msg)) != sizeof(msg)) err_sys("SSL_write failed"); + #if defined(CYASSL_MDK_SHELL) && defined(HAVE_MDK_RTX) + os_dly_wait(500) ; + #endif + SSL_shutdown(ssl); SSL_free(ssl); SSL_CTX_free(ctx); @@ -520,8 +561,10 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) #if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("server") || CurrentDir("build")) + if (CurrentDir("server")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); #ifdef HAVE_STACK_SIZE StackSizeCheck(&args, server_test); diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c index ff24d7edf1..1ada297cf4 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c @@ -96,7 +96,6 @@ extern void ctaocrypt_test(void *args) ; extern void client_test(void *args) ; extern void server_test(void *args) ; extern void kill_task(void *args) ; -extern void time_main(void *args) ; extern void ipaddr_comm(void *args) ; extern void stack_comm(void *args) ; extern void for_command(void *args) ; @@ -214,7 +213,6 @@ static struct { "test", ctaocrypt_test, "client", client_test, "server", server_test, - "time", time_main, /* get/set RTC: [-d mm/dd/yyyy] [-t hh:mm:ss]*/ "ipaddr", ipaddr_comm, /* TBD */ "stack", stack_comm, /* On/Off check stack size */ "for", for_command, /* iterate next command X times */ @@ -470,7 +468,6 @@ static void dbg_comm(void *args) static void help_comm(void *args) { static char *commands[] = { - "time [-d mm/dd/yyyy][-t hh:mm:ss] : set/get time, for cert validation", "test", "benchmark", "echoserver& : simple echo server in background mode", @@ -604,7 +601,6 @@ void shell_main(void *arg) { #if defined(HAVE_KEIL_RTX) InitMutex(&command_mutex) ; #endif - time_main(NULL) ; help_comm(NULL) ; printf("Starting Shell\n") ; @@ -617,14 +613,14 @@ void shell_main(void *arg) { #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS) UnLockMutex((CyaSSL_Mutex *)&command_mutex) ; os_tsk_create_user_ex( (void(*)(void *))&command_invoke, 7, - command_stack, COMMAND_STACK_SIZE, &args) ; - #else - #if defined(CYASSL_CMSIS_RTOS) - UnLockMutex((CyaSSL_Mutex *)&command_mutex) ; - osThreadCreate (osThread (command_invoke) , &args); - #else - command_invoke(&args) ; - #endif + command_stack, COMMAND_STACK_SIZE, &args) ; + #else + #if defined(CYASSL_CMSIS_RTOS) + UnLockMutex((CyaSSL_Mutex *)&command_mutex) ; + osThreadCreate (osThread (command_invoke) , &args); + #else + command_invoke(&args) ; + #endif #endif #ifdef HAVE_KEIL_RTX LockMutex((CyaSSL_Mutex *)&command_mutex) ; diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c index 9c0201a6fd..e19675bd9b 100644 --- a/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c @@ -25,6 +25,10 @@ #include +#ifdef XMALLOC_USER + #include /* we're using malloc / free direct here */ +#endif + #ifndef NO_CRYPT_TEST #ifdef CYASSL_TEST_CERT @@ -54,13 +58,16 @@ #include #ifdef HAVE_ECC #include -#endif +#endif #ifdef HAVE_BLAKE2 #include -#endif +#endif #ifdef HAVE_LIBZ #include #endif +#ifdef HAVE_PKCS7 + #include +#endif #ifdef _MSC_VER /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */ @@ -74,6 +81,18 @@ #include #endif + +#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) + /* include test cert and key buffers for use with NO_FILESYSTEM */ + #if defined(CYASSL_MDK_ARM) + #include "cert_data.h" + /* use certs_test.c for initial data, so other + commands can share the data. */ + #else + #include + #endif +#endif + #if defined(CYASSL_MDK_ARM) #include #include @@ -81,17 +100,6 @@ #define fopen CyaSSL_fopen #endif -#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) - /* include test cert and key buffers for use with NO_FILESYSTEM */ - #if defined(CYASSL_MDK_ARM) && !defined(SINGLE_THREADED) - #include "cert_data.h" - /* use certs_test.c for initial data, so other - commands can share the data. */ - #else - #include - #endif -#endif - #ifdef HAVE_NTRU #include "crypto_ntru.h" #endif @@ -104,6 +112,7 @@ #ifdef FREESCALE_MQX #include #include + #include #else #include #endif @@ -121,7 +130,7 @@ typedef struct testVector { const char* input; - const char* output; + const char* output; size_t inLen; size_t outLen; } testVector; @@ -138,6 +147,8 @@ int hmac_sha_test(void); int hmac_sha256_test(void); int hmac_sha384_test(void); int hmac_sha512_test(void); +int hmac_blake2b_test(void); +int hkdf_test(void); int arc4_test(void); int hc128_test(void); int rabbit_test(void); @@ -145,6 +156,7 @@ int des_test(void); int des3_test(void); int aes_test(void); int aesgcm_test(void); +int gmac_test(void); int aesccm_test(void); int camellia_test(void); int rsa_test(void); @@ -159,6 +171,9 @@ int pkcs12_test(void); int pbkdf2_test(void); #ifdef HAVE_ECC int ecc_test(void); + #ifdef HAVE_ECC_ENCRYPT + int ecc_encrypt_test(void); + #endif #endif #ifdef HAVE_BLAKE2 int blake2b_test(void); @@ -166,6 +181,10 @@ int pbkdf2_test(void); #ifdef HAVE_LIBZ int compress_test(void); #endif +#ifdef HAVE_PKCS7 + int pkcs7enveloped_test(void); + int pkcs7signed_test(void); +#endif @@ -173,7 +192,7 @@ static void err_sys(const char* msg, int es) { printf("%s error = %d\n", msg, es); #if !defined(THREADX) && !defined(CYASSL_MDK_ARM) - if (msg) + if (msg) exit(es); #endif return; @@ -206,63 +225,63 @@ void ctaocrypt_test(void* args) #ifndef NO_MD5 - if ( (ret = md5_test()) != 0) + if ( (ret = md5_test()) != 0) err_sys("MD5 test failed!\n", ret); else printf( "MD5 test passed!\n"); #endif #ifdef CYASSL_MD2 - if ( (ret = md2_test()) != 0) + if ( (ret = md2_test()) != 0) err_sys("MD2 test failed!\n", ret); else printf( "MD2 test passed!\n"); #endif #ifndef NO_MD4 - if ( (ret = md4_test()) != 0) + if ( (ret = md4_test()) != 0) err_sys("MD4 test failed!\n", ret); else printf( "MD4 test passed!\n"); #endif #ifndef NO_SHA - if ( (ret = sha_test()) != 0) + if ( (ret = sha_test()) != 0) err_sys("SHA test failed!\n", ret); else printf( "SHA test passed!\n"); #endif #ifndef NO_SHA256 - if ( (ret = sha256_test()) != 0) + if ( (ret = sha256_test()) != 0) err_sys("SHA-256 test failed!\n", ret); else printf( "SHA-256 test passed!\n"); #endif #ifdef CYASSL_SHA384 - if ( (ret = sha384_test()) != 0) + if ( (ret = sha384_test()) != 0) err_sys("SHA-384 test failed!\n", ret); else printf( "SHA-384 test passed!\n"); #endif #ifdef CYASSL_SHA512 - if ( (ret = sha512_test()) != 0) + if ( (ret = sha512_test()) != 0) err_sys("SHA-512 test failed!\n", ret); else printf( "SHA-512 test passed!\n"); #endif #ifdef CYASSL_RIPEMD - if ( (ret = ripemd_test()) != 0) + if ( (ret = ripemd_test()) != 0) err_sys("RIPEMD test failed!\n", ret); else printf( "RIPEMD test passed!\n"); #endif -#ifdef HAVE_BLAKE2 - if ( (ret = blake2b_test()) != 0) +#ifdef HAVE_BLAKE2 + if ( (ret = blake2b_test()) != 0) err_sys("BLAKE2b test failed!\n", ret); else printf( "BLAKE2b test passed!\n"); @@ -270,40 +289,61 @@ void ctaocrypt_test(void* args) #ifndef NO_HMAC #ifndef NO_MD5 - if ( (ret = hmac_md5_test()) != 0) + if ( (ret = hmac_md5_test()) != 0) err_sys("HMAC-MD5 test failed!\n", ret); else printf( "HMAC-MD5 test passed!\n"); #endif #ifndef NO_SHA - if ( (ret = hmac_sha_test()) != 0) + if ( (ret = hmac_sha_test()) != 0) err_sys("HMAC-SHA test failed!\n", ret); else printf( "HMAC-SHA test passed!\n"); #endif #ifndef NO_SHA256 - if ( (ret = hmac_sha256_test()) != 0) + if ( (ret = hmac_sha256_test()) != 0) err_sys("HMAC-SHA256 test failed!\n", ret); else printf( "HMAC-SHA256 test passed!\n"); #endif #ifdef CYASSL_SHA384 - if ( (ret = hmac_sha384_test()) != 0) + if ( (ret = hmac_sha384_test()) != 0) err_sys("HMAC-SHA384 test failed!\n", ret); else printf( "HMAC-SHA384 test passed!\n"); #endif #ifdef CYASSL_SHA512 - if ( (ret = hmac_sha512_test()) != 0) + if ( (ret = hmac_sha512_test()) != 0) err_sys("HMAC-SHA512 test failed!\n", ret); else printf( "HMAC-SHA512 test passed!\n"); #endif + #ifdef HAVE_BLAKE2 + if ( (ret = hmac_blake2b_test()) != 0) + err_sys("HMAC-BLAKE2 test failed!\n", ret); + else + printf( "HMAC-BLAKE2 test passed!\n"); + #endif + + #ifdef HAVE_HKDF + if ( (ret = hkdf_test()) != 0) + err_sys("HMAC-KDF test failed!\n", ret); + else + printf( "HMAC-KDF test passed!\n"); + #endif + +#endif + +#ifdef HAVE_AESGCM + if ( (ret = gmac_test()) != 0) + err_sys("GMAC test passed!\n", ret); + else + printf( "GMAC test passed!\n"); #endif #ifndef NO_RC4 @@ -313,7 +353,7 @@ void ctaocrypt_test(void* args) printf( "ARC4 test passed!\n"); #endif -#ifndef HAVE_HC128 +#ifndef NO_HC128 if ( (ret = hc128_test()) != 0) err_sys("HC-128 test failed!\n", ret); else @@ -375,54 +415,72 @@ void ctaocrypt_test(void* args) printf( "RANDOM test passed!\n"); #ifndef NO_RSA - if ( (ret = rsa_test()) != 0) + if ( (ret = rsa_test()) != 0) err_sys("RSA test failed!\n", ret); else printf( "RSA test passed!\n"); #endif #ifndef NO_DH - if ( (ret = dh_test()) != 0) + if ( (ret = dh_test()) != 0) err_sys("DH test failed!\n", ret); else printf( "DH test passed!\n"); #endif #ifndef NO_DSA - if ( (ret = dsa_test()) != 0) + if ( (ret = dsa_test()) != 0) err_sys("DSA test failed!\n", ret); else printf( "DSA test passed!\n"); #endif - + #ifndef NO_PWDBASED - if ( (ret = pwdbased_test()) != 0) + if ( (ret = pwdbased_test()) != 0) err_sys("PWDBASED test failed!\n", ret); else printf( "PWDBASED test passed!\n"); #endif - + #ifdef OPENSSL_EXTRA - if ( (ret = openssl_test()) != 0) + if ( (ret = openssl_test()) != 0) err_sys("OPENSSL test failed!\n", ret); else printf( "OPENSSL test passed!\n"); #endif #ifdef HAVE_ECC - if ( (ret = ecc_test()) != 0) + if ( (ret = ecc_test()) != 0) err_sys("ECC test failed!\n", ret); else printf( "ECC test passed!\n"); + #ifdef HAVE_ECC_ENCRYPT + if ( (ret = ecc_encrypt_test()) != 0) + err_sys("ECC Enc test failed!\n", ret); + else + printf( "ECC Enc test passed!\n"); + #endif #endif #ifdef HAVE_LIBZ - if ( (ret = compress_test()) != 0) + if ( (ret = compress_test()) != 0) err_sys("COMPRESS test failed!\n", ret); else printf( "COMPRESS test passed!\n"); #endif +#ifdef HAVE_PKCS7 + if ( (ret = pkcs7enveloped_test()) != 0) + err_sys("PKCS7enveloped test failed!\n", ret); + else + printf( "PKCS7enveloped test passed!\n"); + + if ( (ret = pkcs7signed_test()) != 0) + err_sys("PKCS7signed test failed!\n", ret); + else + printf( "PKCS7signed test passed!\n"); +#endif + ((func_args*)args)->return_code = ret; } @@ -459,7 +517,7 @@ static int OpenNitroxDevice(int dma_mode,int dev_id) func_args args; - + #ifdef HAVE_CAVIUM int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); if (ret != 0) @@ -474,7 +532,7 @@ static int OpenNitroxDevice(int dma_mode,int dev_id) #ifdef HAVE_CAVIUM CspShutdown(CAVIUM_DEV_ID); #endif - + return args.return_code; } @@ -555,7 +613,7 @@ int md2_test() return 0; } -#endif +#endif #ifndef NO_MD5 int md5_test(void) @@ -583,21 +641,21 @@ int md5_test(void) c.output = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00\x7d\xfb\x49\x6c\xca\x67\xe1" "\x3b"; c.inLen = strlen(c.input); - c.outLen = MD5_DIGEST_SIZE; + c.outLen = MD5_DIGEST_SIZE; d.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" "6789"; d.output = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5\xa5\x61\x1c\x2c\x9f\x41\x9d" "\x9f"; d.inLen = strlen(d.input); - d.outLen = MD5_DIGEST_SIZE; + d.outLen = MD5_DIGEST_SIZE; e.input = "1234567890123456789012345678901234567890123456789012345678" "9012345678901234567890"; e.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6" "\x7a"; e.inLen = strlen(e.input); - e.outLen = MD5_DIGEST_SIZE; + e.outLen = MD5_DIGEST_SIZE; test_md5[0] = a; test_md5[1] = b; @@ -632,45 +690,45 @@ int md4_test(void) int times = sizeof(test_md4) / sizeof(testVector), i; a.input = ""; - a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" + a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" "\xc0"; a.inLen = strlen(a.input); a.outLen = MD4_DIGEST_SIZE; b.input = "a"; - b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" + b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" "\x24"; b.inLen = strlen(b.input); - b.outLen = MD4_DIGEST_SIZE; + b.outLen = MD4_DIGEST_SIZE; c.input = "abc"; - c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" + c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" "\x9d"; c.inLen = strlen(c.input); c.outLen = MD4_DIGEST_SIZE; d.input = "message digest"; - d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" + d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" "\x4b"; d.inLen = strlen(d.input); d.outLen = MD4_DIGEST_SIZE; e.input = "abcdefghijklmnopqrstuvwxyz"; - e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" + e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" "\xa9"; e.inLen = strlen(e.input); e.outLen = MD4_DIGEST_SIZE; f.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" "6789"; - f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" + f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" "\xe4"; f.inLen = strlen(f.input); f.outLen = MD4_DIGEST_SIZE; g.input = "1234567890123456789012345678901234567890123456789012345678" "9012345678901234567890"; - g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" + g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" "\x36"; g.inLen = strlen(g.input); g.outLen = MD4_DIGEST_SIZE; @@ -707,6 +765,7 @@ int sha_test(void) testVector a, b, c, d; testVector test_sha[4]; + int ret; int times = sizeof(test_sha) / sizeof(struct testVector), i; a.input = "abc"; @@ -726,7 +785,7 @@ int sha_test(void) c.output = "\x00\x98\xBA\x82\x4B\x5C\x16\x42\x7B\xD7\xA1\x12\x2A\x5A\x44" "\x2A\x25\xEC\x64\x4D"; c.inLen = strlen(c.input); - c.outLen = SHA_DIGEST_SIZE; + c.outLen = SHA_DIGEST_SIZE; d.input = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" @@ -741,7 +800,9 @@ int sha_test(void) test_sha[2] = c; test_sha[3] = d; - InitSha(&sha); + ret = InitSha(&sha); + if (ret != 0) + return -4001; for (i = 0; i < times; ++i) { ShaUpdate(&sha, (byte*)test_sha[i].input, (word32)test_sha[i].inLen); @@ -778,7 +839,7 @@ int ripemd_test(void) b.inLen = strlen(b.input); b.outLen = RIPEMD_DIGEST_SIZE; - c.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; + c.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; c.output = "\x12\xa0\x53\x38\x4a\x9c\x0c\x88\xe4\x05\xa0\x6c\x27\xdc" "\xf4\x9a\xda\x62\xeb\x2b"; c.inLen = strlen(c.input); @@ -787,7 +848,7 @@ int ripemd_test(void) d.input = "12345678901234567890123456789012345678901234567890123456" "789012345678901234567890"; d.output = "\x9b\x75\x2e\x45\x57\x3d\x4b\x39\xf4\xdb\xd3\x32\x3c\xab" - "\x82\xbf\x63\x32\x6b\xfb"; + "\x82\xbf\x63\x32\x6b\xfb"; d.inLen = strlen(d.input); d.outLen = RIPEMD_DIGEST_SIZE; @@ -858,15 +919,23 @@ int blake2b_test(void) Blake2b b2b; byte digest[64]; byte input[64]; - int i; + int i, ret; for (i = 0; i < (int)sizeof(input); i++) input[i] = (byte)i; for (i = 0; i < BLAKE2_TESTS; i++) { - InitBlake2b(&b2b, 64); - Blake2bUpdate(&b2b, input, i); - Blake2bFinal(&b2b, digest, 64); + ret = InitBlake2b(&b2b, 64); + if (ret != 0) + return -4002; + + ret = Blake2bUpdate(&b2b, input, i); + if (ret != 0) + return -4003; + + ret = Blake2bFinal(&b2b, digest, 64); + if (ret != 0) + return -4004; if (memcmp(digest, blake2b_vec[i], 64) != 0) { return -300 - i; @@ -886,6 +955,7 @@ int sha256_test(void) testVector a, b; testVector test_sha[2]; + int ret; int times = sizeof(test_sha) / sizeof(struct testVector), i; a.input = "abc"; @@ -905,11 +975,17 @@ int sha256_test(void) test_sha[0] = a; test_sha[1] = b; - InitSha256(&sha); + ret = InitSha256(&sha); + if (ret != 0) + return -4005; for (i = 0; i < times; ++i) { - Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); - Sha256Final(&sha, hash); + ret = Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + if (ret != 0) + return -4006; + ret = Sha256Final(&sha, hash); + if (ret != 0) + return -4007; if (memcmp(hash, test_sha[i].output, SHA256_DIGEST_SIZE) != 0) return -10 - i; @@ -925,6 +1001,7 @@ int sha512_test(void) { Sha512 sha; byte hash[SHA512_DIGEST_SIZE]; + int ret; testVector a, b; testVector test_sha[2]; @@ -945,18 +1022,25 @@ int sha512_test(void) "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88" "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4" "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b" - "\x87\x4b\xe9\x09"; + "\x87\x4b\xe9\x09"; b.inLen = strlen(b.input); b.outLen = SHA512_DIGEST_SIZE; test_sha[0] = a; test_sha[1] = b; - InitSha512(&sha); + ret = InitSha512(&sha); + if (ret != 0) + return -4009; for (i = 0; i < times; ++i) { - Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); - Sha512Final(&sha, hash); + ret = Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + if (ret != 0) + return -4010; + + ret = Sha512Final(&sha, hash); + if (ret != 0) + return -4011; if (memcmp(hash, test_sha[i].output, SHA512_DIGEST_SIZE) != 0) return -10 - i; @@ -972,6 +1056,7 @@ int sha384_test(void) { Sha384 sha; byte hash[SHA384_DIGEST_SIZE]; + int ret; testVector a, b; testVector test_sha[2]; @@ -992,16 +1077,23 @@ int sha384_test(void) "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91" "\x74\x60\x39"; b.inLen = strlen(b.input); - b.outLen = SHA384_DIGEST_SIZE; + b.outLen = SHA384_DIGEST_SIZE; test_sha[0] = a; test_sha[1] = b; - InitSha384(&sha); + ret = InitSha384(&sha); + if (ret != 0) + return -4012; for (i = 0; i < times; ++i) { - Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); - Sha384Final(&sha, hash); + ret = Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + if (ret != 0) + return -4013; + + ret = Sha384Final(&sha, hash); + if (ret != 0) + return -4014; if (memcmp(hash, test_sha[i].output, SHA384_DIGEST_SIZE) != 0) return -10 - i; @@ -1028,6 +1120,7 @@ int hmac_md5_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1060,12 +1153,18 @@ int hmac_md5_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20009; + return -20009; #endif - HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i])); + if (ret != 0) + return -4015; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4016; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4017; if (memcmp(hash, test_hmac[i].output, MD5_DIGEST_SIZE) != 0) return -20 - i; @@ -1096,6 +1195,7 @@ int hmac_sha_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1128,12 +1228,18 @@ int hmac_sha_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20010; + return -20010; #endif - HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i])); + if (ret != 0) + return -4018; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4019; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4020; if (memcmp(hash, test_hmac[i].output, SHA_DIGEST_SIZE) != 0) return -20 - i; @@ -1165,6 +1271,7 @@ int hmac_sha256_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1200,12 +1307,18 @@ int hmac_sha256_test(void) if (i == 1) continue; /* driver can't handle keys <= bytes */ if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) - return -20011; + return -20011; #endif - HmacSetKey(&hmac, SHA256, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA256, (byte*)keys[i],(word32)strlen(keys[i])); + if (ret != 0) + return -4021; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4022; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4023; if (memcmp(hash, test_hmac[i].output, SHA256_DIGEST_SIZE) != 0) return -20 - i; @@ -1219,6 +1332,86 @@ int hmac_sha256_test(void) #endif +#if !defined(NO_HMAC) && defined(HAVE_BLAKE2) +int hmac_blake2b_test(void) +{ + Hmac hmac; + byte hash[BLAKE2B_256]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" + "\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + "\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int ret; + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\x72\x93\x0d\xdd\xf5\xf7\xe1\x78\x38\x07\x44\x18\x0b\x3f\x51" + "\x37\x25\xb5\x82\xc2\x08\x83\x2f\x1c\x99\xfd\x03\xa0\x16\x75" + "\xac\xfd"; + a.inLen = strlen(a.input); + a.outLen = BLAKE2B_256; + + b.input = "what do ya want for nothing?"; + b.output = "\x3d\x20\x50\x71\x05\xc0\x8c\x0c\x38\x44\x1e\xf7\xf9\xd1\x67" + "\x21\xff\x64\xf5\x94\x00\xcf\xf9\x75\x41\xda\x88\x61\x9d\x7c" + "\xda\x2b"; + b.inLen = strlen(b.input); + b.outLen = BLAKE2B_256; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\xda\xfe\x2a\x24\xfc\xe7\xea\x36\x34\xbe\x41\x92\xc7\x11\xa7" + "\x00\xae\x53\x9c\x11\x9c\x80\x74\x55\x22\x25\x4a\xb9\x55\xd3" + "\x0f\x87"; + c.inLen = strlen(c.input); + c.outLen = BLAKE2B_256; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { +#ifdef HAVE_CAVIUM + if (i == 1) + continue; /* driver can't handle keys <= bytes */ + if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) + return -20011; +#endif + ret = HmacSetKey(&hmac, BLAKE2B_ID, (byte*)keys[i], + (word32)strlen(keys[i])); + if (ret != 0) + return -4024; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + if (ret != 0) + return -4025; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4026; + + if (memcmp(hash, test_hmac[i].output, BLAKE2B_256) != 0) + return -20 - i; +#ifdef HAVE_CAVIUM + HmacFreeCavium(&hmac); +#endif + } + + return 0; +} +#endif + + #if !defined(NO_HMAC) && defined(CYASSL_SHA384) int hmac_sha384_test(void) { @@ -1237,6 +1430,7 @@ int hmac_sha384_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1271,10 +1465,16 @@ int hmac_sha384_test(void) test_hmac[2] = c; for (i = 0; i < times; ++i) { - HmacSetKey(&hmac, SHA384, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA384, (byte*)keys[i],(word32)strlen(keys[i])); + if (ret != 0) + return -4027; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4028; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4029; if (memcmp(hash, test_hmac[i].output, SHA384_DIGEST_SIZE) != 0) return -20 - i; @@ -1303,6 +1503,7 @@ int hmac_sha512_test(void) testVector a, b, c; testVector test_hmac[3]; + int ret; int times = sizeof(test_hmac) / sizeof(testVector), i; a.input = "Hi There"; @@ -1340,10 +1541,16 @@ int hmac_sha512_test(void) test_hmac[2] = c; for (i = 0; i < times; ++i) { - HmacSetKey(&hmac, SHA512, (byte*)keys[i], (word32)strlen(keys[i])); - HmacUpdate(&hmac, (byte*)test_hmac[i].input, + ret = HmacSetKey(&hmac, SHA512, (byte*)keys[i],(word32)strlen(keys[i])); + if (ret != 0) + return -4030; + ret = HmacUpdate(&hmac, (byte*)test_hmac[i].input, (word32)test_hmac[i].inLen); - HmacFinal(&hmac, hash); + if (ret != 0) + return -4031; + ret = HmacFinal(&hmac, hash); + if (ret != 0) + return -4032; if (memcmp(hash, test_hmac[i].output, SHA512_DIGEST_SIZE) != 0) return -20 - i; @@ -1360,8 +1567,8 @@ int arc4_test(void) byte cipher[16]; byte plain[16]; - const char* keys[] = - { + const char* keys[] = + { "\x01\x23\x45\x67\x89\xab\xcd\xef", "\x01\x23\x45\x67\x89\xab\xcd\xef", "\x00\x00\x00\x00\x00\x00\x00\x00", @@ -1407,9 +1614,9 @@ int arc4_test(void) #ifdef HAVE_CAVIUM if (Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0) - return -20001; + return -20001; if (Arc4InitCavium(&dec, CAVIUM_DEV_ID) != 0) - return -20002; + return -20002; #endif Arc4SetKey(&enc, (byte*)keys[i], keylen); @@ -1442,8 +1649,8 @@ int hc128_test(void) byte cipher[16]; byte plain[16]; - const char* keys[] = - { + const char* keys[] = + { "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x53\xA6\xF9\x4C\x9F\xF2\x45\x98\xEB\x3E\x91\xE4\x37\x8A\xDD", @@ -1494,8 +1701,8 @@ int hc128_test(void) HC128 dec; /* align keys/ivs in plain/cipher buffers */ - memcpy(plain, keys[i], 16); - memcpy(cipher, ivs[i], 16); + memcpy(plain, keys[i], 16); + memcpy(cipher, ivs[i], 16); Hc128_SetKey(&enc, plain, cipher); Hc128_SetKey(&dec, plain, cipher); @@ -1523,8 +1730,8 @@ int rabbit_test(void) byte cipher[16]; byte plain[16]; - const char* keys[] = - { + const char* keys[] = + { "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", "\xAC\xC3\x51\xDC\xF1\x62\xFC\x3B\xFE\x36\x3D\x2E\x29\x13\x28\x91" @@ -1553,7 +1760,7 @@ int rabbit_test(void) b.outLen = 8; c.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; - c.output = "\x9C\x51\xE2\x87\x84\xC3\x7F\xE9"; + c.output = "\x04\xCE\xCA\x7A\x1A\x86\x6E\x77"; c.inLen = 8; c.outLen = 8; @@ -1608,34 +1815,40 @@ int des_test(void) Des enc; Des dec; - const byte key[] = + const byte key[] = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef }; - const byte iv[] = + const byte iv[] = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef }; - const byte verify[] = + const byte verify[] = { 0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8, 0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73, 0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b }; + int ret; + + ret = Des_SetKey(&enc, key, iv, DES_ENCRYPTION); + if (ret != 0) + return -31; - Des_SetKey(&enc, key, iv, DES_ENCRYPTION); Des_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); - Des_SetKey(&dec, key, iv, DES_DECRYPTION); + ret = Des_SetKey(&dec, key, iv, DES_DECRYPTION); + if (ret != 0) + return -32; Des_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); if (memcmp(plain, vector, sizeof(plain))) - return -31; + return -33; if (memcmp(cipher, verify, sizeof(cipher))) - return -32; + return -34; return 0; } @@ -1657,44 +1870,54 @@ int des3_test(void) Des3 enc; Des3 dec; - const byte key3[] = + const byte key3[] = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 }; - const byte iv3[] = + const byte iv3[] = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, 0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81 - + }; - const byte verify3[] = + const byte verify3[] = { 0x43,0xa0,0x29,0x7e,0xd1,0x84,0xf8,0x0e, 0x89,0x64,0x84,0x32,0x12,0xd5,0x08,0x98, 0x18,0x94,0x15,0x74,0x87,0x12,0x7d,0xb0 }; + int ret; + #ifdef HAVE_CAVIUM if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) - return -20005; + return -20005; if (Des3_InitCavium(&dec, CAVIUM_DEV_ID) != 0) - return -20006; + return -20006; #endif - Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION); - Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION); - Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); - Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); + ret = Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION); + if (ret != 0) + return -31; + ret = Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION); + if (ret != 0) + return -32; + ret = Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); + if (ret != 0) + return -33; + ret = Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); + if (ret != 0) + return -34; if (memcmp(plain, vector, sizeof(plain))) - return -33; + return -35; if (memcmp(cipher, verify3, sizeof(cipher))) - return -34; + return -36; #ifdef HAVE_CAVIUM Des3_FreeCavium(&enc); @@ -1717,7 +1940,7 @@ int aes_test(void) 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 }; - const byte verify[] = + const byte verify[] = { 0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53, 0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb @@ -1728,18 +1951,27 @@ int aes_test(void) byte cipher[AES_BLOCK_SIZE * 4]; byte plain [AES_BLOCK_SIZE * 4]; + int ret; #ifdef HAVE_CAVIUM if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) - return -20003; + return -20003; if (AesInitCavium(&dec, CAVIUM_DEV_ID) != 0) - return -20004; + return -20004; #endif - AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); - AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION); + ret = AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); + if (ret != 0) + return -1001; + ret = AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION); + if (ret != 0) + return -1002; - AesCbcEncrypt(&enc, cipher, msg, AES_BLOCK_SIZE); - AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE); + ret = AesCbcEncrypt(&enc, cipher, msg, AES_BLOCK_SIZE); + if (ret != 0) + return -1005; + ret = AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE); + if (ret != 0) + return -1006; if (memcmp(plain, msg, AES_BLOCK_SIZE)) return -60; @@ -1753,7 +1985,7 @@ int aes_test(void) #endif #ifdef CYASSL_AES_COUNTER { - const byte ctrKey[] = + const byte ctrKey[] = { 0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6, 0xab,0xf7,0x15,0x88,0x09,0xcf,0x4f,0x3c @@ -1790,6 +2022,12 @@ int aes_test(void) 0x79,0x21,0x70,0xa0,0xf3,0x00,0x9c,0xee }; + const byte oddCipher[] = + { + 0xb9,0xd7,0xcb,0x08,0xb0,0xe1,0x7b,0xa0, + 0xc2 + }; + AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); /* Ctr only uses encrypt, even on key setup */ AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); @@ -1802,9 +2040,73 @@ int aes_test(void) if (memcmp(cipher, ctrCipher, AES_BLOCK_SIZE*4)) return -67; + + /* let's try with just 9 bytes, non block size test */ + AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); + /* Ctr only uses encrypt, even on key setup */ + AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); + + AesCtrEncrypt(&enc, cipher, ctrPlain, 9); + AesCtrEncrypt(&dec, plain, cipher, 9); + + if (memcmp(plain, ctrPlain, 9)) + return -68; + + if (memcmp(cipher, ctrCipher, 9)) + return -69; + + /* and an additional 9 bytes to reuse tmp left buffer */ + AesCtrEncrypt(&enc, cipher, ctrPlain, 9); + AesCtrEncrypt(&dec, plain, cipher, 9); + + if (memcmp(plain, ctrPlain, 9)) + return -70; + + if (memcmp(cipher, oddCipher, 9)) + return -71; } #endif /* CYASSL_AES_COUNTER */ +#if defined(CYASSL_AESNI) && defined(CYASSL_AES_DIRECT) + { + const byte niPlain[] = + { + 0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96, + 0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a + }; + + const byte niCipher[] = + { + 0xf3,0xee,0xd1,0xbd,0xb5,0xd2,0xa0,0x3c, + 0x06,0x4b,0x5a,0x7e,0x3d,0xb1,0x81,0xf8 + }; + + const byte niKey[] = + { + 0x60,0x3d,0xeb,0x10,0x15,0xca,0x71,0xbe, + 0x2b,0x73,0xae,0xf0,0x85,0x7d,0x77,0x81, + 0x1f,0x35,0x2c,0x07,0x3b,0x61,0x08,0xd7, + 0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4 + }; + + XMEMSET(cipher, 0, AES_BLOCK_SIZE); + ret = AesSetKey(&enc, niKey, sizeof(niKey), cipher, AES_ENCRYPTION); + if (ret != 0) + return -1003; + AesEncryptDirect(&enc, cipher, niPlain); + if (XMEMCMP(cipher, niCipher, AES_BLOCK_SIZE) != 0) + return -20006; + + XMEMSET(plain, 0, AES_BLOCK_SIZE); + ret = AesSetKey(&dec, niKey, sizeof(niKey), plain, AES_DECRYPTION); + if (ret != 0) + return -1004; + AesDecryptDirect(&dec, plain, niCipher); + if (XMEMCMP(plain, niPlain, AES_BLOCK_SIZE) != 0) + return -20007; + } +#endif /* CYASSL_AESNI && CYASSL_AES_DIRECT */ + return 0; } @@ -1831,7 +2133,7 @@ int aesgcm_test(void) 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, 0xde, 0xca, 0xf8, 0x88 }; - + const byte p[] = { 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, @@ -1843,14 +2145,14 @@ int aesgcm_test(void) 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, 0xba, 0x63, 0x7b, 0x39 }; - + const byte a[] = { 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, 0xab, 0xad, 0xda, 0xd2 }; - + const byte c[] = { 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, @@ -1897,6 +2199,95 @@ int aesgcm_test(void) return 0; } + +int gmac_test(void) +{ + Gmac gmac; + + const byte k1[] = + { + 0x89, 0xc9, 0x49, 0xe9, 0xc8, 0x04, 0xaf, 0x01, + 0x4d, 0x56, 0x04, 0xb3, 0x94, 0x59, 0xf2, 0xc8 + }; + const byte iv1[] = + { + 0xd1, 0xb1, 0x04, 0xc8, 0x15, 0xbf, 0x1e, 0x94, + 0xe2, 0x8c, 0x8f, 0x16 + }; + const byte a1[] = + { + 0x82, 0xad, 0xcd, 0x63, 0x8d, 0x3f, 0xa9, 0xd9, + 0xf3, 0xe8, 0x41, 0x00, 0xd6, 0x1e, 0x07, 0x77 + }; + const byte t1[] = + { + 0x88, 0xdb, 0x9d, 0x62, 0x17, 0x2e, 0xd0, 0x43, + 0xaa, 0x10, 0xf1, 0x6d, 0x22, 0x7d, 0xc4, 0x1b + }; + + const byte k2[] = + { + 0x40, 0xf7, 0xec, 0xb2, 0x52, 0x6d, 0xaa, 0xd4, + 0x74, 0x25, 0x1d, 0xf4, 0x88, 0x9e, 0xf6, 0x5b + }; + const byte iv2[] = + { + 0xee, 0x9c, 0x6e, 0x06, 0x15, 0x45, 0x45, 0x03, + 0x1a, 0x60, 0x24, 0xa7 + }; + const byte a2[] = + { + 0x94, 0x81, 0x2c, 0x87, 0x07, 0x4e, 0x15, 0x18, + 0x34, 0xb8, 0x35, 0xaf, 0x1c, 0xa5, 0x7e, 0x56 + }; + const byte t2[] = + { + 0xc6, 0x81, 0x79, 0x8e, 0x3d, 0xda, 0xb0, 0x9f, + 0x8d, 0x83, 0xb0, 0xbb, 0x14, 0xb6, 0x91 + }; + + const byte k3[] = + { + 0xb8, 0xe4, 0x9a, 0x5e, 0x37, 0xf9, 0x98, 0x2b, + 0xb9, 0x6d, 0xd0, 0xc9, 0xb6, 0xab, 0x26, 0xac + }; + const byte iv3[] = + { + 0xe4, 0x4a, 0x42, 0x18, 0x8c, 0xae, 0x94, 0x92, + 0x6a, 0x9c, 0x26, 0xb0 + }; + const byte a3[] = + { + 0x9d, 0xb9, 0x61, 0x68, 0xa6, 0x76, 0x7a, 0x31, + 0xf8, 0x29, 0xe4, 0x72, 0x61, 0x68, 0x3f, 0x8a + }; + const byte t3[] = + { + 0x23, 0xe2, 0x9f, 0x66, 0xe4, 0xc6, 0x52, 0x48 + }; + + byte tag[16]; + + memset(tag, 0, sizeof(tag)); + GmacSetKey(&gmac, k1, sizeof(k1)); + GmacUpdate(&gmac, iv1, sizeof(iv1), a1, sizeof(a1), tag, sizeof(t1)); + if (memcmp(t1, tag, sizeof(t1)) != 0) + return -126; + + memset(tag, 0, sizeof(tag)); + GmacSetKey(&gmac, k2, sizeof(k2)); + GmacUpdate(&gmac, iv2, sizeof(iv2), a2, sizeof(a2), tag, sizeof(t2)); + if (memcmp(t2, tag, sizeof(t2)) != 0) + return -127; + + memset(tag, 0, sizeof(tag)); + GmacSetKey(&gmac, k3, sizeof(k3)); + GmacUpdate(&gmac, iv3, sizeof(iv3), a3, sizeof(a3), tag, sizeof(t3)); + if (memcmp(t3, tag, sizeof(t3)) != 0) + return -128; + + return 0; +} #endif /* HAVE_AESGCM */ #ifdef HAVE_AESCCM @@ -1940,7 +2331,7 @@ int aesccm_test(void) const byte t[] = { - 0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 + 0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 }; byte t2[sizeof(t)]; @@ -2009,7 +2400,7 @@ typedef struct { int camellia_test(void) { /* Camellia ECB Test Plaintext */ - static const byte pte[] = + static const byte pte[] = { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 @@ -2061,26 +2452,26 @@ int camellia_test(void) static const byte ptc[] = { 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, - 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A }; /* Camellia CBC Test Initialization Vector */ static const byte ivc[] = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, - 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F }; /* Test 4: Camellia-CBC 128-bit key */ static const byte k4[] = { 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, - 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C + 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C }; static const byte c4[] = { 0x16, 0x07, 0xCF, 0x49, 0x4B, 0x36, 0xBB, 0xF0, - 0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB + 0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB }; /* Test 5: Camellia-CBC 192-bit key */ @@ -2088,12 +2479,12 @@ int camellia_test(void) { 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, - 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B + 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B }; static const byte c5[] = { 0x2A, 0x48, 0x30, 0xAB, 0x5A, 0xC4, 0xA1, 0xA2, - 0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93 + 0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93 }; /* Test 6: CBC 256-bit key */ @@ -2102,12 +2493,12 @@ int camellia_test(void) 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, - 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 }; static const byte c6[] = { 0xE6, 0xCF, 0xA3, 0x5F, 0xC0, 0x2B, 0x13, 0x4A, - 0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA + 0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA }; byte out[CAMELLIA_BLOCK_SIZE]; @@ -2129,14 +2520,11 @@ int camellia_test(void) {CAM_CBC_DEC, ptc, ivc, c6, k6, sizeof(k6), -125} }; - if ((sizeof(pte) != CAMELLIA_BLOCK_SIZE) || - (sizeof(ptc) != CAMELLIA_BLOCK_SIZE)) - return -113; - testsSz = sizeof(testVectors)/sizeof(test_vector_t); for (i = 0; i < testsSz; i++) { - CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz, - testVectors[i].iv); + if (CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz, + testVectors[i].iv) != 0) + return testVectors[i].errorCode; switch (testVectors[i].type) { case CAM_ECB_ENC: @@ -2171,15 +2559,19 @@ int camellia_test(void) if (XMEMCMP(cam.reg, ivc, CAMELLIA_BLOCK_SIZE)) return -1; - /* Setting the IV to NULL should leave the IV unchanged */ + /* Setting the IV to NULL should be same as all zeros IV */ if (CamelliaSetIV(&cam, NULL) != 0 || XMEMCMP(cam.reg, ive, CAMELLIA_BLOCK_SIZE)) return -1; - + /* First parameter should never be null */ if (CamelliaSetIV(NULL, NULL) == 0) return -1; + /* First parameter should never be null, check it fails */ + if (CamelliaSetKey(NULL, k1, sizeof(k1), NULL) == 0) + return -1; + /* Key should have a size of 16, 24, or 32 */ if (CamelliaSetKey(&cam, k1, 0, NULL) == 0) return -1; @@ -2202,7 +2594,8 @@ int random_test(void) ret = InitRng(&rng); if (ret != 0) return -39; - RNG_GenerateBlock(&rng, block, sizeof(block)); + ret = RNG_GenerateBlock(&rng, block, sizeof(block)); + if (ret != 0) return -40; return 0; } @@ -2216,21 +2609,14 @@ byte GetEntropy(ENTROPY_CMD cmd, byte* out) { static RNG rng; - if (cmd == INIT) { - int ret = InitRng(&rng); - if (ret == 0) - return 1; - else - return 0; - } + if (cmd == INIT) + return (InitRng(&rng) == 0) ? 1 : 0; if (out == NULL) return 0; - if (cmd == GET_BYTE_OF_ENTROPY) { - RNG_GenerateBlock(&rng, out, 1); - return 1; - } + if (cmd == GET_BYTE_OF_ENTROPY) + return (RNG_GenerateBlock(&rng, out, 1) == 0) ? 1 : 0; if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) { *out = 1; @@ -2244,30 +2630,46 @@ byte GetEntropy(ENTROPY_CMD cmd, byte* out) #ifndef NO_RSA -#ifdef FREESCALE_MQX - static const char* clientKey = "a:\\certs\\client-key.der"; - static const char* clientCert = "a:\\certs\\client-cert.der"; - #ifdef CYASSL_CERT_GEN - static const char* caKeyFile = "a:\\certs\\ca-key.der"; - static const char* caCertFile = "a:\\certs\\ca-cert.pem"; - #endif -#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && defined(CYASSL_MKD_SHELL) - static char* clientKey = "certs/client-key.der"; - static char* clientCert = "certs/client-cert.der"; - void set_clientKey(char *key) { clientKey = key ; } /* set by shell command */ - void set_clientCert(char *cert) { clientCert = cert ; } /* set by shell command */ - #ifdef CYASSL_CERT_GEN - static char* caKeyFile = "certs/ca-key.der"; - static char* caCertFile = "certs/ca-cert.pem"; - void set_caKeyFile (char * key) { caKeyFile = key ; } /* set by shell command */ - void set_caCertFile(char * cert) { caCertFile = cert ; } /* set by shell command */ - #endif -#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) - static const char* clientKey = "./certs/client-key.der"; - static const char* clientCert = "./certs/client-cert.der"; - #ifdef CYASSL_CERT_GEN - static const char* caKeyFile = "./certs/ca-key.der"; - static const char* caCertFile = "./certs/ca-cert.pem"; +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + #ifdef FREESCALE_MQX + static const char* clientKey = "a:\\certs\\client-key.der"; + static const char* clientCert = "a:\\certs\\client-cert.der"; + #ifdef CYASSL_CERT_GEN + static const char* caKeyFile = "a:\\certs\\ca-key.der"; + static const char* caCertFile = "a:\\certs\\ca-cert.pem"; + #ifdef HAVE_ECC + static const char* eccCaKeyFile = "a:\\certs\\ecc-key.der"; + static const char* eccCaCertFile = "a:\\certs\\server-ecc.pem"; + #endif + #endif + #elif defined(CYASSL_MKD_SHELL) + static char* clientKey = "certs/client-key.der"; + static char* clientCert = "certs/client-cert.der"; + void set_clientKey(char *key) { clientKey = key ; } + void set_clientCert(char *cert) { clientCert = cert ; } + #ifdef CYASSL_CERT_GEN + static char* caKeyFile = "certs/ca-key.der"; + static char* caCertFile = "certs/ca-cert.pem"; + void set_caKeyFile (char * key) { caKeyFile = key ; } + void set_caCertFile(char * cert) { caCertFile = cert ; } + #ifdef HAVE_ECC + static const char* eccCaKeyFile = "certs/ecc-key.der"; + static const char* eccCaCertFile = "certs/server-ecc.pem"; + void set_eccCaKeyFile (char * key) { eccCaKeyFile = key ; } + void set_eccCaCertFile(char * cert) { eccCaCertFile = cert ; } + #endif + #endif + #else + static const char* clientKey = "./certs/client-key.der"; + static const char* clientCert = "./certs/client-cert.der"; + #ifdef CYASSL_CERT_GEN + static const char* caKeyFile = "./certs/ca-key.der"; + static const char* caCertFile = "./certs/ca-cert.pem"; + #ifdef HAVE_ECC + static const char* eccCaKeyFile = "./certs/ecc-key.der"; + static const char* eccCaCertFile = "./certs/server-ecc.pem"; + #endif + #endif #endif #endif @@ -2314,11 +2716,12 @@ int rsa_test(void) bytes = fread(tmp, 1, FOURK_BUF, file); fclose(file); #endif /* USE_CERT_BUFFERS */ - + #ifdef HAVE_CAVIUM RsaInitCavium(&key, CAVIUM_DEV_ID); -#endif - InitRsaKey(&key, 0); +#endif + ret = InitRsaKey(&key, 0); + if (ret != 0) return -39; ret = RsaPrivateKeyDecode(tmp, &idx, &key, (word32)bytes); if (ret != 0) return -41; @@ -2362,8 +2765,8 @@ int rsa_test(void) #endif #ifdef sizeof - #undef sizeof -#endif + #undef sizeof +#endif #ifdef CYASSL_TEST_CERT InitDecodedCert(&cert, tmp, (word32)bytes, 0); @@ -2388,43 +2791,88 @@ int rsa_test(void) FILE* keyFile; FILE* pemFile; - InitRsaKey(&genKey, 0); + ret = InitRsaKey(&genKey, 0); + if (ret != 0) + return -300; ret = MakeRsaKey(&genKey, 1024, 65537, &rng); if (ret != 0) return -301; der = (byte*)malloc(FOURK_BUF); - if (der == NULL) + if (der == NULL) { + FreeRsaKey(&genKey); return -307; + } pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(der); + FreeRsaKey(&genKey); return -308; + } derSz = RsaKeyToDer(&genKey, der, FOURK_BUF); - if (derSz < 0) + if (derSz < 0) { + free(der); + free(pem); return -302; + } keyFile = fopen("./key.der", "wb"); - if (!keyFile) + if (!keyFile) { + free(der); + free(pem); + FreeRsaKey(&genKey); return -303; - ret = (int)fwrite(der, derSz, 1, keyFile); + } + ret = (int)fwrite(der, 1, derSz, keyFile); fclose(keyFile); + if (ret != derSz) { + free(der); + free(pem); + FreeRsaKey(&genKey); + return -313; + } pemSz = DerToPem(der, derSz, pem, FOURK_BUF, PRIVATEKEY_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(der); + free(pem); + FreeRsaKey(&genKey); return -304; + } pemFile = fopen("./key.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(der); + free(pem); + FreeRsaKey(&genKey); return -305; - ret = (int)fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); fclose(pemFile); + if (ret != pemSz) { + free(der); + free(pem); + FreeRsaKey(&genKey); + return -314; + } - InitRsaKey(&derIn, 0); + ret = InitRsaKey(&derIn, 0); + if (ret != 0) { + free(der); + free(pem); + FreeRsaKey(&genKey); + return -3060; + } idx = 0; ret = RsaPrivateKeyDecode(der, &idx, &derIn, derSz); - if (ret != 0) + if (ret != 0) { + free(der); + free(pem); + FreeRsaKey(&derIn); + FreeRsaKey(&genKey); return -306; + } FreeRsaKey(&derIn); FreeRsaKey(&genKey); @@ -2452,8 +2900,10 @@ int rsa_test(void) if (derCert == NULL) return -309; pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(derCert); return -310; + } InitCert(&myCert); @@ -2467,32 +2917,57 @@ int rsa_test(void) myCert.isCA = 1; myCert.sigType = CTC_SHA256wRSA; - certSz = MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng); - if (certSz < 0) + certSz = MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng); + if (certSz < 0) { + free(derCert); + free(pem); return -401; + } #ifdef CYASSL_TEST_CERT InitDecodedCert(&decode, derCert, certSz, 0); ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); - if (ret != 0) + if (ret != 0) { + free(derCert); + free(pem); return -402; + } FreeDecodedCert(&decode); #endif derFile = fopen("./cert.der", "wb"); - if (!derFile) + if (!derFile) { + free(derCert); + free(pem); return -403; - ret = (int)fwrite(derCert, certSz, 1, derFile); + } + ret = (int)fwrite(derCert, 1, certSz, derFile); fclose(derFile); + if (ret != certSz) { + free(derCert); + free(pem); + return -414; + } pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(derCert); + free(pem); return -404; + } pemFile = fopen("./cert.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(derCert); + free(pem); return -405; - ret = (int)fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); fclose(pemFile); + if (ret != pemSz) { + free(derCert); + free(pem); + return -406; + } free(pem); free(derCert); } @@ -2508,7 +2983,7 @@ int rsa_test(void) int pemSz; size_t bytes3; word32 idx3 = 0; - FILE* file3 ; + FILE* file3 ; #ifdef CYASSL_TEST_CERT DecodedCert decode; #endif @@ -2517,20 +2992,35 @@ int rsa_test(void) if (derCert == NULL) return -311; pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(derCert); return -312; + } file3 = fopen(caKeyFile, "rb"); - if (!file3) + if (!file3) { + free(derCert); + free(pem); return -412; + } bytes3 = fread(tmp, 1, FOURK_BUF, file3); fclose(file3); - - InitRsaKey(&caKey, 0); + + ret = InitRsaKey(&caKey, 0); + if (ret != 0) { + free(derCert); + free(pem); + return -411; + } ret = RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3); - if (ret != 0) return -413; + if (ret != 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); + return -413; + } InitCert(&myCert); @@ -2543,46 +3033,224 @@ int rsa_test(void) strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); ret = SetIssuer(&myCert, caCertFile); - if (ret < 0) + if (ret < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -405; + } - certSz = MakeCert(&myCert, derCert, FOURK_BUF, &key, &rng); - if (certSz < 0) + certSz = MakeCert(&myCert, derCert, FOURK_BUF, &key, NULL, &rng); + if (certSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -407; + } certSz = SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF, - &caKey, &rng); - if (certSz < 0) + &caKey, NULL, &rng); + if (certSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -408; + } #ifdef CYASSL_TEST_CERT InitDecodedCert(&decode, derCert, certSz, 0); ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); - if (ret != 0) + if (ret != 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -409; + } FreeDecodedCert(&decode); #endif derFile = fopen("./othercert.der", "wb"); - if (!derFile) + if (!derFile) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -410; - ret = (int)fwrite(derCert, certSz, 1, derFile); + } + ret = (int)fwrite(derCert, 1, certSz, derFile); fclose(derFile); + if (ret != certSz) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); + return -416; + } pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -411; + } pemFile = fopen("./othercert.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -412; - ret = (int)fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); + if (ret != pemSz) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); + return -415; + } fclose(pemFile); free(pem); free(derCert); FreeRsaKey(&caKey); } +#ifdef HAVE_ECC + /* ECC CA style */ + { + ecc_key caKey; + Cert myCert; + byte* derCert; + byte* pem; + FILE* derFile; + FILE* pemFile; + int certSz; + int pemSz; + size_t bytes3; + word32 idx3 = 0; + FILE* file3; +#ifdef CYASSL_TEST_CERT + DecodedCert decode; +#endif + + derCert = (byte*)malloc(FOURK_BUF); + if (derCert == NULL) + return -5311; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) { + free(derCert); + return -5312; + } + + file3 = fopen(eccCaKeyFile, "rb"); + + if (!file3) { + free(derCert); + free(pem); + return -5412; + } + + bytes3 = fread(tmp, 1, FOURK_BUF, file3); + fclose(file3); + + ecc_init(&caKey); + ret = EccPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3); + if (ret != 0) { + free(derCert); + free(pem); + return -5413; + } + + InitCert(&myCert); + myCert.sigType = CTC_SHA256wECDSA; + + strncpy(myCert.subject.country, "US", CTC_NAME_SIZE); + strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE); + strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(myCert.subject.org, "wolfSSL", CTC_NAME_SIZE); + strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(myCert.subject.commonName, "www.wolfssl.com", CTC_NAME_SIZE); + strncpy(myCert.subject.email, "info@wolfssl.com", CTC_NAME_SIZE); + + ret = SetIssuer(&myCert, eccCaCertFile); + if (ret < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5405; + } + + certSz = MakeCert(&myCert, derCert, FOURK_BUF, NULL, &caKey, &rng); + if (certSz < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5407; + } + + certSz = SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF, + NULL, &caKey, &rng); + if (certSz < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5408; + } + +#ifdef CYASSL_TEST_CERT + InitDecodedCert(&decode, derCert, certSz, 0); + ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); + if (ret != 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5409; + } + FreeDecodedCert(&decode); +#endif + + derFile = fopen("./certecc.der", "wb"); + if (!derFile) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5410; + } + ret = (int)fwrite(derCert, 1, certSz, derFile); + fclose(derFile); + if (ret != certSz) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5414; + } + + pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); + if (pemSz < 0) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5411; + } + + pemFile = fopen("./certecc.pem", "wb"); + if (!pemFile) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5412; + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); + if (ret != pemSz) { + free(pem); + free(derCert); + ecc_free(&caKey); + return -5415; + } + fclose(pemFile); + free(pem); + free(derCert); + ecc_free(&caKey); + } +#endif /* HAVE_ECC */ #ifdef HAVE_NTRU { RsaKey caKey; @@ -2595,8 +3263,7 @@ int rsa_test(void) FILE* ntruPrivFile; int certSz; int pemSz; - size_t bytes; - word32 idx = 0; + word32 idx3; #ifdef CYASSL_TEST_CERT DecodedCert decode; #endif @@ -2604,8 +3271,10 @@ int rsa_test(void) if (derCert == NULL) return -311; pem = (byte*)malloc(FOURK_BUF); - if (pem == NULL) + if (pem == NULL) { + free(derCert); return -312; + } byte public_key[557]; /* sized for EES401EP2 */ word16 public_key_len; /* no. of octets in public key */ @@ -2617,32 +3286,53 @@ int rsa_test(void) }; word32 rc = crypto_drbg_instantiate(112, pers_str, sizeof(pers_str), GetEntropy, &drbg); - if (rc != DRBG_OK) + if (rc != DRBG_OK) { + free(derCert); + free(pem); return -450; + } rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len, NULL, &private_key_len, NULL); - if (rc != NTRU_OK) + if (rc != NTRU_OK) { + free(derCert); + free(pem); return -451; + } rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len, public_key, &private_key_len, private_key); crypto_drbg_uninstantiate(drbg); - if (rc != NTRU_OK) + if (rc != NTRU_OK) { + free(derCert); + free(pem); return -452; + } caFile = fopen(caKeyFile, "rb"); - if (!caFile) + if (!caFile) { + free(derCert); + free(pem); return -453; + } bytes = fread(tmp, 1, FOURK_BUF, caFile); fclose(caFile); - - InitRsaKey(&caKey, 0); - ret = RsaPrivateKeyDecode(tmp, &idx, &caKey, (word32)bytes); - if (ret != 0) return -454; + + ret = InitRsaKey(&caKey, 0); + if (ret != 0) { + free(derCert); + free(pem); + return -459; + } + ret = RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes); + if (ret != 0) { + free(derCert); + free(pem); + return -454; + } InitCert(&myCert); @@ -2655,59 +3345,187 @@ int rsa_test(void) strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); ret = SetIssuer(&myCert, caCertFile); - if (ret < 0) + if (ret < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -455; + } certSz = MakeNtruCert(&myCert, derCert, FOURK_BUF, public_key, - public_key_len, &rng); - if (certSz < 0) + public_key_len, &rng); + if (certSz < 0) { + free(derCert); + free(pem); + FreeRsaKey(&caKey); return -456; + } certSz = SignCert(myCert.bodySz, myCert.sigType, derCert, FOURK_BUF, - &caKey, &rng); - if (certSz < 0) + &caKey, NULL, &rng); + FreeRsaKey(&caKey); + if (certSz < 0) { + free(derCert); + free(pem); return -457; + } #ifdef CYASSL_TEST_CERT InitDecodedCert(&decode, derCert, certSz, 0); ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); - if (ret != 0) + if (ret != 0) { + free(derCert); + free(pem); return -458; + } FreeDecodedCert(&decode); #endif derFile = fopen("./ntru-cert.der", "wb"); - if (!derFile) + if (!derFile) { + free(derCert); + free(pem); return -459; - ret = fwrite(derCert, certSz, 1, derFile); + } + ret = (int)fwrite(derCert, 1, certSz, derFile); fclose(derFile); + if (ret != certSz) { + free(derCert); + free(pem); + return -473; + } pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); - if (pemSz < 0) + if (pemSz < 0) { + free(derCert); + free(pem); return -460; + } pemFile = fopen("./ntru-cert.pem", "wb"); - if (!pemFile) + if (!pemFile) { + free(derCert); + free(pem); return -461; - ret = fwrite(pem, pemSz, 1, pemFile); + } + ret = (int)fwrite(pem, 1, pemSz, pemFile); fclose(pemFile); + if (ret != pemSz) { + free(derCert); + free(pem); + return -474; + } ntruPrivFile = fopen("./ntru-key.raw", "wb"); - if (!ntruPrivFile) + if (!ntruPrivFile) { + free(derCert); + free(pem); return -462; - ret = fwrite(private_key, private_key_len, 1, ntruPrivFile); + } + ret = (int)fwrite(private_key, 1, private_key_len, ntruPrivFile); fclose(ntruPrivFile); + if (ret != private_key_len) { + free(pem); + free(derCert); + return -475; + } free(pem); free(derCert); - FreeRsaKey(&caKey); } #endif /* HAVE_NTRU */ +#ifdef CYASSL_CERT_REQ + { + Cert req; + byte* der; + byte* pem; + int derSz; + int pemSz; + FILE* reqFile; + + der = (byte*)malloc(FOURK_BUF); + if (der == NULL) + return -463; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) { + free(der); + return -464; + } + + InitCert(&req); + + req.version = 0; + req.isCA = 1; + strncpy(req.challengePw, "yassl123", CTC_NAME_SIZE); + strncpy(req.subject.country, "US", CTC_NAME_SIZE); + strncpy(req.subject.state, "OR", CTC_NAME_SIZE); + strncpy(req.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(req.subject.org, "yaSSL", CTC_NAME_SIZE); + strncpy(req.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(req.subject.commonName, "www.yassl.com", CTC_NAME_SIZE); + strncpy(req.subject.email, "info@yassl.com", CTC_NAME_SIZE); + req.sigType = CTC_SHA256wRSA; + + derSz = MakeCertReq(&req, der, FOURK_BUF, &key, NULL); + if (derSz < 0) { + free(pem); + free(der); + return -465; + } + + derSz = SignCert(req.bodySz, req.sigType, der, FOURK_BUF, + &key, NULL, &rng); + if (derSz < 0) { + free(pem); + free(der); + return -466; + } + + pemSz = DerToPem(der, derSz, pem, FOURK_BUF, CERTREQ_TYPE); + if (pemSz < 0) { + free(pem); + free(der); + return -467; + } + + reqFile = fopen("./certreq.der", "wb"); + if (!reqFile) { + free(pem); + free(der); + return -468; + } + + ret = (int)fwrite(der, 1, derSz, reqFile); + fclose(reqFile); + if (ret != derSz) { + free(pem); + free(der); + return -471; + } + + reqFile = fopen("./certreq.pem", "wb"); + if (!reqFile) { + free(pem); + free(der); + return -469; + } + ret = (int)fwrite(pem, 1, pemSz, reqFile); + fclose(reqFile); + if (ret != pemSz) { + free(pem); + free(der); + return -470; + } + + free(pem); + free(der); + } +#endif /* CYASSL_CERT_REQ */ #endif /* CYASSL_CERT_GEN */ FreeRsaKey(&key); #ifdef HAVE_CAVIUM RsaFreeCavium(&key); -#endif +#endif free(tmp); return 0; @@ -2718,10 +3536,12 @@ int rsa_test(void) #ifndef NO_DH -#ifdef FREESCALE_MQX - static const char* dhKey = "a:\certs\\dh2048.der"; -#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) - static const char* dhKey = "./certs/dh2048.der"; +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + #ifdef FREESCALE_MQX + static const char* dhKey = "a:\certs\\dh2048.der"; + #else + static const char* dhKey = "./certs/dh2048.der"; + #endif #endif int dh_test(void) @@ -2739,8 +3559,8 @@ int dh_test(void) DhKey key; DhKey key2; RNG rng; - - + + #ifdef USE_CERT_BUFFERS_1024 XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024); bytes = sizeof_dh_key_der_1024; @@ -2757,8 +3577,8 @@ int dh_test(void) fclose(file); #endif /* USE_CERT_BUFFERS */ - InitDhKey(&key); - InitDhKey(&key2); + InitDhKey(&key); + InitDhKey(&key2); ret = DhKeyDecode(tmp, &idx, &key, bytes); if (ret != 0) return -51; @@ -2771,7 +3591,7 @@ int dh_test(void) ret = InitRng(&rng); if (ret != 0) return -53; - + ret = DhGenerateKeyPair(&key, &rng, priv, &privSz, pub, &pubSz); ret += DhGenerateKeyPair(&key2, &rng, priv2, &privSz2, pub2, &pubSz2); if (ret != 0) @@ -2796,10 +3616,12 @@ int dh_test(void) #ifndef NO_DSA -#ifdef FREESCALE_MQX - static const char* dsaKey = "a:\\certs\\dsa2048.der"; -#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) - static const char* dsaKey = "./certs/dsa2048.der"; +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + #ifdef FREESCALE_MQX + static const char* dsaKey = "a:\\certs\\dsa2048.der"; + #else + static const char* dsaKey = "./certs/dsa2048.der"; + #endif #endif int dsa_test(void) @@ -2814,7 +3636,7 @@ int dsa_test(void) byte hash[SHA_DIGEST_SIZE]; byte signature[40]; - + #ifdef USE_CERT_BUFFERS_1024 XMEMCPY(tmp, dsa_key_der_1024, sizeof_dsa_key_der_1024); bytes = sizeof_dsa_key_der_1024; @@ -2830,8 +3652,10 @@ int dsa_test(void) bytes = (word32) fread(tmp, 1, sizeof(tmp), file); fclose(file); #endif /* USE_CERT_BUFFERS */ - - InitSha(&sha); + + ret = InitSha(&sha); + if (ret != 0) + return -4002; ShaUpdate(&sha, tmp, bytes); ShaFinal(&sha, hash); @@ -2848,9 +3672,9 @@ int dsa_test(void) ret = DsaVerify(hash, signature, &key, &answer); if (ret != 0) return -64; if (answer != 1) return -65; - + FreeDsaKey(&key); - + return 0; } @@ -2925,7 +3749,7 @@ int openssl_test(void) e.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b" "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0" "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91" - "\x74\x60\x39"; + "\x74\x60\x39"; e.inLen = strlen(e.input); e.outLen = SHA384_DIGEST_SIZE; @@ -2949,9 +3773,9 @@ int openssl_test(void) "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88" "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4" "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b" - "\x87\x4b\xe9\x09"; + "\x87\x4b\xe9\x09"; f.inLen = strlen(f.input); - f.outLen = SHA512_DIGEST_SIZE; + f.outLen = SHA512_DIGEST_SIZE; EVP_MD_CTX_init(&md_ctx); EVP_DigestInit(&md_ctx, EVP_sha512()); @@ -2967,7 +3791,7 @@ int openssl_test(void) if (RAND_bytes(hash, sizeof(hash)) != 1) return -73; - + c.input = "what do ya want for nothing?"; c.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7" "\x38"; @@ -2989,19 +3813,19 @@ int openssl_test(void) byte plain[24]; byte cipher[24]; - const_DES_cblock key = + const_DES_cblock key = { 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef }; - DES_cblock iv = + DES_cblock iv = { 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef }; DES_key_schedule sched; - const byte verify[] = + const byte verify[] = { 0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8, 0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73, @@ -3038,7 +3862,7 @@ int openssl_test(void) 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 }; - const byte verify[] = + const byte verify[] = { 0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53, 0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb @@ -3084,11 +3908,11 @@ int openssl_test(void) int pkcs12_test(void) { const byte passwd[] = { 0x00, 0x73, 0x00, 0x6d, 0x00, 0x65, 0x00, 0x67, - 0x00, 0x00 }; + 0x00, 0x00 }; const byte salt[] = { 0x0a, 0x58, 0xCF, 0x64, 0x53, 0x0d, 0x82, 0x3f }; const byte passwd2[] = { 0x00, 0x71, 0x00, 0x75, 0x00, 0x65, 0x00, 0x65, - 0x00, 0x67, 0x00, 0x00 }; + 0x00, 0x67, 0x00, 0x00 }; const byte salt2[] = { 0x16, 0x82, 0xC0, 0xfC, 0x5b, 0x3f, 0x7e, 0xc5 }; byte derived[64]; @@ -3117,7 +3941,7 @@ int pkcs12_test(void) return -104; iterations = 1000; - ret = PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8, iterations, + ret = PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8, iterations, kLen, SHA, id); if (ret < 0) return -105; @@ -3143,8 +3967,10 @@ int pbkdf2_test(void) }; - PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations, - kLen, SHA); + int ret = PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, + iterations, kLen, SHA); + if (ret != 0) + return ret; if (memcmp(derived, verify, sizeof(verify)) != 0) return -102; @@ -3186,6 +4012,87 @@ int pwdbased_test(void) #endif /* NO_PWDBASED */ +#if defined(HAVE_HKDF) && (!defined(NO_SHA) || !defined(NO_SHA256)) + +int hkdf_test(void) +{ + int ret; + int L = 42; + byte okm1[42]; + byte ikm1[22] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b }; + byte salt1[13] ={ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c }; + byte info1[10] ={ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf8, 0xf9 }; + byte res1[42] = { 0x0a, 0xc1, 0xaf, 0x70, 0x02, 0xb3, 0xd7, 0x61, + 0xd1, 0xe5, 0x52, 0x98, 0xda, 0x9d, 0x05, 0x06, + 0xb9, 0xae, 0x52, 0x05, 0x72, 0x20, 0xa3, 0x06, + 0xe0, 0x7b, 0x6b, 0x87, 0xe8, 0xdf, 0x21, 0xd0, + 0xea, 0x00, 0x03, 0x3d, 0xe0, 0x39, 0x84, 0xd3, + 0x49, 0x18 }; + byte res2[42] = { 0x08, 0x5a, 0x01, 0xea, 0x1b, 0x10, 0xf3, 0x69, + 0x33, 0x06, 0x8b, 0x56, 0xef, 0xa5, 0xad, 0x81, + 0xa4, 0xf1, 0x4b, 0x82, 0x2f, 0x5b, 0x09, 0x15, + 0x68, 0xa9, 0xcd, 0xd4, 0xf1, 0x55, 0xfd, 0xa2, + 0xc2, 0x2e, 0x42, 0x24, 0x78, 0xd3, 0x05, 0xf3, + 0xf8, 0x96 }; + byte res3[42] = { 0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f, + 0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31, + 0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e, + 0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d, + 0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a, + 0x96, 0xc8 }; + byte res4[42] = { 0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a, + 0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a, + 0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c, + 0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf, + 0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18, + 0x58, 0x65 }; + + (void)res1; + (void)res2; + (void)res3; + (void)res4; + +#ifndef NO_SHA + ret = HKDF(SHA, ikm1, 22, NULL, 0, NULL, 0, okm1, L); + if (ret != 0) + return -2001; + + if (memcmp(okm1, res1, L) != 0) + return -2002; + + ret = HKDF(SHA, ikm1, 11, salt1, 13, info1, 10, okm1, L); + if (ret != 0) + return -2003; + + if (memcmp(okm1, res2, L) != 0) + return -2004; +#endif /* NO_SHA */ + +#ifndef NO_SHA256 + ret = HKDF(SHA256, ikm1, 22, NULL, 0, NULL, 0, okm1, L); + if (ret != 0) + return -2005; + + if (memcmp(okm1, res3, L) != 0) + return -2006; + + ret = HKDF(SHA256, ikm1, 22, salt1, 13, info1, 10, okm1, L); + if (ret != 0) + return -2007; + + if (memcmp(okm1, res4, L) != 0) + return -2007; +#endif /* NO_SHA256 */ + + return 0; +} + +#endif /* HAVE_HKDF */ + #ifdef HAVE_ECC @@ -3210,6 +4117,10 @@ int ecc_test(void) ecc_init(&pubKey); ret = ecc_make_key(&rng, 32, &userA); + + if (ret != 0) + return -1014; + ret = ecc_make_key(&rng, 32, &userB); if (ret != 0) @@ -3217,10 +4128,13 @@ int ecc_test(void) x = sizeof(sharedA); ret = ecc_shared_secret(&userA, &userB, sharedA, &x); - + + if (ret != 0) + return -1015; + y = sizeof(sharedB); ret = ecc_shared_secret(&userB, &userA, sharedB, &y); - + if (ret != 0) return -1003; @@ -3237,12 +4151,12 @@ int ecc_test(void) ret = ecc_import_x963(exportBuf, x, &pubKey); - if (ret != 0) + if (ret != 0) return -1007; y = sizeof(sharedB); ret = ecc_shared_secret(&userB, &pubKey, sharedB, &y); - + if (ret != 0) return -1008; @@ -3251,11 +4165,14 @@ int ecc_test(void) /* test DSA sign hash */ for (i = 0; i < (int)sizeof(digest); i++) - digest[i] = i; + digest[i] = (byte)i; x = sizeof(sig); ret = ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &userA); - + + if (ret != 0) + return -1016; + verify = 0; ret = ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &userA); @@ -3265,6 +4182,11 @@ int ecc_test(void) if (verify != 1) return -1012; + x = sizeof(exportBuf); + ret = ecc_export_private_only(&userA, exportBuf, &x); + if (ret != 0) + return -1013; + ecc_free(&pubKey); ecc_free(&userB); ecc_free(&userA); @@ -3272,6 +4194,134 @@ int ecc_test(void) return 0; } +#ifdef HAVE_ECC_ENCRYPT + +int ecc_encrypt_test(void) +{ + RNG rng; + int ret; + ecc_key userA, userB; + byte msg[48]; + byte plain[48]; + byte out[80]; + word32 outSz = sizeof(out); + word32 plainSz = sizeof(plain); + int i; + + ret = InitRng(&rng); + if (ret != 0) + return -3001; + + ecc_init(&userA); + ecc_init(&userB); + + ret = ecc_make_key(&rng, 32, &userA); + ret += ecc_make_key(&rng, 32, &userB); + + if (ret != 0) + return -3002; + + for (i = 0; i < 48; i++) + msg[i] = i; + + /* encrypt msg to B */ + ret = ecc_encrypt(&userA, &userB, msg, sizeof(msg), out, &outSz, NULL); + if (ret != 0) + return -3003; + + /* decrypt msg from A */ + ret = ecc_decrypt(&userB, &userA, out, outSz, plain, &plainSz, NULL); + if (ret != 0) + return -3004; + + if (memcmp(plain, msg, sizeof(msg)) != 0) + return -3005; + + + { /* let's verify message exchange works, A is client, B is server */ + ecEncCtx* cliCtx = ecc_ctx_new(REQ_RESP_CLIENT, &rng); + ecEncCtx* srvCtx = ecc_ctx_new(REQ_RESP_SERVER, &rng); + + byte cliSalt[EXCHANGE_SALT_SZ]; + byte srvSalt[EXCHANGE_SALT_SZ]; + const byte* tmpSalt; + + if (cliCtx == NULL || srvCtx == NULL) + return -3006; + + /* get salt to send to peer */ + tmpSalt = ecc_ctx_get_own_salt(cliCtx); + if (tmpSalt == NULL) + return -3007; + memcpy(cliSalt, tmpSalt, EXCHANGE_SALT_SZ); + + tmpSalt = ecc_ctx_get_own_salt(srvCtx); + if (tmpSalt == NULL) + return -3007; + memcpy(srvSalt, tmpSalt, EXCHANGE_SALT_SZ); + + /* in actual use, we'd get the peer's salt over the transport */ + ret = ecc_ctx_set_peer_salt(cliCtx, srvSalt); + ret += ecc_ctx_set_peer_salt(srvCtx, cliSalt); + + if (ret != 0) + return -3008; + + /* get encrypted msg (request) to send to B */ + outSz = sizeof(out); + ret = ecc_encrypt(&userA, &userB, msg, sizeof(msg), out, &outSz,cliCtx); + if (ret != 0) + return -3009; + + /* B decrypts msg (request) from A */ + plainSz = sizeof(plain); + ret = ecc_decrypt(&userB, &userA, out, outSz, plain, &plainSz, srvCtx); + if (ret != 0) + return -3010; + + if (memcmp(plain, msg, sizeof(msg)) != 0) + return -3011; + + { + /* msg2 (response) from B to A */ + byte msg2[48]; + byte plain2[48]; + byte out2[80]; + word32 outSz2 = sizeof(out2); + word32 plainSz2 = sizeof(plain2); + + for (i = 0; i < 48; i++) + msg2[i] = i+48; + + /* get encrypted msg (response) to send to B */ + ret = ecc_encrypt(&userB, &userA, msg2, sizeof(msg2), out2, + &outSz2, srvCtx); + if (ret != 0) + return -3012; + + /* A decrypts msg (response) from B */ + ret = ecc_decrypt(&userA, &userB, out2, outSz2, plain2, &plainSz2, + cliCtx); + if (ret != 0) + return -3013; + + if (memcmp(plain2, msg2, sizeof(msg2)) != 0) + return -3014; + } + + /* cleanup */ + ecc_ctx_free(srvCtx); + ecc_ctx_free(cliCtx); + } + + /* cleanup */ + ecc_free(&userB); + ecc_free(&userA); + + return 0; +} + +#endif /* HAVE_ECC_ENCRYPT */ #endif /* HAVE_ECC */ #ifdef HAVE_LIBZ @@ -3381,7 +4431,7 @@ int compress_test(void) if (ret == 0 && memcmp(d, sample_text, dSz)) ret = -303; - + if (c) free(c); if (d) free(d); @@ -3390,4 +4440,319 @@ int compress_test(void) #endif /* HAVE_LIBZ */ +#ifdef HAVE_PKCS7 + +int pkcs7enveloped_test(void) +{ + int ret = 0; + + int cipher = DES3b; + int envelopedSz, decodedSz; + PKCS7 pkcs7; + byte* cert; + byte* privKey; + byte enveloped[2048]; + byte decoded[2048]; + + size_t certSz; + size_t privKeySz; + FILE* certFile; + FILE* keyFile; + FILE* pkcs7File; + const char* pkcs7OutFile = "pkcs7envelopedData.der"; + + const byte data[] = { /* Hello World */ + 0x48,0x65,0x6c,0x6c,0x6f,0x20,0x57,0x6f, + 0x72,0x6c,0x64 + }; + + /* read client cert and key in DER format */ + cert = (byte*)malloc(FOURK_BUF); + if (cert == NULL) + return -201; + + privKey = (byte*)malloc(FOURK_BUF); + if (privKey == NULL) { + free(cert); + return -202; + } + + certFile = fopen(clientCert, "rb"); + if (!certFile) { + free(cert); + free(privKey); + err_sys("can't open ./certs/client-cert.der, " + "Please run from CyaSSL home dir", -42); + } + + certSz = fread(cert, 1, FOURK_BUF, certFile); + fclose(certFile); + + keyFile = fopen(clientKey, "rb"); + if (!keyFile) { + free(cert); + free(privKey); + err_sys("can't open ./certs/client-key.der, " + "Please run from CyaSSL home dir", -43); + } + + privKeySz = fread(privKey, 1, FOURK_BUF, keyFile); + fclose(keyFile); + + PKCS7_InitWithCert(&pkcs7, cert, (word32)certSz); + pkcs7.content = (byte*)data; + pkcs7.contentSz = (word32)sizeof(data); + pkcs7.contentOID = DATA; + pkcs7.encryptOID = cipher; + pkcs7.privateKey = privKey; + pkcs7.privateKeySz = (word32)privKeySz; + + /* encode envelopedData */ + envelopedSz = PKCS7_EncodeEnvelopedData(&pkcs7, enveloped, + sizeof(enveloped)); + if (envelopedSz <= 0) { + free(cert); + free(privKey); + return -203; + } + + /* decode envelopedData */ + decodedSz = PKCS7_DecodeEnvelopedData(&pkcs7, enveloped, envelopedSz, + decoded, sizeof(decoded)); + if (decodedSz <= 0) { + free(cert); + free(privKey); + return -204; + } + + /* test decode result */ + if (memcmp(decoded, data, sizeof(data)) != 0) { + free(cert); + free(privKey); + return -205; + } + + /* output pkcs7 envelopedData for external testing */ + pkcs7File = fopen(pkcs7OutFile, "wb"); + if (!pkcs7File) { + free(cert); + free(privKey); + return -206; + } + + ret = (int)fwrite(enveloped, envelopedSz, 1, pkcs7File); + fclose(pkcs7File); + + free(cert); + free(privKey); + PKCS7_Free(&pkcs7); + + if (ret > 0) + return 0; + + return ret; +} + +int pkcs7signed_test(void) +{ + int ret = 0; + + FILE* file; + byte* certDer; + byte* keyDer; + byte* out; + char data[] = "Hello World"; + word32 dataSz, outSz, certDerSz, keyDerSz; + PKCS7 msg; + RNG rng; + + byte transIdOid[] = + { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01, + 0x09, 0x07 }; + byte messageTypeOid[] = + { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01, + 0x09, 0x02 }; + byte senderNonceOid[] = + { 0x06, 0x0a, 0x60, 0x86, 0x48, 0x01, 0x86, 0xF8, 0x45, 0x01, + 0x09, 0x05 }; + byte transId[(SHA_DIGEST_SIZE + 1) * 2 + 1]; + byte messageType[] = { 0x13, 2, '1', '9' }; + byte senderNonce[PKCS7_NONCE_SZ + 2]; + + PKCS7Attrib attribs[] = + { + { transIdOid, sizeof(transIdOid), + transId, sizeof(transId) - 1 }, /* take off the null */ + { messageTypeOid, sizeof(messageTypeOid), + messageType, sizeof(messageType) }, + { senderNonceOid, sizeof(senderNonceOid), + senderNonce, sizeof(senderNonce) } + }; + + dataSz = (word32) strlen(data); + outSz = FOURK_BUF; + + certDer = (byte*)malloc(FOURK_BUF); + if (certDer == NULL) + return -207; + keyDer = (byte*)malloc(FOURK_BUF); + if (keyDer == NULL) { + free(certDer); + return -208; + } + out = (byte*)malloc(FOURK_BUF); + if (out == NULL) { + free(certDer); + free(keyDer); + return -209; + } + + /* read in DER cert of recipient, into cert of size certSz */ + file = fopen(clientCert, "rb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + err_sys("can't open ./certs/client-cert.der, " + "Please run from CyaSSL home dir", -44); + } + certDerSz = (word32)fread(certDer, 1, FOURK_BUF, file); + fclose(file); + + file = fopen(clientKey, "rb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + err_sys("can't open ./certs/client-key.der, " + "Please run from CyaSSL home dir", -45); + } + keyDerSz = (word32)fread(keyDer, 1, FOURK_BUF, file); + fclose(file); + + ret = InitRng(&rng); + if (ret != 0) { + free(certDer); + free(keyDer); + free(out); + return -210; + } + + senderNonce[0] = 0x04; + senderNonce[1] = PKCS7_NONCE_SZ; + + ret = RNG_GenerateBlock(&rng, &senderNonce[2], PKCS7_NONCE_SZ); + if (ret != 0) { + free(certDer); + free(keyDer); + free(out); + return -211; + } + + PKCS7_InitWithCert(&msg, certDer, certDerSz); + msg.privateKey = keyDer; + msg.privateKeySz = keyDerSz; + msg.content = (byte*)data; + msg.contentSz = dataSz; + msg.hashOID = SHAh; + msg.encryptOID = RSAk; + msg.signedAttribs = attribs; + msg.signedAttribsSz = sizeof(attribs)/sizeof(PKCS7Attrib); + msg.rng = &rng; + { + Sha sha; + byte digest[SHA_DIGEST_SIZE]; + int i,j; + + transId[0] = 0x13; + transId[1] = SHA_DIGEST_SIZE * 2; + + ret = InitSha(&sha); + if (ret != 0) { + free(certDer); + free(keyDer); + free(out); + return -4003; + } + ShaUpdate(&sha, msg.publicKey, msg.publicKeySz); + ShaFinal(&sha, digest); + + for (i = 0, j = 2; i < SHA_DIGEST_SIZE; i++, j += 2) { + snprintf((char*)&transId[j], 3, "%02x", digest[i]); + } + } + ret = PKCS7_EncodeSignedData(&msg, out, outSz); + if (ret < 0) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -212; + } + else + outSz = ret; + + /* write PKCS#7 to output file for more testing */ + file = fopen("./pkcs7signedData.der", "wb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -213; + } + ret = (int)fwrite(out, 1, outSz, file); + fclose(file); + if (ret != (int)outSz) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -218; + } + + PKCS7_Free(&msg); + PKCS7_InitWithCert(&msg, NULL, 0); + + ret = PKCS7_VerifySignedData(&msg, out, outSz); + if (ret < 0) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -214; + } + + if (msg.singleCert == NULL || msg.singleCertSz == 0) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -215; + } + + file = fopen("./pkcs7cert.der", "wb"); + if (!file) { + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + return -216; + } + ret = (int)fwrite(msg.singleCert, 1, msg.singleCertSz, file); + fclose(file); + + free(certDer); + free(keyDer); + free(out); + PKCS7_Free(&msg); + + if (ret > 0) + return 0; + + return ret; +} + +#endif /* HAVE_PKCS7 */ + #endif /* NO_CRYPT_TEST */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/time-CortexM3-4.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/time-CortexM3-4.c new file mode 100644 index 0000000000..46712b34cd --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/time-CortexM3-4.c @@ -0,0 +1,41 @@ +/* time-STM32F2.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + + +#include +#define DWT ((DWT_Type *) (0xE0001000UL) ) +typedef struct +{ + uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +} DWT_Type; + +extern uint32_t SystemCoreClock ; + +double current_time(int reset) +{ + if(reset) DWT->CYCCNT = 0 ; + return ((double)DWT->CYCCNT/SystemCoreClock) ; +} diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/time-dummy.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/time-dummy.c new file mode 100644 index 0000000000..2525eba38b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/time-dummy.c @@ -0,0 +1,34 @@ +/* time-dummy.c.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + return(&date) ; +} + +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt b/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt index 2656e40330..42ac37cf95 100644 --- a/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt @@ -1,7 +1,7 @@ This program is echo client with CyaSSL/wolfCrypt library. In order to run this program, -Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +Copy {PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. Set config-EchoClient.h configuration file for the Callee IP or Port number. For further configuration, refer config-Crypt.h and config-CyaSSL.h. diff --git a/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx index 7e61facf58..903ee3cacc 100644 --- a/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx +++ b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx @@ -76,6 +76,23 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL -REMAP -MPU @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,7 +135,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -209,8 +228,8 @@ 0 0 0 - 0 - 0 + 16 + 99 0 .\main.c main.c @@ -223,10 +242,10 @@ 1 0 0 - 28 + 24 0 - 0 - 0 + 149 + 166 0 .\echoclient.c echoclient.c @@ -247,13 +266,13 @@ 5 0 0 - 24 + 0 0 0 0 0 - .\config-EchoClient.h - config-EchoClient.h + .\RTE\wolfSSL\config-CyaSSL.h + config-CyaSSL.h 0 0 @@ -268,8 +287,8 @@ 0 0 0 - .\RTE\wolfSSL\config-CyaSSL.h - config-CyaSSL.h + .\RTE\wolfSSL\config-Crypt.h + config-Crypt.h 0 0 @@ -279,13 +298,13 @@ 5 0 0 - 0 + 33 0 - 0 - 0 + 3 + 17 0 - .\RTE\wolfSSL\config-Crypt.h - config-Crypt.h + .\RTE\Network\Net_Config_ETH_0.h + Net_Config_ETH_0.h 0 0 @@ -305,8 +324,8 @@ 0 0 0 - 1 - 1 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -315,15 +334,55 @@ + + Devices + 1 + 0 + 0 + 0 + + 4 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\time-dummy.c + time-dummy.c + 0 + 0 + + + ::CMSIS - 0 + 1 0 0 1 - 4 - 7 + 5 + 8 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + RTE\CMSIS\RTX_Conf_CM.c + RTX_Conf_CM.c + 1 + 0 + + + 5 + 9 4 0 0 @@ -332,70 +391,22 @@ 0 0 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib RTX_CM3.lib 1 0 - - 4 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RTE\CMSIS\RTX_Conf_CM.c - RTX_Conf_CM.c - 1 - 0 - ::Device - 0 + 1 0 0 1 - 5 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 - 0 - - - 5 + 6 10 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c - 1 - 0 - - - 5 - 11 5 0 0 @@ -410,15 +421,15 @@ 0 - 5 - 12 + 6 + 11 2 0 0 0 0 - 0 - 0 + 163 + 169 0 RTE\Device\STM32F207IG\startup_stm32f2xx.s startup_stm32f2xx.s @@ -426,8 +437,8 @@ 0 - 5 - 13 + 6 + 12 1 0 0 @@ -441,14 +452,22 @@ 1 0 - - - - ::Drivers - 0 - 0 - 0 - 1 + + 6 + 13 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c + 1 + 0 + 6 14 @@ -460,13 +479,21 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c - PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c 1 0 + + + + ::Drivers + 0 + 0 + 0 + 1 - 6 + 7 15 1 0 @@ -476,13 +503,13 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c - EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c + PHY_ST802RT1.c 1 0 - 6 + 7 16 1 0 @@ -492,7 +519,23 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c + EMAC_STM32F2xx.c + 1 + 0 + + + 7 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c MCI_STM32F2xx.c 1 0 @@ -506,23 +549,7 @@ 0 1 - 7 - 17 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib - 1 - 0 - - - 7 + 8 18 1 0 @@ -538,7 +565,7 @@ 0 - 7 + 8 19 5 0 @@ -553,14 +580,6 @@ 1 0 - - - - ::Network - 0 - 0 - 0 - 1 8 20 @@ -572,13 +591,21 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Dbg_CM3_L.lib + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib 1 0 + + + + ::Network + 1 + 0 + 0 + 1 - 8 + 9 21 1 0 @@ -594,7 +621,7 @@ 0 - 8 + 9 22 5 0 @@ -610,7 +637,7 @@ 0 - 8 + 9 23 5 0 @@ -626,15 +653,15 @@ 0 - 8 + 9 24 5 0 0 - 0 + 33 0 - 0 - 0 + 3 + 17 0 RTE\Network\Net_Config_ETH_0.h Net_Config_ETH_0.h @@ -642,7 +669,7 @@ 0 - 8 + 9 25 5 0 @@ -658,7 +685,7 @@ 0 - 8 + 9 26 5 0 @@ -674,9 +701,25 @@ 0 - 8 + 9 27 1 + 1 + 0 + 0 + 0 + 102 + 125 + 0 + RTE\Network\Net_Debug.c + Net_Debug.c + 1 + 0 + + + 9 + 28 + 4 0 0 0 @@ -684,8 +727,8 @@ 0 0 0 - RTE\Network\Net_Debug.c - Net_Debug.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + Net_Dbg_CM3_L.lib 1 0 @@ -698,680 +741,8 @@ 0 1 - 9 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 9 + 10 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 9 - 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 9 - 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - arc4.c - 1 - 0 - - - 9 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - asm.c - 1 - 0 - - - 9 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - asn.c - 1 - 0 - - - 9 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - blake2b.c - 1 - 0 - - - 9 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - camellia.c - 1 - 0 - - - 9 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - coding.c - 1 - 0 - - - 9 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - compress.c - 1 - 0 - - - 9 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - des3.c - 1 - 0 - - - 9 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - dh.c - 1 - 0 - - - 9 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - dsa.c - 1 - 0 - - - 9 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - ecc.c - 1 - 0 - - - 9 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c - 1 - 0 - - - 9 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - error.c - 1 - 0 - - - 9 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - hc128.c - 1 - 0 - - - 9 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - hmac.c - 1 - 0 - - - 9 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - integer.c - 1 - 0 - - - 9 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - logging.c - 1 - 0 - - - 9 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - md2.c - 1 - 0 - - - 9 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - md4.c - 1 - 0 - - - 9 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - md5.c - 1 - 0 - - - 9 - 51 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - memory.c - 1 - 0 - - - 9 - 52 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - misc.c - 1 - 0 - - - 9 - 53 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c - 1 - 0 - - - 9 - 54 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - rabbit.c - 1 - 0 - - - 9 - 55 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - random.c - 1 - 0 - - - 9 - 56 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - ripemd.c - 1 - 0 - - - 9 - 57 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - rsa.c - 1 - 0 - - - 9 - 58 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - sha.c - 1 - 0 - - - 9 - 59 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - sha256.c - 1 - 0 - - - 9 - 60 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - sha512.c - 1 - 0 - - - 9 - 61 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - tfm.c - 1 - 0 - - - 9 - 62 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - crl.c - 1 - 0 - - - 9 - 63 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - internal.c - 1 - 0 - - - 9 - 64 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - io.c - 1 - 0 - - - 9 - 65 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - keys.c - 1 - 0 - - - 9 - 66 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - ocsp.c - 1 - 0 - - - 9 - 67 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - sniffer.c - 1 - 0 - - - 9 - 68 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - ssl.c - 1 - 0 - - - 9 - 69 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - tls.c - 1 - 0 - - - 9 - 70 5 0 0 @@ -1386,8 +757,8 @@ 0 - 9 - 71 + 10 + 30 5 0 0 @@ -1402,7 +773,663 @@ 0 - 9 + 10 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c + 1 + 0 + + + 10 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c + 1 + 0 + + + 10 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c + 1 + 0 + + + 10 + 34 + 1 + 0 + 0 + 13 + 0 + 1441 + 1569 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c + 1 + 0 + + + 10 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c + 1 + 0 + + + 10 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c + 1 + 0 + + + 10 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c + 1 + 0 + + + 10 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c + 1 + 0 + + + 10 + 39 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c + 1 + 0 + + + 10 + 40 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c + 1 + 0 + + + 10 + 41 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c + 1 + 0 + + + 10 + 42 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c + 1 + 0 + + + 10 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c + 1 + 0 + + + 10 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c + 1 + 0 + + + 10 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c + 1 + 0 + + + 10 + 46 + 1 + 0 + 0 + 0 + 0 + 66 + 89 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c + 1 + 0 + + + 10 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c + 1 + 0 + + + 10 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c + 1 + 0 + + + 10 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c + 1 + 0 + + + 10 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c + 1 + 0 + + + 10 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c + 1 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c + 1 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c + 1 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c + 1 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + crl.c + 1 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + internal.c + 1 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + io.c + 1 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + keys.c + 1 + 0 + + + 10 + 68 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + ocsp.c + 1 + 0 + + + 10 + 69 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + sniffer.c + 1 + 0 + + + 10 + 70 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + ssl.c + 1 + 0 + + + 10 + 71 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c + tls.c + 1 + 0 + + + 10 72 5 0 @@ -1412,8 +1439,24 @@ 0 0 0 - RTE\wolfSSL\config.h - config.h + RTE\wolfSSL\settings.h + settings.h + 1 + 0 + + + 10 + 73 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx index 7b4076c600..9083e55699 100644 --- a/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx +++ b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,9 +355,11 @@ 0 0 0 + 0 + 0 - HAVE_CONFIG_H MDK_CONF_EchoClient CYASSL_STM32F2xx + HAVE_CONFIG_H MDK_CONF_EchoClient @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -413,11 +419,6 @@ Configuration - - config-EchoClient.h - 5 - .\config-EchoClient.h - config-CyaSSL.h 5 @@ -428,6 +429,11 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + Net_Config_ETH_0.h + 5 + .\RTE\Network\Net_Config_ETH_0.h + @@ -441,33 +447,33 @@ - ::CMSIS + Devices - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + time-dummy.c + 1 + .\time-dummy.c + + + + ::CMSIS + RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -483,6 +489,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -491,28 +507,23 @@ PHY_ST802RT1.c 1 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c EMAC_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -523,16 +534,16 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + ::Network - - Net_Dbg_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Config.c 1 @@ -568,221 +579,16 @@ 1 RTE\Network\Net_Debug.c + + Net_Dbg_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + ::wolfSSL - - cyassl_MDK_ARM.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - - - time-STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - - - aes.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - - - arc4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - - - asm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - - - asn.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - - - blake2b.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - - - camellia.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - - - coding.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - - - compress.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - - - des3.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - - - dh.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - - - dsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - - - ecc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - - - ecc_fp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - - - error.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - - - hc128.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - - - hmac.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - - - integer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - - - logging.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - - - md2.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - - - md4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - - - md5.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - - - memory.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - - - misc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - - - pwdbased.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - - - rabbit.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - - - random.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - - - ripemd.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - - - rsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - - - sha.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - - - sha256.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - - - sha512.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - - - tfm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - - - crl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - - - internal.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - - - io.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - - - keys.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - - - ocsp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - - - sniffer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - - - ssl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - - - tls.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - config-Crypt.h 5 @@ -794,9 +600,219 @@ RTE\wolfSSL\config-CyaSSL.h - config.h + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + + + crl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + + + internal.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + + + io.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + + + keys.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + + + ocsp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + + + sniffer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + + + ssl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + + + tls.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c + + + settings.h 5 - RTE\wolfSSL\config.h + RTE\wolfSSL\settings.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c @@ -806,25 +822,25 @@ - + - + - + - + @@ -838,20 +854,20 @@ - - + + - - + + - - + + @@ -928,20 +944,14 @@ - - + + - - - - - - - - + + @@ -950,8 +960,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -1078,24 +1088,30 @@ RTE\wolfSSL\config-Crypt.h - - + + RTE\wolfSSL\config-CyaSSL.h - - + + - RTE\wolfSSL\config.h - - + RTE\wolfSSL\config.h + + + + + + RTE\wolfSSL\settings.h + + diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index 54b3e0bfc3..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 5 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 250 -#endif - -// Main Thread stack size [bytes] <64-20000:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 2000 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 2 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 2500 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-64000:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 4a09246f38..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 1 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index d398143ef3..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00007000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c deleted file mode 100644 index 6b9dc8e00d..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c +++ /dev/null @@ -1,153 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Definitions -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "my_host" - -// Memory Pool size <1536-262144:4><#/4> -// This is the size of a memory pool in bytes. Buffers for -// Network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_SIZE 3000 - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP_0 -#include "Net_Config_PPP_0.h" -#endif -#ifdef RTE_Network_Interface_PPP_1 -#include "Net_Config_PPP_1.h" -#endif - -#ifdef RTE_Network_Interface_SLIP_0 -#include "Net_Config_SLIP_0.h" -#endif -#ifdef RTE_Network_Interface_SLIP_1 -#include "Net_Config_SLIP_1.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (ERROR_CODE error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (ERROR_CODE error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case ERR_MEM_ALLOC: - /* Out of memory */ - break; - - case ERR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case ERR_MEM_CORRUPT: - /* Memory Link pointer Corrupted */ - /* More data written than the size of allocated mem block */ - break; - - case ERR_MEM_LOCK: - /* Locked Memory management function (alloc/free) re-entered */ - break; - - case ERR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case ERR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case ERR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index d7e6a614ae..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,36 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration BSD Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 7 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 1 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h deleted file mode 100644 index d30b718079..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_DNS_Client.h - * Purpose: Network Configuration DNS Client - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// DNS Client -#define DNS_CLIENT_ENABLE 1 - -// Cache Table size <5-100> -// Number of cached DNS host names/IP addresses -// Default: 20 -#define DNS_CLIENT_TAB_SIZE 20 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index 7be57ad6d5..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,222 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration ETH Interface - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 1 - -// MAC Address -// Local Ethernet MAC Address -// Value FF:FF:FF:FF:FF:FF is not allowed. -// It is an ethernet Broadcast MAC address. -// Address byte 1 <0x00-0xff:2> -// LSB is an ethernet Multicast bit. -// Must be 0 for local MAC address. -// Default: 0x1E -#define ETH0_MAC1 0x1E - -// Address byte 2 <0x00-0xff> -// Default: 0x30 -#define ETH0_MAC2 0x30 - -// Address byte 3 <0x00-0xff> -// Default: 0x6C -#define ETH0_MAC3 0x6C - -// Address byte 4 <0x00-0xff> -// Default: 0xA2 -#define ETH0_MAC4 0xA2 - -// Address byte 5 <0x00-0xff> -// Default: 0x45 -#define ETH0_MAC5 0x45 - -// Address byte 6 <0x00-0xff> -// Default: 0x5E -#define ETH0_MAC6 0x5E -// - -// IP Address -// Local Static IP Address -// Value 255.255.255.255 is not allowed. -// It is a Broadcast IP address. -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_IP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_IP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_IP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define ETH0_IP4 100 -// - -// Subnet mask -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define ETH0_MASK1 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define ETH0_MASK2 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define ETH0_MASK3 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define ETH0_MASK4 0 -// - -// Default Gateway -// Default Gateway IP Address -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_GW1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_GW2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_GW3 0 - -// Address byte 4 <0-255> -// Default: 254 -#define ETH0_GW4 254 -// - -// Primary DNS Server -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_PRI_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_PRI_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_PRI_DNS3 2 - -// Address byte 4 <0-255> -// Default: 129 -#define ETH0_PRI_DNS4 129 -// - -// Secondary DNS Server -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_SEC_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_SEC_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_SEC_DNS3 2 - -// Address byte 4 <0-255> -// Default: 130 -#define ETH0_SEC_DNS4 130 -// - -// ARP Definitions -// Address Resolution Protocol Definitions -// Cache Table size <5-100> -// Number of cached hardware/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for a cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by his name on the local LAN using NBNS protocol. -// You need to modify also the number of UDP Sockets, -// because NBNS protocol uses one UDP socket to run. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -// You need to modify also the number of UDP Sockets, -// because DHCP protocol uses one UDP socket to run. -#define ETH0_DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// - -// diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index e659ce9211..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,61 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration TCP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 5 -#define TCP_NUM_SOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low_throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-600> -// Default TCP Socket Keep Alive timeout. When it expires -// with no TCP data frame send, TCP Connection is closed. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1460> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1460 -#define TCP_MAX_SEG_SIZE 1460 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4380 -#define TCP_RECEIVE_WIN_SIZE 4380 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index b7995c22de..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration UDP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 10 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Debug.c deleted file mode 100644 index 735089a409..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Debug.c +++ /dev/null @@ -1,125 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Debug.c - * Purpose: Network Debug Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Print Time Stamp -// Enable printing the time-info in debug messages -#define DBG_TIME 1 - -// TCPnet Debug Definitions -// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Memory debug messages -#define DBG_MEM 1 - -// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Ethernet debug messages -#define DBG_ETH 0 - -// PPP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off PPP debug messages -#define DBG_PPP 0 - -// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SLIP debug messages -#define DBG_SLIP 0 - -// ARP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ARP debug messages -#define DBG_ARP 0 - -// IP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IP debug messages -#define DBG_IP 1 - -// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ICMP debug messages -#define DBG_ICMP 1 - -// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IGMP debug messages -#define DBG_IGMP 1 - -// UDP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off UDP debug messages -#define DBG_UDP 1 - -// TCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TCP debug messages -#define DBG_TCP 1 - -// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off NetBIOS Name Service debug messages -#define DBG_NBNS 1 - -// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Host Configuration debug messages -#define DBG_DHCP 1 - -// DNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Domain Name Service debug messages -#define DBG_DNS 1 - -// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Management debug messages -#define DBG_SNMP 1 - -// SNTP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Time debug messages -#define DBG_SNTP 1 - -// BSD Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off BSD Interface debug messages -#define DBG_BSD 1 -// - -// Application Debug Definitions -// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Web Server debug messages -#define DBG_HTTP_SERVER 1 - -// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Server debug messages -#define DBG_FTP_SERVER 1 - -// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Client debug messages -#define DBG_FTP_CLIENT 1 - -// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Telnet Server debug messages -#define DBG_TELNET_SERVER 1 - -// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Server debug messages -#define DBG_TFTP_SERVER 1 - -// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Client debug messages -#define DBG_TFTP_CLIENT 1 - -// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SMTP Client debug messages -#define DBG_SMTP_CLIENT 1 -// - - -#include "net_debug.h" - - -/** - \fn void net_debug_init (void) - \brief Initialize Network Debug Interface. -*/ -void net_debug_init (void) { - /* Add your code to initialize the Debug output. This is usually the */ - /* serial interface. The function is called at TCPnet system startup. */ - /* You may need to customize also the 'putchar()' function. */ - -} diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/RTE_Components.h deleted file mode 100644 index 631a771434..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/RTE/RTE_Components.h +++ /dev/null @@ -1,28 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'EchoClient' - * Target: 'EchoClient' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ -#define RTE_Network_Core /* Network Core */ - #define RTE_Network_Debug /* Network Debug Version */ -#define RTE_Network_DNS_Client /* Network DNS Client */ -#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ -#define RTE_Network_Socket_BSD /* Network Socket BSD */ -#define RTE_Network_Socket_TCP /* Network Socket TCP */ -#define RTE_Network_Socket_UDP /* Network Socket UDP */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..22dea06d0e --- /dev/null +++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/wolfSSL/settings.h @@ -0,0 +1,627 @@ +/* settings.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#ifdef MICROCHIP_PIC32 + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #include "system/system_services.h" + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 +#endif /* MBED */ + +#ifdef CYASSL_TYTO + #include "rand.h" + #define FREERTOS + #define NO_FILESYSTEM + #define CYASSL_USER_IO + #define NO_DEV_RANDOM + #define HAVE_ECC + #define HAVE_ECC_ENCRYPT + #define ECC_SHAMIR + #define HAVE_HKDF + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FP_MAX_BITS 512 + #define NO_OLD_TLS + #define NO_MD4 + #define NO_RABBIT + #define NO_HC128 + #define NO_RSA + #define NO_DSA + #define NO_PWDBASED + #define NO_PSK +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/EchoClient/config-EchoClient.h b/IDE/MDK5-ARM/Projects/EchoClient/config-EchoClient.h new file mode 100644 index 0000000000..82f5d47828 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/EchoClient/config-EchoClient.h @@ -0,0 +1,34 @@ +/* config-RTX-TCP-FS.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + + +// <<< Use Configuration Wizard in Context Menu >>> +// Build Target: Simple Client +// Callee IP Address +// Default: "192.168.1.100" +#define CYASSL_CALLEE_IP "192.168.11.3" +// Callee Port Number +// Default: "11111" +#define CYASSL_CALLEE_PORT 443 + +// +// <<< end of configuration section >>> diff --git a/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c b/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c index 3793d6dd1c..24a02febc1 100644 --- a/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c +++ b/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c @@ -28,18 +28,18 @@ #include #if defined(CYASSL_MDK_ARM) - #include - #include - - #if defined(CYASSL_MDK5) - #include "cmsis_os.h" - #include "rl_fs.h" - #include "rl_net.h" - #else - #include "rtl.h" - #endif - - #include "cyassl_MDK_ARM.h" + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" #endif #include @@ -68,11 +68,11 @@ void echoclient_test(void* args) int sendSz; int argc = 0; char** argv = 0; - int port = yasslPort; + word16 port = yasslPort; ((func_args*)args)->return_code = -1; /* error state */ -#ifndef CYASSL_MDK_ARM +#ifndef CYASSL_MDK_SHELL argc = ((func_args*)args)->argc; argv = ((func_args*)args)->argv; #endif @@ -104,9 +104,6 @@ void echoclient_test(void* args) #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && !defined(CYASSL_MDK_SHELL) port = ((func_args*)args)->signal->port; #endif -#if defined (CYASSL_CALLEE_PORT) - port = CYASSL_CALLEE_PORT ; -#endif #if defined(CYASSL_DTLS) method = DTLSv1_client_method(); @@ -150,7 +147,7 @@ void echoclient_test(void* args) #endif } -#ifdef OPENSSL_EXTRA +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); #endif @@ -159,8 +156,8 @@ void echoclient_test(void* args) #endif ssl = SSL_new(ctx); - CyaSSL_set_quiet_shutdown(ssl, 1) ; - + + if (doDTLS) { SOCKADDR_IN_T addr; build_addr(&addr, yasslIP, port, 1); @@ -221,10 +218,6 @@ void echoclient_test(void* args) #endif } -#ifdef CYASSL_CMSIS_RTOS - osDelay(5000) ; -#endif - #ifdef CYASSL_DTLS strncpy(msg, "break", 6); @@ -270,8 +263,10 @@ void echoclient_test(void* args) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("echoclient") || CurrentDir("build")) + if (CurrentDir("echoclient")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); echoclient_test(&args); CyaSSL_Cleanup(); diff --git a/IDE/MDK5-ARM/Projects/EchoClient/main.c b/IDE/MDK5-ARM/Projects/EchoClient/main.c index ccfb92fc87..a2db99f5eb 100644 --- a/IDE/MDK5-ARM/Projects/EchoClient/main.c +++ b/IDE/MDK5-ARM/Projects/EchoClient/main.c @@ -86,7 +86,6 @@ char* myoptarg = NULL; int main() { void *args = NULL ; - init_time() ; init_filesystem (); net_initialize() ; osThreadCreate (osThread (tcp_poll), NULL); diff --git a/IDE/MDK5-ARM/Projects/EchoClient/time-dummy.c b/IDE/MDK5-ARM/Projects/EchoClient/time-dummy.c new file mode 100644 index 0000000000..2525eba38b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/EchoClient/time-dummy.c @@ -0,0 +1,34 @@ +/* time-dummy.c.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + return(&date) ; +} + +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt b/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt index d43c94a384..491c61020c 100644 --- a/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt @@ -1,7 +1,7 @@ This program is echo server with CyaSSL/wolfCrypt library. In order to run this program, -Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +Copy {PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. Set the server IP address in Net_Config_ETH_0.h The server default port is 11111, defined in test.h. diff --git a/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx index ba35f0f5cf..242215bf96 100644 --- a/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx +++ b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx @@ -76,6 +76,23 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL -REMAP -MPU @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,7 +135,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -207,10 +226,10 @@ 1 0 0 - 0 + 11 0 - 0 - 0 + 64 + 83 0 .\main.c main.c @@ -273,6 +292,22 @@ 0 0 + + 2 + 5 + 5 + 0 + 0 + 33 + 0 + 1 + 17 + 0 + .\RTE\Network\Net_Config_ETH_0.h + Net_Config_ETH_0.h + 0 + 0 + @@ -283,14 +318,14 @@ 0 3 - 5 + 6 5 0 0 0 0 - 1 - 1 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -300,27 +335,11 @@ - ::CMSIS - 0 + Devices + 1 0 0 - 1 - - 4 - 6 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib - RTX_CM3.lib - 1 - 0 - + 0 4 7 @@ -332,11 +351,51 @@ 0 0 0 + .\time-dummy.c + time-dummy.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + 5 + 8 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + 0 RTE\CMSIS\RTX_Conf_CM.c RTX_Conf_CM.c 1 0 + + 5 + 9 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + RTX_CM3.lib + 1 + 0 + @@ -346,39 +405,7 @@ 0 1 - 5 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 - 0 - - - 5 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c - 1 - 0 - - - 5 + 6 10 5 0 @@ -394,15 +421,15 @@ 0 - 5 + 6 11 2 0 0 0 0 - 0 - 0 + 162 + 169 0 RTE\Device\STM32F207IG\startup_stm32f2xx.s startup_stm32f2xx.s @@ -410,7 +437,7 @@ 0 - 5 + 6 12 1 0 @@ -425,14 +452,6 @@ 1 0 - - - - ::Drivers - 0 - 0 - 0 - 1 6 13 @@ -444,8 +463,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c - PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c 1 0 @@ -460,13 +479,21 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c - EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c 1 0 + + + + ::Drivers + 0 + 0 + 0 + 1 - 6 + 7 15 1 0 @@ -476,23 +503,15 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c - MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c + PHY_ST802RT1.c 1 0 - - - - ::File System - 0 - 0 - 0 - 1 7 16 - 4 + 1 0 0 0 @@ -500,8 +519,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c + EMAC_STM32F2xx.c 1 0 @@ -516,14 +535,38 @@ 0 0 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c + MCI_STM32F2xx.c + 1 + 0 + + + + + ::File System + 0 + 0 + 0 + 1 + + 8 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 RTE\File_System\FS_Config.c FS_Config.c 1 0 - 7 - 18 + 8 + 19 5 0 0 @@ -537,6 +580,22 @@ 1 0 + + 8 + 20 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib + 1 + 0 + @@ -546,24 +605,8 @@ 0 1 - 8 - 19 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Dbg_CM3_L.lib - 1 - 0 - - - 8 - 20 + 9 + 21 1 0 0 @@ -578,8 +621,8 @@ 0 - 8 - 21 + 9 + 22 5 0 0 @@ -594,8 +637,8 @@ 0 - 8 - 22 + 9 + 23 5 0 0 @@ -610,15 +653,15 @@ 0 - 8 - 23 + 9 + 24 5 0 0 - 0 + 33 0 - 0 - 0 + 1 + 17 0 RTE\Network\Net_Config_ETH_0.h Net_Config_ETH_0.h @@ -626,8 +669,8 @@ 0 - 8 - 24 + 9 + 25 5 0 0 @@ -642,8 +685,8 @@ 0 - 8 - 25 + 9 + 26 5 0 0 @@ -658,8 +701,8 @@ 0 - 8 - 26 + 9 + 27 1 0 0 @@ -673,689 +716,33 @@ 1 0 + + 9 + 28 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + Net_Dbg_CM3_L.lib + 1 + 0 + ::wolfSSL - 0 + 1 0 0 1 - 9 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 9 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 9 + 10 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 9 - 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - arc4.c - 1 - 0 - - - 9 - 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - asm.c - 1 - 0 - - - 9 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - asn.c - 1 - 0 - - - 9 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - blake2b.c - 1 - 0 - - - 9 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - camellia.c - 1 - 0 - - - 9 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - coding.c - 1 - 0 - - - 9 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - compress.c - 1 - 0 - - - 9 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - des3.c - 1 - 0 - - - 9 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - dh.c - 1 - 0 - - - 9 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - dsa.c - 1 - 0 - - - 9 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - ecc.c - 1 - 0 - - - 9 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c - 1 - 0 - - - 9 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - error.c - 1 - 0 - - - 9 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - hc128.c - 1 - 0 - - - 9 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - hmac.c - 1 - 0 - - - 9 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - integer.c - 1 - 0 - - - 9 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - logging.c - 1 - 0 - - - 9 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - md2.c - 1 - 0 - - - 9 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - md4.c - 1 - 0 - - - 9 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - md5.c - 1 - 0 - - - 9 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - memory.c - 1 - 0 - - - 9 - 51 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - misc.c - 1 - 0 - - - 9 - 52 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c - 1 - 0 - - - 9 - 53 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - rabbit.c - 1 - 0 - - - 9 - 54 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - random.c - 1 - 0 - - - 9 - 55 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - ripemd.c - 1 - 0 - - - 9 - 56 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - rsa.c - 1 - 0 - - - 9 - 57 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - sha.c - 1 - 0 - - - 9 - 58 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - sha256.c - 1 - 0 - - - 9 - 59 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - sha512.c - 1 - 0 - - - 9 - 60 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - tfm.c - 1 - 0 - - - 9 - 61 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - crl.c - 1 - 0 - - - 9 - 62 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - internal.c - 1 - 0 - - - 9 - 63 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - io.c - 1 - 0 - - - 9 - 64 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - keys.c - 1 - 0 - - - 9 - 65 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - ocsp.c - 1 - 0 - - - 9 - 66 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - sniffer.c - 1 - 0 - - - 9 - 67 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - ssl.c - 1 - 0 - - - 9 - 68 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - tls.c - 1 - 0 - - - 9 - 69 5 0 0 @@ -1370,8 +757,8 @@ 0 - 9 - 70 + 10 + 30 5 0 0 @@ -1386,8 +773,664 @@ 0 - 9 + 10 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c + 1 + 0 + + + 10 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c + 1 + 0 + + + 10 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c + 1 + 0 + + + 10 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c + 1 + 0 + + + 10 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c + 1 + 0 + + + 10 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c + 1 + 0 + + + 10 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c + 1 + 0 + + + 10 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c + 1 + 0 + + + 10 + 39 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c + 1 + 0 + + + 10 + 40 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c + 1 + 0 + + + 10 + 41 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c + 1 + 0 + + + 10 + 42 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c + 1 + 0 + + + 10 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c + 1 + 0 + + + 10 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c + 1 + 0 + + + 10 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c + 1 + 0 + + + 10 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c + 1 + 0 + + + 10 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c + 1 + 0 + + + 10 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c + 1 + 0 + + + 10 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c + 1 + 0 + + + 10 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c + 1 + 0 + + + 10 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c + 1 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c + 1 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c + 1 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c + 1 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + crl.c + 1 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + internal.c + 1 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + io.c + 1 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + keys.c + 1 + 0 + + + 10 + 68 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + ocsp.c + 1 + 0 + + + 10 + 69 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + sniffer.c + 1 + 0 + + + 10 + 70 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + ssl.c + 1 + 0 + + + 10 71 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c + tls.c + 1 + 0 + + + 10 + 72 5 0 0 @@ -1396,8 +1439,24 @@ 0 0 0 - RTE\wolfSSL\config.h - config.h + RTE\wolfSSL\settings.h + settings.h + 1 + 0 + + + 10 + 73 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx index b8ce12e1e6..0c2c836731 100644 --- a/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx +++ b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,9 +355,11 @@ 0 0 0 + 0 + 0 - HAVE_CONFIG_H MDK_CONF_SimpleClient CYASSL_STM32F2xx + HAVE_CONFIG_H MDK_CONF_SimpleClient @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -423,6 +429,11 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + Net_Config_ETH_0.h + 5 + .\RTE\Network\Net_Config_ETH_0.h + @@ -436,33 +447,33 @@ - ::CMSIS + Devices - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + time-dummy.c + 1 + .\time-dummy.c + + + + ::CMSIS + RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -478,6 +489,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -486,28 +507,23 @@ PHY_ST802RT1.c 1 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c EMAC_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -518,16 +534,16 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + ::Network - - Net_Dbg_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Config.c 1 @@ -563,221 +579,16 @@ 1 RTE\Network\Net_Debug.c + + Net_Dbg_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + ::wolfSSL - - cyassl_MDK_ARM.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - - - time-STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - - - aes.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - - - arc4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - - - asm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - - - asn.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - - - blake2b.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - - - camellia.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - - - coding.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - - - compress.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - - - des3.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - - - dh.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - - - dsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - - - ecc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - - - ecc_fp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - - - error.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - - - hc128.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - - - hmac.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - - - integer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - - - logging.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - - - md2.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - - - md4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - - - md5.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - - - memory.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - - - misc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - - - pwdbased.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - - - rabbit.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - - - random.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - - - ripemd.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - - - rsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - - - sha.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - - - sha256.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - - - sha512.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - - - tfm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - - - crl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - - - internal.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - - - io.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - - - keys.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - - - ocsp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - - - sniffer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - - - ssl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - - - tls.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - config-Crypt.h 5 @@ -789,9 +600,219 @@ RTE\wolfSSL\config-CyaSSL.h - config.h + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + + + crl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + + + internal.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + + + io.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + + + keys.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + + + ocsp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + + + sniffer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + + + ssl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + + + tls.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c + + + settings.h 5 - RTE\wolfSSL\config.h + RTE\wolfSSL\settings.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c @@ -833,20 +854,20 @@ - - + + - - + + - - + + @@ -923,20 +944,14 @@ - - + + - - - - - - - - + + @@ -945,8 +960,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -1073,24 +1088,30 @@ RTE\wolfSSL\config-Crypt.h - - + + RTE\wolfSSL\config-CyaSSL.h - - + + - RTE\wolfSSL\config.h - - + RTE\wolfSSL\config.h + + + + + + RTE\wolfSSL\settings.h + + diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index 54b3e0bfc3..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 5 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 250 -#endif - -// Main Thread stack size [bytes] <64-20000:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 2000 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 2 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 2500 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-64000:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 4a09246f38..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 1 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index c4e2ab9fa8..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00002000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00007000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config.c deleted file mode 100644 index 6b9dc8e00d..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config.c +++ /dev/null @@ -1,153 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Definitions -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "my_host" - -// Memory Pool size <1536-262144:4><#/4> -// This is the size of a memory pool in bytes. Buffers for -// Network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_SIZE 3000 - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP_0 -#include "Net_Config_PPP_0.h" -#endif -#ifdef RTE_Network_Interface_PPP_1 -#include "Net_Config_PPP_1.h" -#endif - -#ifdef RTE_Network_Interface_SLIP_0 -#include "Net_Config_SLIP_0.h" -#endif -#ifdef RTE_Network_Interface_SLIP_1 -#include "Net_Config_SLIP_1.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (ERROR_CODE error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (ERROR_CODE error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case ERR_MEM_ALLOC: - /* Out of memory */ - break; - - case ERR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case ERR_MEM_CORRUPT: - /* Memory Link pointer Corrupted */ - /* More data written than the size of allocated mem block */ - break; - - case ERR_MEM_LOCK: - /* Locked Memory management function (alloc/free) re-entered */ - break; - - case ERR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case ERR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case ERR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index 4166a0a2d1..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,36 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration BSD Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 15 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 1 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_DNS_Client.h deleted file mode 100644 index d30b718079..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_DNS_Client.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_DNS_Client.h - * Purpose: Network Configuration DNS Client - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// DNS Client -#define DNS_CLIENT_ENABLE 1 - -// Cache Table size <5-100> -// Number of cached DNS host names/IP addresses -// Default: 20 -#define DNS_CLIENT_TAB_SIZE 20 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index 9a49f38210..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,222 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration ETH Interface - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 1 - -// MAC Address -// Local Ethernet MAC Address -// Value FF:FF:FF:FF:FF:FF is not allowed. -// It is an ethernet Broadcast MAC address. -// Address byte 1 <0x00-0xff:2> -// LSB is an ethernet Multicast bit. -// Must be 0 for local MAC address. -// Default: 0x1E -#define ETH0_MAC1 0x1E - -// Address byte 2 <0x00-0xff> -// Default: 0x30 -#define ETH0_MAC2 0x30 - -// Address byte 3 <0x00-0xff> -// Default: 0x6C -#define ETH0_MAC3 0x6C - -// Address byte 4 <0x00-0xff> -// Default: 0xA2 -#define ETH0_MAC4 0xA2 - -// Address byte 5 <0x00-0xff> -// Default: 0x45 -#define ETH0_MAC5 0x45 - -// Address byte 6 <0x00-0xff> -// Default: 0x5E -#define ETH0_MAC6 0x5E -// - -// IP Address -// Local Static IP Address -// Value 255.255.255.255 is not allowed. -// It is a Broadcast IP address. -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_IP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_IP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_IP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define ETH0_IP4 100 -// - -// Subnet mask -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define ETH0_MASK1 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define ETH0_MASK2 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define ETH0_MASK3 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define ETH0_MASK4 0 -// - -// Default Gateway -// Default Gateway IP Address -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_GW1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_GW2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_GW3 0 - -// Address byte 4 <0-255> -// Default: 254 -#define ETH0_GW4 254 -// - -// Primary DNS Server -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_PRI_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_PRI_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_PRI_DNS3 2 - -// Address byte 4 <0-255> -// Default: 129 -#define ETH0_PRI_DNS4 129 -// - -// Secondary DNS Server -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_SEC_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_SEC_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_SEC_DNS3 2 - -// Address byte 4 <0-255> -// Default: 130 -#define ETH0_SEC_DNS4 130 -// - -// ARP Definitions -// Address Resolution Protocol Definitions -// Cache Table size <5-100> -// Number of cached hardware/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for a cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by his name on the local LAN using NBNS protocol. -// You need to modify also the number of UDP Sockets, -// because NBNS protocol uses one UDP socket to run. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -// You need to modify also the number of UDP Sockets, -// because DHCP protocol uses one UDP socket to run. -#define ETH0_DHCP_ENABLE 0 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// - -// diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index 9d5b419e48..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,61 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration TCP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 5 -#define TCP_NUM_SOCKS 15 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low_throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-600> -// Default TCP Socket Keep Alive timeout. When it expires -// with no TCP data frame send, TCP Connection is closed. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1460> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1460 -#define TCP_MAX_SEG_SIZE 1460 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4380 -#define TCP_RECEIVE_WIN_SIZE 4380 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index 113f314a9e..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration UDP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 20 - -// diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Debug.c deleted file mode 100644 index 735089a409..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Debug.c +++ /dev/null @@ -1,125 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Debug.c - * Purpose: Network Debug Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Print Time Stamp -// Enable printing the time-info in debug messages -#define DBG_TIME 1 - -// TCPnet Debug Definitions -// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Memory debug messages -#define DBG_MEM 1 - -// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Ethernet debug messages -#define DBG_ETH 0 - -// PPP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off PPP debug messages -#define DBG_PPP 0 - -// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SLIP debug messages -#define DBG_SLIP 0 - -// ARP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ARP debug messages -#define DBG_ARP 0 - -// IP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IP debug messages -#define DBG_IP 1 - -// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ICMP debug messages -#define DBG_ICMP 1 - -// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IGMP debug messages -#define DBG_IGMP 1 - -// UDP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off UDP debug messages -#define DBG_UDP 1 - -// TCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TCP debug messages -#define DBG_TCP 1 - -// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off NetBIOS Name Service debug messages -#define DBG_NBNS 1 - -// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Host Configuration debug messages -#define DBG_DHCP 1 - -// DNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Domain Name Service debug messages -#define DBG_DNS 1 - -// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Management debug messages -#define DBG_SNMP 1 - -// SNTP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Time debug messages -#define DBG_SNTP 1 - -// BSD Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off BSD Interface debug messages -#define DBG_BSD 1 -// - -// Application Debug Definitions -// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Web Server debug messages -#define DBG_HTTP_SERVER 1 - -// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Server debug messages -#define DBG_FTP_SERVER 1 - -// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Client debug messages -#define DBG_FTP_CLIENT 1 - -// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Telnet Server debug messages -#define DBG_TELNET_SERVER 1 - -// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Server debug messages -#define DBG_TFTP_SERVER 1 - -// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Client debug messages -#define DBG_TFTP_CLIENT 1 - -// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SMTP Client debug messages -#define DBG_SMTP_CLIENT 1 -// - - -#include "net_debug.h" - - -/** - \fn void net_debug_init (void) - \brief Initialize Network Debug Interface. -*/ -void net_debug_init (void) { - /* Add your code to initialize the Debug output. This is usually the */ - /* serial interface. The function is called at TCPnet system startup. */ - /* You may need to customize also the 'putchar()' function. */ - -} diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/RTE_Components.h deleted file mode 100644 index 20773df02f..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/RTE/RTE_Components.h +++ /dev/null @@ -1,28 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'EchoServer' - * Target: 'EchoServer' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ -#define RTE_Network_Core /* Network Core */ - #define RTE_Network_Debug /* Network Debug Version */ -#define RTE_Network_DNS_Client /* Network DNS Client */ -#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ -#define RTE_Network_Socket_BSD /* Network Socket BSD */ -#define RTE_Network_Socket_TCP /* Network Socket TCP */ -#define RTE_Network_Socket_UDP /* Network Socket UDP */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..22dea06d0e --- /dev/null +++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/wolfSSL/settings.h @@ -0,0 +1,627 @@ +/* settings.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#ifdef MICROCHIP_PIC32 + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #include "system/system_services.h" + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 +#endif /* MBED */ + +#ifdef CYASSL_TYTO + #include "rand.h" + #define FREERTOS + #define NO_FILESYSTEM + #define CYASSL_USER_IO + #define NO_DEV_RANDOM + #define HAVE_ECC + #define HAVE_ECC_ENCRYPT + #define ECC_SHAMIR + #define HAVE_HKDF + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FP_MAX_BITS 512 + #define NO_OLD_TLS + #define NO_MD4 + #define NO_RABBIT + #define NO_HC128 + #define NO_RSA + #define NO_DSA + #define NO_PWDBASED + #define NO_PSK +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c b/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c index 132e4c6d7a..33f6df3df0 100644 --- a/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c +++ b/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c @@ -26,18 +26,18 @@ #include #if defined(CYASSL_MDK_ARM) - #include - #include + #include + #include - #if defined(CYASSL_MDK5) - #include "cmsis_os.h" - #include "rl_fs.h" - #include "rl_net.h" - #else - #include "rtl.h" - #endif + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif - #include "cyassl_MDK_ARM.h" + #include "cyassl_MDK_ARM.h" #endif #include @@ -56,7 +56,7 @@ #define SVR_COMMAND_SIZE 256 -static void SignalReady(void* args, int port) +static void SignalReady(void* args, word16 port) { #if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__) /* signal ready to tcp_accept */ @@ -84,7 +84,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) int outCreated = 0; int shutDown = 0; int useAnyAddr = 0; - int port = yasslPort; + word16 port = yasslPort; int argc = ((func_args*)args)->argc; char** argv = ((func_args*)args)->argv; @@ -115,7 +115,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) #endif #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \ - !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_ARM) + !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_SHELL) port = 0; #endif #if defined(USE_ANY_ADDR) @@ -133,7 +133,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) ctx = CyaSSL_CTX_new(method); /* CyaSSL_CTX_set_session_cache_mode(ctx, SSL_SESS_CACHE_OFF); */ -#ifdef OPENSSL_EXTRA +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); #endif @@ -226,8 +226,6 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) ssl = CyaSSL_new(ctx); if (ssl == NULL) err_sys("SSL_new failed"); - CyaSSL_set_quiet_shutdown(ssl, 1) ; - CyaSSL_set_fd(ssl, clientfd); #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA) CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM); @@ -313,9 +311,7 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) SignalReady(args, port); #endif } -#ifdef CYASSL_CMSIS_RTOS - osDelay(5000) ; -#endif + CloseSocket(sockfd); CyaSSL_CTX_free(ctx); @@ -351,8 +347,10 @@ THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) #if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("echoserver") || CurrentDir("build")) + if (CurrentDir("echoserver")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); echoserver_test(&args); CyaSSL_Cleanup(); diff --git a/IDE/MDK5-ARM/Projects/EchoServer/main.c b/IDE/MDK5-ARM/Projects/EchoServer/main.c index 3947b13a44..810fdbb2ba 100644 --- a/IDE/MDK5-ARM/Projects/EchoServer/main.c +++ b/IDE/MDK5-ARM/Projects/EchoServer/main.c @@ -83,7 +83,6 @@ char* myoptarg = NULL; int main() { void *args = NULL ; - init_time() ; init_filesystem (); net_initialize() ; osThreadCreate (osThread (tcp_poll), NULL); diff --git a/IDE/MDK5-ARM/Projects/EchoServer/time-dummy.c b/IDE/MDK5-ARM/Projects/EchoServer/time-dummy.c new file mode 100644 index 0000000000..2525eba38b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/EchoServer/time-dummy.c @@ -0,0 +1,34 @@ +/* time-dummy.c.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + return(&date) ; +} + +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt b/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt index 39ab9e9eff..1a9a172c9b 100644 --- a/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt @@ -1,10 +1,11 @@ This program is a simple client example with CyaSSL/wolfCrypt library. In order to run this program, -Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +Copy {PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. Set config-SimpleClient.h configuration file for the Callee IP or Port number. For further configuration, refer config-Crypt.h and config-CyaSSL.h. +config-SimpleClient.h is to configure repote callee IP and port. When testing this client, it is recommended to test against one of the standard CyaSSL example applications running on a desktop machine. The standard CyaSSL diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index 54b3e0bfc3..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 5 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 250 -#endif - -// Main Thread stack size [bytes] <64-20000:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 2000 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 2 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 2500 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-64000:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 4a09246f38..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 1 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index d398143ef3..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x00007000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config.c deleted file mode 100644 index 6b9dc8e00d..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config.c +++ /dev/null @@ -1,153 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Definitions -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "my_host" - -// Memory Pool size <1536-262144:4><#/4> -// This is the size of a memory pool in bytes. Buffers for -// Network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_SIZE 3000 - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP_0 -#include "Net_Config_PPP_0.h" -#endif -#ifdef RTE_Network_Interface_PPP_1 -#include "Net_Config_PPP_1.h" -#endif - -#ifdef RTE_Network_Interface_SLIP_0 -#include "Net_Config_SLIP_0.h" -#endif -#ifdef RTE_Network_Interface_SLIP_1 -#include "Net_Config_SLIP_1.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (ERROR_CODE error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (ERROR_CODE error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case ERR_MEM_ALLOC: - /* Out of memory */ - break; - - case ERR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case ERR_MEM_CORRUPT: - /* Memory Link pointer Corrupted */ - /* More data written than the size of allocated mem block */ - break; - - case ERR_MEM_LOCK: - /* Locked Memory management function (alloc/free) re-entered */ - break; - - case ERR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case ERR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case ERR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index d7e6a614ae..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,36 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration BSD Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 7 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 1 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_DNS_Client.h deleted file mode 100644 index d30b718079..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_DNS_Client.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_DNS_Client.h - * Purpose: Network Configuration DNS Client - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// DNS Client -#define DNS_CLIENT_ENABLE 1 - -// Cache Table size <5-100> -// Number of cached DNS host names/IP addresses -// Default: 20 -#define DNS_CLIENT_TAB_SIZE 20 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index 7be57ad6d5..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,222 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration ETH Interface - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 1 - -// MAC Address -// Local Ethernet MAC Address -// Value FF:FF:FF:FF:FF:FF is not allowed. -// It is an ethernet Broadcast MAC address. -// Address byte 1 <0x00-0xff:2> -// LSB is an ethernet Multicast bit. -// Must be 0 for local MAC address. -// Default: 0x1E -#define ETH0_MAC1 0x1E - -// Address byte 2 <0x00-0xff> -// Default: 0x30 -#define ETH0_MAC2 0x30 - -// Address byte 3 <0x00-0xff> -// Default: 0x6C -#define ETH0_MAC3 0x6C - -// Address byte 4 <0x00-0xff> -// Default: 0xA2 -#define ETH0_MAC4 0xA2 - -// Address byte 5 <0x00-0xff> -// Default: 0x45 -#define ETH0_MAC5 0x45 - -// Address byte 6 <0x00-0xff> -// Default: 0x5E -#define ETH0_MAC6 0x5E -// - -// IP Address -// Local Static IP Address -// Value 255.255.255.255 is not allowed. -// It is a Broadcast IP address. -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_IP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_IP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_IP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define ETH0_IP4 100 -// - -// Subnet mask -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define ETH0_MASK1 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define ETH0_MASK2 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define ETH0_MASK3 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define ETH0_MASK4 0 -// - -// Default Gateway -// Default Gateway IP Address -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_GW1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_GW2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_GW3 0 - -// Address byte 4 <0-255> -// Default: 254 -#define ETH0_GW4 254 -// - -// Primary DNS Server -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_PRI_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_PRI_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_PRI_DNS3 2 - -// Address byte 4 <0-255> -// Default: 129 -#define ETH0_PRI_DNS4 129 -// - -// Secondary DNS Server -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_SEC_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_SEC_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_SEC_DNS3 2 - -// Address byte 4 <0-255> -// Default: 130 -#define ETH0_SEC_DNS4 130 -// - -// ARP Definitions -// Address Resolution Protocol Definitions -// Cache Table size <5-100> -// Number of cached hardware/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for a cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by his name on the local LAN using NBNS protocol. -// You need to modify also the number of UDP Sockets, -// because NBNS protocol uses one UDP socket to run. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -// You need to modify also the number of UDP Sockets, -// because DHCP protocol uses one UDP socket to run. -#define ETH0_DHCP_ENABLE 1 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index e659ce9211..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,61 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration TCP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 5 -#define TCP_NUM_SOCKS 10 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low_throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-600> -// Default TCP Socket Keep Alive timeout. When it expires -// with no TCP data frame send, TCP Connection is closed. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1460> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1460 -#define TCP_MAX_SEG_SIZE 1460 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4380 -#define TCP_RECEIVE_WIN_SIZE 4380 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index b7995c22de..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration UDP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 10 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Debug.c deleted file mode 100644 index 735089a409..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Debug.c +++ /dev/null @@ -1,125 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Debug.c - * Purpose: Network Debug Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Print Time Stamp -// Enable printing the time-info in debug messages -#define DBG_TIME 1 - -// TCPnet Debug Definitions -// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Memory debug messages -#define DBG_MEM 1 - -// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Ethernet debug messages -#define DBG_ETH 0 - -// PPP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off PPP debug messages -#define DBG_PPP 0 - -// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SLIP debug messages -#define DBG_SLIP 0 - -// ARP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ARP debug messages -#define DBG_ARP 0 - -// IP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IP debug messages -#define DBG_IP 1 - -// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ICMP debug messages -#define DBG_ICMP 1 - -// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IGMP debug messages -#define DBG_IGMP 1 - -// UDP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off UDP debug messages -#define DBG_UDP 1 - -// TCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TCP debug messages -#define DBG_TCP 1 - -// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off NetBIOS Name Service debug messages -#define DBG_NBNS 1 - -// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Host Configuration debug messages -#define DBG_DHCP 1 - -// DNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Domain Name Service debug messages -#define DBG_DNS 1 - -// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Management debug messages -#define DBG_SNMP 1 - -// SNTP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Time debug messages -#define DBG_SNTP 1 - -// BSD Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off BSD Interface debug messages -#define DBG_BSD 1 -// - -// Application Debug Definitions -// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Web Server debug messages -#define DBG_HTTP_SERVER 1 - -// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Server debug messages -#define DBG_FTP_SERVER 1 - -// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Client debug messages -#define DBG_FTP_CLIENT 1 - -// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Telnet Server debug messages -#define DBG_TELNET_SERVER 1 - -// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Server debug messages -#define DBG_TFTP_SERVER 1 - -// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Client debug messages -#define DBG_TFTP_CLIENT 1 - -// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SMTP Client debug messages -#define DBG_SMTP_CLIENT 1 -// - - -#include "net_debug.h" - - -/** - \fn void net_debug_init (void) - \brief Initialize Network Debug Interface. -*/ -void net_debug_init (void) { - /* Add your code to initialize the Debug output. This is usually the */ - /* serial interface. The function is called at TCPnet system startup. */ - /* You may need to customize also the 'putchar()' function. */ - -} diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/RTE_Components.h deleted file mode 100644 index 938bd18ea2..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/RTE_Components.h +++ /dev/null @@ -1,28 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'simpleClient' - * Target: 'SimpleClient' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ -#define RTE_Network_Core /* Network Core */ - #define RTE_Network_Debug /* Network Debug Version */ -#define RTE_Network_DNS_Client /* Network DNS Client */ -#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ -#define RTE_Network_Socket_BSD /* Network Socket BSD */ -#define RTE_Network_Socket_TCP /* Network Socket TCP */ -#define RTE_Network_Socket_UDP /* Network Socket UDP */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..33d41cfdbe --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/wolfSSL/settings.h @@ -0,0 +1,667 @@ +/* settings.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using PIC32MZ Crypto Engine */ +/* #define CYASSL_MICROCHIP_PIC32MZ */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + +/* Uncomment next line if using LwIP native TCP socket settings */ +/* #define HAVE_LWIP_NATIVE */ + +/* Uncomment next line if building for EROAD */ +/* #define CYASSL_EROAD */ + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef CYASSL_USER_SETTINGS + #include +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */ + #define CYASSL_LWIP + #define NO_WRITEV + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_FILESYSTEM +#endif + +#ifdef MICROCHIP_PIC32 + /* #define CYASSL_MICROCHIP_PIC32MZ */ + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef CYASSL_MICROCHIP_PIC32MZ + #define CYASSL_PIC32MZ_CE + #define CYASSL_PIC32MZ_CRYPT + #define HAVE_AES_ENGINE + #define CYASSL_PIC32MZ_RNG + /* #define CYASSL_PIC32MZ_HASH */ + #define CYASSL_AES_COUNTER + #define HAVE_AESGCM + #define NO_BIG_INT + +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "system/system_services.h" + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define CYASSL_USER_IO + #define NO_FILESYSTEM + #define NO_CERT + #define USE_CERT_BUFFERS_1024 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define HAVE_ECC + #define NO_SESSION_CACHE + #define CYASSL_CMSIS_RTOS +#endif + + +#ifdef CYASSL_EROAD + #define FREESCALE_MQX + #define FREESCALE_MMCAU + #define SINGLE_THREADED + #define NO_STDIO_FILESYSTEM + #define CYASSL_LEANPSK + #define HAVE_NULL_CIPHER + #define NO_OLD_TLS + #define NO_ASN + #define NO_BIG_INT + #define NO_RSA + #define NO_DSA + #define NO_DH + #define NO_CERTS + #define NO_PWDBASED + #define NO_DES3 + #define NO_MD4 + #define NO_RC4 + #define NO_MD5 + #define NO_SESSION_CACHE + #define NO_MAIN_DRIVER +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) && !defined(CYASSL_EROAD) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/SimpleClient/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleClient/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx b/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx index 93fced476b..bdd17d7985 100644 --- a/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx +++ b/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx @@ -76,6 +76,23 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL -REMAP -MPU @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,7 +135,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -207,10 +226,10 @@ 1 0 0 - 0 + 43 0 - 0 - 0 + 18 + 73 0 .\main.c main.c @@ -289,6 +308,22 @@ 0 0 + + 2 + 6 + 5 + 0 + 0 + 33 + 0 + 0 + 0 + 0 + .\RTE\Network\Net_Config_ETH_0.h + Net_Config_ETH_0.h + 0 + 0 + @@ -299,14 +334,14 @@ 0 3 - 6 + 7 5 0 0 0 0 - 1 - 1 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -316,15 +351,15 @@ - ::CMSIS - 0 + Devices + 1 0 0 - 1 + 0 4 - 7 - 4 + 8 + 1 0 0 0 @@ -332,14 +367,38 @@ 0 0 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib - RTX_CM3.lib - 1 + .\time-dummy.c + time-dummy.c + 0 0 4 - 8 + 9 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\time-CortexM3-4.c + time-CortexM3-4.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + 5 + 10 1 0 0 @@ -353,6 +412,22 @@ 1 0 + + 5 + 11 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + RTX_CM3.lib + 1 + 0 + @@ -362,40 +437,8 @@ 0 1 - 5 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 - 0 - - - 5 - 10 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c - 1 - 0 - - - 5 - 11 + 6 + 12 5 0 0 @@ -410,8 +453,8 @@ 0 - 5 - 12 + 6 + 13 2 0 0 @@ -425,30 +468,6 @@ 1 0 - - 5 - 13 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RTE\Device\STM32F207IG\system_stm32f2xx.c - system_stm32f2xx.c - 1 - 0 - - - - - ::Drivers - 0 - 0 - 0 - 1 6 14 @@ -460,8 +479,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c - PHY_ST802RT1.c + RTE\Device\STM32F207IG\system_stm32f2xx.c + system_stm32f2xx.c 1 0 @@ -476,8 +495,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c - EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c 1 0 @@ -492,15 +511,15 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c - MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c 1 0 - ::File System + ::Drivers 0 0 0 @@ -508,7 +527,7 @@ 7 17 - 4 + 1 0 0 0 @@ -516,8 +535,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c + PHY_ST802RT1.c 1 0 @@ -532,14 +551,54 @@ 0 0 0 - RTE\File_System\FS_Config.c - FS_Config.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c + EMAC_STM32F2xx.c 1 0 7 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c + MCI_STM32F2xx.c + 1 + 0 + + + + + ::File System + 0 + 0 + 0 + 1 + + 8 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + RTE\File_System\FS_Config.c + FS_Config.c + 1 + 0 + + + 8 + 21 5 0 0 @@ -553,6 +612,22 @@ 1 0 + + 8 + 22 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib + 1 + 0 + @@ -562,24 +637,8 @@ 0 1 - 8 - 20 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Dbg_CM3_L.lib - 1 - 0 - - - 8 - 21 + 9 + 23 1 0 0 @@ -594,8 +653,8 @@ 0 - 8 - 22 + 9 + 24 5 0 0 @@ -610,8 +669,8 @@ 0 - 8 - 23 + 9 + 25 5 0 0 @@ -626,12 +685,12 @@ 0 - 8 - 24 + 9 + 26 5 0 0 - 0 + 33 0 0 0 @@ -642,8 +701,8 @@ 0 - 8 - 25 + 9 + 27 5 0 0 @@ -658,8 +717,8 @@ 0 - 8 - 26 + 9 + 28 5 0 0 @@ -674,8 +733,8 @@ 0 - 8 - 27 + 9 + 29 1 0 0 @@ -689,689 +748,33 @@ 1 0 + + 9 + 30 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + Net_Dbg_CM3_L.lib + 1 + 0 + ::wolfSSL - 0 + 1 0 0 1 - 9 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 9 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 9 - 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 9 + 10 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - arc4.c - 1 - 0 - - - 9 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - asm.c - 1 - 0 - - - 9 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - asn.c - 1 - 0 - - - 9 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - blake2b.c - 1 - 0 - - - 9 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - camellia.c - 1 - 0 - - - 9 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - coding.c - 1 - 0 - - - 9 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - compress.c - 1 - 0 - - - 9 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - des3.c - 1 - 0 - - - 9 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - dh.c - 1 - 0 - - - 9 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - dsa.c - 1 - 0 - - - 9 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - ecc.c - 1 - 0 - - - 9 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c - 1 - 0 - - - 9 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - error.c - 1 - 0 - - - 9 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - hc128.c - 1 - 0 - - - 9 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - hmac.c - 1 - 0 - - - 9 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - integer.c - 1 - 0 - - - 9 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - logging.c - 1 - 0 - - - 9 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - md2.c - 1 - 0 - - - 9 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - md4.c - 1 - 0 - - - 9 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - md5.c - 1 - 0 - - - 9 - 51 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - memory.c - 1 - 0 - - - 9 - 52 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - misc.c - 1 - 0 - - - 9 - 53 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c - 1 - 0 - - - 9 - 54 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - rabbit.c - 1 - 0 - - - 9 - 55 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - random.c - 1 - 0 - - - 9 - 56 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - ripemd.c - 1 - 0 - - - 9 - 57 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - rsa.c - 1 - 0 - - - 9 - 58 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - sha.c - 1 - 0 - - - 9 - 59 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - sha256.c - 1 - 0 - - - 9 - 60 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - sha512.c - 1 - 0 - - - 9 - 61 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - tfm.c - 1 - 0 - - - 9 - 62 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - crl.c - 1 - 0 - - - 9 - 63 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - internal.c - 1 - 0 - - - 9 - 64 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - io.c - 1 - 0 - - - 9 - 65 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - keys.c - 1 - 0 - - - 9 - 66 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - ocsp.c - 1 - 0 - - - 9 - 67 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - sniffer.c - 1 - 0 - - - 9 - 68 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - ssl.c - 1 - 0 - - - 9 - 69 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - tls.c - 1 - 0 - - - 9 - 70 5 0 0 @@ -1386,8 +789,8 @@ 0 - 9 - 71 + 10 + 32 5 0 0 @@ -1402,8 +805,8 @@ 0 - 9 - 72 + 10 + 33 5 0 0 @@ -1412,8 +815,680 @@ 0 0 0 - RTE\wolfSSL\config.h - config.h + RTE\wolfSSL\settings.h + settings.h + 1 + 0 + + + 10 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c + 1 + 0 + + + 10 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c + 1 + 0 + + + 10 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c + 1 + 0 + + + 10 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c + 1 + 0 + + + 10 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c + 1 + 0 + + + 10 + 39 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c + 1 + 0 + + + 10 + 40 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c + 1 + 0 + + + 10 + 41 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c + 1 + 0 + + + 10 + 42 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c + 1 + 0 + + + 10 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c + 1 + 0 + + + 10 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c + 1 + 0 + + + 10 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c + 1 + 0 + + + 10 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c + 1 + 0 + + + 10 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c + 1 + 0 + + + 10 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c + 1 + 0 + + + 10 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c + 1 + 0 + + + 10 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c + 1 + 0 + + + 10 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c + 1 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c + 1 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c + 1 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c + 1 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c + 1 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c + 1 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c + 1 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c + 1 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 10 + 68 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + crl.c + 1 + 0 + + + 10 + 69 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + internal.c + 1 + 0 + + + 10 + 70 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + io.c + 1 + 0 + + + 10 + 71 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + keys.c + 1 + 0 + + + 10 + 72 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + ocsp.c + 1 + 0 + + + 10 + 73 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + sniffer.c + 1 + 0 + + + 10 + 74 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + ssl.c + 1 + 0 + + + 10 + 75 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c + tls.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/client.c b/IDE/MDK5-ARM/Projects/SimpleClient/client.c index 1d1720dc61..113bed9f6d 100644 --- a/IDE/MDK5-ARM/Projects/SimpleClient/client.c +++ b/IDE/MDK5-ARM/Projects/SimpleClient/client.c @@ -22,7 +22,7 @@ #ifdef HAVE_CONFIG_H #include #endif - #define CYASSL_MDK_ARM + #if defined(CYASSL_MDK_ARM) #include #include @@ -46,11 +46,11 @@ #endif #include + #include #include "examples/client/client.h" -#define USE_CYASSL_MEMORY #ifdef CYASSL_CALLBACKS int handShakeCB(HandShakeInfo*); @@ -139,18 +139,27 @@ static void Usage(void) #ifdef SHOW_SIZES printf("-z Print structure sizes\n"); #endif +#ifdef HAVE_SNI printf("-S Use Host Name Indication\n"); +#endif +#ifdef HAVE_MAX_FRAGMENT + printf("-L Use Maximum Fragment Length [1-5]\n"); +#endif +#ifdef HAVE_TRUNCATED_HMAC + printf("-T Use Truncated HMAC\n"); +#endif +#ifdef HAVE_OCSP + printf("-o Perform OCSP lookup on peer certificate\n"); + printf("-O Perform OCSP lookup using as responder\n"); +#endif +#ifdef ATOMIC_USER + printf("-U Atomic User Record Layer Callbacks\n"); +#endif +#ifdef HAVE_PK_CALLBACKS + printf("-P Public Key Callbacks\n"); +#endif } -#ifdef CYASSL_MDK_SHELL -#define exit(code) return(code) -#endif - -#ifdef CYASSL_MDK_SHELL - #define exit(code) return(code) -#endif - - THREAD_RETURN CYASSL_THREAD client_test(void* args) { SOCKET_T sockfd = 0; @@ -169,7 +178,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) int input; int msgSz = (int)strlen(msg); - int port = yasslPort; + word16 port = yasslPort; char* host = (char*)yasslIP; char* domain = (char*)"www.yassl.com"; @@ -186,6 +195,8 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) int trackMemory = 0; int useClientCert = 1; int fewerPackets = 0; + int atomicUser = 0; + int pkCallbacks = 0; char* cipherList = NULL; char* verifyCert = (char*)caCert; char* ourCert = (char*)cliCert; @@ -194,6 +205,18 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) #ifdef HAVE_SNI char* sniHostName = NULL; #endif +#ifdef HAVE_MAX_FRAGMENT + byte maxFragment = 0; +#endif +#ifdef HAVE_TRUNCATED_HMAC + byte truncatedHMAC = 0; +#endif + + +#ifdef HAVE_OCSP + int useOcsp = 0; + char* ocspUrl = NULL; +#endif int argc = ((func_args*)args)->argc; char** argv = ((func_args*)args)->argv; @@ -209,8 +232,13 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) (void)session; (void)sslResume; (void)trackMemory; + (void)atomicUser; + (void)pkCallbacks; - while ((ch = mygetopt(argc, argv, "?gdusmNrtfxh:p:v:l:A:c:k:b:zS:")) != -1){ + StackTrap(); + + while ((ch = mygetopt(argc, argv, + "?gdusmNrtfxUPh:p:v:l:A:c:k:b:zS:L:ToO:")) != -1) { switch (ch) { case '?' : Usage(); @@ -250,13 +278,25 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) fewerPackets = 1; break; + case 'U' : + #ifdef ATOMIC_USER + atomicUser = 1; + #endif + break; + + case 'P' : + #ifdef HAVE_PK_CALLBACKS + pkCallbacks = 1; + #endif + break; + case 'h' : host = myoptarg; domain = myoptarg; break; case 'p' : - port = atoi(myoptarg); + port = (word16)atoi(myoptarg); #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API) if (port == 0) err_sys("port number cannot be 0"); @@ -315,6 +355,36 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) #endif break; + case 'L' : + #ifdef HAVE_MAX_FRAGMENT + maxFragment = atoi(myoptarg); + if (maxFragment < CYASSL_MFL_2_9 || + maxFragment > CYASSL_MFL_2_13) { + Usage(); + exit(MY_EX_USAGE); + } + #endif + break; + + case 'T' : + #ifdef HAVE_TRUNCATED_HMAC + truncatedHMAC = 1; + #endif + break; + + case 'o' : + #ifdef HAVE_OCSP + useOcsp = 1; + #endif + break; + + case 'O' : + #ifdef HAVE_OCSP + useOcsp = 1; + ocspUrl = myoptarg; + #endif + break; + default: Usage(); exit(MY_EX_USAGE); @@ -390,7 +460,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) ctx = CyaSSL_CTX_new(method); if (ctx == NULL) err_sys("unable to get ctx"); - + if (cipherList) if (CyaSSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS) err_sys("client can't set cipher list 1"); @@ -423,7 +493,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) useClientCert = 0; } -#ifdef OPENSSL_EXTRA +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); #endif @@ -436,6 +506,18 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) } #endif +#ifdef HAVE_OCSP + if (useOcsp) { + if (ocspUrl != NULL) { + CyaSSL_CTX_SetOCSP_OverrideURL(ctx, ocspUrl); + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE + | CYASSL_OCSP_URL_OVERRIDE); + } + else + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE); + } +#endif + #ifdef USER_CA_CB CyaSSL_CTX_SetCACb(ctx, CaCb); #endif @@ -475,6 +557,16 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) != SSL_SUCCESS) err_sys("UseSNI failed"); #endif +#ifdef HAVE_MAX_FRAGMENT + if (maxFragment) + if (CyaSSL_CTX_UseMaxFragment(ctx, maxFragment) != SSL_SUCCESS) + err_sys("UseMaxFragment failed"); +#endif +#ifdef HAVE_TRUNCATED_HMAC + if (truncatedHMAC) + if (CyaSSL_CTX_UseTruncatedHMAC(ctx) != SSL_SUCCESS) + err_sys("UseTruncatedHMAC failed"); +#endif if (benchmark) { /* time passed in number of connects give average */ @@ -513,9 +605,6 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) ssl = CyaSSL_new(ctx); if (ssl == NULL) err_sys("unable to get SSL object"); - - CyaSSL_set_quiet_shutdown(ssl, 1) ; - if (doDTLS) { SOCKADDR_IN_T addr; build_addr(&addr, host, port, 1); @@ -533,6 +622,14 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) err_sys("can't load crl, check crlfile and date validity"); if (CyaSSL_SetCRL_Cb(ssl, CRL_CallBack) != SSL_SUCCESS) err_sys("can't set crl callback"); +#endif +#ifdef ATOMIC_USER + if (atomicUser) + SetupAtomicUser(ctx, ssl); +#endif +#ifdef HAVE_PK_CALLBACKS + if (pkCallbacks) + SetupPkCallbacks(ctx, ssl); #endif if (matchName && doPeerCheck) CyaSSL_check_domain_name(ssl, domain); @@ -545,7 +642,7 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) else if (CyaSSL_connect(ssl) != SSL_SUCCESS) { /* see note at top of README */ int err = CyaSSL_get_error(ssl, 0); - char buffer[80]; + char buffer[CYASSL_MAX_ERROR_SZ]; printf("err = %d, %s\n", err, CyaSSL_ERR_error_string(err, buffer)); err_sys("SSL_connect failed"); @@ -570,32 +667,25 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) input = CyaSSL_read(ssl, reply, sizeof(reply)-1); if (input > 0) { reply[input] = 0; - printf("Server response: %s", reply); + printf("Server response: %s\n", reply); - if (sendGET && (input == (sizeof(reply)-1))) { /* get html */ + if (sendGET) { /* get html */ while (1) { input = CyaSSL_read(ssl, reply, sizeof(reply)-1); if (input > 0) { reply[input] = 0; - printf("%s", reply); - if(input < sizeof(reply)-1) - break ; + printf("%s\n", reply); } else break; } } - printf("\n"); } else if (input < 0) { int readErr = CyaSSL_get_error(ssl, 0); if (readErr != SSL_ERROR_WANT_READ) err_sys("CyaSSL_read failed"); } - -#ifdef CYASSL_CMSIS_RTOS - osDelay(5000) ; -#endif #ifndef NO_SESSION_CACHE if (resumeSession) { @@ -612,6 +702,10 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) if (doDTLS == 0) /* don't send alert after "break" command */ CyaSSL_shutdown(ssl); /* echoserver will interpret as new conn */ +#ifdef ATOMIC_USER + if (atomicUser) + FreeAtomicUser(ssl); +#endif CyaSSL_free(ssl); CloseSocket(sockfd); @@ -713,11 +807,13 @@ THREAD_RETURN CYASSL_THREAD client_test(void* args) args.argv = argv; CyaSSL_Init(); -#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) +#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) && !defined(STACK_TRAP) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("client") || CurrentDir("build")) + if (CurrentDir("client")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); #ifdef HAVE_STACK_SIZE StackSizeCheck(&args, client_test); diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/config-SimpleClient.h b/IDE/MDK5-ARM/Projects/SimpleClient/config-SimpleClient.h new file mode 100644 index 0000000000..83582ca715 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleClient/config-SimpleClient.h @@ -0,0 +1,70 @@ +/* config-RTX-TCP-FS.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/**** CyaSSL for KEIL-RL Configuration ****/ + +#define __CORTEX_M3__ +#define CYASSL_MDK_ARM +#define NO_WRITEV +#define NO_CYASSL_DIR +#define NO_MAIN_DRIVER + + +#define CYASSL_DER_LOAD +#define HAVE_NULL_CIPHER + +#define HAVE_KEIL_RTX +#define CYASSL_CMSIS_RTOS +#define CYASSL_KEIL_TCP_NET + + +// <<< Use Configuration Wizard in Context Menu >>> +// Build Target: Simple Client +// Callee IP Address +// Default: "192.168.1.100" +#define CYASSL_CALLEE_IP "192.168.11.3" +// Callee Port Number +// Default: "443" +#define CYASSL_CALLEE_PORT "443" +// HTTP GET Option <0=> HTTP Get <1=> SSL/TLS Message +#define MDK_CONF_HTTP_GET 0 +#if MDK_CONF_HTTP_GET == 0 + #define CYASSL_HTTP_GET "-g" + #define CYASSL_HTTP_GET_COUNT 1 +#elif MDK_CONF_HTTP_GET == 1 + #define CYASSL_HTTP_GET "" + #define CYASSL_HTTP_GET_COUNT 0 +#endif +// SSL/TLS Version <0=> SSL3 <1=> TLS 1.0 <2=> TLS 1.1 <3=> TLS 1.2 +#define MDK_CONF_SSL_VERSION 3 +#if MDK_CONF_SSL_VERSION == 0 + #define CYASSL_SSL_VER "0" +#elif MDK_CONF_SSL_VERSION == 1 + #define CYASSL_SSL_VER "1" +#elif MDK_CONF_SSL_VERSION == 2 + #define CYASSL_SSL_VER "2" +#elif MDK_CONF_SSL_VERSION == 3 + #define CYASSL_SSL_VER "3" +#endif + +// +// <<< end of configuration section >>> diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/main.c b/IDE/MDK5-ARM/Projects/SimpleClient/main.c index f6f9ff35ab..90447bae80 100644 --- a/IDE/MDK5-ARM/Projects/SimpleClient/main.c +++ b/IDE/MDK5-ARM/Projects/SimpleClient/main.c @@ -71,7 +71,6 @@ typedef struct func_args { } func_args; extern void client_test(func_args * args) ; -extern void init_time(void) ; osThreadDef (tcp_poll, osPriorityHigh , 1, 0) ; /*----------------------------------------------------------------------------- @@ -89,8 +88,7 @@ int main() "-v", CYASSL_SSL_VER, CYASSL_HTTP_GET } ; static func_args args = { 7 + CYASSL_HTTP_GET_COUNT, argv } ; - - init_time() ; + init_filesystem (); net_initialize() ; osThreadCreate (osThread (tcp_poll), NULL); diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx b/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx index fb0174c764..efee3c0c8c 100644 --- a/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx +++ b/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,9 +355,11 @@ 0 0 0 + 0 + 0 - HAVE_CONFIG_H MDK_CONF_SimpleClient CYASSL_STM32F2xx + HAVE_CONFIG_H MDK_CONF_SimpleClient @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -428,6 +434,11 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + Net_Config_ETH_0.h + 5 + .\RTE\Network\Net_Config_ETH_0.h + @@ -441,33 +452,38 @@ - ::CMSIS + Devices - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + time-dummy.c + 1 + .\time-dummy.c + + time-CortexM3-4.c + 1 + .\time-CortexM3-4.c + + + + + ::CMSIS + RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -483,6 +499,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -491,28 +517,23 @@ PHY_ST802RT1.c 1 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c EMAC_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -523,16 +544,16 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + ::Network - - Net_Dbg_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Config.c 1 @@ -568,221 +589,16 @@ 1 RTE\Network\Net_Debug.c + + Net_Dbg_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + ::wolfSSL - - cyassl_MDK_ARM.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - - - time-STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - - - aes.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - - - arc4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - - - asm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - - - asn.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - - - blake2b.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - - - camellia.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - - - coding.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - - - compress.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - - - des3.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - - - dh.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - - - dsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - - - ecc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - - - ecc_fp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - - - error.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - - - hc128.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - - - hmac.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - - - integer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - - - logging.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - - - md2.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - - - md4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - - - md5.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - - - memory.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - - - misc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - - - pwdbased.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - - - rabbit.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - - - random.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - - - ripemd.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - - - rsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - - - sha.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - - - sha256.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - - - sha512.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - - - tfm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - - - crl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - - - internal.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - - - io.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - - - keys.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - - - ocsp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - - - sniffer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - - - ssl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - - - tls.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - config-Crypt.h 5 @@ -794,9 +610,219 @@ RTE\wolfSSL\config-CyaSSL.h - config.h + settings.h 5 - RTE\wolfSSL\config.h + RTE\wolfSSL\settings.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + + + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + + + crl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + + + internal.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + + + io.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + + + keys.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + + + ocsp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + + + sniffer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + + + ssl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + + + tls.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c @@ -806,25 +832,25 @@ - + - + - + - + @@ -838,20 +864,20 @@ - - + + - - + + - - + + @@ -928,20 +954,14 @@ - - + + - - - - - - - - + + @@ -950,8 +970,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -1076,26 +1096,32 @@ - + RTE\wolfSSL\config-Crypt.h - - + + - + RTE\wolfSSL\config-CyaSSL.h - - + + - RTE\wolfSSL\config.h + RTE\wolfSSL\config.h + + + + RTE\wolfSSL\settings.h + + diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/time-CortexM3-4.c b/IDE/MDK5-ARM/Projects/SimpleClient/time-CortexM3-4.c new file mode 100644 index 0000000000..46712b34cd --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleClient/time-CortexM3-4.c @@ -0,0 +1,41 @@ +/* time-STM32F2.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + + +#include +#define DWT ((DWT_Type *) (0xE0001000UL) ) +typedef struct +{ + uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ +} DWT_Type; + +extern uint32_t SystemCoreClock ; + +double current_time(int reset) +{ + if(reset) DWT->CYCCNT = 0 ; + return ((double)DWT->CYCCNT/SystemCoreClock) ; +} diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/time-STM32F2xx.c b/IDE/MDK5-ARM/Projects/SimpleClient/time-STM32F2xx.c new file mode 100644 index 0000000000..3a26db7dc4 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleClient/time-STM32F2xx.c @@ -0,0 +1,82 @@ +/* time-STM32F2.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +#define PERIPH_BASE ((uint32_t)0x40000000) +/*----------------------------------------------------------------------------- + * initialize RTC + *----------------------------------------------------------------------------*/ +#include "stm32f2xx.h" + +#define assert_param(a) + +#if 0 +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) +#define Bcd2ToByte(v) \ + ((((uint8_t)(v & (uint8_t)0xF0) >> (uint8_t)0x4) * 10) + (v & (uint8_t)0x0F)) +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_TR_MNT ((uint32_t)0x00007000) +#define RTC_TR_MNU ((uint32_t)0x00000F00) + +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) +#endif + +/*----------------------------------------------------------------------------- + * initialize TIM + *----------------------------------------------------------------------------*/ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) + +void init_time(void) +{ + uint16_t tmpcr1 = 0; + + ((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ; + + tmpcr1 = TIM2->CR1 ; + tmpcr1 &= (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) )); + /* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */ + tmpcr1 |= (uint16_t)0x0000 ; /* CR1 |= TIM_CounterMode_Up */ + TIM2->CR1= tmpcr1 ; + + TIM2->ARR = 0xffffffff ; /* ARR= TIM_Period */ + TIM2->PSC = 60 ; /* PSC = TIM_Prescaler */ + TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */ + + *(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ; + /* TIM_Cmd(TIM2, ENABLE) ; */ +} + +double current_time() +{ + return ((double)TIM2->CNT/1000000.0) ; +} + diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/time-dummy.c b/IDE/MDK5-ARM/Projects/SimpleClient/time-dummy.c new file mode 100644 index 0000000000..2525eba38b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleClient/time-dummy.c @@ -0,0 +1,34 @@ +/* time-dummy.c.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + return(&date) ; +} + +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt b/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt index ea3ec6412b..89a9fd422e 100644 --- a/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt +++ b/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt @@ -1,11 +1,12 @@ This program is a simple server example with CyaSSL/wolfCrypt library. In order to run this program, -Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +Copy {PACK}\wolfSSL\CyaSSL\{version}\cyassl\certs folder and files to the SD memory. Set the server IP address in Net_Config_ETH_0.h The default server listning port is 11111, defined in test.h For further configuration, refer config-Crypt.h and config-CyaSSL.h. +config-SimpleServer.h is for configuring the server port number. When testing this server, it is recommended to test against one of the standard CyaSSL example applications running on a desktop machine. The standard CyaSSL diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/CMSIS/RTX_Conf_CM.c deleted file mode 100644 index 2298f7ddbe..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/CMSIS/RTX_Conf_CM.c +++ /dev/null @@ -1,276 +0,0 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - RTX - *---------------------------------------------------------------------------- - * Name: RTX_Conf_CM.C - * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * - * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH - * All rights reserved. - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * - Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without - * specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - *---------------------------------------------------------------------------*/ - -#include "cmsis_os.h" - - -/*---------------------------------------------------------------------------- - * RTX User configuration part BEGIN - *---------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// Thread Configuration -// ======================= -// -// Number of concurrent running threads <0-250> -// Defines max. number of threads that will run at the same time. -// Default: 6 -#ifndef OS_TASKCNT - #define OS_TASKCNT 5 -#endif - -// Default Thread stack size [bytes] <64-4096:8><#/4> -// Defines default stack size for threads with osThreadDef stacksz = 0 -// Default: 200 -#ifndef OS_STKSIZE - #define OS_STKSIZE 250 -#endif - -// Main Thread stack size [bytes] <64-20000:8><#/4> -// Defines stack size for main thread. -// Default: 200 -#ifndef OS_MAINSTKSIZE - #define OS_MAINSTKSIZE 3000 -#endif - -// Number of threads with user-provided stack size <0-250> -// Defines the number of threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVCNT - #define OS_PRIVCNT 0 -#endif - -// Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4> -// Defines the combined stack size for threads with user-provided stack size. -// Default: 0 -#ifndef OS_PRIVSTKSIZE - #define OS_PRIVSTKSIZE 4500 -#endif - -// Check for stack overflow -// Includes the stack checking code for stack overflow. -// Note that additional code reduces the Kernel performance. -#ifndef OS_STKCHECK - #define OS_STKCHECK 1 -#endif - -// Processor mode for thread execution -// <0=> Unprivileged mode -// <1=> Privileged mode -// Default: Privileged mode -#ifndef OS_RUNPRIV - #define OS_RUNPRIV 1 -#endif - -// - -// RTX Kernel Timer Tick Configuration -// ====================================== -// Use Cortex-M SysTick timer as RTX Kernel Timer -// Use the Cortex-M SysTick timer as a time-base for RTX. -#ifndef OS_SYSTICK - #define OS_SYSTICK 1 -#endif -// -// Timer clock value [Hz] <1-1000000000> -// Defines the timer clock value. -// Default: 12000000 (12MHz) -#ifndef OS_CLOCK - #define OS_CLOCK 12000000 -#endif - -// Timer tick value [us] <1-1000000> -// Defines the timer tick value. -// Default: 1000 (1ms) -#ifndef OS_TICK - #define OS_TICK 1000 -#endif - -// - -// System Configuration -// ======================= -// -// Round-Robin Thread switching -// =============================== -// -// Enables Round-Robin Thread switching. -#ifndef OS_ROBIN - #define OS_ROBIN 1 -#endif - -// Round-Robin Timeout [ticks] <1-1000> -// Defines how long a thread will execute before a thread switch. -// Default: 5 -#ifndef OS_ROBINTOUT - #define OS_ROBINTOUT 5 -#endif - -// - -// User Timers -// ============== -// Enables user Timers -#ifndef OS_TIMERS - #define OS_TIMERS 1 -#endif - -// Timer Thread Priority -// <1=> Low -// <2=> Below Normal <3=> Normal <4=> Above Normal -// <5=> High -// <6=> Realtime (highest) -// Defines priority for Timer Thread -// Default: High -#ifndef OS_TIMERPRIO - #define OS_TIMERPRIO 5 -#endif - -// Timer Thread stack size [bytes] <64-64000:8><#/4> -// Defines stack size for Timer thread. -// Default: 200 -#ifndef OS_TIMERSTKSZ - #define OS_TIMERSTKSZ 50 -#endif - -// Timer Callback Queue size <1-32> -// Number of concurrent active timer callback functions. -// Default: 4 -#ifndef OS_TIMERCBQS - #define OS_TIMERCBQS 4 -#endif - -// - -// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries -// <12=> 12 entries <16=> 16 entries -// <24=> 24 entries <32=> 32 entries -// <48=> 48 entries <64=> 64 entries -// <96=> 96 entries -// ISR functions store requests to this buffer, -// when they are called from the interrupt handler. -// Default: 16 entries -#ifndef OS_FIFOSZ - #define OS_FIFOSZ 16 -#endif - -// - -//------------- <<< end of configuration section >>> ----------------------- - -// Standard library system mutexes -// =============================== -// Define max. number system mutexes that are used to protect -// the arm standard runtime library. For microlib they are not used. -#ifndef OS_MUTEXCNT - #define OS_MUTEXCNT 8 -#endif - -/*---------------------------------------------------------------------------- - * RTX User configuration part END - *---------------------------------------------------------------------------*/ - -#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) - - -/*---------------------------------------------------------------------------- - * Global Functions - *---------------------------------------------------------------------------*/ - -/*--------------------------- os_idle_demon ---------------------------------*/ - -void os_idle_demon (void) { - /* The idle demon is a system thread, running when no other thread is */ - /* ready to run. */ - - for (;;) { - /* HERE: include optional user code to be executed when no thread runs.*/ - } -} - -#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer - -/*--------------------------- os_tick_init ----------------------------------*/ - -// Initialize alternative hardware timer as RTX kernel timer -// Return: IRQ number of the alternative hardware timer -int os_tick_init (void) { - return (-1); /* Return IRQ number of timer (0..239) */ -} - -/*--------------------------- os_tick_val -----------------------------------*/ - -// Get alternative hardware timer current value (0 .. OS_TRV) -uint32_t os_tick_val (void) { - return (0); -} - -/*--------------------------- os_tick_ovf -----------------------------------*/ - -// Get alternative hardware timer overflow flag -// Return: 1 - overflow, 0 - no overflow -uint32_t os_tick_ovf (void) { - return (0); -} - -/*--------------------------- os_tick_irqack --------------------------------*/ - -// Acknowledge alternative hardware timer interrupt -void os_tick_irqack (void) { - /* ... */ -} - -#endif // (OS_SYSTICK == 0) - -/*--------------------------- os_error --------------------------------------*/ - -void os_error (uint32_t err_code) { - /* This function is called when a runtime error is detected. Parameter */ - /* 'err_code' holds the runtime error code (defined in RTL.H). */ - - /* HERE: include optional code to be executed on runtime error. */ - for (;;); -} - - -/*---------------------------------------------------------------------------- - * RTX Configuration Functions - *---------------------------------------------------------------------------*/ - -#include "RTX_CM_lib.h" - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/RTE_Device.h deleted file mode 100644 index 4a09246f38..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/RTE_Device.h +++ /dev/null @@ -1,3127 +0,0 @@ -/* ----------------------------------------------------------------------------- - * Copyright (C) 2013 ARM Limited. All rights reserved. - * - * $Date: 27. June 2013 - * $Revision: V1.01 - * - * Project: RTE Device Configuration for ST STM32F2xx - * -------------------------------------------------------------------------- */ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -#ifndef __RTE_DEVICE_H -#define __RTE_DEVICE_H - - -#define GPIO_PORT(num) \ - ((num == 0) ? GPIOA : \ - (num == 1) ? GPIOB : \ - (num == 2) ? GPIOC : \ - (num == 3) ? GPIOD : \ - (num == 4) ? GPIOE : \ - (num == 5) ? GPIOF : \ - (num == 6) ? GPIOG : \ - (num == 7) ? GPIOH : \ - (num == 8) ? GPIOI : \ - NULL) - - -// Clock Configuration -// High-speed Internal Clock <1-999999999> -#define RTE_HSI 16000000 -// High-speed External Clock <1-999999999> -#define RTE_HSE 25000000 -// System Clock <1-999999999> -#define RTE_SYSCLK 120000000 -// AHB Clock <1-999999999> -#define RTE_HCLK 120000000 -// APB1 Clock <1-999999999> -#define RTE_PCLK1 30000000 -// APB2 Clock <1-999999999> -#define RTE_PCLK2 60000000 -// 48MHz Clock -#define RTE_PLL48CK 48000000 -// - - -// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] -// Configuration settings for Driver_UART1 in component ::Drivers:UART -#define RTE_USART1 0 - -// USART1_TX Pin <0=>PA9 <1=>PB6 -#define RTE_USART1_TX_ID 0 -#if (RTE_USART1_TX_ID == 0) -#define RTE_USART1_TX_PORT GPIOA -#define RTE_USART1_TX_BIT 9 -#elif (RTE_USART1_TX_ID == 1) -#define RTE_USART1_TX_PORT GPIOB -#define RTE_USART1_TX_BIT 6 -#else -#error "Invalid USART1_TX Pin Configuration!" -#endif - -// USART1_RX Pin <0=>PA10 <1=>PB7 -#define RTE_USART1_RX_ID 0 -#if (RTE_USART1_RX_ID == 0) -#define RTE_USART1_RX_PORT GPIOA -#define RTE_USART1_RX_BIT 10 -#elif (RTE_USART1_RX_ID == 1) -#define RTE_USART1_RX_PORT GPIOB -#define RTE_USART1_RX_BIT 7 -#else -#error "Invalid USART1_RX Pin Configuration!" -#endif - -// Synchronous -// USART1_CK Pin <0=>PA8 -// -#define RTE_USART1_CK 0 -#define RTE_USART1_CK_ID 0 -#if (RTE_USART1_CK_ID == 0) -#define RTE_USART1_CK_PORT GPIOA -#define RTE_USART1_CK_BIT 8 -#else -#error "Invalid USART1_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART1_CTS Pin <0=>PA11 -// USART1_RTS Pin <0=>PA12 -// Manual CTS/RTS -// -#define RTE_USART1_HW_FLOW 0 -#define RTE_USART1_CTS_ID 0 -#define RTE_USART1_RTS_ID 0 -#define RTE_USART1_MANUAL_FLOW 0 -#if (RTE_USART1_CTS_ID == 0) -#define RTE_USART1_CTS_PORT GPIOA -#define RTE_USART1_CTS_BIT 11 -#else -#error "Invalid USART1_CTS Pin Configuration!" -#endif -#if (RTE_USART1_RTS_ID == 0) -#define RTE_USART1_RTS_PORT GPIOA -#define RTE_USART1_RTS_BIT 12 -#else -#error "Invalid USART1_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <2=>2 <5=>5 -// Selects DMA Stream (only Stream 2 or 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_RX_DMA 1 -#define RTE_USART1_RX_DMA_NUMBER 2 -#define RTE_USART1_RX_DMA_STREAM 2 -#define RTE_USART1_RX_DMA_CHANNEL 4 -#define RTE_USART1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART1_TX_DMA 1 -#define RTE_USART1_TX_DMA_NUMBER 2 -#define RTE_USART1_TX_DMA_STREAM 7 -#define RTE_USART1_TX_DMA_CHANNEL 4 -#define RTE_USART1_TX_DMA_PRIORITY 0 - -// - - -// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] -// Configuration settings for Driver_UART2 in component ::Drivers:UART -#define RTE_USART2 0 - -// USART2_TX Pin <0=>PA2 <1=>PD5 -#define RTE_USART2_TX_ID 0 -#if (RTE_USART2_TX_ID == 0) -#define RTE_USART2_TX_PORT GPIOA -#define RTE_USART2_TX_BIT 2 -#elif (RTE_USART2_TX_ID == 1) -#define RTE_USART2_TX_PORT GPIOD -#define RTE_USART2_TX_BIT 5 -#else -#error "Invalid USART2_TX Pin Configuration!" -#endif - -// USART2_RX Pin <0=>PA3 <1=>PD6 -#define RTE_USART2_RX_ID 0 -#if (RTE_USART2_RX_ID == 0) -#define RTE_USART2_RX_PORT GPIOA -#define RTE_USART2_RX_BIT 3 -#elif (RTE_USART2_RX_ID == 1) -#define RTE_USART2_RX_PORT GPIOD -#define RTE_USART2_RX_BIT 6 -#else -#error "Invalid USART2_RX Pin Configuration!" -#endif - -// Synchronous -// USART2_CK Pin <0=>PA4 <1=>PD7 -// -#define RTE_USART2_CK 0 -#define RTE_USART2_CK_ID 0 -#if (RTE_USART2_CK_ID == 0) -#define RTE_USART2_CK_PORT GPIOA -#define RTE_USART2_CK_BIT 4 -#elif (RTE_USART2_CK_ID == 1) -#define RTE_USART2_CK_PORT GPIOD -#define RTE_USART2_CK_BIT 7 -#else -#error "Invalid USART2_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART2_CTS Pin <0=>PA0 <1=>PD3 -// USART2_RTS Pin <0=>PA1 <1=>PD4 -// Manual CTS/RTS -// -#define RTE_USART2_HW_FLOW 0 -#define RTE_USART2_CTS_ID 0 -#define RTE_USART2_RTS_ID 0 -#define RTE_USART2_MANUAL_FLOW 0 -#if (RTE_USART2_CTS_ID == 0) -#define RTE_USART2_CTS_PORT GPIOA -#define RTE_USART2_CTS_BIT 0 -#elif (RTE_USART2_CTS_ID == 1) -#define RTE_USART2_CTS_PORT GPIOD -#define RTE_USART2_CTS_BIT 3 -#else -#error "Invalid USART2_CTS Pin Configuration!" -#endif -#if (RTE_USART2_RTS_ID == 0) -#define RTE_USART2_RTS_PORT GPIOA -#define RTE_USART2_RTS_BIT 1 -#elif (RTE_USART2_RTS_ID == 1) -#define RTE_USART2_RTS_PORT GPIOD -#define RTE_USART2_RTS_BIT 4 -#else -#error "Invalid USART2_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 -// Selects DMA Stream (only Stream 5 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_RX_DMA 1 -#define RTE_USART2_RX_DMA_NUMBER 1 -#define RTE_USART2_RX_DMA_STREAM 5 -#define RTE_USART2_RX_DMA_CHANNEL 4 -#define RTE_USART2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 -// Selects DMA Stream (only Stream 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART2_TX_DMA 1 -#define RTE_USART2_TX_DMA_NUMBER 1 -#define RTE_USART2_TX_DMA_STREAM 6 -#define RTE_USART2_TX_DMA_CHANNEL 4 -#define RTE_USART2_TX_DMA_PRIORITY 0 - -// - - -// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] -// Configuration settings for Driver_UART3 in component ::Drivers:UART -#define RTE_USART3 0 - -// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 -#define RTE_USART3_TX_ID 0 -#if (RTE_USART3_TX_ID == 0) -#define RTE_USART3_TX_PORT GPIOB -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 1) -#define RTE_USART3_TX_PORT GPIOC -#define RTE_USART3_TX_BIT 10 -#elif (RTE_USART3_TX_ID == 2) -#define RTE_USART3_TX_PORT GPIOD -#define RTE_USART3_TX_BIT 8 -#else -#error "Invalid USART3_TX Pin Configuration!" -#endif - -// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 -#define RTE_USART3_RX_ID 0 -#if (RTE_USART3_RX_ID == 0) -#define RTE_USART3_RX_PORT GPIOB -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 1) -#define RTE_USART3_RX_PORT GPIOC -#define RTE_USART3_RX_BIT 11 -#elif (RTE_USART3_RX_ID == 2) -#define RTE_USART3_RX_PORT GPIOD -#define RTE_USART3_RX_BIT 9 -#else -#error "Invalid USART3_RX Pin Configuration!" -#endif - -// Synchronous -// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 -// -#define RTE_USART3_CK 0 -#define RTE_USART3_CK_ID 0 -#if (RTE_USART3_CK_ID == 0) -#define RTE_USART3_CK_PORT GPIOB -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 1) -#define RTE_USART3_CK_PORT GPIOC -#define RTE_USART3_CK_BIT 12 -#elif (RTE_USART3_CK_ID == 2) -#define RTE_USART3_CK_PORT GPIOD -#define RTE_USART3_CK_BIT 10 -#else -#error "Invalid USART3_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART3_CTS Pin <0=>PB13 <1=>PD11 -// USART3_RTS Pin <0=>PB14 <1=>PD12 -// Manual CTS/RTS -// -#define RTE_USART3_HW_FLOW 0 -#define RTE_USART3_CTS_ID 0 -#define RTE_USART3_RTS_ID 0 -#define RTE_USART3_MANUAL_FLOW 0 -#if (RTE_USART3_CTS_ID == 0) -#define RTE_USART3_CTS_PORT GPIOB -#define RTE_USART3_CTS_BIT 13 -#elif (RTE_USART3_CTS_ID == 1) -#define RTE_USART3_CTS_PORT GPIOD -#define RTE_USART3_CTS_BIT 11 -#else -#error "Invalid USART3_CTS Pin Configuration!" -#endif -#if (RTE_USART3_RTS_ID == 0) -#define RTE_USART3_RTS_PORT GPIOB -#define RTE_USART3_RTS_BIT 14 -#elif (RTE_USART3_RTS_ID == 1) -#define RTE_USART3_RTS_PORT GPIOD -#define RTE_USART3_RTS_BIT 12 -#else -#error "Invalid USART3_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <1=>1 -// Selects DMA Stream (only Stream 1 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_RX_DMA 1 -#define RTE_USART3_RX_DMA_NUMBER 1 -#define RTE_USART3_RX_DMA_STREAM 1 -#define RTE_USART3_RX_DMA_CHANNEL 4 -#define RTE_USART3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART3_TX_DMA 1 -#define RTE_USART3_TX_DMA_NUMBER 1 -#define RTE_USART3_TX_DMA_STREAM 3 -#define RTE_USART3_TX_DMA_CHANNEL 4 -#define RTE_USART3_TX_DMA_PRIORITY 0 - -// - - -// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] -// Configuration settings for Driver_UART4 in component ::Drivers:UART -#define RTE_UART4 0 - -// UART4_TX Pin <0=>PA0 <1=>PC10 -#define RTE_UART4_TX_ID 0 -#if (RTE_UART4_TX_ID == 0) -#define RTE_UART4_TX_PORT GPIOA -#define RTE_UART4_TX_BIT 0 -#elif (RTE_UART4_TX_ID == 1) -#define RTE_UART4_TX_PORT GPIOC -#define RTE_UART4_TX_BIT 10 -#else -#error "Invalid UART4_TX Pin Configuration!" -#endif - -// UART4_RX Pin <0=>PA1 <1=>PC11 -#define RTE_UART4_RX_ID 0 -#if (RTE_UART4_RX_ID == 0) -#define RTE_UART4_RX_PORT GPIOA -#define RTE_UART4_RX_BIT 1 -#elif (RTE_UART4_RX_ID == 1) -#define RTE_UART4_RX_PORT GPIOC -#define RTE_UART4_RX_BIT 11 -#else -#error "Invalid UART4_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_RX_DMA 1 -#define RTE_UART4_RX_DMA_NUMBER 1 -#define RTE_UART4_RX_DMA_STREAM 2 -#define RTE_UART4_RX_DMA_CHANNEL 4 -#define RTE_UART4_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART4_TX_DMA 1 -#define RTE_UART4_TX_DMA_NUMBER 1 -#define RTE_UART4_TX_DMA_STREAM 4 -#define RTE_UART4_TX_DMA_CHANNEL 4 -#define RTE_UART4_TX_DMA_PRIORITY 0 - -// - - -// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] -// Configuration settings for Driver_UART5 in component ::Drivers:UART -#define RTE_UART5 0 - -// UART5_TX Pin <0=>PC12 -#define RTE_UART5_TX_ID 0 -#if (RTE_UART5_TX_ID == 0) -#define RTE_UART5_TX_PORT GPIOC -#define RTE_UART5_TX_BIT 12 -#else -#error "Invalid UART5_TX Pin Configuration!" -#endif - -// UART5_RX Pin <0=>PD2 -#define RTE_UART5_RX_ID 0 -#if (RTE_UART5_RX_ID == 0) -#define RTE_UART5_RX_PORT GPIOD -#define RTE_UART5_RX_BIT 2 -#else -#error "Invalid UART5_RX Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 -// Selects DMA Stream (only Stream 0 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_RX_DMA 1 -#define RTE_UART5_RX_DMA_NUMBER 1 -#define RTE_UART5_RX_DMA_STREAM 0 -#define RTE_UART5_RX_DMA_CHANNEL 4 -#define RTE_UART5_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_UART5_TX_DMA 1 -#define RTE_UART5_TX_DMA_NUMBER 1 -#define RTE_UART5_TX_DMA_STREAM 7 -#define RTE_UART5_TX_DMA_CHANNEL 4 -#define RTE_UART5_TX_DMA_PRIORITY 0 - -// - - -// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] -// Configuration settings for Driver_UART6 in component ::Drivers:UART -#define RTE_USART6 0 - -// USART6_TX Pin <0=>PC6 <1=>PG14 -#define RTE_USART6_TX_ID 0 -#if (RTE_USART6_TX_ID == 0) -#define RTE_USART6_TX_PORT GPIOC -#define RTE_USART6_TX_BIT 6 -#elif (RTE_USART6_TX_ID == 1) -#define RTE_USART6_TX_PORT GPIOG -#define RTE_USART6_TX_BIT 14 -#else -#error "Invalid USART6_TX Pin Configuration!" -#endif - -// USART6_RX Pin <0=>PC7 <1=>PG9 -#define RTE_USART6_RX_ID 0 -#if (RTE_USART6_RX_ID == 0) -#define RTE_USART6_RX_PORT GPIOC -#define RTE_USART6_RX_BIT 7 -#elif (RTE_USART6_RX_ID == 1) -#define RTE_USART6_RX_PORT GPIOG -#define RTE_USART6_RX_BIT 9 -#else -#error "Invalid USART6_RX Pin Configuration!" -#endif - -// Synchronous -// USART6_CK Pin <0=>PC8 <1=>PG7 -// -#define RTE_USART6_CK 0 -#define RTE_USART6_CK_ID 0 -#if (RTE_USART6_CK_ID == 0) -#define RTE_USART6_CK_PORT GPIOC -#define RTE_USART6_CK_BIT 8 -#elif (RTE_USART6_CK_ID == 1) -#define RTE_USART6_CK_PORT GPIOG -#define RTE_USART6_CK_BIT 7 -#else -#error "Invalid USART6_CK Pin Configuration!" -#endif - -// Hardware flow control -// USART6_CTS Pin <0=>PG13 <1=>PG15 -// USART6_RTS Pin <0=>PG8 <1=>PG12 -// Manual CTS/RTS -// -#define RTE_USART6_HW_FLOW 0 -#define RTE_USART6_CTS_ID 0 -#define RTE_USART6_RTS_ID 0 -#define RTE_USART6_MANUAL_FLOW 0 -#if (RTE_USART6_CTS_ID == 0) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 13 -#elif (RTE_USART6_CTS_ID == 1) -#define RTE_USART6_CTS_PORT GPIOG -#define RTE_USART6_CTS_BIT 15 -#else -#error "Invalid USART6_CTS Pin Configuration!" -#endif -#if (RTE_USART6_RTS_ID == 0) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 8 -#elif (RTE_USART6_RTS_ID == 1) -#define RTE_USART6_RTS_PORT GPIOG -#define RTE_USART6_RTS_BIT 12 -#else -#error "Invalid USART6_RTS Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <1=>1 <2=>2 -// Selects DMA Stream (only Stream 1 or 2 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_RX_DMA 1 -#define RTE_USART6_RX_DMA_NUMBER 2 -#define RTE_USART6_RX_DMA_STREAM 1 -#define RTE_USART6_RX_DMA_CHANNEL 5 -#define RTE_USART6_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <5=>5 -// Selects DMA Channel (only Channel 5 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_USART6_TX_DMA 1 -#define RTE_USART6_TX_DMA_NUMBER 2 -#define RTE_USART6_TX_DMA_STREAM 6 -#define RTE_USART6_TX_DMA_CHANNEL 5 -#define RTE_USART6_TX_DMA_PRIORITY 0 - -// - - -// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] -// Configuration settings for Driver_I2C1 in component ::Drivers:I2C -#define RTE_I2C1 0 - -// I2C1_SCL Pin <0=>PB6 <1=>PB8 -#define RTE_I2C1_SCL_PORT_ID 0 -#if (RTE_I2C1_SCL_PORT_ID == 0) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 6 -#elif (RTE_I2C1_SCL_PORT_ID == 1) -#define RTE_I2C1_SCL_PORT GPIOB -#define RTE_I2C1_SCL_BIT 8 -#else -#error "Invalid I2C1_SCL Pin Configuration!" -#endif - -// I2C1_SDA Pin <0=>PB7 <1=>PB9 -#define RTE_I2C1_SDA_PORT_ID 0 -#if (RTE_I2C1_SDA_PORT_ID == 0) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 7 -#elif (RTE_I2C1_SDA_PORT_ID == 1) -#define RTE_I2C1_SDA_PORT GPIOB -#define RTE_I2C1_SDA_BIT 9 -#else -#error "Invalid I2C1_SDA Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <5=>5 -// Selects DMA Stream (only Stream 0 or 5 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_RX_DMA 1 -#define RTE_I2C1_RX_DMA_NUMBER 1 -#define RTE_I2C1_RX_DMA_STREAM 0 -#define RTE_I2C1_RX_DMA_CHANNEL 1 -#define RTE_I2C1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <6=>6 <7=>7 -// Selects DMA Stream (only Stream 6 or 7 can be used) -// Channel <1=>1 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C1_TX_DMA 1 -#define RTE_I2C1_TX_DMA_NUMBER 1 -#define RTE_I2C1_TX_DMA_STREAM 6 -#define RTE_I2C1_TX_DMA_CHANNEL 1 -#define RTE_I2C1_TX_DMA_PRIORITY 0 - -// - - -// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] -// Configuration settings for Driver_I2C2 in component ::Drivers:I2C -#define RTE_I2C2 0 - -// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 -#define RTE_I2C2_SCL_PORT_ID 0 -#if (RTE_I2C2_SCL_PORT_ID == 0) -#define RTE_I2C2_SCL_PORT GPIOF -#define RTE_I2C2_SCL_BIT 1 -#elif (RTE_I2C2_SCL_PORT_ID == 1) -#define RTE_I2C2_SCL_PORT GPIOH -#define RTE_I2C2_SCL_BIT 4 -#elif (RTE_I2C2_SCL_PORT_ID == 2) -#define RTE_I2C2_SCL_PORT GPIOB -#define RTE_I2C2_SCL_BIT 10 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 -#define RTE_I2C2_SDA_PORT_ID 0 -#if (RTE_I2C2_SDA_PORT_ID == 0) -#define RTE_I2C2_SDA_PORT GPIOF -#define RTE_I2C2_SDA_BIT 0 -#elif (RTE_I2C2_SDA_PORT_ID == 1) -#define RTE_I2C2_SDA_PORT GPIOH -#define RTE_I2C2_SDA_BIT 5 -#elif (RTE_I2C2_SDA_PORT_ID == 2) -#define RTE_I2C2_SDA_PORT GPIOB -#define RTE_I2C2_SDA_BIT 11 -#else -#error "Invalid I2C2_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 <3=>3 -// Selects DMA Stream (only Stream 2 or 3 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 7 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_RX_DMA 1 -#define RTE_I2C2_RX_DMA_NUMBER 1 -#define RTE_I2C2_RX_DMA_STREAM 2 -#define RTE_I2C2_RX_DMA_CHANNEL 7 -#define RTE_I2C2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <7=>7 -// Selects DMA Stream (only Stream 7 can be used) -// Channel <7=>7 -// Selects DMA Channel (only Channel 1 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C2_TX_DMA 1 -#define RTE_I2C2_TX_DMA_NUMBER 1 -#define RTE_I2C2_TX_DMA_STREAM 7 -#define RTE_I2C2_TX_DMA_CHANNEL 7 -#define RTE_I2C2_TX_DMA_PRIORITY 0 - -// - - -// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] -// Configuration settings for Driver_I2C3 in component ::Drivers:I2C -#define RTE_I2C3 0 - -// I2C3_SCL Pin <0=>PH7 <1=>PA8 -#define RTE_I2C3_SCL_PORT_ID 0 -#if (RTE_I2C3_SCL_PORT_ID == 0) -#define RTE_I2C3_SCL_PORT GPIOH -#define RTE_I2C3_SCL_BIT 7 -#elif (RTE_I2C3_SCL_PORT_ID == 1) -#define RTE_I2C3_SCL_PORT GPIOA -#define RTE_I2C3_SCL_BIT 8 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// I2C3_SDA Pin <0=>PH8 <1=>PC9 -#define RTE_I2C3_SDA_PORT_ID 0 -#if (RTE_I2C3_SDA_PORT_ID == 0) -#define RTE_I2C3_SDA_PORT GPIOH -#define RTE_I2C3_SDA_BIT 8 -#elif (RTE_I2C3_SDA_PORT_ID == 1) -#define RTE_I2C3_SDA_PORT GPIOC -#define RTE_I2C3_SDA_BIT 9 -#else -#error "Invalid I2C3_SCL Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_RX_DMA 1 -#define RTE_I2C3_RX_DMA_NUMBER 1 -#define RTE_I2C3_RX_DMA_STREAM 2 -#define RTE_I2C3_RX_DMA_CHANNEL 3 -#define RTE_I2C3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <4=>4 -// Selects DMA Stream (only Stream 4 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_I2C3_TX_DMA 1 -#define RTE_I2C3_TX_DMA_NUMBER 1 -#define RTE_I2C3_TX_DMA_STREAM 4 -#define RTE_I2C3_TX_DMA_CHANNEL 3 -#define RTE_I2C3_TX_DMA_PRIORITY 0 - -// - - -// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] -// Configuration settings for Driver_SPI1 in component ::Drivers:SPI -#define RTE_SPI1 0 - -// SPI1_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI1_NSS_PIN 1 -#define RTE_SPI1_NSS_PORT GPIO_PORT(0) -#define RTE_SPI1_NSS_BIT 4 - -// SPI1_SCK Pin <0=>PA5 <1=>PB3 -#define RTE_SPI1_SCL_PORT_ID 0 -#if (RTE_SPI1_SCL_PORT_ID == 0) -#define RTE_SPI1_SCL_PORT GPIOA -#define RTE_SPI1_SCL_BIT 5 -#elif (RTE_SPI1_SCL_PORT_ID == 1) -#define RTE_SPI1_SCL_PORT GPIOB -#define RTE_SPI1_SCL_BIT 3 -#else -#error "Invalid SPI1_SCK Pin Configuration!" -#endif - -// SPI1_MISO Pin <0=>PA6 <1=>PB4 -#define RTE_SPI1_MISO_PORT_ID 0 -#if (RTE_SPI1_MISO_PORT_ID == 0) -#define RTE_SPI1_MISO_PORT GPIOA -#define RTE_SPI1_MISO_BIT 6 -#elif (RTE_SPI1_MISO_PORT_ID == 1) -#define RTE_SPI1_MISO_PORT GPIOB -#define RTE_SPI1_MISO_BIT 4 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// SPI1_MOSI Pin <0=>PA7 <1=>PB5 -#define RTE_SPI1_MOSI_PORT_ID 0 -#if (RTE_SPI1_MOSI_PORT_ID == 0) -#define RTE_SPI1_MOSI_PORT GPIOA -#define RTE_SPI1_MOSI_BIT 7 -#elif (RTE_SPI1_MOSI_PORT_ID == 1) -#define RTE_SPI1_MOSI_PORT GPIOB -#define RTE_SPI1_MOSI_BIT 5 -#else -#error "Invalid SPI1_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_RX_DMA 1 -#define RTE_SPI1_RX_DMA_NUMBER 2 -#define RTE_SPI1_RX_DMA_STREAM 0 -#define RTE_SPI1_RX_DMA_CHANNEL 3 -#define RTE_SPI1_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <5=>5 -// Selects DMA Stream (only Stream 3 or 5 can be used) -// Channel <3=>3 -// Selects DMA Channel (only Channel 3 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI1_TX_DMA 1 -#define RTE_SPI1_TX_DMA_NUMBER 2 -#define RTE_SPI1_TX_DMA_STREAM 5 -#define RTE_SPI1_TX_DMA_CHANNEL 3 -#define RTE_SPI1_TX_DMA_PRIORITY 0 - -// - - -// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] -// Configuration settings for Driver_SPI2 in component ::Drivers:SPI -#define RTE_SPI2 0 - -// SPI2_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI2_NSS_PIN 1 -#define RTE_SPI2_NSS_PORT GPIO_PORT(1) -#define RTE_SPI2_NSS_BIT 12 - -// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 -#define RTE_SPI2_SCL_PORT_ID 0 -#if (RTE_SPI2_SCL_PORT_ID == 0) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 10 -#elif (RTE_SPI2_SCL_PORT_ID == 1) -#define RTE_SPI2_SCL_PORT GPIOB -#define RTE_SPI2_SCL_BIT 13 -#elif (RTE_SPI2_SCL_PORT_ID == 2) -#define RTE_SPI2_SCL_PORT GPIOI -#define RTE_SPI2_SCL_BIT 1 -#else -#error "Invalid SPI2_SCK Pin Configuration!" -#endif - -// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 -#define RTE_SPI2_MISO_PORT_ID 0 -#if (RTE_SPI2_MISO_PORT_ID == 0) -#define RTE_SPI2_MISO_PORT GPIOB -#define RTE_SPI2_MISO_BIT 14 -#elif (RTE_SPI2_MISO_PORT_ID == 1) -#define RTE_SPI2_MISO_PORT GPIOC -#define RTE_SPI2_MISO_BIT 2 -#elif (RTE_SPI2_MISO_PORT_ID == 2) -#define RTE_SPI2_MISO_PORT GPIOI -#define RTE_SPI2_MISO_BIT 2 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 -#define RTE_SPI2_MOSI_PORT_ID 0 -#if (RTE_SPI2_MOSI_PORT_ID == 0) -#define RTE_SPI2_MOSI_PORT GPIOB -#define RTE_SPI2_MOSI_BIT 15 -#elif (RTE_SPI2_MOSI_PORT_ID == 1) -#define RTE_SPI2_MOSI_PORT GPIOC -#define RTE_SPI2_MOSI_BIT 3 -#elif (RTE_SPI2_MOSI_PORT_ID == 2) -#define RTE_SPI2_MOSI_PORT GPIOI -#define RTE_SPI2_MOSI_BIT 3 -#else -#error "Invalid SPI2_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <2=>2 -// Selects DMA Stream (only Stream 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_RX_DMA 1 -#define RTE_SPI2_RX_DMA_NUMBER 1 -#define RTE_SPI2_RX_DMA_STREAM 2 -#define RTE_SPI2_RX_DMA_CHANNEL 0 -#define RTE_SPI2_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <3=>3 -// Selects DMA Stream (only Stream 3 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI2_TX_DMA 1 -#define RTE_SPI2_TX_DMA_NUMBER 1 -#define RTE_SPI2_TX_DMA_STREAM 3 -#define RTE_SPI2_TX_DMA_CHANNEL 0 -#define RTE_SPI2_TX_DMA_PRIORITY 0 - -// - - -// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] -// Configuration settings for Driver_SPI3 in component ::Drivers:SPI -#define RTE_SPI3 0 - -// SPI3_NSS Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SPI3_NSS_PIN 1 -#define RTE_SPI3_NSS_PORT GPIO_PORT(0) -#define RTE_SPI3_NSS_BIT 15 - -// SPI3_SCK Pin <0=>PB3 <1=>PC10 -#define RTE_SPI3_SCL_PORT_ID 0 -#if (RTE_SPI3_SCL_PORT_ID == 0) -#define RTE_SPI3_SCL_PORT GPIOB -#define RTE_SPI3_SCL_BIT 3 -#elif (RTE_SPI3_SCL_PORT_ID == 1) -#define RTE_SPI3_SCL_PORT GPIOC -#define RTE_SPI3_SCL_BIT 10 -#else -#error "Invalid SPI3_SCK Pin Configuration!" -#endif - -// SPI3_MISO Pin <0=>PB4 <1=>PC11 -#define RTE_SPI3_MISO_PORT_ID 0 -#if (RTE_SPI3_MISO_PORT_ID == 0) -#define RTE_SPI3_MISO_PORT GPIOB -#define RTE_SPI3_MISO_BIT 4 -#elif (RTE_SPI3_MISO_PORT_ID == 1) -#define RTE_SPI3_MISO_PORT GPIOC -#define RTE_SPI3_MISO_BIT 11 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// SPI3_MOSI Pin <0=>PB5 <1=>PC12 -#define RTE_SPI3_MOSI_PORT_ID 0 -#if (RTE_SPI3_MOSI_PORT_ID == 0) -#define RTE_SPI3_MOSI_PORT GPIOB -#define RTE_SPI3_MOSI_BIT 5 -#elif (RTE_SPI3_MOSI_PORT_ID == 1) -#define RTE_SPI3_MOSI_PORT GPIOC -#define RTE_SPI3_MOSI_BIT 12 -#else -#error "Invalid SPI3_MISO Pin Configuration!" -#endif - -// DMA Rx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <0=>0 <2=>2 -// Selects DMA Stream (only Stream 0 or 2 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_RX_DMA 1 -#define RTE_SPI3_RX_DMA_NUMBER 1 -#define RTE_SPI3_RX_DMA_STREAM 0 -#define RTE_SPI3_RX_DMA_CHANNEL 0 -#define RTE_SPI3_RX_DMA_PRIORITY 0 - -// DMA Tx -// Number <1=>1 -// Selects DMA Number (only DMA1 can be used) -// Stream <5=>5 <7=>7 -// Selects DMA Stream (only Stream 5 or 7 can be used) -// Channel <0=>0 -// Selects DMA Channel (only Channel 0 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SPI3_TX_DMA 1 -#define RTE_SPI3_TX_DMA_NUMBER 1 -#define RTE_SPI3_TX_DMA_STREAM 5 -#define RTE_SPI3_TX_DMA_CHANNEL 0 -#define RTE_SPI3_TX_DMA_PRIORITY 0 - -// - - -// SDIO (Secure Digital Input/Output) [Driver_MCI0] -// Configuration settings for Driver_MCI0 in component ::Drivers:MCI -#define RTE_SDIO 1 - -// SDIO_CD (Card Detect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_CD_PIN 1 -#define RTE_SDIO_CD_ACTIVE 0 -#define RTE_SDIO_CD_PORT GPIO_PORT(7) -#define RTE_SDIO_CD_BIT 15 - -// SDIO_WP (Write Protect) Pin -// Configure Pin if exists -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_SDIO_WP_PIN 0 -#define RTE_SDIO_WP_ACTIVE 0 -#define RTE_SDIO_WP_PORT GPIO_PORT(7) -#define RTE_SDIO_WP_BIT 16 - -// SDIO Bus -// SDIO_CK Pin <0=>PC12 -#define RTE_SDIO_CK_PORT_ID 0 -#if (RTE_SDIO_CK_PORT_ID == 0) -#define RTE_SDIO_CK_PORT GPIOC -#define RTE_SDIO_CK_PIN 12 -#else -#error "Invalid SDIO_CK Pin Configuration!" -#endif -// SDIO_CMD Pin <0=>PD2 -#define RTE_SDIO_CMD_PORT_ID 0 -#if (RTE_SDIO_CMD_PORT_ID == 0) -#define RTE_SDIO_CMD_PORT GPIOD -#define RTE_SDIO_CMD_PIN 2 -#else -#error "Invalid SDIO_CDM Pin Configuration!" -#endif -// SDIO_D0 Pin <0=>PC8 -#define RTE_SDIO_D0_PORT_ID 0 -#if (RTE_SDIO_D0_PORT_ID == 0) -#define RTE_SDIO_D0_PORT GPIOC -#define RTE_SDIO_D0_PIN 8 -#else -#error "Invalid SDIO_D0 Pin Configuration!" -#endif -// SDIO_D1 Pin <0=>PC9 -#define RTE_SDIO_D1_PORT_ID 0 -#if (RTE_SDIO_D1_PORT_ID == 0) -#define RTE_SDIO_D1_PORT GPIOC -#define RTE_SDIO_D1_PIN 9 -#else -#error "Invalid SDIO_D1 Pin Configuration!" -#endif -// SDIO_D2 Pin <0=>PC10 -#define RTE_SDIO_D2_PORT_ID 0 -#if (RTE_SDIO_D2_PORT_ID == 0) -#define RTE_SDIO_D2_PORT GPIOC -#define RTE_SDIO_D2_PIN 10 -#else -#error "Invalid SDIO_D2 Pin Configuration!" -#endif -// SDIO_D3 Pin <0=>PC11 -#define RTE_SDIO_D3_PORT_ID 0 -#if (RTE_SDIO_D3_PORT_ID == 0) -#define RTE_SDIO_D3_PORT GPIOC -#define RTE_SDIO_D3_PIN 11 -#else -#error "Invalid SDIO_D3 Pin Configuration!" -#endif -// SDIO_D4 Pin <0=>PB8 -#define RTE_SDIO_D4_PORT_ID 0 -#if (RTE_SDIO_D4_PORT_ID == 0) -#define RTE_SDIO_D4_PORT GPIOB -#define RTE_SDIO_D4_PIN 8 -#else -#error "Invalid SDIO_D4 Pin Configuration!" -#endif -// SDIO_D5 Pin <0=>PB9 -#define RTE_SDIO_D5_PORT_ID 0 -#if (RTE_SDIO_D5_PORT_ID == 0) -#define RTE_SDIO_D5_PORT GPIOB -#define RTE_SDIO_D5_PIN 9 -#else -#error "Invalid SDIO_D5 Pin Configuration!" -#endif -// SDIO_D6 Pin <0=>PC6 -#define RTE_SDIO_D6_PORT_ID 0 -#if (RTE_SDIO_D6_PORT_ID == 0) -#define RTE_SDIO_D6_PORT GPIOC -#define RTE_SDIO_D6_PIN 6 -#else -#error "Invalid SDIO_D6 Pin Configuration!" -#endif -// SDIO_D7 Pin <0=>PC7 -#define RTE_SDIO_D7_PORT_ID 0 -#if (RTE_SDIO_D7_PORT_ID == 0) -#define RTE_SDIO_D7_PORT GPIOC -#define RTE_SDIO_D7_PIN 7 -#else -#error "Invalid SDIO_D7 Pin Configuration!" -#endif -// - -// DMA -// Number <2=>2 -// Selects DMA Number (only DMA2 can be used) -// Stream <3=>3 <6=>6 -// Selects DMA Stream (only Stream 3 or 6 can be used) -// Channel <4=>4 -// Selects DMA Channel (only Channel 4 can be used) -// Priority <0=>Low <1=>Medium <2=>High <3=>Very High -// Selects DMA Priority -// -#define RTE_SDIO_DMA 1 -#define RTE_SDIO_DMA_NUMBER 2 -#define RTE_SDIO_DMA_STREAM 3 -#define RTE_SDIO_DMA_CHANNEL 4 -#define RTE_SDIO_DMA_PRIORITY 0 - -// - - -// ETH (Ethernet Interface) [Driver_ETH_MAC0] -// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC -#define RTE_ETH 1 - -// MII (Media Independent Interface) -#define RTE_ETH_MII 0 - -// ETH_MII_TX_CLK Pin <0=>PC3 -#define RTE_ETH_MII_TX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_TX_CLK_PORT GPIOC -#define RTE_ETH_MII_TX_CLK_PIN 3 -#else -#error "Invalid ETH_MII_TX_CLK Pin Configuration!" -#endif -// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_MII_TXD0_PORT_ID 0 -#if (RTE_ETH_MII_TXD0_PORT_ID == 0) -#define RTE_ETH_MII_TXD0_PORT GPIOB -#define RTE_ETH_MII_TXD0_PIN 12 -#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) -#define RTE_ETH_MII_TXD0_PORT GPIOG -#define RTE_ETH_MII_TXD0_PIN 13 -#else -#error "Invalid ETH_MII_TXD0 Pin Configuration!" -#endif -// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_MII_TXD1_PORT_ID 0 -#if (RTE_ETH_MII_TXD1_PORT_ID == 0) -#define RTE_ETH_MII_TXD1_PORT GPIOB -#define RTE_ETH_MII_TXD1_PIN 13 -#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) -#define RTE_ETH_MII_TXD1_PORT GPIOG -#define RTE_ETH_MII_TXD1_PIN 14 -#else -#error "Invalid ETH_MII_TXD1 Pin Configuration!" -#endif -// ETH_MII_TXD2 Pin <0=>PC2 -#define RTE_ETH_MII_TXD2_PORT_ID 0 -#if (RTE_ETH_MII_TXD2_PORT_ID == 0) -#define RTE_ETH_MII_TXD2_PORT GPIOC -#define RTE_ETH_MII_TXD2_PIN 2 -#else -#error "Invalid ETH_MII_TXD2 Pin Configuration!" -#endif -// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 -#define RTE_ETH_MII_TXD3_PORT_ID 0 -#if (RTE_ETH_MII_TXD3_PORT_ID == 0) -#define RTE_ETH_MII_TXD3_PORT GPIOB -#define RTE_ETH_MII_TXD3_PIN 8 -#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) -#define RTE_ETH_MII_TXD3_PORT GPIOE -#define RTE_ETH_MII_TXD3_PIN 2 -#else -#error "Invalid ETH_MII_TXD3 Pin Configuration!" -#endif -// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_MII_TX_EN_PORT_ID 0 -#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) -#define RTE_ETH_MII_TX_EN_PORT GPIOB -#define RTE_ETH_MII_TX_EN_PIN 11 -#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) -#define RTE_ETH_MII_TX_EN_PORT GPIOG -#define RTE_ETH_MII_TX_EN_PIN 11 -#else -#error "Invalid ETH_MII_TX_EN Pin Configuration!" -#endif -// ETH_MII_RX_CLK Pin <0=>PA1 -#define RTE_ETH_MII_RX_CLK_PORT_ID 0 -#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) -#define RTE_ETH_MII_RX_CLK_PORT GPIOA -#define RTE_ETH_MII_RX_CLK_PIN 1 -#else -#error "Invalid ETH_MII_RX_CLK Pin Configuration!" -#endif -// ETH_MII_RXD0 Pin <0=>PC4 -#define RTE_ETH_MII_RXD0_PORT_ID 0 -#if (RTE_ETH_MII_RXD0_PORT_ID == 0) -#define RTE_ETH_MII_RXD0_PORT GPIOC -#define RTE_ETH_MII_RXD0_PIN 4 -#else -#error "Invalid ETH_MII_RXD0 Pin Configuration!" -#endif -// ETH_MII_RXD1 Pin <0=>PC5 -#define RTE_ETH_MII_RXD1_PORT_ID 0 -#if (RTE_ETH_MII_RXD1_PORT_ID == 0) -#define RTE_ETH_MII_RXD1_PORT GPIOC -#define RTE_ETH_MII_RXD1_PIN 5 -#else -#error "Invalid ETH_MII_RXD1 Pin Configuration!" -#endif -// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 -#define RTE_ETH_MII_RXD2_PORT_ID 0 -#if (RTE_ETH_MII_RXD2_PORT_ID == 0) -#define RTE_ETH_MII_RXD2_PORT GPIOB -#define RTE_ETH_MII_RXD2_PIN 0 -#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) -#define RTE_ETH_MII_RXD2_PORT GPIOH -#define RTE_ETH_MII_RXD2_PIN 6 -#else -#error "Invalid ETH_MII_RXD2 Pin Configuration!" -#endif -// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 -#define RTE_ETH_MII_RXD3_PORT_ID 0 -#if (RTE_ETH_MII_RXD3_PORT_ID == 0) -#define RTE_ETH_MII_RXD3_PORT GPIOB -#define RTE_ETH_MII_RXD3_PIN 1 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RXD3_PORT GPIOH -#define RTE_ETH_MII_RXD3_PIN 7 -#else -#error "Invalid ETH_MII_RXD3 Pin Configuration!" -#endif -// ETH_MII_RX_DV Pin <0=>PA7 -#define RTE_ETH_MII_RX_DV_PORT_ID 0 -#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) -#define RTE_ETH_MII_RX_DV_PORT GPIOA -#define RTE_ETH_MII_RX_DV_PIN 7 -#else -#error "Invalid ETH_MII_RX_DV Pin Configuration!" -#endif -// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 -#define RTE_ETH_MII_RX_ER_PORT_ID 0 -#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) -#define RTE_ETH_MII_RX_ER_PORT GPIOB -#define RTE_ETH_MII_RX_ER_PIN 10 -#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) -#define RTE_ETH_MII_RX_ER_PORT GPIOI -#define RTE_ETH_MII_RX_ER_PIN 10 -#else -#error "Invalid ETH_MII_RX_ER Pin Configuration!" -#endif -// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 -#define RTE_ETH_MII_CRS_PORT_ID 0 -#if (RTE_ETH_MII_CRS_PORT_ID == 0) -#define RTE_ETH_MII_CRS_PORT GPIOA -#define RTE_ETH_MII_CRS_PIN 0 -#elif (RTE_ETH_MII_CRS_PORT_ID == 1) -#define RTE_ETH_MII_CRS_PORT GPIOH -#define RTE_ETH_MII_CRS_PIN 2 -#else -#error "Invalid ETH_MII_CRS Pin Configuration!" -#endif -// ETH_MII_COL Pin <0=>PA3 <1=>PH3 -#define RTE_ETH_MII_COL_PORT_ID 0 -#if (RTE_ETH_MII_COL_PORT_ID == 0) -#define RTE_ETH_MII_COL_PORT GPIOA -#define RTE_ETH_MII_COL_PIN 3 -#elif (RTE_ETH_MII_COL_PORT_ID == 1) -#define RTE_ETH_MII_COL_PORT GPIOH -#define RTE_ETH_MII_COL_PIN 3 -#else -#error "Invalid ETH_MII_COL Pin Configuration!" -#endif - -// - -// RMII (Reduced Media Independent Interface) -#define RTE_ETH_RMII 1 - -// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 -#define RTE_ETH_RMII_TXD0_PORT_ID 1 -#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) -#define RTE_ETH_RMII_TXD0_PORT GPIOB -#define RTE_ETH_RMII_TXD0_PIN 12 -#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) -#define RTE_ETH_RMII_TXD0_PORT GPIOG -#define RTE_ETH_RMII_TXD0_PIN 13 -#else -#error "Invalid ETH_RMII_TXD0 Pin Configuration!" -#endif -// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 -#define RTE_ETH_RMII_TXD1_PORT_ID 1 -#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) -#define RTE_ETH_RMII_TXD1_PORT GPIOB -#define RTE_ETH_RMII_TXD1_PIN 13 -#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) -#define RTE_ETH_RMII_TXD1_PORT GPIOG -#define RTE_ETH_RMII_TXD1_PIN 14 -#else -#error "Invalid ETH_RMII_TXD1 Pin Configuration!" -#endif -// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 -#define RTE_ETH_RMII_TX_EN_PORT_ID 1 -#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) -#define RTE_ETH_RMII_TX_EN_PORT GPIOB -#define RTE_ETH_RMII_TX_EN_PIN 11 -#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) -#define RTE_ETH_RMII_TX_EN_PORT GPIOG -#define RTE_ETH_RMII_TX_EN_PIN 11 -#else -#error "Invalid ETH_RMII_TX_EN Pin Configuration!" -#endif -// ETH_RMII_RXD0 Pin <0=>PC4 -#define RTE_ETH_RMII_RXD0_PORT_ID 0 -#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) -#define RTE_ETH_RMII_RXD0_PORT GPIOC -#define RTE_ETH_RMII_RXD0_PIN 4 -#else -#error "Invalid ETH_RMII_RXD0 Pin Configuration!" -#endif -// ETH_RMII_RXD1 Pin <0=>PC5 -#define RTE_ETH_RMII_RXD1_PORT_ID 0 -#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) -#define RTE_ETH_RMII_RXD1_PORT GPIOC -#define RTE_ETH_RMII_RXD1_PIN 5 -#else -#error "Invalid ETH_RMII_RXD1 Pin Configuration!" -#endif -// ETH_RMII_REF_CLK Pin <0=>PA1 -#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 -#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) -#define RTE_ETH_RMII_REF_CLK_PORT GPIOA -#define RTE_ETH_RMII_REF_CLK_PIN 1 -#else -#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" -#endif -// ETH_RMII_CRS_DV Pin <0=>PA7 -#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 -#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) -#define RTE_ETH_RMII_CRS_DV_PORT GPIOA -#define RTE_ETH_RMII_CRS_DV_PIN 7 -#else -#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" -#endif - -// - -// Management Data Interface -// ETH_MDC Pin <0=>PC1 -#define RTE_ETH_MDI_MDC_PORT_ID 0 -#if (RTE_ETH_MDI_MDC_PORT_ID == 0) -#define RTE_ETH_MDI_MDC_PORT GPIOC -#define RTE_ETH_MDI_MDC_PIN 1 -#else -#error "Invalid ETH_MDC Pin Configuration!" -#endif -// ETH_MDIO Pin <0=>PA2 -#define RTE_ETH_MDI_MDIO_PORT_ID 0 -#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) -#define RTE_ETH_MDI_MDIO_PORT GPIOA -#define RTE_ETH_MDI_MDIO_PIN 2 -#else -#error "Invalid ETH_MDIO Pin Configuration!" -#endif -// - -// Reference 25MHz/50MHz Clock generation -#define RTE_ETH_REF_CLOCK 0 - -// MCO Pin <0=>PA2 <1=>PC9 -#define RTE_ETH_REF_CLOCK_PORT_ID 0 -#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) -#define RTE_ETH_REF_CLOCK_PORT GPIOA -#define RTE_ETH_REF_CLOCK_PIN 8 -#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) -#define RTE_ETH_REF_CLOCK_PORT GPIOC -#define RTE_ETH_REF_CLOCK_PIN 9 -#else -#error "Invalid MCO Pin Configuration!" -#endif - -// - -// - - -// USB OTG Full-speed -#define RTE_USB_OTG_FS 0 - -// Device [Driver_USBD0] -// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device -#define RTE_USB_OTG_FS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_FS_DEV_EP 0x0000000F -#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E -#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E - -// - -// Host [Driver_USBH0] -// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host - -#define RTE_USB_OTG_FS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_VBUS_PIN 1 -#define RTE_OTG_FS_VBUS_ACTIVE 0 -#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) -#define RTE_OTG_FS_VBUS_BIT 5 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_FS_OC_PIN 1 -#define RTE_OTG_FS_OC_ACTIVE 0 -#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_FS_OC_BIT 11 -// - -// - - -// USB OTG High-speed -#define RTE_USB_OTG_HS 0 - -// PHY (Physical Layer) - -// PHY Interface -// <0=>On-chip full-speed PHY -// <1=>External ULPI high-speed PHY -#define RTE_USB_OTG_HS_PHY 1 - -// External ULPI Pins (UTMI+ Low Pin Interface) - -// OTG_HS_ULPI_CK Pin <0=>PA5 -#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" -#endif -// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 -#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 -#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 -#else -#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" -#endif -// OTG_HS_ULPI_STP Pin <0=>PC0 -#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" -#endif -// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 -#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 -#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 -#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) -#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH -#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 -#else -#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" -#endif -// OTG_HS_ULPI_D0 Pin <0=>PA3 -#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA -#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 -#else -#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" -#endif -// OTG_HS_ULPI_D1 Pin <0=>PB0 -#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 -#else -#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" -#endif -// OTG_HS_ULPI_D2 Pin <0=>PB1 -#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 -#else -#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" -#endif -// OTG_HS_ULPI_D3 Pin <0=>PB10 -#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 -#else -#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" -#endif -// OTG_HS_ULPI_D4 Pin <0=>PB11 -#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 -#else -#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" -#endif -// OTG_HS_ULPI_D5 Pin <0=>PB12 -#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 -#else -#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" -#endif -// OTG_HS_ULPI_D6 Pin <0=>PB13 -#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 -#else -#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" -#endif -// OTG_HS_ULPI_D7 Pin <0=>PB5 -#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 -#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) -#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB -#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 -#else -#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" -#endif - -// - -// - -// Device [Driver_USBD1] -// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device -#define RTE_USB_OTG_HS_DEV 1 - -// Endpoints -// Reduce memory requirements of Driver by disabling unused endpoints -// Endpoint 1 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 2 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 3 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 4 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// Endpoint 5 -// Bulk OUT -// Bulk IN -// Interrupt OUT -// Interrupt IN -// Isochronous OUT -// Isochronous IN -// -// -#define RTE_USB_OTG_HS_DEV_EP 0x0000003F -#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E -#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E - -// - -// Host [Driver_USBH1] -// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host -#define RTE_USB_OTG_HS_HOST 1 - -// VBUS Power On/Off Pin -// Configure Pin for driving VBUS -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_VBUS_PIN 1 -#define RTE_OTG_HS_VBUS_ACTIVE 0 -#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) -#define RTE_OTG_HS_VBUS_BIT 2 - -// Overcurrent Detection Pin -// Configure Pin for overcurrent detection -// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) -// Active State <0=>Low <1=>High -// Selects Active State Logical Level -// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD -// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI -// Selects Port Name -// Bit <0-15> -// Selects Port Bit -// -#define RTE_OTG_HS_OC_PIN 1 -#define RTE_OTG_HS_OC_ACTIVE 0 -#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) -#define RTE_OTG_HS_OC_BIT 12 -// - -// - - -// EXTI (External Interrupt/Event Controller) -#define RTE_EXTI 0 - -// EXTI0 Line -#define RTE_EXTI0 0 -// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 -#define RTE_EXTI0_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI0_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI0_TRIGGER 0 -// - -// EXTI1 Line -#define RTE_EXTI1 0 -// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 -#define RTE_EXTI1_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI1_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI1_TRIGGER 0 -// - -// EXTI2 Line -#define RTE_EXTI2 0 -// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 -#define RTE_EXTI2_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI2_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI2_TRIGGER 0 -// - -// EXTI3 Line -#define RTE_EXTI3 0 -// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 -#define RTE_EXTI3_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI3_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI3_TRIGGER 0 -// - -// EXTI4 Line -#define RTE_EXTI4 0 -// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 -#define RTE_EXTI4_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI4_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI4_TRIGGER 0 -// - -// EXTI5 Line -#define RTE_EXTI5 0 -// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 -#define RTE_EXTI5_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI5_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI5_TRIGGER 0 -// - -// EXTI6 Line -#define RTE_EXTI6 0 -// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 -#define RTE_EXTI6_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI6_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI6_TRIGGER 0 -// - -// EXTI7 Line -#define RTE_EXTI7 0 -// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 -#define RTE_EXTI7_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI7_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI7_TRIGGER 0 -// - -// EXTI8 Line -#define RTE_EXTI8 0 -// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 -#define RTE_EXTI8_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI8_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI8_TRIGGER 0 -// - -// EXTI9 Line -#define RTE_EXTI9 0 -// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 -#define RTE_EXTI9_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI9_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI9_TRIGGER 0 -// - -// EXTI10 Line -#define RTE_EXTI10 0 -// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 -#define RTE_EXTI10_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI10_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI10_TRIGGER 0 -// - -// EXTI11 Line -#define RTE_EXTI11 0 -// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 -#define RTE_EXTI11_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI11_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI11_TRIGGER 0 -// - -// EXTI12 Line -#define RTE_EXTI12 0 -// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 -#define RTE_EXTI12_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI12_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI12_TRIGGER 0 -// - -// EXTI13 Line -#define RTE_EXTI13 0 -// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 -#define RTE_EXTI13_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI13_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI13_TRIGGER 0 -// - -// EXTI14 Line -#define RTE_EXTI14 0 -// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 -#define RTE_EXTI14_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI14_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI14_TRIGGER 0 -// - -// EXTI15 Line -#define RTE_EXTI15 0 -// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 -#define RTE_EXTI15_PIN 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI15_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI15_TRIGGER 0 -// - -// EXTI16 Line: PVD Output -#define RTE_EXTI16 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI16_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI16_TRIGGER 0 -// - -// EXTI17 Line: RTC Alarm -#define RTE_EXTI17 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI17_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI17_TRIGGER 0 -// - -// EXTI18 Line: USB OTG FS Wakeup -#define RTE_EXTI18 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI18_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI18_TRIGGER 0 -// - -// EXTI19 Line: Ethernet Wakeup -#define RTE_EXTI19 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI19_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI19_TRIGGER 0 -// - -// EXTI20 Line: USB OTG HS Wakeup -#define RTE_EXTI20 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI20_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI20_TRIGGER 0 -// - -// EXTI21 Line: RTC Tamper and TimeStamp -#define RTE_EXTI21 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI21_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI21_TRIGGER 0 -// - -// EXTI22 Line: RTC Wakeup -#define RTE_EXTI22 0 -// Mode <0=>Interrupt <1=>Event -#define RTE_EXTI22_MODE 0 -// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge -#define RTE_EXTI22_TRIGGER 0 -// - -// - - -// FSMC (Flexible Static Memory Controller) -#define RTE_FSMC 0 - -// Pin Configuration -// Configure Pins -#define RTE_FSMC_PINS 0 - -// Address Bus Pins -// <0=>A[17:16] -// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] -// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] -// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] -#define RTE_FSMC_ABUS_PINS 10 -// Data Bus Pins <0=>D[7:0] <1=>D[15:0] -#define RTE_FSMC_DBUS_PINS 0 -// FSMC_NOE Pin -#define RTE_FSMC_NOE_PIN 0 -// FSMC_NWE Pin -#define RTE_FSMC_NWE_PIN 0 -// FSMC_NBL0 Pin -#define RTE_FSMC_NBL0_PIN 0 -// FSMC_NBL1 Pin -#define RTE_FSMC_NBL1_PIN 0 -// FSMC_NL Pin -#define RTE_FSMC_NL_PIN 0 -// FSMC_NWAIT Pin -#define RTE_FSMC_NWAIT_PIN 0 -// FSMC_CLK Pin -#define RTE_FSMC_CLK_PIN 0 -// FSMC_NE1/NCE2 Pin -#define RTE_FSMC_NE1_PIN 0 -// FSMC_NE2/NCE3 Pin -#define RTE_FSMC_NE2_PIN 0 -// FSMC_NE3/NCE4_1 Pin -#define RTE_FSMC_NE3_PIN 0 -// FSMC_NE4 Pin -#define RTE_FSMC_NE4_PIN 0 -// FSMC_NCE4_2 Pin -#define RTE_FSMC_NCE42_PIN 0 -// FSMC_INT2 Pin -#define RTE_FSMC_INT2_PIN 0 -// FSMC_INT3 Pin -#define RTE_FSMC_INT3_PIN 0 -// FSMC_INTR Pin -#define RTE_FSMC_INTR_PIN 0 -// FSMC_NIORD Pin -#define RTE_FSMC_NIORD_PIN 0 -// FSMC_NIOWR Pin -#define RTE_FSMC_NIOWR_PIN 0 -// FSMC_NREG Pin -#define RTE_FSMC_NREG_PIN 0 -// FSMC_CD Pin -#define RTE_FSMC_CD_PIN 0 - -// - -// NOR Flash / PSRAM Controller - -// FSMC_NE1 Chip Select -// Configure Device on Chip Select FSMC_NE1 -#define RTE_FSMC_NE1 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR1_CBURSTRW 0 -#define RTE_FSMC_BCR1_ASYNCWAIT 0 -#define RTE_FSMC_BCR1_EXTMOD 0 -#define RTE_FSMC_BCR1_WAITEN 1 -#define RTE_FSMC_BCR1_WREN 1 -#define RTE_FSMC_BCR1_WAITCFG 0 -#define RTE_FSMC_BCR1_WRAPMOD 0 -#define RTE_FSMC_BCR1_WAITPOL 0 -#define RTE_FSMC_BCR1_BURSTEN 0 -#define RTE_FSMC_BCR1_FACCEN 1 -#define RTE_FSMC_BCR1_MWID 1 -#define RTE_FSMC_BCR1_MTYP 2 -#define RTE_FSMC_BCR1_MUXEN 1 -#define RTE_FSMC_BCR1_MBKEN 1 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR1_ACCMOD 0 -#define RTE_FSMC_BTR1_DATLAT 15 -#define RTE_FSMC_BTR1_CLKDIV 15 -#define RTE_FSMC_BTR1_BUSTURN 15 -#define RTE_FSMC_BTR1_DATAST 255 -#define RTE_FSMC_BTR1_ADDHLD 15 -#define RTE_FSMC_BTR1_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR1_ACCMOD 0 -#define RTE_FSMC_BWTR1_DATLAT 15 -#define RTE_FSMC_BWTR1_CLKDIV 15 -#define RTE_FSMC_BWTR1_BUSTURN 15 -#define RTE_FSMC_BWTR1_DATAST 255 -#define RTE_FSMC_BWTR1_ADDHLD 15 -#define RTE_FSMC_BWTR1_ADDSET 15 -// -// - -// FSMC_NE2 Chip Select -// Configure Device on Chip Select FSMC_NE2 -#define RTE_FSMC_NE2 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR2_CBURSTRW 0 -#define RTE_FSMC_BCR2_ASYNCWAIT 0 -#define RTE_FSMC_BCR2_EXTMOD 0 -#define RTE_FSMC_BCR2_WAITEN 1 -#define RTE_FSMC_BCR2_WREN 1 -#define RTE_FSMC_BCR2_WAITCFG 0 -#define RTE_FSMC_BCR2_WRAPMOD 0 -#define RTE_FSMC_BCR2_WAITPOL 0 -#define RTE_FSMC_BCR2_BURSTEN 0 -#define RTE_FSMC_BCR2_FACCEN 1 -#define RTE_FSMC_BCR2_MWID 1 -#define RTE_FSMC_BCR2_MTYP 0 -#define RTE_FSMC_BCR2_MUXEN 1 -#define RTE_FSMC_BCR2_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR2_ACCMOD 0 -#define RTE_FSMC_BTR2_DATLAT 15 -#define RTE_FSMC_BTR2_CLKDIV 15 -#define RTE_FSMC_BTR2_BUSTURN 15 -#define RTE_FSMC_BTR2_DATAST 255 -#define RTE_FSMC_BTR2_ADDHLD 15 -#define RTE_FSMC_BTR2_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR2_ACCMOD 0 -#define RTE_FSMC_BWTR2_DATLAT 15 -#define RTE_FSMC_BWTR2_CLKDIV 15 -#define RTE_FSMC_BWTR2_BUSTURN 15 -#define RTE_FSMC_BWTR2_DATAST 255 -#define RTE_FSMC_BWTR2_ADDHLD 15 -#define RTE_FSMC_BWTR2_ADDSET 15 -// -// - -// FSMC_NE3 Chip Select -// Configure Device on Chip Select FSMC_NE3 -#define RTE_FSMC_NE3 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR3_CBURSTRW 0 -#define RTE_FSMC_BCR3_ASYNCWAIT 0 -#define RTE_FSMC_BCR3_EXTMOD 0 -#define RTE_FSMC_BCR3_WAITEN 1 -#define RTE_FSMC_BCR3_WREN 1 -#define RTE_FSMC_BCR3_WAITCFG 0 -#define RTE_FSMC_BCR3_WRAPMOD 0 -#define RTE_FSMC_BCR3_WAITPOL 0 -#define RTE_FSMC_BCR3_BURSTEN 0 -#define RTE_FSMC_BCR3_FACCEN 1 -#define RTE_FSMC_BCR3_MWID 1 -#define RTE_FSMC_BCR3_MTYP 0 -#define RTE_FSMC_BCR3_MUXEN 1 -#define RTE_FSMC_BCR3_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR3_ACCMOD 0 -#define RTE_FSMC_BTR3_DATLAT 15 -#define RTE_FSMC_BTR3_CLKDIV 15 -#define RTE_FSMC_BTR3_BUSTURN 15 -#define RTE_FSMC_BTR3_DATAST 255 -#define RTE_FSMC_BTR3_ADDHLD 15 -#define RTE_FSMC_BTR3_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR3_ACCMOD 0 -#define RTE_FSMC_BWTR3_DATLAT 15 -#define RTE_FSMC_BWTR3_CLKDIV 15 -#define RTE_FSMC_BWTR3_BUSTURN 15 -#define RTE_FSMC_BWTR3_DATAST 255 -#define RTE_FSMC_BWTR3_ADDHLD 15 -#define RTE_FSMC_BWTR3_ADDSET 15 -// -// - -// FSMC_NE4 Chip Select -// Configure Device on Chip Select FSMC_NE4 -#define RTE_FSMC_NE4 0 - -// Chip-select control -// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write -// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash -// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. -// ASYNCWAIT: Wait signal during asynchronous transfer -// Enables the FSMC to use the wait signal even during an asynchronous protocol. -// EXTMOD: Extended mode enable -// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. -// WAITEN: Wait enable -// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. -// WREN: Write enable -// Enable/disable write operations in the current bank by the FSMC -// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state -// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory -// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted -// by the memory one clock cycle before the wait state or during the wait state -// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high -// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. -// BURSTEN: Burst enable -// Enables the burst access mode for the memory. Valid only with synchronous burst memories. -// FACCEN: Flash access enable -// Enables NOR Flash memory access operations. -// MWID: Memory databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width, valid for all type of memories. -// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash -// Defines the type of external memory attached to the corresponding memory bank. -// MUXEN: Address/data multiplexing enable -// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. -// MBKEN: Memory bank enable -// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a -// disabled bank causes an ERROR on AHB bus. -#define RTE_FSMC_BCR4_CBURSTRW 0 -#define RTE_FSMC_BCR4_ASYNCWAIT 0 -#define RTE_FSMC_BCR4_EXTMOD 0 -#define RTE_FSMC_BCR4_WAITEN 1 -#define RTE_FSMC_BCR4_WREN 1 -#define RTE_FSMC_BCR4_WAITCFG 0 -#define RTE_FSMC_BCR4_WRAPMOD 0 -#define RTE_FSMC_BCR4_WAITPOL 0 -#define RTE_FSMC_BCR4_BURSTEN 0 -#define RTE_FSMC_BCR4_FACCEN 1 -#define RTE_FSMC_BCR4_MWID 1 -#define RTE_FSMC_BCR4_MTYP 0 -#define RTE_FSMC_BCR4_MUXEN 1 -#define RTE_FSMC_BCR4_MBKEN 0 -// - -// Chip-select timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock -// cycles (+2) to issue to the memory before getting the first data: -// 0000: Data latency of 2 CLK clock cycles for first burst access -// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) -// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. -// In the case of CRAM, this field must be set to ‘0’. -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: -// 0000: Reserved -// 0001: CLK period = 2 × HCLK periods -// 0010: CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Define the bus turnaround delay after a read access only -// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive -// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the -// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the -// databus in Hi-Z state. -// These bits are written by software to add a delay at the end of a write/read transaction. This -// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx -// high to NEx low) and the maximum time needed by the memory to free the data bus after a -// read access (tEHQZ): -// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if -// EXTMOD = ‘0’ -// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) -// DATAST: Data phase duration <1-255> -// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Define the duration of the address hold phase used in mode D and multiplexed accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration =1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 -// memory clock period duration. -// ADDSET: Address setup phase duration <0-15> -// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don’t care. -#define RTE_FSMC_BTR4_ACCMOD 0 -#define RTE_FSMC_BTR4_DATLAT 15 -#define RTE_FSMC_BTR4_CLKDIV 15 -#define RTE_FSMC_BTR4_BUSTURN 15 -#define RTE_FSMC_BTR4_DATAST 255 -#define RTE_FSMC_BTR4_ADDHLD 15 -#define RTE_FSMC_BTR4_ADDSET 15 -// - -// Write timing -// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D -// Specifies the asynchronous access modes. Access mode is taken into account only when -// Extended mode is enabled in the Chip-select control register. -// DATLAT: Data latency <0-15> -// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles -// (+2) to issue to the memory before getting the first data. -// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access -// ... -// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) -// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In -// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of -// CRAM, this field must be set to 0 -// CLKDIV: Clock divide ratio (for CLK signal) <1-15> -// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. -// 0000: Reserved -// 0001 CLK period = 2 × HCLK periods -// 0010 CLK period = 3 × HCLK periods -// 1111: CLK period = 16 × HCLK periods (default value after reset) -// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. -// BUSTURN: Bus turnaround phase duration <0-15> -// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). -// (BUSTRUN + 1) HCLK period = tEHELmin. -// 0000: BUSTURN phase duration = 0 HCLK clock cycle added -// ... -// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) -// DATAST: Data phase duration <1-255> -// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. -// 0000 0000: Reserved -// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles -// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles -// ... -// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) -// Note: In synchronous accesses, this value is don't care. -// ADDHLD: Address hold phase duration <1-15> -// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. -// 0000: Reserved -// 0001: ADDHLD phase duration = 1 × HCLK clock cycle -// 0010: ADDHLD phase duration = 2 × HCLK clock cycle -// ... -// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. -// ADDSET: Address setup phase duration <1-15> -// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. -// 0000: ADDSET phase duration = 0 × HCLK clock cycle -// ... -// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) -// Note: In synchronous NOR Flash accesses, this value is don’t care. -#define RTE_FSMC_BWTR4_ACCMOD 0 -#define RTE_FSMC_BWTR4_DATLAT 15 -#define RTE_FSMC_BWTR4_CLKDIV 15 -#define RTE_FSMC_BWTR4_BUSTURN 15 -#define RTE_FSMC_BWTR4_DATAST 255 -#define RTE_FSMC_BWTR4_ADDHLD 15 -#define RTE_FSMC_BWTR4_ADDSET 15 -// -// - -// - -// NAND Flash Controller - -// FSMC_NCE2 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE2 -#define RTE_FSMC_NCE2 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR2_ECCPS 0 -#define RTE_FSMC_PCR2_TAR 0 -#define RTE_FSMC_PCR2_TCLR 0 -#define RTE_FSMC_PCR2_ECCEN 0 -#define RTE_FSMC_PCR2_PWID 0 -#define RTE_FSMC_PCR2_PTYP 1 -#define RTE_FSMC_PCR2_PBKEN 0 -#define RTE_FSMC_PCR2_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR2_IFEN 0 -#define RTE_FSMC_SR2_ILEN 0 -#define RTE_FSMC_SR2_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM2_MEMHIZ 255 -#define RTE_FSMC_PMEM2_MEMHOLD 255 -#define RTE_FSMC_PMEM2_MEMWAIT 255 -#define RTE_FSMC_PMEM2_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT2_ATTHIZ 255 -#define RTE_FSMC_PATT2_ATTHOLD 255 -#define RTE_FSMC_PATT2_ATTWAIT 255 -#define RTE_FSMC_PATT2_ATTSET 255 - -// - -// - -// FSMC_NCE3 Chip Select -// Configure NAND Device on Chip Select FSMC_NCE3 -#define RTE_FSMC_NCE3 0 - -// NAND Flash Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <1=>NAND Flash -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: NAND Flash memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR3_ECCPS 0 -#define RTE_FSMC_PCR3_TAR 0 -#define RTE_FSMC_PCR3_TCLR 0 -#define RTE_FSMC_PCR3_ECCEN 0 -#define RTE_FSMC_PCR3_PWID 0 -#define RTE_FSMC_PCR3_PTYP 1 -#define RTE_FSMC_PCR3_PBKEN 0 -#define RTE_FSMC_PCR3_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR3_IFEN 0 -#define RTE_FSMC_SR3_ILEN 0 -#define RTE_FSMC_SR3_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM3_MEMHIZ 255 -#define RTE_FSMC_PMEM3_MEMHOLD 255 -#define RTE_FSMC_PMEM3_MEMWAIT 255 -#define RTE_FSMC_PMEM3_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT3_ATTHIZ 255 -#define RTE_FSMC_PATT3_ATTHOLD 255 -#define RTE_FSMC_PATT3_ATTWAIT 255 -#define RTE_FSMC_PATT3_ATTSET 255 - -// - -// - -// - -// PC Card Controller - -// FSMC_NCE4_x Chip Select -// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 -#define RTE_FSMC_NCE4 0 - -// PC Card Control -// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes -// Defines the page size for the extended ECC. -// TAR: ALE to RE delay <0-15> -// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). -// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// TCLR: CLE to RE delay <0-15> -// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). -// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period -// 0000: 1 HCLK cycle (default) -// 1111: 16 HCLK cycles -// Note: SET is MEMSET or ATTSET according to the addressed space. -// ECCEN: ECC computation logic enable -// PWID: Databus width <0=>8 bits <1=>16 bits -// Defines the external memory device width. -// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA -// Defines the type of device attached to the corresponding memory bank. -// PBKEN: PC Card memory bank enable -// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. -// PWAITEN: Wait feature enable -// Enables the Wait feature for the PC Card/NAND Flash memory bank. -#define RTE_FSMC_PCR4_ECCPS 0 -#define RTE_FSMC_PCR4_TAR 0 -#define RTE_FSMC_PCR4_TCLR 0 -#define RTE_FSMC_PCR4_ECCEN 0 -#define RTE_FSMC_PCR4_PWID 0 -#define RTE_FSMC_PCR4_PTYP 0 -#define RTE_FSMC_PCR4_PBKEN 0 -#define RTE_FSMC_PCR4_PWAITEN 0 - -// - -// Interrupt configuration -// IFEN: Falling edge detection enable -// ILEN: High-level detection enable -// IREN: Rising edge detection enable -#define RTE_FSMC_SR4_IFEN 0 -#define RTE_FSMC_SR4_ILEN 0 -#define RTE_FSMC_SR4_IREN 0 - -// - -// Common memory space timing -// MEMHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// MEMWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access to. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) -// MEMSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 2 HCLK cycles (for NAND Flash) -// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) -#define RTE_FSMC_PMEM4_MEMHIZ 255 -#define RTE_FSMC_PMEM4_MEMHOLD 255 -#define RTE_FSMC_PMEM4_MEMWAIT 255 -#define RTE_FSMC_PMEM4_MEMSET 255 - -// - -// Attribute memory space timing -// ATTHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a NAND Flash write access. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// ATTWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, -// NOE), for NAND Flash read or write access. The duration for command assertion -// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. -// 0000 0000: reserved -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) -// ATTSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up address before the command -// assertion (NWE, NOE), for NAND Flash read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PATT4_ATTHIZ 255 -#define RTE_FSMC_PATT4_ATTHOLD 255 -#define RTE_FSMC_PATT4_ATTWAIT 255 -#define RTE_FSMC_PATT4_ATTSET 255 - -// - -// I/O space timing -// IOHIZ: Databus HiZ time <0-255> -// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the -// start of a PC Card write access. Only valid for write transaction. -// 0000 0000: 0 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOHOLD: Hold time <1-255> -// Defines the number of HCLK clock cycles to hold address (and data for write access) after -// the command deassertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: reserved -// 0000 0001: 1 HCLK cycle -// 1111 1111: 255 HCLK cycles (default value after reset) -// IOWAIT: Wait time <1-255> -// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, -// SMNOE), for PC Card read or write access. The duration for command assertion is -// extended if the wait signal (NWAIT) is active (low) at the end of the -// programmed value of HCLK. -// 0000 0000: reserved, do not use this value -// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) -// 1111 1111: 256 HCLK cycles -// IOSET: Setup time <0-255> -// Defines the number of HCLK (+1) clock cycles to set up the address before the command -// assertion (NWE, NOE), for PC Card read or write access. -// 0000 0000: 1 HCLK cycle -// 1111 1111: 256 HCLK cycles (default value after reset) -#define RTE_FSMC_PIO4_IOHIZ 255 -#define RTE_FSMC_PIO4_IOHOLD 255 -#define RTE_FSMC_PIO4_IOWAIT 255 -#define RTE_FSMC_PIO4_IOSET 255 - -// - -// - -// - -// - - -#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s deleted file mode 100644 index b2a3fc40f3..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s +++ /dev/null @@ -1,419 +0,0 @@ -;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** -;* File Name : startup_stm32f2xx.s -;* Author : MCD Application Team -;* Version : V1.0.0 -;* Date : 18-April-2011 -;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS -; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. -; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, -; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE -; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING -; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x0000A000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYP crypto - DCD HASH_RNG_IRQHandler ; Hash and Rng -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/system_stm32f2xx.c deleted file mode 100644 index da0e189c88..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/system_stm32f2xx.c +++ /dev/null @@ -1,536 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @version V1.0.0 - * @date 18-April-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32F2xx devices, - * and is generated by the clock configuration tool - * "STM32f2xx_Clock_Configuration_V1.0.0.xls" - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (16 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define - * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - *============================================================================= - * Supported STM32F2xx device revision | Rev B and Y - *----------------------------------------------------------------------------- - * System Clock source | PLL (HSE) - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 120000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 4 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 2 - *----------------------------------------------------------------------------- - * HSE Frequency(Hz) | 25000000 - *----------------------------------------------------------------------------- - * PLL_M | 25 - *----------------------------------------------------------------------------- - * PLL_N | 240 - *----------------------------------------------------------------------------- - * PLL_P | 2 - *----------------------------------------------------------------------------- - * PLL_Q | 5 - *----------------------------------------------------------------------------- - * PLLI2S_N | NA - *----------------------------------------------------------------------------- - * PLLI2S_R | NA - *----------------------------------------------------------------------------- - * I2S input clock | NA - *----------------------------------------------------------------------------- - * VDD(V) | 3.3 - *----------------------------------------------------------------------------- - * Flash Latency(WS) | 3 - *----------------------------------------------------------------------------- - * Prefetch Buffer | ON - *----------------------------------------------------------------------------- - * Instruction cache | ON - *----------------------------------------------------------------------------- - * Data cache | ON - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Enabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -#include "stm32f2xx.h" - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M 25 -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - uint32_t SystemCoreClock = 120000000; - - __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f2xx.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ - +-------------------+--------------------+ -*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR = 0x00000078; - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00cc00cc; - GPIOD->AFR[1] = 0xcc0ccccc; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xa2aa0a0a; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xf3ff0f0f; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xaaaa800a; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xffffc00f; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xcccc0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xaa000aaa; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xff000fff; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0x000000c0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00080aaa; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000c0fff; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR = 0x00000001; - - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001015; - FSMC_Bank1->BTCR[3] = 0x00010400; - FSMC_Bank1E->BWTR[2] = 0x0fffffff; -/* - Bank1_SRAM2 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 4; - p.FSMC_BusTurnAroundDuration = 1; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config.c deleted file mode 100644 index 78564b080c..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config.c +++ /dev/null @@ -1,72 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config.c - * Purpose: File System Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// File System -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define NUM_FILES 8 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACHE_SIZE 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CACHE_ADDR 0x60000000 - -// - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_FileSystem_Drive_RAM -#include "FS_Config_RAM.h" -#endif - -#ifdef RTE_FileSystem_Drive_NOR_0 -#include "FS_Config_NOR_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NOR_1 -#include "FS_Config_NOR_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_NAND_0 -#include "FS_Config_NAND_0.h" -#endif -#ifdef RTE_FileSystem_Drive_NAND_1 -#include "FS_Config_NAND_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_MC_0 -#include "FS_Config_MC_0.h" -#endif -#ifdef RTE_FileSystem_Drive_MC_1 -#include "FS_Config_MC_1.h" -#endif - -#ifdef RTE_FileSystem_Drive_USB_0 -#include "FS_Config_USB_0.h" -#endif -#ifdef RTE_FileSystem_Drive_USB_1 -#include "FS_Config_USB_1.h" -#endif - -#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config_MC_0.h deleted file mode 100644 index 0b1c6d3a71..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config_MC_0.h +++ /dev/null @@ -1,57 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::File System:Drive - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: FS_Config_MC_0.h - * Purpose: File System Configuration for Memory Card Drive - * Rev.: V5.01 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Memory Card Drive 0 -// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" -#define MC0_ENABLE 1 - -// Connect to hardware via Driver_MCI# <0-255> -// Select driver control block for hardware interface -#define MC0_MCI_DRIVER 0 - -// Connect to hardware via Driver_SPI# <0-255> -// Select driver control block for hardware interface when in SPI mode -#define MC0_SPI_DRIVER 0 - -// Memory Card Interface Mode <0=>Native <1=>SPI -// Native uses a SD Bus with up to 8 data lines, CLK, and CMD -// SPI uses 2 data lines (MOSI and MISO), SCLK and CS -// When using SPI both Driver_SPI# and Driver_MCI# must be specified -// since the MCI driver provides the control interface lines. -#define MC0_SPI 0 - -// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Drive Cache stores data sectors and may be increased to speed-up -// file read/write operations on this drive (default: 4 KB) -#define MC0_CACHE_SIZE 4 - -// Locate Drive Cache and Drive Buffer -// Some microcontrollers support DMA only in specific memory areas and -// require to locate the drive buffers at a fixed address. -#define MC0_CACHE_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Set buffer base address to RAM areas that support DMA with the drive. -#define MC0_CACHE_ADDR 0x7FD00000 - -// - -// Use FAT Journal -// Protect File Allocation Table and Directory Entries for -// fail-safe operation. -#define MC0_FAT_JOURNAL 0 - -// Default Drive "M0:" -// Use this drive when no drive letter is specified. -#define MC0_DEFAULT_DRIVE 1 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config.c deleted file mode 100644 index 6b9dc8e00d..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config.c +++ /dev/null @@ -1,153 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config.c - * Purpose: Network Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// System Definitions -// Global Network System definitions -// Local Host Name -// This is the name under which embedded host can be -// accessed on a local area network. -// Default: "my_host" -#define NET_HOST_NAME "my_host" - -// Memory Pool size <1536-262144:4><#/4> -// This is the size of a memory pool in bytes. Buffers for -// Network packets are allocated from this memory pool. -// Default: 12000 bytes -#define NET_MEM_SIZE 3000 - -// - -#include "..\RTE_Components.h" - -#ifdef RTE_Network_Interface_ETH_0 -#include "Net_Config_ETH_0.h" -#endif -#ifdef RTE_Network_Interface_ETH_1 -#include "Net_Config_ETH_1.h" -#endif - -#ifdef RTE_Network_Interface_PPP_0 -#include "Net_Config_PPP_0.h" -#endif -#ifdef RTE_Network_Interface_PPP_1 -#include "Net_Config_PPP_1.h" -#endif - -#ifdef RTE_Network_Interface_SLIP_0 -#include "Net_Config_SLIP_0.h" -#endif -#ifdef RTE_Network_Interface_SLIP_1 -#include "Net_Config_SLIP_1.h" -#endif - -#ifdef RTE_Network_Socket_UDP -#include "Net_Config_UDP.h" -#endif -#ifdef RTE_Network_Socket_TCP -#include "Net_Config_TCP.h" -#endif -#ifdef RTE_Network_Socket_BSD -#include "Net_Config_BSD.h" -#endif - -#ifdef RTE_Network_Web_Server_RO -#include "Net_Config_HTTP_Server.h" -#endif -#ifdef RTE_Network_Web_Server_FS -#include "Net_Config_HTTP_Server.h" -#endif - -#ifdef RTE_Network_Telnet_Server -#include "Net_Config_Telnet_Server.h" -#endif - -#ifdef RTE_Network_TFTP_Server -#include "Net_Config_TFTP_Server.h" -#endif -#ifdef RTE_Network_TFTP_Client -#include "Net_Config_TFTP_Client.h" -#endif - -#ifdef RTE_Network_FTP_Server -#include "Net_Config_FTP_Server.h" -#endif -#ifdef RTE_Network_FTP_Client -#include "Net_Config_FTP_Client.h" -#endif - -#ifdef RTE_Network_DNS_Client -#include "Net_Config_DNS_Client.h" -#endif - -#ifdef RTE_Network_SMTP_Client -#include "Net_Config_SMTP_Client.h" -#endif - -#ifdef RTE_Network_SNMP_Agent -#include "Net_Config_SNMP_Agent.h" -#endif - -#ifdef RTE_Network_SNTP_Client -#include "Net_Config_SNTP_Client.h" -#endif - -#include "net_config.h" - -/** -\addtogroup net_genFunc -@{ -*/ -/** - \fn void net_sys_error (ERROR_CODE error) - \ingroup net_cores - \brief Network system error handler. -*/ -void net_sys_error (ERROR_CODE error) { - /* This function is called when a fatal error is encountered. */ - /* The normal program execution is not possible anymore. */ - - switch (error) { - case ERR_MEM_ALLOC: - /* Out of memory */ - break; - - case ERR_MEM_FREE: - /* Trying to release non existing memory block */ - break; - - case ERR_MEM_CORRUPT: - /* Memory Link pointer Corrupted */ - /* More data written than the size of allocated mem block */ - break; - - case ERR_MEM_LOCK: - /* Locked Memory management function (alloc/free) re-entered */ - break; - - case ERR_UDP_ALLOC: - /* Out of UDP Sockets */ - break; - - case ERR_TCP_ALLOC: - /* Out of TCP Sockets */ - break; - - case ERR_TCP_STATE: - /* TCP State machine in undefined state */ - break; - } - - /* End-less loop */ - while (1); -} -/** -@} -*/ diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_BSD.h deleted file mode 100644 index 4166a0a2d1..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_BSD.h +++ /dev/null @@ -1,36 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_BSD.h - * Purpose: Network Configuration BSD Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Berkley (BSD) Sockets -#define BSD_ENABLE 1 - -// Number of BSD Sockets <1-20> -// Number of available Berkeley Sockets -// Default: 2 -#define BSD_NUM_SOCKS 15 - -// Number of Streaming Server Sockets <0-20> -// Defines a number of Streaming (TCP) Server sockets, -// that listen for an incoming connection from the client. -// Default: 1 -#define BSD_SERVER_SOCKS 1 - -// Receive Timeout in seconds <0-600> -// A timeout for socket receive in blocking mode. -// Timeout value of 0 means indefinite timeout. -// Default: 20 -#define BSD_RECEIVE_TOUT 20 - -// Hostname Resolver -// Enable or disable Berkeley style hostname resolver. -#define BSD_HOSTNAME_ENABLE 0 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_DNS_Client.h deleted file mode 100644 index d30b718079..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_DNS_Client.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Service - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_DNS_Client.h - * Purpose: Network Configuration DNS Client - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// DNS Client -#define DNS_CLIENT_ENABLE 1 - -// Cache Table size <5-100> -// Number of cached DNS host names/IP addresses -// Default: 20 -#define DNS_CLIENT_TAB_SIZE 20 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_ETH_0.h deleted file mode 100644 index 9a49f38210..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_ETH_0.h +++ /dev/null @@ -1,222 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Interface - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_ETH_0.h - * Purpose: Network Configuration ETH Interface - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Ethernet Network Interface 0 -#define ETH0_ENABLE 1 - -// Connect to hardware via Driver_ETH# <0-255> -// Select driver control block for MAC and PHY interface -#define ETH0_DRIVER 1 - -// MAC Address -// Local Ethernet MAC Address -// Value FF:FF:FF:FF:FF:FF is not allowed. -// It is an ethernet Broadcast MAC address. -// Address byte 1 <0x00-0xff:2> -// LSB is an ethernet Multicast bit. -// Must be 0 for local MAC address. -// Default: 0x1E -#define ETH0_MAC1 0x1E - -// Address byte 2 <0x00-0xff> -// Default: 0x30 -#define ETH0_MAC2 0x30 - -// Address byte 3 <0x00-0xff> -// Default: 0x6C -#define ETH0_MAC3 0x6C - -// Address byte 4 <0x00-0xff> -// Default: 0xA2 -#define ETH0_MAC4 0xA2 - -// Address byte 5 <0x00-0xff> -// Default: 0x45 -#define ETH0_MAC5 0x45 - -// Address byte 6 <0x00-0xff> -// Default: 0x5E -#define ETH0_MAC6 0x5E -// - -// IP Address -// Local Static IP Address -// Value 255.255.255.255 is not allowed. -// It is a Broadcast IP address. -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_IP1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_IP2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_IP3 0 - -// Address byte 4 <0-255> -// Default: 100 -#define ETH0_IP4 100 -// - -// Subnet mask -// Local Subnet mask -// Mask byte 1 <0-255> -// Default: 255 -#define ETH0_MASK1 255 - -// Mask byte 2 <0-255> -// Default: 255 -#define ETH0_MASK2 255 - -// Mask byte 3 <0-255> -// Default: 255 -#define ETH0_MASK3 255 - -// Mask byte 4 <0-255> -// Default: 0 -#define ETH0_MASK4 0 -// - -// Default Gateway -// Default Gateway IP Address -// Address byte 1 <0-255> -// Default: 192 -#define ETH0_GW1 192 - -// Address byte 2 <0-255> -// Default: 168 -#define ETH0_GW2 168 - -// Address byte 3 <0-255> -// Default: 0 -#define ETH0_GW3 0 - -// Address byte 4 <0-255> -// Default: 254 -#define ETH0_GW4 254 -// - -// Primary DNS Server -// Primary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_PRI_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_PRI_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_PRI_DNS3 2 - -// Address byte 4 <0-255> -// Default: 129 -#define ETH0_PRI_DNS4 129 -// - -// Secondary DNS Server -// Secondary DNS Server IP Address -// Address byte 1 <0-255> -// Default: 194 -#define ETH0_SEC_DNS1 194 - -// Address byte 2 <0-255> -// Default: 25 -#define ETH0_SEC_DNS2 25 - -// Address byte 3 <0-255> -// Default: 2 -#define ETH0_SEC_DNS3 2 - -// Address byte 4 <0-255> -// Default: 130 -#define ETH0_SEC_DNS4 130 -// - -// ARP Definitions -// Address Resolution Protocol Definitions -// Cache Table size <5-100> -// Number of cached hardware/IP addresses -// Default: 10 -#define ETH0_ARP_TAB_SIZE 10 - -// Cache Timeout in seconds <5-255> -// A timeout for a cached hardware/IP addresses -// Default: 150 -#define ETH0_ARP_CACHE_TOUT 150 - -// Number of Retries <0-20> -// Number of Retries to resolve an IP address -// before ARP module gives up -// Default: 4 -#define ETH0_ARP_MAX_RETRY 4 - -// Resend Timeout in seconds <1-10> -// A timeout to resend the ARP Request -// Default: 2 -#define ETH0_ARP_RESEND_TOUT 2 - -// Send Notification on Address changes -// When this option is enabled, the embedded host -// will send a Gratuitous ARP notification at startup, -// or when the device IP address has changed. -// Default: Disabled -#define ETH0_ARP_NOTIFY 0 -// - -// IGMP Group Management -// Enable or disable Internet Group Management Protocol -#define ETH0_IGMP_ENABLE 0 - -// Membership Table size <2-50> -// Number of Groups this host can join -// Default: 5 -#define ETH0_IGMP_TAB_SIZE 5 -// - -// NetBIOS Name Service -// When this option is enabled, the embedded host can be -// accessed by his name on the local LAN using NBNS protocol. -// You need to modify also the number of UDP Sockets, -// because NBNS protocol uses one UDP socket to run. -#define ETH0_NBNS_ENABLE 1 - -// Dynamic Host Configuration -// When this option is enabled, local IP address, Net Mask -// and Default Gateway are obtained automatically from -// the DHCP Server on local LAN. -// You need to modify also the number of UDP Sockets, -// because DHCP protocol uses one UDP socket to run. -#define ETH0_DHCP_ENABLE 0 - -// Vendor Class Identifier -// This value is optional. If specified, it is added -// to DHCP request message, identifying vendor type. -// Default: "" -#define ETH0_DHCP_VCID "" - -// Bootfile Name -// This value is optional. If enabled, the Bootfile Name -// (option 67) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_BOOTFILE 0 - -// NTP Servers -// This value is optional. If enabled, a list of NTP Servers -// (option 42) is also requested from DHCP server. -// Default: disabled -#define ETH0_DHCP_NTP_SERVERS 0 -// - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_TCP.h deleted file mode 100644 index 9d5b419e48..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_TCP.h +++ /dev/null @@ -1,61 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_TCP.h - * Purpose: Network Configuration TCP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// TCP Sockets -#define TCP_ENABLE 1 - -// Number of TCP Sockets <1-20> -// Number of available TCP sockets -// Default: 5 -#define TCP_NUM_SOCKS 15 - -// Number of Retries <0-20> -// How many times TCP module will try to retransmit data -// before giving up. Increase this value for high-latency -// and low_throughput networks. -// Default: 5 -#define TCP_MAX_RETRY 5 - -// Retry Timeout in seconds <1-10> -// If data frame not acknowledged within this time frame, -// TCP module will try to resend the data again. -// Default: 4 -#define TCP_RETRY_TOUT 4 - -// Default Connect Timeout in seconds <1-600> -// Default TCP Socket Keep Alive timeout. When it expires -// with no TCP data frame send, TCP Connection is closed. -// Default: 120 -#define TCP_DEFAULT_TOUT 120 - -// Maximum Segment Size <536-1460> -// The Maximum Segment Size specifies the maximum -// number of bytes in the TCP segment's Data field. -// Default: 1460 -#define TCP_MAX_SEG_SIZE 1460 - -// Receive Window Size <536-65535> -// Receive Window Size specifies the size of data, -// that the socket is able to buffer in flow-control mode. -// Default: 4380 -#define TCP_RECEIVE_WIN_SIZE 4380 - -// - -// TCP Initial Retransmit period in seconds -#define TCP_INITIAL_RETRY_TOUT 1 - -// TCP SYN frame retransmit period in seconds -#define TCP_SYN_RETRY_TOUT 2 - -// Number of retries to establish a connection -#define TCP_CONNECT_RETRY 7 - diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_UDP.h deleted file mode 100644 index 113f314a9e..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_UDP.h +++ /dev/null @@ -1,20 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network:Socket - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Config_UDP.h - * Purpose: Network Configuration UDP Sockets - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// UDP Sockets -#define UDP_ENABLE 1 - -// Number of UDP Sockets <1-20> -// Number of available UDP sockets -// Default: 5 -#define UDP_NUM_SOCKS 20 - -// diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Debug.c deleted file mode 100644 index 735089a409..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Debug.c +++ /dev/null @@ -1,125 +0,0 @@ -/*------------------------------------------------------------------------------ - * MDK Middleware - Component ::Network - * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. - *------------------------------------------------------------------------------ - * Name: Net_Debug.c - * Purpose: Network Debug Configuration - * Rev.: V5.00 - *----------------------------------------------------------------------------*/ - -//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- - -// Print Time Stamp -// Enable printing the time-info in debug messages -#define DBG_TIME 1 - -// TCPnet Debug Definitions -// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Memory debug messages -#define DBG_MEM 1 - -// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Ethernet debug messages -#define DBG_ETH 0 - -// PPP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off PPP debug messages -#define DBG_PPP 0 - -// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SLIP debug messages -#define DBG_SLIP 0 - -// ARP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ARP debug messages -#define DBG_ARP 0 - -// IP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IP debug messages -#define DBG_IP 1 - -// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off ICMP debug messages -#define DBG_ICMP 1 - -// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off IGMP debug messages -#define DBG_IGMP 1 - -// UDP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off UDP debug messages -#define DBG_UDP 1 - -// TCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TCP debug messages -#define DBG_TCP 1 - -// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off NetBIOS Name Service debug messages -#define DBG_NBNS 1 - -// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Dynamic Host Configuration debug messages -#define DBG_DHCP 1 - -// DNS Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Domain Name Service debug messages -#define DBG_DNS 1 - -// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Management debug messages -#define DBG_SNMP 1 - -// SNTP Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Simple Network Time debug messages -#define DBG_SNTP 1 - -// BSD Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off BSD Interface debug messages -#define DBG_BSD 1 -// - -// Application Debug Definitions -// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Web Server debug messages -#define DBG_HTTP_SERVER 1 - -// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Server debug messages -#define DBG_FTP_SERVER 1 - -// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off FTP Client debug messages -#define DBG_FTP_CLIENT 1 - -// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off Telnet Server debug messages -#define DBG_TELNET_SERVER 1 - -// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Server debug messages -#define DBG_TFTP_SERVER 1 - -// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off TFTP Client debug messages -#define DBG_TFTP_CLIENT 1 - -// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug -// Turn On/Off SMTP Client debug messages -#define DBG_SMTP_CLIENT 1 -// - - -#include "net_debug.h" - - -/** - \fn void net_debug_init (void) - \brief Initialize Network Debug Interface. -*/ -void net_debug_init (void) { - /* Add your code to initialize the Debug output. This is usually the */ - /* serial interface. The function is called at TCPnet system startup. */ - /* You may need to customize also the 'putchar()' function. */ - -} diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/RTE_Components.h deleted file mode 100644 index dc29d6c59e..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/RTE_Components.h +++ /dev/null @@ -1,28 +0,0 @@ - -/* - * Auto generated Run-Time-Environment Component Configuration File - * *** Do not modify ! *** - * - * Project: 'SimpleServer' - * Target: 'SimpleServer' - */ - -#ifndef RTE_COMPONENTS_H -#define RTE_COMPONENTS_H - -#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ -#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ -#define RTE_Drivers_MCI0 /* Driver MCI0 */ -#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */ -#define RTE_FileSystem_Core /* File System Core */ - #define RTE_FileSystem_LFN /* File System with Long Filename support */ -#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ -#define RTE_Network_Core /* Network Core */ - #define RTE_Network_Debug /* Network Debug Version */ -#define RTE_Network_DNS_Client /* Network DNS Client */ -#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ -#define RTE_Network_Socket_BSD /* Network Socket BSD */ -#define RTE_Network_Socket_TCP /* Network Socket TCP */ -#define RTE_Network_Socket_UDP /* Network Socket UDP */ - -#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/wolfSSL/settings.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/wolfSSL/settings.h new file mode 100644 index 0000000000..22dea06d0e --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/wolfSSL/settings.h @@ -0,0 +1,627 @@ +/* settings.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* Place OS specific preprocessor flags, defines, includes here, will be + included into every file because types.h includes it */ + + +#ifndef CTAO_CRYPT_SETTINGS_H +#define CTAO_CRYPT_SETTINGS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Uncomment next line if using IPHONE */ +/* #define IPHONE */ + +/* Uncomment next line if using ThreadX */ +/* #define THREADX */ + +/* Uncomment next line if using Micrium ucOS */ +/* #define MICRIUM */ + +/* Uncomment next line if using Mbed */ +/* #define MBED */ + +/* Uncomment next line if using Microchip PIC32 ethernet starter kit */ +/* #define MICROCHIP_PIC32 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 5 */ +/* #define MICROCHIP_TCPIP_V5 */ + +/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */ +/* #define MICROCHIP_TCPIP */ + +/* Uncomment next line if using FreeRTOS */ +/* #define FREERTOS */ + +/* Uncomment next line if using FreeRTOS Windows Simulator */ +/* #define FREERTOS_WINSIM */ + +/* Uncomment next line if using RTIP */ +/* #define EBSNET */ + +/* Uncomment next line if using lwip */ +/* #define CYASSL_LWIP */ + +/* Uncomment next line if building CyaSSL for a game console */ +/* #define CYASSL_GAME_BUILD */ + +/* Uncomment next line if building CyaSSL for LSR */ +/* #define CYASSL_LSR */ + +/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */ +/* #define FREESCALE_MQX */ + +/* Uncomment next line if using STM32F2 */ +/* #define CYASSL_STM32F2 */ + +/* Uncomment next line if using Comverge settings */ +/* #define COMVERGE */ + +/* Uncomment next line if using QL SEP settings */ +/* #define CYASSL_QL */ + + +#include + +#ifdef IPHONE + #define SIZEOF_LONG_LONG 8 +#endif + + +#ifdef COMVERGE + #define THREADX + #define HAVE_NETX + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_RSA + #define NO_SESSION_CACHE + #define HAVE_ECC +#endif + + +#ifdef THREADX + #define SIZEOF_LONG_LONG 8 +#endif + +#ifdef HAVE_NETX + #include "nx_api.h" +#endif + +#ifdef MICROCHIP_PIC32 + #define SIZEOF_LONG_LONG 8 + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_FILESYSTEM + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT +#endif + +#ifdef MICROCHIP_TCPIP_V5 + /* include timer functions */ + #include "TCPIP Stack/TCPIP.h" +#endif + +#ifdef MICROCHIP_TCPIP + /* include timer, NTP functions */ + #include "system/system_services.h" + #ifdef MICROCHIP_MPLAB_HARMONY + #include "tcpip/tcpip.h" + #else + #include "tcpip/sntp.h" + #endif +#endif + +#ifdef MBED + #define SINGLE_THREADED + #define CYASSL_USER_IO + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 +#endif /* MBED */ + +#ifdef CYASSL_TYTO + #include "rand.h" + #define FREERTOS + #define NO_FILESYSTEM + #define CYASSL_USER_IO + #define NO_DEV_RANDOM + #define HAVE_ECC + #define HAVE_ECC_ENCRYPT + #define ECC_SHAMIR + #define HAVE_HKDF + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FP_MAX_BITS 512 + #define NO_OLD_TLS + #define NO_MD4 + #define NO_RABBIT + #define NO_HC128 + #define NO_RSA + #define NO_DSA + #define NO_PWDBASED + #define NO_PSK +#endif + +#ifdef FREERTOS_WINSIM + #define FREERTOS + #define USE_WINDOWS_API +#endif + + +/* Micrium will use Visual Studio for compilation but not the Win32 API */ +#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \ + && !defined(EBSNET) + #define USE_WINDOWS_API +#endif + + +#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER) + #include + #define XMALLOC(s, h, type) malloc((s)) + #define XFREE(p, h, type) free((p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + +#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL) + #undef XMALLOC + #define XMALLOC yaXMALLOC + #undef XFREE + #define XFREE yaXFREE + #undef XREALLOC + #define XREALLOC yaXREALLOC +#endif + + +#ifdef FREERTOS + #ifndef NO_WRITEV + #define NO_WRITEV + #endif + #ifndef NO_SHA512 + #define NO_SHA512 + #endif + #ifndef NO_DH + #define NO_DH + #endif + #ifndef NO_DSA + #define NO_DSA + #endif + #ifndef NO_HC128 + #define NO_HC128 + #endif + + #ifndef SINGLE_THREADED + #include "FreeRTOS.h" + #include "semphr.h" + #endif +#endif + +#ifdef EBSNET + #include "rtip.h" + + /* #define DEBUG_CYASSL */ + #define NO_CYASSL_DIR /* tbd */ + + #if (POLLOS) + #define SINGLE_THREADED + #endif + + #if (RTPLATFORM) + #if (!RTP_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #else + #if (!KS_LITTLE_ENDIAN) + #define BIG_ENDIAN_ORDER + #endif + #endif + + #if (WINMSP3) + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #else + #sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG + #endif + + #define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC)) + #define XFREE(p, h, type) (rtp_free(p)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) + +#endif /* EBSNET */ + +#ifdef CYASSL_GAME_BUILD + #define SIZEOF_LONG_LONG 8 + #if defined(__PPU) || defined(__XENON) + #define BIG_ENDIAN_ORDER + #endif +#endif + +#ifdef CYASSL_LSR + #define HAVE_WEBSERVER + #define SIZEOF_LONG_LONG 8 + #define CYASSL_LOW_MEMORY + #define NO_WRITEV + #define NO_SHA512 + #define NO_DH + #define NO_DSA + #define NO_HC128 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #ifndef NO_FILESYSTEM + #define LSR_FS + #include "inc/hw_types.h" + #include "fs.h" + #endif + #define CYASSL_LWIP + #include /* for tcp errno */ + #define CYASSL_SAFERTOS + #if defined(__IAR_SYSTEMS_ICC__) + /* enum uses enum */ + #pragma diag_suppress=Pa089 + #endif +#endif + +#ifdef CYASSL_SAFERTOS + #ifndef SINGLE_THREADED + #include "SafeRTOS/semphr.h" + #endif + + #include "SafeRTOS/heap.h" + #define XMALLOC(s, h, type) pvPortMalloc((s)) + #define XFREE(p, h, type) vPortFree((p)) + #define XREALLOC(p, n, h, t) pvPortRealloc((p), (n)) +#endif + +#ifdef CYASSL_LOW_MEMORY + #undef RSA_LOW_MEM + #define RSA_LOW_MEM + #undef CYASSL_SMALL_STACK + #define CYASSL_SMALL_STACK + #undef TFM_TIMING_RESISTANT + #define TFM_TIMING_RESISTANT +#endif + +#ifdef FREESCALE_MQX + #define SIZEOF_LONG_LONG 8 + #define NO_WRITEV + #define NO_DEV_RANDOM + #define NO_RABBIT + #define NO_CYASSL_DIR + #define USE_FAST_MATH + #define TFM_TIMING_RESISTANT + #define FREESCALE_K70_RNGA + /* #define FREESCALE_K53_RNGB */ + #include "mqx.h" + #ifndef NO_FILESYSTEM + #include "mfs.h" + #include "fio.h" + #endif + #ifndef SINGLE_THREADED + #include "mutex.h" + #endif + + #define XMALLOC(s, h, t) (void *)_mem_alloc_system((s)) + #define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));} + /* Note: MQX has no realloc, using fastmath above */ +#endif + +#ifdef CYASSL_STM32F2 + #define SIZEOF_LONG_LONG 8 + #define NO_DEV_RANDOM + #define NO_CYASSL_DIR + #define NO_RABBIT + #define STM32F2_RNG + #define STM32F2_CRYPTO + #define KEIL_INTRINSICS +#endif + +#ifdef MICRIUM + + #include "stdlib.h" + #include "net_cfg.h" + #include "ssl_cfg.h" + #include "net_secure_os.h" + + #define CYASSL_TYPES + + typedef CPU_INT08U byte; + typedef CPU_INT16U word16; + typedef CPU_INT32U word32; + + #if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32) + #define SIZEOF_LONG 4 + #undef SIZEOF_LONG_LONG + #else + #undef SIZEOF_LONG + #define SIZEOF_LONG_LONG 8 + #endif + + #define STRING_USER + + #define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr))) + #define XSTRNCPY(pstr_dest, pstr_src, len_max) \ + ((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \ + (CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max))) + #define XSTRNCMP(pstr_1, pstr_2, len_max) \ + ((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \ + (CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max))) + #define XSTRSTR(pstr, pstr_srch) \ + ((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \ + (CPU_CHAR *)(pstr_srch))) + #define XMEMSET(pmem, data_val, size) \ + ((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \ + (CPU_SIZE_T)(size))) + #define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \ + (void *)(psrc), (CPU_SIZE_T)(size))) + #define XMEMCMP(pmem_1, pmem_2, size) \ + (((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \ + (CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES) + #define XMEMMOVE XMEMCPY + +#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED) + #define MICRIUM_MALLOC + #define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \ + (CPU_SIZE_T)(s), (void *)0)) + #define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \ + (p), (void *)0)) + #define XREALLOC(p, n, h, t) realloc((p), (n)) +#endif + + #if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED) + #undef NO_FILESYSTEM + #else + #define NO_FILESYSTEM + #endif + + #if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG) + #define DEBUG_CYASSL + #else + #undef DEBUG_CYASSL + #endif + + #if (SSL_CFG_OPENSSL_EN == DEF_ENABLED) + #define OPENSSL_EXTRA + #else + #undef OPENSSL_EXTRA + #endif + + #if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED) + #undef SINGLE_THREADED + #else + #define SINGLE_THREADED + #endif + + #if (SSL_CFG_DH_EN == DEF_ENABLED) + #undef NO_DH + #else + #define NO_DH + #endif + + #if (SSL_CFG_DSA_EN == DEF_ENABLED) + #undef NO_DSA + #else + #define NO_DSA + #endif + + #if (SSL_CFG_PSK_EN == DEF_ENABLED) + #undef NO_PSK + #else + #define NO_PSK + #endif + + #if (SSL_CFG_3DES_EN == DEF_ENABLED) + #undef NO_DES + #else + #define NO_DES + #endif + + #if (SSL_CFG_AES_EN == DEF_ENABLED) + #undef NO_AES + #else + #define NO_AES + #endif + + #if (SSL_CFG_RC4_EN == DEF_ENABLED) + #undef NO_RC4 + #else + #define NO_RC4 + #endif + + #if (SSL_CFG_RABBIT_EN == DEF_ENABLED) + #undef NO_RABBIT + #else + #define NO_RABBIT + #endif + + #if (SSL_CFG_HC128_EN == DEF_ENABLED) + #undef NO_HC128 + #else + #define NO_HC128 + #endif + + #if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG) + #define BIG_ENDIAN_ORDER + #else + #undef BIG_ENDIAN_ORDER + #define LITTLE_ENDIAN_ORDER + #endif + + #if (SSL_CFG_MD4_EN == DEF_ENABLED) + #undef NO_MD4 + #else + #define NO_MD4 + #endif + + #if (SSL_CFG_WRITEV_EN == DEF_ENABLED) + #undef NO_WRITEV + #else + #define NO_WRITEV + #endif + + #if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED) + #define NO_DEV_RANDOM + #else + #undef NO_DEV_RANDOM + #endif + + #if (SSL_CFG_USER_IO_EN == DEF_ENABLED) + #define CYASSL_USER_IO + #else + #undef CYASSL_USER_IO + #endif + + #if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED) + #undef LARGE_STATIC_BUFFERS + #undef STATIC_CHUNKS_ONLY + #else + #define LARGE_STATIC_BUFFERS + #define STATIC_CHUNKS_ONLY + #endif + + #if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED) + #define CYASSL_DER_LOAD + #else + #undef CYASSL_DER_LOAD + #endif + + #if (SSL_CFG_DTLS_EN == DEF_ENABLED) + #define CYASSL_DTLS + #else + #undef CYASSL_DTLS + #endif + + #if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED) + #define CYASSL_CALLBACKS + #else + #undef CYASSL_CALLBACKS + #endif + + #if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED) + #define USE_FAST_MATH + #else + #undef USE_FAST_MATH + #endif + + #if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED) + #define TFM_TIMING_RESISTANT + #else + #undef TFM_TIMING_RESISTANT + #endif + +#endif /* MICRIUM */ + + +#ifdef CYASSL_QL + #ifndef CYASSL_SEP + #define CYASSL_SEP + #endif + #ifndef OPENSSL_EXTRA + #define OPENSSL_EXTRA + #endif + #ifndef SESSION_CERTS + #define SESSION_CERTS + #endif + #ifndef HAVE_AESCCM + #define HAVE_AESCCM + #endif + #ifndef ATOMIC_USER + #define ATOMIC_USER + #endif + #ifndef CYASSL_DER_LOAD + #define CYASSL_DER_LOAD + #endif + #ifndef KEEP_PEER_CERT + #define KEEP_PEER_CERT + #endif + #ifndef HAVE_ECC + #define HAVE_ECC + #endif + #ifndef SESSION_INDEX + #define SESSION_INDEX + #endif +#endif /* CYASSL_QL */ + + +#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \ + !defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY) + #define USE_CYASSL_MEMORY +#endif + + +#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS) + #undef KEEP_PEER_CERT + #define KEEP_PEER_CERT +#endif + + +/* stream ciphers except arc4 need 32bit alignment, intel ok without */ +#ifndef XSTREAM_ALIGNMENT + #if defined(__x86_64__) || defined(__ia64__) || defined(__i386__) + #define NO_XSTREAM_ALIGNMENT + #else + #define XSTREAM_ALIGNMENT + #endif +#endif + + +/* if using hardware crypto and have alignment requirements, specify the + requirement here. The record header of SSL/TLS will prvent easy alignment. + This hint tries to help as much as possible. */ +#ifndef CYASSL_GENERAL_ALIGNMENT + #ifdef CYASSL_AESNI + #define CYASSL_GENERAL_ALIGNMENT 16 + #elif defined(XSTREAM_ALIGNMENT) + #define CYASSL_GENERAL_ALIGNMENT 4 + #else + #define CYASSL_GENERAL_ALIGNMENT 0 + #endif +#endif + +#ifdef HAVE_CRL + /* not widely supported yet */ + #undef NO_SKID + #define NO_SKID +#endif + +/* Place any other flags or defines here */ + + +#ifdef __cplusplus + } /* extern "C" */ +#endif + + +#endif /* CTAO_CRYPT_SETTINGS_H */ + diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/SimpleServer/STM32_SWO.ini deleted file mode 100644 index 239abce37b..0000000000 --- a/IDE/MDK5-ARM/Projects/SimpleServer/STM32_SWO.ini +++ /dev/null @@ -1,36 +0,0 @@ -/******************************************************************************/ -/* STM32_SWO.ini: STM32 Debugger Initialization File */ -/******************************************************************************/ -// <<< Use Configuration Wizard in Context Menu >>> // -/******************************************************************************/ -/* This file is part of the uVision/ARM development tools. */ -/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ -/* This software may only be used under the terms of a valid, current, */ -/* end user licence from KEIL for a compatible version of KEIL software */ -/* development tools. Nothing else gives you the right to use this software. */ -/******************************************************************************/ - - -FUNC void DebugSetup (void) { -// Debug MCU Configuration -// DBG_SLEEP Debug Sleep Mode -// DBG_STOP Debug Stop Mode -// DBG_STANDBY Debug Standby Mode -// TRACE_IOEN Trace I/O Enable -// TRACE_MODE Trace Mode -// <0=> Asynchronous -// <1=> Synchronous: TRACEDATA Size 1 -// <2=> Synchronous: TRACEDATA Size 2 -// <3=> Synchronous: TRACEDATA Size 4 -// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted -// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted -// DBG_TIM1_STOP Timer 1 Stopped when Core is halted -// DBG_TIM2_STOP Timer 2 Stopped when Core is halted -// DBG_TIM3_STOP Timer 3 Stopped when Core is halted -// DBG_TIM4_STOP Timer 4 Stopped when Core is halted -// DBG_CAN_STOP CAN Stopped when Core is halted -// - _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR -} - -DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx index b3a8b8dbb7..dcd3ae74a5 100644 --- a/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx +++ b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx @@ -76,6 +76,23 @@ 1 255 + + + 0 + Schematics (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200-schematics.pdf + + + 1 + User Manual (MCBSTM32F200) + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\Documents\mcbstm32f200.chm + + + 2 + MCBSTM32F200 Evaluation Board Web Page (MCBSTM32F200) + http://www.keil.com/mcbstm32f200/ + + SARMCM3.DLL -REMAP -MPU @@ -104,6 +121,8 @@ 0 1 1 + 1 + 1 0 0 8 @@ -116,7 +135,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -197,7 +216,7 @@ Source - 1 + 0 0 0 0 @@ -207,10 +226,10 @@ 1 0 0 - 4 + 0 0 - 0 - 0 + 37 + 44 0 .\main.c main.c @@ -223,7 +242,7 @@ 1 0 0 - 4 + 33 0 0 0 @@ -273,24 +292,56 @@ 0 0 - - - - Documentation - 1 - 0 - 0 - 0 - 3 + 2 5 5 0 0 + 33 + 0 + 0 + 0 + 0 + .\RTE\Network\Net_Config_ETH_0.h + Net_Config_ETH_0.h + 0 + 0 + + + 2 + 6 + 5 + 0 + 0 0 0 - 1 - 1 + 0 + 0 + 0 + .\config-SimpleServer.h + config-SimpleServer.h + 0 + 0 + + + + + Documentation + 0 + 0 + 0 + 0 + + 3 + 7 + 5 + 0 + 0 + 0 + 0 + 0 + 0 0 .\Abstract.txt Abstract.txt @@ -299,6 +350,30 @@ + + Devices + 1 + 0 + 0 + 0 + + 4 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\time-dummy.c + time-dummy.c + 0 + 0 + + + ::CMSIS 0 @@ -306,8 +381,24 @@ 0 1 - 4 - 6 + 5 + 9 + 1 + 0 + 0 + 0 + 0 + 212 + 218 + 0 + RTE\CMSIS\RTX_Conf_CM.c + RTX_Conf_CM.c + 1 + 0 + + + 5 + 10 4 0 0 @@ -316,27 +407,11 @@ 0 0 0 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib RTX_CM3.lib 1 0 - - 4 - 7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RTE\CMSIS\RTX_Conf_CM.c - RTX_Conf_CM.c - 1 - 0 - @@ -346,40 +421,8 @@ 0 1 - 5 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - DMA_STM32F2xx.c - 1 - 0 - - - 5 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - GPIO_STM32F2xx.c - 1 - 0 - - - 5 - 10 + 6 + 11 5 0 0 @@ -394,45 +437,21 @@ 0 - 5 - 11 + 6 + 12 2 0 0 0 0 - 0 - 0 + 164 + 169 0 RTE\Device\STM32F207IG\startup_stm32f2xx.s startup_stm32f2xx.s 1 0 - - 5 - 12 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - RTE\Device\STM32F207IG\system_stm32f2xx.c - system_stm32f2xx.c - 1 - 0 - - - - - ::Drivers - 0 - 0 - 0 - 1 6 13 @@ -444,8 +463,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c - PHY_ST802RT1.c + RTE\Device\STM32F207IG\system_stm32f2xx.c + system_stm32f2xx.c 1 0 @@ -460,8 +479,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c - EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + DMA_STM32F2xx.c 1 0 @@ -476,15 +495,15 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c - MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + GPIO_STM32F2xx.c 1 0 - ::File System + ::Drivers 0 0 0 @@ -492,7 +511,7 @@ 7 16 - 4 + 1 0 0 0 @@ -500,8 +519,8 @@ 0 0 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_LFN_CM3_L.lib + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c + PHY_ST802RT1.c 1 0 @@ -516,14 +535,54 @@ 0 0 0 - RTE\File_System\FS_Config.c - FS_Config.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c + EMAC_STM32F2xx.c 1 0 7 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c + MCI_STM32F2xx.c + 1 + 0 + + + + + ::File System + 0 + 0 + 0 + 1 + + 8 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + RTE\File_System\FS_Config.c + FS_Config.c + 1 + 0 + + + 8 + 20 5 0 0 @@ -537,6 +596,22 @@ 1 0 + + 8 + 21 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + FS_LFN_CM3_L.lib + 1 + 0 + @@ -546,24 +621,8 @@ 0 1 - 8 - 19 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Dbg_CM3_L.lib - 1 - 0 - - - 8 - 20 + 9 + 22 1 0 0 @@ -578,8 +637,8 @@ 0 - 8 - 21 + 9 + 23 5 0 0 @@ -594,8 +653,8 @@ 0 - 8 - 22 + 9 + 24 5 0 0 @@ -610,12 +669,12 @@ 0 - 8 - 23 + 9 + 25 5 0 0 - 0 + 33 0 0 0 @@ -626,8 +685,8 @@ 0 - 8 - 24 + 9 + 26 5 0 0 @@ -642,8 +701,8 @@ 0 - 8 - 25 + 9 + 27 5 0 0 @@ -658,18 +717,34 @@ 0 - 8 - 26 + 9 + 28 1 0 0 + 33 + 0 + 0 + 0 + 0 + RTE\Network\Net_Debug.c + Net_Debug.c + 1 + 0 + + + 9 + 29 + 4 + 0 + 0 0 0 0 0 0 - RTE\Network\Net_Debug.c - Net_Debug.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + Net_Dbg_CM3_L.lib 1 0 @@ -682,680 +757,8 @@ 0 1 - 9 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - cyassl_MDK_ARM.c - 1 - 0 - - - 9 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - time-STM32F2xx.c - 1 - 0 - - - 9 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - aes.c - 1 - 0 - - - 9 + 10 30 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - arc4.c - 1 - 0 - - - 9 - 31 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - asm.c - 1 - 0 - - - 9 - 32 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - asn.c - 1 - 0 - - - 9 - 33 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - blake2b.c - 1 - 0 - - - 9 - 34 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - camellia.c - 1 - 0 - - - 9 - 35 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - coding.c - 1 - 0 - - - 9 - 36 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - compress.c - 1 - 0 - - - 9 - 37 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - des3.c - 1 - 0 - - - 9 - 38 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - dh.c - 1 - 0 - - - 9 - 39 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - dsa.c - 1 - 0 - - - 9 - 40 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - ecc.c - 1 - 0 - - - 9 - 41 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - ecc_fp.c - 1 - 0 - - - 9 - 42 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - error.c - 1 - 0 - - - 9 - 43 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - hc128.c - 1 - 0 - - - 9 - 44 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - hmac.c - 1 - 0 - - - 9 - 45 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - integer.c - 1 - 0 - - - 9 - 46 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - logging.c - 1 - 0 - - - 9 - 47 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - md2.c - 1 - 0 - - - 9 - 48 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - md4.c - 1 - 0 - - - 9 - 49 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - md5.c - 1 - 0 - - - 9 - 50 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - memory.c - 1 - 0 - - - 9 - 51 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - misc.c - 1 - 0 - - - 9 - 52 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - pwdbased.c - 1 - 0 - - - 9 - 53 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - rabbit.c - 1 - 0 - - - 9 - 54 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - random.c - 1 - 0 - - - 9 - 55 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - ripemd.c - 1 - 0 - - - 9 - 56 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - rsa.c - 1 - 0 - - - 9 - 57 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - sha.c - 1 - 0 - - - 9 - 58 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - sha256.c - 1 - 0 - - - 9 - 59 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - sha512.c - 1 - 0 - - - 9 - 60 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - tfm.c - 1 - 0 - - - 9 - 61 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - crl.c - 1 - 0 - - - 9 - 62 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - internal.c - 1 - 0 - - - 9 - 63 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - io.c - 1 - 0 - - - 9 - 64 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - keys.c - 1 - 0 - - - 9 - 65 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - ocsp.c - 1 - 0 - - - 9 - 66 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - sniffer.c - 1 - 0 - - - 9 - 67 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - ssl.c - 1 - 0 - - - 9 - 68 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - tls.c - 1 - 0 - - - 9 - 69 5 0 0 @@ -1370,8 +773,8 @@ 0 - 9 - 70 + 10 + 31 5 0 0 @@ -1386,8 +789,8 @@ 0 - 9 - 71 + 10 + 32 5 0 0 @@ -1396,8 +799,680 @@ 0 0 0 - RTE\wolfSSL\config.h - config.h + RTE\wolfSSL\settings.h + settings.h + 1 + 0 + + + 10 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + cyassl_MDK_ARM.c + 1 + 0 + + + 10 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + aes.c + 1 + 0 + + + 10 + 35 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + arc4.c + 1 + 0 + + + 10 + 36 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + asm.c + 1 + 0 + + + 10 + 37 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + asn.c + 1 + 0 + + + 10 + 38 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + blake2b.c + 1 + 0 + + + 10 + 39 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + camellia.c + 1 + 0 + + + 10 + 40 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + coding.c + 1 + 0 + + + 10 + 41 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + compress.c + 1 + 0 + + + 10 + 42 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + des3.c + 1 + 0 + + + 10 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + dh.c + 1 + 0 + + + 10 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + dsa.c + 1 + 0 + + + 10 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + ecc.c + 1 + 0 + + + 10 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c + 1 + 0 + + + 10 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + error.c + 1 + 0 + + + 10 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + hc128.c + 1 + 0 + + + 10 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + hmac.c + 1 + 0 + + + 10 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + integer.c + 1 + 0 + + + 10 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + logging.c + 1 + 0 + + + 10 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + md2.c + 1 + 0 + + + 10 + 53 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + md4.c + 1 + 0 + + + 10 + 54 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + md5.c + 1 + 0 + + + 10 + 55 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + memory.c + 1 + 0 + + + 10 + 56 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + misc.c + 1 + 0 + + + 10 + 57 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + port.c + 1 + 0 + + + 10 + 58 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 10 + 59 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 10 + 60 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 10 + 61 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 10 + 62 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 10 + 63 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 10 + 64 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 10 + 65 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 10 + 66 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 10 + 67 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + crl.c + 1 + 0 + + + 10 + 68 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + internal.c + 1 + 0 + + + 10 + 69 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + io.c + 1 + 0 + + + 10 + 70 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + keys.c + 1 + 0 + + + 10 + 71 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + ocsp.c + 1 + 0 + + + 10 + 72 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + sniffer.c + 1 + 0 + + + 10 + 73 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + ssl.c + 1 + 0 + + + 10 + 74 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c + tls.c 1 0 diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx index d354efbe42..156a9906d0 100644 --- a/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx +++ b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx @@ -139,6 +139,8 @@ 0 1 1 + 1 + 1 0 8 @@ -154,7 +156,7 @@ - .\STM32_SWO.ini + BIN\ULP2CM3.DLL @@ -353,9 +355,11 @@ 0 0 0 + 0 + 0 - HAVE_CONFIG_H MDK_CONF_SimpleServer CYASSL_STM32F2xx + HAVE_CONFIG_H MDK_CONF_SimpleServer @@ -369,6 +373,7 @@ 0 0 0 + 0 @@ -385,6 +390,7 @@ 0 0x08000000 0x20000000 + @@ -423,6 +429,16 @@ 5 .\RTE\wolfSSL\config-Crypt.h + + Net_Config_ETH_0.h + 5 + .\RTE\Network\Net_Config_ETH_0.h + + + config-SimpleServer.h + 5 + .\config-SimpleServer.h + @@ -436,33 +452,33 @@ - ::CMSIS + Devices - RTX_CM3.lib - 4 - C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + time-dummy.c + 1 + .\time-dummy.c + + + + ::CMSIS + RTX_Conf_CM.c 1 RTE\CMSIS\RTX_Conf_CM.c + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.4\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + ::Device - - DMA_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c - - - GPIO_STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c - RTE_Device.h 5 @@ -478,6 +494,16 @@ 1 RTE\Device\STM32F207IG\system_stm32f2xx.c + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\GPIO_STM32F2xx.c + @@ -486,28 +512,23 @@ PHY_ST802RT1.c 1 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Driver\PHY_ST802RT1.c EMAC_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\EMAC_STM32F2xx.c MCI_STM32F2xx.c 1 - C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.7\RTE_Driver\MCI_STM32F2xx.c ::File System - - FS_LFN_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib - FS_Config.c 1 @@ -518,16 +539,16 @@ 5 RTE\File_System\FS_Config_MC_0.h + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + ::Network - - Net_Dbg_CM3_L.lib - 4 - C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib - Net_Config.c 1 @@ -563,221 +584,16 @@ 1 RTE\Network\Net_Debug.c + + Net_Dbg_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.4\Network\Lib\ARM\Net_Dbg_CM3_L.lib + ::wolfSSL - - cyassl_MDK_ARM.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c - - - time-STM32F2xx.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c - - - aes.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c - - - arc4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c - - - asm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c - - - asn.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c - - - blake2b.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c - - - camellia.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c - - - coding.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c - - - compress.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c - - - des3.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c - - - dh.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c - - - dsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c - - - ecc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c - - - ecc_fp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c - - - error.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c - - - hc128.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c - - - hmac.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c - - - integer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c - - - logging.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c - - - md2.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c - - - md4.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c - - - md5.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c - - - memory.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c - - - misc.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c - - - pwdbased.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c - - - rabbit.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c - - - random.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c - - - ripemd.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c - - - rsa.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c - - - sha.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c - - - sha256.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c - - - sha512.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c - - - tfm.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c - - - crl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c - - - internal.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c - - - io.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c - - - keys.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c - - - ocsp.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c - - - sniffer.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c - - - ssl.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c - - - tls.c - 1 - C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c - config-Crypt.h 5 @@ -789,9 +605,219 @@ RTE\wolfSSL\config-CyaSSL.h - config.h + settings.h 5 - RTE\wolfSSL\config.h + RTE\wolfSSL\settings.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\IDE\MDK5-ARM\Src\cyassl_MDK_ARM.c + + + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\ctaocrypt\src\tfm.c + + + crl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\crl.c + + + internal.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\internal.c + + + io.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\io.c + + + keys.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\keys.c + + + ocsp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ocsp.c + + + sniffer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\sniffer.c + + + ssl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\ssl.c + + + tls.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\3.0.0\cyassl\src\tls.c @@ -801,25 +827,25 @@ - + - + - + - + @@ -833,20 +859,20 @@ - - + + - - + + - - + + @@ -923,20 +949,14 @@ - - + + - - - - - - - - + + @@ -945,8 +965,8 @@ RTE\CMSIS\RTX_Conf_CM.c - - + + @@ -1071,26 +1091,32 @@ - + RTE\wolfSSL\config-Crypt.h - - + + - + RTE\wolfSSL\config-CyaSSL.h - - + + - RTE\wolfSSL\config.h - - + RTE\wolfSSL\config.h + + + + + + RTE\wolfSSL\settings.h + + diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/config-SimpleServer.h b/IDE/MDK5-ARM/Projects/SimpleServer/config-SimpleServer.h new file mode 100644 index 0000000000..19685ee09b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleServer/config-SimpleServer.h @@ -0,0 +1,31 @@ +/* config-RTX-TCP-FS.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + + +// <<< Use Configuration Wizard in Context Menu >>> +// Build Target: Simple Server +// Listen Port Number +// Default: "11111" +#define CYASSL_LISTEN_PORT "443" + +// +// <<< end of configuration section >>> diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/main.c b/IDE/MDK5-ARM/Projects/SimpleServer/main.c index 76c1d72fa9..053ff48bdf 100644 --- a/IDE/MDK5-ARM/Projects/SimpleServer/main.c +++ b/IDE/MDK5-ARM/Projects/SimpleServer/main.c @@ -33,6 +33,8 @@ #include "cyassl_MDK_ARM.h" #include +#include "config-SimpleServer.h" + /*----------------------------------------------------------------------------- * Initialize a Flash Memory Card *----------------------------------------------------------------------------*/ @@ -82,10 +84,9 @@ char* myoptarg = NULL; int main() { - static char *argv[] = { "client", ""} ; - static func_args args = { 2, argv } ; + static char *argv[] = { "server", "-p", CYASSL_LISTEN_PORT, "-d"} ; + static func_args args = { 4, argv } ; - init_time() ; init_filesystem (); net_initialize() ; osThreadCreate (osThread (tcp_poll), NULL); diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/server.c b/IDE/MDK5-ARM/Projects/SimpleServer/server.c index bcb9f0475d..a42581d900 100644 --- a/IDE/MDK5-ARM/Projects/SimpleServer/server.c +++ b/IDE/MDK5-ARM/Projects/SimpleServer/server.c @@ -31,20 +31,19 @@ #endif #if defined(CYASSL_MDK_ARM) - #include - #include - - #if defined(CYASSL_MDK5) - #include "cmsis_os.h" - #include "rl_fs.h" - #include "rl_net.h" - #else - #include "rtl.h" - #endif - - #include "cyassl_MDK_ARM.h" -#endif + #include + #include + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif #include #include @@ -131,12 +130,14 @@ static void Usage(void) printf("-f Fewer packets/group messages\n"); printf("-N Use Non-blocking sockets\n"); printf("-S Use Host Name Indication\n"); -} - -#ifdef CYASSL_MDK_SHELL -#define exit(code) return(code) +#ifdef HAVE_OCSP + printf("-o Perform OCSP lookup on peer certificate\n"); + printf("-O Perform OCSP lookup using as responder\n"); #endif - +#ifdef HAVE_PK_CALLBACKS + printf("-P Public Key Callbacks\n"); +#endif +} THREAD_RETURN CYASSL_THREAD server_test(void* args) { @@ -154,13 +155,14 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) int version = SERVER_DEFAULT_VERSION; int doCliCertCheck = 1; int useAnyAddr = 0; - int port = yasslPort; + word16 port = yasslPort; int usePsk = 0; int doDTLS = 0; int useNtruKey = 0; int nonBlocking = 0; int trackMemory = 0; int fewerPackets = 0; + int pkCallbacks = 0; char* cipherList = NULL; char* verifyCert = (char*)cliCert; char* ourCert = (char*)svrCert; @@ -172,6 +174,11 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) char* sniHostName = NULL; #endif +#ifdef HAVE_OCSP + int useOcsp = 0; + char* ocspUrl = NULL; +#endif + ((func_args*)args)->return_code = -1; /* error state */ #ifdef NO_RSA @@ -180,8 +187,9 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) ourKey = (char*)eccKey; #endif (void)trackMemory; + (void)pkCallbacks; - while ((ch = mygetopt(argc, argv, "?dbstnNufp:v:l:A:c:k:S:")) != -1) { + while ((ch = mygetopt(argc, argv, "?dbstnNufPp:v:l:A:c:k:S:oO:")) != -1) { switch (ch) { case '?' : Usage(); @@ -217,8 +225,14 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) fewerPackets = 1; break; + case 'P' : + #ifdef HAVE_PK_CALLBACKS + pkCallbacks = 1; + #endif + break; + case 'p' : - port = atoi(myoptarg); + port = (word16)atoi(myoptarg); #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API) if (port == 0) err_sys("port number cannot be 0"); @@ -259,6 +273,19 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) #endif break; + case 'o' : + #ifdef HAVE_OCSP + useOcsp = 1; + #endif + break; + + case 'O' : + #ifdef HAVE_OCSP + useOcsp = 1; + ocspUrl = myoptarg; + #endif + break; + default: Usage(); exit(MY_EX_USAGE); @@ -349,6 +376,10 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) if (fewerPackets) CyaSSL_CTX_set_group_messages(ctx); +#if defined(OPENSSL_EXTRA) || defined(HAVE_WEBSERVER) + SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + #if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) if (!usePsk) { if (SSL_CTX_use_certificate_file(ctx, ourCert, SSL_FILETYPE_PEM) @@ -371,8 +402,8 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) if (!useNtruKey && !usePsk) { if (SSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM) != SSL_SUCCESS) - err_sys("can't load server cert file, check file and run from" - " CyaSSL home dir"); + err_sys("can't load server private key file, check file and run " + "from CyaSSL home dir"); } #endif @@ -403,10 +434,6 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) } #endif -#ifdef OPENSSL_EXTRA - SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); -#endif - #if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC) /* don't use EDH, can't sniff tmp keys */ if (cipherList == NULL) { @@ -416,27 +443,38 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) #endif #ifdef HAVE_SNI - if (sniHostName) { + if (sniHostName) if (CyaSSL_CTX_UseSNI(ctx, CYASSL_SNI_HOST_NAME, sniHostName, XSTRLEN(sniHostName)) != SSL_SUCCESS) err_sys("UseSNI failed"); - else - CyaSSL_CTX_SNI_SetOptions(ctx, CYASSL_SNI_HOST_NAME, - CYASSL_SNI_ABORT_ON_MISMATCH); - } #endif ssl = SSL_new(ctx); if (ssl == NULL) err_sys("unable to get SSL"); - CyaSSL_set_quiet_shutdown(ssl, 1) ; + #ifdef HAVE_CRL CyaSSL_EnableCRL(ssl, 0); CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, CYASSL_CRL_MONITOR | CYASSL_CRL_START_MON); CyaSSL_SetCRL_Cb(ssl, CRL_CallBack); #endif - osDelay(5000) ; +#ifdef HAVE_OCSP + if (useOcsp) { + if (ocspUrl != NULL) { + CyaSSL_CTX_SetOCSP_OverrideURL(ctx, ocspUrl); + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE + | CYASSL_OCSP_URL_OVERRIDE); + } + else + CyaSSL_CTX_EnableOCSP(ctx, CYASSL_OCSP_NO_NONCE); + } +#endif +#ifdef HAVE_PK_CALLBACKS + if (pkCallbacks) + SetupPkCallbacks(ctx, ssl); +#endif + tcp_accept(&sockfd, &clientfd, (func_args*)args, port, useAnyAddr, doDTLS); if (!doDTLS) CloseSocket(sockfd); @@ -449,7 +487,7 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) SetDH(ssl); /* repick suites with DHE, higher priority than PSK */ #endif } - osDelay(5000) ; + #ifndef CYASSL_CALLBACKS if (nonBlocking) { CyaSSL_set_using_nonblock(ssl, 1); @@ -457,7 +495,7 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) NonBlockingSSL_Accept(ssl); } else if (SSL_accept(ssl) != SSL_SUCCESS) { int err = SSL_get_error(ssl, 0); - char buffer[80]; + char buffer[CYASSL_MAX_ERROR_SZ]; printf("error = %d, %s\n", err, ERR_error_string(err, buffer)); err_sys("SSL_accept failed"); } @@ -465,7 +503,7 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) NonBlockingSSL_Accept(ssl); #endif showPeer(ssl); - osDelay(5000) ; + idx = SSL_read(ssl, input, sizeof(input)-1); if (idx > 0) { input[idx] = 0; @@ -481,6 +519,10 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) if (SSL_write(ssl, msg, sizeof(msg)) != sizeof(msg)) err_sys("SSL_write failed"); + #if defined(CYASSL_MDK_SHELL) && defined(HAVE_MDK_RTX) + os_dly_wait(500) ; + #endif + SSL_shutdown(ssl); SSL_free(ssl); SSL_CTX_free(ctx); @@ -519,8 +561,10 @@ THREAD_RETURN CYASSL_THREAD server_test(void* args) #if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) CyaSSL_Debugging_ON(); #endif - if (CurrentDir("server") || CurrentDir("build")) + if (CurrentDir("server")) ChangeDirBack(2); + else if (CurrentDir("Debug") || CurrentDir("Release")) + ChangeDirBack(3); #ifdef HAVE_STACK_SIZE StackSizeCheck(&args, server_test); diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/time-dummy.c b/IDE/MDK5-ARM/Projects/SimpleServer/time-dummy.c new file mode 100644 index 0000000000..2525eba38b --- /dev/null +++ b/IDE/MDK5-ARM/Projects/SimpleServer/time-dummy.c @@ -0,0 +1,34 @@ +/* time-dummy.c.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include "time.h" + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + return(&date) ; +} + +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c b/IDE/MDK5-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c deleted file mode 100644 index e2912d19f0..0000000000 --- a/IDE/MDK5-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c +++ /dev/null @@ -1,299 +0,0 @@ -/* main.c - * - * Copyright (C) 2006-2014 wolfSSL Inc. - * - * This file is part of CyaSSL. - * - * CyaSSL is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * CyaSSL is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - */ - -#ifdef HAVE_CONFIG_H - #include -#endif - -#include "time.h" - -#define PERIPH_BASE ((uint32_t)0x40000000) -/*----------------------------------------------------------------------------- - * initialize RTC - *----------------------------------------------------------------------------*/ -#include "stm32f2xx.h" - -#define assert_param(a) - -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) -#define Bcd2ToByte(v) \ - ((((uint8_t)(v & (uint8_t)0xF0) >> (uint8_t)0x4) * 10) + (v & (uint8_t)0x0F)) -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_TR_MNT ((uint32_t)0x00007000) -#define RTC_TR_MNU ((uint32_t)0x00000F00) - -#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) -#define CR_OFFSET (PWR_OFFSET + 0x00) -#define DBP_BitNumber 0x08 -#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) - -static void init_RTC() -{ - __IO uint32_t initcounter = 0x00 ; - uint32_t initstatus = 0x00; /* Enable the PWR clock : RCC_APB1Periph_PWR */ - ((uint32_t *)RCC)[0x10] |= ((uint32_t)0x10000000) ; - - /* Allow access to RTC */ - *(__IO uint32_t *) CR_DBP_BB = ENABLE ; - /* RCC_LSEConfig(RCC_LSE_ON) */ - *(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x00); - /* Reset LSEBYP bit */ - *(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x00); - *(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x01); - /* Wait till LSE is ready */ - while((RCC->BDCR << 0x2) == 0x0) { } - /* Select the RTC clock source: RCC_RTCCLKSource_LSE */ - ((RCC_TypeDef *)RCC)->BDCR |= (uint32_t)0x00000100; - - /* Enable the RTC Clock */ - *(__IO uint32_t *) (PERIPH_BB_BASE + (((RCC_BASE - PERIPH_BASE)+ 0x70) * 32) + (0x0F* 4)) = (uint32_t)ENABLE; - - *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; - RTC->ISR = (uint32_t) RTC_INIT_MASK; - do { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); /* Clear RTC CR FMT Bit */ - /* Set RTC_CR register */ - RTC->CR |= ((uint32_t)0x00000000) ; /* RTC_HourFormat_24 */ - - /* Configure the RTC PRER */ - RTC->PRER = 0x7f ; - RTC->PRER |= (uint32_t)(0xff << 16); - - /* Exit Initialization mode */ - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Enable the write protection for RTC registers */ - RTC->WPR = 0xFF; -} - -/*----------------------------------------------------------------------------- - * initialize TIM - *----------------------------------------------------------------------------*/ -#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) - -static void init_TIM() -{ - uint16_t tmpcr1 = 0; - - ((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ; - - tmpcr1 = TIM2->CR1 ; - tmpcr1 &= (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) )); - /* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */ - tmpcr1 |= (uint16_t)0x0000 ; /* CR1 |= TIM_CounterMode_Up */ - TIM2->CR1= tmpcr1 ; - - TIM2->ARR = 0xffffffff ; /* ARR= TIM_Period */ - TIM2->PSC = 60 ; /* PSC = TIM_Prescaler */ - TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */ - - *(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ; - /* TIM_Cmd(TIM2, ENABLE) ; */ -} - -void init_time(void) { - init_RTC() ; - init_TIM() ; -} - -static void GetTime(uint8_t *h, uint8_t *m, uint8_t *s) -{ - uint32_t tmpreg = 0; - tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); - *h = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16)); - *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8)); - *s = (uint8_t)Bcd2ToByte((tmpreg & (RTC_TR_ST | RTC_TR_SU))); -} - -static uint32_t ByteToBcd2(uint8_t Value) -{ - uint8_t bcdhigh = 0; - while (Value >= 10) { - bcdhigh++; - Value -= 10; - } - return ((uint8_t)(bcdhigh << 4) | Value); -} - -static void SetTime(uint8_t h, uint8_t m, uint8_t s) -{ - __IO uint32_t synchrocounter = 0; - uint32_t synchrostatus = 0x00; - __IO uint32_t initcounter = 0; - uint32_t initstatus = 0x00; - uint32_t tmpreg ; - - tmpreg = ((ByteToBcd2(h) << 16) | (ByteToBcd2(m) << 8) | ByteToBcd2(s)) ; - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; - - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - /* Wait the registers to be synchronised */ - do { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - RTC->WPR = 0xFF; -} - -static void GetDate(uint8_t *y, uint8_t *m, uint8_t *d) -{ - uint32_t tmpreg = 0; - tmpreg = (uint32_t)(RTC->DR & RTC_TR_RESERVED_MASK); - *y = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_YT|RTC_DR_YU)) >>16)); - *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_MT|RTC_DR_MU)) >> 8)); - *d = (uint8_t)Bcd2ToByte((uint8_t)(tmpreg & (RTC_DR_DT |RTC_DR_DU))); -} - -static void SetDate(uint8_t y, uint8_t m, uint8_t d) -{ - __IO uint32_t synchrocounter = 0; - uint32_t synchrostatus = 0x00; - __IO uint32_t initcounter = 0; - uint32_t initstatus = 0x00; - uint32_t tmpreg = 0 ; - - tmpreg = ((ByteToBcd2(y) << 16) | (ByteToBcd2(m) << 8) | ByteToBcd2(d)) ; - /* Disable the write protection for RTC registers */ - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - RTC->ISR &= (uint32_t)~RTC_ISR_INIT; - - RTC->ISR = (uint32_t)RTC_INIT_MASK; - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - do { - initstatus = RTC->ISR & RTC_ISR_INITF; - initcounter++; - } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); - - RTC->DR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - RTC->ISR &= (uint32_t)RTC_RSF_MASK; - /* Wait the registers to be synchronised */ - do { - synchrostatus = RTC->ISR & RTC_ISR_RSF; - synchrocounter++; - } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); - - RTC->WPR = 0xFF; -} - - -#include -void CYASSL_MSG(const char *msg) ; - -struct tm *Cyassl_MDK_gmtime(const time_t *c) -{ - uint8_t h, m, s ; - uint8_t y, mo, d ; - static struct tm date ; - - GetTime(&h, &m, &s) ; - GetDate(&y, &mo, &d) ; - - date.tm_year = y + 100 ; - date.tm_mon = mo - 1 ; - date.tm_mday = d ; - date.tm_hour = h ; - date.tm_min = m ; - date.tm_sec = s ; - - #if defined(DEBUG_CYASSL) - { - char msg[100] ; - sprintf(msg, - "Debug::Cyassl_KEIL_gmtime(DATE=/%2d/%02d/%04d TIME=%02d:%02d:%02d)\n", - d, mo, y+2000, h, m, s) ; - CYASSL_MSG(msg) ; - } - #endif - - return(&date) ; -} - -double current_time() -{ - return ((double)TIM2->CNT/1000000.0) ; -} - -typedef struct func_args { - int argc; - char** argv; - int return_code; -} func_args; - -void time_main(void *args) -{ - char * datetime ; - uint8_t h, m, s ; - uint8_t y, mo, d ; - - if( args == NULL || ((func_args *)args)->argc == 1) { - GetTime(&h, &m, &s) ; - GetDate(&y, &mo, &d) ; - printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", - mo, d, y+2000, h, m, s) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 'd' ) { - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d/%d/%d", (int *)&mo, (int *)&d, (int *) &y) ; - SetDate(y-2000, mo, d) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 't' ) { - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d:%d:%d", - (int *)&h, (int *)&m, (int *)&s) ; - SetTime(h, m, s) ; - } else printf("Invalid argument\n") ; -} - - -/******************************************************************* - time() -********************************************************************/ -time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Src/cert_data.c b/IDE/MDK5-ARM/Src/cert_data.c new file mode 100644 index 0000000000..d29fbf3b1d --- /dev/null +++ b/IDE/MDK5-ARM/Src/cert_data.c @@ -0,0 +1,28 @@ +/* certs_test.c + * + * Copyright (C) 2006-2014 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +/* Define initial data for cert buffers */ +#include + diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c b/IDE/MDK5-ARM/Src/cyassl_MDK_ARM.c similarity index 100% rename from IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c rename to IDE/MDK5-ARM/Src/cyassl_MDK_ARM.c diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/ssl-dummy.c b/IDE/MDK5-ARM/Src/ssl-dummy.c similarity index 100% rename from IDE/MDK5-ARM/MDK-ARM/CyaSSL/ssl-dummy.c rename to IDE/MDK5-ARM/Src/ssl-dummy.c diff --git a/IDE/MDK5-ARM/wolfSSL.CyaSSL.pdsc b/IDE/MDK5-ARM/wolfSSL.CyaSSL.pdsc deleted file mode 100644 index b0a7a6b34d..0000000000 --- a/IDE/MDK5-ARM/wolfSSL.CyaSSL.pdsc +++ /dev/null @@ -1,281 +0,0 @@ - - - - CyaSSL - Light weight SSL/TLS and Crypt Library for Embedded Systems - wolfSSL - http://www.wolfSSL.com/files/ide - cyassl\IDE\MDK5-ARM\Docs\CyaSSL-License.txt - - wolfSSL: SSL/TLS and Crypt Library - CyaSSL: SSL/TLS Library - wolfCrypt: Crypt Library - - - - - Oct/7/2013, Initial release of CyaSSL pack - - - - - CyaSSL - wolfSSL - Security - Crypt - Cipher - SSL - TLS - - - - - - - - The condition is true if the package is used with a Cortex-Mx based device - - - - - - - CMSIS Core with Cortex-M processor - - - - - - CMSIS Core with RTOS for Cortex-M processor - - - - - - File System on Memory Card - - - - - Network UDP/TCP and CORE component - - - - - - - - - - - - - - - - - - - - - - - - wolfSSL: SSL/TLS and Crypt Library - cyassl\IDE\MDK5-ARM\Docs\CyaSSLManual-TableofContents.htm - - CyaSSL, Light weight SSL/TLS library - - - - - - - - - - - - - - - - - - - - wolfCrypt Core, Light weight Crypt/Cipher Library - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Dummy file for Crypt alone use - - - - - - - - Device depend Timer functions - - - - - - - - - - - - CyaSSL Demo, SSL/TLS Server/Client Examples, Simple test suites, Benchmark - - - - - - - Middleware - Security - SSL - TLS - - - - wolfCrypt Simple Test Suite - - - - - - - Middleware - Security - Crypt - Cipher - - - - wolfCrypt Benchmark Suite - - - - - - - Middleware - Security - Crypt - Cipher - - - - CyaSSL Simple Client Example - - - - - - - Middleware - Security - Crypt - Cipher - - - - CyaSSL Simple Server Example - - - - - - - Middleware - Security - Crypt - Cipher - - - - CyaSSL Echo Client Example - - - - - - - Middleware - Security - Crypt - Cipher - - - - CyaSSL Echo Server Example - - - - - - - Middleware - Security - Crypt - Cipher - - - - diff --git a/ctaocrypt/src/random.c b/ctaocrypt/src/random.c index 2ba0fc096d..22643e3ad4 100644 --- a/ctaocrypt/src/random.c +++ b/ctaocrypt/src/random.c @@ -698,7 +698,7 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz) #endif /* FREESCALE_K70_RNGA */ #elif defined(CYASSL_SAFERTOS) || defined(CYASSL_LEANPSK) \ - || defined(CYASSL_IAR_ARM) + || defined(CYASSL_IAR_ARM) || defined(CYASSL_MDK_ARM) #warning "write a real random seed!!!!, just for testing now" diff --git a/cyassl/ctaocrypt/port.h b/cyassl/ctaocrypt/port.h index 9a2c9776ab..9f8a46d801 100644 --- a/cyassl/ctaocrypt/port.h +++ b/cyassl/ctaocrypt/port.h @@ -168,6 +168,7 @@ CYASSL_LOCAL int UnLockMutex(CyaSSL_Mutex*); /* stdio, default case */ #define XFILE FILE* #if defined(CYASSL_MDK_ARM) + #include extern FILE * CyaSSL_fopen(const char *name, const char *mode) ; #define XFOPEN CyaSSL_fopen #else diff --git a/examples/client/client.c b/examples/client/client.c index a472016526..113bed9f6d 100644 --- a/examples/client/client.c +++ b/examples/client/client.c @@ -20,13 +20,21 @@ */ #ifdef HAVE_CONFIG_H - #include + #include #endif - + #if defined(CYASSL_MDK_ARM) - #include + #include #include - #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + #include "cyassl_MDK_ARM.h" #endif @@ -38,6 +46,7 @@ #endif #include + #include #include "examples/client/client.h" @@ -151,12 +160,6 @@ static void Usage(void) #endif } - -#ifdef CYASSL_MDK_SHELL - #define exit(code) return(code) -#endif - - THREAD_RETURN CYASSL_THREAD client_test(void* args) { SOCKET_T sockfd = 0; diff --git a/examples/echoclient/echoclient.c b/examples/echoclient/echoclient.c index 29e062e7ff..24a02febc1 100644 --- a/examples/echoclient/echoclient.c +++ b/examples/echoclient/echoclient.c @@ -28,10 +28,18 @@ #include #if defined(CYASSL_MDK_ARM) - #include - #include - #include - #include "cyassl_MDK_ARM.h" + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" #endif #include diff --git a/examples/echoserver/echoserver.c b/examples/echoserver/echoserver.c index 945fc12699..33f6df3df0 100644 --- a/examples/echoserver/echoserver.c +++ b/examples/echoserver/echoserver.c @@ -26,10 +26,18 @@ #include #if defined(CYASSL_MDK_ARM) - #include - #include - #include - #include "cyassl_MDK_ARM.h" + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" #endif #include diff --git a/examples/server/server.c b/examples/server/server.c index 85058caca1..a42581d900 100644 --- a/examples/server/server.c +++ b/examples/server/server.c @@ -31,12 +31,19 @@ #endif #if defined(CYASSL_MDK_ARM) - #include - #include - #include - #include "cyassl_MDK_ARM.h" -#endif + #include + #include + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif #include #include @@ -132,11 +139,6 @@ static void Usage(void) #endif } -#ifdef CYASSL_MDK_SHELL -#define exit(code) return(code) -#endif - - THREAD_RETURN CYASSL_THREAD server_test(void* args) { SOCKET_T sockfd = 0;