forked from wolfSSL/wolfssl
Synchronous Cavium OCTEON Support for Sniffer
1. Add configure option for sync IntelQA that uses the crypto callback API. 2. Make a synchonous copy of the quickassist files. 3. Tie in the crypto device to the sniffer. 4. When making a sniffer build, define static DH enabled. 5. The readme files in the Cavium were being added to the distro optionally, changed to always add the readme files. 6. Added an include of the cavium_octeon header in the wc_ports.c. 7. Updated the Cavium OCTEON callback for AES-GCM. 8. Add the global tag to the list of crypto callback function pointers. 9. Add an accessor to the OCTEON crypto callback module to return the device ID of the OCTEON device. 10. Add a new version of ssl_SetWatchKeyCallback which takes an additional parameter of a device ID. This ID is used to set up the wolfSSL_CTXs in the sniffer session trackers. 11. Update the benchmark to use sync OCTEON and QAT.
This commit is contained in:
48
configure.ac
48
configure.ac
@@ -3882,6 +3882,39 @@ AC_ARG_WITH([cavium-v],
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)
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# Cavium Octeon
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OCTEON_ROOT=""
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AC_ARG_WITH([octeon-sync],
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[AS_HELP_STRING([--with-octeon-sync=PATH],[PATH to Cavium Octeon SDK dir (sync)])],
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[
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AC_MSG_CHECKING([for octeon])
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if test "x$withval" = "xyes" ; then
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AC_MSG_ERROR([need a PATH for --with-octeon])
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fi
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if test "x$withval" != "xno" ; then
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OCTEON_ROOT=$withval
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fi
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AM_CFLAGS="$AM_CFLAGS -DHAVE_CAVIUM_OCTEON_SYNC"
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AM_CFLAGS="$AM_CFLAGS -DOCTEON_MODEL=$OCTEON_MODEL -DCVMX_BUILD_FOR_LINUX_HOST"
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AM_CFLAGS="$AM_CFLAGS -I$OCTEON_ROOT/executive"
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#-I$OCTEON_ROOT/target/include
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LDFLAGS="$LDFLAGS -lrt -Xlinker -T -Xlinker $OCTEON_ROOT/executive/cvmx-shared-linux.ld"
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LIBS="$LIBS $OCTEON_ROOT/executive/obj-octeon3/libcvmx.a $OCTEON_ROOT/executive/obj-octeon3/libfdt.a"
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enable_shared=no
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enable_static=yes
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ENABLED_OCTEON_SYNC=yes
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AC_MSG_RESULT([yes])
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],
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[ENABLED_OCTEON_SYNC=no]
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)
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# Intel QuickAssist
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QAT_DIR=""
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BUILD_INTEL_QAT_VERSION=2
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@@ -4580,9 +4613,10 @@ AS_IF([test "x$ENABLED_OCSP" = "xyes" && \
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test "x$ENABLED_ECC" = "xno"],
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[AC_MSG_ERROR([please enable rsa or ecc if enabling ocsp.])])
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# Sync Intel QA requires the crypto callback
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AS_IF([test "x$ENABLED_CRYPTOCB" = "xno" && test "x$ENABLED_INTEL_QA_SYNC" = "xyes"],
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[AC_MSG_ERROR([please enable the crypto callback support using --enable-cryptocb])])
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# Sync Intel QA and Sync Cavium Octeon require the crypto callback
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AS_IF([test "x$ENABLED_INTEL_QA_SYNC" = "xyes" || test "x$ENABLED_OCTEON_SYNC" = "xyes"],
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[AS_IF([test "x$ENABLED_CRYPTOCB" = "xno"],
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[AC_MSG_ERROR([please enable the crypto callback support using --enable-cryptocb])])])
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# checks for pkcs7 needed enables
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AS_IF([test "x$ENABLED_PKCS7" = "xyes" && \
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@@ -4900,6 +4934,7 @@ AM_CONDITIONAL([BUILD_LIBZ],[test "x$ENABLED_LIBZ" = "xyes"])
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AM_CONDITIONAL([BUILD_PKCS11],[test "x$ENABLED_PKCS11" = "xyes"])
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AM_CONDITIONAL([BUILD_CAVIUM],[test "x$ENABLED_CAVIUM" = "xyes"])
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AM_CONDITIONAL([BUILD_CAVIUM_V],[test "x$ENABLED_CAVIUM_V" = "xyes"])
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AM_CONDITIONAL([BUILD_OCTEON_SYNC],[test "x$ENABLED_OCTEON_SYNC" = "xyes"])
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AM_CONDITIONAL([BUILD_INTEL_QA],[test "x$ENABLED_INTEL_QA" = "xyes"])
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AM_CONDITIONAL([BUILD_INTEL_QA_SYNC],[test "x$ENABLED_INTEL_QA_SYNC" = "xyes"])
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AM_CONDITIONAL([BUILD_SP],[test "x$ENABLED_SP" = "xyes"])
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@@ -5191,16 +5226,17 @@ echo " * Single Precision: $ENABLED_SP"
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echo " * Async Crypto: $ENABLED_ASYNCCRYPT"
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echo " * PKCS#11: $ENABLED_PKCS11"
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echo " * PKCS#12: $ENABLED_PKCS12"
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echo " * Cavium: $ENABLED_CAVIUM"
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echo " * Cavium Nitox: $ENABLED_CAVIUM"
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echo " * Cavium Octeon (Sync): $ENABLED_OCTEON_SYNC"
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echo " * Intel Quick Assist: $ENABLED_INTEL_QA"
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echo " * ARM ASM: $ENABLED_ARMASM"
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echo " * AES Key Wrap: $ENABLED_AESKEYWRAP"
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echo " * Write duplicate: $ENABLED_WRITEDUP"
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echo " * Intel Quick Assist: $ENABLED_INTEL_QA"
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echo " * Xilinx Hardware Acc.: $ENABLED_XILINX"
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echo " * Inline Code: $ENABLED_INLINE"
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echo " * Linux AF_ALG: $ENABLED_AFALG"
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echo " * Linux devcrypto: $ENABLED_DEVCRYPTO"
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echo " * Crypto callback: $ENABLED_CRYPTOCB"
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echo " * Crypto callbacks: $ENABLED_CRYPTOCB"
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echo ""
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echo "---"
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