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Added support for AES GCM with STM32F2/STM32F4 using Standard Peripheral Library and CubeMX. Added AES ECB Decrypt for Standard Peripheral Library. Fixes for wolfCrypt test with STM32 crypto hardware for unsupported tests (AES CTR plus 9 and AES GCM with IV != 12). Improve AES CBC for STM32 to handle block aligned only. Added IDE example for SystemWorkbench for STM32 (Open STM32 tools) IDE.

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This commit is contained in:
David Garske
2017-05-19 11:15:46 -07:00
parent bdaa827114
commit a616513860
15 changed files with 4307 additions and 125 deletions
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148
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105
IDE/OPENSTM32/Inc/lwipopts.h Normal file
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/* Define to prevent recursive inclusion --------------------------------------*/
#ifndef __LWIPOPTS__H__
#define __LWIPOPTS__H__
#include "stm32f4xx_hal.h"
/*-----------------------------------------------------------------------------*/
/* Current version of LwIP supported by CubeMx: 1.5.0_RC0_20160211 -*/
/*-----------------------------------------------------------------------------*/
/* Within 'USER CODE' section, code will be kept by default at each generation */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
#ifdef __cplusplus
extern "C" {
#endif
/* STM32CubeMX Specific Parameters (not defined in opt.h) ---------------------*/
/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
/*----- WITH_RTOS enabled (Since FREERTOS is set) -----*/
#define WITH_RTOS 1
/*----- CHECKSUM_BY_HARDWARE disabled -----*/
#define CHECKSUM_BY_HARDWARE 0
/*-----------------------------------------------------------------------------*/
/* LwIP Stack Parameters (modified compared to initialization value in opt.h) -*/
/* Parameters set in STM32CubeMX LwIP Configuration GUI -*/
/*----- Value in opt.h for LWIP_DHCP: 0 -----*/
#define LWIP_DHCP 1
/*----- Value in opt.h for MEM_ALIGNMENT: 1 -----*/
#define MEM_ALIGNMENT 4
/*----- Value in opt.h for MEMP_NUM_SYS_TIMEOUT: (LWIP_TCP + IP_REASSEMBLY + LWIP_ARP + (2*LWIP_DHCP) + LWIP_AUTOIP + LWIP_IGMP + LWIP_DNS + (PPP_SUPPORT*6*MEMP_NUM_PPP_PCB) + (LWIP_IPV6 ? (1 + LWIP_IPV6_REASS + LWIP_IPV6_MLD) : 0)) -*/
//#define MEMP_NUM_SYS_TIMEOUT 5
/*----- Value in opt.h for LWIP_ETHERNET: LWIP_ARP || PPPOE_SUPPORT -*/
#define LWIP_ETHERNET 1
/*----- Value in opt.h for LWIP_DNS_SECURE: (LWIP_DNS_SECURE_RAND_XID | LWIP_DNS_SECURE_NO_MULTIPLE_OUTSTANDING | LWIP_DNS_SECURE_RAND_SRC_PORT) -*/
#define LWIP_DNS_SECURE 7
/*----- Value in opt.h for TCP_SND_QUEUELEN: (4*TCP_SND_BUF + (TCP_MSS - 1))/TCP_MSS -----*/
#define TCP_SND_QUEUELEN 9
/*----- Value in opt.h for TCP_SNDLOWAT: LWIP_MIN(LWIP_MAX(((TCP_SND_BUF)/2), (2 * TCP_MSS) + 1), (TCP_SND_BUF) - 1) -*/
#define TCP_SNDLOWAT 1071
/*----- Value in opt.h for TCP_SNDQUEUELOWAT: LWIP_MAX(TCP_SND_QUEUELEN)/2, 5) -*/
#define TCP_SNDQUEUELOWAT 5
/*----- Value in opt.h for TCP_WND_UPDATE_THRESHOLD: LWIP_MIN(TCP_WND/4, TCP_MSS*4) -----*/
#define TCP_WND_UPDATE_THRESHOLD 536
/*----- Value in opt.h for TCPIP_THREAD_STACKSIZE: 0 -----*/
#define TCPIP_THREAD_STACKSIZE 1024
/*----- Value in opt.h for TCPIP_THREAD_PRIO: 1 -----*/
#define TCPIP_THREAD_PRIO 3
/*----- Value in opt.h for SLIPIF_THREAD_STACKSIZE: 0 -----*/
#define SLIPIF_THREAD_STACKSIZE 1024
/*----- Value in opt.h for SLIPIF_THREAD_PRIO: 1 -----*/
#define SLIPIF_THREAD_PRIO 3
/*----- Value in opt.h for DEFAULT_THREAD_STACKSIZE: 0 -----*/
#define DEFAULT_THREAD_STACKSIZE 1024
/*----- Value in opt.h for DEFAULT_THREAD_PRIO: 1 -----*/
#define DEFAULT_THREAD_PRIO 3
/*----- Value in opt.h for LWIP_STATS: 1 -----*/
#define LWIP_STATS 0
/*----- Value in opt.h for CHECKSUM_GEN_IP: 1 -----*/
#define CHECKSUM_GEN_IP 0
/*----- Value in opt.h for CHECKSUM_GEN_UDP: 1 -----*/
#define CHECKSUM_GEN_UDP 0
/*----- Value in opt.h for CHECKSUM_GEN_TCP: 1 -----*/
#define CHECKSUM_GEN_TCP 0
/*----- Value in opt.h for CHECKSUM_GEN_ICMP: 1 -----*/
#define CHECKSUM_GEN_ICMP 0
/*----- Value in opt.h for CHECKSUM_GEN_ICMP6: 1 -----*/
#define CHECKSUM_GEN_ICMP6 0
/*----- Value in opt.h for CHECKSUM_CHECK_IP: 1 -----*/
#define CHECKSUM_CHECK_IP 0
/*----- Value in opt.h for CHECKSUM_CHECK_UDP: 1 -----*/
#define CHECKSUM_CHECK_UDP 0
/*----- Value in opt.h for CHECKSUM_CHECK_TCP: 1 -----*/
#define CHECKSUM_CHECK_TCP 0
/*----- Value in opt.h for CHECKSUM_CHECK_ICMP: 1 -----*/
#define CHECKSUM_CHECK_ICMP 0
/*----- Value in opt.h for CHECKSUM_CHECK_ICMP6: 1 -----*/
#define CHECKSUM_CHECK_ICMP6 0
/*-----------------------------------------------------------------------------*/
/* Parameter(s) not set in STM32CubeMX LwIP Configuration GUI -*/
/* LwIP Parameter(s) not in opt.h -----------------------------*/
#define LWIP_PROVIDE_ERRNO 1
#define LWIP_TIMEVAL_PRIVATE 0
#define LWIP_DEBUG 1
#define LWIP_DNS 1
#define LWIP_SOCKET 1
#define LWIP_RAW 1
#define LWIP_NETCONN 1
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
#ifdef __cplusplus
}
#endif
#endif /*__LWIPOPTS__H_H */

401
IDE/OPENSTM32/Inc/user_settings.h Normal file
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/* Example wolfSSL user settings for STM32F4 with CubeMX */
#ifndef WOLFSSL_USER_SETTINGS_H
#define WOLFSSL_USER_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------------------------------------------------------- */
/* Platform */
/* ------------------------------------------------------------------------- */
#undef WOLFSSL_GENERAL_ALIGNMENT
#define WOLFSSL_GENERAL_ALIGNMENT 4
#undef SINGLE_THREADED
#define SINGLE_THREADED
#undef WOLFSSL_SMALL_STACK
#define WOLFSSL_SMALL_STACK
#undef WOLFSSL_STM32F4
#define WOLFSSL_STM32F4
#undef WOLFSSL_STM32_CUBEMX
#define WOLFSSL_STM32_CUBEMX
#undef FREERTOS
//#define FREERTOS
#undef WOLFSSL_LWIP
//#define WOLFSSL_LWIP
#define HAVE_LWIP_NATIVE
/* ------------------------------------------------------------------------- */
/* Math Configuration */
/* ------------------------------------------------------------------------- */
#undef USE_FAST_MATH
#define USE_FAST_MATH
#ifdef USE_FAST_MATH
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#undef TFM_NO_ASM
//#define TFM_NO_ASM
/* Optimizations (TFM_ARM, TFM_ASM or none) */
//#define TFM_ASM
#endif
/* ------------------------------------------------------------------------- */
/* Crypto */
/* ------------------------------------------------------------------------- */
/* ECC */
#if 1
#undef HAVE_ECC
#define HAVE_ECC
/* Manually define enabled curves */
#undef ECC_USER_CURVES
#define ECC_USER_CURVES
//#define HAVE_ECC192
//#define HAVE_ECC224
#undef NO_ECC256
//#define HAVE_ECC384
//#define HAVE_ECC521
/* Fixed point cache (speeds repeated operations against same private key) */
#undef FP_ECC
//#define FP_ECC
#ifdef FP_ECC
/* Bits / Entries */
#undef FP_ENTRIES
#define FP_ENTRIES 2
#undef FP_LUT
#define FP_LUT 4
#endif
/* Optional ECC calculation method */
/* Note: doubles heap usage, but slightly faster */
#undef ECC_SHAMIR
#define ECC_SHAMIR
/* Reduces heap usage, but slower */
#undef ECC_TIMING_RESISTANT
#define ECC_TIMING_RESISTANT
#ifdef USE_FAST_MATH
/* use reduced size math buffers for ecc points */
#undef ALT_ECC_SIZE
#define ALT_ECC_SIZE
/* optionally override the default max ecc bits */
//#undef FP_MAX_BITS_ECC
//#define FP_MAX_BITS_ECC 512
/* Enable TFM optimizations for ECC */
//#define TFM_ECC192
//#define TFM_ECC224
//#define TFM_ECC256
//#define TFM_ECC384
//#define TFM_ECC521
#endif
#endif
/* RSA */
#undef NO_RSA
#if 1
#ifdef USE_FAST_MATH
/* Maximum math bits (Max RSA key bits * 2) */
#undef FP_MAX_BITS
#define FP_MAX_BITS 4096
#endif
/* half as much memory but twice as slow */
#undef RSA_LOW_MEM
//#define RSA_LOW_MEM
/* Enables blinding mode, to prevent timing attacks */
#undef WC_RSA_BLINDING
#define WC_RSA_BLINDING
#else
#define NO_RSA
#endif
/* AES */
#undef NO_AES
#if 1
#undef HAVE_AESGCM
#define HAVE_AESGCM
#ifdef HAVE_AESGCM
/* GCM with hardware acceleration requires AES counter/direct for unaligned sizes */
#undef WOLFSSL_AES_COUNTER
#define WOLFSSL_AES_COUNTER
#undef WOLFSSL_AES_DIRECT
#define WOLFSSL_AES_DIRECT
#endif
/* GCM Method: GCM_SMALL, GCM_WORD32 or GCM_TABLE */
#undef GCM_SMALL
#define GCM_SMALL
#else
#define NO_AES
#endif
/* ChaCha20 / Poly1305 */
#undef HAVE_CHACHA
#undef HAVE_POLY1305
#if 0
#define HAVE_CHACHA
#define HAVE_POLY1305
/* Needed for Poly1305 */
#undef HAVE_ONE_TIME_AUTH
#define HAVE_ONE_TIME_AUTH
#endif
/* Ed25519 / Curve25519 */
#undef HAVE_CURVE25519
#undef HAVE_ED25519
#if 0
#define HAVE_CURVE25519
#define HAVE_ED25519
/* Optionally use small math (less flash usage, but much slower) */
#if 0
#define CURVED25519_SMALL
#endif
#endif
/* ------------------------------------------------------------------------- */
/* Hashing */
/* ------------------------------------------------------------------------- */
/* Sha */
#undef NO_SHA
#if 1
/* 1k smaller, but 25% slower */
//#define USE_SLOW_SHA
#else
#define NO_SHA
#endif
/* Sha256 */
#undef NO_SHA256
#if 1
#else
#define NO_SHA256
#endif
/* Sha512 */
#undef WOLFSSL_SHA512
#if 1
#define WOLFSSL_SHA512
/* Sha384 */
#undef WOLFSSL_SHA384
#if 1
#define WOLFSSL_SHA384
#endif
/* over twice as small, but 50% slower */
//#define USE_SLOW_SHA2
#endif
/* MD5 */
#undef NO_MD5
#if 1
/* enabled */
#else
#define NO_MD5
#endif
/* ------------------------------------------------------------------------- */
/* HW Crypto Acceleration */
/* ------------------------------------------------------------------------- */
// See settings.h STM32F4 section
/* ------------------------------------------------------------------------- */
/* Benchmark / Test */
/* ------------------------------------------------------------------------- */
/* Use reduced benchmark / test sizes */
#undef BENCH_EMBEDDED
#define BENCH_EMBEDDED
#undef USE_CERT_BUFFERS_2048
#define USE_CERT_BUFFERS_2048
#undef USE_CERT_BUFFERS_256
#define USE_CERT_BUFFERS_256
/* ------------------------------------------------------------------------- */
/* Debugging */
/* ------------------------------------------------------------------------- */
#undef WOLFSSL_DEBUG
//#define WOLFSSL_DEBUG
#ifdef WOLFSSL_DEBUG
/* Use this to measure / print heap usage */
#if 0
#undef USE_WOLFSSL_MEMORY
#define USE_WOLFSSL_MEMORY
#undef WOLFSSL_TRACK_MEMORY
#define WOLFSSL_TRACK_MEMORY
#endif
#else
#undef NO_WOLFSSL_MEMORY
#define NO_WOLFSSL_MEMORY
#undef NO_ERROR_STRINGS
//#define NO_ERROR_STRINGS
#endif
/* ------------------------------------------------------------------------- */
/* Port */
/* ------------------------------------------------------------------------- */
/* Override Current Time */
/* Allows custom "custom_time()" function to be used for benchmark */
#define WOLFSSL_USER_CURRTIME
/* ------------------------------------------------------------------------- */
/* RNG */
/* ------------------------------------------------------------------------- */
/* Size of returned HW RNG value */
#define CUSTOM_RAND_TYPE unsigned int
#define NO_OLD_RNGNAME
/* Choose RNG method */
#if 0
#if 1
/* Use built-in P-RNG (SHA256 based) with HW RNG */
/* P-RNG + HW RNG (P-RNG is ~8K) */
#undef HAVE_HASHDRBG
#define HAVE_HASHDRBG
extern unsigned int custom_rand_generate(void);
#undef CUSTOM_RAND_GENERATE
#define CUSTOM_RAND_GENERATE custom_rand_generate
#else
/* Bypass P-RNG and use only HW RNG */
extern int custom_rand_generate_block(unsigned char* output, unsigned int sz);
#undef CUSTOM_RAND_GENERATE_BLOCK
#define CUSTOM_RAND_GENERATE_BLOCK custom_rand_generate_block
#endif
#endif
/* ------------------------------------------------------------------------- */
/* Enable Features */
/* ------------------------------------------------------------------------- */
#undef KEEP_PEER_CERT
//#define KEEP_PEER_CERT
#undef HAVE_COMP_KEY
//#define HAVE_COMP_KEY
#undef HAVE_TLS_EXTENSIONS
#define HAVE_TLS_EXTENSIONS
#undef HAVE_SUPPORTED_CURVES
#define HAVE_SUPPORTED_CURVES
#undef WOLFSSL_BASE64_ENCODE
//#define WOLFSSL_BASE64_ENCODE
/* TLS Session Cache */
#if 0
#define SMALL_SESSION_CACHE
#else
#define NO_SESSION_CACHE
#endif
/* ------------------------------------------------------------------------- */
/* Disable Features */
/* ------------------------------------------------------------------------- */
#undef NO_WOLFSSL_SERVER
//#define NO_WOLFSSL_SERVER
#undef NO_WOLFSSL_CLIENT
//#define NO_WOLFSSL_CLIENT
#undef NO_CRYPT_TEST
//#define NO_CRYPT_TEST
#undef NO_CRYPT_BENCHMARK
//#define NO_CRYPT_BENCHMARK
/* In-lining of misc.c functions */
/* If defined, must include wolfcrypt/src/misc.c in build */
/* Slower, but about 1k smaller */
#undef NO_INLINE
//#define NO_INLINE
#undef NO_FILESYSTEM
#define NO_FILESYSTEM
#undef NO_WRITEV
#define NO_WRITEV
#undef NO_MAIN_DRIVER
#define NO_MAIN_DRIVER
#undef NO_DEV_RANDOM
#define NO_DEV_RANDOM
#undef NO_DSA
#define NO_DSA
#undef NO_DH
#define NO_DH
#undef NO_DES3
#define NO_DES3
#undef NO_RC4
#define NO_RC4
#undef NO_OLD_TLS
#define NO_OLD_TLS
#undef NO_HC128
#define NO_HC128
#undef NO_RABBIT
#define NO_RABBIT
#undef NO_PSK
#define NO_PSK
#undef NO_MD4
#define NO_MD4
#undef NO_PWDBASED
#define NO_PWDBASED
#undef NO_CODING
#define NO_CODING
#ifdef __cplusplus
}
#endif
#endif /* WOLFSSL_USER_SETTINGS_H */

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/*
* wolfssl_example.h
*
* Created on: Oct 3, 2016
* Author: davidgarske
*/
#ifndef WOLFSSL_EXAMPLE_H_
#define WOLFSSL_EXAMPLE_H_
void wolfCryptDemo(void const * argument);
#endif /* WOLFSSL_EXAMPLE_H_ */

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# wolfSSL STM32F2/F4 Example for Open STM32 Tools System Workbench
## Requirements
* STM32CubeMX: STM32 CubeMX HAL code generation tool - [http://www.st.com/en/development-tools/stm32cubemx.html](http://www.st.com/en/development-tools/stm32cubemx.html)
* SystemWorkbench for STM32 - [http://www.st.com/en/development-tools/sw4stm32.html](http://www.st.com/en/development-tools/sw4stm32.html)
## Setup
1. Using the STM32CubeMX tool, load the `<wolfssl-root>/IDE/OPENSTM32/wolfSTM32.ino` file.
2. Adjust the HAL options based on your specific micro-controller.
3. Generate source code.
4. Run `SystemWorkbench` and choose a new workspace location for this project.
5. Import `wolfSTM32' project from `<wolfssl-root>/IDE/OPENSTM32/`.
6. Adjust the micro-controller define in `Project Settings -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C`. Example uses `STM32F437xx`, but should be changed to reflect your micro-controller type.
7. Build and Run
Note: You may need to manually copy over the CubeMX HAL files for `stm32f4xx_hal_cryp.c`, `stm32f4xx_hal_cryp_ex.c`, `stm32f4xx_hal_cryp.h`, `stm32f4xx_hal_cryp_ex.h`. Also uncomment the `#define HAL_CRYP_MODULE_ENABLED` line in `stm32f4xx_hal_conf.h`.
## Configuration
The settings for the wolfSTM32 project are located in `<wolfssl-root>/IDE/OPENSTM32/Inc/user_settings.h`.
## Support
For questions please email [support@wolfssl.com](mailto:support@wolfssl.com)

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/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
#include "cmsis_os.h"
#include "lwip.h"
#include "wolfssl_example.h"
/* USER CODE BEGIN Includes */
/* USER CODE END Includes */
/* Private variables ---------------------------------------------------------*/
CRC_HandleTypeDef hcrc;
RNG_HandleTypeDef hrng;
RTC_HandleTypeDef hrtc;
UART_HandleTypeDef huart4;
osThreadId defaultTaskHandle;
/* USER CODE BEGIN PV */
/* Private variables ---------------------------------------------------------*/
/* USER CODE END PV */
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
void Error_Handler(void);
static void MX_GPIO_Init(void);
static void MX_CRC_Init(void);
static void MX_RNG_Init(void);
static void MX_UART4_Init(void);
static void MX_RTC_Init(void);
/* USER CODE BEGIN PFP */
/* Private function prototypes -----------------------------------------------*/
/* USER CODE END PFP */
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
int main(void)
{
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */
/* MCU Configuration----------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_CRC_Init();
MX_RNG_Init();
MX_UART4_Init();
MX_RTC_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
/* USER CODE BEGIN RTOS_MUTEX */
/* add mutexes, ... */
/* USER CODE END RTOS_MUTEX */
/* USER CODE BEGIN RTOS_SEMAPHORES */
/* add semaphores, ... */
/* USER CODE END RTOS_SEMAPHORES */
/* USER CODE BEGIN RTOS_TIMERS */
/* start timers, add new ones, ... */
/* USER CODE END RTOS_TIMERS */
/* Create the thread(s) */
/* definition and creation of defaultTask */
osThreadDef(defaultTask, wolfCryptDemo, osPriorityNormal, 0, 24000);
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
/* USER CODE BEGIN RTOS_THREADS */
/* add threads, ... */
/* USER CODE END RTOS_THREADS */
/* USER CODE BEGIN RTOS_QUEUES */
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Start scheduler */
osKernelStart();
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
/* USER CODE BEGIN 3 */
}
/* USER CODE END 3 */
}
/** System Clock Configuration
*/
#define SysTick_IRQn -1
void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 15;
RCC_OscInitStruct.PLL.PLLN = 144;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 5;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
}
/* CRC init function */
static void MX_CRC_Init(void)
{
hcrc.Instance = CRC;
if (HAL_CRC_Init(&hcrc) != HAL_OK)
{
Error_Handler();
}
}
/* RNG init function */
static void MX_RNG_Init(void)
{
hrng.Instance = RNG;
if (HAL_RNG_Init(&hrng) != HAL_OK)
{
Error_Handler();
}
}
/* RTC init function */
#define RTC_ASYNCH_PREDIV 0x7F /* LSE as RTC clock */
#define RTC_SYNCH_PREDIV 0x00FF /* LSE as RTC clock */
static void MX_RTC_Init(void)
{
RTC_TimeTypeDef sTime;
RTC_DateTypeDef sDate;
/**Initialize RTC and set the Time and Date
*/
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
hrtc.Init.SynchPrediv = RTC_SYNCH_PREDIV;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
sTime.Hours = 0x0;
sTime.Minutes = 0x0;
sTime.Seconds = 0x0;
sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
sTime.StoreOperation = RTC_STOREOPERATION_RESET;
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
sDate.WeekDay = RTC_WEEKDAY_MONDAY;
sDate.Month = RTC_MONTH_JANUARY;
sDate.Date = 0x1;
sDate.Year = 0x0;
if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
/**Enable the TimeStamp
*/
if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_DEFAULT) != HAL_OK)
{
Error_Handler();
}
/**Enable the reference Clock input
*/
if (HAL_RTCEx_SetRefClock(&hrtc) != HAL_OK)
{
Error_Handler();
}
}
/* UART4 init function */
static void MX_UART4_Init(void)
{
huart4.Instance = UART4;
huart4.Init.BaudRate = 115200;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart4) != HAL_OK)
{
Error_Handler();
}
// Turn off buffers, so I/O occurs immediately
setvbuf(stdin, NULL, _IONBF, 0);
setvbuf(stdout, NULL, _IONBF, 0);
setvbuf(stderr, NULL, _IONBF, 0);
}
int _write (int fd, char *ptr, int len)
{
(void)fd;
/* Write "len" of char from "ptr" to file id "fd"
* Return number of char written.
* Need implementing with UART here. */
HAL_UART_Transmit(&huart4, (uint8_t *)ptr, len, 0xFFFF);
return len;
}
int _read (int fd, char *ptr, int len)
{
/* Read "len" of char to "ptr" from file id "fd"
* Return number of char read.
* Need implementing with UART here. */
(void)fd;
return HAL_UART_Receive(&huart4, (uint8_t*)ptr, len, 0xFFFF);
}
void _ttywrch(int ch) {
/* Write one char "ch" to the default console
* Need implementing with UART here. */
_write(0, (char*)&ch, 1);
}
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
*/
static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
}
/* USER CODE BEGIN 4 */
/* USER CODE END 4 */
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM1 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM1) {
HAL_IncTick();
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t* file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif

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#include <string.h>
#include "stm32f4xx_hal.h"
#include "cmsis_os.h"
#include "lwip.h"
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include <wolfssl/wolfcrypt/settings.h>
#include <wolfssl/ssl.h>
#include <wolfcrypt/test/test.h>
#include <wolfcrypt/benchmark/benchmark.h>
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
/* UART definitions */
extern UART_HandleTypeDef huart4;
/*****************************************************************************
* Public types/enumerations/variables
****************************************************************************/
typedef struct func_args {
int argc;
char** argv;
int return_code;
} func_args;
const char menu1[] = "\r\n"
"\tt. WolfSSL Test\r\n"
"\tb. WolfSSL Benchmark\r\n";
/*****************************************************************************
* Private functions
****************************************************************************/
/*****************************************************************************
* Public functions
****************************************************************************/
void wolfCryptDemo(void const * argument)
{
uint8_t buffer[1] = {'t'};
func_args args;
/* init code for LWIP */
MX_LWIP_Init();
while (1) {
printf("\r\n\t\t\t\tMENU\r\n");
printf(menu1);
printf("Please select one of the above options: ");
HAL_UART_Receive(&huart4, buffer, sizeof(buffer), 1000);
switch (buffer[0]) {
case 't':
memset(&args, 0, sizeof(args));
printf("\nCrypt Test\n");
wolfcrypt_test(&args);
printf("Crypt Test: Return code %d\n", args.return_code);
break;
case 'b':
memset(&args, 0, sizeof(args));
printf("\nBenchmark Test\n");
benchmark_test(&args);
printf("Benchmark Test: Return code %d\n", args.return_code);
break;
// All other cases go here
default: printf("\r\nSelection out of range\r\n"); break;
}
}
}
extern RTC_HandleTypeDef hrtc;
double current_time()
{
RTC_TimeTypeDef time;
RTC_DateTypeDef date;
uint32_t subsec;
/* must get time and date here due to STM32 HW bug */
HAL_RTC_GetTime(&hrtc, &time, FORMAT_BIN);
HAL_RTC_GetDate(&hrtc, &date, FORMAT_BIN);
subsec = (255 - time.SubSeconds) * 1000 / 255;
(void)date;
/* return seconds.milliseconds */
return ((double)time.Hours * 24) +
((double)time.Minutes * 60) +
(double)time.Seconds +
((double)subsec/1000);
}

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# vim:ft=automake
# included from Top Level Makefile.am
# All paths should be given relative to the root
EXTRA_DIST+= IDE/OPENSTM32/README.md
EXTRA_DIST+= IDE/OPENSTM32/.cproject
EXTRA_DIST+= IDE/OPENSTM32/.project
EXTRA_DIST+= IDE/OPENSTM32/wolfSTM32.cfg
EXTRA_DIST+= IDE/OPENSTM32/wolfSTM32.ioc
EXTRA_DIST+= IDE/OPENSTM32/wolfSTM32.xml
EXTRA_DIST+= IDE/OPENSTM32/Src/main.c
EXTRA_DIST+= IDE/OPENSTM32/Src/wolfssl_example.c
EXTRA_DIST+= IDE/OPENSTM32/Inc/user_settings.h
EXTRA_DIST+= IDE/OPENSTM32/Inc/wolfssl_example.h
EXTRA_DIST+= IDE/OPENSTM32/Inc/lwipopts.h

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# This is an wolfSTM32 board with a single STM32F437IIHx chip.
# Generated by System Workbench for STM32
source [find interface/stlink-v2-1.cfg]
set WORKAREASIZE 0x30000
transport select "hla_jtag"
set CPUTAPID 0x4ba00477
source [find target/stm32f4x_stlink.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

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#MicroXplorer Configuration settings - do not modify
FREERTOS.IPParameters=Tasks01
FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default
File.Version=6
KeepUserPlacement=false
LWIP.Version=v1.5.0_RC0_20160211_Cube
Mcu.Family=STM32F4
Mcu.IP0=CRC
Mcu.IP1=ETH
Mcu.IP2=FREERTOS
Mcu.IP3=LWIP
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SYS
Mcu.IP9=UART4
Mcu.IPNb=10
Mcu.Name=STM32F437I(G-I)Hx
Mcu.Package=UFBGA176
Mcu.Pin0=PE2
Mcu.Pin1=PG14
Mcu.Pin10=PC10
Mcu.Pin11=PC13
Mcu.Pin12=PC14/OSC32_IN
Mcu.Pin13=PC15/OSC32_OUT
Mcu.Pin14=PH2
Mcu.Pin15=PH0/OSC_IN
Mcu.Pin16=PH3
Mcu.Pin17=PH1/OSC_OUT
Mcu.Pin18=PC1
Mcu.Pin19=PC2
Mcu.Pin2=PG13
Mcu.Pin20=PC3
Mcu.Pin21=PH6
Mcu.Pin22=PA1
Mcu.Pin23=PC4
Mcu.Pin24=PH7
Mcu.Pin25=PA2
Mcu.Pin26=PC5
Mcu.Pin27=PA7
Mcu.Pin28=PB15
Mcu.Pin29=VP_CRC_VS_CRC
Mcu.Pin3=PB4
Mcu.Pin30=VP_FREERTOS_VS_ENABLE
Mcu.Pin31=VP_LWIP_VS_Enabled
Mcu.Pin32=VP_RNG_VS_RNG
Mcu.Pin33=VP_SYS_VS_tim1
Mcu.Pin4=PB3
Mcu.Pin5=PA15
Mcu.Pin6=PA14
Mcu.Pin7=PA13
Mcu.Pin8=PG11
Mcu.Pin9=PC11
Mcu.PinsNb=34
Mcu.UserConstants=
Mcu.UserName=STM32F437IIHx
MxCube.Version=4.16.1
MxDb.Version=DB.4.0.161
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true
NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.TimeBase=TIM1_UP_TIM10_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
PA1.Mode=MII
PA1.Signal=ETH_RX_CLK
PA13.Mode=JTAG_5_pins
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=JTAG_5_pins
PA14.Signal=SYS_JTCK-SWCLK
PA15.Mode=JTAG_5_pins
PA15.Signal=SYS_JTDI
PA2.Mode=MII
PA2.Signal=ETH_MDIO
PA7.Mode=MII
PA7.Signal=ETH_RX_DV
PB15.Mode=Reference_Clock_Detection_Activate
PB15.Signal=RTC_REFIN
PB3.Mode=JTAG_5_pins
PB3.Signal=SYS_JTDO-SWO
PB4.Mode=JTAG_5_pins
PB4.Signal=SYS_JTRST
PC1.Mode=MII
PC1.Signal=ETH_MDC
PC10.Mode=Asynchronous
PC10.Signal=UART4_TX
PC11.Mode=Asynchronous
PC11.Signal=UART4_RX
PC13.Mode=Timestamp enabled - Input Enabled to AF1
PC13.Signal=RTC_AF1
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.Mode=MII
PC2.Signal=ETH_TXD2
PC3.Mode=MII
PC3.Signal=ETH_TX_CLK
PC4.Mode=MII
PC4.Signal=ETH_RXD0
PC5.Mode=MII
PC5.Signal=ETH_RXD1
PCC.Checker=false
PCC.Line=STM32F427/437
PCC.MCU=STM32F437I(G-I)Hx
PCC.MXVersion=4.16.1
PCC.PartNumber=STM32F437IIHx
PCC.Seq0=0
PCC.Series=STM32F4
PCC.Temperature=25
PCC.Vdd=null
PE2.Mode=MII
PE2.Signal=ETH_TXD3
PG11.Mode=MII
PG11.Signal=ETH_TX_EN
PG13.Mode=MII
PG13.Signal=ETH_TXD0
PG14.Mode=MII
PG14.Signal=ETH_TXD1
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
PH1/OSC_OUT.Signal=RCC_OSC_OUT
PH2.Mode=MII
PH2.Signal=ETH_CRS
PH3.Mode=MII
PH3.Signal=ETH_COL
PH6.Mode=MII
PH6.Signal=ETH_RXD2
PH7.Mode=MII
PH7.Signal=ETH_RXD3
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=2
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F437IIHx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.13.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x10000
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.PreviousToolchain=SW4STM32
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=wolfSTM32.ioc
ProjectManager.ProjectName=wolfSTM32
ProjectManager.StackSize=0x4000
ProjectManager.TargetToolchain=SW4STM32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false,2-MX_CRC_Init-CRC-false,3-MX_RNG_Init-RNG-false,4-MX_UART4_Init-UART4-false,5-MX_LWIP_Init-LWIP-false,6-MX_RTC_Init-RTC-false
RCC.48MHZClocksFreq_Value=48000000
RCC.AHBFreq_Value=120000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=30000000
RCC.APB1TimFreq_Value=60000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=60000000
RCC.APB2TimFreq_Value=120000000
RCC.CortexFreq_Value=120000000
RCC.EthernetFreq_Value=120000000
RCC.FCLKCortexFreq_Value=120000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=120000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=160000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=120000000
RCC.PLLCLKFreq_Value=120000000
RCC.PLLM=15
RCC.PLLN=144
RCC.PLLQ=5
RCC.PLLQCLKFreq_Value=48000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=12500000
RCC.SAI_AClocksFreq_Value=20416666.666666668
RCC.SAI_BClocksFreq_Value=20416666.666666668
RCC.SYSCLKFreq_VALUE=120000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.VCOI2SOutputFreq_Value=320000000
RCC.VCOInputFreq_Value=1666666.6666666667
RCC.VCOOutputFreq_Value=240000000
RCC.VCOSAIOutputFreq_Value=81666666.66666667
RCC.VCOSAIOutputFreq_ValueQ=20416666.666666668
RCC.VcooutputI2S=160000000
RCC.VcooutputI2SQ=160000000
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_FREERTOS_VS_ENABLE.Mode=Enabled
VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE
VP_LWIP_VS_Enabled.Mode=Enabled
VP_LWIP_VS_Enabled.Signal=LWIP_VS_Enabled
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
board=wolfSTM32

9
IDE/OPENSTM32/wolfSTM32.xml Normal file
View File

@ -0,0 +1,9 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<targetDefinitions xmlns="http://openstm32.org/stm32TargetDefinitions" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://openstm32.org/stm32TargetDefinitions stm32TargetDefinitions.xsd">
<board id="wolfstm32">
<name>wolfSTM32</name>
<mcuId>stm32f437iihx</mcuId>
<dbgIF>JTAG</dbgIF>
<dbgDEV>ST-LinkV2-1</dbgDEV>
</board>
</targetDefinitions>

1
IDE/include.am
View File

@ -9,5 +9,6 @@ include IDE/WORKBENCH/include.am
include IDE/ROWLEY-CROSSWORKS-ARM/include.am include IDE/ROWLEY-CROSSWORKS-ARM/include.am
include IDE/ARDUINO/include.am include IDE/ARDUINO/include.am
include IDE/INTIME-RTOS/include.am include IDE/INTIME-RTOS/include.am
include IDE/OPENSTM32/include.am
EXTRA_DIST+= IDE/IAR-EWARM IDE/MDK-ARM IDE/MDK5-ARM IDE/MYSQL IDE/LPCXPRESSO IDE/HEXIWEAR EXTRA_DIST+= IDE/IAR-EWARM IDE/MDK-ARM IDE/MDK5-ARM IDE/MYSQL IDE/LPCXPRESSO IDE/HEXIWEAR

543
wolfcrypt/src/aes.c
View File

@ -203,15 +203,17 @@
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO) #if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
/* STM32F2/F4 hardware AES support for CBC, CTR modes */ /* STM32F2/F4 hardware AES support for CBC, CTR modes */
/* CRYPT_AES_GCM starts the IV with 2 */
#define STM32_GCM_IV_START 2
#if defined(WOLFSSL_AES_DIRECT) || defined(HAVE_AESGCM) || defined(HAVE_AESCCM) #if defined(WOLFSSL_AES_DIRECT) || defined(HAVE_AESGCM) || defined(HAVE_AESCCM)
static int wc_AesEncrypt(Aes* aes, const byte* inBlock, byte* outBlock) static int wc_AesEncrypt(Aes* aes, const byte* inBlock, byte* outBlock)
{ {
int ret = 0; int ret = 0;
#ifdef WOLFSSL_STM32_CUBEMX #ifdef WOLFSSL_STM32_CUBEMX
CRYP_HandleTypeDef hcryp; CRYP_HandleTypeDef hcryp;
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
/* load key into correct registers */ XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
switch(aes->rounds) { switch(aes->rounds) {
case 10: /* 128-bit key */ case 10: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B; hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
@ -232,7 +234,7 @@
HAL_CRYP_Init(&hcryp); HAL_CRYP_Init(&hcryp);
if (HAL_CRYP_AESECB_Encrypt(&hcryp, (uint8_t*)inBlock, AES_BLOCK_SIZE, if (HAL_CRYP_AESECB_Encrypt(&hcryp, (uint8_t*)inBlock, AES_BLOCK_SIZE,
outBlock, STM32_HAL_TIMEOUT) != HAL_OK) { outBlock, STM32_HAL_TIMEOUT) != HAL_OK) {
ret = WC_TIMEOUT_E; ret = WC_TIMEOUT_E;
} }
@ -252,8 +254,7 @@
CRYP_DeInit(); CRYP_DeInit();
/* load key into correct registers */ /* load key into correct registers */
switch(aes->rounds) switch (aes->rounds) {
{
case 10: /* 128-bit key */ case 10: /* 128-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0]; AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0];
@ -307,7 +308,7 @@
CRYP_DataIn(*(uint32_t*)&inBlock[12]); CRYP_DataIn(*(uint32_t*)&inBlock[12]);
/* wait until the complete message has been processed */ /* wait until the complete message has been processed */
while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {} while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
*(uint32_t*)&outBlock[0] = CRYP_DataOut(); *(uint32_t*)&outBlock[0] = CRYP_DataOut();
*(uint32_t*)&outBlock[4] = CRYP_DataOut(); *(uint32_t*)&outBlock[4] = CRYP_DataOut();
@ -328,8 +329,8 @@
int ret = 0; int ret = 0;
#ifdef WOLFSSL_STM32_CUBEMX #ifdef WOLFSSL_STM32_CUBEMX
CRYP_HandleTypeDef hcryp; CRYP_HandleTypeDef hcryp;
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef)); XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
/* load key into correct registers */
switch(aes->rounds) { switch(aes->rounds) {
case 10: /* 128-bit key */ case 10: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B; hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
@ -350,13 +351,89 @@
HAL_CRYP_Init(&hcryp); HAL_CRYP_Init(&hcryp);
if (HAL_CRYP_AESECB_Decrypt(&hcryp, (uint8_t*)inBlock, AES_BLOCK_SIZE, if (HAL_CRYP_AESECB_Decrypt(&hcryp, (uint8_t*)inBlock, AES_BLOCK_SIZE,
outBlock, STM32_HAL_TIMEOUT) != HAL_OK) { outBlock, STM32_HAL_TIMEOUT) != HAL_OK) {
ret = WC_TIMEOUT_E; ret = WC_TIMEOUT_E;
} }
HAL_CRYP_DeInit(&hcryp); HAL_CRYP_DeInit(&hcryp);
#else #else
#error AES Decrypt not implemented for STM32 StdPeri lib word32 *enc_key;
CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
enc_key = aes->key;
/* crypto structure initialization */
CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
CRYP_StructInit(&AES_CRYP_InitStructure);
/* reset registers to their default values */
CRYP_DeInit();
/* load key into correct registers */
switch (aes->rounds) {
case 10: /* 128-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0];
AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[1];
AES_CRYP_KeyInitStructure.CRYP_Key3Left = enc_key[2];
AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[3];
break;
case 12: /* 192-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_192b;
AES_CRYP_KeyInitStructure.CRYP_Key1Left = enc_key[0];
AES_CRYP_KeyInitStructure.CRYP_Key1Right = enc_key[1];
AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[2];
AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[3];
AES_CRYP_KeyInitStructure.CRYP_Key3Left = enc_key[4];
AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[5];
break;
case 14: /* 256-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_256b;
AES_CRYP_KeyInitStructure.CRYP_Key0Left = enc_key[0];
AES_CRYP_KeyInitStructure.CRYP_Key0Right = enc_key[1];
AES_CRYP_KeyInitStructure.CRYP_Key1Left = enc_key[2];
AES_CRYP_KeyInitStructure.CRYP_Key1Right = enc_key[3];
AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[4];
AES_CRYP_KeyInitStructure.CRYP_Key2Right = enc_key[5];
AES_CRYP_KeyInitStructure.CRYP_Key3Left = enc_key[6];
AES_CRYP_KeyInitStructure.CRYP_Key3Right = enc_key[7];
break;
default:
break;
}
CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
/* set direction, mode, and datatype */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
CRYP_Init(&AES_CRYP_InitStructure);
/* enable crypto processor */
CRYP_Cmd(ENABLE);
/* flush IN/OUT FIFOs */
CRYP_FIFOFlush();
CRYP_DataIn(*(uint32_t*)&inBlock[0]);
CRYP_DataIn(*(uint32_t*)&inBlock[4]);
CRYP_DataIn(*(uint32_t*)&inBlock[8]);
CRYP_DataIn(*(uint32_t*)&inBlock[12]);
/* wait until the complete message has been processed */
while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
*(uint32_t*)&outBlock[0] = CRYP_DataOut();
*(uint32_t*)&outBlock[4] = CRYP_DataOut();
*(uint32_t*)&outBlock[8] = CRYP_DataOut();
*(uint32_t*)&outBlock[12] = CRYP_DataOut();
/* disable crypto processor */
CRYP_Cmd(DISABLE);
#endif /* WOLFSSL_STM32_CUBEMX */ #endif /* WOLFSSL_STM32_CUBEMX */
return ret; return ret;
} }
@ -2086,10 +2163,11 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz) int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{ {
int ret = 0; int ret = 0;
word32 blocks = (sz / AES_BLOCK_SIZE);
CRYP_HandleTypeDef hcryp; CRYP_HandleTypeDef hcryp;
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef)); XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
/* load key into correct registers */ switch (aes->rounds) {
switch(aes->rounds) {
case 10: /* 128-bit key */ case 10: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B; hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
break; break;
@ -2109,7 +2187,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
HAL_CRYP_Init(&hcryp); HAL_CRYP_Init(&hcryp);
while (sz > 0) { while (blocks--) {
if (HAL_CRYP_AESCBC_Encrypt(&hcryp, (uint8_t*)in, AES_BLOCK_SIZE, if (HAL_CRYP_AESCBC_Encrypt(&hcryp, (uint8_t*)in, AES_BLOCK_SIZE,
out, STM32_HAL_TIMEOUT) != HAL_OK) { out, STM32_HAL_TIMEOUT) != HAL_OK) {
ret = WC_TIMEOUT_E; ret = WC_TIMEOUT_E;
@ -2132,10 +2210,11 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz) int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{ {
int ret = 0; int ret = 0;
word32 blocks = (sz / AES_BLOCK_SIZE);
CRYP_HandleTypeDef hcryp; CRYP_HandleTypeDef hcryp;
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef)); XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
/* load key into correct registers */ switch (aes->rounds) {
switch(aes->rounds) {
case 10: /* 128-bit key */ case 10: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B; hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
break; break;
@ -2155,7 +2234,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
HAL_CRYP_Init(&hcryp); HAL_CRYP_Init(&hcryp);
while (sz > 0) { while (blocks--) {
if (HAL_CRYP_AESCBC_Decrypt(&hcryp, (uint8_t*)in, AES_BLOCK_SIZE, if (HAL_CRYP_AESCBC_Decrypt(&hcryp, (uint8_t*)in, AES_BLOCK_SIZE,
out, STM32_HAL_TIMEOUT) != HAL_OK) { out, STM32_HAL_TIMEOUT) != HAL_OK) {
ret = WC_TIMEOUT_E; ret = WC_TIMEOUT_E;
@ -2164,8 +2243,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
/* store iv for next call */ /* store iv for next call */
XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE); XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
sz -= AES_BLOCK_SIZE; in += AES_BLOCK_SIZE;
in += AES_BLOCK_SIZE;
out += AES_BLOCK_SIZE; out += AES_BLOCK_SIZE;
} }
@ -2178,6 +2256,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz) int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{ {
word32 *enc_key, *iv; word32 *enc_key, *iv;
word32 blocks = (sz / AES_BLOCK_SIZE);
CRYP_InitTypeDef AES_CRYP_InitStructure; CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
@ -2194,8 +2273,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
CRYP_DeInit(); CRYP_DeInit();
/* load key into correct registers */ /* load key into correct registers */
switch(aes->rounds) switch (aes->rounds) {
{
case 10: /* 128-bit key */ case 10: /* 128-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0]; AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0];
@ -2248,8 +2326,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
/* enable crypto processor */ /* enable crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
while (sz > 0) while (blocks--) {
{
/* flush IN/OUT FIFOs */ /* flush IN/OUT FIFOs */
CRYP_FIFOFlush(); CRYP_FIFOFlush();
@ -2259,7 +2336,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
CRYP_DataIn(*(uint32_t*)&in[12]); CRYP_DataIn(*(uint32_t*)&in[12]);
/* wait until the complete message has been processed */ /* wait until the complete message has been processed */
while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {} while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
*(uint32_t*)&out[0] = CRYP_DataOut(); *(uint32_t*)&out[0] = CRYP_DataOut();
*(uint32_t*)&out[4] = CRYP_DataOut(); *(uint32_t*)&out[4] = CRYP_DataOut();
@ -2284,6 +2361,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz) int wc_AesCbcDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{ {
word32 *dec_key, *iv; word32 *dec_key, *iv;
word32 blocks = (sz / AES_BLOCK_SIZE);
CRYP_InitTypeDef AES_CRYP_InitStructure; CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
@ -2297,14 +2375,13 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
CRYP_IVStructInit(&AES_CRYP_IVInitStructure); CRYP_IVStructInit(&AES_CRYP_IVInitStructure);
/* if input and output same will overwrite input iv */ /* if input and output same will overwrite input iv */
XMEMCPY(aes->tmp, in + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE); XMEMCPY(aes->tmp, in + len - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
/* reset registers to their default values */ /* reset registers to their default values */
CRYP_DeInit(); CRYP_DeInit();
/* load key into correct registers */ /* load key into correct registers */
switch(aes->rounds) switch (aes->rounds) {
{
case 10: /* 128-bit key */ case 10: /* 128-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = dec_key[0]; AES_CRYP_KeyInitStructure.CRYP_Key2Left = dec_key[0];
@ -2350,7 +2427,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
/* wait until key has been prepared */ /* wait until key has been prepared */
while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {} while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
/* set direction, mode, and datatype for decryption */ /* set direction, mode, and datatype for decryption */
AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt; AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
@ -2370,8 +2447,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
/* enable crypto processor */ /* enable crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
while (sz > 0) while (blocks--) {
{
/* flush IN/OUT FIFOs */ /* flush IN/OUT FIFOs */
CRYP_FIFOFlush(); CRYP_FIFOFlush();
@ -2381,7 +2457,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
CRYP_DataIn(*(uint32_t*)&in[12]); CRYP_DataIn(*(uint32_t*)&in[12]);
/* wait until the complete message has been processed */ /* wait until the complete message has been processed */
while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {} while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
*(uint32_t*)&out[0] = CRYP_DataOut(); *(uint32_t*)&out[0] = CRYP_DataOut();
*(uint32_t*)&out[4] = CRYP_DataOut(); *(uint32_t*)&out[4] = CRYP_DataOut();
@ -2391,8 +2467,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
/* store iv for next call */ /* store iv for next call */
XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE); XMEMCPY(aes->reg, aes->tmp, AES_BLOCK_SIZE);
sz -= AES_BLOCK_SIZE; in += AES_BLOCK_SIZE;
in += AES_BLOCK_SIZE;
out += AES_BLOCK_SIZE; out += AES_BLOCK_SIZE;
} }
@ -2910,16 +2985,15 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
#endif #endif
/* AES-CTR */ /* AES-CTR */
#ifdef WOLFSSL_AES_COUNTER #if defined(WOLFSSL_AES_COUNTER) || (defined(HAVE_AESGCM_DECRYPT) && defined(STM32F4_CRYPTO))
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO) #if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#ifdef WOLFSSL_STM32_CUBEMX #ifdef WOLFSSL_STM32_CUBEMX
void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz) void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{ {
CRYP_HandleTypeDef hcryp; CRYP_HandleTypeDef hcryp;
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef)); XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
/* load key into correct registers */ switch (aes->rounds) {
switch(aes->rounds) {
case 10: /* 128-bit key */ case 10: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B; hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
break; break;
@ -2934,13 +3008,15 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
} }
hcryp.Instance = CRYP; hcryp.Instance = CRYP;
hcryp.Init.DataType = CRYP_DATATYPE_8B; hcryp.Init.DataType = CRYP_DATATYPE_8B;
hcryp.Init.pKey = aes->key; hcryp.Init.pKey = (byte*)aes->key;
hcryp.Init.pInitVect = aes->reg; hcryp.Init.pInitVect = (byte*)aes->reg;
HAL_CRYP_Init(&hcryp); HAL_CRYP_Init(&hcryp);
HAL_CRYP_AESCTR_Encrypt(&hcryp, in, AES_BLOCK_SIZE, out, if (HAL_CRYP_AESCTR_Encrypt(&hcryp, (byte*)in, sz, out,
STM32_HAL_TIMEOUT); STM32_HAL_TIMEOUT) != HAL_OK) {
/* failed */
}
HAL_CRYP_DeInit(&hcryp); HAL_CRYP_DeInit(&hcryp);
} }
@ -2948,6 +3024,7 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz) void wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{ {
word32 *enc_key, *iv; word32 *enc_key, *iv;
int len = (int)sz;
CRYP_InitTypeDef AES_CRYP_InitStructure; CRYP_InitTypeDef AES_CRYP_InitStructure;
CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure; CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
CRYP_IVInitTypeDef AES_CRYP_IVInitStructure; CRYP_IVInitTypeDef AES_CRYP_IVInitStructure;
@ -2964,8 +3041,7 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
CRYP_DeInit(); CRYP_DeInit();
/* load key into correct registers */ /* load key into correct registers */
switch(aes->rounds) switch (aes->rounds) {
{
case 10: /* 128-bit key */ case 10: /* 128-bit key */
AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b; AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0]; AES_CRYP_KeyInitStructure.CRYP_Key2Left = enc_key[0];
@ -3018,8 +3094,7 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
/* enable crypto processor */ /* enable crypto processor */
CRYP_Cmd(ENABLE); CRYP_Cmd(ENABLE);
while (sz > 0) while (len > 0) {
{
/* flush IN/OUT FIFOs */ /* flush IN/OUT FIFOs */
CRYP_FIFOFlush(); CRYP_FIFOFlush();
@ -3029,7 +3104,7 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
CRYP_DataIn(*(uint32_t*)&in[12]); CRYP_DataIn(*(uint32_t*)&in[12]);
/* wait until the complete message has been processed */ /* wait until the complete message has been processed */
while(CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {} while (CRYP_GetFlagStatus(CRYP_FLAG_BUSY) != RESET) {}
*(uint32_t*)&out[0] = CRYP_DataOut(); *(uint32_t*)&out[0] = CRYP_DataOut();
*(uint32_t*)&out[4] = CRYP_DataOut(); *(uint32_t*)&out[4] = CRYP_DataOut();
@ -3037,9 +3112,9 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
*(uint32_t*)&out[12] = CRYP_DataOut(); *(uint32_t*)&out[12] = CRYP_DataOut();
/* store iv for next call */ /* store iv for next call */
XMEMCPY(aes->reg, out + sz - AES_BLOCK_SIZE, AES_BLOCK_SIZE); XMEMCPY(aes->reg, out + len - AES_BLOCK_SIZE, AES_BLOCK_SIZE);
sz -= AES_BLOCK_SIZE; len -= AES_BLOCK_SIZE;
in += AES_BLOCK_SIZE; in += AES_BLOCK_SIZE;
out += AES_BLOCK_SIZE; out += AES_BLOCK_SIZE;
} }
@ -4273,30 +4348,11 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
byte* authTag, word32 authTagSz, byte* authTag, word32 authTagSz,
const byte* authIn, word32 authInSz) const byte* authIn, word32 authInSz)
{ {
#if defined(FREESCALE_LTC_AES_GCM) int ret = 0;
byte *key; word32 keySize;
uint32_t keySize; #ifdef FREESCALE_LTC_AES_GCM
status_t status; status_t status;
#else
if (authTagSz < WOLFSSL_MIN_AUTH_TAG_SZ) {
WOLFSSL_MSG("GcmEncrypt authTagSz too small error");
return BAD_FUNC_ARG;
}
key = (byte*)aes->key;
status = wc_AesGetKeySize(aes, &keySize);
if (status != 0) {
return status;
}
status = LTC_AES_EncryptTagGcm(LTC_BASE, in, out, sz,
iv, ivSz, authIn, authInSz, key, keySize, authTag, authTagSz);
return (status == kStatus_Success) ? 0 : AES_GCM_AUTH_E;
#else /* FREESCALE_LTC_AES_GCM */
word32 blocks = sz / AES_BLOCK_SIZE; word32 blocks = sz / AES_BLOCK_SIZE;
word32 partial = sz % AES_BLOCK_SIZE; word32 partial = sz % AES_BLOCK_SIZE;
const byte* p = in; const byte* p = in;
@ -4305,16 +4361,138 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
byte initialCounter[AES_BLOCK_SIZE]; byte initialCounter[AES_BLOCK_SIZE];
byte *ctr; byte *ctr;
byte scratch[AES_BLOCK_SIZE]; byte scratch[AES_BLOCK_SIZE];
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#ifdef WOLFSSL_STM32_CUBEMX
CRYP_HandleTypeDef hcryp;
#else
byte keyCopy[AES_BLOCK_SIZE * 2];
#endif /* WOLFSSL_STM32_CUBEMX */
int status = 0;
byte* authInPadded = NULL;
byte tag[AES_BLOCK_SIZE];
int authPadSz;
#endif /* STM32F2_CRYPTO || STM32F4_CRYPTO */
#endif /* FREESCALE_LTC_AES_GCM */
/* Sanity check for XMEMCPY in GHASH function and local xorbuf call */ /* argument checks */
if (authTagSz > AES_BLOCK_SIZE) if (aes == NULL || authTagSz > AES_BLOCK_SIZE) {
return BAD_FUNC_ARG; return BAD_FUNC_ARG;
}
if (authTagSz < WOLFSSL_MIN_AUTH_TAG_SZ) { if (authTagSz < WOLFSSL_MIN_AUTH_TAG_SZ) {
WOLFSSL_MSG("GcmEncrypt authTagSz too small error"); WOLFSSL_MSG("GcmEncrypt authTagSz too small error");
return BAD_FUNC_ARG; return BAD_FUNC_ARG;
} }
ret = wc_AesGetKeySize(aes, &keySize);
if (ret != 0)
return ret;
#ifdef FREESCALE_LTC_AES_GCM
status = LTC_AES_EncryptTagGcm(LTC_BASE, in, out, sz, iv, ivSz,
authIn, authInSz, (byte*)aes->key, keySize, authTag, authTagSz);
ret = (status == kStatus_Success) ? 0 : AES_GCM_AUTH_E;
#else
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
/* additional argument checks - STM32 HW only supports 12 byte IV */
if (ivSz != NONCE_SZ) {
return BAD_FUNC_ARG;
}
XMEMSET(initialCounter, 0, AES_BLOCK_SIZE);
XMEMCPY(initialCounter, iv, ivSz);
initialCounter[AES_BLOCK_SIZE - 1] = STM32_GCM_IV_START;
/* STM32 HW AES-GCM requires / assumes inputs are a multiple of block size.
* We can avoid this by zero padding (authIn) AAD, but zero-padded plaintext
* will be encrypted and output incorrectly, causing a bad authTag.
* We will use HW accelerated AES-GCM if plain%AES_BLOCK_SZ==0.
* Otherwise, we will use accelerated AES_CTR for encrypt, and then
* perform GHASH in software.
* See NIST SP 800-38D */
/* Plain text is a multiple of block size, so use HW-Accelerated AES_GCM */
if (!partial) {
/* pad authIn if it is not a block multiple */
if ((authInSz % AES_BLOCK_SIZE) != 0) {
authPadSz = ((authInSz / AES_BLOCK_SIZE) + 1) * AES_BLOCK_SIZE;
/* Need to pad the AAD to a full block with zeros. */
authInPadded = XMALLOC(authPadSz, aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
if (authInPadded == NULL) {
return MEMORY_E;
}
XMEMSET(authInPadded, 0, authPadSz);
XMEMCPY(authInPadded, authIn, authInSz);
} else {
authPadSz = authInSz;
authInPadded = (byte*)authIn;
}
#ifdef WOLFSSL_STM32_CUBEMX
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
switch (keySize) {
case 16: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
break;
case 24: /* 192-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_192B;
break;
case 32: /* 256-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_256B;
break;
default:
break;
}
hcryp.Instance = CRYP;
hcryp.Init.DataType = CRYP_DATATYPE_8B;
hcryp.Init.pKey = (byte*)aes->key;
hcryp.Init.pInitVect = initialCounter;
hcryp.Init.Header = authInPadded;
hcryp.Init.HeaderSize = authInSz;
HAL_CRYP_Init(&hcryp);
status = HAL_CRYPEx_AESGCM_Encrypt(&hcryp, (byte*)in, sz,
out, STM32_HAL_TIMEOUT);
/* Compute the authTag */
if (status == HAL_OK)
status = HAL_CRYPEx_AESGCM_Finish(&hcryp, sz, tag, STM32_HAL_TIMEOUT);
if (status != HAL_OK)
ret = AES_GCM_AUTH_E;
HAL_CRYP_DeInit(&hcryp);
#else
ByteReverseWords((word32*)keyCopy, (word32*)aes->key, keySize);
status = CRYP_AES_GCM(MODE_ENCRYPT, (uint8_t*)initialCounter,
(uint8_t*)keyCopy, keySize * 8,
(uint8_t*)in, sz,
(uint8_t*)authInPadded,authInSz,
(uint8_t*)out, tag);
if (status != SUCCESS)
ret = AES_GCM_AUTH_E;
#endif /* WOLFSSL_STM32_CUBEMX */
/* authTag may be shorter than AES_BLOCK_SZ, store separately */
if (ret == 0)
XMEMCPY(authTag, tag, authTagSz);
/* We only allocate extra memory if authInPadded is not a multiple of AES_BLOCK_SZ */
if (authInPadded != NULL && authInSz != authPadSz) {
XFREE(authInPadded, aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
}
return ret;
}
#endif
/* Software AES-GCM */
#if defined(WOLFSSL_ASYNC_CRYPT) && defined(WC_ASYNC_ENABLE_AES) #if defined(WOLFSSL_ASYNC_CRYPT) && defined(WC_ASYNC_ENABLE_AES)
/* if async and byte count above threshold */ /* if async and byte count above threshold */
if (aes->asyncDev.marker == WOLFSSL_ASYNC_MARKER_AES && if (aes->asyncDev.marker == WOLFSSL_ASYNC_MARKER_AES &&
@ -4369,17 +4547,19 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
XMEMCPY(ctr, initialCounter, AES_BLOCK_SIZE); XMEMCPY(ctr, initialCounter, AES_BLOCK_SIZE);
#ifdef WOLFSSL_PIC32MZ_CRYPT #ifdef WOLFSSL_PIC32MZ_CRYPT
if(blocks) if (blocks) {
wc_AesCrypt(aes, out, in, blocks*AES_BLOCK_SIZE, wc_AesCrypt(aes, out, in, blocks * AES_BLOCK_SIZE,
PIC32_ENCRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_AES_GCM ); PIC32_ENCRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_AES_GCM);
}
/* process remainder using partial handling */
#endif #endif
while (blocks--) { while (blocks--) {
IncrementGcmCounter(ctr); IncrementGcmCounter(ctr);
#ifndef WOLFSSL_PIC32MZ_CRYPT #ifndef WOLFSSL_PIC32MZ_CRYPT
wc_AesEncrypt(aes, ctr, scratch); wc_AesEncrypt(aes, ctr, scratch);
xorbuf(scratch, p, AES_BLOCK_SIZE); xorbuf(scratch, p, AES_BLOCK_SIZE);
XMEMCPY(c, scratch, AES_BLOCK_SIZE); XMEMCPY(c, scratch, AES_BLOCK_SIZE);
#endif #endif
p += AES_BLOCK_SIZE; p += AES_BLOCK_SIZE;
c += AES_BLOCK_SIZE; c += AES_BLOCK_SIZE;
} }
@ -4396,8 +4576,9 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
wc_AesEncrypt(aes, initialCounter, scratch); wc_AesEncrypt(aes, initialCounter, scratch);
xorbuf(authTag, scratch, authTagSz); xorbuf(authTag, scratch, authTagSz);
return 0;
#endif /* FREESCALE_LTC_AES_GCM */ #endif /* FREESCALE_LTC_AES_GCM */
return ret;
} }
@ -4407,25 +4588,23 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
const byte* authTag, word32 authTagSz, const byte* authTag, word32 authTagSz,
const byte* authIn, word32 authInSz) const byte* authIn, word32 authInSz)
{ {
#if defined(FREESCALE_LTC_AES_GCM) int ret = 0;
byte *key; word32 keySize;
uint32_t keySize; #ifdef FREESCALE_LTC_AES_GCM
status_t status; status_t status;
#elif defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
key = (byte*)aes->key; #ifdef WOLFSSL_STM32_CUBEMX
CRYP_HandleTypeDef hcryp;
status = wc_AesGetKeySize(aes, &keySize); #else
if (status != 0) { byte keyCopy[AES_BLOCK_SIZE * 2];
return status; #endif /* WOLFSSL_STM32_CUBEMX */
} int status;
int inPadSz, authPadSz;
status = LTC_AES_DecryptTagGcm(LTC_BASE, in, out, sz, byte tag[AES_BLOCK_SIZE];
iv, ivSz, authIn, authInSz, key, keySize, authTag, authTagSz); byte *inPadded = NULL;
byte *authInPadded = NULL;
return (status == kStatus_Success) ? 0 : AES_GCM_AUTH_E; byte initialCounter[AES_BLOCK_SIZE];
#else /* software AES-GCM */
#else /* FREESCALE_LTC_AES_GCM */
word32 blocks = sz / AES_BLOCK_SIZE; word32 blocks = sz / AES_BLOCK_SIZE;
word32 partial = sz % AES_BLOCK_SIZE; word32 partial = sz % AES_BLOCK_SIZE;
const byte* c = in; const byte* c = in;
@ -4434,6 +4613,9 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
byte initialCounter[AES_BLOCK_SIZE]; byte initialCounter[AES_BLOCK_SIZE];
byte *ctr; byte *ctr;
byte scratch[AES_BLOCK_SIZE]; byte scratch[AES_BLOCK_SIZE];
byte Tprime[AES_BLOCK_SIZE];
byte EKY0[AES_BLOCK_SIZE];
#endif
/* argument checks */ /* argument checks */
if (aes == NULL || out == NULL || in == NULL || sz == 0 || iv == NULL || if (aes == NULL || out == NULL || in == NULL || sz == 0 || iv == NULL ||
@ -4441,6 +4623,129 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
return BAD_FUNC_ARG; return BAD_FUNC_ARG;
} }
ret = wc_AesGetKeySize(aes, &keySize);
if (ret != 0) {
return ret;
}
#ifdef FREESCALE_LTC_AES_GCM
status = LTC_AES_DecryptTagGcm(LTC_BASE, in, out, sz, iv, ivSz,
authIn, authInSz, (byte*)aes->key, keySize, authTag, authTagSz);
ret = (status == kStatus_Success) ? 0 : AES_GCM_AUTH_E;
#elif defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
/* additional argument checks - STM32 HW only supports 12 byte IV */
if (ivSz != NONCE_SZ) {
return BAD_FUNC_ARG;
}
XMEMSET(initialCounter, 0, AES_BLOCK_SIZE);
XMEMCPY(initialCounter, iv, ivSz);
initialCounter[AES_BLOCK_SIZE - 1] = STM32_GCM_IV_START;
/* Need to pad the AAD and input cipher text to a full block size since
* CRYP_AES_GCM will assume these are a multiple of AES_BLOCK_SIZE.
* It is okay to pad with zeros because GCM does this before GHASH already.
* See NIST SP 800-38D */
if ((sz % AES_BLOCK_SIZE) > 0) {
inPadSz = ((sz / AES_BLOCK_SIZE) + 1) * AES_BLOCK_SIZE;
inPadded = XMALLOC(inPadSz, aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
if (inPadded == NULL) {
return MEMORY_E;
}
XMEMSET(inPadded, 0, inPadSz);
XMEMCPY(inPadded, in, sz);
} else {
inPadSz = sz;
inPadded = (byte*)in;
}
if ((authInSz % AES_BLOCK_SIZE) > 0) {
authPadSz = ((authInSz / AES_BLOCK_SIZE) + 1) * AES_BLOCK_SIZE;
authInPadded = XMALLOC(authPadSz, aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
if (authInPadded == NULL) {
if (inPadded != NULL && inPadSz != sz)
XFREE(inPadded , aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
return MEMORY_E;
}
XMEMSET(authInPadded, 0, authPadSz);
XMEMCPY(authInPadded, authIn, authInSz);
} else {
authPadSz = authInSz;
authInPadded = (byte*)authIn;
}
#ifdef WOLFSSL_STM32_CUBEMX
XMEMSET(&hcryp, 0, sizeof(CRYP_HandleTypeDef));
switch(keySize) {
case 16: /* 128-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_128B;
break;
case 24: /* 192-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_192B;
break;
case 32: /* 256-bit key */
hcryp.Init.KeySize = CRYP_KEYSIZE_256B;
break;
default:
break;
}
hcryp.Instance = CRYP;
hcryp.Init.DataType = CRYP_DATATYPE_8B;
hcryp.Init.pKey = (byte*)aes->key;
hcryp.Init.pInitVect = initialCounter;
hcryp.Init.Header = authInPadded;
hcryp.Init.HeaderSize = authInSz;
HAL_CRYP_Init(&hcryp);
/* Use inPadded for output buffer instead of
* out so that we don't overflow our size. */
status = HAL_CRYPEx_AESGCM_Decrypt(&hcryp, (byte*)inPadded,
sz, inPadded, STM32_HAL_TIMEOUT);
/* Compute the authTag */
if (status == HAL_OK)
status = HAL_CRYPEx_AESGCM_Finish(&hcryp, sz, tag, STM32_HAL_TIMEOUT);
if (status != HAL_OK)
ret = AES_GCM_AUTH_E;
HAL_CRYP_DeInit(&hcryp);
#else
ByteReverseWords((word32*)keyCopy, (word32*)aes->key, keySize);
/* Input size and auth size need to be the actual sizes, even though
* they are not block aligned, because this length (in bits) is used
* in the final GHASH. Use inPadded for output buffer instead of
* out so that we don't overflow our size. */
status = CRYP_AES_GCM(MODE_DECRYPT, (uint8_t*)initialCounter,
(uint8_t*)keyCopy, keySize * 8,
(uint8_t*)inPadded, sz,
(uint8_t*)authInPadded,authInSz,
(uint8_t*)inPadded, tag);
if (status != SUCCESS)
ret = AES_GCM_AUTH_E;
#endif /* WOLFSSL_STM32_CUBEMX */
if (ret == 0 && ConstantCompare(authTag, tag, authTagSz) == 0) {
/* Only keep the decrypted data if authTag success. */
XMEMCPY(out, inPadded, sz);
ret = 0; /* success */
}
/* only allocate padding buffers if the inputs are not a multiple of block sz */
if (inPadded != NULL && inPadSz != sz)
XFREE(inPadded , aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
if (authInPadded != NULL && authPadSz != authInSz)
XFREE(authInPadded, aes->heap, DYNAMIC_TYPE_TMP_BUFFER);
#else
/* software AES GCM */
#if defined(WOLFSSL_ASYNC_CRYPT) && defined(WC_ASYNC_ENABLE_AES) #if defined(WOLFSSL_ASYNC_CRYPT) && defined(WC_ASYNC_ENABLE_AES)
/* if async and byte count above threshold */ /* if async and byte count above threshold */
if (aes->asyncDev.marker == WOLFSSL_ASYNC_MARKER_AES && if (aes->asyncDev.marker == WOLFSSL_ASYNC_MARKER_AES &&
@ -4496,34 +4801,30 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
} }
XMEMCPY(ctr, initialCounter, AES_BLOCK_SIZE); XMEMCPY(ctr, initialCounter, AES_BLOCK_SIZE);
/* Calculate the authTag again using the received auth data and the /* Calc the authTag again using the received auth data and the cipher text */
* cipher text. */ GHASH(aes, authIn, authInSz, in, sz, Tprime, sizeof(Tprime));
{ wc_AesEncrypt(aes, ctr, EKY0);
byte Tprime[AES_BLOCK_SIZE]; xorbuf(Tprime, EKY0, sizeof(Tprime));
byte EKY0[AES_BLOCK_SIZE];
GHASH(aes, authIn, authInSz, in, sz, Tprime, sizeof(Tprime)); if (ConstantCompare(authTag, Tprime, authTagSz) != 0) {
wc_AesEncrypt(aes, ctr, EKY0); return AES_GCM_AUTH_E;
xorbuf(Tprime, EKY0, sizeof(Tprime));
if (ConstantCompare(authTag, Tprime, authTagSz) != 0) {
return AES_GCM_AUTH_E;
}
} }
#ifdef WOLFSSL_PIC32MZ_CRYPT #ifdef WOLFSSL_PIC32MZ_CRYPT
if(blocks) if (blocks) {
wc_AesCrypt(aes, out, in, blocks*AES_BLOCK_SIZE, wc_AesCrypt(aes, out, in, blocks * AES_BLOCK_SIZE,
PIC32_DECRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_AES_GCM ); PIC32_DECRYPTION, PIC32_ALGO_AES, PIC32_CRYPTOALGO_AES_GCM);
}
/* process remainder using partial handling */
#endif #endif
while (blocks--) { while (blocks--) {
IncrementGcmCounter(ctr); IncrementGcmCounter(ctr);
#ifndef WOLFSSL_PIC32MZ_CRYPT #ifndef WOLFSSL_PIC32MZ_CRYPT
wc_AesEncrypt(aes, ctr, scratch); wc_AesEncrypt(aes, ctr, scratch);
xorbuf(scratch, c, AES_BLOCK_SIZE); xorbuf(scratch, c, AES_BLOCK_SIZE);
XMEMCPY(p, scratch, AES_BLOCK_SIZE); XMEMCPY(p, scratch, AES_BLOCK_SIZE);
#endif #endif
p += AES_BLOCK_SIZE; p += AES_BLOCK_SIZE;
c += AES_BLOCK_SIZE; c += AES_BLOCK_SIZE;
} }
@ -4533,8 +4834,10 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
xorbuf(scratch, c, partial); xorbuf(scratch, c, partial);
XMEMCPY(p, scratch, partial); XMEMCPY(p, scratch, partial);
} }
return 0;
#endif /* FREESCALE_LTC_AES_GCM */ #endif
return ret;
} }
#endif /* HAVE_AES_DECRYPT || HAVE_AESGCM_DECRYPT */ #endif /* HAVE_AES_DECRYPT || HAVE_AESGCM_DECRYPT */

14
wolfcrypt/test/test.c
View File

@ -3892,6 +3892,7 @@ int aes_test(void)
if (XMEMCMP(cipher, ctr128Cipher, sizeof(oddCipher))) if (XMEMCMP(cipher, ctr128Cipher, sizeof(oddCipher)))
return -4216; return -4216;
#if !defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO) /* test not supported on STM32 crypto HW */
/* and an additional 9 bytes to reuse tmp left buffer */ /* and an additional 9 bytes to reuse tmp left buffer */
wc_AesCtrEncrypt(&enc, cipher, ctrPlain, sizeof(oddCipher)); wc_AesCtrEncrypt(&enc, cipher, ctrPlain, sizeof(oddCipher));
wc_AesCtrEncrypt(&dec, plain, cipher, sizeof(oddCipher)); wc_AesCtrEncrypt(&dec, plain, cipher, sizeof(oddCipher));
@ -3901,6 +3902,7 @@ int aes_test(void)
if (XMEMCMP(cipher, oddCipher, sizeof(oddCipher))) if (XMEMCMP(cipher, oddCipher, sizeof(oddCipher)))
return -4218; return -4218;
#endif
/* 192 bit key */ /* 192 bit key */
wc_AesSetKeyDirect(&enc, ctr192Key, sizeof(ctr192Key), wc_AesSetKeyDirect(&enc, ctr192Key, sizeof(ctr192Key),
@ -4217,7 +4219,8 @@ int aesgcm_test(void)
0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b 0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b
}; };
#if !defined(HAVE_FIPS) && !defined(HAVE_INTEL_QA) #if !defined(HAVE_FIPS) && !defined(HAVE_INTEL_QA) && \
!defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO)
/* Test Case 12, uses same plaintext and AAD data. */ /* Test Case 12, uses same plaintext and AAD data. */
const byte k2[] = const byte k2[] =
{ {
@ -4255,7 +4258,7 @@ int aesgcm_test(void)
0xdc, 0xf5, 0x66, 0xff, 0x29, 0x1c, 0x25, 0xbb, 0xdc, 0xf5, 0x66, 0xff, 0x29, 0x1c, 0x25, 0xbb,
0xb8, 0x56, 0x8f, 0xc3, 0xd3, 0x76, 0xa6, 0xd9 0xb8, 0x56, 0x8f, 0xc3, 0xd3, 0x76, 0xa6, 0xd9
}; };
#endif /* !HAVE_FIPS && !HAVE_INTEL_QA */ #endif /* !HAVE_FIPS && !HAVE_INTEL_QA && !STM32F2_CRYPTO && !STM32F4_CRYPTO */
byte resultT[sizeof(t1)]; byte resultT[sizeof(t1)];
byte resultP[sizeof(p)]; byte resultP[sizeof(p)];
@ -4297,8 +4300,9 @@ int aesgcm_test(void)
if (XMEMCMP(p, resultP, sizeof(resultP))) if (XMEMCMP(p, resultP, sizeof(resultP)))
return -4306; return -4306;
/* QAT only supports 12-byte IV */ /* FIPS, QAT and STM32F2/4 HW Crypto only support 12-byte IV */
#if !defined(HAVE_FIPS) && !defined(HAVE_INTEL_QA) #if !defined(HAVE_FIPS) && !defined(HAVE_INTEL_QA) && \
!defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO)
XMEMSET(resultT, 0, sizeof(resultT)); XMEMSET(resultT, 0, sizeof(resultT));
XMEMSET(resultC, 0, sizeof(resultC)); XMEMSET(resultC, 0, sizeof(resultC));
XMEMSET(resultP, 0, sizeof(resultP)); XMEMSET(resultP, 0, sizeof(resultP));
@ -4326,7 +4330,7 @@ int aesgcm_test(void)
return -4310; return -4310;
if (XMEMCMP(p, resultP, sizeof(resultP))) if (XMEMCMP(p, resultP, sizeof(resultP)))
return -4311; return -4311;
#endif /* !HAVE_FIPS && !HAVE_INTEL_QA */ #endif /* !HAVE_FIPS && !HAVE_INTEL_QA && !STM32F2_CRYPTO && !STM32F4_CRYPTO */
wc_AesFree(&enc); wc_AesFree(&enc);