forked from wolfSSL/wolfssl
SP ARM 32: Fixes to get building for armv7-a
Change ldrd to either have even first register or change over to ldm with even first register. Ensure shift value in ORR instruction has a hash before it. Don't index loads and stores by 256 or more - make them post-index. div2 for P521 simplified.
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@ -6254,7 +6254,7 @@ do
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;;
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;;
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*)
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*)
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AC_MSG_ERROR([Invalid choice of Single Precision length in bits [256, 2048, 3072]: $ENABLED_SP.])
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AC_MSG_ERROR([Invalid choice of Single Precision length in bits [256, 384, 521, 1024, 2048, 3072, 4096]: $ENABLED_SP.])
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break;;
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break;;
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esac
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esac
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done
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done
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