diff --git a/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c b/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c index 4efaf2746..bf32ef2dd 100644 --- a/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c +++ b/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c @@ -27,15 +27,15 @@ /*----------------------------------------------------------------------------- * initialize RTC *----------------------------------------------------------------------------*/ -#include +#include #include "lpc43xx_rtc.h" #include "lpc43xx_cgu.h" static void init_RTC() -{ - /* Enable GPIO register interface clock */ - LPC_CCU1->CLK_M4_GPIO_CFG |= 1; - while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 1)) ; +{ + /* Enable GPIO register interface clock */ + LPC_CCU1->CLK_M4_GPIO_CFG |= 1; + while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 1)) ; /* RTC Block section ------------------------------------------------------ */ /* Init RTC module */ @@ -51,7 +51,7 @@ static void init_RTC() RTC_CntIncrIntConfig (LPC_RTC, RTC_TIMETYPE_MINUTE, ENABLE); /* Enable rtc (starts increase the tick counter and second counter register) */ - RTC_Cmd(LPC_RTC, ENABLE); + RTC_Cmd(LPC_RTC, ENABLE); } @@ -60,12 +60,8 @@ static void init_RTC() *----------------------------------------------------------------------------*/ #include "lpc43xx_timer.h" -//#include "lpc43xx_cgu.h" -//#include "lpc43xx_scu.h" -//#include "lpc43xx_libcfg.h" -//#include "debug_frmwrk.h" - -static void init_TIM() + +static void init_TIM() { TIM_TIMERCFG_Type TIM_ConfigStruct; /* Initialize timer 0, prescale count time of 1uS */ @@ -78,93 +74,93 @@ static void init_TIM() TIM_Cmd(LPC_TIMER2,ENABLE); } -double current_time() -{ - return (double)LPC_TIMER2->TC/1000000.0; -} - - -void init_time(void) { - init_RTC() ; - init_TIM() ; -} - -#include - -struct tm *Cyassl_MDK_gmtime(const time_t *c) -{ - static struct tm date ; - - RTC_TIME_Type RTCFullTime; - RTC_GetFullTime (LPC_RTC, &RTCFullTime); - - date.tm_year = RTCFullTime.YEAR + 100 ; - date.tm_mon = RTCFullTime.MONTH - 1 ; - date.tm_mday = RTCFullTime.DOM ; - date.tm_hour = RTCFullTime.HOUR ; - date.tm_min = RTCFullTime.MIN ; - date.tm_sec = RTCFullTime.SEC ; - - #if defined(DEBUG_CYASSL) - { - extern void CYASSL_MSG(char *msg) ; - char msg[100] ; - sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n", - RTCFullTime.YEAR+2000, RTCFullTime.MONTH, RTCFullTime.DOM, - RTCFullTime.HOUR, RTCFullTime.MIN, RTCFullTime.SEC) ; - CYASSL_MSG(msg) ; - } - #endif - - return(&date) ; -} - -typedef struct func_args { - int argc; - char** argv; - int return_code; -} func_args; - -#include - -void time_main(void *args) -{ - char * datetime ; - int year ; - RTC_TIME_Type RTCFullTime; - - if( args == NULL || ((func_args *)args)->argc == 1) { - RTC_GetFullTime (LPC_RTC, &RTCFullTime); - printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", - RTCFullTime.MONTH, RTCFullTime.DOM, RTCFullTime.YEAR+2000, - RTCFullTime.HOUR, RTCFullTime.MIN, RTCFullTime.SEC) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 'd' ) { - - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d/%d/%d", - (int *)&RTCFullTime.MONTH, (int *)&RTCFullTime.DOM, &year) ; - RTCFullTime.YEAR = year - 2000 ; - RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MONTH, RTCFullTime.MONTH); - RTC_SetTime (LPC_RTC, RTC_TIMETYPE_YEAR, RTCFullTime.YEAR); - RTC_SetTime (LPC_RTC, RTC_TIMETYPE_DAYOFMONTH, RTCFullTime.DOM); - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 't' ) { - RTC_GetFullTime (LPC_RTC, &RTCFullTime); - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d:%d:%d", - (int *)&RTCFullTime.HOUR, - (int *)&RTCFullTime.MIN, - (int *)&RTCFullTime.SEC - ) ; - RTC_SetTime (LPC_RTC, RTC_TIMETYPE_SECOND, RTCFullTime.SEC); - RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MINUTE, RTCFullTime.MIN); - RTC_SetTime (LPC_RTC, RTC_TIMETYPE_HOUR, RTCFullTime.HOUR); - } else printf("Invalid argument\n") ; -} - - - - +double current_time() +{ + return (double)LPC_TIMER2->TC/1000000.0; +} + + +void init_time(void) { + init_RTC() ; + init_TIM() ; +} + +#include + +struct tm *Cyassl_MDK_gmtime(const time_t *c) +{ + static struct tm date ; + + RTC_TIME_Type RTCFullTime; + RTC_GetFullTime (LPC_RTC, &RTCFullTime); + + date.tm_year = RTCFullTime.YEAR + 100 ; + date.tm_mon = RTCFullTime.MONTH - 1 ; + date.tm_mday = RTCFullTime.DOM ; + date.tm_hour = RTCFullTime.HOUR ; + date.tm_min = RTCFullTime.MIN ; + date.tm_sec = RTCFullTime.SEC ; + + #if defined(DEBUG_CYASSL) + { + extern void CYASSL_MSG(char *msg) ; + char msg[100] ; + sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n", + RTCFullTime.YEAR+2000, RTCFullTime.MONTH, RTCFullTime.DOM, + RTCFullTime.HOUR, RTCFullTime.MIN, RTCFullTime.SEC) ; + CYASSL_MSG(msg) ; + } + #endif + + return(&date) ; +} + +typedef struct func_args { + int argc; + char** argv; + int return_code; +} func_args; + +#include + +void time_main(void *args) +{ + char * datetime ; + int year ; + RTC_TIME_Type RTCFullTime; + + if( args == NULL || ((func_args *)args)->argc == 1) { + RTC_GetFullTime (LPC_RTC, &RTCFullTime); + printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", + RTCFullTime.MONTH, RTCFullTime.DOM, RTCFullTime.YEAR+2000, + RTCFullTime.HOUR, RTCFullTime.MIN, RTCFullTime.SEC) ; + } else if(((func_args *)args)->argc == 3 && + ((func_args *)args)->argv[1][0] == '-' && + ((func_args *)args)->argv[1][1] == 'd' ) { + + datetime = ((func_args *)args)->argv[2]; + sscanf(datetime, "%d/%d/%d", + (int *)&RTCFullTime.MONTH, (int *)&RTCFullTime.DOM, &year) ; + RTCFullTime.YEAR = year - 2000 ; + RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MONTH, RTCFullTime.MONTH); + RTC_SetTime (LPC_RTC, RTC_TIMETYPE_YEAR, RTCFullTime.YEAR); + RTC_SetTime (LPC_RTC, RTC_TIMETYPE_DAYOFMONTH, RTCFullTime.DOM); + } else if(((func_args *)args)->argc == 3 && + ((func_args *)args)->argv[1][0] == '-' && + ((func_args *)args)->argv[1][1] == 't' ) { + RTC_GetFullTime (LPC_RTC, &RTCFullTime); + datetime = ((func_args *)args)->argv[2]; + sscanf(datetime, "%d:%d:%d", + (int *)&RTCFullTime.HOUR, + (int *)&RTCFullTime.MIN, + (int *)&RTCFullTime.SEC + ) ; + RTC_SetTime (LPC_RTC, RTC_TIMETYPE_SECOND, RTCFullTime.SEC); + RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MINUTE, RTCFullTime.MIN); + RTC_SetTime (LPC_RTC, RTC_TIMETYPE_HOUR, RTCFullTime.HOUR); + } else printf("Invalid argument\n") ; +} + + + + diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/Retarget.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/Retarget.c index 00aaef181..bb59c8ce1 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/Retarget.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/Retarget.c @@ -259,11 +259,3 @@ void _sys_exit (int return_code) } -/*--------------------------- time -----------------------------------------*/ -long time(long *t) -{ - return ((long) 0) ; /** DUMMY TIME() **/ -} -/*----------------------------------------------------------------------------- - * end of file - *----------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c index f0959de12..ab6e4d8c5 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c @@ -1,23 +1,23 @@ -/* cyassl_KEIL_RL.c - * - * Copyright (C) 2006-2013 wolfSSL Inc. - * - * This file is part of CyaSSL. - * - * CyaSSL is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * CyaSSL is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA - */ +/* cyassl_MDK_ARM.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ /***************************************************************************************/ @@ -28,17 +28,29 @@ #endif #include +#if defined (CYASSL_MDK5) + #include "cmsis_os.h" + #if defined(CYASSL_KEIL_TCP_NET) + #include "rl_net.h" + #endif +#else + #include +#endif -#include #include "cyassl_MDK_ARM.h" #include #include +#if defined (CYASSL_CMSIS_RTOS) + #define os_dly_wait(t) osDelay(10*t) +#endif + /** KEIL-RL TCPnet ****/ /** TCPnet BSD socket does not have following functions. **/ +#if defined(CYASSL_KEIL_TCP_NET) char *inet_ntoa(struct in_addr in) { #define NAMESIZE 16 @@ -115,7 +127,7 @@ int Cyassl_recv(int sd, void *buf, size_t len, int flags) while(1) { #undef recv /* Go to KEIL TCPnet recv */ ret = recv(sd, buf, len, flags) ; - if(ret != SCK_EWOULDBLOCK) break ; + if((ret != SCK_EWOULDBLOCK) &&( ret != SCK_ETIMEOUT)) break ; os_dly_wait(1); } #ifdef DEBUG_CYASSL @@ -154,6 +166,8 @@ int Cyassl_send(int sd, const void *buf, size_t len, int flags) } +#endif /* CYASSL_KEIL_TCP_NET */ + #if defined(CYASSL_KEIL_TCP_NET) void Cyassl_sleep(int t) { @@ -170,18 +184,52 @@ int Cyassl_tcp_select(int sd, int timeout) } #endif +extern int strlen(const char *s) ; +FILE * CyaSSL_fopen(const char *name, const char *openmode) +{ + int i ; FILE * ret ; + #define PATHSIZE 100 + char path[PATHSIZE] ; char *p ; + + if(strlen(name) > PATHSIZE)return(NULL) ; + + for(i = 0; i<= strlen(name); i++) { + if(name[i] == '/')path[i] = '\\' ; + else path[i] = name[i] ; + } + if(path[0] == '.' && path[1] == '\\') p = path + 2 ; + else p = path ; + + ret = fopen (p, openmode) ; + + return(ret) ; +} + +#if defined (CYASSL_MDK5) +#define getkey getchar +#define sendchar putchar +#else extern int getkey(void) ; extern int sendchar(int c) ; +#endif char * Cyassl_fgets ( char * str, int num, FILE * f ) { int i ; for(i = 0 ; i< num ; i++) { - while((str[i] = getkey()) == 0) ; + while((str[i] = getkey()) == 0) { + #if defined (HAVE_KEIL_RTX) + #if !defined(CYASSL_CMSIS_RTOS) + os_tsk_pass (); + #else + osThreadYield (); + #endif + #endif + } if(str[i] == '\n' || str[i] == '\012' || str[i] == '\015') { - sendchar('\n') ; + sendchar('\n') ; str[i++] = '\n' ; str[i] = '\0' ; break ; diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c index 7a39b51f4..8883a88dd 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c @@ -108,7 +108,7 @@ void main_task (void) init_TcpNet (); os_tsk_create (tcp_tick, 2); - os_tsk_create (tcp_poll, 1); + os_tsk_create (tcp_poll, 1); #endif #ifdef CYASSL_MDK_SHELL @@ -122,7 +122,7 @@ void main_task (void) /************************************/ /*** USER APPLICATION HERE ***/ /************************************/ - printf("USER LOGIC STARTED\n") ; + printf("USER LOGIC STARTED\n") ; #endif @@ -137,37 +137,36 @@ void main_task (void) int myoptind = 0; char* myoptarg = NULL; - #if defined(DEBUG_CYASSL) - extern void CyaSSL_Debugging_ON(void) ; +#if defined(DEBUG_CYASSL) + extern void CyaSSL_Debugging_ON(void) ; #endif /*** main entry ***/ -extern void init_time(void) ; -extern void SystemInit(void); - -int main() { - - SystemInit(); - SER_Init() ; - #if !defined(NO_FILESYSTEM) - init_card () ; /* initializing SD card */ - #endif - - init_time() ; +extern void init_time(void) ; +extern void SystemInit(void); + +int main() { + + SystemInit(); + SER_Init() ; + #if !defined(NO_FILESYSTEM) + init_card () ; /* initializing SD card */ + #endif + + init_time() ; - #if defined(DEBUG_CYASSL) printf("Turning ON Debug message\n") ; CyaSSL_Debugging_ON() ; #endif #ifdef HAVE_KEIL_RTX - os_sys_init (main_task) ; + os_sys_init (main_task) ; #else - main_task() ; + main_task() ; #endif - + return 0 ; /* There should be no return here */ } diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c index 024d10373..261fa2edc 100644 --- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c +++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c @@ -45,9 +45,9 @@ int CyaSSL_get_using_nonblock(CYASSL* ssl) CYASSL_LEAVE("CyaSSL_get_using_nonblock", ssl->options.usingNonblock); return ssl->options.usingNonblock; } - -Signer* GetCAByName(void* vp, byte* hash) -{ - Signer * ca ; - return(ca) ; + +Signer* GetCAByName(void* vp, byte* hash) +{ + Signer * ca ; + return(ca) ; } diff --git a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c index 96b6dada2..9a162ba88 100644 --- a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c +++ b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c @@ -1,401 +1,401 @@ -/*---------------------------------------------------------------------------- - * RL-ARM - FlashFS - *---------------------------------------------------------------------------- - * Name: FILE_CONFIG.C - * Purpose: Configuration of RL FlashFS by user - * Rev.: V4.70 - *---------------------------------------------------------------------------- - * This code is part of the RealView Run-Time Library. - * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ - -#include - -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -// -// File System -// ============== -// Define File System global parameters - -// Number of open files <4-16> -// Define number of files that can be -// opened at the same time. -// Default: 8 -#define N_FILES 6 - -// FAT Name Cache Size <0-1000000> -// Define number of cached FAT file or directory names. -// 48 bytes of RAM is required for each cached name. -#define FAT_NAME_CACNT 0 - -// Relocate FAT Name Cache Buffer -// Locate Cache Buffer at a specific address. -#define FAT_NAME_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -#define FAT_NAME_CADR 0x60000000 - -// -// CPU Clock Frequency [Hz]<0-1000000000> -// Define the CPU Clock frequency used for -// flash programming and erasing. -#define CPU_CLK 180000000 - -// -// Flash Drive -// ============== -// Enable Embedded Flash Drive [F:] -#define FL0_EN 0 - -// Base address <0x0-0xFFFFF000:0x1000> -// Define the target device Base address -// Default: 0x80000000 -#define FL0_BADR 0x80000000 - -// Device Size <0x4000-0xFFFFF000:0x4000> -// Define the size of Flash device in bytes -// Default: 0x100000 (1MB) -#define FL0_SIZE 0x0200000 - -// Content of Erased Memory <0=>0x00 <0xFF=>0xFF -// Define the initial value for erased Flash data -// Default: 0xFF -#define FL0_INITV 0xFF - -// Device Description file -// Specify a file name with a relative path -// Default: FS_FlashDev.h -#define FL0_HFILE "FS_FlashDev.h" - -// Default Drive [F:] -// Used when Drive letter not specified -#define FL0_DEF 1 - -// -// SPI Flash Drive -// ================== -// Enable SPI Flash Drive [S:] -#define SF0_EN 0 - -// Device Size <0x10000-0xFFFFF000:0x8000> -// Define the size of SPI Flash device in bytes -// Default: 0x100000 (1MB) -#define SF0_SIZE 0x0200000 - -// Content of Erased Memory <0=>0x00 <0xFF=>0xFF -// Define the initial value for erased Flash data -// Default: 0xFF -#define SF0_INITV 0xFF - -// Device Description file -// Specify a file name with a relative path -// Default: FS_SPI_FlashDev.h -#define SF0_HFILE "FS_SPI_FlashDev.h" - -// Default Drive [S:] -// Used when Drive letter not specified -#define SF0_DEF 0 - -// -// RAM Drive -// ============ -// Enable Embedded RAM Drive [R:] -#define RAM0_EN 0 - -// Device Size <0x4000-0xFFFFF000:0x4000> -// Define the size of RAM device in bytes -// Default: 0x40000 -#define RAM0_SIZE 0x004000 - -// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 -// Define number of virtual sectors for RAM device -// Default: 32 -#define RAM0_NSECT 64 - -// Relocate Device Buffer -// Locate RAM Device Buffer at a specific address. -// If not enabled, the linker selects base address. -#define RAM0_RELOC 1 - -// Base address <0x0-0xFFFFF000:0x1000> -// Define the target device Base address. -// Default: 0x81000000 -#define RAM0_BADR 0x81010000 - -// -// Default Drive [R:] -// Used when Drive letter not specified -#define RAM0_DEF 0 - -// -// Memory Card Drive 0 -// ====================== -// Enable Memory Card Drive [M0:] -#define MC0_EN 1 - -// Bus Mode <0=>SD-Native <1=>SPI -// Define Memory Card bus interface mode. -// SD-Native mode needs MCI peripheral. -// SPI mode uses SD Card in SPI mode. -#define MC0_SPI 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define MC0_CASZ 4 - -// Relocate Cache Buffer -// Locate Cache Buffer at a specific address. -// Some devices like NXP LPC23xx require a Cache buffer -// for DMA transfer located at specific address. -#define MC0_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -// For LPC23xx/24xx devices this is USB RAM -// starting at 0x7FD00000. -#define MC0_CADR 0x7FD00000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define MC0_FSJ 0 - -// Default Drive [M0:] -// Used when Drive letter not specified -#define MC0_DEF 1 - -// -// Memory Card Drive 1 -// ====================== -// Enable Memory Card Drive [M1:] -#define MC1_EN 0 - -// Bus Mode <0=>SD-Native <1=>SPI -// Define Memory Card bus interface mode. -// SD-Native mode needs MCI peripheral. -// SPI mode uses SD Card in SPI mode. -#define MC1_SPI 1 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define MC1_CASZ 0 - -// Relocate Cache Buffer -// Locate Cache Buffer at a specific address. -// Some devices like NXP LPC23xx require a Cache buffer -// for DMA transfer located at specific address. -#define MC1_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define the Cache buffer base address. -// For LPC23xx/24xx devices this is USB RAM -// starting at 0x7FD00000. -#define MC1_CADR 0x7FD00000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define MC1_FSJ 0 - -// Default Drive [M1:] -// Used when Drive letter not specified -#define MC1_DEF 0 - -// -// USB Flash Drive 0 -// ==================== -// Enable USB Flash Drive [U0:] -#define USB0_EN 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define USB0_CASZ 8 - -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define USB0_FSJ 0 - -// Default Drive [U0:] -// Used when Drive letter not specified -#define USB0_DEF 0 - -// -// USB Flash Drive 1 -// ==================== -// Enable USB Flash Drive [U1:] -#define USB1_EN 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define USB1_CASZ 8 - -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define USB1_FSJ 0 - -// Default Drive [U1:] -// Used when Drive letter not specified -#define USB1_DEF 0 - -// -// NAND Flash Drive 0 -// =================== -// Enable NAND Flash Drive [N0:] -#define NAND0_EN 0 - -// Page size <528=> 512 + 16 bytes -// <2112=>2048 + 64 bytes -// <4224=>4096 + 128 bytes -// <8448=>8192 + 256 bytes -// Define program Page size in bytes (User + Spare area). -#define NAND0_PGSZ 2112 - -// Block Size <8=>8 pages <16=>16 pages <32=>32 pages -// <64=>64 pages <128=>128 pages <256=>256 pages -// Define number of pages in a block. -#define NAND0_PGCNT 64 - -// Device Size [blocks] <512-32768> -// Define number of blocks in NAND Flash device. -#define NAND0_BLCNT 4096 - -// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages -// <8=>8 pages <16=>16 pages <32=>32 pages -// Define number of cached Pages. -// Default: 4 pages -#define NAND0_CAPG 2 - -// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks -// <8=>8 blocks <16=>16 blocks <32=>32 blocks -// <64=>64 blocks <128=>128 blocks <256=>256 blocks -// Define number of indexed Flash Blocks. -// Increase this number for better performance. -// Default: 16 blocks -#define NAND0_CABL 16 - -// Software ECC <0=>None <1=>Hamming (SLC) -// Enable software ECC calculation only, -// if not supported by hardware. -#define NAND0_SWECC 1 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define NAND0_CASZ 4 - -// Relocate Cache Buffers -// Use this option to locate Cache buffers -// at specific address in RAM or SDRAM. -#define NAND0_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define base address for Cache Buffers. -#define NAND0_CADR 0x80000000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define NAND0_FSJ 0 - -// Default Drive [N0:] -// Used when Drive letter not specified -#define NAND0_DEF 0 - -// -// NAND Flash Drive 1 -// =================== -// Enable NAND Flash Drive [N1:] -#define NAND1_EN 0 - -// Page size <528=> 512 + 16 bytes -// <2112=>2048 + 64 bytes -// <4224=>4096 + 128 bytes -// <8448=>8192 + 256 bytes -// Define program Page size in bytes (User + Spare area). -#define NAND1_PGSZ 2112 - -// Block Size <8=>8 pages <16=>16 pages <32=>32 pages -// <64=>64 pages <128=>128 pages <256=>256 pages -// Define number of pages in a block. -#define NAND1_PGCNT 32 - -// Device Size [blocks] <512-32768> -// Define number of blocks in NAND Flash device. -#define NAND1_BLCNT 512 - -// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages -// <8=>8 pages <16=>16 pages <32=>32 pages -// Define number of cached Pages. -// Default: 4 pages -#define NAND1_CAPG 4 - -// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks -// <8=>8 blocks <16=>16 blocks <32=>32 blocks -// <64=>64 blocks <128=>128 blocks <256=>256 blocks -// Define number of indexed Flash Blocks. -// Increase this number for better performance. -// Default: 16 blocks -#define NAND1_CABL 16 - -// Software ECC <0=>None <1=>Hamming (SLC) -// Enable software ECC calculation only, -// if not supported by hardware. -#define NAND1_SWECC 0 - -// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB -// <8=>8 KB <16=>16 KB <32=>32 KB -// Define System Cache buffer size for file IO. -// Increase this number for faster r/w access. -// Default: 4 kB -#define NAND1_CASZ 4 - -// Relocate Cache Buffers -// Use this option to locate Cache buffers -// at specific address in RAM or SDRAM. -#define NAND1_RELOC 0 - -// Base address <0x0000-0xFFFFFE00:0x200> -// Define base address for Cache Buffers. -#define NAND1_CADR 0x80000000 - -// -// FAT Journal -// Enable FAT Journal in order to guarantee -// fail-safe FAT file system operation. -#define NAND1_FSJ 0 - -// Default Drive [N1:] -// Used when Drive letter not specified -#define NAND1_DEF 0 - -// - -//------------- <<< end of configuration section >>> ----------------------- - -#ifndef __NO_FILE_LIB_C -#include -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * RL-ARM - FlashFS + *---------------------------------------------------------------------------- + * Name: FILE_CONFIG.C + * Purpose: Configuration of RL FlashFS by user + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * This code is part of the RealView Run-Time Library. + * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved. + *---------------------------------------------------------------------------*/ + +#include + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// File System +// ============== +// Define File System global parameters + +// Number of open files <4-16> +// Define number of files that can be +// opened at the same time. +// Default: 8 +#define N_FILES 6 + +// FAT Name Cache Size <0-1000000> +// Define number of cached FAT file or directory names. +// 48 bytes of RAM is required for each cached name. +#define FAT_NAME_CACNT 0 + +// Relocate FAT Name Cache Buffer +// Locate Cache Buffer at a specific address. +#define FAT_NAME_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +#define FAT_NAME_CADR 0x60000000 + +// +// CPU Clock Frequency [Hz]<0-1000000000> +// Define the CPU Clock frequency used for +// flash programming and erasing. +#define CPU_CLK 180000000 + +// +// Flash Drive +// ============== +// Enable Embedded Flash Drive [F:] +#define FL0_EN 0 + +// Base address <0x0-0xFFFFF000:0x1000> +// Define the target device Base address +// Default: 0x80000000 +#define FL0_BADR 0x80000000 + +// Device Size <0x4000-0xFFFFF000:0x4000> +// Define the size of Flash device in bytes +// Default: 0x100000 (1MB) +#define FL0_SIZE 0x0200000 + +// Content of Erased Memory <0=>0x00 <0xFF=>0xFF +// Define the initial value for erased Flash data +// Default: 0xFF +#define FL0_INITV 0xFF + +// Device Description file +// Specify a file name with a relative path +// Default: FS_FlashDev.h +#define FL0_HFILE "FS_FlashDev.h" + +// Default Drive [F:] +// Used when Drive letter not specified +#define FL0_DEF 1 + +// +// SPI Flash Drive +// ================== +// Enable SPI Flash Drive [S:] +#define SF0_EN 0 + +// Device Size <0x10000-0xFFFFF000:0x8000> +// Define the size of SPI Flash device in bytes +// Default: 0x100000 (1MB) +#define SF0_SIZE 0x0200000 + +// Content of Erased Memory <0=>0x00 <0xFF=>0xFF +// Define the initial value for erased Flash data +// Default: 0xFF +#define SF0_INITV 0xFF + +// Device Description file +// Specify a file name with a relative path +// Default: FS_SPI_FlashDev.h +#define SF0_HFILE "FS_SPI_FlashDev.h" + +// Default Drive [S:] +// Used when Drive letter not specified +#define SF0_DEF 0 + +// +// RAM Drive +// ============ +// Enable Embedded RAM Drive [R:] +#define RAM0_EN 0 + +// Device Size <0x4000-0xFFFFF000:0x4000> +// Define the size of RAM device in bytes +// Default: 0x40000 +#define RAM0_SIZE 0x004000 + +// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 +// Define number of virtual sectors for RAM device +// Default: 32 +#define RAM0_NSECT 64 + +// Relocate Device Buffer +// Locate RAM Device Buffer at a specific address. +// If not enabled, the linker selects base address. +#define RAM0_RELOC 1 + +// Base address <0x0-0xFFFFF000:0x1000> +// Define the target device Base address. +// Default: 0x81000000 +#define RAM0_BADR 0x81010000 + +// +// Default Drive [R:] +// Used when Drive letter not specified +#define RAM0_DEF 0 + +// +// Memory Card Drive 0 +// ====================== +// Enable Memory Card Drive [M0:] +#define MC0_EN 1 + +// Bus Mode <0=>SD-Native <1=>SPI +// Define Memory Card bus interface mode. +// SD-Native mode needs MCI peripheral. +// SPI mode uses SD Card in SPI mode. +#define MC0_SPI 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define MC0_CASZ 4 + +// Relocate Cache Buffer +// Locate Cache Buffer at a specific address. +// Some devices like NXP LPC23xx require a Cache buffer +// for DMA transfer located at specific address. +#define MC0_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +// For LPC23xx/24xx devices this is USB RAM +// starting at 0x7FD00000. +#define MC0_CADR 0x7FD00000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define MC0_FSJ 0 + +// Default Drive [M0:] +// Used when Drive letter not specified +#define MC0_DEF 1 + +// +// Memory Card Drive 1 +// ====================== +// Enable Memory Card Drive [M1:] +#define MC1_EN 0 + +// Bus Mode <0=>SD-Native <1=>SPI +// Define Memory Card bus interface mode. +// SD-Native mode needs MCI peripheral. +// SPI mode uses SD Card in SPI mode. +#define MC1_SPI 1 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define MC1_CASZ 0 + +// Relocate Cache Buffer +// Locate Cache Buffer at a specific address. +// Some devices like NXP LPC23xx require a Cache buffer +// for DMA transfer located at specific address. +#define MC1_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +// For LPC23xx/24xx devices this is USB RAM +// starting at 0x7FD00000. +#define MC1_CADR 0x7FD00000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define MC1_FSJ 0 + +// Default Drive [M1:] +// Used when Drive letter not specified +#define MC1_DEF 0 + +// +// USB Flash Drive 0 +// ==================== +// Enable USB Flash Drive [U0:] +#define USB0_EN 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define USB0_CASZ 8 + +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define USB0_FSJ 0 + +// Default Drive [U0:] +// Used when Drive letter not specified +#define USB0_DEF 0 + +// +// USB Flash Drive 1 +// ==================== +// Enable USB Flash Drive [U1:] +#define USB1_EN 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define USB1_CASZ 8 + +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define USB1_FSJ 0 + +// Default Drive [U1:] +// Used when Drive letter not specified +#define USB1_DEF 0 + +// +// NAND Flash Drive 0 +// =================== +// Enable NAND Flash Drive [N0:] +#define NAND0_EN 0 + +// Page size <528=> 512 + 16 bytes +// <2112=>2048 + 64 bytes +// <4224=>4096 + 128 bytes +// <8448=>8192 + 256 bytes +// Define program Page size in bytes (User + Spare area). +#define NAND0_PGSZ 2112 + +// Block Size <8=>8 pages <16=>16 pages <32=>32 pages +// <64=>64 pages <128=>128 pages <256=>256 pages +// Define number of pages in a block. +#define NAND0_PGCNT 64 + +// Device Size [blocks] <512-32768> +// Define number of blocks in NAND Flash device. +#define NAND0_BLCNT 4096 + +// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages +// <8=>8 pages <16=>16 pages <32=>32 pages +// Define number of cached Pages. +// Default: 4 pages +#define NAND0_CAPG 2 + +// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks +// <8=>8 blocks <16=>16 blocks <32=>32 blocks +// <64=>64 blocks <128=>128 blocks <256=>256 blocks +// Define number of indexed Flash Blocks. +// Increase this number for better performance. +// Default: 16 blocks +#define NAND0_CABL 16 + +// Software ECC <0=>None <1=>Hamming (SLC) +// Enable software ECC calculation only, +// if not supported by hardware. +#define NAND0_SWECC 1 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define NAND0_CASZ 4 + +// Relocate Cache Buffers +// Use this option to locate Cache buffers +// at specific address in RAM or SDRAM. +#define NAND0_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define base address for Cache Buffers. +#define NAND0_CADR 0x80000000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define NAND0_FSJ 0 + +// Default Drive [N0:] +// Used when Drive letter not specified +#define NAND0_DEF 0 + +// +// NAND Flash Drive 1 +// =================== +// Enable NAND Flash Drive [N1:] +#define NAND1_EN 0 + +// Page size <528=> 512 + 16 bytes +// <2112=>2048 + 64 bytes +// <4224=>4096 + 128 bytes +// <8448=>8192 + 256 bytes +// Define program Page size in bytes (User + Spare area). +#define NAND1_PGSZ 2112 + +// Block Size <8=>8 pages <16=>16 pages <32=>32 pages +// <64=>64 pages <128=>128 pages <256=>256 pages +// Define number of pages in a block. +#define NAND1_PGCNT 32 + +// Device Size [blocks] <512-32768> +// Define number of blocks in NAND Flash device. +#define NAND1_BLCNT 512 + +// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages +// <8=>8 pages <16=>16 pages <32=>32 pages +// Define number of cached Pages. +// Default: 4 pages +#define NAND1_CAPG 4 + +// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks +// <8=>8 blocks <16=>16 blocks <32=>32 blocks +// <64=>64 blocks <128=>128 blocks <256=>256 blocks +// Define number of indexed Flash Blocks. +// Increase this number for better performance. +// Default: 16 blocks +#define NAND1_CABL 16 + +// Software ECC <0=>None <1=>Hamming (SLC) +// Enable software ECC calculation only, +// if not supported by hardware. +#define NAND1_SWECC 0 + +// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Define System Cache buffer size for file IO. +// Increase this number for faster r/w access. +// Default: 4 kB +#define NAND1_CASZ 4 + +// Relocate Cache Buffers +// Use this option to locate Cache buffers +// at specific address in RAM or SDRAM. +#define NAND1_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define base address for Cache Buffers. +#define NAND1_CADR 0x80000000 + +// +// FAT Journal +// Enable FAT Journal in order to guarantee +// fail-safe FAT file system operation. +#define NAND1_FSJ 0 + +// Default Drive [N1:] +// Used when Drive letter not specified +#define NAND1_DEF 0 + +// + +//------------- <<< end of configuration section >>> ----------------------- + +#ifndef __NO_FILE_LIB_C +#include +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt index e93e9595f..ddc1a5000 100644 --- a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt +++ b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt @@ -29,8 +29,8 @@ 1 1 - 1 - 0 + 0 + 1 1 @@ -73,7 +73,7 @@ 1 0 - 1 + 0 255 @@ -120,6 +120,11 @@ BIN\ULP2CM3.DLL + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + 0 DLGTARM @@ -229,7 +234,7 @@ 1 0 - 0 + 1 255 @@ -532,7 +537,7 @@ 1 0 0 - 0 + 5 0 0 0 @@ -614,8 +619,8 @@ 0 0 0 - 0 - 0 + 106 + 149 0 ..\MDK-ARM\CyaSSL\main.c main.c @@ -642,122 +647,10 @@ STM32F2xx_StdPeriph_Lib - 0 + 1 0 0 0 - - 2 - 10 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_cryp.c - stm32f2xx_cryp.c - 0 - 0 - - - 2 - 11 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_hash.c - stm32f2xx_hash.c - 0 - 0 - - - 2 - 12 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rcc.c - stm32f2xx_rcc.c - 0 - 0 - - - 2 - 13 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rng.c - stm32f2xx_rng.c - 0 - 0 - - - 2 - 14 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rtc.c - stm32f2xx_rtc.c - 0 - 0 - - - 2 - 15 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_pwr.c - stm32f2xx_pwr.c - 0 - 0 - - - 2 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_tim.c - stm32f2xx_tim.c - 0 - 0 - @@ -768,7 +661,7 @@ 0 3 - 17 + 10 1 0 0 @@ -784,7 +677,7 @@ 3 - 18 + 11 1 0 0 @@ -800,7 +693,7 @@ 3 - 19 + 12 4 0 0 @@ -816,7 +709,7 @@ 3 - 20 + 13 4 0 0 @@ -832,7 +725,7 @@ 3 - 21 + 14 1 0 0 @@ -848,7 +741,7 @@ 3 - 22 + 15 4 0 0 @@ -864,7 +757,7 @@ 3 - 23 + 16 4 0 0 @@ -880,7 +773,7 @@ 3 - 24 + 17 1 0 0 @@ -904,7 +797,7 @@ 0 4 - 25 + 18 1 0 0 @@ -920,7 +813,7 @@ 4 - 26 + 19 1 0 0 @@ -936,7 +829,7 @@ 4 - 27 + 20 1 0 0 @@ -952,7 +845,7 @@ 4 - 28 + 21 1 0 0 @@ -968,7 +861,7 @@ 4 - 29 + 22 1 0 0 @@ -984,7 +877,7 @@ 4 - 30 + 23 1 0 0 @@ -1000,7 +893,7 @@ 4 - 31 + 24 1 0 0 @@ -1016,7 +909,7 @@ 4 - 32 + 25 1 0 0 @@ -1032,7 +925,7 @@ 4 - 33 + 26 1 0 0 @@ -1056,7 +949,7 @@ 0 5 - 34 + 27 1 0 0 @@ -1072,7 +965,7 @@ 5 - 35 + 28 1 0 0 @@ -1088,7 +981,7 @@ 5 - 36 + 29 1 0 0 @@ -1104,7 +997,7 @@ 5 - 37 + 30 1 0 0 @@ -1120,7 +1013,7 @@ 5 - 38 + 31 1 0 0 @@ -1136,7 +1029,7 @@ 5 - 39 + 32 1 0 0 @@ -1152,7 +1045,7 @@ 5 - 40 + 33 1 0 0 @@ -1168,7 +1061,7 @@ 5 - 41 + 34 1 0 0 @@ -1184,7 +1077,7 @@ 5 - 42 + 35 1 0 0 @@ -1200,7 +1093,7 @@ 5 - 43 + 36 1 0 0 @@ -1216,7 +1109,7 @@ 5 - 44 + 37 1 0 0 @@ -1232,7 +1125,7 @@ 5 - 45 + 38 1 0 0 @@ -1248,7 +1141,7 @@ 5 - 46 + 39 1 0 0 @@ -1264,7 +1157,7 @@ 5 - 47 + 40 1 0 0 @@ -1280,7 +1173,7 @@ 5 - 48 + 41 1 0 0 @@ -1296,7 +1189,7 @@ 5 - 49 + 42 1 0 0 @@ -1312,7 +1205,7 @@ 5 - 50 + 43 1 0 0 @@ -1328,7 +1221,7 @@ 5 - 51 + 44 1 0 0 @@ -1344,7 +1237,7 @@ 5 - 52 + 45 1 0 0 @@ -1360,7 +1253,7 @@ 5 - 53 + 46 1 0 0 @@ -1376,7 +1269,7 @@ 5 - 54 + 47 1 0 0 @@ -1392,7 +1285,23 @@ 5 - 55 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\..\ctaocrypt\src\port.c + port.c + 0 + 0 + + + 5 + 49 1 0 0 @@ -1408,7 +1317,7 @@ 5 - 56 + 50 1 0 0 @@ -1424,7 +1333,7 @@ 5 - 57 + 51 1 0 0 @@ -1440,7 +1349,7 @@ 5 - 58 + 52 1 0 0 @@ -1456,7 +1365,7 @@ 5 - 59 + 53 1 0 0 @@ -1472,7 +1381,7 @@ 5 - 60 + 54 1 0 0 @@ -1488,7 +1397,7 @@ 5 - 61 + 55 1 0 0 @@ -1504,7 +1413,7 @@ 5 - 62 + 56 1 0 0 @@ -1520,7 +1429,7 @@ 5 - 63 + 57 1 0 0 @@ -1534,33 +1443,17 @@ 0 0 - - 5 - 64 - 1 - 0 - 0 - 9 - 0 - 0 - 0 - 0 - ..\..\..\ctaocrypt\src\port.c - port.c - 0 - 0 - Configuration - 0 + 1 0 0 0 6 - 65 + 58 1 0 0 @@ -1576,7 +1469,7 @@ 6 - 66 + 59 1 0 0 @@ -1592,7 +1485,7 @@ 6 - 67 + 60 5 0 0 @@ -1608,7 +1501,7 @@ 6 - 68 + 61 1 0 0 @@ -1624,7 +1517,7 @@ 6 - 69 + 62 1 0 0 @@ -1640,14 +1533,14 @@ 6 - 70 + 63 5 0 0 0 0 - 0 - 0 + 1 + 1 0 ..\MDK-ARM\CyaSSL\config-FS.h config-FS.h @@ -1656,7 +1549,7 @@ 6 - 71 + 64 5 0 0 @@ -1672,7 +1565,7 @@ 6 - 72 + 65 5 0 0 @@ -1688,14 +1581,14 @@ 6 - 73 + 66 2 0 0 0 0 - 0 - 0 + 152 + 169 0 ..\MDK-ARM\config\startup_stm32f2xx.s startup_stm32f2xx.s @@ -1712,14 +1605,14 @@ 0 7 - 74 + 67 1 0 0 0 0 - 0 - 0 + 182 + 222 0 ..\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c cyassl_MDK_ARM.c @@ -1728,9 +1621,9 @@ 7 - 75 + 68 1 - 0 + 1 0 0 0 @@ -1744,11 +1637,11 @@ 7 - 76 + 69 1 0 0 - 0 + 1 0 0 0 diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj index 7f2501b14..833dc0d1b 100644 --- a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj +++ b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj @@ -165,7 +165,7 @@ 1 4100 - 0 + 1 BIN\ULP2CM3.DLL "" () @@ -349,7 +349,7 @@ 0 - HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM __RTX USE_STDPERIPH_DRIVER MDK_CONF_RTX_TCP_FS + HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM __RTX MDK_CONF_RTX_TCP_FS ..\MDK-ARM\CyaSSL;C:..\STM32F2xx_StdPeriph_Lib\inc;..\..\..\ @@ -441,43 +441,6 @@ STM32F2xx_StdPeriph_Lib - - - stm32f2xx_cryp.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_cryp.c - - - stm32f2xx_hash.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_hash.c - - - stm32f2xx_rcc.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rcc.c - - - stm32f2xx_rng.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rng.c - - - stm32f2xx_rtc.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rtc.c - - - stm32f2xx_pwr.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_pwr.c - - - stm32f2xx_tim.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_tim.c - - MDK-ARM @@ -1287,7 +1250,7 @@ 0 - HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM USE_STDPERIPH_DRIVER MDK_CONF_FS + HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM MDK_CONF_FS ..\MDK-ARM\CyaSSL;..\MDK-ARM\inc;..\STM32F2xx_StdPeriph_Lib\inc;..\POSIX\..\..\..\ @@ -1539,43 +1502,6 @@ STM32F2xx_StdPeriph_Lib - - - stm32f2xx_cryp.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_cryp.c - - - stm32f2xx_hash.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_hash.c - - - stm32f2xx_rcc.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rcc.c - - - stm32f2xx_rng.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rng.c - - - stm32f2xx_rtc.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rtc.c - - - stm32f2xx_pwr.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_pwr.c - - - stm32f2xx_tim.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_tim.c - - MDK-ARM @@ -1723,46 +1649,6 @@ crl.c 1 ..\..\..\src\crl.c - - - internal.c - 1 - ..\..\..\src\internal.c - - - io.c - 1 - ..\..\..\src\io.c - - - keys.c - 1 - ..\..\..\src\keys.c - - - ocsp.c - 1 - ..\..\..\src\ocsp.c - - - sniffer.c - 1 - ..\..\..\src\sniffer.c - - - ssl.c - 1 - ..\..\..\src\ssl.c - - - tls.c - 1 - ..\..\..\src\tls.c - - - ssl-dummy.c - 1 - ..\MDK-ARM\CyaSSL\ssl-dummy.c 2 @@ -1804,6 +1690,326 @@ + + internal.c + 1 + ..\..\..\src\internal.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + io.c + 1 + ..\..\..\src\io.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + keys.c + 1 + ..\..\..\src\keys.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + ocsp.c + 1 + ..\..\..\src\ocsp.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + sniffer.c + 1 + ..\..\..\src\sniffer.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + ssl.c + 1 + ..\..\..\src\ssl.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + tls.c + 1 + ..\..\..\src\tls.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + + + + ssl-dummy.c + 1 + ..\MDK-ARM\CyaSSL\ssl-dummy.c + @@ -1914,6 +2120,11 @@ 1 ..\..\..\ctaocrypt\src\misc.c + + port.c + 1 + ..\..\..\ctaocrypt\src\port.c + pwdbased.c 1 @@ -1959,11 +2170,6 @@ 1 ..\..\..\ctaocrypt\src\tfm.c - - port.c - 1 - ..\..\..\ctaocrypt\src\port.c - @@ -2501,7 +2707,7 @@ 0 - HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM USE_STDPERIPH_DRIVER MDK_CONF_BARE_METAL + HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM MDK_CONF_BARE_METAL ..\MDK-ARM\CyaSSL;..\MDK-ARM\inc;..\STM32F2xx_StdPeriph_Lib\inc;..\POSIX;..\..\..\ @@ -2753,43 +2959,6 @@ STM32F2xx_StdPeriph_Lib - - - stm32f2xx_cryp.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_cryp.c - - - stm32f2xx_hash.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_hash.c - - - stm32f2xx_rcc.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rcc.c - - - stm32f2xx_rng.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rng.c - - - stm32f2xx_rtc.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_rtc.c - - - stm32f2xx_pwr.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_pwr.c - - - stm32f2xx_tim.c - 1 - ..\STM32F2xx_StdPeriph_Lib\src\stm32f2xx_tim.c - - MDK-ARM @@ -2995,6 +3164,46 @@ crl.c 1 ..\..\..\src\crl.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + internal.c @@ -3045,21 +3254,181 @@ io.c 1 ..\..\..\src\io.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + keys.c 1 ..\..\..\src\keys.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + ocsp.c 1 ..\..\..\src\ocsp.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + sniffer.c 1 ..\..\..\src\sniffer.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + + + + + + + + + ssl.c @@ -3266,6 +3635,11 @@ 1 ..\..\..\ctaocrypt\src\misc.c + + port.c + 1 + ..\..\..\ctaocrypt\src\port.c + pwdbased.c 1 @@ -3351,11 +3725,6 @@ - - port.c - 1 - ..\..\..\ctaocrypt\src\port.c - diff --git a/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c b/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c index 66940453a..37154d136 100644 --- a/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c +++ b/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c @@ -24,109 +24,229 @@ #endif #include "time.h" -#include "stm32f2xx_tim.h" -#include "stm32f2xx_rcc.h" - +#define PERIPH_BASE ((uint32_t)0x40000000) /*----------------------------------------------------------------------------- * initialize RTC *----------------------------------------------------------------------------*/ -#include "stm32f2xx_rtc.h" -#include "stm32f2xx_rcc.h" -#include "stm32f2xx_pwr.h" +#include "stm32f2xx.h" -static init_RTC() +#define assert_param(a) + +#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) +#define Bcd2ToByte(v) \ + ((((uint8_t)(v & (uint8_t)0xF0) >> (uint8_t)0x4) * 10) + (v & (uint8_t)0x0F)) +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_TR_MNT ((uint32_t)0x00007000) +#define RTC_TR_MNU ((uint32_t)0x00000F00) + +#define PWR_OFFSET (PWR_BASE - PERIPH_BASE) +#define CR_OFFSET (PWR_OFFSET + 0x00) +#define DBP_BitNumber 0x08 +#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define INITMODE_TIMEOUT ((uint32_t) 0x00010000) + +static void init_RTC() { - RTC_InitTypeDef RTC_InitStruct ; + __IO uint32_t initcounter = 0x00 ; + uint32_t initstatus = 0x00; /* Enable the PWR clock : RCC_APB1Periph_PWR */ + ((uint32_t *)RCC)[0x10] |= ((uint32_t)0x10000000) ; - RTC_TimeTypeDef RTC_Time ; - RTC_DateTypeDef RTC_Date ; - - - /* Enable the PWR clock */ - RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE); - /* Allow access to RTC */ - PWR_BackupAccessCmd(ENABLE); - -/***Configures the External Low Speed oscillator (LSE)****/ - - RCC_LSEConfig(RCC_LSE_ON); - + *(__IO uint32_t *) CR_DBP_BB = ENABLE ; + /* RCC_LSEConfig(RCC_LSE_ON) */ + *(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x00); + /* Reset LSEBYP bit */ + *(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x00); + *(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x01); /* Wait till LSE is ready */ - while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET) - { - } + while((RCC->BDCR << 0x2) == 0x0) { } + /* Select the RTC clock source: RCC_RTCCLKSource_LSE */ + ((RCC_TypeDef *)RCC)->BDCR |= (uint32_t)0x00000100; - /* Select the RTC Clock Source */ - RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE); - /* Enable the RTC Clock */ - RCC_RTCCLKCmd(ENABLE); + *(__IO uint32_t *) (PERIPH_BB_BASE + (((RCC_BASE - PERIPH_BASE)+ 0x70) * 32) + (0x0F* 4)) = (uint32_t)ENABLE; - /* Wait for RTC APB registers synchronisation */ - RTC_WaitForSynchro(); + *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; + RTC->ISR = (uint32_t) RTC_INIT_MASK; + do { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; - /* Calendar Configuration with LSI supposed at 32KHz */ - RTC_InitStruct.RTC_AsynchPrediv = 0x7F; - RTC_InitStruct.RTC_SynchPrediv = 0xFF; - RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24; - RTC_Init(&RTC_InitStruct); + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); /* Clear RTC CR FMT Bit */ + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)0x00000000) ; /* RTC_HourFormat_24 */ - RTC_GetTime(RTC_Format_BIN, &RTC_Time) ; - RTC_GetDate(RTC_Format_BIN, &RTC_Date) ; + /* Configure the RTC PRER */ + RTC->PRER = 0x7f ; + RTC->PRER |= (uint32_t)(0xff << 16); + + /* Exit Initialization mode */ + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; } /*----------------------------------------------------------------------------- * initialize TIM *----------------------------------------------------------------------------*/ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) + static void init_TIM() { - TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure ; + uint16_t tmpcr1 = 0; - RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) ; + ((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ; - TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); - TIM_TimeBaseStructure.TIM_Prescaler = 60; - TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; - TIM_TimeBaseStructure.TIM_Period = 0xffffffff; - TIM_TimeBaseStructure.TIM_ClockDivision = 0; - TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + tmpcr1 = TIM2->CR1 ; + tmpcr1 &= (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) )); + /* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */ + tmpcr1 |= (uint16_t)0x0000 ; /* CR1 |= TIM_CounterMode_Up */ + TIM2->CR1= tmpcr1 ; - TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); + TIM2->ARR = 0xffffffff ; /* ARR= TIM_Period */ + TIM2->PSC = 60 ; /* PSC = TIM_Prescaler */ + TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */ - TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure) ; - TIM_Cmd(TIM2, ENABLE) ; + *(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ; + /* TIM_Cmd(TIM2, ENABLE) ; */ } void init_time(void) { - init_RTC() ; + init_RTC() ; init_TIM() ; } +static void GetTime(uint8_t *h, uint8_t *m, uint8_t *s) +{ + uint32_t tmpreg = 0; + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + *h = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16)); + *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8)); + *s = (uint8_t)Bcd2ToByte((tmpreg & (RTC_TR_ST | RTC_TR_SU))); +} + +static uint32_t ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + while (Value >= 10) { + bcdhigh++; + Value -= 10; + } + return ((uint8_t)(bcdhigh << 4) | Value); +} + +static void SetTime(uint8_t h, uint8_t m, uint8_t s) +{ + __IO uint32_t synchrocounter = 0; + uint32_t synchrostatus = 0x00; + __IO uint32_t initcounter = 0; + uint32_t initstatus = 0x00; + uint32_t tmpreg ; + + tmpreg = ((ByteToBcd2(h) << 16) | (ByteToBcd2(m) << 8) | ByteToBcd2(s)) ; + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; + + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + /* Wait the registers to be synchronised */ + do { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + RTC->WPR = 0xFF; +} + +static void GetDate(uint8_t *y, uint8_t *m, uint8_t *d) +{ + uint32_t tmpreg = 0; + tmpreg = (uint32_t)(RTC->DR & RTC_TR_RESERVED_MASK); + *y = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_YT|RTC_DR_YU)) >>16)); + *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_MT|RTC_DR_MU)) >> 8)); + *d = (uint8_t)Bcd2ToByte((uint8_t)(tmpreg & (RTC_DR_DT |RTC_DR_DU))); +} + +static void SetDate(uint8_t y, uint8_t m, uint8_t d) +{ + __IO uint32_t synchrocounter = 0; + uint32_t synchrostatus = 0x00; + __IO uint32_t initcounter = 0; + uint32_t initstatus = 0x00; + uint32_t tmpreg = 0 ; + + tmpreg = ((ByteToBcd2(y) << 16) | (ByteToBcd2(m) << 8) | ByteToBcd2(d)) ; + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + RTC->ISR &= (uint32_t)~RTC_ISR_INIT; + + RTC->ISR = (uint32_t)RTC_INIT_MASK; + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + do { + initstatus = RTC->ISR & RTC_ISR_INITF; + initcounter++; + } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + RTC->DR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); + + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + /* Wait the registers to be synchronised */ + do { + synchrostatus = RTC->ISR & RTC_ISR_RSF; + synchrocounter++; + } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + RTC->WPR = 0xFF; +} + + +#include +void CYASSL_MSG(const char *msg) ; + struct tm *Cyassl_MDK_gmtime(const time_t *c) { - - RTC_TimeTypeDef RTC_Time ; - RTC_DateTypeDef RTC_Date ; + uint8_t h, m, s ; + uint8_t y, mo, d ; static struct tm date ; - RTC_GetTime(RTC_Format_BIN, &RTC_Time) ; - RTC_GetDate(RTC_Format_BIN, &RTC_Date) ; + GetTime(&h, &m, &s) ; + GetDate(&y, &mo, &d) ; - date.tm_year = RTC_Date.RTC_Year + 100 ; - date.tm_mon = RTC_Date.RTC_Month - 1 ; - date.tm_mday = RTC_Date.RTC_Date ; - date.tm_hour = RTC_Time.RTC_Hours ; - date.tm_min = RTC_Time.RTC_Minutes ; - date.tm_sec = RTC_Time.RTC_Seconds ; + date.tm_year = y + 100 ; + date.tm_mon = mo - 1 ; + date.tm_mday = d ; + date.tm_hour = h ; + date.tm_min = m ; + date.tm_sec = s ; #if defined(DEBUG_CYASSL) { char msg[100] ; - sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n", - RTC_Date.RTC_Year+2000, RTC_Date.RTC_Month, RTC_Date.RTC_Date, - RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ; + sprintf(msg, + "Debug::Cyassl_KEIL_gmtime(DATE=/%2d/%02d/%04d TIME=%02d:%02d:%02d)\n", + d, mo, y+2000, h, m, s) ; CYASSL_MSG(msg) ; } #endif @@ -138,48 +258,42 @@ double current_time() { return ((double)TIM2->CNT/1000000.0) ; } - -typedef struct func_args { - int argc; - char** argv; - int return_code; -} func_args; - - -#include - -void time_main(void *args) -{ - char * datetime ; - RTC_TimeTypeDef RTC_Time ; - RTC_DateTypeDef RTC_Date ; - int year ; - if( args == NULL || ((func_args *)args)->argc == 1) { - RTC_GetTime(RTC_Format_BIN, &RTC_Time) ; - RTC_GetDate(RTC_Format_BIN, &RTC_Date) ; - printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", - RTC_Date.RTC_Month, RTC_Date.RTC_Date, RTC_Date.RTC_Year+2000, - RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 'd' ) { - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d/%d/%d", - (int *)&RTC_Date.RTC_Month, (int *)&RTC_Date.RTC_Date, &year) ; - RTC_Date.RTC_Year = year - 2000 ; - RTC_Date.RTC_WeekDay = 0 ; - RTC_SetDate(RTC_Format_BIN, &RTC_Date) ; - } else if(((func_args *)args)->argc == 3 && - ((func_args *)args)->argv[1][0] == '-' && - ((func_args *)args)->argv[1][1] == 't' ) { - datetime = ((func_args *)args)->argv[2]; - sscanf(datetime, "%d:%d:%d", - (int *)&RTC_Time.RTC_Hours, - (int *)&RTC_Time.RTC_Minutes, - (int *)&RTC_Time.RTC_Seconds - ) ; - RTC_SetTime(RTC_Format_BIN, &RTC_Time) ; - } else printf("Invalid argument\n") ; -} + +typedef struct func_args { + int argc; + char** argv; + int return_code; +} func_args; + +void time_main(void *args) +{ + char * datetime ; + uint8_t h, m, s ; + uint8_t y, mo, d ; + + if( args == NULL || ((func_args *)args)->argc == 1) { + GetTime(&h, &m, &s) ; + GetDate(&y, &mo, &d) ; + printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", + mo, d, y+2000, h, m, s) ; + } else if(((func_args *)args)->argc == 3 && + ((func_args *)args)->argv[1][0] == '-' && + ((func_args *)args)->argv[1][1] == 'd' ) { + datetime = ((func_args *)args)->argv[2]; + sscanf(datetime, "%d/%d/%d", (int *)&mo, (int *)&d, (int *) &y) ; + SetDate(y-2000, mo, d) ; + } else if(((func_args *)args)->argc == 3 && + ((func_args *)args)->argv[1][0] == '-' && + ((func_args *)args)->argv[1][1] == 't' ) { + datetime = ((func_args *)args)->argv[2]; + sscanf(datetime, "%d:%d:%d", + (int *)&h, (int *)&m, (int *)&s) ; + SetTime(h, m, s) ; + } else printf("Invalid argument\n") ; +} +/******************************************************************* + time() +********************************************************************/ +time_t time(time_t * t) { return 0 ; } diff --git a/IDE/MDK5-ARM/Docs/CyaSSL-Licnese.txt b/IDE/MDK5-ARM/Docs/CyaSSL-Licnese.txt new file mode 100644 index 000000000..6262c57c2 --- /dev/null +++ b/IDE/MDK5-ARM/Docs/CyaSSL-Licnese.txt @@ -0,0 +1,107 @@ +LICENSE AGREEMENT + +The wolfSSL source code is subject to the U.S. Export Administration Regulations and other U.S. law, and may not be exported or re-exported to certain countries (currently Afghanistan, Cuba, Iran, Iraq, Libya, North Korea, Sudan and Syria) or to persons or entities prohibited from receiving U.S. exports (including Denied Parties, entities on the Bureau of Export Administration Entity List, and Specially Designated Nationals). + +--- + +GNU GENERAL PUBLIC LICENSE +Version 2, June 1991 + +============================================================ + +Copyright (C) 1989, 1991 Free Software Foundation, Inc. +59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. + +========================================================= + +Preamble + +The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.) You can apply it to +your programs, too. + +When we speak of free software, we are referring to freedom, not price. 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IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + +END OF TERMS AND CONDITIONS \ No newline at end of file diff --git a/IDE/MDK5-ARM/Docs/CyaSSLManual-TableofContents.htm b/IDE/MDK5-ARM/Docs/CyaSSLManual-TableofContents.htm new file mode 100644 index 000000000..2f90e2972 --- /dev/null +++ b/IDE/MDK5-ARM/Docs/CyaSSLManual-TableofContents.htm @@ -0,0 +1 @@ + \ No newline at end of file diff --git a/IDE/MDK5-ARM/Docs/CyaSSLManual-wolfCryptUsageReference.htm b/IDE/MDK5-ARM/Docs/CyaSSLManual-wolfCryptUsageReference.htm new file mode 100644 index 000000000..d860715fd --- /dev/null +++ b/IDE/MDK5-ARM/Docs/CyaSSLManual-wolfCryptUsageReference.htm @@ -0,0 +1 @@ + diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.c b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.c new file mode 100644 index 000000000..398d85c70 --- /dev/null +++ b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.c @@ -0,0 +1,28 @@ +/* certs_test.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +/* Define initial data for cert buffers */ +#include + diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.h b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.h new file mode 100644 index 000000000..6629ee051 --- /dev/null +++ b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cert_data.h @@ -0,0 +1,39 @@ +#ifndef CYASSL_CERT_DATA_H +#define CYASSL_CERT_DATA_H + +#ifdef USE_CERT_BUFFERS_1024 +extern const unsigned char client_key_der_1024[] ; +extern int sizeof_client_key_der_1024 ; +/* ./certs/1024/client-cert.der, 1024-bit */ +extern const unsigned char client_cert_der_1024[] ; +extern int sizeof_client_cert_der_1024 ; +/* ./certs/1024/dh1024.der, 1024-bit */ +extern const unsigned char dh_key_der_1024[] ; +extern int sizeof_dh_key_der_1024 ; +/* ./certs/1024/dsa1024.der, 1024-bit */ +extern const unsigned char dsa_key_der_1024[] ; +extern int sizeof_dsa_key_der_1024 ; +/* ./certs/1024/rsa1024.der, 1024-bit */ +extern const unsigned char rsa_key_der_1024[] ; +extern int sizeof_rsa_key_der_1024 ; + +#elif defined(USE_CERT_BUFFERS_2048) +/* ./certs/client-key.der, 2048-bit */ +extern const unsigned char client_key_der_2048[] ; +extern int sizeof_client_key_der_2048 ; +/* ./certs/client-cert.der, 2048-bit */ +extern const unsigned char client_cert_der_2048[] ; +extern int sizeof_client_cert_der_2048 ; +/* ./certs/dh2048.der, 2048-bit */ +extern const unsigned char dh_key_der_2048[] ; +extern int sizeof_dh_key_der_2048 ; +/* ./certs/dsa2048.der, 2048-bit */ +extern const unsigned char dsa_key_der_2048[] ; +extern int sizeof_dsa_key_der_2048; +/* ./certs/rsa2048.der, 2048-bit */ +extern const unsigned char rsa_key_der_2048[] ; +extern int sizeof_rsa_key_der_2048 ; +#endif + +#endif + diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c new file mode 100644 index 000000000..53747afae --- /dev/null +++ b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c @@ -0,0 +1,247 @@ +/* cyassl_KEIL_RL.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + + +/***************************************************************************************/ +/** This file is for defining functions for specific to KEIL-RL. **/ +/***************************************************************************************/ +#ifdef HAVE_CONFIG_H + #include +#endif + +#include +#if defined (CYASSL_MDK5) + #include "cmsis_os.h" + #if defined(CYASSL_KEIL_TCP_NET) + #include "rl_net.h" + #endif +#else + #include +#endif + +#include "cyassl_MDK_ARM.h" + +#include +#include + +#if defined (CYASSL_CMSIS_RTOS) + #define os_dly_wait(t) osDelay(10*t) +#endif + + +/** KEIL-RL TCPnet ****/ +/** TCPnet BSD socket does not have following functions. **/ + +#if defined(CYASSL_KEIL_TCP_NET) +char *inet_ntoa(struct in_addr in) +{ + #define NAMESIZE 16 + static char name[NAMESIZE] ; + sprintf(name, "%d.%d.%d.%d", (in.s_addr>>24)&0xff, (in.s_addr>>16)&0xff, (in.s_addr>>8)&0xff, in.s_addr&0xff) ; + return name ; +} + +unsigned long inet_addr(const char *cp) +{ + unsigned int a[4] ; unsigned long ret ; + sscanf(cp, "%d.%d.%d.%d", &a[0], &a[1], &a[2], &a[3]) ; + ret = ((a[3]<<24) + (a[2]<<16) + (a[1]<<8) + a[0]) ; + return(ret) ; +} + + +/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/ +int Cyassl_connect(int sd, const struct sockaddr* sa, int sz) +{ + int ret = 0 ; + #if defined(CYASSL_KEIL_TCP_NET) + + SOCKADDR_IN addr ; + + addr = *(SOCKADDR_IN *)sa ; + + do { + #undef connect /* Go to KEIL TCPnet connect */ + ret = connect(sd, (SOCKADDR *)&addr, sizeof(addr)) ; + os_dly_wait(50); + } while(ret == SCK_EWOULDBLOCK) ; + #ifdef DEBUG_CYASSL + { + char msg[50] ; + sprintf(msg, "BSD Connect return code: %d\n", ret) ; + CYASSL_MSG(msg) ; + } + #endif + + #endif /* CYASSL_KEIL_TCP_NET */ + return(ret ) ; +} + + +int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen) +{ + int ret = 0 ; + + #if defined(CYASSL_KEIL_TCP_NET) + while(1) { + #undef accept /* Go to KEIL TCPnet accept */ + ret = accept(sd, addr, addrlen) ; + if(ret != SCK_EWOULDBLOCK) break ; + os_dly_wait(1); + } + #ifdef DEBUG_CYASSL + { + char msg[50] ; + sprintf(msg, "BSD Accept return code: %d\n", ret) ; + CYASSL_MSG(msg) ; + } + #endif + + #endif /* CYASSL_KEIL_TCP_NET */ + return(ret ) ; + +} + +int Cyassl_recv(int sd, void *buf, size_t len, int flags) +{ + int ret = 0; + #if defined(CYASSL_KEIL_TCP_NET) + while(1) { + #undef recv /* Go to KEIL TCPnet recv */ + ret = recv(sd, buf, len, flags) ; + if((ret != SCK_EWOULDBLOCK) &&( ret != SCK_ETIMEOUT)) break ; + os_dly_wait(1); + } + #ifdef DEBUG_CYASSL + { + char msg[50] ; + sprintf(msg, "BSD Recv return code: %d\n", ret) ; + CYASSL_MSG(msg) ; + } + #endif + + #endif /* CYASSL_KEIL_TCP_NET */ + return(ret ) ; +} + +int Cyassl_send(int sd, const void *buf, size_t len, int flags) +{ + int ret = 0 ; + + #if defined(CYASSL_KEIL_TCP_NET) + while(1) { + #undef send /* Go to KEIL TCPnet send */ + ret = send(sd, buf, len, flags) ; + if(ret != SCK_EWOULDBLOCK) break ; + os_dly_wait(1); + } + #ifdef DEBUG_CYASSL + { + char msg[50] ; + sprintf(msg, "BSD Send return code: %d\n", ret) ; + CYASSL_MSG(msg) ; + } + #endif + +#endif /* CYASSL_KEIL_TCP_NET */ + return(ret) ; + +} + +#endif /* CYASSL_KEIL_TCP_NET */ + +#if defined(CYASSL_KEIL_TCP_NET) +void Cyassl_sleep(int t) +{ + #if defined(HAVE_KEIL_RTX) + os_dly_wait(t/1000+1) ; + #endif +} + +int Cyassl_tcp_select(int sd, int timeout) +{ + + return 0 ; + +} +#endif + +extern int strlen(const char *s) ; + +FILE * CyaSSL_fopen(const char *name, const char *openmode) +{ + int i ; FILE * ret ; + #define PATHSIZE 100 + char path[PATHSIZE] ; char *p ; + + if(strlen(name) > PATHSIZE)return(NULL) ; + + for(i = 0; i<= strlen(name); i++) { + if(name[i] == '/')path[i] = '\\' ; + else path[i] = name[i] ; + } + if(path[0] == '.' && path[1] == '\\') p = path + 2 ; + else p = path ; + + ret = fopen (p, openmode) ; + + return(ret) ; +} + +#if defined (CYASSL_MDK5) +#define getkey getchar +#define sendchar putchar +#else +extern int getkey(void) ; +extern int sendchar(int c) ; +#endif + +char * Cyassl_fgets ( char * str, int num, FILE * f ) +{ + int i ; + + for(i = 0 ; i< num ; i++) { + while((str[i] = getkey()) == 0) { + #if defined (HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS) + os_tsk_pass (); + #else + osThreadYield (); + #endif + } + if(str[i] == '\n' || str[i] == '\012' || str[i] == '\015') { + sendchar('\n') ; + str[i++] = '\n' ; + str[i] = '\0' ; + break ; + } else if(str[i] == '\010') { /* BS */ + if(i) { /* erace one char */ + sendchar('\010') ; sendchar(' ') ; sendchar('\010') ; + i = (i>0 ? (i-2) : -1 ) ; + continue ; + } + } else if(str[i] == '\033' || str[i] == '\004' ) { /* ESC or ^D */ + str[i] = '\0' ; + return(0) ; + } + sendchar(str[i]) ; + } + return(str) ; +} diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h new file mode 100644 index 000000000..51f3c901d --- /dev/null +++ b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h @@ -0,0 +1,106 @@ +/* cyassl_KEIL_RL.h + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/******************************************************************************/ +/** This file is for defining types, values for specific to KEIL-MDK-ARM. **/ +/******************************************************************************/ +#ifndef CYASSL_KEIL_RL_H +#define CYASSL_KEIL_RL_H + + + +#include + +/* Go to STDIN */ +#define fgets(buff, sz, fd) Cyassl_fgets(buff, sz, fd) +extern char * Cyassl_fgets ( char * str, int num, FILE * f ) ; + +#define SOCKET_T int + +/*** #include ***/ +#define NUMBITSPERBYTE 8 +#define FD_SETSIZE 10 + +typedef long fd_mask; +#define NFDBITS (sizeof(fd_mask) * NUMBITSPERBYTE) /* bits per mask */ + +typedef struct fd_set { + fd_mask fds_bits[(FD_SETSIZE + NFDBITS - 1) / NFDBITS]; +} fd_set; + +/*** #include ***/ +struct timeval { + long tv_sec; /* seconds */ + long tv_usec; /* microseconds */ +}; + + +#if defined(CYASSL_KEIL_TCP_NET) + + +#if defined(CYASSL_MDK5) +#define SCK_EWOULDBLOCK BSD_ERROR_WOULDBLOCK +#define SCK_ETIMEOUT BSD_ERROR_TIMEOUT +#include "rl_net.h" +#endif + +typedef int socklen_t ; + +/* for avoiding conflict with KEIL-TCPnet BSD socket */ +/* Bodies are in cyassl_KEIL_RL.c */ +#define connect Cyassl_connect +#define accept Cyassl_accept +#define recv Cyassl_recv +#define send Cyassl_send +#define sleep Cyassl_sleep + +/* for avoiding conflicting with KEIL-TCPnet TCP socket */ +/* Bodies are in test.h */ +#define tcp_connect Cyassl_tcp_connect +#define tcp_socket Cyassl_tcp_soket +#define tcp_listen Cyassl_tcp_listen +#define tcp_select Cyassl_tcp_select + +extern int Cyassl_connect(int sd, const struct sockaddr * sa, int sz) ; +extern int Cyassl_accept(int sd, struct sockaddr *addr, socklen_t *addrlen); +extern int Cyassl_recv(int sd, void *buf, size_t len, int flags); +extern int Cyassl_send(int sd, const void *buf, size_t len, int flags); +extern void Cyassl_sleep(int sec) ; +extern int Cyassl_tcp_select(int sd, int timeout) ; + +/** KEIL-RL TCPnet ****/ +/* TCPnet BSD socket does not have following functions. */ +extern char *inet_ntoa(struct in_addr in); +extern unsigned long inet_addr(const char *cp); +extern int setsockopt(int sockfd, int level, int optname, + const void *optval, socklen_t optlen); +extern int select(int nfds, fd_set *readfds, fd_set *writefds, + fd_set *exceptfds, const struct timeval *timeout); + +#endif /* CYASSL_KEIL_TCP_NET */ + + +/* CyaSSL MDK-ARM time functions */ +#include +struct tm *Cyassl_MDK_gmtime(const time_t *c) ; +extern double current_time(void) ; + +#endif /* CYASSL_KEIL_RL_H */ diff --git a/IDE/MDK5-ARM/MDK-ARM/CyaSSL/ssl-dummy.c b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/ssl-dummy.c new file mode 100644 index 000000000..88110ce98 --- /dev/null +++ b/IDE/MDK5-ARM/MDK-ARM/CyaSSL/ssl-dummy.c @@ -0,0 +1,52 @@ +/* ssl-dummy.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include +#include + +Signer* GetCA(void* vp, byte* hash) +{ + return NULL ; +} + +int CyaSSL_dtls(CYASSL* ssl) +{ + return NULL ; +} + +int CyaSSL_get_using_nonblock(CYASSL* ssl) +{ + return NULL ; +} + +Signer* GetCAByName(void* vp, byte* hash) +{ + return NULL ; +} + +int CyaSSL_PemCertToDer(const char* fileName, unsigned char* derBuf, int derSz) +{ + return NULL ; +} diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt b/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt new file mode 100644 index 000000000..e19c56403 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/Abstract.txt @@ -0,0 +1,15 @@ +This program is a simple benchmark of wolfCrypt library. + +In order to run this benchmark, copy +{PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. + +For benchmark configuration, refer config-Crypt.h. + +For the hardware crypt on config-Crypt.h, download +STSW-STM32062: STM32F2xx standard peripherals library at +http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to + {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib + +Support +------- +Please send questions or comments to support@wolfssl.com diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx new file mode 100644 index 000000000..888271586 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvoptx @@ -0,0 +1,1094 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + CryptBenchmark + 0x4 + ARM-ADS + + 120000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Object\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -REMAP -MPU + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 8 + + + + + + + + + + .\STM32_SWO.ini + BIN\ULP2CM3.DLL + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ULP2CM3 + -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + + + + + + 1 + 8 + 0x20000408 + + + + + 2 + 8 + 0x8004dc8 + + + + 0 + + + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 32 + 0 + 0 + 0 + 0 + .\benchmark.c + benchmark.c + 0 + 0 + + + + + Configuration + 1 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\RTE\wolfSSL\config-Crypt.h + config-Crypt.h + 0 + 0 + + + + + Documentation + 1 + 0 + 0 + 0 + + 3 + 4 + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\Abstract.txt + Abstract.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + 4 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + 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C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c + misc.c + 1 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c + port.c + 1 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + + diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx new file mode 100644 index 000000000..180a81f8d --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/CryptBenchmark.uvprojx @@ -0,0 +1,917 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + CryptBenchmark + 0x4 + ARM-ADS + + + STM32F207IG + STMicroelectronics + IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + 0 + $$Device:STM32F207IG$Device\Include\stm32f2xx.h + + + + + + + + + + $$Device:STM32F207IG$SVD\STM32F20x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Object\ + CryptBenchmark + 1 + 0 + 0 + 1 + 1 + .\Object\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -REMAP -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 8 + + + + + + + + + + + + + .\STM32_SWO.ini + BIN\ULP2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\ULP2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + HAVE_CONFIG_H MDK_CONF_Benchmark CYASSL_STM32F2xx + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + benchmark.c + 1 + .\benchmark.c + + + + + Configuration + + + config-Crypt.h + 5 + .\RTE\wolfSSL\config-Crypt.h + + + + + Documentation + + + Abstract.txt + 5 + .\Abstract.txt + + + + + ::CMSIS + + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + + + RTX_Conf_CM.c + 1 + RTE\CMSIS\RTX_Conf_CM.c + + + + + ::Device + + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c + + + RTE_Device.h + 5 + RTE\Device\STM32F207IG\RTE_Device.h + + + startup_stm32f2xx.s + 2 + RTE\Device\STM32F207IG\startup_stm32f2xx.s + + + system_stm32f2xx.c + 1 + RTE\Device\STM32F207IG\system_stm32f2xx.c + + + + + ::Drivers + + + MCI_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + + + + + ::File System + + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + + + FS_Config.c + 1 + RTE\File_System\FS_Config.c + + + FS_Config_MC_0.h + 5 + RTE\File_System\FS_Config_MC_0.h + + + + + ::wolfSSL + + + config-Crypt.h + 5 + RTE\wolfSSL\config-Crypt.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + + + ssl-dummy.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c + + + time-STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c + + + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Conf_CM.c + + + + + + + + RTE\Device\STM32F207IG\RTE_Device.h + + + + + + + + RTE\Device\STM32F207IG\startup_stm32f2xx.s + + + + + + + + RTE\Device\STM32F207IG\system_stm32f2xx.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + RTE\File_System\FS_Config_MC_0.h + + + + + + + + RTE\Network\Net_Config.c + + + + + + RTE\Network\Net_Config_BSD.h + + + + + + RTE\Network\Net_Config_DNS_Client.h + + + + + + RTE\Network\Net_Config_ETH_0.h + + + + + + RTE\Network\Net_Config_TCP.h + + + + + + RTE\Network\Net_Config_UDP.h + + + + + + RTE\Network\Net_Debug.c + + + + + + RTE\Other\config-Crypt.h + + + + + + RTE\Other\config-FS.h + + + + + + RTE\Other\config-RTX-TCP-FS.h + + + + + + RTE\Other\config.h + + + + + + RTE\wolfSSL\config-Crypt.h + + + + + + + + RTE\wolfSSL\config.h + + + + + + + + diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c new file mode 100644 index 000000000..af8fdc4d5 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/CMSIS/RTX_Conf_CM.c @@ -0,0 +1,276 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running threads <0-250> +// Defines max. number of threads that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 6 +#endif + +// Default Thread stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for threads with osThreadDef stacksz = 0 +// Default: 200 +#ifndef OS_STKSIZE + #define OS_STKSIZE 50 +#endif + +// Main Thread stack size [bytes] <64-10000:8><#/4> +// Defines stack size for main thread. +// Default: 200 +#ifndef OS_MAINSTKSIZE + #define OS_MAINSTKSIZE 1500 +#endif + +// Number of threads with user-provided stack size <0-250> +// Defines the number of threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> +// Defines the combined stack size for threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVSTKSIZE + #define OS_PRIVSTKSIZE 0 +#endif + +// Check for stack overflow +// Includes the stack checking code for stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 1 +#endif + +// + +// RTX Kernel Timer Tick Configuration +// ====================================== +// Use Cortex-M SysTick timer as RTX Kernel Timer +// Use the Cortex-M SysTick timer as a time-base for RTX. +#ifndef OS_SYSTICK + #define OS_SYSTICK 1 +#endif +// +// Timer clock value [Hz] <1-1000000000> +// Defines the timer clock value. +// Default: 12000000 (12MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 12000000 +#endif + +// Timer tick value [us] <1-1000000> +// Defines the timer tick value. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal <3=> Normal <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ 50 +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQS + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +void os_idle_demon (void) { + /* The idle demon is a system thread, running when no other thread is */ + /* ready to run. */ + + for (;;) { + /* HERE: include optional user code to be executed when no thread runs.*/ + } +} + +#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer + +/*--------------------------- os_tick_init ----------------------------------*/ + +// Initialize alternative hardware timer as RTX kernel timer +// Return: IRQ number of the alternative hardware timer +int os_tick_init (void) { + return (-1); /* Return IRQ number of timer (0..239) */ +} + +/*--------------------------- os_tick_val -----------------------------------*/ + +// Get alternative hardware timer current value (0 .. OS_TRV) +uint32_t os_tick_val (void) { + return (0); +} + +/*--------------------------- os_tick_ovf -----------------------------------*/ + +// Get alternative hardware timer overflow flag +// Return: 1 - overflow, 0 - no overflow +uint32_t os_tick_ovf (void) { + return (0); +} + +/*--------------------------- os_tick_irqack --------------------------------*/ + +// Acknowledge alternative hardware timer interrupt +void os_tick_irqack (void) { + /* ... */ +} + +#endif // (OS_SYSTICK == 0) + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (uint32_t err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/RTE_Device.h new file mode 100644 index 000000000..2648e44d4 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/RTE_Device.h @@ -0,0 +1,3127 @@ +/* ----------------------------------------------------------------------------- + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * $Date: 27. June 2013 + * $Revision: V1.01 + * + * Project: RTE Device Configuration for ST STM32F2xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + (num == 7) ? GPIOH : \ + (num == 8) ? GPIOI : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 16000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 120000000 +// AHB Clock <1-999999999> +#define RTE_HCLK 120000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 30000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 60000000 +// 48MHz Clock +#define RTE_PLL48CK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::Drivers:UART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>PA9 <1=>PB6 +#define RTE_USART1_TX_ID 0 +#if (RTE_USART1_TX_ID == 0) +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 9 +#elif (RTE_USART1_TX_ID == 1) +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>PA10 <1=>PB7 +#define RTE_USART1_RX_ID 0 +#if (RTE_USART1_RX_ID == 0) +#define RTE_USART1_RX_PORT GPIOA +#define RTE_USART1_RX_BIT 10 +#elif (RTE_USART1_RX_ID == 1) +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// Synchronous +// USART1_CK Pin <0=>PA8 +// +#define RTE_USART1_CK 0 +#define RTE_USART1_CK_ID 0 +#if (RTE_USART1_CK_ID == 0) +#define RTE_USART1_CK_PORT GPIOA +#define RTE_USART1_CK_BIT 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART1_CTS Pin <0=>PA11 +// USART1_RTS Pin <0=>PA12 +// Manual CTS/RTS +// +#define RTE_USART1_HW_FLOW 0 +#define RTE_USART1_CTS_ID 0 +#define RTE_USART1_RTS_ID 0 +#define RTE_USART1_MANUAL_FLOW 0 +#if (RTE_USART1_CTS_ID == 0) +#define RTE_USART1_CTS_PORT GPIOA +#define RTE_USART1_CTS_BIT 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif +#if (RTE_USART1_RTS_ID == 0) +#define RTE_USART1_RTS_PORT GPIOA +#define RTE_USART1_RTS_BIT 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <5=>5 +// Selects DMA Stream (only Stream 2 or 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_RX_DMA 1 +#define RTE_USART1_RX_DMA_NUMBER 2 +#define RTE_USART1_RX_DMA_STREAM 2 +#define RTE_USART1_RX_DMA_CHANNEL 4 +#define RTE_USART1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_TX_DMA 1 +#define RTE_USART1_TX_DMA_NUMBER 2 +#define RTE_USART1_TX_DMA_STREAM 7 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 + +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] +// Configuration settings for Driver_UART2 in component ::Drivers:UART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>PA2 <1=>PD5 +#define RTE_USART2_TX_ID 0 +#if (RTE_USART2_TX_ID == 0) +#define RTE_USART2_TX_PORT GPIOA +#define RTE_USART2_TX_BIT 2 +#elif (RTE_USART2_TX_ID == 1) +#define RTE_USART2_TX_PORT GPIOD +#define RTE_USART2_TX_BIT 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>PA3 <1=>PD6 +#define RTE_USART2_RX_ID 0 +#if (RTE_USART2_RX_ID == 0) +#define RTE_USART2_RX_PORT GPIOA +#define RTE_USART2_RX_BIT 3 +#elif (RTE_USART2_RX_ID == 1) +#define RTE_USART2_RX_PORT GPIOD +#define RTE_USART2_RX_BIT 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// Synchronous +// USART2_CK Pin <0=>PA4 <1=>PD7 +// +#define RTE_USART2_CK 0 +#define RTE_USART2_CK_ID 0 +#if (RTE_USART2_CK_ID == 0) +#define RTE_USART2_CK_PORT GPIOA +#define RTE_USART2_CK_BIT 4 +#elif (RTE_USART2_CK_ID == 1) +#define RTE_USART2_CK_PORT GPIOD +#define RTE_USART2_CK_BIT 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART2_CTS Pin <0=>PA0 <1=>PD3 +// USART2_RTS Pin <0=>PA1 <1=>PD4 +// Manual CTS/RTS +// +#define RTE_USART2_HW_FLOW 0 +#define RTE_USART2_CTS_ID 0 +#define RTE_USART2_RTS_ID 0 +#define RTE_USART2_MANUAL_FLOW 0 +#if (RTE_USART2_CTS_ID == 0) +#define RTE_USART2_CTS_PORT GPIOA +#define RTE_USART2_CTS_BIT 0 +#elif (RTE_USART2_CTS_ID == 1) +#define RTE_USART2_CTS_PORT GPIOD +#define RTE_USART2_CTS_BIT 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif +#if (RTE_USART2_RTS_ID == 0) +#define RTE_USART2_RTS_PORT GPIOA +#define RTE_USART2_RTS_BIT 1 +#elif (RTE_USART2_RTS_ID == 1) +#define RTE_USART2_RTS_PORT GPIOD +#define RTE_USART2_RTS_BIT 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_RX_DMA 1 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_STREAM 5 +#define RTE_USART2_RX_DMA_CHANNEL 4 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_TX_DMA 1 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_STREAM 6 +#define RTE_USART2_TX_DMA_CHANNEL 4 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] +// Configuration settings for Driver_UART3 in component ::Drivers:UART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) +#define RTE_USART3_TX_PORT GPIOB +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 1) +#define RTE_USART3_TX_PORT GPIOC +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 2) +#define RTE_USART3_TX_PORT GPIOD +#define RTE_USART3_TX_BIT 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) +#define RTE_USART3_RX_PORT GPIOB +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 1) +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 2) +#define RTE_USART3_RX_PORT GPIOD +#define RTE_USART3_RX_BIT 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// Synchronous +// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 +// +#define RTE_USART3_CK 0 +#define RTE_USART3_CK_ID 0 +#if (RTE_USART3_CK_ID == 0) +#define RTE_USART3_CK_PORT GPIOB +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 1) +#define RTE_USART3_CK_PORT GPIOC +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 2) +#define RTE_USART3_CK_PORT GPIOD +#define RTE_USART3_CK_BIT 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART3_CTS Pin <0=>PB13 <1=>PD11 +// USART3_RTS Pin <0=>PB14 <1=>PD12 +// Manual CTS/RTS +// +#define RTE_USART3_HW_FLOW 0 +#define RTE_USART3_CTS_ID 0 +#define RTE_USART3_RTS_ID 0 +#define RTE_USART3_MANUAL_FLOW 0 +#if (RTE_USART3_CTS_ID == 0) +#define RTE_USART3_CTS_PORT GPIOB +#define RTE_USART3_CTS_BIT 13 +#elif (RTE_USART3_CTS_ID == 1) +#define RTE_USART3_CTS_PORT GPIOD +#define RTE_USART3_CTS_BIT 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif +#if (RTE_USART3_RTS_ID == 0) +#define RTE_USART3_RTS_PORT GPIOB +#define RTE_USART3_RTS_BIT 14 +#elif (RTE_USART3_RTS_ID == 1) +#define RTE_USART3_RTS_PORT GPIOD +#define RTE_USART3_RTS_BIT 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_RX_DMA 1 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_STREAM 1 +#define RTE_USART3_RX_DMA_CHANNEL 4 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_TX_DMA 1 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_STREAM 3 +#define RTE_USART3_TX_DMA_CHANNEL 4 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] +// Configuration settings for Driver_UART4 in component ::Drivers:UART +#define RTE_UART4 0 + +// UART4_TX Pin <0=>PA0 <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>PA1 <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 1 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_RX_DMA 1 +#define RTE_UART4_RX_DMA_NUMBER 1 +#define RTE_UART4_RX_DMA_STREAM 2 +#define RTE_UART4_RX_DMA_CHANNEL 4 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_TX_DMA 1 +#define RTE_UART4_TX_DMA_NUMBER 1 +#define RTE_UART4_TX_DMA_STREAM 4 +#define RTE_UART4_TX_DMA_CHANNEL 4 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] +// Configuration settings for Driver_UART5 in component ::Drivers:UART +#define RTE_UART5 0 + +// UART5_TX Pin <0=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_RX_DMA 1 +#define RTE_UART5_RX_DMA_NUMBER 1 +#define RTE_UART5_RX_DMA_STREAM 0 +#define RTE_UART5_RX_DMA_CHANNEL 4 +#define RTE_UART5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_TX_DMA 1 +#define RTE_UART5_TX_DMA_NUMBER 1 +#define RTE_UART5_TX_DMA_STREAM 7 +#define RTE_UART5_TX_DMA_CHANNEL 4 +#define RTE_UART5_TX_DMA_PRIORITY 0 + +// + + +// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] +// Configuration settings for Driver_UART6 in component ::Drivers:UART +#define RTE_USART6 0 + +// USART6_TX Pin <0=>PC6 <1=>PG14 +#define RTE_USART6_TX_ID 0 +#if (RTE_USART6_TX_ID == 0) +#define RTE_USART6_TX_PORT GPIOC +#define RTE_USART6_TX_BIT 6 +#elif (RTE_USART6_TX_ID == 1) +#define RTE_USART6_TX_PORT GPIOG +#define RTE_USART6_TX_BIT 14 +#else +#error "Invalid USART6_TX Pin Configuration!" +#endif + +// USART6_RX Pin <0=>PC7 <1=>PG9 +#define RTE_USART6_RX_ID 0 +#if (RTE_USART6_RX_ID == 0) +#define RTE_USART6_RX_PORT GPIOC +#define RTE_USART6_RX_BIT 7 +#elif (RTE_USART6_RX_ID == 1) +#define RTE_USART6_RX_PORT GPIOG +#define RTE_USART6_RX_BIT 9 +#else +#error "Invalid USART6_RX Pin Configuration!" +#endif + +// Synchronous +// USART6_CK Pin <0=>PC8 <1=>PG7 +// +#define RTE_USART6_CK 0 +#define RTE_USART6_CK_ID 0 +#if (RTE_USART6_CK_ID == 0) +#define RTE_USART6_CK_PORT GPIOC +#define RTE_USART6_CK_BIT 8 +#elif (RTE_USART6_CK_ID == 1) +#define RTE_USART6_CK_PORT GPIOG +#define RTE_USART6_CK_BIT 7 +#else +#error "Invalid USART6_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART6_CTS Pin <0=>PG13 <1=>PG15 +// USART6_RTS Pin <0=>PG8 <1=>PG12 +// Manual CTS/RTS +// +#define RTE_USART6_HW_FLOW 0 +#define RTE_USART6_CTS_ID 0 +#define RTE_USART6_RTS_ID 0 +#define RTE_USART6_MANUAL_FLOW 0 +#if (RTE_USART6_CTS_ID == 0) +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 13 +#elif (RTE_USART6_CTS_ID == 1) +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 15 +#else +#error "Invalid USART6_CTS Pin Configuration!" +#endif +#if (RTE_USART6_RTS_ID == 0) +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 8 +#elif (RTE_USART6_RTS_ID == 1) +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 12 +#else +#error "Invalid USART6_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_RX_DMA 1 +#define RTE_USART6_RX_DMA_NUMBER 2 +#define RTE_USART6_RX_DMA_STREAM 1 +#define RTE_USART6_RX_DMA_CHANNEL 5 +#define RTE_USART6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_TX_DMA 1 +#define RTE_USART6_TX_DMA_NUMBER 2 +#define RTE_USART6_TX_DMA_STREAM 6 +#define RTE_USART6_TX_DMA_CHANNEL 5 +#define RTE_USART6_TX_DMA_PRIORITY 0 + +// + + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 <1=>PB8 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 <1=>PB9 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 9 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 1 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_STREAM 0 +#define RTE_I2C1_RX_DMA_CHANNEL 1 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 1 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_STREAM 6 +#define RTE_I2C1_TX_DMA_CHANNEL 1 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 0 + +// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOF +#define RTE_I2C2_SCL_BIT 1 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT GPIOH +#define RTE_I2C2_SCL_BIT 4 +#elif (RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOF +#define RTE_I2C2_SDA_BIT 0 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT GPIOH +#define RTE_I2C2_SDA_BIT 5 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 <3=>3 +// Selects DMA Stream (only Stream 2 or 3 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_STREAM 2 +#define RTE_I2C2_RX_DMA_CHANNEL 7 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_STREAM 7 +#define RTE_I2C2_TX_DMA_CHANNEL 7 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C +#define RTE_I2C3 0 + +// I2C3_SCL Pin <0=>PH7 <1=>PA8 +#define RTE_I2C3_SCL_PORT_ID 0 +#if (RTE_I2C3_SCL_PORT_ID == 0) +#define RTE_I2C3_SCL_PORT GPIOH +#define RTE_I2C3_SCL_BIT 7 +#elif (RTE_I2C3_SCL_PORT_ID == 1) +#define RTE_I2C3_SCL_PORT GPIOA +#define RTE_I2C3_SCL_BIT 8 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// I2C3_SDA Pin <0=>PH8 <1=>PC9 +#define RTE_I2C3_SDA_PORT_ID 0 +#if (RTE_I2C3_SDA_PORT_ID == 0) +#define RTE_I2C3_SDA_PORT GPIOH +#define RTE_I2C3_SDA_BIT 8 +#elif (RTE_I2C3_SDA_PORT_ID == 1) +#define RTE_I2C3_SDA_PORT GPIOC +#define RTE_I2C3_SDA_BIT 9 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_RX_DMA 1 +#define RTE_I2C3_RX_DMA_NUMBER 1 +#define RTE_I2C3_RX_DMA_STREAM 2 +#define RTE_I2C3_RX_DMA_CHANNEL 3 +#define RTE_I2C3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_TX_DMA 1 +#define RTE_I2C3_TX_DMA_NUMBER 1 +#define RTE_I2C3_TX_DMA_STREAM 4 +#define RTE_I2C3_TX_DMA_CHANNEL 3 +#define RTE_I2C3_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 <1=>PB3 +#define RTE_SPI1_SCL_PORT_ID 0 +#if (RTE_SPI1_SCL_PORT_ID == 0) +#define RTE_SPI1_SCL_PORT GPIOA +#define RTE_SPI1_SCL_BIT 5 +#elif (RTE_SPI1_SCL_PORT_ID == 1) +#define RTE_SPI1_SCL_PORT GPIOB +#define RTE_SPI1_SCL_BIT 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>PA6 <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID 0 +#if (RTE_SPI1_MISO_PORT_ID == 0) +#define RTE_SPI1_MISO_PORT GPIOA +#define RTE_SPI1_MISO_BIT 6 +#elif (RTE_SPI1_MISO_PORT_ID == 1) +#define RTE_SPI1_MISO_PORT GPIOB +#define RTE_SPI1_MISO_BIT 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>PA7 <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID 0 +#if (RTE_SPI1_MOSI_PORT_ID == 0) +#define RTE_SPI1_MOSI_PORT GPIOA +#define RTE_SPI1_MOSI_BIT 7 +#elif (RTE_SPI1_MOSI_PORT_ID == 1) +#define RTE_SPI1_MOSI_PORT GPIOB +#define RTE_SPI1_MOSI_BIT 5 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 1 +#define RTE_SPI1_RX_DMA_NUMBER 2 +#define RTE_SPI1_RX_DMA_STREAM 0 +#define RTE_SPI1_RX_DMA_CHANNEL 3 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 1 +#define RTE_SPI1_TX_DMA_NUMBER 2 +#define RTE_SPI1_TX_DMA_STREAM 5 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 +#define RTE_SPI2_SCL_PORT_ID 0 +#if (RTE_SPI2_SCL_PORT_ID == 0) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 10 +#elif (RTE_SPI2_SCL_PORT_ID == 1) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 13 +#elif (RTE_SPI2_SCL_PORT_ID == 2) +#define RTE_SPI2_SCL_PORT GPIOI +#define RTE_SPI2_SCL_BIT 1 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO_PORT GPIOC +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 2) +#define RTE_SPI2_MISO_PORT GPIOI +#define RTE_SPI2_MISO_BIT 2 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 2) +#define RTE_SPI2_MOSI_PORT GPIOI +#define RTE_SPI2_MOSI_BIT 3 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 1 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_STREAM 2 +#define RTE_SPI2_RX_DMA_CHANNEL 0 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 1 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_STREAM 3 +#define RTE_SPI2_TX_DMA_CHANNEL 0 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 <1=>PC10 +#define RTE_SPI3_SCL_PORT_ID 0 +#if (RTE_SPI3_SCL_PORT_ID == 0) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 3 +#elif (RTE_SPI3_SCL_PORT_ID == 1) +#define RTE_SPI3_SCL_PORT GPIOC +#define RTE_SPI3_SCL_BIT 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>PB4 <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID 0 +#if (RTE_SPI3_MISO_PORT_ID == 0) +#define RTE_SPI3_MISO_PORT GPIOB +#define RTE_SPI3_MISO_BIT 4 +#elif (RTE_SPI3_MISO_PORT_ID == 1) +#define RTE_SPI3_MISO_PORT GPIOC +#define RTE_SPI3_MISO_BIT 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI Pin <0=>PB5 <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID 0 +#if (RTE_SPI3_MOSI_PORT_ID == 0) +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 5 +#elif (RTE_SPI3_MOSI_PORT_ID == 1) +#define RTE_SPI3_MOSI_PORT GPIOC +#define RTE_SPI3_MOSI_BIT 12 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 1 +#define RTE_SPI3_RX_DMA_NUMBER 1 +#define RTE_SPI3_RX_DMA_STREAM 0 +#define RTE_SPI3_RX_DMA_CHANNEL 0 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 1 +#define RTE_SPI3_TX_DMA_NUMBER 1 +#define RTE_SPI3_TX_DMA_STREAM 5 +#define RTE_SPI3_TX_DMA_CHANNEL 0 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::Drivers:MCI +#define RTE_SDIO 1 + +// SDIO_CD (Card Detect) Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_PIN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(7) +#define RTE_SDIO_CD_BIT 15 + +// SDIO_WP (Write Protect) Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_PIN 0 +#define RTE_SDIO_WP_ACTIVE 0 +#define RTE_SDIO_WP_PORT GPIO_PORT(7) +#define RTE_SDIO_WP_BIT 16 + +// SDIO Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) +#define RTE_SDIO_CK_PORT GPIOC +#define RTE_SDIO_CK_PIN 12 +#else +#error "Invalid SDIO_CK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) +#define RTE_SDIO_CMD_PORT GPIOD +#define RTE_SDIO_CMD_PIN 2 +#else +#error "Invalid SDIO_CDM Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) +#define RTE_SDIO_D0_PORT GPIOC +#define RTE_SDIO_D0_PIN 8 +#else +#error "Invalid SDIO_D0 Pin Configuration!" +#endif +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) +#define RTE_SDIO_D1_PORT GPIOC +#define RTE_SDIO_D1_PIN 9 +#else +#error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) +#define RTE_SDIO_D2_PORT GPIOC +#define RTE_SDIO_D2_PIN 10 +#else +#error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) +#define RTE_SDIO_D3_PORT GPIOC +#define RTE_SDIO_D3_PIN 11 +#else +#error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) +#define RTE_SDIO_D4_PORT GPIOB +#define RTE_SDIO_D4_PIN 8 +#else +#error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) +#define RTE_SDIO_D5_PORT GPIOB +#define RTE_SDIO_D5_PIN 9 +#else +#error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) +#define RTE_SDIO_D6_PORT GPIOC +#define RTE_SDIO_D6_PIN 6 +#else +#error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) +#define RTE_SDIO_D7_PORT GPIOC +#define RTE_SDIO_D7_PIN 7 +#else +#error "Invalid SDIO_D7 Pin Configuration!" +#endif +// + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA 1 +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_STREAM 3 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) +#define RTE_ETH_MII_TXD0_PORT GPIOG +#define RTE_ETH_MII_TXD0_PIN 13 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) +#define RTE_ETH_MII_TXD1_PORT GPIOG +#define RTE_ETH_MII_TXD1_PIN 14 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) +#define RTE_ETH_MII_TXD3_PORT GPIOE +#define RTE_ETH_MII_TXD3_PIN 2 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) +#define RTE_ETH_MII_TX_EN_PORT GPIOG +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_PORT_ID 0 +#if (RTE_ETH_MII_RXD0_PORT_ID == 0) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_PORT_ID 0 +#if (RTE_ETH_MII_RXD1_PORT_ID == 0) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif +// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 +#define RTE_ETH_MII_RXD2_PORT_ID 0 +#if (RTE_ETH_MII_RXD2_PORT_ID == 0) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) +#define RTE_ETH_MII_RXD2_PORT GPIOH +#define RTE_ETH_MII_RXD2_PIN 6 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 +#define RTE_ETH_MII_RXD3_PORT_ID 0 +#if (RTE_ETH_MII_RXD3_PORT_ID == 0) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RXD3_PORT GPIOH +#define RTE_ETH_MII_RXD3_PIN 7 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_PORT_ID 0 +#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif +// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RX_ER_PORT GPIOI +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#elif (RTE_ETH_MII_CRS_PORT_ID == 1) +#define RTE_ETH_MII_CRS_PORT GPIOH +#define RTE_ETH_MII_CRS_PIN 2 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 <1=>PH3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#elif (RTE_ETH_MII_COL_PORT_ID == 1) +#define RTE_ETH_MII_COL_PORT GPIOH +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 1 + +// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_RMII_TXD0_PORT_ID 1 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) +#define RTE_ETH_RMII_TXD0_PORT GPIOG +#define RTE_ETH_RMII_TXD0_PIN 13 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_RMII_TXD1_PORT_ID 1 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) +#define RTE_ETH_RMII_TXD1_PORT GPIOG +#define RTE_ETH_RMII_TXD1_PIN 14 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 1 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) +#define RTE_ETH_RMII_TX_EN_PORT GPIOG +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_PORT_ID 0 +#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_PORT_ID 0 +#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 +#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz/50MHz Clock generation +#define RTE_ETH_REF_CLOCK 0 + +// MCO Pin <0=>PA2 <1=>PC9 +#define RTE_ETH_REF_CLOCK_PORT_ID 0 +#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) +#define RTE_ETH_REF_CLOCK_PORT GPIOA +#define RTE_ETH_REF_CLOCK_PIN 8 +#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) +#define RTE_ETH_REF_CLOCK_PORT GPIOC +#define RTE_ETH_REF_CLOCK_PIN 9 +#else +#error "Invalid MCO Pin Configuration!" +#endif + +// + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_OTG_FS_DEV 1 + +// Endpoints +// Reduce memory requirements of Driver by disabling unused endpoints +// Endpoint 1 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 2 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 3 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// +#define RTE_USB_OTG_FS_DEV_EP 0x0000000F +#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E +#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E +#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E + +// + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 1 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) +#define RTE_OTG_FS_VBUS_BIT 5 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_FS_OC_BIT 11 +// + +// + + +// USB OTG High-speed +#define RTE_USB_OTG_HS 0 + +// PHY (Physical Layer) + +// PHY Interface +// <0=>On-chip full-speed PHY +// <1=>External ULPI high-speed PHY +#define RTE_USB_OTG_HS_PHY 1 + +// External ULPI Pins (UTMI+ Low Pin Interface) + +// OTG_HS_ULPI_CK Pin <0=>PA5 +#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" +#endif +// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 +#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 +#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 +#else +#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" +#endif +// OTG_HS_ULPI_STP Pin <0=>PC0 +#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" +#endif +// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 +#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 +#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 +#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 +#else +#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" +#endif +// OTG_HS_ULPI_D0 Pin <0=>PA3 +#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 +#else +#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" +#endif +// OTG_HS_ULPI_D1 Pin <0=>PB0 +#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" +#endif +// OTG_HS_ULPI_D2 Pin <0=>PB1 +#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 +#else +#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" +#endif +// OTG_HS_ULPI_D3 Pin <0=>PB10 +#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 +#else +#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" +#endif +// OTG_HS_ULPI_D4 Pin <0=>PB11 +#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 +#else +#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" +#endif +// OTG_HS_ULPI_D5 Pin <0=>PB12 +#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 +#else +#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" +#endif +// OTG_HS_ULPI_D6 Pin <0=>PB13 +#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 +#else +#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" +#endif +// OTG_HS_ULPI_D7 Pin <0=>PB5 +#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" +#endif + +// + +// + +// Device [Driver_USBD1] +// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device +#define RTE_USB_OTG_HS_DEV 1 + +// Endpoints +// Reduce memory requirements of Driver by disabling unused endpoints +// Endpoint 1 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 2 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 3 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 4 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 5 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// +#define RTE_USB_OTG_HS_DEV_EP 0x0000003F +#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E +#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E +#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E + +// + +// Host [Driver_USBH1] +// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host +#define RTE_USB_OTG_HS_HOST 1 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_VBUS_PIN 1 +#define RTE_OTG_HS_VBUS_ACTIVE 0 +#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_HS_VBUS_BIT 2 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_OC_PIN 1 +#define RTE_OTG_HS_OC_ACTIVE 0 +#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_HS_OC_BIT 12 +// + +// + + +// EXTI (External Interrupt/Event Controller) +#define RTE_EXTI 0 + +// EXTI0 Line +#define RTE_EXTI0 0 +// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 +#define RTE_EXTI0_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI0_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI0_TRIGGER 0 +// + +// EXTI1 Line +#define RTE_EXTI1 0 +// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 +#define RTE_EXTI1_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI1_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI1_TRIGGER 0 +// + +// EXTI2 Line +#define RTE_EXTI2 0 +// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 +#define RTE_EXTI2_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI2_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI2_TRIGGER 0 +// + +// EXTI3 Line +#define RTE_EXTI3 0 +// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 +#define RTE_EXTI3_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI3_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI3_TRIGGER 0 +// + +// EXTI4 Line +#define RTE_EXTI4 0 +// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 +#define RTE_EXTI4_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI4_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI4_TRIGGER 0 +// + +// EXTI5 Line +#define RTE_EXTI5 0 +// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 +#define RTE_EXTI5_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI5_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI5_TRIGGER 0 +// + +// EXTI6 Line +#define RTE_EXTI6 0 +// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 +#define RTE_EXTI6_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI6_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI6_TRIGGER 0 +// + +// EXTI7 Line +#define RTE_EXTI7 0 +// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 +#define RTE_EXTI7_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI7_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI7_TRIGGER 0 +// + +// EXTI8 Line +#define RTE_EXTI8 0 +// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 +#define RTE_EXTI8_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI8_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI8_TRIGGER 0 +// + +// EXTI9 Line +#define RTE_EXTI9 0 +// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 +#define RTE_EXTI9_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI9_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI9_TRIGGER 0 +// + +// EXTI10 Line +#define RTE_EXTI10 0 +// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 +#define RTE_EXTI10_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI10_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI10_TRIGGER 0 +// + +// EXTI11 Line +#define RTE_EXTI11 0 +// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 +#define RTE_EXTI11_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI11_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI11_TRIGGER 0 +// + +// EXTI12 Line +#define RTE_EXTI12 0 +// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 +#define RTE_EXTI12_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI12_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI12_TRIGGER 0 +// + +// EXTI13 Line +#define RTE_EXTI13 0 +// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 +#define RTE_EXTI13_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI13_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI13_TRIGGER 0 +// + +// EXTI14 Line +#define RTE_EXTI14 0 +// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 +#define RTE_EXTI14_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI14_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI14_TRIGGER 0 +// + +// EXTI15 Line +#define RTE_EXTI15 0 +// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 +#define RTE_EXTI15_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI15_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI15_TRIGGER 0 +// + +// EXTI16 Line: PVD Output +#define RTE_EXTI16 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI16_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI16_TRIGGER 0 +// + +// EXTI17 Line: RTC Alarm +#define RTE_EXTI17 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI17_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI17_TRIGGER 0 +// + +// EXTI18 Line: USB OTG FS Wakeup +#define RTE_EXTI18 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI18_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI18_TRIGGER 0 +// + +// EXTI19 Line: Ethernet Wakeup +#define RTE_EXTI19 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI19_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI19_TRIGGER 0 +// + +// EXTI20 Line: USB OTG HS Wakeup +#define RTE_EXTI20 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI20_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI20_TRIGGER 0 +// + +// EXTI21 Line: RTC Tamper and TimeStamp +#define RTE_EXTI21 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI21_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI21_TRIGGER 0 +// + +// EXTI22 Line: RTC Wakeup +#define RTE_EXTI22 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI22_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI22_TRIGGER 0 +// + +// + + +// FSMC (Flexible Static Memory Controller) +#define RTE_FSMC 0 + +// Pin Configuration +// Configure Pins +#define RTE_FSMC_PINS 0 + +// Address Bus Pins +// <0=>A[17:16] +// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] +// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] +// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] +#define RTE_FSMC_ABUS_PINS 10 +// Data Bus Pins <0=>D[7:0] <1=>D[15:0] +#define RTE_FSMC_DBUS_PINS 0 +// FSMC_NOE Pin +#define RTE_FSMC_NOE_PIN 0 +// FSMC_NWE Pin +#define RTE_FSMC_NWE_PIN 0 +// FSMC_NBL0 Pin +#define RTE_FSMC_NBL0_PIN 0 +// FSMC_NBL1 Pin +#define RTE_FSMC_NBL1_PIN 0 +// FSMC_NL Pin +#define RTE_FSMC_NL_PIN 0 +// FSMC_NWAIT Pin +#define RTE_FSMC_NWAIT_PIN 0 +// FSMC_CLK Pin +#define RTE_FSMC_CLK_PIN 0 +// FSMC_NE1/NCE2 Pin +#define RTE_FSMC_NE1_PIN 0 +// FSMC_NE2/NCE3 Pin +#define RTE_FSMC_NE2_PIN 0 +// FSMC_NE3/NCE4_1 Pin +#define RTE_FSMC_NE3_PIN 0 +// FSMC_NE4 Pin +#define RTE_FSMC_NE4_PIN 0 +// FSMC_NCE4_2 Pin +#define RTE_FSMC_NCE42_PIN 0 +// FSMC_INT2 Pin +#define RTE_FSMC_INT2_PIN 0 +// FSMC_INT3 Pin +#define RTE_FSMC_INT3_PIN 0 +// FSMC_INTR Pin +#define RTE_FSMC_INTR_PIN 0 +// FSMC_NIORD Pin +#define RTE_FSMC_NIORD_PIN 0 +// FSMC_NIOWR Pin +#define RTE_FSMC_NIOWR_PIN 0 +// FSMC_NREG Pin +#define RTE_FSMC_NREG_PIN 0 +// FSMC_CD Pin +#define RTE_FSMC_CD_PIN 0 + +// + +// NOR Flash / PSRAM Controller + +// FSMC_NE1 Chip Select +// Configure Device on Chip Select FSMC_NE1 +#define RTE_FSMC_NE1 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR1_CBURSTRW 0 +#define RTE_FSMC_BCR1_ASYNCWAIT 0 +#define RTE_FSMC_BCR1_EXTMOD 0 +#define RTE_FSMC_BCR1_WAITEN 1 +#define RTE_FSMC_BCR1_WREN 1 +#define RTE_FSMC_BCR1_WAITCFG 0 +#define RTE_FSMC_BCR1_WRAPMOD 0 +#define RTE_FSMC_BCR1_WAITPOL 0 +#define RTE_FSMC_BCR1_BURSTEN 0 +#define RTE_FSMC_BCR1_FACCEN 1 +#define RTE_FSMC_BCR1_MWID 1 +#define RTE_FSMC_BCR1_MTYP 2 +#define RTE_FSMC_BCR1_MUXEN 1 +#define RTE_FSMC_BCR1_MBKEN 1 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR1_ACCMOD 0 +#define RTE_FSMC_BTR1_DATLAT 15 +#define RTE_FSMC_BTR1_CLKDIV 15 +#define RTE_FSMC_BTR1_BUSTURN 15 +#define RTE_FSMC_BTR1_DATAST 255 +#define RTE_FSMC_BTR1_ADDHLD 15 +#define RTE_FSMC_BTR1_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR1_ACCMOD 0 +#define RTE_FSMC_BWTR1_DATLAT 15 +#define RTE_FSMC_BWTR1_CLKDIV 15 +#define RTE_FSMC_BWTR1_BUSTURN 15 +#define RTE_FSMC_BWTR1_DATAST 255 +#define RTE_FSMC_BWTR1_ADDHLD 15 +#define RTE_FSMC_BWTR1_ADDSET 15 +// +// + +// FSMC_NE2 Chip Select +// Configure Device on Chip Select FSMC_NE2 +#define RTE_FSMC_NE2 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR2_CBURSTRW 0 +#define RTE_FSMC_BCR2_ASYNCWAIT 0 +#define RTE_FSMC_BCR2_EXTMOD 0 +#define RTE_FSMC_BCR2_WAITEN 1 +#define RTE_FSMC_BCR2_WREN 1 +#define RTE_FSMC_BCR2_WAITCFG 0 +#define RTE_FSMC_BCR2_WRAPMOD 0 +#define RTE_FSMC_BCR2_WAITPOL 0 +#define RTE_FSMC_BCR2_BURSTEN 0 +#define RTE_FSMC_BCR2_FACCEN 1 +#define RTE_FSMC_BCR2_MWID 1 +#define RTE_FSMC_BCR2_MTYP 0 +#define RTE_FSMC_BCR2_MUXEN 1 +#define RTE_FSMC_BCR2_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR2_ACCMOD 0 +#define RTE_FSMC_BTR2_DATLAT 15 +#define RTE_FSMC_BTR2_CLKDIV 15 +#define RTE_FSMC_BTR2_BUSTURN 15 +#define RTE_FSMC_BTR2_DATAST 255 +#define RTE_FSMC_BTR2_ADDHLD 15 +#define RTE_FSMC_BTR2_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR2_ACCMOD 0 +#define RTE_FSMC_BWTR2_DATLAT 15 +#define RTE_FSMC_BWTR2_CLKDIV 15 +#define RTE_FSMC_BWTR2_BUSTURN 15 +#define RTE_FSMC_BWTR2_DATAST 255 +#define RTE_FSMC_BWTR2_ADDHLD 15 +#define RTE_FSMC_BWTR2_ADDSET 15 +// +// + +// FSMC_NE3 Chip Select +// Configure Device on Chip Select FSMC_NE3 +#define RTE_FSMC_NE3 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR3_CBURSTRW 0 +#define RTE_FSMC_BCR3_ASYNCWAIT 0 +#define RTE_FSMC_BCR3_EXTMOD 0 +#define RTE_FSMC_BCR3_WAITEN 1 +#define RTE_FSMC_BCR3_WREN 1 +#define RTE_FSMC_BCR3_WAITCFG 0 +#define RTE_FSMC_BCR3_WRAPMOD 0 +#define RTE_FSMC_BCR3_WAITPOL 0 +#define RTE_FSMC_BCR3_BURSTEN 0 +#define RTE_FSMC_BCR3_FACCEN 1 +#define RTE_FSMC_BCR3_MWID 1 +#define RTE_FSMC_BCR3_MTYP 0 +#define RTE_FSMC_BCR3_MUXEN 1 +#define RTE_FSMC_BCR3_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR3_ACCMOD 0 +#define RTE_FSMC_BTR3_DATLAT 15 +#define RTE_FSMC_BTR3_CLKDIV 15 +#define RTE_FSMC_BTR3_BUSTURN 15 +#define RTE_FSMC_BTR3_DATAST 255 +#define RTE_FSMC_BTR3_ADDHLD 15 +#define RTE_FSMC_BTR3_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR3_ACCMOD 0 +#define RTE_FSMC_BWTR3_DATLAT 15 +#define RTE_FSMC_BWTR3_CLKDIV 15 +#define RTE_FSMC_BWTR3_BUSTURN 15 +#define RTE_FSMC_BWTR3_DATAST 255 +#define RTE_FSMC_BWTR3_ADDHLD 15 +#define RTE_FSMC_BWTR3_ADDSET 15 +// +// + +// FSMC_NE4 Chip Select +// Configure Device on Chip Select FSMC_NE4 +#define RTE_FSMC_NE4 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR4_CBURSTRW 0 +#define RTE_FSMC_BCR4_ASYNCWAIT 0 +#define RTE_FSMC_BCR4_EXTMOD 0 +#define RTE_FSMC_BCR4_WAITEN 1 +#define RTE_FSMC_BCR4_WREN 1 +#define RTE_FSMC_BCR4_WAITCFG 0 +#define RTE_FSMC_BCR4_WRAPMOD 0 +#define RTE_FSMC_BCR4_WAITPOL 0 +#define RTE_FSMC_BCR4_BURSTEN 0 +#define RTE_FSMC_BCR4_FACCEN 1 +#define RTE_FSMC_BCR4_MWID 1 +#define RTE_FSMC_BCR4_MTYP 0 +#define RTE_FSMC_BCR4_MUXEN 1 +#define RTE_FSMC_BCR4_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR4_ACCMOD 0 +#define RTE_FSMC_BTR4_DATLAT 15 +#define RTE_FSMC_BTR4_CLKDIV 15 +#define RTE_FSMC_BTR4_BUSTURN 15 +#define RTE_FSMC_BTR4_DATAST 255 +#define RTE_FSMC_BTR4_ADDHLD 15 +#define RTE_FSMC_BTR4_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR4_ACCMOD 0 +#define RTE_FSMC_BWTR4_DATLAT 15 +#define RTE_FSMC_BWTR4_CLKDIV 15 +#define RTE_FSMC_BWTR4_BUSTURN 15 +#define RTE_FSMC_BWTR4_DATAST 255 +#define RTE_FSMC_BWTR4_ADDHLD 15 +#define RTE_FSMC_BWTR4_ADDSET 15 +// +// + +// + +// NAND Flash Controller + +// FSMC_NCE2 Chip Select +// Configure NAND Device on Chip Select FSMC_NCE2 +#define RTE_FSMC_NCE2 0 + +// NAND Flash Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <1=>NAND Flash +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: NAND Flash memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR2_ECCPS 0 +#define RTE_FSMC_PCR2_TAR 0 +#define RTE_FSMC_PCR2_TCLR 0 +#define RTE_FSMC_PCR2_ECCEN 0 +#define RTE_FSMC_PCR2_PWID 0 +#define RTE_FSMC_PCR2_PTYP 1 +#define RTE_FSMC_PCR2_PBKEN 0 +#define RTE_FSMC_PCR2_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR2_IFEN 0 +#define RTE_FSMC_SR2_ILEN 0 +#define RTE_FSMC_SR2_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM2_MEMHIZ 255 +#define RTE_FSMC_PMEM2_MEMHOLD 255 +#define RTE_FSMC_PMEM2_MEMWAIT 255 +#define RTE_FSMC_PMEM2_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT2_ATTHIZ 255 +#define RTE_FSMC_PATT2_ATTHOLD 255 +#define RTE_FSMC_PATT2_ATTWAIT 255 +#define RTE_FSMC_PATT2_ATTSET 255 + +// + +// + +// FSMC_NCE3 Chip Select +// Configure NAND Device on Chip Select FSMC_NCE3 +#define RTE_FSMC_NCE3 0 + +// NAND Flash Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <1=>NAND Flash +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: NAND Flash memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR3_ECCPS 0 +#define RTE_FSMC_PCR3_TAR 0 +#define RTE_FSMC_PCR3_TCLR 0 +#define RTE_FSMC_PCR3_ECCEN 0 +#define RTE_FSMC_PCR3_PWID 0 +#define RTE_FSMC_PCR3_PTYP 1 +#define RTE_FSMC_PCR3_PBKEN 0 +#define RTE_FSMC_PCR3_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR3_IFEN 0 +#define RTE_FSMC_SR3_ILEN 0 +#define RTE_FSMC_SR3_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM3_MEMHIZ 255 +#define RTE_FSMC_PMEM3_MEMHOLD 255 +#define RTE_FSMC_PMEM3_MEMWAIT 255 +#define RTE_FSMC_PMEM3_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT3_ATTHIZ 255 +#define RTE_FSMC_PATT3_ATTHOLD 255 +#define RTE_FSMC_PATT3_ATTWAIT 255 +#define RTE_FSMC_PATT3_ATTSET 255 + +// + +// + +// + +// PC Card Controller + +// FSMC_NCE4_x Chip Select +// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 +#define RTE_FSMC_NCE4 0 + +// PC Card Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: PC Card memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR4_ECCPS 0 +#define RTE_FSMC_PCR4_TAR 0 +#define RTE_FSMC_PCR4_TCLR 0 +#define RTE_FSMC_PCR4_ECCEN 0 +#define RTE_FSMC_PCR4_PWID 0 +#define RTE_FSMC_PCR4_PTYP 0 +#define RTE_FSMC_PCR4_PBKEN 0 +#define RTE_FSMC_PCR4_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR4_IFEN 0 +#define RTE_FSMC_SR4_ILEN 0 +#define RTE_FSMC_SR4_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM4_MEMHIZ 255 +#define RTE_FSMC_PMEM4_MEMHOLD 255 +#define RTE_FSMC_PMEM4_MEMWAIT 255 +#define RTE_FSMC_PMEM4_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT4_ATTHIZ 255 +#define RTE_FSMC_PATT4_ATTHOLD 255 +#define RTE_FSMC_PATT4_ATTWAIT 255 +#define RTE_FSMC_PATT4_ATTSET 255 + +// + +// I/O space timing +// IOHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a PC Card write access. Only valid for write transaction. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// IOHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for PC Card read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// IOWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, +// SMNOE), for PC Card read or write access. The duration for command assertion is +// extended if the wait signal (NWAIT) is active (low) at the end of the +// programmed value of HCLK. +// 0000 0000: reserved, do not use this value +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles +// IOSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for PC Card read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PIO4_IOHIZ 255 +#define RTE_FSMC_PIO4_IOHOLD 255 +#define RTE_FSMC_PIO4_IOWAIT 255 +#define RTE_FSMC_PIO4_IOSET 255 + +// + +// + +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s new file mode 100644 index 000000000..eae6859dd --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/startup_stm32f2xx.s @@ -0,0 +1,419 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 18-April-2011 +;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00009000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c new file mode 100644 index 000000000..da0e189c8 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/Device/STM32F207IG/system_stm32f2xx.c @@ -0,0 +1,536 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-April-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c new file mode 100644 index 000000000..78564b080 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config.c @@ -0,0 +1,72 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config.c + * Purpose: File System Configuration + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// File System +// Define File System global parameters + +// Number of open files <4-16> +// Define number of files that can be +// opened at the same time. +// Default: 8 +#define NUM_FILES 8 + +// FAT Name Cache Size <0-1000000> +// Define number of cached FAT file or directory names. +// 48 bytes of RAM is required for each cached name. +#define FAT_NAME_CACHE_SIZE 0 + +// Relocate FAT Name Cache Buffer +// Locate Cache Buffer at a specific address. +#define FAT_NAME_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +#define FAT_NAME_CACHE_ADDR 0x60000000 + +// + +// + +#include "..\RTE_Components.h" + +#ifdef RTE_FileSystem_Drive_RAM +#include "FS_Config_RAM.h" +#endif + +#ifdef RTE_FileSystem_Drive_NOR_0 +#include "FS_Config_NOR_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NOR_1 +#include "FS_Config_NOR_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NAND_0 +#include "FS_Config_NAND_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NAND_1 +#include "FS_Config_NAND_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_MC_0 +#include "FS_Config_MC_0.h" +#endif +#ifdef RTE_FileSystem_Drive_MC_1 +#include "FS_Config_MC_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_USB_0 +#include "FS_Config_USB_0.h" +#endif +#ifdef RTE_FileSystem_Drive_USB_1 +#include "FS_Config_USB_1.h" +#endif + +#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h new file mode 100644 index 000000000..0b1c6d3a7 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/File_System/FS_Config_MC_0.h @@ -0,0 +1,57 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System:Drive + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config_MC_0.h + * Purpose: File System Configuration for Memory Card Drive + * Rev.: V5.01 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Memory Card Drive 0 +// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" +#define MC0_ENABLE 1 + +// Connect to hardware via Driver_MCI# <0-255> +// Select driver control block for hardware interface +#define MC0_MCI_DRIVER 0 + +// Connect to hardware via Driver_SPI# <0-255> +// Select driver control block for hardware interface when in SPI mode +#define MC0_SPI_DRIVER 0 + +// Memory Card Interface Mode <0=>Native <1=>SPI +// Native uses a SD Bus with up to 8 data lines, CLK, and CMD +// SPI uses 2 data lines (MOSI and MISO), SCLK and CS +// When using SPI both Driver_SPI# and Driver_MCI# must be specified +// since the MCI driver provides the control interface lines. +#define MC0_SPI 0 + +// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Drive Cache stores data sectors and may be increased to speed-up +// file read/write operations on this drive (default: 4 KB) +#define MC0_CACHE_SIZE 4 + +// Locate Drive Cache and Drive Buffer +// Some microcontrollers support DMA only in specific memory areas and +// require to locate the drive buffers at a fixed address. +#define MC0_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Set buffer base address to RAM areas that support DMA with the drive. +#define MC0_CACHE_ADDR 0x7FD00000 + +// + +// Use FAT Journal +// Protect File Allocation Table and Directory Entries for +// fail-safe operation. +#define MC0_FAT_JOURNAL 0 + +// Default Drive "M0:" +// Use this drive when no drive letter is specified. +#define MC0_DEFAULT_DRIVE 1 + +// diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h new file mode 100644 index 000000000..aa51462ab --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/RTE/RTE_Components.h @@ -0,0 +1,19 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'CryptBenchmark' + * Target: 'CryptBenchmark' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ +#define RTE_Drivers_MCI0 /* Driver MCI0 */ +#define RTE_FileSystem_Core /* File System Core */ + #define RTE_FileSystem_LFN /* File System with Long Filename support */ +#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini new file mode 100644 index 000000000..239abce37 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/STM32_SWO.ini @@ -0,0 +1,36 @@ +/******************************************************************************/ +/* STM32_SWO.ini: STM32 Debugger Initialization File */ +/******************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> // +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + + +FUNC void DebugSetup (void) { +// Debug MCU Configuration +// DBG_SLEEP Debug Sleep Mode +// DBG_STOP Debug Stop Mode +// DBG_STANDBY Debug Standby Mode +// TRACE_IOEN Trace I/O Enable +// TRACE_MODE Trace Mode +// <0=> Asynchronous +// <1=> Synchronous: TRACEDATA Size 1 +// <2=> Synchronous: TRACEDATA Size 2 +// <3=> Synchronous: TRACEDATA Size 4 +// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted +// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted +// DBG_TIM1_STOP Timer 1 Stopped when Core is halted +// DBG_TIM2_STOP Timer 2 Stopped when Core is halted +// DBG_TIM3_STOP Timer 3 Stopped when Core is halted +// DBG_TIM4_STOP Timer 4 Stopped when Core is halted +// DBG_CAN_STOP CAN Stopped when Core is halted +// + _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR +} + +DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c new file mode 100644 index 000000000..d0f9fbd38 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/benchmark.c @@ -0,0 +1,1106 @@ +/* benchmark.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* CTaoCrypt benchmark */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#ifdef HAVE_CAVIUM + #include "cavium_sysdep.h" + #include "cavium_common.h" + #include "cavium_ioctl.h" +#endif + +#if defined(CYASSL_MDK_ARM) + extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ; + #define fopen CyaSSL_fopen +#endif + +#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) + /* include test cert and key buffers for use with NO_FILESYSTEM */ + #if defined(CYASSL_MDK_ARM) + #include "cert_data.h" /* use certs_test.c for initial data, + so other commands can share the data. */ + #else + #include + #endif +#endif + + +#ifdef HAVE_BLAKE2 + #include + void bench_blake2(void); +#endif + +#ifdef _MSC_VER + /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */ + #pragma warning(disable: 4996) +#endif + +void bench_des(void); +void bench_arc4(void); +void bench_hc128(void); +void bench_rabbit(void); +void bench_aes(int); +void bench_aesgcm(void); +void bench_aesccm(void); +void bench_camellia(void); + +void bench_md5(void); +void bench_sha(void); +void bench_sha256(void); +void bench_sha512(void); +void bench_ripemd(void); + +void bench_rsa(void); +void bench_rsaKeyGen(void); +void bench_dh(void); +#ifdef HAVE_ECC +void bench_eccKeyGen(void); +void bench_eccKeyAgree(void); +#endif + +double current_time(int); + + +#ifdef HAVE_CAVIUM + +static int OpenNitroxDevice(int dma_mode,int dev_id) +{ + Csp1CoreAssignment core_assign; + Uint32 device; + + if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID)) + return -1; + if (Csp1GetDevType(&device)) + return -1; + if (device != NPX_DEVICE) { + if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT, + (Uint32 *)&core_assign)!= 0) + return -1; + } + CspShutdown(CAVIUM_DEV_ID); + + return CspInitialize(dma_mode, dev_id); +} + +#endif + + +/* so embedded projects can pull in tests on their own */ +#if !defined(NO_MAIN_DRIVER) + +int main(int argc, char** argv) + +{ + (void)argc; + (void)argv; +#else +int benchmark_test(void *args) +{ +#endif + + #ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) { + printf("Cavium OpenNitroxDevice failed\n"); + exit(-1); + } +#endif /* HAVE_CAVIUM */ +#ifndef NO_AES + bench_aes(0); + bench_aes(1); +#endif +#ifdef HAVE_AESGCM + bench_aesgcm(); +#endif +#ifdef HAVE_AESCCM + bench_aesccm(); +#endif +#ifdef HAVE_CAMELLIA + bench_camellia(); +#endif +#ifndef NO_RC4 + bench_arc4(); +#endif +#ifdef HAVE_HC128 + bench_hc128(); +#endif +#ifndef NO_RABBIT + bench_rabbit(); +#endif +#ifndef NO_DES3 + bench_des(); +#endif + + printf("\n"); + +#ifndef NO_MD5 + bench_md5(); +#endif +#ifndef NO_SHA + bench_sha(); +#endif +#ifndef NO_SHA256 + bench_sha256(); +#endif +#ifdef CYASSL_SHA512 + bench_sha512(); +#endif +#ifdef CYASSL_RIPEMD + bench_ripemd(); +#endif +#ifdef HAVE_BLAKE2 + bench_blake2(); +#endif + + printf("\n"); + +#ifndef NO_RSA + bench_rsa(); +#endif + +#ifndef NO_DH + bench_dh(); +#endif + +#if defined(CYASSL_KEY_GEN) && !defined(NO_RSA) + bench_rsaKeyGen(); +#endif + +#ifdef HAVE_ECC + bench_eccKeyGen(); + bench_eccKeyAgree(); +#endif + + return 0; +} + + +#ifdef BENCH_EMBEDDED +const int numBlocks = 25; /* how many kB/megs to test (en/de)cryption */ +const char blockType[] = "kB"; /* used in printf output */ +const int times = 1; /* public key iterations */ +#else +const int numBlocks = 5; +const char blockType[] = "megs"; +const int times = 100; +#endif + +const byte key[] = +{ + 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, + 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, + 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 +}; + +const byte iv[] = +{ + 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81 + +}; + + +/* use kB instead of mB for embedded benchmarking */ +#ifdef BENCH_EMBEDDED +byte plain [1024]; +byte cipher[1024]; +#else +byte plain [1024*1024]; +byte cipher[1024*1024]; +#endif + + +#ifndef NO_AES +void bench_aes(int show) +{ + Aes enc; + double start, total, persec; + int i; + +#ifdef HAVE_CAVIUM + if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) + printf("aes init cavium failed\n"); +#endif + + AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesCbcEncrypt(&enc, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + if (show) + printf("AES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +#ifdef HAVE_CAVIUM + AesFreeCavium(&enc); +#endif +} +#endif + + +byte additional[13]; +byte tag[16]; + + +#ifdef HAVE_AESGCM +void bench_aesgcm(void) +{ + Aes enc; + double start, total, persec; + int i; + + AesGcmSetKey(&enc, key, 16); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesGcmEncrypt(&enc, cipher, plain, sizeof(plain), iv, 12, + tag, 16, additional, 13); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("AES-GCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifdef HAVE_AESCCM +void bench_aesccm(void) +{ + Aes enc; + double start, total, persec; + int i; + + AesCcmSetKey(&enc, key, 16); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesCcmEncrypt(&enc, cipher, plain, sizeof(plain), iv, 12, + tag, 16, additional, 13); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("AES-CCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifdef HAVE_CAMELLIA +void bench_camellia(void) +{ + Camellia cam; + double start, total, persec; + int i; + + CamelliaSetKey(&cam, key, 16, iv); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + CamelliaCbcEncrypt(&cam, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("Camellia %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifndef NO_DES3 +void bench_des(void) +{ + Des3 enc; + double start, total, persec; + int i; + +#ifdef HAVE_CAVIUM + if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) + printf("des3 init cavium failed\n"); +#endif + Des3_SetKey(&enc, key, iv, DES_ENCRYPTION); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Des3_CbcEncrypt(&enc, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("3DES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +#ifdef HAVE_CAVIUM + Des3_FreeCavium(&enc); +#endif +} +#endif + + +#ifndef NO_RC4 +void bench_arc4(void) +{ + Arc4 enc; + double start, total, persec; + int i; + +#ifdef HAVE_CAVIUM + if (Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0) + printf("arc4 init cavium failed\n"); +#endif + + Arc4SetKey(&enc, key, 16); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Arc4Process(&enc, cipher, plain, sizeof(plain)); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("ARC4 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +#ifdef HAVE_CAVIUM + Arc4FreeCavium(&enc); +#endif +} +#endif + + +#ifdef HAVE_HC128 +void bench_hc128(void) +{ + HC128 enc; + double start, total, persec; + int i; + + Hc128_SetKey(&enc, key, iv); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Hc128_Process(&enc, cipher, plain, sizeof(plain)); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("HC128 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* HAVE_HC128 */ + + +#ifndef NO_RABBIT +void bench_rabbit(void) +{ + Rabbit enc; + double start, total, persec; + int i; + + RabbitSetKey(&enc, key, iv); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + RabbitProcess(&enc, cipher, plain, sizeof(plain)); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("RABBIT %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* NO_RABBIT */ + + +#ifndef NO_MD5 +void bench_md5(void) +{ + Md5 hash; + byte digest[MD5_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitMd5(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Md5Update(&hash, plain, sizeof(plain)); + + Md5Final(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("MD5 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* NO_MD5 */ + + +#ifndef NO_SHA +void bench_sha(void) +{ + Sha hash; + byte digest[SHA_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitSha(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + ShaUpdate(&hash, plain, sizeof(plain)); + + ShaFinal(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("SHA %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* NO_SHA */ + + +#ifndef NO_SHA256 +void bench_sha256(void) +{ + Sha256 hash; + byte digest[SHA256_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitSha256(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Sha256Update(&hash, plain, sizeof(plain)); + + Sha256Final(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("SHA-256 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + +#ifdef CYASSL_SHA512 +void bench_sha512(void) +{ + Sha512 hash; + byte digest[SHA512_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitSha512(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Sha512Update(&hash, plain, sizeof(plain)); + + Sha512Final(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("SHA-512 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + +#ifdef CYASSL_RIPEMD +void bench_ripemd(void) +{ + RipeMd hash; + byte digest[RIPEMD_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitRipeMd(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + RipeMdUpdate(&hash, plain, sizeof(plain)); + + RipeMdFinal(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("RIPEMD %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifdef HAVE_BLAKE2 +void bench_blake2(void) +{ + Blake2b b2b; + byte digest[64]; + double start, total, persec; + int i; + + InitBlake2b(&b2b, 64); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Blake2bUpdate(&b2b, plain, sizeof(plain)); + + Blake2bFinal(&b2b, digest, 64); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("BLAKE2b %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#if !defined(NO_RSA) || !defined(NO_DH) \ + || defined(CYASSL_KEYGEN) || defined(HAVE_ECC) +RNG rng; +#endif + +#ifndef NO_RSA + + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && \ + defined(CYASSL_MDK_SHELL) +static char *certRSAname = "certs/rsa2048.der" ; +void set_Bench_RSA_File(char * cert) { certRSAname = cert ; } + /* set by shell command */ +#elif defined(CYASSL_MDK_SHELL) + /* nothing */ +#else +static const char *certRSAname = "certs/rsa2048.der" ; +#endif + +void bench_rsa(void) +{ + int i; + int ret; + byte tmp[3072]; + size_t bytes; + word32 idx = 0; + + byte message[] = "Everyone gets Friday off."; + byte enc[512]; /* for up to 4096 bit */ + const int len = (int)strlen((char*)message); + double start, total, each, milliEach; + + RsaKey rsaKey; + int rsaKeySz = 2048; /* used in printf */ + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, rsa_key_der_1024, sizeof_rsa_key_der_1024); + bytes = sizeof_rsa_key_der_1024; + rsaKeySz = 1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, rsa_key_der_2048, sizeof_rsa_key_der_2048); + bytes = sizeof_rsa_key_der_2048; +#else + FILE* file = fopen(certRSAname, "rb"); + + if (!file) { + printf("can't find %s, Please run from CyaSSL home dir\n", certRSAname); + return; + } + + bytes = fread(tmp, 1, sizeof(tmp), file); + fclose(file); +#endif /* USE_CERT_BUFFERS */ + + +#ifdef HAVE_CAVIUM + if (RsaInitCavium(&rsaKey, CAVIUM_DEV_ID) != 0) + printf("RSA init cavium failed\n"); +#endif + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } + InitRsaKey(&rsaKey, 0); + ret = RsaPrivateKeyDecode(tmp, &idx, &rsaKey, (word32)bytes); + + start = current_time(1); + + for (i = 0; i < times; i++) + ret = RsaPublicEncrypt(message,len,enc,sizeof(enc), &rsaKey, &rng); + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("RSA %d encryption took %6.2f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, times); + + if (ret < 0) { + printf("Rsa Public Encrypt failed\n"); + return; + } + + start = current_time(1); + + for (i = 0; i < times; i++) { + byte out[512]; /* for up to 4096 bit */ + RsaPrivateDecrypt(enc, (word32)ret, out, sizeof(out), &rsaKey); + } + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("RSA %d decryption took %6.2f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, times); + + FreeRsaKey(&rsaKey); +#ifdef HAVE_CAVIUM + RsaFreeCavium(&rsaKey); +#endif +} +#endif + + +#ifndef NO_DH + + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && \ + defined(CYASSL_MDK_SHELL) +static char *certDHname = "certs/dh2048.der" ; +void set_Bench_DH_File(char * cert) { certDHname = cert ; } + /* set by shell command */ +#elif defined(CYASSL_MDK_SHELL) + /* nothing */ +#else +static const char *certDHname = "certs/dh2048.der" ; +#endif + +void bench_dh(void) +{ + int i, ret; + byte tmp[1024]; + size_t bytes; + word32 idx = 0, pubSz, privSz, pubSz2, privSz2, agreeSz; + + byte pub[256]; /* for 2048 bit */ + byte priv[256]; /* for 2048 bit */ + byte pub2[256]; /* for 2048 bit */ + byte priv2[256]; /* for 2048 bit */ + byte agree[256]; /* for 2048 bit */ + + double start, total, each, milliEach; + DhKey dhKey; + int dhKeySz = 2048; /* used in printf */ + + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024); + bytes = sizeof_dh_key_der_1024; + dhKeySz = 1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, dh_key_der_2048, sizeof_dh_key_der_2048); + bytes = sizeof_dh_key_der_2048; +#else + FILE* file = fopen(certDHname, "rb"); + + if (!file) { + printf("can't find %s, Please run from CyaSSL home dir\n", certDHname); + return; + } + + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } + bytes = fread(tmp, 1, sizeof(tmp), file); +#endif /* USE_CERT_BUFFERS */ + + + InitDhKey(&dhKey); + bytes = DhKeyDecode(tmp, &idx, &dhKey, (word32)bytes); + if (bytes != 0) { + printf("dhekydecode failed, can't benchmark\n"); + #if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + fclose(file); + #endif + return; + } + + start = current_time(1); + + for (i = 0; i < times; i++) + DhGenerateKeyPair(&dhKey, &rng, priv, &privSz, pub, &pubSz); + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("DH %d key generation %6.2f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, times); + + DhGenerateKeyPair(&dhKey, &rng, priv2, &privSz2, pub2, &pubSz2); + start = current_time(1); + + for (i = 0; i < times; i++) + DhAgree(&dhKey, agree, &agreeSz, priv, privSz, pub2, pubSz2); + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("DH %d key agreement %6.2f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, times); + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + fclose(file); +#endif + FreeDhKey(&dhKey); +} +#endif + +#if defined(CYASSL_KEY_GEN) && !defined(NO_RSA) +void bench_rsaKeyGen(void) +{ + RsaKey genKey; + double start, total, each, milliEach; + int i; + const int genTimes = 5; + + /* 1024 bit */ + start = current_time(1); + + for(i = 0; i < genTimes; i++) { + InitRsaKey(&genKey, 0); + MakeRsaKey(&genKey, 1024, 65537, &rng); + FreeRsaKey(&genKey); + } + + total = current_time(0) - start; + each = total / genTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("\n"); + printf("RSA 1024 key generation %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, genTimes); + + /* 2048 bit */ + start = current_time(1); + + for(i = 0; i < genTimes; i++) { + InitRsaKey(&genKey, 0); + MakeRsaKey(&genKey, 2048, 65537, &rng); + FreeRsaKey(&genKey); + } + + total = current_time(0) - start; + each = total / genTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("RSA 2048 key generation %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, genTimes); +} +#endif /* CYASSL_KEY_GEN */ + +#ifdef HAVE_ECC +void bench_eccKeyGen(void) +{ + ecc_key genKey; + double start, total, each, milliEach; + int i, ret; + const int genTimes = 5; + + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } + /* 256 bit */ + start = current_time(1); + + for(i = 0; i < genTimes; i++) { + ecc_make_key(&rng, 32, &genKey); + ecc_free(&genKey); + } + + total = current_time(0) - start; + each = total / genTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("\n"); + printf("ECC 256 key generation %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, genTimes); +} + + +void bench_eccKeyAgree(void) +{ + ecc_key genKey, genKey2; + double start, total, each, milliEach; + int i, ret; + const int agreeTimes = 5; + byte shared[1024]; + byte sig[1024]; + byte digest[32]; + word32 x; + + ecc_init(&genKey); + ecc_init(&genKey2); + + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } + + ret = ecc_make_key(&rng, 32, &genKey); + if (ret != 0) { + printf("ecc_make_key failed\n"); + return; + } + ret = ecc_make_key(&rng, 32, &genKey2); + if (ret != 0) { + printf("ecc_make_key failed\n"); + return; + } + + /* 256 bit */ + start = current_time(1); + + for(i = 0; i < agreeTimes; i++) { + x = sizeof(shared); + ret = ecc_shared_secret(&genKey, &genKey2, shared, &x); + if (ret != 0) { + printf("ecc_shared_secret failed\n"); + return; + } + } + + total = current_time(0) - start; + each = total / agreeTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("EC-DHE key agreement %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, agreeTimes); + + /* make dummy digest */ + for (i = 0; i < (int)sizeof(digest); i++) + digest[i] = i; + + + start = current_time(1); + + for(i = 0; i < agreeTimes; i++) { + x = sizeof(sig); + ret = ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &genKey); + if (ret != 0) { + printf("ecc_sign_hash failed\n"); + return; + } + } + + total = current_time(0) - start; + each = total / agreeTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("EC-DSA sign time %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, agreeTimes); + + start = current_time(1); + + for(i = 0; i < agreeTimes; i++) { + int verify = 0; + ret = ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &genKey); + if (ret != 0) { + printf("ecc_verify_hash failed\n"); + return; + } + } + + total = current_time(0) - start; + each = total / agreeTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("EC-DSA verify time %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, agreeTimes); + + ecc_free(&genKey2); + ecc_free(&genKey); +} +#endif /* HAVE_ECC */ + + +#ifdef _WIN32 + + #define WIN32_LEAN_AND_MEAN + #include + + double current_time(int reset) + { + (void)reset; + + static int init = 0; + static LARGE_INTEGER freq; + + LARGE_INTEGER count; + + if (!init) { + QueryPerformanceFrequency(&freq); + init = 1; + } + + QueryPerformanceCounter(&count); + + return (double)count.QuadPart / freq.QuadPart; + } + +#elif defined MICROCHIP_PIC32 + + #include + + double current_time(int reset) + { + /* NOTE: core timer tick rate = 40 Mhz, 1 tick = 25 ns */ + + unsigned int ns; + + /* should we reset our timer back to zero? Helps prevent timer + rollover */ + + if (reset) { + WriteCoreTimer(0); + } + + /* get timer in ns */ + ns = ReadCoreTimer() * 25; + + /* return seconds as a double */ + return ( ns / 1000000000.0 ); + } + +#elif defined CYASSL_MDK_ARM + extern double current_time(int reset) ; +#else + + #include + + double current_time(int reset) + { + (void) reset; + + struct timeval tv; + gettimeofday(&tv, 0); + + return (double)tv.tv_sec + (double)tv.tv_usec / 1000000; + } + +#endif /* _WIN32 */ + diff --git a/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c b/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c new file mode 100644 index 000000000..4bc12cbd0 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptBenchmark/main.c @@ -0,0 +1,71 @@ +/* main.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include +#include + +#include "cmsis_os.h" +#include "rl_fs.h" + +#include + +/*----------------------------------------------------------------------------- + * Initialize a Flash Memory Card + *----------------------------------------------------------------------------*/ +static void init_filesystem (void) { + int32_t retv; + + retv = finit ("M0:"); + if (retv == 0) { + retv = fmount ("M0:"); + if (retv == 0) { + printf ("Drive M0 ready!\n"); + } + else { + printf ("Drive M0 mount failed!\n"); + } + } + else { + printf ("Drive M0 initialization failed!\n"); + } +} +extern void benchmark_test(void * arg) ; +extern void init_time(void) ; + +/*----------------------------------------------------------------------------- + * mian entry + *----------------------------------------------------------------------------*/ + +int main() +{ + void * arg = NULL ; + + init_time() ; + init_filesystem (); + printf("=== Start: Crypt Benchmark ===\n") ; + benchmark_test(arg) ; + printf("=== End: Crypt Benchmark ===\n") ; + +} diff --git a/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt b/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt new file mode 100644 index 000000000..5d4a8312e --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/Abstract.txt @@ -0,0 +1,16 @@ +This program is a simple test suite of wolfCrypt library. + +In order to run this test suite, copy +{PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. + +For test configuration, refer config-Crypt.h. + +For the hardware crypt on config-Crypt.h, download +STSW-STM32062: STM32F2xx standard peripherals library at +http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to + {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib + + + Support +------- +Please send questions or comments to support@wolfssl.com diff --git a/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx new file mode 100644 index 000000000..a7474ba71 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvoptx @@ -0,0 +1,1094 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + CryptTest + 0x4 + ARM-ADS + + 120000000 + + 1 + 1 + 0 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Object\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -REMAP -MPU + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 8 + + + + + + + + + + .\STM32_SWO.ini + BIN\ULP2CM3.DLL + + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + ULP2CM3 + -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm) + + + 0 + DLGUARM + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + + + + + + 1 + 8 + tmp + + + + + 2 + 8 + 0x8004dc8 + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\test.c + test.c + 0 + 0 + + + + + Configuration + 1 + 0 + 0 + 0 + + 2 + 3 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\RTE\wolfSSL\config-Crypt.h + config-Crypt.h + 0 + 0 + + + + + Documentation + 1 + 0 + 0 + 0 + + 3 + 4 + 5 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\Abstract.txt + Abstract.txt + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + 4 + 5 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + RTX_CM3.lib + 1 + 0 + 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C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c + des3.c + 1 + 0 + + + 8 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c + dh.c + 1 + 0 + + + 8 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c + dsa.c + 1 + 0 + + + 8 + 30 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c + ecc.c + 1 + 0 + + + 8 + 31 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c + ecc_fp.c + 1 + 0 + + + 8 + 32 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c + error.c + 1 + 0 + + + 8 + 33 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c + hc128.c + 1 + 0 + + + 8 + 34 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c + hmac.c + 1 + 0 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C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c + pwdbased.c + 1 + 0 + + + 8 + 43 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c + rabbit.c + 1 + 0 + + + 8 + 44 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c + random.c + 1 + 0 + + + 8 + 45 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c + ripemd.c + 1 + 0 + + + 8 + 46 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c + rsa.c + 1 + 0 + + + 8 + 47 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c + sha.c + 1 + 0 + + + 8 + 48 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 8 + 49 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 8 + 50 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 8 + 51 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + RTE\wolfSSL\config-Crypt.h + config-Crypt.h + 1 + 0 + + + 8 + 52 + 5 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + RTE\wolfSSL\config.h + config.h + 1 + 0 + + + + diff --git a/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx new file mode 100644 index 000000000..6db3f16fa --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/CryptTest.uvprojx @@ -0,0 +1,919 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + CryptTest + 0x4 + ARM-ADS + + + STM32F207IG + STMicroelectronics + IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + 0 + $$Device:STM32F207IG$Device\Include\stm32f2xx.h + + + + + + + + + + $$Device:STM32F207IG$SVD\STM32F20x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Object\ + CryptTest + 1 + 0 + 0 + 1 + 1 + .\Object\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -REMAP -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 8 + + + + + + + + + + + + + .\STM32_SWO.ini + BIN\ULP2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\ULP2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + HAVE_CONFIG_H MDK_CONF_CryptTest CYASSL_STM32F2xx __DBG_ITM + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + test.c + 1 + .\test.c + + + + + Configuration + + + config-Crypt.h + 5 + .\RTE\wolfSSL\config-Crypt.h + + + + + Documentation + + + Abstract.txt + 5 + .\Abstract.txt + + + + + ::CMSIS + + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + + + RTX_Conf_CM.c + 1 + RTE\CMSIS\RTX_Conf_CM.c + + + + + ::Device + + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c + + + RTE_Device.h + 5 + RTE\Device\STM32F207IG\RTE_Device.h + + + startup_stm32f2xx.s + 2 + RTE\Device\STM32F207IG\startup_stm32f2xx.s + + + system_stm32f2xx.c + 1 + RTE\Device\STM32F207IG\system_stm32f2xx.c + + + + + ::Drivers + + + MCI_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + + + + + ::File System + + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + + + FS_Config.c + 1 + RTE\File_System\FS_Config.c + + + FS_Config_MC_0.h + 5 + RTE\File_System\FS_Config_MC_0.h + + + + + ::wolfSSL + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + + + ssl-dummy.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\ssl-dummy.c + + + time-STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c + + + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c + + + config-Crypt.h + 5 + RTE\wolfSSL\config-Crypt.h + + + config.h + 5 + RTE\wolfSSL\config.h + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Conf_CM.c + + + + + + + + RTE\Device\STM32F207IG\RTE_Device.h + + + + + + + + RTE\Device\STM32F207IG\startup_stm32f2xx.s + + + + + + + + RTE\Device\STM32F207IG\system_stm32f2xx.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + RTE\File_System\FS_Config_MC_0.h + + + + + + + + RTE\Network\Net_Config.c + + + + + + RTE\Network\Net_Config_BSD.h + + + + + + RTE\Network\Net_Config_DNS_Client.h + + + + + + RTE\Network\Net_Config_ETH_0.h + + + + + + RTE\Network\Net_Config_TCP.h + + + + + + RTE\Network\Net_Config_UDP.h + + + + + + RTE\Network\Net_Debug.c + + + + + + RTE\Other\config-Crypt.h + + + + + + RTE\Other\config-FS.h + + + + + + RTE\Other\config-RTX-TCP-FS.h + + + + + + RTE\Other\config.h + + + + + + RTE\wolfSSL\config-Crypt.h + + + + + + + + RTE\wolfSSL\config.h + + + + + + + + + + diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c new file mode 100644 index 000000000..31dd53c78 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/CMSIS/RTX_Conf_CM.c @@ -0,0 +1,276 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running threads <0-250> +// Defines max. number of threads that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 6 +#endif + +// Default Thread stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for threads with osThreadDef stacksz = 0 +// Default: 200 +#ifndef OS_STKSIZE + #define OS_STKSIZE 50 +#endif + +// Main Thread stack size [bytes] <64-10000:8><#/4> +// Defines stack size for main thread. +// Default: 200 +#ifndef OS_MAINSTKSIZE + #define OS_MAINSTKSIZE 2000 +#endif + +// Number of threads with user-provided stack size <0-250> +// Defines the number of threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 0 +#endif + +// Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> +// Defines the combined stack size for threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVSTKSIZE + #define OS_PRIVSTKSIZE 0 +#endif + +// Check for stack overflow +// Includes the stack checking code for stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 1 +#endif + +// + +// RTX Kernel Timer Tick Configuration +// ====================================== +// Use Cortex-M SysTick timer as RTX Kernel Timer +// Use the Cortex-M SysTick timer as a time-base for RTX. +#ifndef OS_SYSTICK + #define OS_SYSTICK 1 +#endif +// +// Timer clock value [Hz] <1-1000000000> +// Defines the timer clock value. +// Default: 12000000 (12MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 12000000 +#endif + +// Timer tick value [us] <1-1000000> +// Defines the timer tick value. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal <3=> Normal <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ 50 +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQS + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +void os_idle_demon (void) { + /* The idle demon is a system thread, running when no other thread is */ + /* ready to run. */ + + for (;;) { + /* HERE: include optional user code to be executed when no thread runs.*/ + } +} + +#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer + +/*--------------------------- os_tick_init ----------------------------------*/ + +// Initialize alternative hardware timer as RTX kernel timer +// Return: IRQ number of the alternative hardware timer +int os_tick_init (void) { + return (-1); /* Return IRQ number of timer (0..239) */ +} + +/*--------------------------- os_tick_val -----------------------------------*/ + +// Get alternative hardware timer current value (0 .. OS_TRV) +uint32_t os_tick_val (void) { + return (0); +} + +/*--------------------------- os_tick_ovf -----------------------------------*/ + +// Get alternative hardware timer overflow flag +// Return: 1 - overflow, 0 - no overflow +uint32_t os_tick_ovf (void) { + return (0); +} + +/*--------------------------- os_tick_irqack --------------------------------*/ + +// Acknowledge alternative hardware timer interrupt +void os_tick_irqack (void) { + /* ... */ +} + +#endif // (OS_SYSTICK == 0) + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (uint32_t err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/RTE_Device.h new file mode 100644 index 000000000..2648e44d4 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/RTE_Device.h @@ -0,0 +1,3127 @@ +/* ----------------------------------------------------------------------------- + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * $Date: 27. June 2013 + * $Revision: V1.01 + * + * Project: RTE Device Configuration for ST STM32F2xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + (num == 7) ? GPIOH : \ + (num == 8) ? GPIOI : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 16000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 120000000 +// AHB Clock <1-999999999> +#define RTE_HCLK 120000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 30000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 60000000 +// 48MHz Clock +#define RTE_PLL48CK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::Drivers:UART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>PA9 <1=>PB6 +#define RTE_USART1_TX_ID 0 +#if (RTE_USART1_TX_ID == 0) +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 9 +#elif (RTE_USART1_TX_ID == 1) +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>PA10 <1=>PB7 +#define RTE_USART1_RX_ID 0 +#if (RTE_USART1_RX_ID == 0) +#define RTE_USART1_RX_PORT GPIOA +#define RTE_USART1_RX_BIT 10 +#elif (RTE_USART1_RX_ID == 1) +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// Synchronous +// USART1_CK Pin <0=>PA8 +// +#define RTE_USART1_CK 0 +#define RTE_USART1_CK_ID 0 +#if (RTE_USART1_CK_ID == 0) +#define RTE_USART1_CK_PORT GPIOA +#define RTE_USART1_CK_BIT 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART1_CTS Pin <0=>PA11 +// USART1_RTS Pin <0=>PA12 +// Manual CTS/RTS +// +#define RTE_USART1_HW_FLOW 0 +#define RTE_USART1_CTS_ID 0 +#define RTE_USART1_RTS_ID 0 +#define RTE_USART1_MANUAL_FLOW 0 +#if (RTE_USART1_CTS_ID == 0) +#define RTE_USART1_CTS_PORT GPIOA +#define RTE_USART1_CTS_BIT 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif +#if (RTE_USART1_RTS_ID == 0) +#define RTE_USART1_RTS_PORT GPIOA +#define RTE_USART1_RTS_BIT 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <5=>5 +// Selects DMA Stream (only Stream 2 or 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_RX_DMA 1 +#define RTE_USART1_RX_DMA_NUMBER 2 +#define RTE_USART1_RX_DMA_STREAM 2 +#define RTE_USART1_RX_DMA_CHANNEL 4 +#define RTE_USART1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_TX_DMA 1 +#define RTE_USART1_TX_DMA_NUMBER 2 +#define RTE_USART1_TX_DMA_STREAM 7 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 + +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] +// Configuration settings for Driver_UART2 in component ::Drivers:UART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>PA2 <1=>PD5 +#define RTE_USART2_TX_ID 0 +#if (RTE_USART2_TX_ID == 0) +#define RTE_USART2_TX_PORT GPIOA +#define RTE_USART2_TX_BIT 2 +#elif (RTE_USART2_TX_ID == 1) +#define RTE_USART2_TX_PORT GPIOD +#define RTE_USART2_TX_BIT 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>PA3 <1=>PD6 +#define RTE_USART2_RX_ID 0 +#if (RTE_USART2_RX_ID == 0) +#define RTE_USART2_RX_PORT GPIOA +#define RTE_USART2_RX_BIT 3 +#elif (RTE_USART2_RX_ID == 1) +#define RTE_USART2_RX_PORT GPIOD +#define RTE_USART2_RX_BIT 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// Synchronous +// USART2_CK Pin <0=>PA4 <1=>PD7 +// +#define RTE_USART2_CK 0 +#define RTE_USART2_CK_ID 0 +#if (RTE_USART2_CK_ID == 0) +#define RTE_USART2_CK_PORT GPIOA +#define RTE_USART2_CK_BIT 4 +#elif (RTE_USART2_CK_ID == 1) +#define RTE_USART2_CK_PORT GPIOD +#define RTE_USART2_CK_BIT 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART2_CTS Pin <0=>PA0 <1=>PD3 +// USART2_RTS Pin <0=>PA1 <1=>PD4 +// Manual CTS/RTS +// +#define RTE_USART2_HW_FLOW 0 +#define RTE_USART2_CTS_ID 0 +#define RTE_USART2_RTS_ID 0 +#define RTE_USART2_MANUAL_FLOW 0 +#if (RTE_USART2_CTS_ID == 0) +#define RTE_USART2_CTS_PORT GPIOA +#define RTE_USART2_CTS_BIT 0 +#elif (RTE_USART2_CTS_ID == 1) +#define RTE_USART2_CTS_PORT GPIOD +#define RTE_USART2_CTS_BIT 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif +#if (RTE_USART2_RTS_ID == 0) +#define RTE_USART2_RTS_PORT GPIOA +#define RTE_USART2_RTS_BIT 1 +#elif (RTE_USART2_RTS_ID == 1) +#define RTE_USART2_RTS_PORT GPIOD +#define RTE_USART2_RTS_BIT 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_RX_DMA 1 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_STREAM 5 +#define RTE_USART2_RX_DMA_CHANNEL 4 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_TX_DMA 1 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_STREAM 6 +#define RTE_USART2_TX_DMA_CHANNEL 4 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] +// Configuration settings for Driver_UART3 in component ::Drivers:UART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) +#define RTE_USART3_TX_PORT GPIOB +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 1) +#define RTE_USART3_TX_PORT GPIOC +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 2) +#define RTE_USART3_TX_PORT GPIOD +#define RTE_USART3_TX_BIT 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) +#define RTE_USART3_RX_PORT GPIOB +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 1) +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 2) +#define RTE_USART3_RX_PORT GPIOD +#define RTE_USART3_RX_BIT 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// Synchronous +// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 +// +#define RTE_USART3_CK 0 +#define RTE_USART3_CK_ID 0 +#if (RTE_USART3_CK_ID == 0) +#define RTE_USART3_CK_PORT GPIOB +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 1) +#define RTE_USART3_CK_PORT GPIOC +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 2) +#define RTE_USART3_CK_PORT GPIOD +#define RTE_USART3_CK_BIT 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART3_CTS Pin <0=>PB13 <1=>PD11 +// USART3_RTS Pin <0=>PB14 <1=>PD12 +// Manual CTS/RTS +// +#define RTE_USART3_HW_FLOW 0 +#define RTE_USART3_CTS_ID 0 +#define RTE_USART3_RTS_ID 0 +#define RTE_USART3_MANUAL_FLOW 0 +#if (RTE_USART3_CTS_ID == 0) +#define RTE_USART3_CTS_PORT GPIOB +#define RTE_USART3_CTS_BIT 13 +#elif (RTE_USART3_CTS_ID == 1) +#define RTE_USART3_CTS_PORT GPIOD +#define RTE_USART3_CTS_BIT 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif +#if (RTE_USART3_RTS_ID == 0) +#define RTE_USART3_RTS_PORT GPIOB +#define RTE_USART3_RTS_BIT 14 +#elif (RTE_USART3_RTS_ID == 1) +#define RTE_USART3_RTS_PORT GPIOD +#define RTE_USART3_RTS_BIT 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_RX_DMA 1 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_STREAM 1 +#define RTE_USART3_RX_DMA_CHANNEL 4 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_TX_DMA 1 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_STREAM 3 +#define RTE_USART3_TX_DMA_CHANNEL 4 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] +// Configuration settings for Driver_UART4 in component ::Drivers:UART +#define RTE_UART4 0 + +// UART4_TX Pin <0=>PA0 <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>PA1 <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 1 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_RX_DMA 1 +#define RTE_UART4_RX_DMA_NUMBER 1 +#define RTE_UART4_RX_DMA_STREAM 2 +#define RTE_UART4_RX_DMA_CHANNEL 4 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_TX_DMA 1 +#define RTE_UART4_TX_DMA_NUMBER 1 +#define RTE_UART4_TX_DMA_STREAM 4 +#define RTE_UART4_TX_DMA_CHANNEL 4 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] +// Configuration settings for Driver_UART5 in component ::Drivers:UART +#define RTE_UART5 0 + +// UART5_TX Pin <0=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_RX_DMA 1 +#define RTE_UART5_RX_DMA_NUMBER 1 +#define RTE_UART5_RX_DMA_STREAM 0 +#define RTE_UART5_RX_DMA_CHANNEL 4 +#define RTE_UART5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_TX_DMA 1 +#define RTE_UART5_TX_DMA_NUMBER 1 +#define RTE_UART5_TX_DMA_STREAM 7 +#define RTE_UART5_TX_DMA_CHANNEL 4 +#define RTE_UART5_TX_DMA_PRIORITY 0 + +// + + +// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] +// Configuration settings for Driver_UART6 in component ::Drivers:UART +#define RTE_USART6 0 + +// USART6_TX Pin <0=>PC6 <1=>PG14 +#define RTE_USART6_TX_ID 0 +#if (RTE_USART6_TX_ID == 0) +#define RTE_USART6_TX_PORT GPIOC +#define RTE_USART6_TX_BIT 6 +#elif (RTE_USART6_TX_ID == 1) +#define RTE_USART6_TX_PORT GPIOG +#define RTE_USART6_TX_BIT 14 +#else +#error "Invalid USART6_TX Pin Configuration!" +#endif + +// USART6_RX Pin <0=>PC7 <1=>PG9 +#define RTE_USART6_RX_ID 0 +#if (RTE_USART6_RX_ID == 0) +#define RTE_USART6_RX_PORT GPIOC +#define RTE_USART6_RX_BIT 7 +#elif (RTE_USART6_RX_ID == 1) +#define RTE_USART6_RX_PORT GPIOG +#define RTE_USART6_RX_BIT 9 +#else +#error "Invalid USART6_RX Pin Configuration!" +#endif + +// Synchronous +// USART6_CK Pin <0=>PC8 <1=>PG7 +// +#define RTE_USART6_CK 0 +#define RTE_USART6_CK_ID 0 +#if (RTE_USART6_CK_ID == 0) +#define RTE_USART6_CK_PORT GPIOC +#define RTE_USART6_CK_BIT 8 +#elif (RTE_USART6_CK_ID == 1) +#define RTE_USART6_CK_PORT GPIOG +#define RTE_USART6_CK_BIT 7 +#else +#error "Invalid USART6_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART6_CTS Pin <0=>PG13 <1=>PG15 +// USART6_RTS Pin <0=>PG8 <1=>PG12 +// Manual CTS/RTS +// +#define RTE_USART6_HW_FLOW 0 +#define RTE_USART6_CTS_ID 0 +#define RTE_USART6_RTS_ID 0 +#define RTE_USART6_MANUAL_FLOW 0 +#if (RTE_USART6_CTS_ID == 0) +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 13 +#elif (RTE_USART6_CTS_ID == 1) +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 15 +#else +#error "Invalid USART6_CTS Pin Configuration!" +#endif +#if (RTE_USART6_RTS_ID == 0) +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 8 +#elif (RTE_USART6_RTS_ID == 1) +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 12 +#else +#error "Invalid USART6_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_RX_DMA 1 +#define RTE_USART6_RX_DMA_NUMBER 2 +#define RTE_USART6_RX_DMA_STREAM 1 +#define RTE_USART6_RX_DMA_CHANNEL 5 +#define RTE_USART6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_TX_DMA 1 +#define RTE_USART6_TX_DMA_NUMBER 2 +#define RTE_USART6_TX_DMA_STREAM 6 +#define RTE_USART6_TX_DMA_CHANNEL 5 +#define RTE_USART6_TX_DMA_PRIORITY 0 + +// + + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 <1=>PB8 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 <1=>PB9 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 9 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 1 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_STREAM 0 +#define RTE_I2C1_RX_DMA_CHANNEL 1 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 1 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_STREAM 6 +#define RTE_I2C1_TX_DMA_CHANNEL 1 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 0 + +// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOF +#define RTE_I2C2_SCL_BIT 1 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT GPIOH +#define RTE_I2C2_SCL_BIT 4 +#elif (RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOF +#define RTE_I2C2_SDA_BIT 0 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT GPIOH +#define RTE_I2C2_SDA_BIT 5 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 <3=>3 +// Selects DMA Stream (only Stream 2 or 3 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_STREAM 2 +#define RTE_I2C2_RX_DMA_CHANNEL 7 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_STREAM 7 +#define RTE_I2C2_TX_DMA_CHANNEL 7 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C +#define RTE_I2C3 0 + +// I2C3_SCL Pin <0=>PH7 <1=>PA8 +#define RTE_I2C3_SCL_PORT_ID 0 +#if (RTE_I2C3_SCL_PORT_ID == 0) +#define RTE_I2C3_SCL_PORT GPIOH +#define RTE_I2C3_SCL_BIT 7 +#elif (RTE_I2C3_SCL_PORT_ID == 1) +#define RTE_I2C3_SCL_PORT GPIOA +#define RTE_I2C3_SCL_BIT 8 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// I2C3_SDA Pin <0=>PH8 <1=>PC9 +#define RTE_I2C3_SDA_PORT_ID 0 +#if (RTE_I2C3_SDA_PORT_ID == 0) +#define RTE_I2C3_SDA_PORT GPIOH +#define RTE_I2C3_SDA_BIT 8 +#elif (RTE_I2C3_SDA_PORT_ID == 1) +#define RTE_I2C3_SDA_PORT GPIOC +#define RTE_I2C3_SDA_BIT 9 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_RX_DMA 1 +#define RTE_I2C3_RX_DMA_NUMBER 1 +#define RTE_I2C3_RX_DMA_STREAM 2 +#define RTE_I2C3_RX_DMA_CHANNEL 3 +#define RTE_I2C3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_TX_DMA 1 +#define RTE_I2C3_TX_DMA_NUMBER 1 +#define RTE_I2C3_TX_DMA_STREAM 4 +#define RTE_I2C3_TX_DMA_CHANNEL 3 +#define RTE_I2C3_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 <1=>PB3 +#define RTE_SPI1_SCL_PORT_ID 0 +#if (RTE_SPI1_SCL_PORT_ID == 0) +#define RTE_SPI1_SCL_PORT GPIOA +#define RTE_SPI1_SCL_BIT 5 +#elif (RTE_SPI1_SCL_PORT_ID == 1) +#define RTE_SPI1_SCL_PORT GPIOB +#define RTE_SPI1_SCL_BIT 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>PA6 <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID 0 +#if (RTE_SPI1_MISO_PORT_ID == 0) +#define RTE_SPI1_MISO_PORT GPIOA +#define RTE_SPI1_MISO_BIT 6 +#elif (RTE_SPI1_MISO_PORT_ID == 1) +#define RTE_SPI1_MISO_PORT GPIOB +#define RTE_SPI1_MISO_BIT 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>PA7 <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID 0 +#if (RTE_SPI1_MOSI_PORT_ID == 0) +#define RTE_SPI1_MOSI_PORT GPIOA +#define RTE_SPI1_MOSI_BIT 7 +#elif (RTE_SPI1_MOSI_PORT_ID == 1) +#define RTE_SPI1_MOSI_PORT GPIOB +#define RTE_SPI1_MOSI_BIT 5 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 1 +#define RTE_SPI1_RX_DMA_NUMBER 2 +#define RTE_SPI1_RX_DMA_STREAM 0 +#define RTE_SPI1_RX_DMA_CHANNEL 3 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 1 +#define RTE_SPI1_TX_DMA_NUMBER 2 +#define RTE_SPI1_TX_DMA_STREAM 5 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 +#define RTE_SPI2_SCL_PORT_ID 0 +#if (RTE_SPI2_SCL_PORT_ID == 0) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 10 +#elif (RTE_SPI2_SCL_PORT_ID == 1) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 13 +#elif (RTE_SPI2_SCL_PORT_ID == 2) +#define RTE_SPI2_SCL_PORT GPIOI +#define RTE_SPI2_SCL_BIT 1 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO_PORT GPIOC +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 2) +#define RTE_SPI2_MISO_PORT GPIOI +#define RTE_SPI2_MISO_BIT 2 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 2) +#define RTE_SPI2_MOSI_PORT GPIOI +#define RTE_SPI2_MOSI_BIT 3 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 1 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_STREAM 2 +#define RTE_SPI2_RX_DMA_CHANNEL 0 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 1 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_STREAM 3 +#define RTE_SPI2_TX_DMA_CHANNEL 0 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 <1=>PC10 +#define RTE_SPI3_SCL_PORT_ID 0 +#if (RTE_SPI3_SCL_PORT_ID == 0) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 3 +#elif (RTE_SPI3_SCL_PORT_ID == 1) +#define RTE_SPI3_SCL_PORT GPIOC +#define RTE_SPI3_SCL_BIT 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>PB4 <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID 0 +#if (RTE_SPI3_MISO_PORT_ID == 0) +#define RTE_SPI3_MISO_PORT GPIOB +#define RTE_SPI3_MISO_BIT 4 +#elif (RTE_SPI3_MISO_PORT_ID == 1) +#define RTE_SPI3_MISO_PORT GPIOC +#define RTE_SPI3_MISO_BIT 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI Pin <0=>PB5 <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID 0 +#if (RTE_SPI3_MOSI_PORT_ID == 0) +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 5 +#elif (RTE_SPI3_MOSI_PORT_ID == 1) +#define RTE_SPI3_MOSI_PORT GPIOC +#define RTE_SPI3_MOSI_BIT 12 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 1 +#define RTE_SPI3_RX_DMA_NUMBER 1 +#define RTE_SPI3_RX_DMA_STREAM 0 +#define RTE_SPI3_RX_DMA_CHANNEL 0 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 1 +#define RTE_SPI3_TX_DMA_NUMBER 1 +#define RTE_SPI3_TX_DMA_STREAM 5 +#define RTE_SPI3_TX_DMA_CHANNEL 0 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::Drivers:MCI +#define RTE_SDIO 1 + +// SDIO_CD (Card Detect) Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_PIN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(7) +#define RTE_SDIO_CD_BIT 15 + +// SDIO_WP (Write Protect) Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_PIN 0 +#define RTE_SDIO_WP_ACTIVE 0 +#define RTE_SDIO_WP_PORT GPIO_PORT(7) +#define RTE_SDIO_WP_BIT 16 + +// SDIO Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) +#define RTE_SDIO_CK_PORT GPIOC +#define RTE_SDIO_CK_PIN 12 +#else +#error "Invalid SDIO_CK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) +#define RTE_SDIO_CMD_PORT GPIOD +#define RTE_SDIO_CMD_PIN 2 +#else +#error "Invalid SDIO_CDM Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) +#define RTE_SDIO_D0_PORT GPIOC +#define RTE_SDIO_D0_PIN 8 +#else +#error "Invalid SDIO_D0 Pin Configuration!" +#endif +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) +#define RTE_SDIO_D1_PORT GPIOC +#define RTE_SDIO_D1_PIN 9 +#else +#error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) +#define RTE_SDIO_D2_PORT GPIOC +#define RTE_SDIO_D2_PIN 10 +#else +#error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) +#define RTE_SDIO_D3_PORT GPIOC +#define RTE_SDIO_D3_PIN 11 +#else +#error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) +#define RTE_SDIO_D4_PORT GPIOB +#define RTE_SDIO_D4_PIN 8 +#else +#error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) +#define RTE_SDIO_D5_PORT GPIOB +#define RTE_SDIO_D5_PIN 9 +#else +#error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) +#define RTE_SDIO_D6_PORT GPIOC +#define RTE_SDIO_D6_PIN 6 +#else +#error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) +#define RTE_SDIO_D7_PORT GPIOC +#define RTE_SDIO_D7_PIN 7 +#else +#error "Invalid SDIO_D7 Pin Configuration!" +#endif +// + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA 1 +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_STREAM 3 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) +#define RTE_ETH_MII_TXD0_PORT GPIOG +#define RTE_ETH_MII_TXD0_PIN 13 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) +#define RTE_ETH_MII_TXD1_PORT GPIOG +#define RTE_ETH_MII_TXD1_PIN 14 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) +#define RTE_ETH_MII_TXD3_PORT GPIOE +#define RTE_ETH_MII_TXD3_PIN 2 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) +#define RTE_ETH_MII_TX_EN_PORT GPIOG +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_PORT_ID 0 +#if (RTE_ETH_MII_RXD0_PORT_ID == 0) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_PORT_ID 0 +#if (RTE_ETH_MII_RXD1_PORT_ID == 0) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif +// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 +#define RTE_ETH_MII_RXD2_PORT_ID 0 +#if (RTE_ETH_MII_RXD2_PORT_ID == 0) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) +#define RTE_ETH_MII_RXD2_PORT GPIOH +#define RTE_ETH_MII_RXD2_PIN 6 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 +#define RTE_ETH_MII_RXD3_PORT_ID 0 +#if (RTE_ETH_MII_RXD3_PORT_ID == 0) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RXD3_PORT GPIOH +#define RTE_ETH_MII_RXD3_PIN 7 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_PORT_ID 0 +#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif +// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RX_ER_PORT GPIOI +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#elif (RTE_ETH_MII_CRS_PORT_ID == 1) +#define RTE_ETH_MII_CRS_PORT GPIOH +#define RTE_ETH_MII_CRS_PIN 2 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 <1=>PH3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#elif (RTE_ETH_MII_COL_PORT_ID == 1) +#define RTE_ETH_MII_COL_PORT GPIOH +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 1 + +// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_RMII_TXD0_PORT_ID 1 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) +#define RTE_ETH_RMII_TXD0_PORT GPIOG +#define RTE_ETH_RMII_TXD0_PIN 13 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_RMII_TXD1_PORT_ID 1 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) +#define RTE_ETH_RMII_TXD1_PORT GPIOG +#define RTE_ETH_RMII_TXD1_PIN 14 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 1 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) +#define RTE_ETH_RMII_TX_EN_PORT GPIOG +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_PORT_ID 0 +#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_PORT_ID 0 +#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 +#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz/50MHz Clock generation +#define RTE_ETH_REF_CLOCK 0 + +// MCO Pin <0=>PA2 <1=>PC9 +#define RTE_ETH_REF_CLOCK_PORT_ID 0 +#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) +#define RTE_ETH_REF_CLOCK_PORT GPIOA +#define RTE_ETH_REF_CLOCK_PIN 8 +#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) +#define RTE_ETH_REF_CLOCK_PORT GPIOC +#define RTE_ETH_REF_CLOCK_PIN 9 +#else +#error "Invalid MCO Pin Configuration!" +#endif + +// + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_OTG_FS_DEV 1 + +// Endpoints +// Reduce memory requirements of Driver by disabling unused endpoints +// Endpoint 1 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 2 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 3 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// +#define RTE_USB_OTG_FS_DEV_EP 0x0000000F +#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E +#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E +#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E + +// + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 1 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) +#define RTE_OTG_FS_VBUS_BIT 5 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_FS_OC_BIT 11 +// + +// + + +// USB OTG High-speed +#define RTE_USB_OTG_HS 0 + +// PHY (Physical Layer) + +// PHY Interface +// <0=>On-chip full-speed PHY +// <1=>External ULPI high-speed PHY +#define RTE_USB_OTG_HS_PHY 1 + +// External ULPI Pins (UTMI+ Low Pin Interface) + +// OTG_HS_ULPI_CK Pin <0=>PA5 +#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" +#endif +// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 +#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 +#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 +#else +#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" +#endif +// OTG_HS_ULPI_STP Pin <0=>PC0 +#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" +#endif +// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 +#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 +#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 +#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 +#else +#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" +#endif +// OTG_HS_ULPI_D0 Pin <0=>PA3 +#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 +#else +#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" +#endif +// OTG_HS_ULPI_D1 Pin <0=>PB0 +#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" +#endif +// OTG_HS_ULPI_D2 Pin <0=>PB1 +#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 +#else +#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" +#endif +// OTG_HS_ULPI_D3 Pin <0=>PB10 +#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 +#else +#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" +#endif +// OTG_HS_ULPI_D4 Pin <0=>PB11 +#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 +#else +#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" +#endif +// OTG_HS_ULPI_D5 Pin <0=>PB12 +#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 +#else +#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" +#endif +// OTG_HS_ULPI_D6 Pin <0=>PB13 +#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 +#else +#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" +#endif +// OTG_HS_ULPI_D7 Pin <0=>PB5 +#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" +#endif + +// + +// + +// Device [Driver_USBD1] +// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device +#define RTE_USB_OTG_HS_DEV 1 + +// Endpoints +// Reduce memory requirements of Driver by disabling unused endpoints +// Endpoint 1 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 2 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 3 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 4 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 5 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// +#define RTE_USB_OTG_HS_DEV_EP 0x0000003F +#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E +#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E +#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E + +// + +// Host [Driver_USBH1] +// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host +#define RTE_USB_OTG_HS_HOST 1 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_VBUS_PIN 1 +#define RTE_OTG_HS_VBUS_ACTIVE 0 +#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_HS_VBUS_BIT 2 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_OC_PIN 1 +#define RTE_OTG_HS_OC_ACTIVE 0 +#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_HS_OC_BIT 12 +// + +// + + +// EXTI (External Interrupt/Event Controller) +#define RTE_EXTI 0 + +// EXTI0 Line +#define RTE_EXTI0 0 +// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 +#define RTE_EXTI0_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI0_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI0_TRIGGER 0 +// + +// EXTI1 Line +#define RTE_EXTI1 0 +// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 +#define RTE_EXTI1_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI1_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI1_TRIGGER 0 +// + +// EXTI2 Line +#define RTE_EXTI2 0 +// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 +#define RTE_EXTI2_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI2_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI2_TRIGGER 0 +// + +// EXTI3 Line +#define RTE_EXTI3 0 +// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 +#define RTE_EXTI3_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI3_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI3_TRIGGER 0 +// + +// EXTI4 Line +#define RTE_EXTI4 0 +// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 +#define RTE_EXTI4_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI4_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI4_TRIGGER 0 +// + +// EXTI5 Line +#define RTE_EXTI5 0 +// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 +#define RTE_EXTI5_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI5_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI5_TRIGGER 0 +// + +// EXTI6 Line +#define RTE_EXTI6 0 +// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 +#define RTE_EXTI6_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI6_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI6_TRIGGER 0 +// + +// EXTI7 Line +#define RTE_EXTI7 0 +// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 +#define RTE_EXTI7_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI7_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI7_TRIGGER 0 +// + +// EXTI8 Line +#define RTE_EXTI8 0 +// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 +#define RTE_EXTI8_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI8_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI8_TRIGGER 0 +// + +// EXTI9 Line +#define RTE_EXTI9 0 +// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 +#define RTE_EXTI9_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI9_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI9_TRIGGER 0 +// + +// EXTI10 Line +#define RTE_EXTI10 0 +// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 +#define RTE_EXTI10_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI10_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI10_TRIGGER 0 +// + +// EXTI11 Line +#define RTE_EXTI11 0 +// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 +#define RTE_EXTI11_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI11_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI11_TRIGGER 0 +// + +// EXTI12 Line +#define RTE_EXTI12 0 +// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 +#define RTE_EXTI12_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI12_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI12_TRIGGER 0 +// + +// EXTI13 Line +#define RTE_EXTI13 0 +// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 +#define RTE_EXTI13_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI13_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI13_TRIGGER 0 +// + +// EXTI14 Line +#define RTE_EXTI14 0 +// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 +#define RTE_EXTI14_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI14_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI14_TRIGGER 0 +// + +// EXTI15 Line +#define RTE_EXTI15 0 +// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 +#define RTE_EXTI15_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI15_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI15_TRIGGER 0 +// + +// EXTI16 Line: PVD Output +#define RTE_EXTI16 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI16_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI16_TRIGGER 0 +// + +// EXTI17 Line: RTC Alarm +#define RTE_EXTI17 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI17_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI17_TRIGGER 0 +// + +// EXTI18 Line: USB OTG FS Wakeup +#define RTE_EXTI18 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI18_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI18_TRIGGER 0 +// + +// EXTI19 Line: Ethernet Wakeup +#define RTE_EXTI19 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI19_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI19_TRIGGER 0 +// + +// EXTI20 Line: USB OTG HS Wakeup +#define RTE_EXTI20 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI20_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI20_TRIGGER 0 +// + +// EXTI21 Line: RTC Tamper and TimeStamp +#define RTE_EXTI21 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI21_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI21_TRIGGER 0 +// + +// EXTI22 Line: RTC Wakeup +#define RTE_EXTI22 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI22_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI22_TRIGGER 0 +// + +// + + +// FSMC (Flexible Static Memory Controller) +#define RTE_FSMC 0 + +// Pin Configuration +// Configure Pins +#define RTE_FSMC_PINS 0 + +// Address Bus Pins +// <0=>A[17:16] +// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] +// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] +// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] +#define RTE_FSMC_ABUS_PINS 10 +// Data Bus Pins <0=>D[7:0] <1=>D[15:0] +#define RTE_FSMC_DBUS_PINS 0 +// FSMC_NOE Pin +#define RTE_FSMC_NOE_PIN 0 +// FSMC_NWE Pin +#define RTE_FSMC_NWE_PIN 0 +// FSMC_NBL0 Pin +#define RTE_FSMC_NBL0_PIN 0 +// FSMC_NBL1 Pin +#define RTE_FSMC_NBL1_PIN 0 +// FSMC_NL Pin +#define RTE_FSMC_NL_PIN 0 +// FSMC_NWAIT Pin +#define RTE_FSMC_NWAIT_PIN 0 +// FSMC_CLK Pin +#define RTE_FSMC_CLK_PIN 0 +// FSMC_NE1/NCE2 Pin +#define RTE_FSMC_NE1_PIN 0 +// FSMC_NE2/NCE3 Pin +#define RTE_FSMC_NE2_PIN 0 +// FSMC_NE3/NCE4_1 Pin +#define RTE_FSMC_NE3_PIN 0 +// FSMC_NE4 Pin +#define RTE_FSMC_NE4_PIN 0 +// FSMC_NCE4_2 Pin +#define RTE_FSMC_NCE42_PIN 0 +// FSMC_INT2 Pin +#define RTE_FSMC_INT2_PIN 0 +// FSMC_INT3 Pin +#define RTE_FSMC_INT3_PIN 0 +// FSMC_INTR Pin +#define RTE_FSMC_INTR_PIN 0 +// FSMC_NIORD Pin +#define RTE_FSMC_NIORD_PIN 0 +// FSMC_NIOWR Pin +#define RTE_FSMC_NIOWR_PIN 0 +// FSMC_NREG Pin +#define RTE_FSMC_NREG_PIN 0 +// FSMC_CD Pin +#define RTE_FSMC_CD_PIN 0 + +// + +// NOR Flash / PSRAM Controller + +// FSMC_NE1 Chip Select +// Configure Device on Chip Select FSMC_NE1 +#define RTE_FSMC_NE1 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR1_CBURSTRW 0 +#define RTE_FSMC_BCR1_ASYNCWAIT 0 +#define RTE_FSMC_BCR1_EXTMOD 0 +#define RTE_FSMC_BCR1_WAITEN 1 +#define RTE_FSMC_BCR1_WREN 1 +#define RTE_FSMC_BCR1_WAITCFG 0 +#define RTE_FSMC_BCR1_WRAPMOD 0 +#define RTE_FSMC_BCR1_WAITPOL 0 +#define RTE_FSMC_BCR1_BURSTEN 0 +#define RTE_FSMC_BCR1_FACCEN 1 +#define RTE_FSMC_BCR1_MWID 1 +#define RTE_FSMC_BCR1_MTYP 2 +#define RTE_FSMC_BCR1_MUXEN 1 +#define RTE_FSMC_BCR1_MBKEN 1 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR1_ACCMOD 0 +#define RTE_FSMC_BTR1_DATLAT 15 +#define RTE_FSMC_BTR1_CLKDIV 15 +#define RTE_FSMC_BTR1_BUSTURN 15 +#define RTE_FSMC_BTR1_DATAST 255 +#define RTE_FSMC_BTR1_ADDHLD 15 +#define RTE_FSMC_BTR1_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR1_ACCMOD 0 +#define RTE_FSMC_BWTR1_DATLAT 15 +#define RTE_FSMC_BWTR1_CLKDIV 15 +#define RTE_FSMC_BWTR1_BUSTURN 15 +#define RTE_FSMC_BWTR1_DATAST 255 +#define RTE_FSMC_BWTR1_ADDHLD 15 +#define RTE_FSMC_BWTR1_ADDSET 15 +// +// + +// FSMC_NE2 Chip Select +// Configure Device on Chip Select FSMC_NE2 +#define RTE_FSMC_NE2 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR2_CBURSTRW 0 +#define RTE_FSMC_BCR2_ASYNCWAIT 0 +#define RTE_FSMC_BCR2_EXTMOD 0 +#define RTE_FSMC_BCR2_WAITEN 1 +#define RTE_FSMC_BCR2_WREN 1 +#define RTE_FSMC_BCR2_WAITCFG 0 +#define RTE_FSMC_BCR2_WRAPMOD 0 +#define RTE_FSMC_BCR2_WAITPOL 0 +#define RTE_FSMC_BCR2_BURSTEN 0 +#define RTE_FSMC_BCR2_FACCEN 1 +#define RTE_FSMC_BCR2_MWID 1 +#define RTE_FSMC_BCR2_MTYP 0 +#define RTE_FSMC_BCR2_MUXEN 1 +#define RTE_FSMC_BCR2_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR2_ACCMOD 0 +#define RTE_FSMC_BTR2_DATLAT 15 +#define RTE_FSMC_BTR2_CLKDIV 15 +#define RTE_FSMC_BTR2_BUSTURN 15 +#define RTE_FSMC_BTR2_DATAST 255 +#define RTE_FSMC_BTR2_ADDHLD 15 +#define RTE_FSMC_BTR2_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR2_ACCMOD 0 +#define RTE_FSMC_BWTR2_DATLAT 15 +#define RTE_FSMC_BWTR2_CLKDIV 15 +#define RTE_FSMC_BWTR2_BUSTURN 15 +#define RTE_FSMC_BWTR2_DATAST 255 +#define RTE_FSMC_BWTR2_ADDHLD 15 +#define RTE_FSMC_BWTR2_ADDSET 15 +// +// + +// FSMC_NE3 Chip Select +// Configure Device on Chip Select FSMC_NE3 +#define RTE_FSMC_NE3 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR3_CBURSTRW 0 +#define RTE_FSMC_BCR3_ASYNCWAIT 0 +#define RTE_FSMC_BCR3_EXTMOD 0 +#define RTE_FSMC_BCR3_WAITEN 1 +#define RTE_FSMC_BCR3_WREN 1 +#define RTE_FSMC_BCR3_WAITCFG 0 +#define RTE_FSMC_BCR3_WRAPMOD 0 +#define RTE_FSMC_BCR3_WAITPOL 0 +#define RTE_FSMC_BCR3_BURSTEN 0 +#define RTE_FSMC_BCR3_FACCEN 1 +#define RTE_FSMC_BCR3_MWID 1 +#define RTE_FSMC_BCR3_MTYP 0 +#define RTE_FSMC_BCR3_MUXEN 1 +#define RTE_FSMC_BCR3_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR3_ACCMOD 0 +#define RTE_FSMC_BTR3_DATLAT 15 +#define RTE_FSMC_BTR3_CLKDIV 15 +#define RTE_FSMC_BTR3_BUSTURN 15 +#define RTE_FSMC_BTR3_DATAST 255 +#define RTE_FSMC_BTR3_ADDHLD 15 +#define RTE_FSMC_BTR3_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR3_ACCMOD 0 +#define RTE_FSMC_BWTR3_DATLAT 15 +#define RTE_FSMC_BWTR3_CLKDIV 15 +#define RTE_FSMC_BWTR3_BUSTURN 15 +#define RTE_FSMC_BWTR3_DATAST 255 +#define RTE_FSMC_BWTR3_ADDHLD 15 +#define RTE_FSMC_BWTR3_ADDSET 15 +// +// + +// FSMC_NE4 Chip Select +// Configure Device on Chip Select FSMC_NE4 +#define RTE_FSMC_NE4 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR4_CBURSTRW 0 +#define RTE_FSMC_BCR4_ASYNCWAIT 0 +#define RTE_FSMC_BCR4_EXTMOD 0 +#define RTE_FSMC_BCR4_WAITEN 1 +#define RTE_FSMC_BCR4_WREN 1 +#define RTE_FSMC_BCR4_WAITCFG 0 +#define RTE_FSMC_BCR4_WRAPMOD 0 +#define RTE_FSMC_BCR4_WAITPOL 0 +#define RTE_FSMC_BCR4_BURSTEN 0 +#define RTE_FSMC_BCR4_FACCEN 1 +#define RTE_FSMC_BCR4_MWID 1 +#define RTE_FSMC_BCR4_MTYP 0 +#define RTE_FSMC_BCR4_MUXEN 1 +#define RTE_FSMC_BCR4_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR4_ACCMOD 0 +#define RTE_FSMC_BTR4_DATLAT 15 +#define RTE_FSMC_BTR4_CLKDIV 15 +#define RTE_FSMC_BTR4_BUSTURN 15 +#define RTE_FSMC_BTR4_DATAST 255 +#define RTE_FSMC_BTR4_ADDHLD 15 +#define RTE_FSMC_BTR4_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR4_ACCMOD 0 +#define RTE_FSMC_BWTR4_DATLAT 15 +#define RTE_FSMC_BWTR4_CLKDIV 15 +#define RTE_FSMC_BWTR4_BUSTURN 15 +#define RTE_FSMC_BWTR4_DATAST 255 +#define RTE_FSMC_BWTR4_ADDHLD 15 +#define RTE_FSMC_BWTR4_ADDSET 15 +// +// + +// + +// NAND Flash Controller + +// FSMC_NCE2 Chip Select +// Configure NAND Device on Chip Select FSMC_NCE2 +#define RTE_FSMC_NCE2 0 + +// NAND Flash Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <1=>NAND Flash +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: NAND Flash memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR2_ECCPS 0 +#define RTE_FSMC_PCR2_TAR 0 +#define RTE_FSMC_PCR2_TCLR 0 +#define RTE_FSMC_PCR2_ECCEN 0 +#define RTE_FSMC_PCR2_PWID 0 +#define RTE_FSMC_PCR2_PTYP 1 +#define RTE_FSMC_PCR2_PBKEN 0 +#define RTE_FSMC_PCR2_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR2_IFEN 0 +#define RTE_FSMC_SR2_ILEN 0 +#define RTE_FSMC_SR2_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM2_MEMHIZ 255 +#define RTE_FSMC_PMEM2_MEMHOLD 255 +#define RTE_FSMC_PMEM2_MEMWAIT 255 +#define RTE_FSMC_PMEM2_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT2_ATTHIZ 255 +#define RTE_FSMC_PATT2_ATTHOLD 255 +#define RTE_FSMC_PATT2_ATTWAIT 255 +#define RTE_FSMC_PATT2_ATTSET 255 + +// + +// + +// FSMC_NCE3 Chip Select +// Configure NAND Device on Chip Select FSMC_NCE3 +#define RTE_FSMC_NCE3 0 + +// NAND Flash Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <1=>NAND Flash +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: NAND Flash memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR3_ECCPS 0 +#define RTE_FSMC_PCR3_TAR 0 +#define RTE_FSMC_PCR3_TCLR 0 +#define RTE_FSMC_PCR3_ECCEN 0 +#define RTE_FSMC_PCR3_PWID 0 +#define RTE_FSMC_PCR3_PTYP 1 +#define RTE_FSMC_PCR3_PBKEN 0 +#define RTE_FSMC_PCR3_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR3_IFEN 0 +#define RTE_FSMC_SR3_ILEN 0 +#define RTE_FSMC_SR3_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM3_MEMHIZ 255 +#define RTE_FSMC_PMEM3_MEMHOLD 255 +#define RTE_FSMC_PMEM3_MEMWAIT 255 +#define RTE_FSMC_PMEM3_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT3_ATTHIZ 255 +#define RTE_FSMC_PATT3_ATTHOLD 255 +#define RTE_FSMC_PATT3_ATTWAIT 255 +#define RTE_FSMC_PATT3_ATTSET 255 + +// + +// + +// + +// PC Card Controller + +// FSMC_NCE4_x Chip Select +// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 +#define RTE_FSMC_NCE4 0 + +// PC Card Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: PC Card memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR4_ECCPS 0 +#define RTE_FSMC_PCR4_TAR 0 +#define RTE_FSMC_PCR4_TCLR 0 +#define RTE_FSMC_PCR4_ECCEN 0 +#define RTE_FSMC_PCR4_PWID 0 +#define RTE_FSMC_PCR4_PTYP 0 +#define RTE_FSMC_PCR4_PBKEN 0 +#define RTE_FSMC_PCR4_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR4_IFEN 0 +#define RTE_FSMC_SR4_ILEN 0 +#define RTE_FSMC_SR4_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM4_MEMHIZ 255 +#define RTE_FSMC_PMEM4_MEMHOLD 255 +#define RTE_FSMC_PMEM4_MEMWAIT 255 +#define RTE_FSMC_PMEM4_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT4_ATTHIZ 255 +#define RTE_FSMC_PATT4_ATTHOLD 255 +#define RTE_FSMC_PATT4_ATTWAIT 255 +#define RTE_FSMC_PATT4_ATTSET 255 + +// + +// I/O space timing +// IOHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a PC Card write access. Only valid for write transaction. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// IOHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for PC Card read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// IOWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, +// SMNOE), for PC Card read or write access. The duration for command assertion is +// extended if the wait signal (NWAIT) is active (low) at the end of the +// programmed value of HCLK. +// 0000 0000: reserved, do not use this value +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles +// IOSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for PC Card read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PIO4_IOHIZ 255 +#define RTE_FSMC_PIO4_IOHOLD 255 +#define RTE_FSMC_PIO4_IOWAIT 255 +#define RTE_FSMC_PIO4_IOSET 255 + +// + +// + +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s new file mode 100644 index 000000000..c31ce1991 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/startup_stm32f2xx.s @@ -0,0 +1,419 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 18-April-2011 +;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00009000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c new file mode 100644 index 000000000..da0e189c8 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/Device/STM32F207IG/system_stm32f2xx.c @@ -0,0 +1,536 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-April-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c new file mode 100644 index 000000000..78564b080 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config.c @@ -0,0 +1,72 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config.c + * Purpose: File System Configuration + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// File System +// Define File System global parameters + +// Number of open files <4-16> +// Define number of files that can be +// opened at the same time. +// Default: 8 +#define NUM_FILES 8 + +// FAT Name Cache Size <0-1000000> +// Define number of cached FAT file or directory names. +// 48 bytes of RAM is required for each cached name. +#define FAT_NAME_CACHE_SIZE 0 + +// Relocate FAT Name Cache Buffer +// Locate Cache Buffer at a specific address. +#define FAT_NAME_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +#define FAT_NAME_CACHE_ADDR 0x60000000 + +// + +// + +#include "..\RTE_Components.h" + +#ifdef RTE_FileSystem_Drive_RAM +#include "FS_Config_RAM.h" +#endif + +#ifdef RTE_FileSystem_Drive_NOR_0 +#include "FS_Config_NOR_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NOR_1 +#include "FS_Config_NOR_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NAND_0 +#include "FS_Config_NAND_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NAND_1 +#include "FS_Config_NAND_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_MC_0 +#include "FS_Config_MC_0.h" +#endif +#ifdef RTE_FileSystem_Drive_MC_1 +#include "FS_Config_MC_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_USB_0 +#include "FS_Config_USB_0.h" +#endif +#ifdef RTE_FileSystem_Drive_USB_1 +#include "FS_Config_USB_1.h" +#endif + +#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h new file mode 100644 index 000000000..0b1c6d3a7 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/File_System/FS_Config_MC_0.h @@ -0,0 +1,57 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System:Drive + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config_MC_0.h + * Purpose: File System Configuration for Memory Card Drive + * Rev.: V5.01 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Memory Card Drive 0 +// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" +#define MC0_ENABLE 1 + +// Connect to hardware via Driver_MCI# <0-255> +// Select driver control block for hardware interface +#define MC0_MCI_DRIVER 0 + +// Connect to hardware via Driver_SPI# <0-255> +// Select driver control block for hardware interface when in SPI mode +#define MC0_SPI_DRIVER 0 + +// Memory Card Interface Mode <0=>Native <1=>SPI +// Native uses a SD Bus with up to 8 data lines, CLK, and CMD +// SPI uses 2 data lines (MOSI and MISO), SCLK and CS +// When using SPI both Driver_SPI# and Driver_MCI# must be specified +// since the MCI driver provides the control interface lines. +#define MC0_SPI 0 + +// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Drive Cache stores data sectors and may be increased to speed-up +// file read/write operations on this drive (default: 4 KB) +#define MC0_CACHE_SIZE 4 + +// Locate Drive Cache and Drive Buffer +// Some microcontrollers support DMA only in specific memory areas and +// require to locate the drive buffers at a fixed address. +#define MC0_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Set buffer base address to RAM areas that support DMA with the drive. +#define MC0_CACHE_ADDR 0x7FD00000 + +// + +// Use FAT Journal +// Protect File Allocation Table and Directory Entries for +// fail-safe operation. +#define MC0_FAT_JOURNAL 0 + +// Default Drive "M0:" +// Use this drive when no drive letter is specified. +#define MC0_DEFAULT_DRIVE 1 + +// diff --git a/IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h new file mode 100644 index 000000000..4d1a63720 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/RTE/RTE_Components.h @@ -0,0 +1,19 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'CryptTest' + * Target: 'CryptTest' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ +#define RTE_Drivers_MCI0 /* Driver MCI0 */ +#define RTE_FileSystem_Core /* File System Core */ + #define RTE_FileSystem_LFN /* File System with Long Filename support */ +#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini new file mode 100644 index 000000000..239abce37 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini @@ -0,0 +1,36 @@ +/******************************************************************************/ +/* STM32_SWO.ini: STM32 Debugger Initialization File */ +/******************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> // +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + + +FUNC void DebugSetup (void) { +// Debug MCU Configuration +// DBG_SLEEP Debug Sleep Mode +// DBG_STOP Debug Stop Mode +// DBG_STANDBY Debug Standby Mode +// TRACE_IOEN Trace I/O Enable +// TRACE_MODE Trace Mode +// <0=> Asynchronous +// <1=> Synchronous: TRACEDATA Size 1 +// <2=> Synchronous: TRACEDATA Size 2 +// <3=> Synchronous: TRACEDATA Size 4 +// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted +// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted +// DBG_TIM1_STOP Timer 1 Stopped when Core is halted +// DBG_TIM2_STOP Timer 2 Stopped when Core is halted +// DBG_TIM3_STOP Timer 3 Stopped when Core is halted +// DBG_TIM4_STOP Timer 4 Stopped when Core is halted +// DBG_CAN_STOP CAN Stopped when Core is halted +// + _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR +} + +DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/CryptTest/main.c b/IDE/MDK5-ARM/Projects/CryptTest/main.c new file mode 100644 index 000000000..a0dd1aa3f --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/main.c @@ -0,0 +1,71 @@ +/* main.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include +#include + +#include "cmsis_os.h" +#include "rl_fs.h" + +#include + +/*----------------------------------------------------------------------------- + * Initialize a Flash Memory Card + *----------------------------------------------------------------------------*/ +static void init_filesystem (void) { + int32_t retv; + + retv = finit ("M0:"); + if (retv == 0) { + retv = fmount ("M0:"); + if (retv == 0) { + printf ("Drive M0 ready!\n"); + } + else { + printf ("Drive M0 mount failed!\n"); + } + } + else { + printf ("Drive M0 initialization failed!\n"); + } +} +extern void ctaocrypt_test(void * arg) ; +extern void init_time(void) ; + +/*----------------------------------------------------------------------------- + * mian entry + *----------------------------------------------------------------------------*/ + +int main() +{ + void * arg = NULL ; + + init_time() ; + init_filesystem (); + printf("=== Start: Crypt test ===\n") ; + ctaocrypt_test(arg) ; + printf("=== End: Crypt test ===\n") ; + +} diff --git a/IDE/MDK5-ARM/Projects/CryptTest/test.c b/IDE/MDK5-ARM/Projects/CryptTest/test.c new file mode 100644 index 000000000..7ba1b0b39 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CryptTest/test.c @@ -0,0 +1,3710 @@ +/* test.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +#ifndef NO_CRYPT_TEST + +#ifdef CYASSL_TEST_CERT + #include +#else + #include +#endif +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef HAVE_ECC + #include +#endif +#ifdef HAVE_BLAKE2 + #include +#endif +#ifdef HAVE_LIBZ + #include +#endif + +#ifdef _MSC_VER + /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */ + #pragma warning(disable: 4996) +#endif + +#ifdef OPENSSL_EXTRA + #include + #include + #include + #include +#endif + + +#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) + /* include test cert and key buffers for use with NO_FILESYSTEM */ + #if defined(CYASSL_MDK_ARM) + #include "cert_data.h" + /* use certs_test.c for initial data, so other + commands can share the data. */ + #else + #include + #endif +#endif + +#if defined(CYASSL_MDK_ARM) + #include + #include + extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ; + #define fopen CyaSSL_fopen +#endif + +#ifdef HAVE_NTRU + #include "crypto_ntru.h" +#endif +#ifdef HAVE_CAVIUM + #include "cavium_sysdep.h" + #include "cavium_common.h" + #include "cavium_ioctl.h" +#endif + +#ifdef FREESCALE_MQX + #include + #include + #include +#else + #include +#endif + + +#ifdef THREADX + /* since just testing, use THREADX log printf instead */ + int dc_log_printf(char*, ...); + #undef printf + #define printf dc_log_printf +#endif + +#include "ctaocrypt/test/test.h" + + +typedef struct testVector { + const char* input; + const char* output; + size_t inLen; + size_t outLen; +} testVector; + +int md2_test(void); +int md5_test(void); +int md4_test(void); +int sha_test(void); +int sha256_test(void); +int sha512_test(void); +int sha384_test(void); +int hmac_md5_test(void); +int hmac_sha_test(void); +int hmac_sha256_test(void); +int hmac_sha384_test(void); +int hmac_sha512_test(void); +int hmac_blake2b_test(void); +int hkdf_test(void); +int arc4_test(void); +int hc128_test(void); +int rabbit_test(void); +int des_test(void); +int des3_test(void); +int aes_test(void); +int aesgcm_test(void); +int gmac_test(void); +int aesccm_test(void); +int camellia_test(void); +int rsa_test(void); +int dh_test(void); +int dsa_test(void); +int random_test(void); +int pwdbased_test(void); +int ripemd_test(void); +int openssl_test(void); /* test mini api */ +int pbkdf1_test(void); +int pkcs12_test(void); +int pbkdf2_test(void); +#ifdef HAVE_ECC + int ecc_test(void); +#endif +#ifdef HAVE_BLAKE2 + int blake2b_test(void); +#endif +#ifdef HAVE_LIBZ + int compress_test(void); +#endif + + + +static void err_sys(const char* msg, int es) +{ + printf("%s error = %d\n", msg, es); + #if !defined(THREADX) && !defined(CYASSL_MDK_ARM) + if (msg) + exit(es); + #endif + return; +} + +/* func_args from test.h, so don't have to pull in other junk */ +typedef struct func_args { + int argc; + char** argv; + int return_code; +} func_args; + + + +void ctaocrypt_test(void* args) +{ + int ret = 0; + + ((func_args*)args)->return_code = -1; /* error state */ + +#if !defined(NO_BIG_INT) + if (CheckCtcSettings() != 1) + err_sys("Build vs runtime math mismatch\n", -1234); + +#ifdef USE_FAST_MATH + if (CheckFastMathSettings() != 1) + err_sys("Build vs runtime fastmath FP_MAX_BITS mismatch\n", -1235); +#endif /* USE_FAST_MATH */ +#endif /* !NO_BIG_INT */ + + +#ifndef NO_MD5 + if ( (ret = md5_test()) != 0) + err_sys("MD5 test failed!\n", ret); + else + printf( "MD5 test passed!\n"); +#endif + +#ifdef CYASSL_MD2 + if ( (ret = md2_test()) != 0) + err_sys("MD2 test failed!\n", ret); + else + printf( "MD2 test passed!\n"); +#endif + +#ifndef NO_MD4 + if ( (ret = md4_test()) != 0) + err_sys("MD4 test failed!\n", ret); + else + printf( "MD4 test passed!\n"); +#endif + +#ifndef NO_SHA + if ( (ret = sha_test()) != 0) + err_sys("SHA test failed!\n", ret); + else + printf( "SHA test passed!\n"); +#endif + +#ifndef NO_SHA256 + if ( (ret = sha256_test()) != 0) + err_sys("SHA-256 test failed!\n", ret); + else + printf( "SHA-256 test passed!\n"); +#endif + +#ifdef CYASSL_SHA384 + if ( (ret = sha384_test()) != 0) + err_sys("SHA-384 test failed!\n", ret); + else + printf( "SHA-384 test passed!\n"); +#endif + +#ifdef CYASSL_SHA512 + if ( (ret = sha512_test()) != 0) + err_sys("SHA-512 test failed!\n", ret); + else + printf( "SHA-512 test passed!\n"); +#endif + +#ifdef CYASSL_RIPEMD + if ( (ret = ripemd_test()) != 0) + err_sys("RIPEMD test failed!\n", ret); + else + printf( "RIPEMD test passed!\n"); +#endif + +#ifdef HAVE_BLAKE2 + if ( (ret = blake2b_test()) != 0) + err_sys("BLAKE2b test failed!\n", ret); + else + printf( "BLAKE2b test passed!\n"); +#endif + +#ifndef NO_HMAC + #ifndef NO_MD5 + if ( (ret = hmac_md5_test()) != 0) + err_sys("HMAC-MD5 test failed!\n", ret); + else + printf( "HMAC-MD5 test passed!\n"); + #endif + + #ifndef NO_SHA + if ( (ret = hmac_sha_test()) != 0) + err_sys("HMAC-SHA test failed!\n", ret); + else + printf( "HMAC-SHA test passed!\n"); + #endif + + #ifndef NO_SHA256 + if ( (ret = hmac_sha256_test()) != 0) + err_sys("HMAC-SHA256 test failed!\n", ret); + else + printf( "HMAC-SHA256 test passed!\n"); + #endif + + #ifdef CYASSL_SHA384 + if ( (ret = hmac_sha384_test()) != 0) + err_sys("HMAC-SHA384 test failed!\n", ret); + else + printf( "HMAC-SHA384 test passed!\n"); + #endif + + #ifdef CYASSL_SHA512 + if ( (ret = hmac_sha512_test()) != 0) + err_sys("HMAC-SHA512 test failed!\n", ret); + else + printf( "HMAC-SHA512 test passed!\n"); + #endif + + #ifdef HAVE_BLAKE2 + if ( (ret = hmac_blake2b_test()) != 0) + err_sys("HMAC-BLAKE2 test failed!\n", ret); + else + printf( "HMAC-BLAKE2 test passed!\n"); + #endif + + #ifdef HAVE_HKDF + if ( (ret = hkdf_test()) != 0) + err_sys("HMAC-KDF test failed!\n", ret); + else + printf( "HMAC-KDF test passed!\n"); + #endif + +#endif + +#ifdef HAVE_AESGCM + if ( (ret = gmac_test()) != 0) + err_sys("GMAC test passed!\n", ret); + else + printf( "GMAC test passed!\n"); +#endif + +#ifndef NO_RC4 + if ( (ret = arc4_test()) != 0) + err_sys("ARC4 test failed!\n", ret); + else + printf( "ARC4 test passed!\n"); +#endif + +#ifndef NO_HC128 + if ( (ret = hc128_test()) != 0) + err_sys("HC-128 test failed!\n", ret); + else + printf( "HC-128 test passed!\n"); +#endif + +#ifndef NO_RABBIT + if ( (ret = rabbit_test()) != 0) + err_sys("Rabbit test failed!\n", ret); + else + printf( "Rabbit test passed!\n"); +#endif + +#ifndef NO_DES3 + if ( (ret = des_test()) != 0) + err_sys("DES test failed!\n", ret); + else + printf( "DES test passed!\n"); +#endif + +#ifndef NO_DES3 + if ( (ret = des3_test()) != 0) + err_sys("DES3 test failed!\n", ret); + else + printf( "DES3 test passed!\n"); +#endif + +#ifndef NO_AES + if ( (ret = aes_test()) != 0) + err_sys("AES test failed!\n", ret); + else + printf( "AES test passed!\n"); + +#ifdef HAVE_AESGCM + if ( (ret = aesgcm_test()) != 0) + err_sys("AES-GCM test failed!\n", ret); + else + printf( "AES-GCM test passed!\n"); +#endif + +#ifdef HAVE_AESCCM + if ( (ret = aesccm_test()) != 0) + err_sys("AES-CCM test failed!\n", ret); + else + printf( "AES-CCM test passed!\n"); +#endif +#endif + +#ifdef HAVE_CAMELLIA + if ( (ret = camellia_test()) != 0) + err_sys("CAMELLIA test failed!\n", ret); + else + printf( "CAMELLIA test passed!\n"); +#endif + + if ( (ret = random_test()) != 0) + err_sys("RANDOM test failed!\n", ret); + else + printf( "RANDOM test passed!\n"); + +#ifndef NO_RSA + if ( (ret = rsa_test()) != 0) + err_sys("RSA test failed!\n", ret); + else + printf( "RSA test passed!\n"); +#endif + +#ifndef NO_DH + if ( (ret = dh_test()) != 0) + err_sys("DH test failed!\n", ret); + else + printf( "DH test passed!\n"); +#endif + +#ifndef NO_DSA + if ( (ret = dsa_test()) != 0) + err_sys("DSA test failed!\n", ret); + else + printf( "DSA test passed!\n"); +#endif + +#ifndef NO_PWDBASED + if ( (ret = pwdbased_test()) != 0) + err_sys("PWDBASED test failed!\n", ret); + else + printf( "PWDBASED test passed!\n"); +#endif + +#ifdef OPENSSL_EXTRA + if ( (ret = openssl_test()) != 0) + err_sys("OPENSSL test failed!\n", ret); + else + printf( "OPENSSL test passed!\n"); +#endif + +#ifdef HAVE_ECC + if ( (ret = ecc_test()) != 0) + err_sys("ECC test failed!\n", ret); + else + printf( "ECC test passed!\n"); +#endif + +#ifdef HAVE_LIBZ + if ( (ret = compress_test()) != 0) + err_sys("COMPRESS test failed!\n", ret); + else + printf( "COMPRESS test passed!\n"); +#endif + + ((func_args*)args)->return_code = ret; +} + + +#ifndef NO_MAIN_DRIVER + +#ifdef HAVE_CAVIUM + +static int OpenNitroxDevice(int dma_mode,int dev_id) +{ + Csp1CoreAssignment core_assign; + Uint32 device; + + if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID)) + return -1; + if (Csp1GetDevType(&device)) + return -1; + if (device != NPX_DEVICE) { + if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT, + (Uint32 *)&core_assign)!= 0) + return -1; + } + CspShutdown(CAVIUM_DEV_ID); + + return CspInitialize(dma_mode, dev_id); +} + +#endif /* HAVE_CAVIUM */ + + /* so overall tests can pull in test function */ + + int main(int argc, char** argv) + { + + func_args args; + + +#ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) + err_sys("Cavium OpenNitroxDevice failed", -1236); +#endif /* HAVE_CAVIUM */ + + args.argc = argc; + args.argv = argv; + + ctaocrypt_test(&args); + +#ifdef HAVE_CAVIUM + CspShutdown(CAVIUM_DEV_ID); +#endif + + return args.return_code; + } + +#endif /* NO_MAIN_DRIVER */ + + +#ifdef CYASSL_MD2 +int md2_test() +{ + Md2 md2; + byte hash[MD2_DIGEST_SIZE]; + + testVector a, b, c, d, e, f, g; + testVector test_md2[7]; + int times = sizeof(test_md2) / sizeof(testVector), i; + + a.input = ""; + a.output = "\x83\x50\xe5\xa3\xe2\x4c\x15\x3d\xf2\x27\x5c\x9f\x80\x69" + "\x27\x73"; + a.inLen = strlen(a.input); + a.outLen = MD2_DIGEST_SIZE; + + b.input = "a"; + b.output = "\x32\xec\x01\xec\x4a\x6d\xac\x72\xc0\xab\x96\xfb\x34\xc0" + "\xb5\xd1"; + b.inLen = strlen(b.input); + b.outLen = MD2_DIGEST_SIZE; + + c.input = "abc"; + c.output = "\xda\x85\x3b\x0d\x3f\x88\xd9\x9b\x30\x28\x3a\x69\xe6\xde" + "\xd6\xbb"; + c.inLen = strlen(c.input); + c.outLen = MD2_DIGEST_SIZE; + + d.input = "message digest"; + d.output = "\xab\x4f\x49\x6b\xfb\x2a\x53\x0b\x21\x9f\xf3\x30\x31\xfe" + "\x06\xb0"; + d.inLen = strlen(d.input); + d.outLen = MD2_DIGEST_SIZE; + + e.input = "abcdefghijklmnopqrstuvwxyz"; + e.output = "\x4e\x8d\xdf\xf3\x65\x02\x92\xab\x5a\x41\x08\xc3\xaa\x47" + "\x94\x0b"; + e.inLen = strlen(e.input); + e.outLen = MD2_DIGEST_SIZE; + + f.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" + "6789"; + f.output = "\xda\x33\xde\xf2\xa4\x2d\xf1\x39\x75\x35\x28\x46\xc3\x03" + "\x38\xcd"; + f.inLen = strlen(f.input); + f.outLen = MD2_DIGEST_SIZE; + + g.input = "1234567890123456789012345678901234567890123456789012345678" + "9012345678901234567890"; + g.output = "\xd5\x97\x6f\x79\xd8\x3d\x3a\x0d\xc9\x80\x6c\x3c\x66\xf3" + "\xef\xd8"; + g.inLen = strlen(g.input); + g.outLen = MD2_DIGEST_SIZE; + + test_md2[0] = a; + test_md2[1] = b; + test_md2[2] = c; + test_md2[3] = d; + test_md2[4] = e; + test_md2[5] = f; + test_md2[6] = g; + + InitMd2(&md2); + + for (i = 0; i < times; ++i) { + Md2Update(&md2, (byte*)test_md2[i].input, (word32)test_md2[i].inLen); + Md2Final(&md2, hash); + + if (memcmp(hash, test_md2[i].output, MD2_DIGEST_SIZE) != 0) + return -155 - i; + } + + return 0; +} +#endif + +#ifndef NO_MD5 +int md5_test(void) +{ + Md5 md5; + byte hash[MD5_DIGEST_SIZE]; + + testVector a, b, c, d, e; + testVector test_md5[5]; + int times = sizeof(test_md5) / sizeof(testVector), i; + + a.input = "abc"; + a.output = "\x90\x01\x50\x98\x3c\xd2\x4f\xb0\xd6\x96\x3f\x7d\x28\xe1\x7f" + "\x72"; + a.inLen = strlen(a.input); + a.outLen = MD5_DIGEST_SIZE; + + b.input = "message digest"; + b.output = "\xf9\x6b\x69\x7d\x7c\xb7\x93\x8d\x52\x5a\x2f\x31\xaa\xf1\x61" + "\xd0"; + b.inLen = strlen(b.input); + b.outLen = MD5_DIGEST_SIZE; + + c.input = "abcdefghijklmnopqrstuvwxyz"; + c.output = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00\x7d\xfb\x49\x6c\xca\x67\xe1" + "\x3b"; + c.inLen = strlen(c.input); + c.outLen = MD5_DIGEST_SIZE; + + d.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" + "6789"; + d.output = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5\xa5\x61\x1c\x2c\x9f\x41\x9d" + "\x9f"; + d.inLen = strlen(d.input); + d.outLen = MD5_DIGEST_SIZE; + + e.input = "1234567890123456789012345678901234567890123456789012345678" + "9012345678901234567890"; + e.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6" + "\x7a"; + e.inLen = strlen(e.input); + e.outLen = MD5_DIGEST_SIZE; + + test_md5[0] = a; + test_md5[1] = b; + test_md5[2] = c; + test_md5[3] = d; + test_md5[4] = e; + + InitMd5(&md5); + + for (i = 0; i < times; ++i) { + Md5Update(&md5, (byte*)test_md5[i].input, (word32)test_md5[i].inLen); + Md5Final(&md5, hash); + + if (memcmp(hash, test_md5[i].output, MD5_DIGEST_SIZE) != 0) + return -5 - i; + } + + return 0; +} +#endif /* NO_MD5 */ + + +#ifndef NO_MD4 + +int md4_test(void) +{ + Md4 md4; + byte hash[MD4_DIGEST_SIZE]; + + testVector a, b, c, d, e, f, g; + testVector test_md4[7]; + int times = sizeof(test_md4) / sizeof(testVector), i; + + a.input = ""; + a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" + "\xc0"; + a.inLen = strlen(a.input); + a.outLen = MD4_DIGEST_SIZE; + + b.input = "a"; + b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" + "\x24"; + b.inLen = strlen(b.input); + b.outLen = MD4_DIGEST_SIZE; + + c.input = "abc"; + c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" + "\x9d"; + c.inLen = strlen(c.input); + c.outLen = MD4_DIGEST_SIZE; + + d.input = "message digest"; + d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" + "\x4b"; + d.inLen = strlen(d.input); + d.outLen = MD4_DIGEST_SIZE; + + e.input = "abcdefghijklmnopqrstuvwxyz"; + e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" + "\xa9"; + e.inLen = strlen(e.input); + e.outLen = MD4_DIGEST_SIZE; + + f.input = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345" + "6789"; + f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" + "\xe4"; + f.inLen = strlen(f.input); + f.outLen = MD4_DIGEST_SIZE; + + g.input = "1234567890123456789012345678901234567890123456789012345678" + "9012345678901234567890"; + g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" + "\x36"; + g.inLen = strlen(g.input); + g.outLen = MD4_DIGEST_SIZE; + + test_md4[0] = a; + test_md4[1] = b; + test_md4[2] = c; + test_md4[3] = d; + test_md4[4] = e; + test_md4[5] = f; + test_md4[6] = g; + + InitMd4(&md4); + + for (i = 0; i < times; ++i) { + Md4Update(&md4, (byte*)test_md4[i].input, (word32)test_md4[i].inLen); + Md4Final(&md4, hash); + + if (memcmp(hash, test_md4[i].output, MD4_DIGEST_SIZE) != 0) + return -205 - i; + } + + return 0; +} + +#endif /* NO_MD4 */ + +#ifndef NO_SHA + +int sha_test(void) +{ + Sha sha; + byte hash[SHA_DIGEST_SIZE]; + + testVector a, b, c, d; + testVector test_sha[4]; + int times = sizeof(test_sha) / sizeof(struct testVector), i; + + a.input = "abc"; + a.output = "\xA9\x99\x3E\x36\x47\x06\x81\x6A\xBA\x3E\x25\x71\x78\x50\xC2" + "\x6C\x9C\xD0\xD8\x9D"; + a.inLen = strlen(a.input); + a.outLen = SHA_DIGEST_SIZE; + + b.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; + b.output = "\x84\x98\x3E\x44\x1C\x3B\xD2\x6E\xBA\xAE\x4A\xA1\xF9\x51\x29" + "\xE5\xE5\x46\x70\xF1"; + b.inLen = strlen(b.input); + b.outLen = SHA_DIGEST_SIZE; + + c.input = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" + "aaaaaa"; + c.output = "\x00\x98\xBA\x82\x4B\x5C\x16\x42\x7B\xD7\xA1\x12\x2A\x5A\x44" + "\x2A\x25\xEC\x64\x4D"; + c.inLen = strlen(c.input); + c.outLen = SHA_DIGEST_SIZE; + + d.input = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" + "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" + "aaaaaaaaaa"; + d.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7" + "\x53\x99\x5E\x26\xA0"; + d.inLen = strlen(d.input); + d.outLen = SHA_DIGEST_SIZE; + + test_sha[0] = a; + test_sha[1] = b; + test_sha[2] = c; + test_sha[3] = d; + + InitSha(&sha); + + for (i = 0; i < times; ++i) { + ShaUpdate(&sha, (byte*)test_sha[i].input, (word32)test_sha[i].inLen); + ShaFinal(&sha, hash); + + if (memcmp(hash, test_sha[i].output, SHA_DIGEST_SIZE) != 0) + return -10 - i; + } + + return 0; +} + +#endif /* NO_SHA */ + +#ifdef CYASSL_RIPEMD +int ripemd_test(void) +{ + RipeMd ripemd; + byte hash[RIPEMD_DIGEST_SIZE]; + + testVector a, b, c, d; + testVector test_ripemd[4]; + int times = sizeof(test_ripemd) / sizeof(struct testVector), i; + + a.input = "abc"; + a.output = "\x8e\xb2\x08\xf7\xe0\x5d\x98\x7a\x9b\x04\x4a\x8e\x98\xc6" + "\xb0\x87\xf1\x5a\x0b\xfc"; + a.inLen = strlen(a.input); + a.outLen = RIPEMD_DIGEST_SIZE; + + b.input = "message digest"; + b.output = "\x5d\x06\x89\xef\x49\xd2\xfa\xe5\x72\xb8\x81\xb1\x23\xa8" + "\x5f\xfa\x21\x59\x5f\x36"; + b.inLen = strlen(b.input); + b.outLen = RIPEMD_DIGEST_SIZE; + + c.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; + c.output = "\x12\xa0\x53\x38\x4a\x9c\x0c\x88\xe4\x05\xa0\x6c\x27\xdc" + "\xf4\x9a\xda\x62\xeb\x2b"; + c.inLen = strlen(c.input); + c.outLen = RIPEMD_DIGEST_SIZE; + + d.input = "12345678901234567890123456789012345678901234567890123456" + "789012345678901234567890"; + d.output = "\x9b\x75\x2e\x45\x57\x3d\x4b\x39\xf4\xdb\xd3\x32\x3c\xab" + "\x82\xbf\x63\x32\x6b\xfb"; + d.inLen = strlen(d.input); + d.outLen = RIPEMD_DIGEST_SIZE; + + test_ripemd[0] = a; + test_ripemd[1] = b; + test_ripemd[2] = c; + test_ripemd[3] = d; + + InitRipeMd(&ripemd); + + for (i = 0; i < times; ++i) { + RipeMdUpdate(&ripemd, (byte*)test_ripemd[i].input, + (word32)test_ripemd[i].inLen); + RipeMdFinal(&ripemd, hash); + + if (memcmp(hash, test_ripemd[i].output, RIPEMD_DIGEST_SIZE) != 0) + return -10 - i; + } + + return 0; +} +#endif /* CYASSL_RIPEMD */ + + +#ifdef HAVE_BLAKE2 + + +#define BLAKE2_TESTS 3 + +static const byte blake2b_vec[BLAKE2_TESTS][BLAKE2B_OUTBYTES] = +{ + { + 0x78, 0x6A, 0x02, 0xF7, 0x42, 0x01, 0x59, 0x03, + 0xC6, 0xC6, 0xFD, 0x85, 0x25, 0x52, 0xD2, 0x72, + 0x91, 0x2F, 0x47, 0x40, 0xE1, 0x58, 0x47, 0x61, + 0x8A, 0x86, 0xE2, 0x17, 0xF7, 0x1F, 0x54, 0x19, + 0xD2, 0x5E, 0x10, 0x31, 0xAF, 0xEE, 0x58, 0x53, + 0x13, 0x89, 0x64, 0x44, 0x93, 0x4E, 0xB0, 0x4B, + 0x90, 0x3A, 0x68, 0x5B, 0x14, 0x48, 0xB7, 0x55, + 0xD5, 0x6F, 0x70, 0x1A, 0xFE, 0x9B, 0xE2, 0xCE + }, + { + 0x2F, 0xA3, 0xF6, 0x86, 0xDF, 0x87, 0x69, 0x95, + 0x16, 0x7E, 0x7C, 0x2E, 0x5D, 0x74, 0xC4, 0xC7, + 0xB6, 0xE4, 0x8F, 0x80, 0x68, 0xFE, 0x0E, 0x44, + 0x20, 0x83, 0x44, 0xD4, 0x80, 0xF7, 0x90, 0x4C, + 0x36, 0x96, 0x3E, 0x44, 0x11, 0x5F, 0xE3, 0xEB, + 0x2A, 0x3A, 0xC8, 0x69, 0x4C, 0x28, 0xBC, 0xB4, + 0xF5, 0xA0, 0xF3, 0x27, 0x6F, 0x2E, 0x79, 0x48, + 0x7D, 0x82, 0x19, 0x05, 0x7A, 0x50, 0x6E, 0x4B + }, + { + 0x1C, 0x08, 0x79, 0x8D, 0xC6, 0x41, 0xAB, 0xA9, + 0xDE, 0xE4, 0x35, 0xE2, 0x25, 0x19, 0xA4, 0x72, + 0x9A, 0x09, 0xB2, 0xBF, 0xE0, 0xFF, 0x00, 0xEF, + 0x2D, 0xCD, 0x8E, 0xD6, 0xF8, 0xA0, 0x7D, 0x15, + 0xEA, 0xF4, 0xAE, 0xE5, 0x2B, 0xBF, 0x18, 0xAB, + 0x56, 0x08, 0xA6, 0x19, 0x0F, 0x70, 0xB9, 0x04, + 0x86, 0xC8, 0xA7, 0xD4, 0x87, 0x37, 0x10, 0xB1, + 0x11, 0x5D, 0x3D, 0xEB, 0xBB, 0x43, 0x27, 0xB5 + } +}; + + + +int blake2b_test(void) +{ + Blake2b b2b; + byte digest[64]; + byte input[64]; + int i; + + for (i = 0; i < (int)sizeof(input); i++) + input[i] = (byte)i; + + for (i = 0; i < BLAKE2_TESTS; i++) { + InitBlake2b(&b2b, 64); + Blake2bUpdate(&b2b, input, i); + Blake2bFinal(&b2b, digest, 64); + + if (memcmp(digest, blake2b_vec[i], 64) != 0) { + return -300 - i; + } + } + + return 0; +} +#endif /* HAVE_BLAKE2 */ + + +#ifndef NO_SHA256 +int sha256_test(void) +{ + Sha256 sha; + byte hash[SHA256_DIGEST_SIZE]; + + testVector a, b; + testVector test_sha[2]; + int times = sizeof(test_sha) / sizeof(struct testVector), i; + + a.input = "abc"; + a.output = "\xBA\x78\x16\xBF\x8F\x01\xCF\xEA\x41\x41\x40\xDE\x5D\xAE\x22" + "\x23\xB0\x03\x61\xA3\x96\x17\x7A\x9C\xB4\x10\xFF\x61\xF2\x00" + "\x15\xAD"; + a.inLen = strlen(a.input); + a.outLen = SHA256_DIGEST_SIZE; + + b.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; + b.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60" + "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB" + "\x06\xC1"; + b.inLen = strlen(b.input); + b.outLen = SHA256_DIGEST_SIZE; + + test_sha[0] = a; + test_sha[1] = b; + + InitSha256(&sha); + + for (i = 0; i < times; ++i) { + Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + Sha256Final(&sha, hash); + + if (memcmp(hash, test_sha[i].output, SHA256_DIGEST_SIZE) != 0) + return -10 - i; + } + + return 0; +} +#endif + + +#ifdef CYASSL_SHA512 +int sha512_test(void) +{ + Sha512 sha; + byte hash[SHA512_DIGEST_SIZE]; + + testVector a, b; + testVector test_sha[2]; + int times = sizeof(test_sha) / sizeof(struct testVector), i; + + a.input = "abc"; + a.output = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba\xcc\x41\x73\x49\xae\x20\x41" + "\x31\x12\xe6\xfa\x4e\x89\xa9\x7e\xa2\x0a\x9e\xee\xe6\x4b\x55" + "\xd3\x9a\x21\x92\x99\x2a\x27\x4f\xc1\xa8\x36\xba\x3c\x23\xa3" + "\xfe\xeb\xbd\x45\x4d\x44\x23\x64\x3c\xe8\x0e\x2a\x9a\xc9\x4f" + "\xa5\x4c\xa4\x9f"; + a.inLen = strlen(a.input); + a.outLen = SHA512_DIGEST_SIZE; + + b.input = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi" + "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu"; + b.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14" + "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88" + "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4" + "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b" + "\x87\x4b\xe9\x09"; + b.inLen = strlen(b.input); + b.outLen = SHA512_DIGEST_SIZE; + + test_sha[0] = a; + test_sha[1] = b; + + InitSha512(&sha); + + for (i = 0; i < times; ++i) { + Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + Sha512Final(&sha, hash); + + if (memcmp(hash, test_sha[i].output, SHA512_DIGEST_SIZE) != 0) + return -10 - i; + } + + return 0; +} +#endif + + +#ifdef CYASSL_SHA384 +int sha384_test(void) +{ + Sha384 sha; + byte hash[SHA384_DIGEST_SIZE]; + + testVector a, b; + testVector test_sha[2]; + int times = sizeof(test_sha) / sizeof(struct testVector), i; + + a.input = "abc"; + a.output = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b\xb5\xa0\x3d\x69\x9a\xc6\x50" + "\x07\x27\x2c\x32\xab\x0e\xde\xd1\x63\x1a\x8b\x60\x5a\x43\xff" + "\x5b\xed\x80\x86\x07\x2b\xa1\xe7\xcc\x23\x58\xba\xec\xa1\x34" + "\xc8\x25\xa7"; + a.inLen = strlen(a.input); + a.outLen = SHA384_DIGEST_SIZE; + + b.input = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi" + "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu"; + b.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b" + "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0" + "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91" + "\x74\x60\x39"; + b.inLen = strlen(b.input); + b.outLen = SHA384_DIGEST_SIZE; + + test_sha[0] = a; + test_sha[1] = b; + + InitSha384(&sha); + + for (i = 0; i < times; ++i) { + Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen); + Sha384Final(&sha, hash); + + if (memcmp(hash, test_sha[i].output, SHA384_DIGEST_SIZE) != 0) + return -10 - i; + } + + return 0; +} +#endif /* CYASSL_SHA384 */ + + +#if !defined(NO_HMAC) && !defined(NO_MD5) +int hmac_md5_test(void) +{ + Hmac hmac; + byte hash[MD5_DIGEST_SIZE]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\x92\x94\x72\x7a\x36\x38\xbb\x1c\x13\xf4\x8e\xf8\x15\x8b\xfc" + "\x9d"; + a.inLen = strlen(a.input); + a.outLen = MD5_DIGEST_SIZE; + + b.input = "what do ya want for nothing?"; + b.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7" + "\x38"; + b.inLen = strlen(b.input); + b.outLen = MD5_DIGEST_SIZE; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\x56\xbe\x34\x52\x1d\x14\x4c\x88\xdb\xb8\xc7\x33\xf0\xe8\xb3" + "\xf6"; + c.inLen = strlen(c.input); + c.outLen = MD5_DIGEST_SIZE; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { +#ifdef HAVE_CAVIUM + if (i == 1) + continue; /* driver can't handle keys <= bytes */ + if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) + return -20009; +#endif + HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i])); + HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + HmacFinal(&hmac, hash); + + if (memcmp(hash, test_hmac[i].output, MD5_DIGEST_SIZE) != 0) + return -20 - i; +#ifdef HAVE_CAVIUM + HmacFreeCavium(&hmac); +#endif + } + + return 0; +} +#endif /* NO_HMAC && NO_MD5 */ + +#if !defined(NO_HMAC) && !defined(NO_SHA) +int hmac_sha_test(void) +{ + Hmac hmac; + byte hash[SHA_DIGEST_SIZE]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" + "\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + "\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\xb6\x17\x31\x86\x55\x05\x72\x64\xe2\x8b\xc0\xb6\xfb\x37\x8c" + "\x8e\xf1\x46\xbe\x00"; + a.inLen = strlen(a.input); + a.outLen = SHA_DIGEST_SIZE; + + b.input = "what do ya want for nothing?"; + b.output = "\xef\xfc\xdf\x6a\xe5\xeb\x2f\xa2\xd2\x74\x16\xd5\xf1\x84\xdf" + "\x9c\x25\x9a\x7c\x79"; + b.inLen = strlen(b.input); + b.outLen = SHA_DIGEST_SIZE; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\x12\x5d\x73\x42\xb9\xac\x11\xcd\x91\xa3\x9a\xf4\x8a\xa1\x7b" + "\x4f\x63\xf1\x75\xd3"; + c.inLen = strlen(c.input); + c.outLen = SHA_DIGEST_SIZE; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { +#ifdef HAVE_CAVIUM + if (i == 1) + continue; /* driver can't handle keys <= bytes */ + if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) + return -20010; +#endif + HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i])); + HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + HmacFinal(&hmac, hash); + + if (memcmp(hash, test_hmac[i].output, SHA_DIGEST_SIZE) != 0) + return -20 - i; +#ifdef HAVE_CAVIUM + HmacFreeCavium(&hmac); +#endif + } + + return 0; +} +#endif + + +#if !defined(NO_HMAC) && !defined(NO_SHA256) +int hmac_sha256_test(void) +{ + Hmac hmac; + byte hash[SHA256_DIGEST_SIZE]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" + "\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + "\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\xb0\x34\x4c\x61\xd8\xdb\x38\x53\x5c\xa8\xaf\xce\xaf\x0b\xf1" + "\x2b\x88\x1d\xc2\x00\xc9\x83\x3d\xa7\x26\xe9\x37\x6c\x2e\x32" + "\xcf\xf7"; + a.inLen = strlen(a.input); + a.outLen = SHA256_DIGEST_SIZE; + + b.input = "what do ya want for nothing?"; + b.output = "\x5b\xdc\xc1\x46\xbf\x60\x75\x4e\x6a\x04\x24\x26\x08\x95\x75" + "\xc7\x5a\x00\x3f\x08\x9d\x27\x39\x83\x9d\xec\x58\xb9\x64\xec" + "\x38\x43"; + b.inLen = strlen(b.input); + b.outLen = SHA256_DIGEST_SIZE; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\x77\x3e\xa9\x1e\x36\x80\x0e\x46\x85\x4d\xb8\xeb\xd0\x91\x81" + "\xa7\x29\x59\x09\x8b\x3e\xf8\xc1\x22\xd9\x63\x55\x14\xce\xd5" + "\x65\xfe"; + c.inLen = strlen(c.input); + c.outLen = SHA256_DIGEST_SIZE; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { +#ifdef HAVE_CAVIUM + if (i == 1) + continue; /* driver can't handle keys <= bytes */ + if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) + return -20011; +#endif + HmacSetKey(&hmac, SHA256, (byte*)keys[i], (word32)strlen(keys[i])); + HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + HmacFinal(&hmac, hash); + + if (memcmp(hash, test_hmac[i].output, SHA256_DIGEST_SIZE) != 0) + return -20 - i; +#ifdef HAVE_CAVIUM + HmacFreeCavium(&hmac); +#endif + } + + return 0; +} +#endif + + +#if !defined(NO_HMAC) && defined(HAVE_BLAKE2) +int hmac_blake2b_test(void) +{ + Hmac hmac; + byte hash[BLAKE2B_256]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" + "\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + "\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\x72\x93\x0d\xdd\xf5\xf7\xe1\x78\x38\x07\x44\x18\x0b\x3f\x51" + "\x37\x25\xb5\x82\xc2\x08\x83\x2f\x1c\x99\xfd\x03\xa0\x16\x75" + "\xac\xfd"; + a.inLen = strlen(a.input); + a.outLen = BLAKE2B_256; + + b.input = "what do ya want for nothing?"; + b.output = "\x3d\x20\x50\x71\x05\xc0\x8c\x0c\x38\x44\x1e\xf7\xf9\xd1\x67" + "\x21\xff\x64\xf5\x94\x00\xcf\xf9\x75\x41\xda\x88\x61\x9d\x7c" + "\xda\x2b"; + b.inLen = strlen(b.input); + b.outLen = BLAKE2B_256; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\xda\xfe\x2a\x24\xfc\xe7\xea\x36\x34\xbe\x41\x92\xc7\x11\xa7" + "\x00\xae\x53\x9c\x11\x9c\x80\x74\x55\x22\x25\x4a\xb9\x55\xd3" + "\x0f\x87"; + c.inLen = strlen(c.input); + c.outLen = BLAKE2B_256; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { +#ifdef HAVE_CAVIUM + if (i == 1) + continue; /* driver can't handle keys <= bytes */ + if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0) + return -20011; +#endif + HmacSetKey(&hmac, BLAKE2B_ID, (byte*)keys[i], (word32)strlen(keys[i])); + HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + HmacFinal(&hmac, hash); + + if (memcmp(hash, test_hmac[i].output, BLAKE2B_256) != 0) + return -20 - i; +#ifdef HAVE_CAVIUM + HmacFreeCavium(&hmac); +#endif + } + + return 0; +} +#endif + + +#if !defined(NO_HMAC) && defined(CYASSL_SHA384) +int hmac_sha384_test(void) +{ + Hmac hmac; + byte hash[SHA384_DIGEST_SIZE]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" + "\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + "\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\xaf\xd0\x39\x44\xd8\x48\x95\x62\x6b\x08\x25\xf4\xab\x46\x90" + "\x7f\x15\xf9\xda\xdb\xe4\x10\x1e\xc6\x82\xaa\x03\x4c\x7c\xeb" + "\xc5\x9c\xfa\xea\x9e\xa9\x07\x6e\xde\x7f\x4a\xf1\x52\xe8\xb2" + "\xfa\x9c\xb6"; + a.inLen = strlen(a.input); + a.outLen = SHA384_DIGEST_SIZE; + + b.input = "what do ya want for nothing?"; + b.output = "\xaf\x45\xd2\xe3\x76\x48\x40\x31\x61\x7f\x78\xd2\xb5\x8a\x6b" + "\x1b\x9c\x7e\xf4\x64\xf5\xa0\x1b\x47\xe4\x2e\xc3\x73\x63\x22" + "\x44\x5e\x8e\x22\x40\xca\x5e\x69\xe2\xc7\x8b\x32\x39\xec\xfa" + "\xb2\x16\x49"; + b.inLen = strlen(b.input); + b.outLen = SHA384_DIGEST_SIZE; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\x88\x06\x26\x08\xd3\xe6\xad\x8a\x0a\xa2\xac\xe0\x14\xc8\xa8" + "\x6f\x0a\xa6\x35\xd9\x47\xac\x9f\xeb\xe8\x3e\xf4\xe5\x59\x66" + "\x14\x4b\x2a\x5a\xb3\x9d\xc1\x38\x14\xb9\x4e\x3a\xb6\xe1\x01" + "\xa3\x4f\x27"; + c.inLen = strlen(c.input); + c.outLen = SHA384_DIGEST_SIZE; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { + HmacSetKey(&hmac, SHA384, (byte*)keys[i], (word32)strlen(keys[i])); + HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + HmacFinal(&hmac, hash); + + if (memcmp(hash, test_hmac[i].output, SHA384_DIGEST_SIZE) != 0) + return -20 - i; + } + + return 0; +} +#endif + + +#if !defined(NO_HMAC) && defined(CYASSL_SHA512) +int hmac_sha512_test(void) +{ + Hmac hmac; + byte hash[SHA512_DIGEST_SIZE]; + + const char* keys[]= + { + "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b" + "\x0b\x0b\x0b", + "Jefe", + "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA" + "\xAA\xAA\xAA" + }; + + testVector a, b, c; + testVector test_hmac[3]; + + int times = sizeof(test_hmac) / sizeof(testVector), i; + + a.input = "Hi There"; + a.output = "\x87\xaa\x7c\xde\xa5\xef\x61\x9d\x4f\xf0\xb4\x24\x1a\x1d\x6c" + "\xb0\x23\x79\xf4\xe2\xce\x4e\xc2\x78\x7a\xd0\xb3\x05\x45\xe1" + "\x7c\xde\xda\xa8\x33\xb7\xd6\xb8\xa7\x02\x03\x8b\x27\x4e\xae" + "\xa3\xf4\xe4\xbe\x9d\x91\x4e\xeb\x61\xf1\x70\x2e\x69\x6c\x20" + "\x3a\x12\x68\x54"; + a.inLen = strlen(a.input); + a.outLen = SHA512_DIGEST_SIZE; + + b.input = "what do ya want for nothing?"; + b.output = "\x16\x4b\x7a\x7b\xfc\xf8\x19\xe2\xe3\x95\xfb\xe7\x3b\x56\xe0" + "\xa3\x87\xbd\x64\x22\x2e\x83\x1f\xd6\x10\x27\x0c\xd7\xea\x25" + "\x05\x54\x97\x58\xbf\x75\xc0\x5a\x99\x4a\x6d\x03\x4f\x65\xf8" + "\xf0\xe6\xfd\xca\xea\xb1\xa3\x4d\x4a\x6b\x4b\x63\x6e\x07\x0a" + "\x38\xbc\xe7\x37"; + b.inLen = strlen(b.input); + b.outLen = SHA512_DIGEST_SIZE; + + c.input = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD" + "\xDD\xDD\xDD\xDD\xDD\xDD"; + c.output = "\xfa\x73\xb0\x08\x9d\x56\xa2\x84\xef\xb0\xf0\x75\x6c\x89\x0b" + "\xe9\xb1\xb5\xdb\xdd\x8e\xe8\x1a\x36\x55\xf8\x3e\x33\xb2\x27" + "\x9d\x39\xbf\x3e\x84\x82\x79\xa7\x22\xc8\x06\xb4\x85\xa4\x7e" + "\x67\xc8\x07\xb9\x46\xa3\x37\xbe\xe8\x94\x26\x74\x27\x88\x59" + "\xe1\x32\x92\xfb"; + c.inLen = strlen(c.input); + c.outLen = SHA512_DIGEST_SIZE; + + test_hmac[0] = a; + test_hmac[1] = b; + test_hmac[2] = c; + + for (i = 0; i < times; ++i) { + HmacSetKey(&hmac, SHA512, (byte*)keys[i], (word32)strlen(keys[i])); + HmacUpdate(&hmac, (byte*)test_hmac[i].input, + (word32)test_hmac[i].inLen); + HmacFinal(&hmac, hash); + + if (memcmp(hash, test_hmac[i].output, SHA512_DIGEST_SIZE) != 0) + return -20 - i; + } + + return 0; +} +#endif + + +#ifndef NO_RC4 +int arc4_test(void) +{ + byte cipher[16]; + byte plain[16]; + + const char* keys[] = + { + "\x01\x23\x45\x67\x89\xab\xcd\xef", + "\x01\x23\x45\x67\x89\xab\xcd\xef", + "\x00\x00\x00\x00\x00\x00\x00\x00", + "\xef\x01\x23\x45" + }; + + testVector a, b, c, d; + testVector test_arc4[4]; + + int times = sizeof(test_arc4) / sizeof(testVector), i; + + a.input = "\x01\x23\x45\x67\x89\xab\xcd\xef"; + a.output = "\x75\xb7\x87\x80\x99\xe0\xc5\x96"; + a.inLen = 8; + a.outLen = 8; + + b.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + b.output = "\x74\x94\xc2\xe7\x10\x4b\x08\x79"; + b.inLen = 8; + b.outLen = 8; + + c.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + c.output = "\xde\x18\x89\x41\xa3\x37\x5d\x3a"; + c.inLen = 8; + c.outLen = 8; + + d.input = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"; + d.output = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf\xbd\x61"; + d.inLen = 10; + d.outLen = 10; + + test_arc4[0] = a; + test_arc4[1] = b; + test_arc4[2] = c; + test_arc4[3] = d; + + for (i = 0; i < times; ++i) { + Arc4 enc; + Arc4 dec; + int keylen = 8; /* strlen with key 0x00 not good */ + if (i == 3) + keylen = 4; + +#ifdef HAVE_CAVIUM + if (Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0) + return -20001; + if (Arc4InitCavium(&dec, CAVIUM_DEV_ID) != 0) + return -20002; +#endif + + Arc4SetKey(&enc, (byte*)keys[i], keylen); + Arc4SetKey(&dec, (byte*)keys[i], keylen); + + Arc4Process(&enc, cipher, (byte*)test_arc4[i].input, + (word32)test_arc4[i].outLen); + Arc4Process(&dec, plain, cipher, (word32)test_arc4[i].outLen); + + if (memcmp(plain, test_arc4[i].input, test_arc4[i].outLen)) + return -20 - i; + + if (memcmp(cipher, test_arc4[i].output, test_arc4[i].outLen)) + return -20 - 5 - i; + +#ifdef HAVE_CAVIUM + Arc4FreeCavium(&enc); + Arc4FreeCavium(&dec); +#endif + } + + return 0; +} +#endif + + +int hc128_test(void) +{ +#ifdef HAVE_HC128 + byte cipher[16]; + byte plain[16]; + + const char* keys[] = + { + "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + "\x00\x53\xA6\xF9\x4C\x9F\xF2\x45\x98\xEB\x3E\x91\xE4\x37\x8A\xDD", + "\x0F\x62\xB5\x08\x5B\xAE\x01\x54\xA7\xFA\x4D\xA0\xF3\x46\x99\xEC" + }; + + const char* ivs[] = + { + "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + "\x0D\x74\xDB\x42\xA9\x10\x77\xDE\x45\xAC\x13\x7A\xE1\x48\xAF\x16", + "\x28\x8F\xF6\x5D\xC4\x2B\x92\xF9\x60\xC7\x2E\x95\xFC\x63\xCA\x31" + }; + + + testVector a, b, c, d; + testVector test_hc128[4]; + + int times = sizeof(test_hc128) / sizeof(testVector), i; + + a.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + a.output = "\x37\x86\x02\xB9\x8F\x32\xA7\x48"; + a.inLen = 8; + a.outLen = 8; + + b.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + b.output = "\x33\x7F\x86\x11\xC6\xED\x61\x5F"; + b.inLen = 8; + b.outLen = 8; + + c.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + c.output = "\x2E\x1E\xD1\x2A\x85\x51\xC0\x5A"; + c.inLen = 8; + c.outLen = 8; + + d.input = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"; + d.output = "\x1C\xD8\xAE\xDD\xFE\x52\xE2\x17\xE8\x35\xD0\xB7\xE8\x4E\x29"; + d.inLen = 15; + d.outLen = 15; + + test_hc128[0] = a; + test_hc128[1] = b; + test_hc128[2] = c; + test_hc128[3] = d; + + for (i = 0; i < times; ++i) { + HC128 enc; + HC128 dec; + + /* align keys/ivs in plain/cipher buffers */ + memcpy(plain, keys[i], 16); + memcpy(cipher, ivs[i], 16); + + Hc128_SetKey(&enc, plain, cipher); + Hc128_SetKey(&dec, plain, cipher); + + /* align input */ + memcpy(plain, test_hc128[i].input, test_hc128[i].outLen); + Hc128_Process(&enc, cipher, plain, (word32)test_hc128[i].outLen); + Hc128_Process(&dec, plain, cipher, (word32)test_hc128[i].outLen); + + if (memcmp(plain, test_hc128[i].input, test_hc128[i].outLen)) + return -120 - i; + + if (memcmp(cipher, test_hc128[i].output, test_hc128[i].outLen)) + return -120 - 5 - i; + } + +#endif /* HAVE_HC128 */ + return 0; +} + + +#ifndef NO_RABBIT +int rabbit_test(void) +{ + byte cipher[16]; + byte plain[16]; + + const char* keys[] = + { + "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", + "\xAC\xC3\x51\xDC\xF1\x62\xFC\x3B\xFE\x36\x3D\x2E\x29\x13\x28\x91" + }; + + const char* ivs[] = + { + "\x00\x00\x00\x00\x00\x00\x00\x00", + "\x59\x7E\x26\xC1\x75\xF5\x73\xC3", + 0 + }; + + testVector a, b, c; + testVector test_rabbit[3]; + + int times = sizeof(test_rabbit) / sizeof(testVector), i; + + a.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + a.output = "\xED\xB7\x05\x67\x37\x5D\xCD\x7C"; + a.inLen = 8; + a.outLen = 8; + + b.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + b.output = "\x6D\x7D\x01\x22\x92\xCC\xDC\xE0"; + b.inLen = 8; + b.outLen = 8; + + c.input = "\x00\x00\x00\x00\x00\x00\x00\x00"; + c.output = "\x04\xCE\xCA\x7A\x1A\x86\x6E\x77"; + c.inLen = 8; + c.outLen = 8; + + test_rabbit[0] = a; + test_rabbit[1] = b; + test_rabbit[2] = c; + + for (i = 0; i < times; ++i) { + Rabbit enc; + Rabbit dec; + byte* iv; + + /* align keys/ivs in plain/cipher buffers */ + memcpy(plain, keys[i], 16); + if (ivs[i]) { + memcpy(cipher, ivs[i], 8); + iv = cipher; + } else + iv = NULL; + RabbitSetKey(&enc, plain, iv); + RabbitSetKey(&dec, plain, iv); + + /* align input */ + memcpy(plain, test_rabbit[i].input, test_rabbit[i].outLen); + RabbitProcess(&enc, cipher, plain, (word32)test_rabbit[i].outLen); + RabbitProcess(&dec, plain, cipher, (word32)test_rabbit[i].outLen); + + if (memcmp(plain, test_rabbit[i].input, test_rabbit[i].outLen)) + return -130 - i; + + if (memcmp(cipher, test_rabbit[i].output, test_rabbit[i].outLen)) + return -130 - 5 - i; + } + + return 0; +} +#endif /* NO_RABBIT */ + + +#ifndef NO_DES3 +int des_test(void) +{ + const byte vector[] = { /* "now is the time for all " w/o trailing 0 */ + 0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74, + 0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20, + 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 + }; + + byte plain[24]; + byte cipher[24]; + + Des enc; + Des dec; + + const byte key[] = + { + 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef + }; + + const byte iv[] = + { + 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef + }; + + const byte verify[] = + { + 0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8, + 0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73, + 0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b + }; + + + Des_SetKey(&enc, key, iv, DES_ENCRYPTION); + Des_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); + Des_SetKey(&dec, key, iv, DES_DECRYPTION); + Des_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); + + if (memcmp(plain, vector, sizeof(plain))) + return -31; + + if (memcmp(cipher, verify, sizeof(cipher))) + return -32; + + return 0; +} +#endif /* NO_DES3 */ + + +#ifndef NO_DES3 +int des3_test(void) +{ + const byte vector[] = { /* "Now is the time for all " w/o trailing 0 */ + 0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74, + 0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20, + 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 + }; + + byte plain[24]; + byte cipher[24]; + + Des3 enc; + Des3 dec; + + const byte key3[] = + { + 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, + 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, + 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 + }; + const byte iv3[] = + { + 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81 + + }; + + const byte verify3[] = + { + 0x43,0xa0,0x29,0x7e,0xd1,0x84,0xf8,0x0e, + 0x89,0x64,0x84,0x32,0x12,0xd5,0x08,0x98, + 0x18,0x94,0x15,0x74,0x87,0x12,0x7d,0xb0 + }; + + +#ifdef HAVE_CAVIUM + if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) + return -20005; + if (Des3_InitCavium(&dec, CAVIUM_DEV_ID) != 0) + return -20006; +#endif + Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION); + Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION); + Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector)); + Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher)); + + if (memcmp(plain, vector, sizeof(plain))) + return -33; + + if (memcmp(cipher, verify3, sizeof(cipher))) + return -34; + +#ifdef HAVE_CAVIUM + Des3_FreeCavium(&enc); + Des3_FreeCavium(&dec); +#endif + return 0; +} +#endif /* NO_DES */ + + +#ifndef NO_AES +int aes_test(void) +{ + Aes enc; + Aes dec; + + const byte msg[] = { /* "Now is the time for all " w/o trailing 0 */ + 0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74, + 0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20, + 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 + }; + + const byte verify[] = + { + 0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53, + 0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb + }; + + byte key[] = "0123456789abcdef "; /* align */ + byte iv[] = "1234567890abcdef "; /* align */ + + byte cipher[AES_BLOCK_SIZE * 4]; + byte plain [AES_BLOCK_SIZE * 4]; + +#ifdef HAVE_CAVIUM + if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) + return -20003; + if (AesInitCavium(&dec, CAVIUM_DEV_ID) != 0) + return -20004; +#endif + AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION); + AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION); + + AesCbcEncrypt(&enc, cipher, msg, AES_BLOCK_SIZE); + AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE); + + if (memcmp(plain, msg, AES_BLOCK_SIZE)) + return -60; + + if (memcmp(cipher, verify, AES_BLOCK_SIZE)) + return -61; + +#ifdef HAVE_CAVIUM + AesFreeCavium(&enc); + AesFreeCavium(&dec); +#endif +#ifdef CYASSL_AES_COUNTER + { + const byte ctrKey[] = + { + 0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6, + 0xab,0xf7,0x15,0x88,0x09,0xcf,0x4f,0x3c + }; + + const byte ctrIv[] = + { + 0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7, + 0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff + }; + + + const byte ctrPlain[] = + { + 0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96, + 0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a, + 0xae,0x2d,0x8a,0x57,0x1e,0x03,0xac,0x9c, + 0x9e,0xb7,0x6f,0xac,0x45,0xaf,0x8e,0x51, + 0x30,0xc8,0x1c,0x46,0xa3,0x5c,0xe4,0x11, + 0xe5,0xfb,0xc1,0x19,0x1a,0x0a,0x52,0xef, + 0xf6,0x9f,0x24,0x45,0xdf,0x4f,0x9b,0x17, + 0xad,0x2b,0x41,0x7b,0xe6,0x6c,0x37,0x10 + }; + + const byte ctrCipher[] = + { + 0x87,0x4d,0x61,0x91,0xb6,0x20,0xe3,0x26, + 0x1b,0xef,0x68,0x64,0x99,0x0d,0xb6,0xce, + 0x98,0x06,0xf6,0x6b,0x79,0x70,0xfd,0xff, + 0x86,0x17,0x18,0x7b,0xb9,0xff,0xfd,0xff, + 0x5a,0xe4,0xdf,0x3e,0xdb,0xd5,0xd3,0x5e, + 0x5b,0x4f,0x09,0x02,0x0d,0xb0,0x3e,0xab, + 0x1e,0x03,0x1d,0xda,0x2f,0xbe,0x03,0xd1, + 0x79,0x21,0x70,0xa0,0xf3,0x00,0x9c,0xee + }; + + AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); + /* Ctr only uses encrypt, even on key setup */ + AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION); + + AesCtrEncrypt(&enc, cipher, ctrPlain, AES_BLOCK_SIZE*4); + AesCtrEncrypt(&dec, plain, cipher, AES_BLOCK_SIZE*4); + + if (memcmp(plain, ctrPlain, AES_BLOCK_SIZE*4)) + return -66; + + if (memcmp(cipher, ctrCipher, AES_BLOCK_SIZE*4)) + return -67; + } +#endif /* CYASSL_AES_COUNTER */ + +#if defined(CYASSL_AESNI) && defined(CYASSL_AES_DIRECT) + { + const byte niPlain[] = + { + 0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96, + 0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a + }; + + const byte niCipher[] = + { + 0xf3,0xee,0xd1,0xbd,0xb5,0xd2,0xa0,0x3c, + 0x06,0x4b,0x5a,0x7e,0x3d,0xb1,0x81,0xf8 + }; + + const byte niKey[] = + { + 0x60,0x3d,0xeb,0x10,0x15,0xca,0x71,0xbe, + 0x2b,0x73,0xae,0xf0,0x85,0x7d,0x77,0x81, + 0x1f,0x35,0x2c,0x07,0x3b,0x61,0x08,0xd7, + 0x2d,0x98,0x10,0xa3,0x09,0x14,0xdf,0xf4 + }; + + XMEMSET(cipher, 0, AES_BLOCK_SIZE); + AesSetKey(&enc, niKey, sizeof(niKey), cipher, AES_ENCRYPTION); + AesEncryptDirect(&enc, cipher, niPlain); + if (XMEMCMP(cipher, niCipher, AES_BLOCK_SIZE) != 0) + return -20006; + + XMEMSET(plain, 0, AES_BLOCK_SIZE); + AesSetKey(&dec, niKey, sizeof(niKey), plain, AES_DECRYPTION); + AesDecryptDirect(&dec, plain, niCipher); + if (XMEMCMP(plain, niPlain, AES_BLOCK_SIZE) != 0) + return -20007; + } +#endif /* CYASSL_AESNI && CYASSL_AES_DIRECT */ + + return 0; +} + +#ifdef HAVE_AESGCM +int aesgcm_test(void) +{ + Aes enc; + + /* + * This is Test Case 16 from the document Galois/ + * Counter Mode of Operation (GCM) by McGrew and + * Viega. + */ + const byte k[] = + { + 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, + 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08, + 0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c, + 0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08 + }; + + const byte iv[] = + { + 0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad, + 0xde, 0xca, 0xf8, 0x88 + }; + + const byte p[] = + { + 0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5, + 0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a, + 0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda, + 0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72, + 0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53, + 0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25, + 0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57, + 0xba, 0x63, 0x7b, 0x39 + }; + + const byte a[] = + { + 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, + 0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef, + 0xab, 0xad, 0xda, 0xd2 + }; + + const byte c[] = + { + 0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07, + 0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d, + 0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9, + 0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa, + 0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d, + 0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38, + 0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a, + 0xbc, 0xc9, 0xf6, 0x62 + }; + + const byte t[] = + { + 0x76, 0xfc, 0x6e, 0xce, 0x0f, 0x4e, 0x17, 0x68, + 0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b + }; + + byte t2[sizeof(t)]; + byte p2[sizeof(c)]; + byte c2[sizeof(p)]; + + int result; + + memset(t2, 0, sizeof(t2)); + memset(c2, 0, sizeof(c2)); + memset(p2, 0, sizeof(p2)); + + AesGcmSetKey(&enc, k, sizeof(k)); + /* AES-GCM encrypt and decrypt both use AES encrypt internally */ + AesGcmEncrypt(&enc, c2, p, sizeof(c2), iv, sizeof(iv), + t2, sizeof(t2), a, sizeof(a)); + if (memcmp(c, c2, sizeof(c2))) + return -68; + if (memcmp(t, t2, sizeof(t2))) + return -69; + + result = AesGcmDecrypt(&enc, p2, c2, sizeof(p2), iv, sizeof(iv), + t2, sizeof(t2), a, sizeof(a)); + if (result != 0) + return -70; + if (memcmp(p, p2, sizeof(p2))) + return -71; + + return 0; +} + +int gmac_test(void) +{ + Gmac gmac; + + const byte k1[] = + { + 0x89, 0xc9, 0x49, 0xe9, 0xc8, 0x04, 0xaf, 0x01, + 0x4d, 0x56, 0x04, 0xb3, 0x94, 0x59, 0xf2, 0xc8 + }; + const byte iv1[] = + { + 0xd1, 0xb1, 0x04, 0xc8, 0x15, 0xbf, 0x1e, 0x94, + 0xe2, 0x8c, 0x8f, 0x16 + }; + const byte a1[] = + { + 0x82, 0xad, 0xcd, 0x63, 0x8d, 0x3f, 0xa9, 0xd9, + 0xf3, 0xe8, 0x41, 0x00, 0xd6, 0x1e, 0x07, 0x77 + }; + const byte t1[] = + { + 0x88, 0xdb, 0x9d, 0x62, 0x17, 0x2e, 0xd0, 0x43, + 0xaa, 0x10, 0xf1, 0x6d, 0x22, 0x7d, 0xc4, 0x1b + }; + + const byte k2[] = + { + 0x40, 0xf7, 0xec, 0xb2, 0x52, 0x6d, 0xaa, 0xd4, + 0x74, 0x25, 0x1d, 0xf4, 0x88, 0x9e, 0xf6, 0x5b + }; + const byte iv2[] = + { + 0xee, 0x9c, 0x6e, 0x06, 0x15, 0x45, 0x45, 0x03, + 0x1a, 0x60, 0x24, 0xa7 + }; + const byte a2[] = + { + 0x94, 0x81, 0x2c, 0x87, 0x07, 0x4e, 0x15, 0x18, + 0x34, 0xb8, 0x35, 0xaf, 0x1c, 0xa5, 0x7e, 0x56 + }; + const byte t2[] = + { + 0xc6, 0x81, 0x79, 0x8e, 0x3d, 0xda, 0xb0, 0x9f, + 0x8d, 0x83, 0xb0, 0xbb, 0x14, 0xb6, 0x91 + }; + + const byte k3[] = + { + 0xb8, 0xe4, 0x9a, 0x5e, 0x37, 0xf9, 0x98, 0x2b, + 0xb9, 0x6d, 0xd0, 0xc9, 0xb6, 0xab, 0x26, 0xac + }; + const byte iv3[] = + { + 0xe4, 0x4a, 0x42, 0x18, 0x8c, 0xae, 0x94, 0x92, + 0x6a, 0x9c, 0x26, 0xb0 + }; + const byte a3[] = + { + 0x9d, 0xb9, 0x61, 0x68, 0xa6, 0x76, 0x7a, 0x31, + 0xf8, 0x29, 0xe4, 0x72, 0x61, 0x68, 0x3f, 0x8a + }; + const byte t3[] = + { + 0x23, 0xe2, 0x9f, 0x66, 0xe4, 0xc6, 0x52, 0x48 + }; + + byte tag[16]; + + memset(tag, 0, sizeof(tag)); + GmacSetKey(&gmac, k1, sizeof(k1)); + GmacUpdate(&gmac, iv1, sizeof(iv1), a1, sizeof(a1), tag, sizeof(t1)); + if (memcmp(t1, tag, sizeof(t1)) != 0) + return -126; + + memset(tag, 0, sizeof(tag)); + GmacSetKey(&gmac, k2, sizeof(k2)); + GmacUpdate(&gmac, iv2, sizeof(iv2), a2, sizeof(a2), tag, sizeof(t2)); + if (memcmp(t2, tag, sizeof(t2)) != 0) + return -127; + + memset(tag, 0, sizeof(tag)); + GmacSetKey(&gmac, k3, sizeof(k3)); + GmacUpdate(&gmac, iv3, sizeof(iv3), a3, sizeof(a3), tag, sizeof(t3)); + if (memcmp(t3, tag, sizeof(t3)) != 0) + return -128; + + return 0; +} +#endif /* HAVE_AESGCM */ + +#ifdef HAVE_AESCCM +int aesccm_test(void) +{ + Aes enc; + + /* key */ + const byte k[] = + { + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf + }; + + /* nonce */ + const byte iv[] = + { + 0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xa0, + 0xa1, 0xa2, 0xa3, 0xa4, 0xa5 + }; + + /* plaintext */ + const byte p[] = + { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e + }; + + const byte a[] = + { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 + }; + + const byte c[] = + { + 0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x63, 0xd2, + 0xf0, 0x66, 0xd0, 0xc2, 0xc0, 0xf9, 0x89, 0x80, + 0x6d, 0x5f, 0x6b, 0x61, 0xda, 0xc3, 0x84 + }; + + const byte t[] = + { + 0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 + }; + + byte t2[sizeof(t)]; + byte p2[sizeof(p)]; + byte c2[sizeof(c)]; + + int result; + + memset(t2, 0, sizeof(t2)); + memset(c2, 0, sizeof(c2)); + memset(p2, 0, sizeof(p2)); + + AesCcmSetKey(&enc, k, sizeof(k)); + /* AES-CCM encrypt and decrypt both use AES encrypt internally */ + AesCcmEncrypt(&enc, c2, p, sizeof(c2), iv, sizeof(iv), + t2, sizeof(t2), a, sizeof(a)); + if (memcmp(c, c2, sizeof(c2))) + return -107; + if (memcmp(t, t2, sizeof(t2))) + return -108; + + result = AesCcmDecrypt(&enc, p2, c2, sizeof(p2), iv, sizeof(iv), + t2, sizeof(t2), a, sizeof(a)); + if (result != 0) + return -109; + if (memcmp(p, p2, sizeof(p2))) + return -110; + + /* Test the authentication failure */ + t2[0]++; /* Corrupt the authentication tag. */ + result = AesCcmDecrypt(&enc, p2, c, sizeof(p2), iv, sizeof(iv), + t2, sizeof(t2), a, sizeof(a)); + if (result == 0) + return -111; + + /* Clear c2 to compare against p2. p2 should be set to zero in case of + * authentication fail. */ + memset(c2, 0, sizeof(c2)); + if (memcmp(p2, c2, sizeof(p2))) + return -112; + + return 0; +} +#endif /* HAVE_AESCCM */ + + +#endif /* NO_AES */ + + +#ifdef HAVE_CAMELLIA + +enum { + CAM_ECB_ENC, CAM_ECB_DEC, CAM_CBC_ENC, CAM_CBC_DEC +}; + +typedef struct { + int type; + const byte* plaintext; + const byte* iv; + const byte* ciphertext; + const byte* key; + word32 keySz; + int errorCode; +} test_vector_t; + +int camellia_test(void) +{ + /* Camellia ECB Test Plaintext */ + static const byte pte[] = + { + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 + }; + + /* Camellia ECB Test Initialization Vector */ + static const byte ive[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; + + /* Test 1: Camellia ECB 128-bit key */ + static const byte k1[] = + { + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10 + }; + static const byte c1[] = + { + 0x67, 0x67, 0x31, 0x38, 0x54, 0x96, 0x69, 0x73, + 0x08, 0x57, 0x06, 0x56, 0x48, 0xea, 0xbe, 0x43 + }; + + /* Test 2: Camellia ECB 192-bit key */ + static const byte k2[] = + { + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77 + }; + static const byte c2[] = + { + 0xb4, 0x99, 0x34, 0x01, 0xb3, 0xe9, 0x96, 0xf8, + 0x4e, 0xe5, 0xce, 0xe7, 0xd7, 0x9b, 0x09, 0xb9 + }; + + /* Test 3: Camellia ECB 256-bit key */ + static const byte k3[] = + { + 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, + 0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff + }; + static const byte c3[] = + { + 0x9a, 0xcc, 0x23, 0x7d, 0xff, 0x16, 0xd7, 0x6c, + 0x20, 0xef, 0x7c, 0x91, 0x9e, 0x3a, 0x75, 0x09 + }; + + /* Camellia CBC Test Plaintext */ + static const byte ptc[] = + { + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A + }; + + /* Camellia CBC Test Initialization Vector */ + static const byte ivc[] = + { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F + }; + + /* Test 4: Camellia-CBC 128-bit key */ + static const byte k4[] = + { + 0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6, + 0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C + }; + static const byte c4[] = + { + 0x16, 0x07, 0xCF, 0x49, 0x4B, 0x36, 0xBB, 0xF0, + 0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB + }; + + /* Test 5: Camellia-CBC 192-bit key */ + static const byte k5[] = + { + 0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52, + 0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5, + 0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B + }; + static const byte c5[] = + { + 0x2A, 0x48, 0x30, 0xAB, 0x5A, 0xC4, 0xA1, 0xA2, + 0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93 + }; + + /* Test 6: CBC 256-bit key */ + static const byte k6[] = + { + 0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE, + 0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81, + 0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7, + 0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 + }; + static const byte c6[] = + { + 0xE6, 0xCF, 0xA3, 0x5F, 0xC0, 0x2B, 0x13, 0x4A, + 0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA + }; + + byte out[CAMELLIA_BLOCK_SIZE]; + Camellia cam; + int i, testsSz; + const test_vector_t testVectors[] = + { + {CAM_ECB_ENC, pte, ive, c1, k1, sizeof(k1), -114}, + {CAM_ECB_ENC, pte, ive, c2, k2, sizeof(k2), -115}, + {CAM_ECB_ENC, pte, ive, c3, k3, sizeof(k3), -116}, + {CAM_ECB_DEC, pte, ive, c1, k1, sizeof(k1), -117}, + {CAM_ECB_DEC, pte, ive, c2, k2, sizeof(k2), -118}, + {CAM_ECB_DEC, pte, ive, c3, k3, sizeof(k3), -119}, + {CAM_CBC_ENC, ptc, ivc, c4, k4, sizeof(k4), -120}, + {CAM_CBC_ENC, ptc, ivc, c5, k5, sizeof(k5), -121}, + {CAM_CBC_ENC, ptc, ivc, c6, k6, sizeof(k6), -122}, + {CAM_CBC_DEC, ptc, ivc, c4, k4, sizeof(k4), -123}, + {CAM_CBC_DEC, ptc, ivc, c5, k5, sizeof(k5), -124}, + {CAM_CBC_DEC, ptc, ivc, c6, k6, sizeof(k6), -125} + }; + + if ((sizeof(pte) != CAMELLIA_BLOCK_SIZE) || + (sizeof(ptc) != CAMELLIA_BLOCK_SIZE)) + return -113; + + testsSz = sizeof(testVectors)/sizeof(test_vector_t); + for (i = 0; i < testsSz; i++) { + CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz, + testVectors[i].iv); + + switch (testVectors[i].type) { + case CAM_ECB_ENC: + CamelliaEncryptDirect(&cam, out, testVectors[i].plaintext); + if (memcmp(out, testVectors[i].ciphertext, CAMELLIA_BLOCK_SIZE)) + return testVectors[i].errorCode; + break; + case CAM_ECB_DEC: + CamelliaDecryptDirect(&cam, out, testVectors[i].ciphertext); + if (memcmp(out, testVectors[i].plaintext, CAMELLIA_BLOCK_SIZE)) + return testVectors[i].errorCode; + break; + case CAM_CBC_ENC: + CamelliaCbcEncrypt(&cam, out, testVectors[i].plaintext, + CAMELLIA_BLOCK_SIZE); + if (memcmp(out, testVectors[i].ciphertext, CAMELLIA_BLOCK_SIZE)) + return testVectors[i].errorCode; + break; + case CAM_CBC_DEC: + CamelliaCbcDecrypt(&cam, out, testVectors[i].ciphertext, + CAMELLIA_BLOCK_SIZE); + if (memcmp(out, testVectors[i].plaintext, CAMELLIA_BLOCK_SIZE)) + return testVectors[i].errorCode; + break; + default: + break; + } + } + + /* Setting the IV and checking it was actually set. */ + CamelliaSetIV(&cam, ivc); + if (XMEMCMP(cam.reg, ivc, CAMELLIA_BLOCK_SIZE)) + return -1; + + /* Setting the IV to NULL should be same as all zeros IV */ + if (CamelliaSetIV(&cam, NULL) != 0 || + XMEMCMP(cam.reg, ive, CAMELLIA_BLOCK_SIZE)) + return -1; + + /* First parameter should never be null */ + if (CamelliaSetIV(NULL, NULL) == 0) + return -1; + + /* First parameter should never be null, check it fails */ + if (CamelliaSetKey(NULL, k1, sizeof(k1), NULL) == 0) + return -1; + + /* Key should have a size of 16, 24, or 32 */ + if (CamelliaSetKey(&cam, k1, 0, NULL) == 0) + return -1; + + return 0; +} +#endif /* HAVE_CAMELLIA */ + + +int random_test(void) +{ + RNG rng; + byte block[32]; + int ret; + +#ifdef HAVE_CAVIUM + ret = InitRngCavium(&rng, CAVIUM_DEV_ID); + if (ret != 0) return -2007; +#endif + ret = InitRng(&rng); + if (ret != 0) return -39; + + RNG_GenerateBlock(&rng, block, sizeof(block)); + + return 0; +} + + +#ifdef HAVE_NTRU + +byte GetEntropy(ENTROPY_CMD cmd, byte* out); + +byte GetEntropy(ENTROPY_CMD cmd, byte* out) +{ + static RNG rng; + + if (cmd == INIT) { + int ret = InitRng(&rng); + if (ret == 0) + return 1; + else + return 0; + } + + if (out == NULL) + return 0; + + if (cmd == GET_BYTE_OF_ENTROPY) { + RNG_GenerateBlock(&rng, out, 1); + return 1; + } + + if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) { + *out = 1; + return 1; + } + + return 0; +} + +#endif /* HAVE_NTRU */ + +#ifndef NO_RSA + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + #ifdef FREESCALE_MQX + static const char* clientKey = "a:\\certs\\client-key.der"; + static const char* clientCert = "a:\\certs\\client-cert.der"; + #ifdef CYASSL_CERT_GEN + static const char* caKeyFile = "a:\\certs\\ca-key.der"; + static const char* caCertFile = "a:\\certs\\ca-cert.pem"; + #endif + #elif defined(CYASSL_MKD_SHELL) + static char* clientKey = "certs/client-key.der"; + static char* clientCert = "certs/client-cert.der"; + void set_clientKey(char *key) { clientKey = key ; } /* set by shell command */ + void set_clientCert(char *cert) { clientCert = cert ; } /* set by shell command */ + #ifdef CYASSL_CERT_GEN + static char* caKeyFile = "certs/ca-key.der"; + static char* caCertFile = "certs/ca-cert.pem"; + void set_caKeyFile (char * key) { caKeyFile = key ; } /* set by shell command */ + void set_caCertFile(char * cert) { caCertFile = cert ; } /* set by shell command */ + #endif + #else + static const char* clientKey = "./certs/client-key.der"; + static const char* clientCert = "./certs/client-cert.der"; + #ifdef CYASSL_CERT_GEN + static const char* caKeyFile = "./certs/ca-key.der"; + static const char* caCertFile = "./certs/ca-cert.pem"; + #endif + #endif +#endif + + + +#define FOURK_BUF 4096 + +int rsa_test(void) +{ + byte* tmp; + size_t bytes; + RsaKey key; + RNG rng; + word32 idx = 0; + int ret; + byte in[] = "Everyone gets Friday off."; + word32 inLen = (word32)strlen((char*)in); + byte out[256]; + byte plain[256]; +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + FILE* file, * file2; +#endif +#ifdef CYASSL_TEST_CERT + DecodedCert cert; +#endif + + tmp = (byte*)malloc(FOURK_BUF); + if (tmp == NULL) + return -40; + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, client_key_der_1024, sizeof_client_key_der_1024); + bytes = sizeof_client_key_der_1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, client_key_der_2048, sizeof_client_key_der_2048); + bytes = sizeof_client_key_der_2048; +#else + file = fopen(clientKey, "rb"); + + if (!file) + err_sys("can't open ./certs/client-key.der, " + "Please run from CyaSSL home dir", -40); + + bytes = fread(tmp, 1, FOURK_BUF, file); + fclose(file); +#endif /* USE_CERT_BUFFERS */ + +#ifdef HAVE_CAVIUM + RsaInitCavium(&key, CAVIUM_DEV_ID); +#endif + InitRsaKey(&key, 0); + ret = RsaPrivateKeyDecode(tmp, &idx, &key, (word32)bytes); + if (ret != 0) return -41; + + ret = InitRng(&rng); + if (ret != 0) return -42; + + ret = RsaPublicEncrypt(in, inLen, out, sizeof(out), &key, &rng); + if (ret < 0) return -43; + + ret = RsaPrivateDecrypt(out, ret, plain, sizeof(plain), &key); + if (ret < 0) return -44; + + if (memcmp(plain, in, inLen)) return -45; + + ret = RsaSSL_Sign(in, inLen, out, sizeof(out), &key, &rng); + if (ret < 0) return -46; + + memset(plain, 0, sizeof(plain)); + ret = RsaSSL_Verify(out, ret, plain, sizeof(plain), &key); + if (ret < 0) return -47; + + if (memcmp(plain, in, ret)) return -48; + +#if defined(CYASSL_MDK_ARM) + #define sizeof(s) strlen((char *)(s)) +#endif + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, client_cert_der_1024, sizeof_client_cert_der_1024); + bytes = sizeof_client_cert_der_1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, client_cert_der_2048, sizeof_client_cert_der_2048); + bytes = sizeof_client_cert_der_2048; +#else + file2 = fopen(clientCert, "rb"); + if (!file2) + return -49; + + bytes = fread(tmp, 1, FOURK_BUF, file2); + fclose(file2); +#endif + +#ifdef sizeof + #undef sizeof +#endif + +#ifdef CYASSL_TEST_CERT + InitDecodedCert(&cert, tmp, (word32)bytes, 0); + + ret = ParseCert(&cert, CERT_TYPE, NO_VERIFY, 0); + if (ret != 0) return -491; + + FreeDecodedCert(&cert); +#else + (void)bytes; +#endif + + +#ifdef CYASSL_KEY_GEN + { + byte* der; + byte* pem; + int derSz = 0; + int pemSz = 0; + RsaKey derIn; + RsaKey genKey; + FILE* keyFile; + FILE* pemFile; + + InitRsaKey(&genKey, 0); + ret = MakeRsaKey(&genKey, 1024, 65537, &rng); + if (ret != 0) + return -301; + + der = (byte*)malloc(FOURK_BUF); + if (der == NULL) + return -307; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) + return -308; + + derSz = RsaKeyToDer(&genKey, der, FOURK_BUF); + if (derSz < 0) + return -302; + + keyFile = fopen("./key.der", "wb"); + if (!keyFile) + return -303; + ret = (int)fwrite(der, derSz, 1, keyFile); + fclose(keyFile); + + pemSz = DerToPem(der, derSz, pem, FOURK_BUF, PRIVATEKEY_TYPE); + if (pemSz < 0) + return -304; + + pemFile = fopen("./key.pem", "wb"); + if (!pemFile) + return -305; + ret = (int)fwrite(pem, pemSz, 1, pemFile); + fclose(pemFile); + + InitRsaKey(&derIn, 0); + idx = 0; + ret = RsaPrivateKeyDecode(der, &idx, &derIn, derSz); + if (ret != 0) + return -306; + + FreeRsaKey(&derIn); + FreeRsaKey(&genKey); + free(pem); + free(der); + } +#endif /* CYASSL_KEY_GEN */ + + +#ifdef CYASSL_CERT_GEN + /* self signed */ + { + Cert myCert; + byte* derCert; + byte* pem; + FILE* derFile; + FILE* pemFile; + int certSz; + int pemSz; +#ifdef CYASSL_TEST_CERT + DecodedCert decode; +#endif + + derCert = (byte*)malloc(FOURK_BUF); + if (derCert == NULL) + return -309; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) + return -310; + + InitCert(&myCert); + + strncpy(myCert.subject.country, "US", CTC_NAME_SIZE); + strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE); + strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE); + strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE); + strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); + myCert.isCA = 1; + myCert.sigType = CTC_SHA256wRSA; + + certSz = MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng); + if (certSz < 0) + return -401; + +#ifdef CYASSL_TEST_CERT + InitDecodedCert(&decode, derCert, certSz, 0); + ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); + if (ret != 0) + return -402; + FreeDecodedCert(&decode); +#endif + derFile = fopen("./cert.der", "wb"); + if (!derFile) + return -403; + ret = (int)fwrite(derCert, certSz, 1, derFile); + fclose(derFile); + + pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); + if (pemSz < 0) + return -404; + + pemFile = fopen("./cert.pem", "wb"); + if (!pemFile) + return -405; + ret = (int)fwrite(pem, pemSz, 1, pemFile); + fclose(pemFile); + free(pem); + free(derCert); + } + /* CA style */ + { + RsaKey caKey; + Cert myCert; + byte* derCert; + byte* pem; + FILE* derFile; + FILE* pemFile; + int certSz; + int pemSz; + size_t bytes3; + word32 idx3 = 0; + FILE* file3 ; +#ifdef CYASSL_TEST_CERT + DecodedCert decode; +#endif + + derCert = (byte*)malloc(FOURK_BUF); + if (derCert == NULL) + return -311; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) + return -312; + + file3 = fopen(caKeyFile, "rb"); + + if (!file3) + return -412; + + bytes3 = fread(tmp, 1, FOURK_BUF, file3); + fclose(file3); + + InitRsaKey(&caKey, 0); + ret = RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3); + if (ret != 0) return -413; + + InitCert(&myCert); + + strncpy(myCert.subject.country, "US", CTC_NAME_SIZE); + strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE); + strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE); + strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE); + strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); + + ret = SetIssuer(&myCert, caCertFile); + if (ret < 0) + return -405; + + certSz = MakeCert(&myCert, derCert, FOURK_BUF, &key, &rng); + if (certSz < 0) + return -407; + + certSz = SignCert(&myCert, derCert, FOURK_BUF, &caKey, &rng); + if (certSz < 0) + return -408; + + +#ifdef CYASSL_TEST_CERT + InitDecodedCert(&decode, derCert, certSz, 0); + ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); + if (ret != 0) + return -409; + FreeDecodedCert(&decode); +#endif + + derFile = fopen("./othercert.der", "wb"); + if (!derFile) + return -410; + ret = (int)fwrite(derCert, certSz, 1, derFile); + fclose(derFile); + + pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); + if (pemSz < 0) + return -411; + + pemFile = fopen("./othercert.pem", "wb"); + if (!pemFile) + return -412; + ret = (int)fwrite(pem, pemSz, 1, pemFile); + fclose(pemFile); + free(pem); + free(derCert); + FreeRsaKey(&caKey); + } +#ifdef HAVE_NTRU + { + RsaKey caKey; + Cert myCert; + byte* derCert; + byte* pem; + FILE* derFile; + FILE* pemFile; + FILE* caFile; + FILE* ntruPrivFile; + int certSz; + int pemSz; + size_t bytes; + word32 idx = 0; +#ifdef CYASSL_TEST_CERT + DecodedCert decode; +#endif + derCert = (byte*)malloc(FOURK_BUF); + if (derCert == NULL) + return -311; + pem = (byte*)malloc(FOURK_BUF); + if (pem == NULL) + return -312; + + byte public_key[557]; /* sized for EES401EP2 */ + word16 public_key_len; /* no. of octets in public key */ + byte private_key[607]; /* sized for EES401EP2 */ + word16 private_key_len; /* no. of octets in private key */ + DRBG_HANDLE drbg; + static uint8_t const pers_str[] = { + 'C', 'y', 'a', 'S', 'S', 'L', ' ', 't', 'e', 's', 't' + }; + word32 rc = crypto_drbg_instantiate(112, pers_str, sizeof(pers_str), + GetEntropy, &drbg); + if (rc != DRBG_OK) + return -450; + + rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len, + NULL, &private_key_len, NULL); + if (rc != NTRU_OK) + return -451; + + rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len, + public_key, &private_key_len, private_key); + crypto_drbg_uninstantiate(drbg); + + if (rc != NTRU_OK) + return -452; + + caFile = fopen(caKeyFile, "rb"); + + if (!caFile) + return -453; + + bytes = fread(tmp, 1, FOURK_BUF, caFile); + fclose(caFile); + + InitRsaKey(&caKey, 0); + ret = RsaPrivateKeyDecode(tmp, &idx, &caKey, (word32)bytes); + if (ret != 0) return -454; + + InitCert(&myCert); + + strncpy(myCert.subject.country, "US", CTC_NAME_SIZE); + strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE); + strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE); + strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE); + strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE); + strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE); + strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE); + + ret = SetIssuer(&myCert, caCertFile); + if (ret < 0) + return -455; + + certSz = MakeNtruCert(&myCert, derCert, FOURK_BUF, public_key, + public_key_len, &rng); + if (certSz < 0) + return -456; + + certSz = SignCert(&myCert, derCert, FOURK_BUF, &caKey, &rng); + if (certSz < 0) + return -457; + + +#ifdef CYASSL_TEST_CERT + InitDecodedCert(&decode, derCert, certSz, 0); + ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0); + if (ret != 0) + return -458; + FreeDecodedCert(&decode); +#endif + derFile = fopen("./ntru-cert.der", "wb"); + if (!derFile) + return -459; + ret = fwrite(derCert, certSz, 1, derFile); + fclose(derFile); + + pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE); + if (pemSz < 0) + return -460; + + pemFile = fopen("./ntru-cert.pem", "wb"); + if (!pemFile) + return -461; + ret = fwrite(pem, pemSz, 1, pemFile); + fclose(pemFile); + + ntruPrivFile = fopen("./ntru-key.raw", "wb"); + if (!ntruPrivFile) + return -462; + ret = fwrite(private_key, private_key_len, 1, ntruPrivFile); + fclose(ntruPrivFile); + free(pem); + free(derCert); + FreeRsaKey(&caKey); + } +#endif /* HAVE_NTRU */ +#endif /* CYASSL_CERT_GEN */ + + FreeRsaKey(&key); +#ifdef HAVE_CAVIUM + RsaFreeCavium(&key); +#endif + free(tmp); + + return 0; +} + +#endif + + +#ifndef NO_DH + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + #ifdef FREESCALE_MQX + static const char* dhKey = "a:\certs\\dh2048.der"; + #else + static const char* dhKey = "./certs/dh2048.der"; + #endif +#endif + +int dh_test(void) +{ + int ret; + word32 bytes; + word32 idx = 0, privSz, pubSz, privSz2, pubSz2, agreeSz, agreeSz2; + byte tmp[1024]; + byte priv[256]; + byte pub[256]; + byte priv2[256]; + byte pub2[256]; + byte agree[256]; + byte agree2[256]; + DhKey key; + DhKey key2; + RNG rng; + + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024); + bytes = sizeof_dh_key_der_1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, dh_key_der_2048, sizeof_dh_key_der_2048); + bytes = sizeof_dh_key_der_2048; +#else + FILE* file = fopen(dhKey, "rb"); + + if (!file) + return -50; + + bytes = (word32) fread(tmp, 1, sizeof(tmp), file); + fclose(file); +#endif /* USE_CERT_BUFFERS */ + + InitDhKey(&key); + InitDhKey(&key2); + ret = DhKeyDecode(tmp, &idx, &key, bytes); + if (ret != 0) + return -51; + + idx = 0; + ret = DhKeyDecode(tmp, &idx, &key2, bytes); + if (ret != 0) + return -52; + + ret = InitRng(&rng); + if (ret != 0) + return -53; + + ret = DhGenerateKeyPair(&key, &rng, priv, &privSz, pub, &pubSz); + ret += DhGenerateKeyPair(&key2, &rng, priv2, &privSz2, pub2, &pubSz2); + if (ret != 0) + return -54; + + ret = DhAgree(&key, agree, &agreeSz, priv, privSz, pub2, pubSz2); + ret += DhAgree(&key2, agree2, &agreeSz2, priv2, privSz2, pub, pubSz); + if (ret != 0) + return -55; + + if (memcmp(agree, agree2, agreeSz)) + return -56; + + FreeDhKey(&key); + FreeDhKey(&key2); + + return 0; +} + +#endif /* NO_DH */ + + +#ifndef NO_DSA + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + #ifdef FREESCALE_MQX + static const char* dsaKey = "a:\\certs\\dsa2048.der"; + #else + static const char* dsaKey = "./certs/dsa2048.der"; + #endif +#endif + +int dsa_test(void) +{ + int ret, answer; + word32 bytes; + word32 idx = 0; + byte tmp[1024]; + DsaKey key; + RNG rng; + Sha sha; + byte hash[SHA_DIGEST_SIZE]; + byte signature[40]; + + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, dsa_key_der_1024, sizeof_dsa_key_der_1024); + bytes = sizeof_dsa_key_der_1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, dsa_key_der_2048, sizeof_dsa_key_der_2048); + bytes = sizeof_dsa_key_der_2048; +#else + FILE* file = fopen(dsaKey, "rb"); + + if (!file) + return -60; + + bytes = (word32) fread(tmp, 1, sizeof(tmp), file); + fclose(file); +#endif /* USE_CERT_BUFFERS */ + + InitSha(&sha); + ShaUpdate(&sha, tmp, bytes); + ShaFinal(&sha, hash); + + InitDsaKey(&key); + ret = DsaPrivateKeyDecode(tmp, &idx, &key, bytes); + if (ret != 0) return -61; + + ret = InitRng(&rng); + if (ret != 0) return -62; + + ret = DsaSign(hash, signature, &key, &rng); + if (ret != 0) return -63; + + ret = DsaVerify(hash, signature, &key, &answer); + if (ret != 0) return -64; + if (answer != 1) return -65; + + FreeDsaKey(&key); + + return 0; +} + +#endif /* NO_DSA */ + + +#ifdef OPENSSL_EXTRA + +int openssl_test(void) +{ + EVP_MD_CTX md_ctx; + testVector a, b, c, d, e, f; + byte hash[SHA_DIGEST_SIZE*4]; /* max size */ + + (void)e; + (void)f; + + a.input = "1234567890123456789012345678901234567890123456789012345678" + "9012345678901234567890"; + a.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6" + "\x7a"; + a.inLen = strlen(a.input); + a.outLen = MD5_DIGEST_SIZE; + + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_md5()); + + EVP_DigestUpdate(&md_ctx, a.input, a.inLen); + EVP_DigestFinal(&md_ctx, hash, 0); + + if (memcmp(hash, a.output, MD5_DIGEST_SIZE) != 0) + return -71; + + b.input = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" + "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa" + "aaaaaaaaaa"; + b.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7" + "\x53\x99\x5E\x26\xA0"; + b.inLen = strlen(b.input); + b.outLen = SHA_DIGEST_SIZE; + + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_sha1()); + + EVP_DigestUpdate(&md_ctx, b.input, b.inLen); + EVP_DigestFinal(&md_ctx, hash, 0); + + if (memcmp(hash, b.output, SHA_DIGEST_SIZE) != 0) + return -72; + + + d.input = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; + d.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60" + "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB" + "\x06\xC1"; + d.inLen = strlen(d.input); + d.outLen = SHA256_DIGEST_SIZE; + + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_sha256()); + + EVP_DigestUpdate(&md_ctx, d.input, d.inLen); + EVP_DigestFinal(&md_ctx, hash, 0); + + if (memcmp(hash, d.output, SHA256_DIGEST_SIZE) != 0) + return -78; + +#ifdef CYASSL_SHA384 + + e.input = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi" + "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu"; + e.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b" + "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0" + "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91" + "\x74\x60\x39"; + e.inLen = strlen(e.input); + e.outLen = SHA384_DIGEST_SIZE; + + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_sha384()); + + EVP_DigestUpdate(&md_ctx, e.input, e.inLen); + EVP_DigestFinal(&md_ctx, hash, 0); + + if (memcmp(hash, e.output, SHA384_DIGEST_SIZE) != 0) + return -79; + +#endif /* CYASSL_SHA384 */ + + +#ifdef CYASSL_SHA512 + + f.input = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi" + "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu"; + f.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14" + "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88" + "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4" + "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b" + "\x87\x4b\xe9\x09"; + f.inLen = strlen(f.input); + f.outLen = SHA512_DIGEST_SIZE; + + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_sha512()); + + EVP_DigestUpdate(&md_ctx, f.input, f.inLen); + EVP_DigestFinal(&md_ctx, hash, 0); + + if (memcmp(hash, f.output, SHA512_DIGEST_SIZE) != 0) + return -80; + +#endif /* CYASSL_SHA512 */ + + + if (RAND_bytes(hash, sizeof(hash)) != 1) + return -73; + + c.input = "what do ya want for nothing?"; + c.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7" + "\x38"; + c.inLen = strlen(c.input); + c.outLen = MD5_DIGEST_SIZE; + + HMAC(EVP_md5(), "Jefe", 4, (byte*)c.input, (int)c.inLen, hash, 0); + + if (memcmp(hash, c.output, MD5_DIGEST_SIZE) != 0) + return -74; + + { /* des test */ + const byte vector[] = { /* "now is the time for all " w/o trailing 0 */ + 0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74, + 0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20, + 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 + }; + + byte plain[24]; + byte cipher[24]; + + const_DES_cblock key = + { + 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef + }; + + DES_cblock iv = + { + 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef + }; + + DES_key_schedule sched; + + const byte verify[] = + { + 0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8, + 0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73, + 0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b + }; + + DES_key_sched(&key, &sched); + + DES_cbc_encrypt(vector, cipher, sizeof(vector), &sched, &iv, DES_ENCRYPT); + DES_cbc_encrypt(cipher, plain, sizeof(vector), &sched, &iv, DES_DECRYPT); + + if (memcmp(plain, vector, sizeof(vector)) != 0) + return -75; + + if (memcmp(cipher, verify, sizeof(verify)) != 0) + return -76; + + /* test changing iv */ + DES_ncbc_encrypt(vector, cipher, 8, &sched, &iv, DES_ENCRYPT); + DES_ncbc_encrypt(vector + 8, cipher + 8, 16, &sched, &iv, DES_ENCRYPT); + + if (memcmp(cipher, verify, sizeof(verify)) != 0) + return -77; + + } /* end des test */ + + { /* evp_cipher test */ + EVP_CIPHER_CTX ctx; + + + const byte msg[] = { /* "Now is the time for all " w/o trailing 0 */ + 0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74, + 0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20, + 0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20 + }; + + const byte verify[] = + { + 0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53, + 0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb + }; + + byte key[] = "0123456789abcdef "; /* align */ + byte iv[] = "1234567890abcdef "; /* align */ + + byte cipher[AES_BLOCK_SIZE * 4]; + byte plain [AES_BLOCK_SIZE * 4]; + + EVP_CIPHER_CTX_init(&ctx); + if (EVP_CipherInit(&ctx, EVP_aes_128_cbc(), key, iv, 1) == 0) + return -81; + + if (EVP_Cipher(&ctx, cipher, (byte*)msg, 16) == 0) + return -82; + + if (memcmp(cipher, verify, AES_BLOCK_SIZE)) + return -83; + + EVP_CIPHER_CTX_init(&ctx); + if (EVP_CipherInit(&ctx, EVP_aes_128_cbc(), key, iv, 0) == 0) + return -84; + + if (EVP_Cipher(&ctx, plain, cipher, 16) == 0) + return -85; + + if (memcmp(plain, msg, AES_BLOCK_SIZE)) + return -86; + + + } /* end evp_cipher test */ + + return 0; +} + +#endif /* OPENSSL_EXTRA */ + + +#ifndef NO_PWDBASED + +int pkcs12_test(void) +{ + const byte passwd[] = { 0x00, 0x73, 0x00, 0x6d, 0x00, 0x65, 0x00, 0x67, + 0x00, 0x00 }; + const byte salt[] = { 0x0a, 0x58, 0xCF, 0x64, 0x53, 0x0d, 0x82, 0x3f }; + + const byte passwd2[] = { 0x00, 0x71, 0x00, 0x75, 0x00, 0x65, 0x00, 0x65, + 0x00, 0x67, 0x00, 0x00 }; + const byte salt2[] = { 0x16, 0x82, 0xC0, 0xfC, 0x5b, 0x3f, 0x7e, 0xc5 }; + byte derived[64]; + + const byte verify[] = { + 0x8A, 0xAA, 0xE6, 0x29, 0x7B, 0x6C, 0xB0, 0x46, + 0x42, 0xAB, 0x5B, 0x07, 0x78, 0x51, 0x28, 0x4E, + 0xB7, 0x12, 0x8F, 0x1A, 0x2A, 0x7F, 0xBC, 0xA3 + }; + + const byte verify2[] = { + 0x48, 0x3D, 0xD6, 0xE9, 0x19, 0xD7, 0xDE, 0x2E, + 0x8E, 0x64, 0x8B, 0xA8, 0xF8, 0x62, 0xF3, 0xFB, + 0xFB, 0xDC, 0x2B, 0xCB, 0x2C, 0x02, 0x95, 0x7F + }; + + int id = 1; + int kLen = 24; + int iterations = 1; + int ret = PKCS12_PBKDF(derived, passwd, sizeof(passwd), salt, 8, iterations, + kLen, SHA, id); + + if (ret < 0) + return -103; + + if ( (ret = memcmp(derived, verify, kLen)) != 0) + return -104; + + iterations = 1000; + ret = PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8, iterations, + kLen, SHA, id); + if (ret < 0) + return -105; + + if ( (ret = memcmp(derived, verify2, 24)) != 0) + return -106; + + return 0; +} + + +int pbkdf2_test(void) +{ + char passwd[] = "password"; + const byte salt[] = { 0x78, 0x57, 0x8E, 0x5a, 0x5d, 0x63, 0xcb, 0x06 }; + int iterations = 2048; + int kLen = 24; + byte derived[64]; + + const byte verify[] = { + 0xBF, 0xDE, 0x6B, 0xE9, 0x4D, 0xF7, 0xE1, 0x1D, 0xD4, 0x09, 0xBC, 0xE2, + 0x0A, 0x02, 0x55, 0xEC, 0x32, 0x7C, 0xB9, 0x36, 0xFF, 0xE9, 0x36, 0x43 + + }; + + PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations, + kLen, SHA); + + if (memcmp(derived, verify, sizeof(verify)) != 0) + return -102; + + return 0; +} + + +int pbkdf1_test(void) +{ + char passwd[] = "password"; + const byte salt[] = { 0x78, 0x57, 0x8E, 0x5a, 0x5d, 0x63, 0xcb, 0x06 }; + int iterations = 1000; + int kLen = 16; + byte derived[16]; + + const byte verify[] = { + 0xDC, 0x19, 0x84, 0x7E, 0x05, 0xC6, 0x4D, 0x2F, 0xAF, 0x10, 0xEB, 0xFB, + 0x4A, 0x3D, 0x2A, 0x20 + }; + + PBKDF1(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations, + kLen, SHA); + + if (memcmp(derived, verify, sizeof(verify)) != 0) + return -101; + + return 0; +} + + +int pwdbased_test(void) +{ + int ret = pbkdf1_test(); + ret += pbkdf2_test(); + + return ret + pkcs12_test(); +} + +#endif /* NO_PWDBASED */ + +#if defined(HAVE_HKDF) && (!defined(NO_SHA) || !defined(NO_SHA256)) + +int hkdf_test(void) +{ + int ret; + int L = 42; + byte okm1[42]; + byte ikm1[22] = { 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, + 0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0b }; + byte salt1[13] ={ 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c }; + byte info1[10] ={ 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xf8, 0xf9 }; + byte res1[42] = { 0x0a, 0xc1, 0xaf, 0x70, 0x02, 0xb3, 0xd7, 0x61, + 0xd1, 0xe5, 0x52, 0x98, 0xda, 0x9d, 0x05, 0x06, + 0xb9, 0xae, 0x52, 0x05, 0x72, 0x20, 0xa3, 0x06, + 0xe0, 0x7b, 0x6b, 0x87, 0xe8, 0xdf, 0x21, 0xd0, + 0xea, 0x00, 0x03, 0x3d, 0xe0, 0x39, 0x84, 0xd3, + 0x49, 0x18 }; + byte res2[42] = { 0x08, 0x5a, 0x01, 0xea, 0x1b, 0x10, 0xf3, 0x69, + 0x33, 0x06, 0x8b, 0x56, 0xef, 0xa5, 0xad, 0x81, + 0xa4, 0xf1, 0x4b, 0x82, 0x2f, 0x5b, 0x09, 0x15, + 0x68, 0xa9, 0xcd, 0xd4, 0xf1, 0x55, 0xfd, 0xa2, + 0xc2, 0x2e, 0x42, 0x24, 0x78, 0xd3, 0x05, 0xf3, + 0xf8, 0x96 }; + byte res3[42] = { 0x8d, 0xa4, 0xe7, 0x75, 0xa5, 0x63, 0xc1, 0x8f, + 0x71, 0x5f, 0x80, 0x2a, 0x06, 0x3c, 0x5a, 0x31, + 0xb8, 0xa1, 0x1f, 0x5c, 0x5e, 0xe1, 0x87, 0x9e, + 0xc3, 0x45, 0x4e, 0x5f, 0x3c, 0x73, 0x8d, 0x2d, + 0x9d, 0x20, 0x13, 0x95, 0xfa, 0xa4, 0xb6, 0x1a, + 0x96, 0xc8 }; + byte res4[42] = { 0x3c, 0xb2, 0x5f, 0x25, 0xfa, 0xac, 0xd5, 0x7a, + 0x90, 0x43, 0x4f, 0x64, 0xd0, 0x36, 0x2f, 0x2a, + 0x2d, 0x2d, 0x0a, 0x90, 0xcf, 0x1a, 0x5a, 0x4c, + 0x5d, 0xb0, 0x2d, 0x56, 0xec, 0xc4, 0xc5, 0xbf, + 0x34, 0x00, 0x72, 0x08, 0xd5, 0xb8, 0x87, 0x18, + 0x58, 0x65 }; + + (void)res1; + (void)res2; + (void)res3; + (void)res4; + +#ifndef NO_SHA + ret = HKDF(SHA, ikm1, 22, NULL, 0, NULL, 0, okm1, L); + if (ret != 0) + return -2001; + + if (memcmp(okm1, res1, L) != 0) + return -2002; + + ret = HKDF(SHA, ikm1, 11, salt1, 13, info1, 10, okm1, L); + if (ret != 0) + return -2003; + + if (memcmp(okm1, res2, L) != 0) + return -2004; +#endif /* NO_SHA */ + +#ifndef NO_SHA256 + ret = HKDF(SHA256, ikm1, 22, NULL, 0, NULL, 0, okm1, L); + if (ret != 0) + return -2005; + + if (memcmp(okm1, res3, L) != 0) + return -2006; + + ret = HKDF(SHA256, ikm1, 22, salt1, 13, info1, 10, okm1, L); + if (ret != 0) + return -2007; + + if (memcmp(okm1, res4, L) != 0) + return -2007; +#endif /* NO_SHA256 */ + + return 0; +} + +#endif /* HAVE_HKDF */ + + +#ifdef HAVE_ECC + +int ecc_test(void) +{ + RNG rng; + byte sharedA[1024]; + byte sharedB[1024]; + byte sig[1024]; + byte digest[20]; + byte exportBuf[1024]; + word32 x, y; + int i, verify, ret; + ecc_key userA, userB, pubKey; + + ret = InitRng(&rng); + if (ret != 0) + return -1001; + + ecc_init(&userA); + ecc_init(&userB); + ecc_init(&pubKey); + + ret = ecc_make_key(&rng, 32, &userA); + ret = ecc_make_key(&rng, 32, &userB); + + if (ret != 0) + return -1002; + + x = sizeof(sharedA); + ret = ecc_shared_secret(&userA, &userB, sharedA, &x); + + y = sizeof(sharedB); + ret = ecc_shared_secret(&userB, &userA, sharedB, &y); + + if (ret != 0) + return -1003; + + if (y != x) + return -1004; + + if (memcmp(sharedA, sharedB, x)) + return -1005; + + x = sizeof(exportBuf); + ret = ecc_export_x963(&userA, exportBuf, &x); + if (ret != 0) + return -1006; + + ret = ecc_import_x963(exportBuf, x, &pubKey); + + if (ret != 0) + return -1007; + + y = sizeof(sharedB); + ret = ecc_shared_secret(&userB, &pubKey, sharedB, &y); + + if (ret != 0) + return -1008; + + if (memcmp(sharedA, sharedB, y)) + return -1010; + + /* test DSA sign hash */ + for (i = 0; i < (int)sizeof(digest); i++) + digest[i] = i; + + x = sizeof(sig); + ret = ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &userA); + + verify = 0; + ret = ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &userA); + + if (ret != 0) + return -1011; + + if (verify != 1) + return -1012; + + x = sizeof(exportBuf); + ret = ecc_export_private_only(&userA, exportBuf, &x); + if (ret != 0) + return -1013; + + ecc_free(&pubKey); + ecc_free(&userB); + ecc_free(&userA); + + return 0; +} + +#endif /* HAVE_ECC */ + +#ifdef HAVE_LIBZ + +const byte sample_text[] = + "Biodiesel cupidatat marfa, cliche aute put a bird on it incididunt elit\n" + "polaroid. Sunt tattooed bespoke reprehenderit. Sint twee organic id\n" + "marfa. Commodo veniam ad esse gastropub. 3 wolf moon sartorial vero,\n" + "plaid delectus biodiesel squid +1 vice. Post-ironic keffiyeh leggings\n" + "selfies cray fap hoodie, forage anim. Carles cupidatat shoreditch, VHS\n" + "small batch meggings kogi dolore food truck bespoke gastropub.\n" + "\n" + "Terry richardson adipisicing actually typewriter tumblr, twee whatever\n" + "four loko you probably haven't heard of them high life. Messenger bag\n" + "whatever tattooed deep v mlkshk. Brooklyn pinterest assumenda chillwave\n" + "et, banksy ullamco messenger bag umami pariatur direct trade forage.\n" + "Typewriter culpa try-hard, pariatur sint brooklyn meggings. Gentrify\n" + "food truck next level, tousled irony non semiotics PBR ethical anim cred\n" + "readymade. Mumblecore brunch lomo odd future, portland organic terry\n" + "richardson elit leggings adipisicing ennui raw denim banjo hella. Godard\n" + "mixtape polaroid, pork belly readymade organic cray typewriter helvetica\n" + "four loko whatever street art yr farm-to-table.\n" + "\n" + "Vinyl keytar vice tofu. Locavore you probably haven't heard of them pug\n" + "pickled, hella tonx labore truffaut DIY mlkshk elit cosby sweater sint\n" + "et mumblecore. Elit swag semiotics, reprehenderit DIY sartorial nisi ugh\n" + "nesciunt pug pork belly wayfarers selfies delectus. Ethical hoodie\n" + "seitan fingerstache kale chips. Terry richardson artisan williamsburg,\n" + "eiusmod fanny pack irony tonx ennui lo-fi incididunt tofu YOLO\n" + "readymade. 8-bit sed ethnic beard officia. Pour-over iphone DIY butcher,\n" + "ethnic art party qui letterpress nisi proident jean shorts mlkshk\n" + "locavore.\n" + "\n" + "Narwhal flexitarian letterpress, do gluten-free voluptate next level\n" + "banh mi tonx incididunt carles DIY. Odd future nulla 8-bit beard ut\n" + "cillum pickled velit, YOLO officia you probably haven't heard of them\n" + "trust fund gastropub. Nisi adipisicing tattooed, Austin mlkshk 90's\n" + "small batch american apparel. Put a bird on it cosby sweater before they\n" + "sold out pork belly kogi hella. Street art mollit sustainable polaroid,\n" + "DIY ethnic ea pug beard dreamcatcher cosby sweater magna scenester nisi.\n" + "Sed pork belly skateboard mollit, labore proident eiusmod. Sriracha\n" + "excepteur cosby sweater, anim deserunt laborum eu aliquip ethical et\n" + "neutra PBR selvage.\n" + "\n" + "Raw denim pork belly truffaut, irony plaid sustainable put a bird on it\n" + "next level jean shorts exercitation. Hashtag keytar whatever, nihil\n" + "authentic aliquip disrupt laborum. Tattooed selfies deserunt trust fund\n" + "wayfarers. 3 wolf moon synth church-key sartorial, gastropub leggings\n" + "tattooed. Labore high life commodo, meggings raw denim fingerstache pug\n" + "trust fund leggings seitan forage. Nostrud ullamco duis, reprehenderit\n" + "incididunt flannel sustainable helvetica pork belly pug banksy you\n" + "probably haven't heard of them nesciunt farm-to-table. Disrupt nostrud\n" + "mollit magna, sriracha sartorial helvetica.\n" + "\n" + "Nulla kogi reprehenderit, skateboard sustainable duis adipisicing viral\n" + "ad fanny pack salvia. Fanny pack trust fund you probably haven't heard\n" + "of them YOLO vice nihil. Keffiyeh cray lo-fi pinterest cardigan aliqua,\n" + "reprehenderit aute. Culpa tousled williamsburg, marfa lomo actually anim\n" + "skateboard. Iphone aliqua ugh, semiotics pariatur vero readymade\n" + "organic. Marfa squid nulla, in laborum disrupt laboris irure gastropub.\n" + "Veniam sunt food truck leggings, sint vinyl fap.\n" + "\n" + "Hella dolore pork belly, truffaut carles you probably haven't heard of\n" + "them PBR helvetica in sapiente. Fashion axe ugh bushwick american\n" + "apparel. Fingerstache sed iphone, jean shorts blue bottle nisi bushwick\n" + "flexitarian officia veniam plaid bespoke fap YOLO lo-fi. Blog\n" + "letterpress mumblecore, food truck id cray brooklyn cillum ad sed.\n" + "Assumenda chambray wayfarers vinyl mixtape sustainable. VHS vinyl\n" + "delectus, culpa williamsburg polaroid cliche swag church-key synth kogi\n" + "magna pop-up literally. Swag thundercats ennui shoreditch vegan\n" + "pitchfork neutra truffaut etsy, sed single-origin coffee craft beer.\n" + "\n" + "Odio letterpress brooklyn elit. Nulla single-origin coffee in occaecat\n" + "meggings. Irony meggings 8-bit, chillwave lo-fi adipisicing cred\n" + "dreamcatcher veniam. Put a bird on it irony umami, trust fund bushwick\n" + "locavore kale chips. Sriracha swag thundercats, chillwave disrupt\n" + "tousled beard mollit mustache leggings portland next level. Nihil esse\n" + "est, skateboard art party etsy thundercats sed dreamcatcher ut iphone\n" + "swag consectetur et. Irure skateboard banjo, nulla deserunt messenger\n" + "bag dolor terry richardson sapiente.\n"; + + +int compress_test(void) +{ + int ret = 0; + word32 dSz = sizeof(sample_text); + word32 cSz = (dSz + (word32)(dSz * 0.001) + 12); + byte *c = NULL; + byte *d = NULL; + + c = calloc(cSz, sizeof(byte)); + d = calloc(dSz, sizeof(byte)); + + if (c == NULL || d == NULL) + ret = -300; + + if (ret == 0 && (ret = Compress(c, cSz, sample_text, dSz, 0)) < 0) + ret = -301; + + if (ret > 0) { + cSz = (word32)ret; + ret = 0; + } + + if (ret == 0 && DeCompress(d, dSz, c, cSz) != (int)dSz) + ret = -302; + + if (ret == 0 && memcmp(d, sample_text, dSz)) + ret = -303; + + if (c) free(c); + if (d) free(d); + + return ret; +} + +#endif /* HAVE_LIBZ */ + +#endif /* NO_CRYPT_TEST */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt b/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt new file mode 100644 index 000000000..b541cb662 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/Abstract.txt @@ -0,0 +1,89 @@ +This program gives wolfCrypt and CyaSSL library demo. + +In order to run the demo, +Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory. +For demo configuration, refer config-Crypt.h and config-CyaSSL.h. + +After download and start the execution, you can type in commands through the +Debug(printf) viewer. + +time [-d date][-t time] Set/Get RTC: The time is used for certificate validation. +test wolfCrypt Simple test suite +benchmark wolfCrypt Simple benchmark +server& simple server in background mode +client simple client +echoserver& echo server in background mode +echoclient echo client +server/client -h help for server/client command + + +=== Typical Command Usage Scenario === + +Starting Shell +>time -d 9/23/2013 +>time +Date: 9/23/2013, Time: 00:38:31 +>test +MD5 test passed! +MD4 test passed! +SHA test passed! +... + +>benchmark +AES 25 kB took 0.025 seconds, 0.96 MB/s +ARC4 25 kB took 0.006 seconds, 3.83 MB/s +... + +DH 2048 key agreement 685.93 milliseconds, avg over 1 iterations + +>echoserver& +"echoserver" is running with the background mode. + +>echoclient +ABCDEFG +ABCDEFG +WXYZ +WXYZ +quit +sending server shutdown command: quit! +client sent quit command: shutting down! + +>server& +"server" is running with the background mode. + +>client +peer's cert info: + issuer : /C=... + subject: /C=... + serial number:02 +SSL version is TLSv1.2 +SSL cipher suite is TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 +peer's cert info: + issuer : /C=... + subject: /C=... + serial number:... +SSL version is TLSv1.2 +SSL cipher suite is TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 +Client message: hello cyassl! +Server response: I hear you fa shizzle! + +>client -h 192.168.2.100 -p 443 -g -v 0 +peer's cert info: + issuer : /CN=... + subject: /CN=... + serial number:44:39:... +SSL version is SSLv3 +SSL cipher suite is SSL_RSA_WITH_RC4_128_SHA +SSL connect ok, sending GET... +... +=== + +For the hardware crypt on config-Crypt.h, download +STSW-STM32062: STM32F2xx standard peripherals library at +http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to + {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib + + +Support +------- +Please send questions or comments to support@wolfssl.com diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvguix.kojo b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvguix.kojo new file mode 100644 index 000000000..6bb8a7870 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvguix.kojo @@ -0,0 +1,1342 @@ + + + + -4.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 1920 + 1080 + + + + + + + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx new file mode 100644 index 000000000..4084d9ab1 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvoptx @@ -0,0 +1,1530 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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-FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 ) -FN1 -FC1000 -FD20000000 -FF0STM32F2xx_1024 -FL0100000 -FS08000000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm) + + + + + + 0 + 1 + str[i] + + + 1 + 1 + str + + + + + 1 + 3 + 0x20003d9e + + + + + 2 + 8 + 0x8004dc8 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + + + + + + + + Source + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + 0 + 57 + 80 + 0 + .\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 13 + 0 + 0 + 0 + 0 + .\shell.c + shell.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\test.c + test.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\benchmark.c + benchmark.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\client.c + client.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + .\echoclient.c + echoclient.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\echoserver.c + echoserver.c + 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C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c + sha256.c + 1 + 0 + + + 9 + 69 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c + sha512.c + 1 + 0 + + + 9 + 70 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + tfm.c + 1 + 0 + + + 9 + 71 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\crl.c + crl.c + 1 + 0 + + + 9 + 72 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\internal.c + internal.c + 1 + 0 + + + 9 + 73 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\io.c + io.c + 1 + 0 + + + 9 + 74 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\keys.c + keys.c + 1 + 0 + + + 9 + 75 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ocsp.c + ocsp.c + 1 + 0 + + + 9 + 76 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\sniffer.c + sniffer.c + 1 + 0 + + + 9 + 77 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ssl.c + ssl.c + 1 + 0 + + + 9 + 78 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\tls.c + tls.c + 1 + 0 + + + + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx new file mode 100644 index 000000000..05a58e1ec --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full.uvprojx @@ -0,0 +1,1122 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + CyaSSL-Full + 0x4 + ARM-ADS + + + STM32F207IG + STMicroelectronics + IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)) + 0 + $$Device:STM32F207IG$Device\Include\stm32f2xx.h + + + + + + + + + + $$Device:STM32F207IG$SVD\STM32F20x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Object\ + CyaSSL-Full + 1 + 0 + 0 + 1 + 1 + .\Object\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -REMAP -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + + 0 + 8 + + + + + + + + + + + + + .\STM32_SWO.ini + BIN\ULP2CM3.DLL + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 0 + BIN\ULP2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + HAVE_CONFIG_H MDK_CONF_CYASSL + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + Source + + + main.c + 1 + .\main.c + + + shell.c + 1 + .\shell.c + + + test.c + 1 + .\test.c + + + benchmark.c + 1 + .\benchmark.c + + + client.c + 1 + .\client.c + + + echoclient.c + 1 + .\echoclient.c + + + echoserver.c + 1 + .\echoserver.c + + + server.c + 1 + .\server.c + + + cert_data.c + 1 + .\cert_data.c + + + + + Configuration + + + config-CyaSSL.h + 5 + .\RTE\wolfSSL\config-CyaSSL.h + + + config-Crypt.h + 5 + .\RTE\wolfSSL\config-Crypt.h + + + + + Documentation + + + Abstract.txt + 5 + .\Abstract.txt + + + + + ::CMSIS + + + RTX_CM3.lib + 4 + C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib + + + RTX_Conf_CM.c + 1 + RTE\CMSIS\RTX_Conf_CM.c + + + + + ::Device + + + DMA_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c + + + GPIO_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c + + + RTE_Device.h + 5 + RTE\Device\STM32F207IG\RTE_Device.h + + + startup_stm32f2xx.s + 2 + RTE\Device\STM32F207IG\startup_stm32f2xx.s + + + system_stm32f2xx.c + 1 + RTE\Device\STM32F207IG\system_stm32f2xx.c + + + + + ::Drivers + + + PHY_ST802RT1.c + 1 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c + + + EMAC_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c + + + MCI_STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c + + + + + ::File System + + + FS_LFN_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib + + + FS_Config.c + 1 + RTE\File_System\FS_Config.c + + + FS_Config_MC_0.h + 5 + RTE\File_System\FS_Config_MC_0.h + + + + + ::Network + + + Net_Dbg_CM3_L.lib + 4 + C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib + + + Net_Config.c + 1 + RTE\Network\Net_Config.c + + + Net_Config_BSD.h + 5 + RTE\Network\Net_Config_BSD.h + + + Net_Config_DNS_Client.h + 5 + RTE\Network\Net_Config_DNS_Client.h + + + Net_Config_ETH_0.h + 5 + RTE\Network\Net_Config_ETH_0.h + + + Net_Config_TCP.h + 5 + RTE\Network\Net_Config_TCP.h + + + Net_Config_UDP.h + 5 + RTE\Network\Net_Config_UDP.h + + + Net_Debug.c + 1 + RTE\Network\Net_Debug.c + + + + + ::wolfSSL + + + config-Crypt.h + 5 + RTE\wolfSSL\config-Crypt.h + + + config-CyaSSL.h + 5 + RTE\wolfSSL\config-CyaSSL.h + + + cyassl_MDK_ARM.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c + + + time-STM32F2xx.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c + + + aes.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\aes.c + + + arc4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\arc4.c + + + asm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asm.c + + + asn.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\asn.c + + + blake2b.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\blake2b.c + + + camellia.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\camellia.c + + + coding.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\coding.c + + + compress.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\compress.c + + + des3.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\des3.c + + + dh.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dh.c + + + dsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\dsa.c + + + ecc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc.c + + + ecc_fp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ecc_fp.c + + + error.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\error.c + + + hc128.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hc128.c + + + hmac.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\hmac.c + + + integer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\integer.c + + + logging.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\logging.c + + + md2.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md2.c + + + md4.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md4.c + + + md5.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\md5.c + + + memory.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\memory.c + + + misc.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\misc.c + + + port.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\port.c + + + pwdbased.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\pwdbased.c + + + rabbit.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rabbit.c + + + random.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\random.c + + + ripemd.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\ripemd.c + + + rsa.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\rsa.c + + + sha.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha.c + + + sha256.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha256.c + + + sha512.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\sha512.c + + + tfm.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\ctaocrypt\src\tfm.c + + + crl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\crl.c + + + internal.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\internal.c + + + io.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\io.c + + + keys.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\keys.c + + + ocsp.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ocsp.c + + + sniffer.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\sniffer.c + + + ssl.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\ssl.c + + + tls.c + 1 + C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.1\cyassl\src\tls.c + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Conf_CM.c + + + + + + + + RTE\Device\STM32F207IG\RTE_Device.h + + + + + + + + RTE\Device\STM32F207IG\startup_stm32f2xx.s + + + + + + + + RTE\Device\STM32F207IG\system_stm32f2xx.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + RTE\File_System\FS_Config_MC_0.h + + + + + + + + RTE\Network\Net_Config.c + + + + + + + + RTE\Network\Net_Config_BSD.h + + + + + + + + RTE\Network\Net_Config_DNS_Client.h + + + + + + + + RTE\Network\Net_Config_ETH_0.h + + + + + + + + RTE\Network\Net_Config_TCP.h + + + + + + + + RTE\Network\Net_Config_UDP.h + + + + + + + + RTE\Network\Net_Debug.c + + + + + + + + RTE\Other\config-RTX-TCP-FS.h + + + + + + RTE\Other\config.h + + + + + + RTE\wolfSSL\config-Crypt.h + + + + + + + + RTE\wolfSSL\config-CyaSSL.h + + + + + + + + RTE\wolfSSL\config.h + + + + + + + + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full_CyaSSL-Full.dep b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full_CyaSSL-Full.dep new file mode 100644 index 000000000..966cbe457 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/CyaSSL-Full_CyaSSL-Full.dep @@ -0,0 +1,79 @@ +Dependencies for Project 'CyaSSL-Full', Target 'CyaSSL-Full': (DO NOT MODIFY !) +F (.\main.c)(0x52675C4A)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\main.o --omf_browse .\object\main.crf --depend .\object\main.d) +F (.\shell.c)(0x523B984C)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\shell.o --omf_browse .\object\shell.crf --depend .\object\shell.d) +F (.\test.c)(0x524E6E34)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\test.o --omf_browse .\object\test.crf --depend .\object\test.d) +F (.\benchmark.c)(0x5232780E)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\benchmark.o --omf_browse .\object\benchmark.crf --depend .\object\benchmark.d) +F (.\client.c)(0x523AC4A0)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\client.o --omf_browse .\object\client.crf --depend .\object\client.d) +F (.\echoclient.c)(0x523277E2)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\echoclient.o --omf_browse .\object\echoclient.crf --depend .\object\echoclient.d) +F (.\echoserver.c)(0x523277D4)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\echoserver.o --omf_browse .\object\echoserver.crf --depend .\object\echoserver.d) +F (.\server.c)(0x523AC4BA)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\server.o --omf_browse .\object\server.crf --depend .\object\server.d) +F (.\cert_data.c)(0x523277FE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\cert_data.o --omf_browse .\object\cert_data.crf --depend .\object\cert_data.d) +F (.\RTE\wolfSSL\config-CyaSSL.h)(0x523279FE)() +F (.\RTE\wolfSSL\config-Crypt.h)(0x52327A08)() +F (.\Abstract.txt)(0x526765CD)() +F (C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib)(0x5244BA9A)() +F (RTE\CMSIS\RTX_Conf_CM.c)(0x522BC824)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\rtx_conf_cm.o --omf_browse .\object\rtx_conf_cm.crf --depend .\object\rtx_conf_cm.d) +F (C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c)(0x520AB72C)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\dma_stm32f2xx.o --omf_browse .\object\dma_stm32f2xx.crf --depend .\object\dma_stm32f2xx.d) +F (C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c)(0x514117F8)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\gpio_stm32f2xx.o --omf_browse .\object\gpio_stm32f2xx.crf --depend .\object\gpio_stm32f2xx.d) +F (RTE\Device\STM32F207IG\RTE_Device.h)(0x520C57EA)() +F (RTE\Device\STM32F207IG\startup_stm32f2xx.s)(0x524C04BE)(--cpu Cortex-M3 --pd "__RTX SETA 1" -g --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL --list .\object\startup_stm32f2xx.lst --xref -o .\object\startup_stm32f2xx.o --depend .\object\startup_stm32f2xx.d) +F (RTE\Device\STM32F207IG\system_stm32f2xx.c)(0x4E640246)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\system_stm32f2xx.o --omf_browse .\object\system_stm32f2xx.crf --depend .\object\system_stm32f2xx.d) +F (C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c)(0x52411D22)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\phy_st802rt1.o --omf_browse .\object\phy_st802rt1.crf --depend .\object\phy_st802rt1.d) +F (C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c)(0x52328C8E)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\emac_stm32f2xx.o --omf_browse .\object\emac_stm32f2xx.crf --depend .\object\emac_stm32f2xx.d) +F (C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c)(0x52324BC0)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\mci_stm32f2xx.o --omf_browse .\object\mci_stm32f2xx.crf --depend .\object\mci_stm32f2xx.d) +F (C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib)(0x524362F0)() +F (RTE\File_System\FS_Config.c)(0x51CBD1D2)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\fs_config.o --omf_browse .\object\fs_config.crf --depend .\object\fs_config.d) +F (RTE\File_System\FS_Config_MC_0.h)(0x520C36F0)() +F (C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib)(0x524B8A0E)() +F (RTE\Network\Net_Config.c)(0x520C5816)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\net_config.o --omf_browse .\object\net_config.crf --depend .\object\net_config.d) +F (RTE\Network\Net_Config_BSD.h)(0x52326150)() +F (RTE\Network\Net_Config_DNS_Client.h)(0x51CBD1D2)() +F (RTE\Network\Net_Config_ETH_0.h)(0x520C56DC)() +F (RTE\Network\Net_Config_TCP.h)(0x52326152)() +F (RTE\Network\Net_Config_UDP.h)(0x52326152)() +F (RTE\Network\Net_Debug.c)(0x523BA1F2)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\net_debug.o --omf_browse .\object\net_debug.crf --depend .\object\net_debug.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c)(0x523AC74C)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\cyassl_mdk_arm.o --omf_browse .\object\cyassl_mdk_arm.crf --depend .\object\cyassl_mdk_arm.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c)(0x525754AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\time-stm32f2xx.o --omf_browse .\object\time-stm32f2xx.crf --depend .\object\time-stm32f2xx.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c)(0x5216DBDE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\aes.o --omf_browse .\object\aes.crf --depend .\object\aes.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\arc4.o --omf_browse .\object\arc4.crf --depend .\object\arc4.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\asm.o --omf_browse .\object\asm.crf --depend .\object\asm.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c)(0x52329E8A)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\asn.o --omf_browse .\object\asn.crf --depend .\object\asn.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\blake2b.o --omf_browse .\object\blake2b.crf --depend .\object\blake2b.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c)(0x51DA2952)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\camellia.o --omf_browse .\object\camellia.crf --depend .\object\camellia.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\coding.o --omf_browse .\object\coding.crf --depend .\object\coding.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\compress.o --omf_browse .\object\compress.crf --depend .\object\compress.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c)(0x51DA2952)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\des3.o --omf_browse .\object\des3.crf --depend .\object\des3.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\dh.o --omf_browse .\object\dh.crf --depend .\object\dh.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\dsa.o --omf_browse .\object\dsa.crf --depend .\object\dsa.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c)(0x5215D7AC)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\ecc.o --omf_browse .\object\ecc.crf --depend .\object\ecc.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c)(0x4FBF1BB4)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\ecc_fp.o --omf_browse .\object\ecc_fp.crf --depend .\object\ecc_fp.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c)(0x520063E0)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\error.o --omf_browse .\object\error.crf --depend .\object\error.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c)(0x51DA2952)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\hc128.o --omf_browse .\object\hc128.crf --depend .\object\hc128.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c)(0x51942D42)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\hmac.o --omf_browse .\object\hmac.crf --depend .\object\hmac.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c)(0x51F0CCBE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\integer.o --omf_browse .\object\integer.crf --depend .\object\integer.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c)(0x51942D42)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\logging.o --omf_browse .\object\logging.crf --depend .\object\logging.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\md2.o --omf_browse .\object\md2.crf --depend .\object\md2.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\md4.o --omf_browse .\object\md4.crf --depend .\object\md4.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c)(0x51942D42)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\md5.o --omf_browse .\object\md5.crf --depend .\object\md5.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c)(0x523ABC8A)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\memory.o --omf_browse .\object\memory.crf --depend .\object\memory.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c)(0x51942D42)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\misc.o --omf_browse .\object\misc.crf --depend .\object\misc.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c)(0x51942D42)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\pwdbased.o --omf_browse .\object\pwdbased.crf --depend .\object\pwdbased.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c)(0x51DA2952)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\rabbit.o --omf_browse .\object\rabbit.crf --depend .\object\rabbit.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c)(0x51BA9FE8)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\random.o --omf_browse .\object\random.crf --depend .\object\random.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\ripemd.o --omf_browse .\object\ripemd.crf --depend .\object\ripemd.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\rsa.o --omf_browse .\object\rsa.crf --depend .\object\rsa.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c)(0x51942D42)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\sha.o --omf_browse .\object\sha.crf --depend .\object\sha.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\sha256.o --omf_browse .\object\sha256.crf --depend .\object\sha256.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\sha512.o --omf_browse .\object\sha512.crf --depend .\object\sha512.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c)(0x51F0CCBE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\tfm.o --omf_browse .\object\tfm.crf --depend .\object\tfm.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c)(0x5164C8AE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\crl.o --omf_browse .\object\crl.crf --depend .\object\crl.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c)(0x52663ACA)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\internal.o --omf_browse .\object\internal.crf --depend .\object\internal.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c)(0x5232A8CE)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\io.o --omf_browse .\object\io.crf --depend .\object\io.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c)(0x521C327A)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\keys.o --omf_browse .\object\keys.crf --depend .\object\keys.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c)(0x51C7D2F0)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\ocsp.o --omf_browse .\object\ocsp.crf --depend .\object\ocsp.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c)(0x5204A7E4)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\sniffer.o --omf_browse .\object\sniffer.crf --depend .\object\sniffer.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c)(0x524BE6BC)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\ssl.o --omf_browse .\object\ssl.crf --depend .\object\ssl.d) +F (C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c)(0x524E69A6)(-c --cpu Cortex-M3 -D__RTX -g -O3 --apcs=interwork -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\Device\STM32F207IG -I C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\RTE\wolfSSL -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Driver\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS\Include -I C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\INC -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Include -I C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\Device\Include -I C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl -I C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL -D_RTE_ -DSTM32F2XX -DHAVE_CONFIG_H -D__DBG_ITM -D__RTX -DMDK_CONF_CYASSL -DCYASSL_STM32F2xx -o .\object\tls.o --omf_browse .\object\tls.crf --depend .\object\tls.d) +F (RTE\wolfSSL\config-Crypt.h)(0x52327A08)() +F (RTE\wolfSSL\config-CyaSSL.h)(0x523279FE)() +F (RTE\wolfSSL\config.h)(0x524BE316)() diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/Object/CyaSSL-Full.build_log.htm b/IDE/MDK5-ARM/Projects/CyaSSL-Full/Object/CyaSSL-Full.build_log.htm new file mode 100644 index 000000000..dc05157d2 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/Object/CyaSSL-Full.build_log.htm @@ -0,0 +1,12 @@ + + +
+
µVision Build Log

+
Project:

+C:\ROOT\CyaSSL-Release\MDK5-Pack-2.8.0\wolfSSL.CyaSSL\cyassl\IDE\MDK5-ARM\Projects\CyaSSL-Full\CyaSSL-Full.uvprojx
+Project File Date:  10/23/2013
+
+
Output:

+
+ + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c new file mode 100644 index 000000000..3ff6766f3 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c @@ -0,0 +1,276 @@ +/*---------------------------------------------------------------------------- + * RL-ARM - RTX + *---------------------------------------------------------------------------- + * Name: RTX_Conf_CM.C + * Purpose: Configuration of CMSIS RTX Kernel for Cortex-M + * Rev.: V4.70 + *---------------------------------------------------------------------------- + * + * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH + * All rights reserved. + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * - Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * - Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * - Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + *---------------------------------------------------------------------------*/ + +#include "cmsis_os.h" + + +/*---------------------------------------------------------------------------- + * RTX User configuration part BEGIN + *---------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +// +// Thread Configuration +// ======================= +// +// Number of concurrent running threads <0-250> +// Defines max. number of threads that will run at the same time. +// Default: 6 +#ifndef OS_TASKCNT + #define OS_TASKCNT 6 +#endif + +// Default Thread stack size [bytes] <64-4096:8><#/4> +// Defines default stack size for threads with osThreadDef stacksz = 0 +// Default: 200 +#ifndef OS_STKSIZE + #define OS_STKSIZE 250 +#endif + +// Main Thread stack size [bytes] <64-4096:8><#/4> +// Defines stack size for main thread. +// Default: 200 +#ifndef OS_MAINSTKSIZE + #define OS_MAINSTKSIZE 250 +#endif + +// Number of threads with user-provided stack size <0-250> +// Defines the number of threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVCNT + #define OS_PRIVCNT 2 +#endif + +// Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4> +// Defines the combined stack size for threads with user-provided stack size. +// Default: 0 +#ifndef OS_PRIVSTKSIZE + #define OS_PRIVSTKSIZE 4500 +#endif + +// Check for stack overflow +// Includes the stack checking code for stack overflow. +// Note that additional code reduces the Kernel performance. +#ifndef OS_STKCHECK + #define OS_STKCHECK 1 +#endif + +// Processor mode for thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_RUNPRIV + #define OS_RUNPRIV 1 +#endif + +// + +// RTX Kernel Timer Tick Configuration +// ====================================== +// Use Cortex-M SysTick timer as RTX Kernel Timer +// Use the Cortex-M SysTick timer as a time-base for RTX. +#ifndef OS_SYSTICK + #define OS_SYSTICK 1 +#endif +// +// Timer clock value [Hz] <1-1000000000> +// Defines the timer clock value. +// Default: 12000000 (12MHz) +#ifndef OS_CLOCK + #define OS_CLOCK 12000000 +#endif + +// Timer tick value [us] <1-1000000> +// Defines the timer tick value. +// Default: 1000 (1ms) +#ifndef OS_TICK + #define OS_TICK 1000 +#endif + +// + +// System Configuration +// ======================= +// +// Round-Robin Thread switching +// =============================== +// +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN + #define OS_ROBIN 1 +#endif + +// Round-Robin Timeout [ticks] <1-1000> +// Defines how long a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBINTOUT + #define OS_ROBINTOUT 5 +#endif + +// + +// User Timers +// ============== +// Enables user Timers +#ifndef OS_TIMERS + #define OS_TIMERS 1 +#endif + +// Timer Thread Priority +// <1=> Low +// <2=> Below Normal <3=> Normal <4=> Above Normal +// <5=> High +// <6=> Realtime (highest) +// Defines priority for Timer Thread +// Default: High +#ifndef OS_TIMERPRIO + #define OS_TIMERPRIO 5 +#endif + +// Timer Thread stack size [bytes] <64-64000:8><#/4> +// Defines stack size for Timer thread. +// Default: 200 +#ifndef OS_TIMERSTKSZ + #define OS_TIMERSTKSZ 50 +#endif + +// Timer Callback Queue size <1-32> +// Number of concurrent active timer callback functions. +// Default: 4 +#ifndef OS_TIMERCBQS + #define OS_TIMERCBQS 4 +#endif + +// + +// ISR FIFO Queue size<4=> 4 entries <8=> 8 entries +// <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries +// <48=> 48 entries <64=> 64 entries +// <96=> 96 entries +// ISR functions store requests to this buffer, +// when they are called from the interrupt handler. +// Default: 16 entries +#ifndef OS_FIFOSZ + #define OS_FIFOSZ 16 +#endif + +// + +//------------- <<< end of configuration section >>> ----------------------- + +// Standard library system mutexes +// =============================== +// Define max. number system mutexes that are used to protect +// the arm standard runtime library. For microlib they are not used. +#ifndef OS_MUTEXCNT + #define OS_MUTEXCNT 8 +#endif + +/*---------------------------------------------------------------------------- + * RTX User configuration part END + *---------------------------------------------------------------------------*/ + +#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) + + +/*---------------------------------------------------------------------------- + * Global Functions + *---------------------------------------------------------------------------*/ + +/*--------------------------- os_idle_demon ---------------------------------*/ + +void os_idle_demon (void) { + /* The idle demon is a system thread, running when no other thread is */ + /* ready to run. */ + + for (;;) { + /* HERE: include optional user code to be executed when no thread runs.*/ + } +} + +#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer + +/*--------------------------- os_tick_init ----------------------------------*/ + +// Initialize alternative hardware timer as RTX kernel timer +// Return: IRQ number of the alternative hardware timer +int os_tick_init (void) { + return (-1); /* Return IRQ number of timer (0..239) */ +} + +/*--------------------------- os_tick_val -----------------------------------*/ + +// Get alternative hardware timer current value (0 .. OS_TRV) +uint32_t os_tick_val (void) { + return (0); +} + +/*--------------------------- os_tick_ovf -----------------------------------*/ + +// Get alternative hardware timer overflow flag +// Return: 1 - overflow, 0 - no overflow +uint32_t os_tick_ovf (void) { + return (0); +} + +/*--------------------------- os_tick_irqack --------------------------------*/ + +// Acknowledge alternative hardware timer interrupt +void os_tick_irqack (void) { + /* ... */ +} + +#endif // (OS_SYSTICK == 0) + +/*--------------------------- os_error --------------------------------------*/ + +void os_error (uint32_t err_code) { + /* This function is called when a runtime error is detected. Parameter */ + /* 'err_code' holds the runtime error code (defined in RTL.H). */ + + /* HERE: include optional code to be executed on runtime error. */ + for (;;); +} + + +/*---------------------------------------------------------------------------- + * RTX Configuration Functions + *---------------------------------------------------------------------------*/ + +#include "RTX_CM_lib.h" + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/RTE_Device.h new file mode 100644 index 000000000..4a09246f3 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/RTE_Device.h @@ -0,0 +1,3127 @@ +/* ----------------------------------------------------------------------------- + * Copyright (C) 2013 ARM Limited. All rights reserved. + * + * $Date: 27. June 2013 + * $Revision: V1.01 + * + * Project: RTE Device Configuration for ST STM32F2xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT(num) \ + ((num == 0) ? GPIOA : \ + (num == 1) ? GPIOB : \ + (num == 2) ? GPIOC : \ + (num == 3) ? GPIOD : \ + (num == 4) ? GPIOE : \ + (num == 5) ? GPIOF : \ + (num == 6) ? GPIOG : \ + (num == 7) ? GPIOH : \ + (num == 8) ? GPIOI : \ + NULL) + + +// Clock Configuration +// High-speed Internal Clock <1-999999999> +#define RTE_HSI 16000000 +// High-speed External Clock <1-999999999> +#define RTE_HSE 25000000 +// System Clock <1-999999999> +#define RTE_SYSCLK 120000000 +// AHB Clock <1-999999999> +#define RTE_HCLK 120000000 +// APB1 Clock <1-999999999> +#define RTE_PCLK1 30000000 +// APB2 Clock <1-999999999> +#define RTE_PCLK2 60000000 +// 48MHz Clock +#define RTE_PLL48CK 48000000 +// + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1] +// Configuration settings for Driver_UART1 in component ::Drivers:UART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>PA9 <1=>PB6 +#define RTE_USART1_TX_ID 0 +#if (RTE_USART1_TX_ID == 0) +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 9 +#elif (RTE_USART1_TX_ID == 1) +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 6 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>PA10 <1=>PB7 +#define RTE_USART1_RX_ID 0 +#if (RTE_USART1_RX_ID == 0) +#define RTE_USART1_RX_PORT GPIOA +#define RTE_USART1_RX_BIT 10 +#elif (RTE_USART1_RX_ID == 1) +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 7 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// Synchronous +// USART1_CK Pin <0=>PA8 +// +#define RTE_USART1_CK 0 +#define RTE_USART1_CK_ID 0 +#if (RTE_USART1_CK_ID == 0) +#define RTE_USART1_CK_PORT GPIOA +#define RTE_USART1_CK_BIT 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART1_CTS Pin <0=>PA11 +// USART1_RTS Pin <0=>PA12 +// Manual CTS/RTS +// +#define RTE_USART1_HW_FLOW 0 +#define RTE_USART1_CTS_ID 0 +#define RTE_USART1_RTS_ID 0 +#define RTE_USART1_MANUAL_FLOW 0 +#if (RTE_USART1_CTS_ID == 0) +#define RTE_USART1_CTS_PORT GPIOA +#define RTE_USART1_CTS_BIT 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif +#if (RTE_USART1_RTS_ID == 0) +#define RTE_USART1_RTS_PORT GPIOA +#define RTE_USART1_RTS_BIT 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <5=>5 +// Selects DMA Stream (only Stream 2 or 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_RX_DMA 1 +#define RTE_USART1_RX_DMA_NUMBER 2 +#define RTE_USART1_RX_DMA_STREAM 2 +#define RTE_USART1_RX_DMA_CHANNEL 4 +#define RTE_USART1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_TX_DMA 1 +#define RTE_USART1_TX_DMA_NUMBER 2 +#define RTE_USART1_TX_DMA_STREAM 7 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 + +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2] +// Configuration settings for Driver_UART2 in component ::Drivers:UART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>PA2 <1=>PD5 +#define RTE_USART2_TX_ID 0 +#if (RTE_USART2_TX_ID == 0) +#define RTE_USART2_TX_PORT GPIOA +#define RTE_USART2_TX_BIT 2 +#elif (RTE_USART2_TX_ID == 1) +#define RTE_USART2_TX_PORT GPIOD +#define RTE_USART2_TX_BIT 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>PA3 <1=>PD6 +#define RTE_USART2_RX_ID 0 +#if (RTE_USART2_RX_ID == 0) +#define RTE_USART2_RX_PORT GPIOA +#define RTE_USART2_RX_BIT 3 +#elif (RTE_USART2_RX_ID == 1) +#define RTE_USART2_RX_PORT GPIOD +#define RTE_USART2_RX_BIT 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// Synchronous +// USART2_CK Pin <0=>PA4 <1=>PD7 +// +#define RTE_USART2_CK 0 +#define RTE_USART2_CK_ID 0 +#if (RTE_USART2_CK_ID == 0) +#define RTE_USART2_CK_PORT GPIOA +#define RTE_USART2_CK_BIT 4 +#elif (RTE_USART2_CK_ID == 1) +#define RTE_USART2_CK_PORT GPIOD +#define RTE_USART2_CK_BIT 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART2_CTS Pin <0=>PA0 <1=>PD3 +// USART2_RTS Pin <0=>PA1 <1=>PD4 +// Manual CTS/RTS +// +#define RTE_USART2_HW_FLOW 0 +#define RTE_USART2_CTS_ID 0 +#define RTE_USART2_RTS_ID 0 +#define RTE_USART2_MANUAL_FLOW 0 +#if (RTE_USART2_CTS_ID == 0) +#define RTE_USART2_CTS_PORT GPIOA +#define RTE_USART2_CTS_BIT 0 +#elif (RTE_USART2_CTS_ID == 1) +#define RTE_USART2_CTS_PORT GPIOD +#define RTE_USART2_CTS_BIT 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif +#if (RTE_USART2_RTS_ID == 0) +#define RTE_USART2_RTS_PORT GPIOA +#define RTE_USART2_RTS_BIT 1 +#elif (RTE_USART2_RTS_ID == 1) +#define RTE_USART2_RTS_PORT GPIOD +#define RTE_USART2_RTS_BIT 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_RX_DMA 1 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_STREAM 5 +#define RTE_USART2_RX_DMA_CHANNEL 4 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_TX_DMA 1 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_STREAM 6 +#define RTE_USART2_TX_DMA_CHANNEL 4 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3] +// Configuration settings for Driver_UART3 in component ::Drivers:UART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8 +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) +#define RTE_USART3_TX_PORT GPIOB +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 1) +#define RTE_USART3_TX_PORT GPIOC +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 2) +#define RTE_USART3_TX_PORT GPIOD +#define RTE_USART3_TX_BIT 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9 +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) +#define RTE_USART3_RX_PORT GPIOB +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 1) +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 2) +#define RTE_USART3_RX_PORT GPIOD +#define RTE_USART3_RX_BIT 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// Synchronous +// USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10 +// +#define RTE_USART3_CK 0 +#define RTE_USART3_CK_ID 0 +#if (RTE_USART3_CK_ID == 0) +#define RTE_USART3_CK_PORT GPIOB +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 1) +#define RTE_USART3_CK_PORT GPIOC +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 2) +#define RTE_USART3_CK_PORT GPIOD +#define RTE_USART3_CK_BIT 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART3_CTS Pin <0=>PB13 <1=>PD11 +// USART3_RTS Pin <0=>PB14 <1=>PD12 +// Manual CTS/RTS +// +#define RTE_USART3_HW_FLOW 0 +#define RTE_USART3_CTS_ID 0 +#define RTE_USART3_RTS_ID 0 +#define RTE_USART3_MANUAL_FLOW 0 +#if (RTE_USART3_CTS_ID == 0) +#define RTE_USART3_CTS_PORT GPIOB +#define RTE_USART3_CTS_BIT 13 +#elif (RTE_USART3_CTS_ID == 1) +#define RTE_USART3_CTS_PORT GPIOD +#define RTE_USART3_CTS_BIT 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif +#if (RTE_USART3_RTS_ID == 0) +#define RTE_USART3_RTS_PORT GPIOB +#define RTE_USART3_RTS_BIT 14 +#elif (RTE_USART3_RTS_ID == 1) +#define RTE_USART3_RTS_PORT GPIOD +#define RTE_USART3_RTS_BIT 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_RX_DMA 1 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_STREAM 1 +#define RTE_USART3_RX_DMA_CHANNEL 4 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_TX_DMA 1 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_STREAM 3 +#define RTE_USART3_TX_DMA_CHANNEL 4 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) [Driver_UART4] +// Configuration settings for Driver_UART4 in component ::Drivers:UART +#define RTE_UART4 0 + +// UART4_TX Pin <0=>PA0 <1=>PC10 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>PA1 <1=>PC11 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 1 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_RX_DMA 1 +#define RTE_UART4_RX_DMA_NUMBER 1 +#define RTE_UART4_RX_DMA_STREAM 2 +#define RTE_UART4_RX_DMA_CHANNEL 4 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_TX_DMA 1 +#define RTE_UART4_TX_DMA_NUMBER 1 +#define RTE_UART4_TX_DMA_STREAM 4 +#define RTE_UART4_TX_DMA_CHANNEL 4 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) [Driver_UART5] +// Configuration settings for Driver_UART5 in component ::Drivers:UART +#define RTE_UART5 0 + +// UART5_TX Pin <0=>PC12 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>PD2 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_RX_DMA 1 +#define RTE_UART5_RX_DMA_NUMBER 1 +#define RTE_UART5_RX_DMA_STREAM 0 +#define RTE_UART5_RX_DMA_CHANNEL 4 +#define RTE_UART5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_TX_DMA 1 +#define RTE_UART5_TX_DMA_NUMBER 1 +#define RTE_UART5_TX_DMA_STREAM 7 +#define RTE_UART5_TX_DMA_CHANNEL 4 +#define RTE_UART5_TX_DMA_PRIORITY 0 + +// + + +// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6] +// Configuration settings for Driver_UART6 in component ::Drivers:UART +#define RTE_USART6 0 + +// USART6_TX Pin <0=>PC6 <1=>PG14 +#define RTE_USART6_TX_ID 0 +#if (RTE_USART6_TX_ID == 0) +#define RTE_USART6_TX_PORT GPIOC +#define RTE_USART6_TX_BIT 6 +#elif (RTE_USART6_TX_ID == 1) +#define RTE_USART6_TX_PORT GPIOG +#define RTE_USART6_TX_BIT 14 +#else +#error "Invalid USART6_TX Pin Configuration!" +#endif + +// USART6_RX Pin <0=>PC7 <1=>PG9 +#define RTE_USART6_RX_ID 0 +#if (RTE_USART6_RX_ID == 0) +#define RTE_USART6_RX_PORT GPIOC +#define RTE_USART6_RX_BIT 7 +#elif (RTE_USART6_RX_ID == 1) +#define RTE_USART6_RX_PORT GPIOG +#define RTE_USART6_RX_BIT 9 +#else +#error "Invalid USART6_RX Pin Configuration!" +#endif + +// Synchronous +// USART6_CK Pin <0=>PC8 <1=>PG7 +// +#define RTE_USART6_CK 0 +#define RTE_USART6_CK_ID 0 +#if (RTE_USART6_CK_ID == 0) +#define RTE_USART6_CK_PORT GPIOC +#define RTE_USART6_CK_BIT 8 +#elif (RTE_USART6_CK_ID == 1) +#define RTE_USART6_CK_PORT GPIOG +#define RTE_USART6_CK_BIT 7 +#else +#error "Invalid USART6_CK Pin Configuration!" +#endif + +// Hardware flow control +// USART6_CTS Pin <0=>PG13 <1=>PG15 +// USART6_RTS Pin <0=>PG8 <1=>PG12 +// Manual CTS/RTS +// +#define RTE_USART6_HW_FLOW 0 +#define RTE_USART6_CTS_ID 0 +#define RTE_USART6_RTS_ID 0 +#define RTE_USART6_MANUAL_FLOW 0 +#if (RTE_USART6_CTS_ID == 0) +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 13 +#elif (RTE_USART6_CTS_ID == 1) +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 15 +#else +#error "Invalid USART6_CTS Pin Configuration!" +#endif +#if (RTE_USART6_RTS_ID == 0) +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 8 +#elif (RTE_USART6_RTS_ID == 1) +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 12 +#else +#error "Invalid USART6_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_RX_DMA 1 +#define RTE_USART6_RX_DMA_NUMBER 2 +#define RTE_USART6_RX_DMA_STREAM 1 +#define RTE_USART6_RX_DMA_CHANNEL 5 +#define RTE_USART6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_TX_DMA 1 +#define RTE_USART6_TX_DMA_NUMBER 2 +#define RTE_USART6_TX_DMA_STREAM 6 +#define RTE_USART6_TX_DMA_CHANNEL 5 +#define RTE_USART6_TX_DMA_PRIORITY 0 + +// + + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 <1=>PB8 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 <1=>PB9 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 9 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 1 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_STREAM 0 +#define RTE_I2C1_RX_DMA_CHANNEL 1 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 1 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_STREAM 6 +#define RTE_I2C1_TX_DMA_CHANNEL 1 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C +#define RTE_I2C2 0 + +// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOF +#define RTE_I2C2_SCL_BIT 1 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT GPIOH +#define RTE_I2C2_SCL_BIT 4 +#elif (RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOF +#define RTE_I2C2_SDA_BIT 0 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT GPIOH +#define RTE_I2C2_SDA_BIT 5 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 <3=>3 +// Selects DMA Stream (only Stream 2 or 3 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 1 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_STREAM 2 +#define RTE_I2C2_RX_DMA_CHANNEL 7 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 1 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_STREAM 7 +#define RTE_I2C2_TX_DMA_CHANNEL 7 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C +#define RTE_I2C3 0 + +// I2C3_SCL Pin <0=>PH7 <1=>PA8 +#define RTE_I2C3_SCL_PORT_ID 0 +#if (RTE_I2C3_SCL_PORT_ID == 0) +#define RTE_I2C3_SCL_PORT GPIOH +#define RTE_I2C3_SCL_BIT 7 +#elif (RTE_I2C3_SCL_PORT_ID == 1) +#define RTE_I2C3_SCL_PORT GPIOA +#define RTE_I2C3_SCL_BIT 8 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// I2C3_SDA Pin <0=>PH8 <1=>PC9 +#define RTE_I2C3_SDA_PORT_ID 0 +#if (RTE_I2C3_SDA_PORT_ID == 0) +#define RTE_I2C3_SDA_PORT GPIOH +#define RTE_I2C3_SDA_BIT 8 +#elif (RTE_I2C3_SDA_PORT_ID == 1) +#define RTE_I2C3_SDA_PORT GPIOC +#define RTE_I2C3_SDA_BIT 9 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_RX_DMA 1 +#define RTE_I2C3_RX_DMA_NUMBER 1 +#define RTE_I2C3_RX_DMA_STREAM 2 +#define RTE_I2C3_RX_DMA_CHANNEL 3 +#define RTE_I2C3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_TX_DMA 1 +#define RTE_I2C3_TX_DMA_NUMBER 1 +#define RTE_I2C3_TX_DMA_STREAM 4 +#define RTE_I2C3_TX_DMA_CHANNEL 3 +#define RTE_I2C3_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 0 + +// SPI1_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIO_PORT(0) +#define RTE_SPI1_NSS_BIT 4 + +// SPI1_SCK Pin <0=>PA5 <1=>PB3 +#define RTE_SPI1_SCL_PORT_ID 0 +#if (RTE_SPI1_SCL_PORT_ID == 0) +#define RTE_SPI1_SCL_PORT GPIOA +#define RTE_SPI1_SCL_BIT 5 +#elif (RTE_SPI1_SCL_PORT_ID == 1) +#define RTE_SPI1_SCL_PORT GPIOB +#define RTE_SPI1_SCL_BIT 3 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_MISO Pin <0=>PA6 <1=>PB4 +#define RTE_SPI1_MISO_PORT_ID 0 +#if (RTE_SPI1_MISO_PORT_ID == 0) +#define RTE_SPI1_MISO_PORT GPIOA +#define RTE_SPI1_MISO_BIT 6 +#elif (RTE_SPI1_MISO_PORT_ID == 1) +#define RTE_SPI1_MISO_PORT GPIOB +#define RTE_SPI1_MISO_BIT 4 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>PA7 <1=>PB5 +#define RTE_SPI1_MOSI_PORT_ID 0 +#if (RTE_SPI1_MOSI_PORT_ID == 0) +#define RTE_SPI1_MOSI_PORT GPIOA +#define RTE_SPI1_MOSI_BIT 7 +#elif (RTE_SPI1_MOSI_PORT_ID == 1) +#define RTE_SPI1_MOSI_PORT GPIOB +#define RTE_SPI1_MOSI_BIT 5 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 1 +#define RTE_SPI1_RX_DMA_NUMBER 2 +#define RTE_SPI1_RX_DMA_STREAM 0 +#define RTE_SPI1_RX_DMA_CHANNEL 3 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 1 +#define RTE_SPI1_TX_DMA_NUMBER 2 +#define RTE_SPI1_TX_DMA_STREAM 5 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 0 + +// SPI2_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIO_PORT(1) +#define RTE_SPI2_NSS_BIT 12 + +// SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1 +#define RTE_SPI2_SCL_PORT_ID 0 +#if (RTE_SPI2_SCL_PORT_ID == 0) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 10 +#elif (RTE_SPI2_SCL_PORT_ID == 1) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 13 +#elif (RTE_SPI2_SCL_PORT_ID == 2) +#define RTE_SPI2_SCL_PORT GPIOI +#define RTE_SPI2_SCL_BIT 1 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO_PORT GPIOC +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 2) +#define RTE_SPI2_MISO_PORT GPIOI +#define RTE_SPI2_MISO_BIT 2 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 2) +#define RTE_SPI2_MOSI_PORT GPIOI +#define RTE_SPI2_MOSI_BIT 3 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 1 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_STREAM 2 +#define RTE_SPI2_RX_DMA_CHANNEL 0 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 1 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_STREAM 3 +#define RTE_SPI2_TX_DMA_CHANNEL 0 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 0 + +// SPI3_NSS Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIO_PORT(0) +#define RTE_SPI3_NSS_BIT 15 + +// SPI3_SCK Pin <0=>PB3 <1=>PC10 +#define RTE_SPI3_SCL_PORT_ID 0 +#if (RTE_SPI3_SCL_PORT_ID == 0) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 3 +#elif (RTE_SPI3_SCL_PORT_ID == 1) +#define RTE_SPI3_SCL_PORT GPIOC +#define RTE_SPI3_SCL_BIT 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_MISO Pin <0=>PB4 <1=>PC11 +#define RTE_SPI3_MISO_PORT_ID 0 +#if (RTE_SPI3_MISO_PORT_ID == 0) +#define RTE_SPI3_MISO_PORT GPIOB +#define RTE_SPI3_MISO_BIT 4 +#elif (RTE_SPI3_MISO_PORT_ID == 1) +#define RTE_SPI3_MISO_PORT GPIOC +#define RTE_SPI3_MISO_BIT 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI Pin <0=>PB5 <1=>PC12 +#define RTE_SPI3_MOSI_PORT_ID 0 +#if (RTE_SPI3_MOSI_PORT_ID == 0) +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 5 +#elif (RTE_SPI3_MOSI_PORT_ID == 1) +#define RTE_SPI3_MOSI_PORT GPIOC +#define RTE_SPI3_MOSI_BIT 12 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 1 +#define RTE_SPI3_RX_DMA_NUMBER 1 +#define RTE_SPI3_RX_DMA_STREAM 0 +#define RTE_SPI3_RX_DMA_CHANNEL 0 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 1 +#define RTE_SPI3_TX_DMA_NUMBER 1 +#define RTE_SPI3_TX_DMA_STREAM 5 +#define RTE_SPI3_TX_DMA_CHANNEL 0 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SDIO (Secure Digital Input/Output) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::Drivers:MCI +#define RTE_SDIO 1 + +// SDIO_CD (Card Detect) Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_CD_PIN 1 +#define RTE_SDIO_CD_ACTIVE 0 +#define RTE_SDIO_CD_PORT GPIO_PORT(7) +#define RTE_SDIO_CD_BIT 15 + +// SDIO_WP (Write Protect) Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_SDIO_WP_PIN 0 +#define RTE_SDIO_WP_ACTIVE 0 +#define RTE_SDIO_WP_PORT GPIO_PORT(7) +#define RTE_SDIO_WP_BIT 16 + +// SDIO Bus +// SDIO_CK Pin <0=>PC12 +#define RTE_SDIO_CK_PORT_ID 0 +#if (RTE_SDIO_CK_PORT_ID == 0) +#define RTE_SDIO_CK_PORT GPIOC +#define RTE_SDIO_CK_PIN 12 +#else +#error "Invalid SDIO_CK Pin Configuration!" +#endif +// SDIO_CMD Pin <0=>PD2 +#define RTE_SDIO_CMD_PORT_ID 0 +#if (RTE_SDIO_CMD_PORT_ID == 0) +#define RTE_SDIO_CMD_PORT GPIOD +#define RTE_SDIO_CMD_PIN 2 +#else +#error "Invalid SDIO_CDM Pin Configuration!" +#endif +// SDIO_D0 Pin <0=>PC8 +#define RTE_SDIO_D0_PORT_ID 0 +#if (RTE_SDIO_D0_PORT_ID == 0) +#define RTE_SDIO_D0_PORT GPIOC +#define RTE_SDIO_D0_PIN 8 +#else +#error "Invalid SDIO_D0 Pin Configuration!" +#endif +// SDIO_D1 Pin <0=>PC9 +#define RTE_SDIO_D1_PORT_ID 0 +#if (RTE_SDIO_D1_PORT_ID == 0) +#define RTE_SDIO_D1_PORT GPIOC +#define RTE_SDIO_D1_PIN 9 +#else +#error "Invalid SDIO_D1 Pin Configuration!" +#endif +// SDIO_D2 Pin <0=>PC10 +#define RTE_SDIO_D2_PORT_ID 0 +#if (RTE_SDIO_D2_PORT_ID == 0) +#define RTE_SDIO_D2_PORT GPIOC +#define RTE_SDIO_D2_PIN 10 +#else +#error "Invalid SDIO_D2 Pin Configuration!" +#endif +// SDIO_D3 Pin <0=>PC11 +#define RTE_SDIO_D3_PORT_ID 0 +#if (RTE_SDIO_D3_PORT_ID == 0) +#define RTE_SDIO_D3_PORT GPIOC +#define RTE_SDIO_D3_PIN 11 +#else +#error "Invalid SDIO_D3 Pin Configuration!" +#endif +// SDIO_D4 Pin <0=>PB8 +#define RTE_SDIO_D4_PORT_ID 0 +#if (RTE_SDIO_D4_PORT_ID == 0) +#define RTE_SDIO_D4_PORT GPIOB +#define RTE_SDIO_D4_PIN 8 +#else +#error "Invalid SDIO_D4 Pin Configuration!" +#endif +// SDIO_D5 Pin <0=>PB9 +#define RTE_SDIO_D5_PORT_ID 0 +#if (RTE_SDIO_D5_PORT_ID == 0) +#define RTE_SDIO_D5_PORT GPIOB +#define RTE_SDIO_D5_PIN 9 +#else +#error "Invalid SDIO_D5 Pin Configuration!" +#endif +// SDIO_D6 Pin <0=>PC6 +#define RTE_SDIO_D6_PORT_ID 0 +#if (RTE_SDIO_D6_PORT_ID == 0) +#define RTE_SDIO_D6_PORT GPIOC +#define RTE_SDIO_D6_PIN 6 +#else +#error "Invalid SDIO_D6 Pin Configuration!" +#endif +// SDIO_D7 Pin <0=>PC7 +#define RTE_SDIO_D7_PORT_ID 0 +#if (RTE_SDIO_D7_PORT_ID == 0) +#define RTE_SDIO_D7_PORT GPIOC +#define RTE_SDIO_D7_PIN 7 +#else +#error "Invalid SDIO_D7 Pin Configuration!" +#endif +// + +// DMA +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDIO_DMA 1 +#define RTE_SDIO_DMA_NUMBER 2 +#define RTE_SDIO_DMA_STREAM 3 +#define RTE_SDIO_DMA_CHANNEL 4 +#define RTE_SDIO_DMA_PRIORITY 0 + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC +#define RTE_ETH 1 + +// MII (Media Independent Interface) +#define RTE_ETH_MII 0 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) +#define RTE_ETH_MII_TXD0_PORT GPIOG +#define RTE_ETH_MII_TXD0_PIN 13 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) +#define RTE_ETH_MII_TXD1_PORT GPIOG +#define RTE_ETH_MII_TXD1_PIN 14 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) +#define RTE_ETH_MII_TXD3_PORT GPIOE +#define RTE_ETH_MII_TXD3_PIN 2 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) +#define RTE_ETH_MII_TX_EN_PORT GPIOG +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_PORT_ID 0 +#if (RTE_ETH_MII_RXD0_PORT_ID == 0) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_PORT_ID 0 +#if (RTE_ETH_MII_RXD1_PORT_ID == 0) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif +// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 +#define RTE_ETH_MII_RXD2_PORT_ID 0 +#if (RTE_ETH_MII_RXD2_PORT_ID == 0) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) +#define RTE_ETH_MII_RXD2_PORT GPIOH +#define RTE_ETH_MII_RXD2_PIN 6 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 +#define RTE_ETH_MII_RXD3_PORT_ID 0 +#if (RTE_ETH_MII_RXD3_PORT_ID == 0) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RXD3_PORT GPIOH +#define RTE_ETH_MII_RXD3_PIN 7 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_PORT_ID 0 +#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif +// ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RX_ER_PORT GPIOI +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>PA0 <1=>PH2 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#elif (RTE_ETH_MII_CRS_PORT_ID == 1) +#define RTE_ETH_MII_CRS_PORT GPIOH +#define RTE_ETH_MII_CRS_PIN 2 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>PA3 <1=>PH3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#elif (RTE_ETH_MII_COL_PORT_ID == 1) +#define RTE_ETH_MII_COL_PORT GPIOH +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 1 + +// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_RMII_TXD0_PORT_ID 1 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) +#define RTE_ETH_RMII_TXD0_PORT GPIOG +#define RTE_ETH_RMII_TXD0_PIN 13 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_RMII_TXD1_PORT_ID 1 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) +#define RTE_ETH_RMII_TXD1_PORT GPIOG +#define RTE_ETH_RMII_TXD1_PIN 14 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 1 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) +#define RTE_ETH_RMII_TX_EN_PORT GPIOG +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_PORT_ID 0 +#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_PORT_ID 0 +#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 +#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// Management Data Interface +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_MDI_MDC_PORT_ID 0 +#if (RTE_ETH_MDI_MDC_PORT_ID == 0) +#define RTE_ETH_MDI_MDC_PORT GPIOC +#define RTE_ETH_MDI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_MDI_MDIO_PORT_ID 0 +#if (RTE_ETH_MDI_MDIO_PORT_ID == 0) +#define RTE_ETH_MDI_MDIO_PORT GPIOA +#define RTE_ETH_MDI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Reference 25MHz/50MHz Clock generation +#define RTE_ETH_REF_CLOCK 0 + +// MCO Pin <0=>PA2 <1=>PC9 +#define RTE_ETH_REF_CLOCK_PORT_ID 0 +#if (RTE_ETH_REF_CLOCK_PORT_ID == 0) +#define RTE_ETH_REF_CLOCK_PORT GPIOA +#define RTE_ETH_REF_CLOCK_PIN 8 +#elif (RTE_ETH_REF_CLOCK_PORT_ID == 1) +#define RTE_ETH_REF_CLOCK_PORT GPIOC +#define RTE_ETH_REF_CLOCK_PIN 9 +#else +#error "Invalid MCO Pin Configuration!" +#endif + +// + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::Drivers:USB Device +#define RTE_USB_OTG_FS_DEV 1 + +// Endpoints +// Reduce memory requirements of Driver by disabling unused endpoints +// Endpoint 1 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 2 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 3 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// +#define RTE_USB_OTG_FS_DEV_EP 0x0000000F +#define RTE_USB_OTG_FS_DEV_EP_BULK 0x000E000E +#define RTE_USB_OTG_FS_DEV_EP_INT 0x000E000E +#define RTE_USB_OTG_FS_DEV_EP_ISO 0x000E000E + +// + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::Drivers:USB Host + +#define RTE_USB_OTG_FS_HOST 1 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 1 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(7) +#define RTE_OTG_FS_VBUS_BIT 5 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 1 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_FS_OC_BIT 11 +// + +// + + +// USB OTG High-speed +#define RTE_USB_OTG_HS 0 + +// PHY (Physical Layer) + +// PHY Interface +// <0=>On-chip full-speed PHY +// <1=>External ULPI high-speed PHY +#define RTE_USB_OTG_HS_PHY 1 + +// External ULPI Pins (UTMI+ Low Pin Interface) + +// OTG_HS_ULPI_CK Pin <0=>PA5 +#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" +#endif +// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 +#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 +#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 +#else +#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" +#endif +// OTG_HS_ULPI_STP Pin <0=>PC0 +#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" +#endif +// OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4 +#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 +#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 2 +#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 +#else +#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" +#endif +// OTG_HS_ULPI_D0 Pin <0=>PA3 +#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 +#else +#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" +#endif +// OTG_HS_ULPI_D1 Pin <0=>PB0 +#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" +#endif +// OTG_HS_ULPI_D2 Pin <0=>PB1 +#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 +#else +#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" +#endif +// OTG_HS_ULPI_D3 Pin <0=>PB10 +#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 +#else +#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" +#endif +// OTG_HS_ULPI_D4 Pin <0=>PB11 +#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 +#else +#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" +#endif +// OTG_HS_ULPI_D5 Pin <0=>PB12 +#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 +#else +#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" +#endif +// OTG_HS_ULPI_D6 Pin <0=>PB13 +#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 +#else +#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" +#endif +// OTG_HS_ULPI_D7 Pin <0=>PB5 +#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" +#endif + +// + +// + +// Device [Driver_USBD1] +// Configuration settings for Driver_USBD1 in component ::Drivers:USB Device +#define RTE_USB_OTG_HS_DEV 1 + +// Endpoints +// Reduce memory requirements of Driver by disabling unused endpoints +// Endpoint 1 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 2 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 3 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 4 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// Endpoint 5 +// Bulk OUT +// Bulk IN +// Interrupt OUT +// Interrupt IN +// Isochronous OUT +// Isochronous IN +// +// +#define RTE_USB_OTG_HS_DEV_EP 0x0000003F +#define RTE_USB_OTG_HS_DEV_EP_BULK 0x003E003E +#define RTE_USB_OTG_HS_DEV_EP_INT 0x003E003E +#define RTE_USB_OTG_HS_DEV_EP_ISO 0x003E003E + +// + +// Host [Driver_USBH1] +// Configuration settings for Driver_USBH1 in component ::Drivers:USB Host +#define RTE_USB_OTG_HS_HOST 1 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_VBUS_PIN 1 +#define RTE_OTG_HS_VBUS_ACTIVE 0 +#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(2) +#define RTE_OTG_HS_VBUS_BIT 2 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_OC_PIN 1 +#define RTE_OTG_HS_OC_ACTIVE 0 +#define RTE_OTG_HS_OC_PORT GPIO_PORT(5) +#define RTE_OTG_HS_OC_BIT 12 +// + +// + + +// EXTI (External Interrupt/Event Controller) +#define RTE_EXTI 0 + +// EXTI0 Line +#define RTE_EXTI0 0 +// Pin <0=>PA0 <1=>PB0 <2=>PC0 <3=>PD0 <4=>PE0 <5=>PF0 <6=>PG0 <7=>PH0 <8=>PI0 +#define RTE_EXTI0_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI0_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI0_TRIGGER 0 +// + +// EXTI1 Line +#define RTE_EXTI1 0 +// Pin <0=>PA1 <1=>PB1 <2=>PC1 <3=>PD1 <4=>PE1 <5=>PF1 <6=>PG1 <7=>PH1 <8=>PI1 +#define RTE_EXTI1_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI1_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI1_TRIGGER 0 +// + +// EXTI2 Line +#define RTE_EXTI2 0 +// Pin <0=>PA2 <1=>PB2 <2=>PC2 <3=>PD2 <4=>PE2 <5=>PF2 <6=>PG2 <7=>PH2 <8=>PI2 +#define RTE_EXTI2_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI2_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI2_TRIGGER 0 +// + +// EXTI3 Line +#define RTE_EXTI3 0 +// Pin <0=>PA3 <1=>PB3 <2=>PC3 <3=>PD3 <4=>PE3 <5=>PF3 <6=>PG3 <7=>PH3 <8=>PI3 +#define RTE_EXTI3_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI3_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI3_TRIGGER 0 +// + +// EXTI4 Line +#define RTE_EXTI4 0 +// Pin <0=>PA4 <1=>PB4 <2=>PC4 <3=>PD4 <4=>PE4 <5=>PF4 <6=>PG4 <7=>PH4 <8=>PI4 +#define RTE_EXTI4_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI4_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI4_TRIGGER 0 +// + +// EXTI5 Line +#define RTE_EXTI5 0 +// Pin <0=>PA5 <1=>PB5 <2=>PC5 <3=>PD5 <4=>PE5 <5=>PF5 <6=>PG5 <7=>PH5 <8=>PI5 +#define RTE_EXTI5_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI5_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI5_TRIGGER 0 +// + +// EXTI6 Line +#define RTE_EXTI6 0 +// Pin <0=>PA6 <1=>PB6 <2=>PC6 <3=>PD6 <4=>PE6 <5=>PF6 <6=>PG6 <7=>PH6 <8=>PI6 +#define RTE_EXTI6_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI6_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI6_TRIGGER 0 +// + +// EXTI7 Line +#define RTE_EXTI7 0 +// Pin <0=>PA7 <1=>PB7 <2=>PC7 <3=>PD7 <4=>PE7 <5=>PF7 <6=>PG7 <7=>PH7 <8=>PI7 +#define RTE_EXTI7_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI7_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI7_TRIGGER 0 +// + +// EXTI8 Line +#define RTE_EXTI8 0 +// Pin <0=>PA8 <1=>PB8 <2=>PC8 <3=>PD8 <4=>PE8 <5=>PF8 <6=>PG8 <7=>PH8 <8=>PI8 +#define RTE_EXTI8_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI8_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI8_TRIGGER 0 +// + +// EXTI9 Line +#define RTE_EXTI9 0 +// Pin <0=>PA9 <1=>PB9 <2=>PC9 <3=>PD9 <4=>PE9 <5=>PF9 <6=>PG9 <7=>PH9 <8=>PI9 +#define RTE_EXTI9_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI9_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI9_TRIGGER 0 +// + +// EXTI10 Line +#define RTE_EXTI10 0 +// Pin <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10 +#define RTE_EXTI10_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI10_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI10_TRIGGER 0 +// + +// EXTI11 Line +#define RTE_EXTI11 0 +// Pin <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11 +#define RTE_EXTI11_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI11_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI11_TRIGGER 0 +// + +// EXTI12 Line +#define RTE_EXTI12 0 +// Pin <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12 +#define RTE_EXTI12_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI12_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI12_TRIGGER 0 +// + +// EXTI13 Line +#define RTE_EXTI13 0 +// Pin <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13 +#define RTE_EXTI13_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI13_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI13_TRIGGER 0 +// + +// EXTI14 Line +#define RTE_EXTI14 0 +// Pin <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14 +#define RTE_EXTI14_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI14_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI14_TRIGGER 0 +// + +// EXTI15 Line +#define RTE_EXTI15 0 +// Pin <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15 +#define RTE_EXTI15_PIN 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI15_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI15_TRIGGER 0 +// + +// EXTI16 Line: PVD Output +#define RTE_EXTI16 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI16_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI16_TRIGGER 0 +// + +// EXTI17 Line: RTC Alarm +#define RTE_EXTI17 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI17_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI17_TRIGGER 0 +// + +// EXTI18 Line: USB OTG FS Wakeup +#define RTE_EXTI18 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI18_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI18_TRIGGER 0 +// + +// EXTI19 Line: Ethernet Wakeup +#define RTE_EXTI19 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI19_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI19_TRIGGER 0 +// + +// EXTI20 Line: USB OTG HS Wakeup +#define RTE_EXTI20 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI20_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI20_TRIGGER 0 +// + +// EXTI21 Line: RTC Tamper and TimeStamp +#define RTE_EXTI21 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI21_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI21_TRIGGER 0 +// + +// EXTI22 Line: RTC Wakeup +#define RTE_EXTI22 0 +// Mode <0=>Interrupt <1=>Event +#define RTE_EXTI22_MODE 0 +// Trigger <0=>None <1=>Raising edge <2=>Falling edge <3=>Any edge +#define RTE_EXTI22_TRIGGER 0 +// + +// + + +// FSMC (Flexible Static Memory Controller) +#define RTE_FSMC 0 + +// Pin Configuration +// Configure Pins +#define RTE_FSMC_PINS 0 + +// Address Bus Pins +// <0=>A[17:16] +// <1=>A[10:0] <2=>A[15:0] <3=>A[16:0] <4=>A[17:0] +// <5=>A[18:0] <6=>A[19:0] <7=>A[20:0] <8=>A[21:0] +// <9=>A[22:0] <10=>A[23:0] <11=>A[24:0] <12=>A[25:0] +#define RTE_FSMC_ABUS_PINS 10 +// Data Bus Pins <0=>D[7:0] <1=>D[15:0] +#define RTE_FSMC_DBUS_PINS 0 +// FSMC_NOE Pin +#define RTE_FSMC_NOE_PIN 0 +// FSMC_NWE Pin +#define RTE_FSMC_NWE_PIN 0 +// FSMC_NBL0 Pin +#define RTE_FSMC_NBL0_PIN 0 +// FSMC_NBL1 Pin +#define RTE_FSMC_NBL1_PIN 0 +// FSMC_NL Pin +#define RTE_FSMC_NL_PIN 0 +// FSMC_NWAIT Pin +#define RTE_FSMC_NWAIT_PIN 0 +// FSMC_CLK Pin +#define RTE_FSMC_CLK_PIN 0 +// FSMC_NE1/NCE2 Pin +#define RTE_FSMC_NE1_PIN 0 +// FSMC_NE2/NCE3 Pin +#define RTE_FSMC_NE2_PIN 0 +// FSMC_NE3/NCE4_1 Pin +#define RTE_FSMC_NE3_PIN 0 +// FSMC_NE4 Pin +#define RTE_FSMC_NE4_PIN 0 +// FSMC_NCE4_2 Pin +#define RTE_FSMC_NCE42_PIN 0 +// FSMC_INT2 Pin +#define RTE_FSMC_INT2_PIN 0 +// FSMC_INT3 Pin +#define RTE_FSMC_INT3_PIN 0 +// FSMC_INTR Pin +#define RTE_FSMC_INTR_PIN 0 +// FSMC_NIORD Pin +#define RTE_FSMC_NIORD_PIN 0 +// FSMC_NIOWR Pin +#define RTE_FSMC_NIOWR_PIN 0 +// FSMC_NREG Pin +#define RTE_FSMC_NREG_PIN 0 +// FSMC_CD Pin +#define RTE_FSMC_CD_PIN 0 + +// + +// NOR Flash / PSRAM Controller + +// FSMC_NE1 Chip Select +// Configure Device on Chip Select FSMC_NE1 +#define RTE_FSMC_NE1 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR1_CBURSTRW 0 +#define RTE_FSMC_BCR1_ASYNCWAIT 0 +#define RTE_FSMC_BCR1_EXTMOD 0 +#define RTE_FSMC_BCR1_WAITEN 1 +#define RTE_FSMC_BCR1_WREN 1 +#define RTE_FSMC_BCR1_WAITCFG 0 +#define RTE_FSMC_BCR1_WRAPMOD 0 +#define RTE_FSMC_BCR1_WAITPOL 0 +#define RTE_FSMC_BCR1_BURSTEN 0 +#define RTE_FSMC_BCR1_FACCEN 1 +#define RTE_FSMC_BCR1_MWID 1 +#define RTE_FSMC_BCR1_MTYP 2 +#define RTE_FSMC_BCR1_MUXEN 1 +#define RTE_FSMC_BCR1_MBKEN 1 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR1_ACCMOD 0 +#define RTE_FSMC_BTR1_DATLAT 15 +#define RTE_FSMC_BTR1_CLKDIV 15 +#define RTE_FSMC_BTR1_BUSTURN 15 +#define RTE_FSMC_BTR1_DATAST 255 +#define RTE_FSMC_BTR1_ADDHLD 15 +#define RTE_FSMC_BTR1_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR1_ACCMOD 0 +#define RTE_FSMC_BWTR1_DATLAT 15 +#define RTE_FSMC_BWTR1_CLKDIV 15 +#define RTE_FSMC_BWTR1_BUSTURN 15 +#define RTE_FSMC_BWTR1_DATAST 255 +#define RTE_FSMC_BWTR1_ADDHLD 15 +#define RTE_FSMC_BWTR1_ADDSET 15 +// +// + +// FSMC_NE2 Chip Select +// Configure Device on Chip Select FSMC_NE2 +#define RTE_FSMC_NE2 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR2_CBURSTRW 0 +#define RTE_FSMC_BCR2_ASYNCWAIT 0 +#define RTE_FSMC_BCR2_EXTMOD 0 +#define RTE_FSMC_BCR2_WAITEN 1 +#define RTE_FSMC_BCR2_WREN 1 +#define RTE_FSMC_BCR2_WAITCFG 0 +#define RTE_FSMC_BCR2_WRAPMOD 0 +#define RTE_FSMC_BCR2_WAITPOL 0 +#define RTE_FSMC_BCR2_BURSTEN 0 +#define RTE_FSMC_BCR2_FACCEN 1 +#define RTE_FSMC_BCR2_MWID 1 +#define RTE_FSMC_BCR2_MTYP 0 +#define RTE_FSMC_BCR2_MUXEN 1 +#define RTE_FSMC_BCR2_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR2_ACCMOD 0 +#define RTE_FSMC_BTR2_DATLAT 15 +#define RTE_FSMC_BTR2_CLKDIV 15 +#define RTE_FSMC_BTR2_BUSTURN 15 +#define RTE_FSMC_BTR2_DATAST 255 +#define RTE_FSMC_BTR2_ADDHLD 15 +#define RTE_FSMC_BTR2_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR2_ACCMOD 0 +#define RTE_FSMC_BWTR2_DATLAT 15 +#define RTE_FSMC_BWTR2_CLKDIV 15 +#define RTE_FSMC_BWTR2_BUSTURN 15 +#define RTE_FSMC_BWTR2_DATAST 255 +#define RTE_FSMC_BWTR2_ADDHLD 15 +#define RTE_FSMC_BWTR2_ADDSET 15 +// +// + +// FSMC_NE3 Chip Select +// Configure Device on Chip Select FSMC_NE3 +#define RTE_FSMC_NE3 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR3_CBURSTRW 0 +#define RTE_FSMC_BCR3_ASYNCWAIT 0 +#define RTE_FSMC_BCR3_EXTMOD 0 +#define RTE_FSMC_BCR3_WAITEN 1 +#define RTE_FSMC_BCR3_WREN 1 +#define RTE_FSMC_BCR3_WAITCFG 0 +#define RTE_FSMC_BCR3_WRAPMOD 0 +#define RTE_FSMC_BCR3_WAITPOL 0 +#define RTE_FSMC_BCR3_BURSTEN 0 +#define RTE_FSMC_BCR3_FACCEN 1 +#define RTE_FSMC_BCR3_MWID 1 +#define RTE_FSMC_BCR3_MTYP 0 +#define RTE_FSMC_BCR3_MUXEN 1 +#define RTE_FSMC_BCR3_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR3_ACCMOD 0 +#define RTE_FSMC_BTR3_DATLAT 15 +#define RTE_FSMC_BTR3_CLKDIV 15 +#define RTE_FSMC_BTR3_BUSTURN 15 +#define RTE_FSMC_BTR3_DATAST 255 +#define RTE_FSMC_BTR3_ADDHLD 15 +#define RTE_FSMC_BTR3_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR3_ACCMOD 0 +#define RTE_FSMC_BWTR3_DATLAT 15 +#define RTE_FSMC_BWTR3_CLKDIV 15 +#define RTE_FSMC_BWTR3_BUSTURN 15 +#define RTE_FSMC_BWTR3_DATAST 255 +#define RTE_FSMC_BWTR3_ADDHLD 15 +#define RTE_FSMC_BWTR3_ADDSET 15 +// +// + +// FSMC_NE4 Chip Select +// Configure Device on Chip Select FSMC_NE4 +#define RTE_FSMC_NE4 0 + +// Chip-select control +// CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write +// For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash +// memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal. +// ASYNCWAIT: Wait signal during asynchronous transfer +// Enables the FSMC to use the wait signal even during an asynchronous protocol. +// EXTMOD: Extended mode enable +// Enables the FSMC to program inside the write timing register, so it allows different timings for read and write. +// WAITEN: Wait enable +// For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal. +// WREN: Write enable +// Enable/disable write operations in the current bank by the FSMC +// WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state +// For memory access in burst mode, the NWAIT signal indicates whether the data from the memory +// are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted +// by the memory one clock cycle before the wait state or during the wait state +// WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high +// Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode. +// BURSTEN: Burst enable +// Enables the burst access mode for the memory. Valid only with synchronous burst memories. +// FACCEN: Flash access enable +// Enables NOR Flash memory access operations. +// MWID: Memory databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width, valid for all type of memories. +// MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash +// Defines the type of external memory attached to the corresponding memory bank. +// MUXEN: Address/data multiplexing enable +// When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories. +// MBKEN: Memory bank enable +// Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a +// disabled bank causes an ERROR on AHB bus. +#define RTE_FSMC_BCR4_CBURSTRW 0 +#define RTE_FSMC_BCR4_ASYNCWAIT 0 +#define RTE_FSMC_BCR4_EXTMOD 0 +#define RTE_FSMC_BCR4_WAITEN 1 +#define RTE_FSMC_BCR4_WREN 1 +#define RTE_FSMC_BCR4_WAITCFG 0 +#define RTE_FSMC_BCR4_WRAPMOD 0 +#define RTE_FSMC_BCR4_WAITPOL 0 +#define RTE_FSMC_BCR4_BURSTEN 0 +#define RTE_FSMC_BCR4_FACCEN 1 +#define RTE_FSMC_BCR4_MWID 1 +#define RTE_FSMC_BCR4_MTYP 0 +#define RTE_FSMC_BCR4_MUXEN 1 +#define RTE_FSMC_BCR4_MBKEN 0 +// + +// Chip-select timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with synchronous burst mode enabled, defines the number of memory clock +// cycles (+2) to issue to the memory before getting the first data: +// 0000: Data latency of 2 CLK clock cycles for first burst access +// 1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) +// periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care. +// In the case of CRAM, this field must be set to ‘0’. +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles: +// 0000: Reserved +// 0001: CLK period = 2 × HCLK periods +// 0010: CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Define the bus turnaround delay after a read access only +// from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive +// addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the +// minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the +// databus in Hi-Z state. +// These bits are written by software to add a delay at the end of a write/read transaction. This +// delay allows to match the minimum time between consecutive transactions (tEHEL from NEx +// high to NEx low) and the maximum time needed by the memory to free the data bus after a +// read access (tEHQZ): +// (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if +// EXTMOD = ‘0’ +// (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset) +// DATAST: Data phase duration <1-255> +// Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Define the duration of the address hold phase used in mode D and multiplexed accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration =1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is not used, the address hold phase is always 1 +// memory clock period duration. +// ADDSET: Address setup phase duration <0-15> +// Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don’t care. +#define RTE_FSMC_BTR4_ACCMOD 0 +#define RTE_FSMC_BTR4_DATLAT 15 +#define RTE_FSMC_BTR4_CLKDIV 15 +#define RTE_FSMC_BTR4_BUSTURN 15 +#define RTE_FSMC_BTR4_DATAST 255 +#define RTE_FSMC_BTR4_ADDHLD 15 +#define RTE_FSMC_BTR4_ADDSET 15 +// + +// Write timing +// ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D +// Specifies the asynchronous access modes. Access mode is taken into account only when +// Extended mode is enabled in the Chip-select control register. +// DATLAT: Data latency <0-15> +// For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles +// (+2) to issue to the memory before getting the first data. +// 0000: (0x0) Data latency of 2 CLK clock cycles for first burst access +// ... +// 1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset) +// Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In +// asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of +// CRAM, this field must be set to 0 +// CLKDIV: Clock divide ratio (for CLK signal) <1-15> +// Defines the period of CLK clock output signal, expressed in number of HCLK cycles. +// 0000: Reserved +// 0001 CLK period = 2 × HCLK periods +// 0010 CLK period = 3 × HCLK periods +// 1111: CLK period = 16 × HCLK periods (default value after reset) +// In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. +// BUSTURN: Bus turnaround phase duration <0-15> +// Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low). +// (BUSTRUN + 1) HCLK period = tEHELmin. +// 0000: BUSTURN phase duration = 0 HCLK clock cycle added +// ... +// 1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset) +// DATAST: Data phase duration <1-255> +// Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses. +// 0000 0000: Reserved +// 0000 0001: DATAST phase duration = 1 × HCLK clock cycles +// 0000 0010: DATAST phase duration = 2 × HCLK clock cycles +// ... +// 1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset) +// Note: In synchronous accesses, this value is don't care. +// ADDHLD: Address hold phase duration <1-15> +// Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses. +// 0000: Reserved +// 0001: ADDHLD phase duration = 1 × HCLK clock cycle +// 0010: ADDHLD phase duration = 2 × HCLK clock cycle +// ... +// 1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration. +// ADDSET: Address setup phase duration <1-15> +// Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed. +// 0000: ADDSET phase duration = 0 × HCLK clock cycle +// ... +// 1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset) +// Note: In synchronous NOR Flash accesses, this value is don’t care. +#define RTE_FSMC_BWTR4_ACCMOD 0 +#define RTE_FSMC_BWTR4_DATLAT 15 +#define RTE_FSMC_BWTR4_CLKDIV 15 +#define RTE_FSMC_BWTR4_BUSTURN 15 +#define RTE_FSMC_BWTR4_DATAST 255 +#define RTE_FSMC_BWTR4_ADDHLD 15 +#define RTE_FSMC_BWTR4_ADDSET 15 +// +// + +// + +// NAND Flash Controller + +// FSMC_NCE2 Chip Select +// Configure NAND Device on Chip Select FSMC_NCE2 +#define RTE_FSMC_NCE2 0 + +// NAND Flash Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <1=>NAND Flash +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: NAND Flash memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR2_ECCPS 0 +#define RTE_FSMC_PCR2_TAR 0 +#define RTE_FSMC_PCR2_TCLR 0 +#define RTE_FSMC_PCR2_ECCEN 0 +#define RTE_FSMC_PCR2_PWID 0 +#define RTE_FSMC_PCR2_PTYP 1 +#define RTE_FSMC_PCR2_PBKEN 0 +#define RTE_FSMC_PCR2_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR2_IFEN 0 +#define RTE_FSMC_SR2_ILEN 0 +#define RTE_FSMC_SR2_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM2_MEMHIZ 255 +#define RTE_FSMC_PMEM2_MEMHOLD 255 +#define RTE_FSMC_PMEM2_MEMWAIT 255 +#define RTE_FSMC_PMEM2_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT2_ATTHIZ 255 +#define RTE_FSMC_PATT2_ATTHOLD 255 +#define RTE_FSMC_PATT2_ATTWAIT 255 +#define RTE_FSMC_PATT2_ATTSET 255 + +// + +// + +// FSMC_NCE3 Chip Select +// Configure NAND Device on Chip Select FSMC_NCE3 +#define RTE_FSMC_NCE3 0 + +// NAND Flash Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <1=>NAND Flash +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: NAND Flash memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR3_ECCPS 0 +#define RTE_FSMC_PCR3_TAR 0 +#define RTE_FSMC_PCR3_TCLR 0 +#define RTE_FSMC_PCR3_ECCEN 0 +#define RTE_FSMC_PCR3_PWID 0 +#define RTE_FSMC_PCR3_PTYP 1 +#define RTE_FSMC_PCR3_PBKEN 0 +#define RTE_FSMC_PCR3_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR3_IFEN 0 +#define RTE_FSMC_SR3_ILEN 0 +#define RTE_FSMC_SR3_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM3_MEMHIZ 255 +#define RTE_FSMC_PMEM3_MEMHOLD 255 +#define RTE_FSMC_PMEM3_MEMWAIT 255 +#define RTE_FSMC_PMEM3_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT3_ATTHIZ 255 +#define RTE_FSMC_PATT3_ATTHOLD 255 +#define RTE_FSMC_PATT3_ATTWAIT 255 +#define RTE_FSMC_PATT3_ATTSET 255 + +// + +// + +// + +// PC Card Controller + +// FSMC_NCE4_x Chip Select +// Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2 +#define RTE_FSMC_NCE4 0 + +// PC Card Control +// ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes +// Defines the page size for the extended ECC. +// TAR: ALE to RE delay <0-15> +// Sets time from ALE low to RE low in number of AHB clock cycles (HCLK). +// Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// TCLR: CLE to RE delay <0-15> +// Sets time from CLE low to RE low in number of AHB clock cycles (HCLK). +// Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period +// 0000: 1 HCLK cycle (default) +// 1111: 16 HCLK cycles +// Note: SET is MEMSET or ATTSET according to the addressed space. +// ECCEN: ECC computation logic enable +// PWID: Databus width <0=>8 bits <1=>16 bits +// Defines the external memory device width. +// PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA +// Defines the type of device attached to the corresponding memory bank. +// PBKEN: PC Card memory bank enable +// Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus. +// PWAITEN: Wait feature enable +// Enables the Wait feature for the PC Card/NAND Flash memory bank. +#define RTE_FSMC_PCR4_ECCPS 0 +#define RTE_FSMC_PCR4_TAR 0 +#define RTE_FSMC_PCR4_TCLR 0 +#define RTE_FSMC_PCR4_ECCEN 0 +#define RTE_FSMC_PCR4_PWID 0 +#define RTE_FSMC_PCR4_PTYP 0 +#define RTE_FSMC_PCR4_PBKEN 0 +#define RTE_FSMC_PCR4_PWAITEN 0 + +// + +// Interrupt configuration +// IFEN: Falling edge detection enable +// ILEN: High-level detection enable +// IREN: Rising edge detection enable +#define RTE_FSMC_SR4_IFEN 0 +#define RTE_FSMC_SR4_ILEN 0 +#define RTE_FSMC_SR4_IREN 0 + +// + +// Common memory space timing +// MEMHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// MEMWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access to. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset) +// MEMSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 2 HCLK cycles (for NAND Flash) +// 1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset) +#define RTE_FSMC_PMEM4_MEMHIZ 255 +#define RTE_FSMC_PMEM4_MEMHOLD 255 +#define RTE_FSMC_PMEM4_MEMWAIT 255 +#define RTE_FSMC_PMEM4_MEMSET 255 + +// + +// Attribute memory space timing +// ATTHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a NAND Flash write access. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// ATTWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE, +// NOE), for NAND Flash read or write access. The duration for command assertion +// is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value. +// 0000 0000: reserved +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT) +// ATTSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up address before the command +// assertion (NWE, NOE), for NAND Flash read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PATT4_ATTHIZ 255 +#define RTE_FSMC_PATT4_ATTHOLD 255 +#define RTE_FSMC_PATT4_ATTWAIT 255 +#define RTE_FSMC_PATT4_ATTSET 255 + +// + +// I/O space timing +// IOHIZ: Databus HiZ time <0-255> +// Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the +// start of a PC Card write access. Only valid for write transaction. +// 0000 0000: 0 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// IOHOLD: Hold time <1-255> +// Defines the number of HCLK clock cycles to hold address (and data for write access) after +// the command deassertion (NWE, NOE), for PC Card read or write access. +// 0000 0000: reserved +// 0000 0001: 1 HCLK cycle +// 1111 1111: 255 HCLK cycles (default value after reset) +// IOWAIT: Wait time <1-255> +// Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE, +// SMNOE), for PC Card read or write access. The duration for command assertion is +// extended if the wait signal (NWAIT) is active (low) at the end of the +// programmed value of HCLK. +// 0000 0000: reserved, do not use this value +// 0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT) +// 1111 1111: 256 HCLK cycles +// IOSET: Setup time <0-255> +// Defines the number of HCLK (+1) clock cycles to set up the address before the command +// assertion (NWE, NOE), for PC Card read or write access. +// 0000 0000: 1 HCLK cycle +// 1111 1111: 256 HCLK cycles (default value after reset) +#define RTE_FSMC_PIO4_IOHIZ 255 +#define RTE_FSMC_PIO4_IOHOLD 255 +#define RTE_FSMC_PIO4_IOWAIT 255 +#define RTE_FSMC_PIO4_IOSET 255 + +// + +// + +// + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s new file mode 100644 index 000000000..205f9ffbb --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/startup_stm32f2xx.s @@ -0,0 +1,419 @@ +;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** +;* File Name : startup_stm32f2xx.s +;* Author : MCD Application Team +;* Version : V1.0.0 +;* Date : 18-April-2011 +;* Description : STM32F2xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS +; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, +; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE +; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING +; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00001000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x0000F000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYP crypto + DCD HASH_RNG_IRQHandler ; Hash and Rng +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c new file mode 100644 index 000000000..da0e189c8 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Device/STM32F207IG/system_stm32f2xx.c @@ -0,0 +1,536 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @version V1.0.0 + * @date 18-April-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * This file contains the system clock configuration for STM32F2xx devices, + * and is generated by the clock configuration tool + * "STM32f2xx_Clock_Configuration_V1.0.0.xls" + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * and Divider factors, AHB/APBx prescalers and Flash settings), + * depending on the configuration made in the clock xls tool. + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (16 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define + * in "stm32f2xx.h" file. When HSE is used as system clock source, directly or + * through PLL, and you are using different crystal you have to adapt the HSE + * value to your own configuration. + * + * 5. This file configures the system clock as follows: + *============================================================================= + *============================================================================= + * Supported STM32F2xx device revision | Rev B and Y + *----------------------------------------------------------------------------- + * System Clock source | PLL (HSE) + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 120000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 4 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 2 + *----------------------------------------------------------------------------- + * HSE Frequency(Hz) | 25000000 + *----------------------------------------------------------------------------- + * PLL_M | 25 + *----------------------------------------------------------------------------- + * PLL_N | 240 + *----------------------------------------------------------------------------- + * PLL_P | 2 + *----------------------------------------------------------------------------- + * PLL_Q | 5 + *----------------------------------------------------------------------------- + * PLLI2S_N | NA + *----------------------------------------------------------------------------- + * PLLI2S_R | NA + *----------------------------------------------------------------------------- + * I2S input clock | NA + *----------------------------------------------------------------------------- + * VDD(V) | 3.3 + *----------------------------------------------------------------------------- + * Flash Latency(WS) | 3 + *----------------------------------------------------------------------------- + * Prefetch Buffer | ON + *----------------------------------------------------------------------------- + * Instruction cache | ON + *----------------------------------------------------------------------------- + * Data cache | ON + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Enabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +#include "stm32f2xx.h" + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +/* #define DATA_IN_ExtSRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ +#define PLL_M 25 +#define PLL_N 240 + +/* SYSCLK = PLL_VCO / PLL_P */ +#define PLL_P 2 + +/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ +#define PLL_Q 5 + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + + uint32_t SystemCoreClock = 120000000; + + __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f2xx.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ +/* + +-------------------+--------------------+------------------+------------------+ + + SRAM pins assignment + + +-------------------+--------------------+------------------+------------------+ + | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | + | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | + | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | + | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | + | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | + | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | + | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | + | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ + | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | + | PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | + | PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+ + +-------------------+--------------------+ +*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR = 0x00000078; + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00cc00cc; + GPIOD->AFR[1] = 0xcc0ccccc; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xa2aa0a0a; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xf3ff0f0f; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xaaaa800a; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xffffc00f; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xcccc0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xaa000aaa; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xff000fff; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0x000000c0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00080aaa; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000c0fff; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FSMC Configuration ------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR = 0x00000001; + + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001015; + FSMC_Bank1->BTCR[3] = 0x00010400; + FSMC_Bank1E->BWTR[2] = 0x0fffffff; +/* + Bank1_SRAM2 is configured as follow: + + p.FSMC_AddressSetupTime = 0; + p.FSMC_AddressHoldTime = 0; + p.FSMC_DataSetupTime = 4; + p.FSMC_BusTurnAroundDuration = 1; + p.FSMC_CLKDivision = 0; + p.FSMC_DataLatency = 0; + p.FSMC_AccessMode = FSMC_AccessMode_A; + + FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2; + FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; + FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM; + FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; + FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; + FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; + FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; +*/ + +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c new file mode 100644 index 000000000..78564b080 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config.c @@ -0,0 +1,72 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config.c + * Purpose: File System Configuration + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// File System +// Define File System global parameters + +// Number of open files <4-16> +// Define number of files that can be +// opened at the same time. +// Default: 8 +#define NUM_FILES 8 + +// FAT Name Cache Size <0-1000000> +// Define number of cached FAT file or directory names. +// 48 bytes of RAM is required for each cached name. +#define FAT_NAME_CACHE_SIZE 0 + +// Relocate FAT Name Cache Buffer +// Locate Cache Buffer at a specific address. +#define FAT_NAME_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Define the Cache buffer base address. +#define FAT_NAME_CACHE_ADDR 0x60000000 + +// + +// + +#include "..\RTE_Components.h" + +#ifdef RTE_FileSystem_Drive_RAM +#include "FS_Config_RAM.h" +#endif + +#ifdef RTE_FileSystem_Drive_NOR_0 +#include "FS_Config_NOR_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NOR_1 +#include "FS_Config_NOR_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NAND_0 +#include "FS_Config_NAND_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NAND_1 +#include "FS_Config_NAND_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_MC_0 +#include "FS_Config_MC_0.h" +#endif +#ifdef RTE_FileSystem_Drive_MC_1 +#include "FS_Config_MC_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_USB_0 +#include "FS_Config_USB_0.h" +#endif +#ifdef RTE_FileSystem_Drive_USB_1 +#include "FS_Config_USB_1.h" +#endif + +#include "fs_config.h" diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h new file mode 100644 index 000000000..0b1c6d3a7 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/File_System/FS_Config_MC_0.h @@ -0,0 +1,57 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System:Drive + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config_MC_0.h + * Purpose: File System Configuration for Memory Card Drive + * Rev.: V5.01 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Memory Card Drive 0 +// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:" +#define MC0_ENABLE 1 + +// Connect to hardware via Driver_MCI# <0-255> +// Select driver control block for hardware interface +#define MC0_MCI_DRIVER 0 + +// Connect to hardware via Driver_SPI# <0-255> +// Select driver control block for hardware interface when in SPI mode +#define MC0_SPI_DRIVER 0 + +// Memory Card Interface Mode <0=>Native <1=>SPI +// Native uses a SD Bus with up to 8 data lines, CLK, and CMD +// SPI uses 2 data lines (MOSI and MISO), SCLK and CS +// When using SPI both Driver_SPI# and Driver_MCI# must be specified +// since the MCI driver provides the control interface lines. +#define MC0_SPI 0 + +// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Drive Cache stores data sectors and may be increased to speed-up +// file read/write operations on this drive (default: 4 KB) +#define MC0_CACHE_SIZE 4 + +// Locate Drive Cache and Drive Buffer +// Some microcontrollers support DMA only in specific memory areas and +// require to locate the drive buffers at a fixed address. +#define MC0_CACHE_RELOC 0 + +// Base address <0x0000-0xFFFFFE00:0x200> +// Set buffer base address to RAM areas that support DMA with the drive. +#define MC0_CACHE_ADDR 0x7FD00000 + +// + +// Use FAT Journal +// Protect File Allocation Table and Directory Entries for +// fail-safe operation. +#define MC0_FAT_JOURNAL 0 + +// Default Drive "M0:" +// Use this drive when no drive letter is specified. +#define MC0_DEFAULT_DRIVE 1 + +// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c new file mode 100644 index 000000000..6b9dc8e00 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config.c @@ -0,0 +1,153 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config.c + * Purpose: Network Configuration + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Definitions +// Global Network System definitions +// Local Host Name +// This is the name under which embedded host can be +// accessed on a local area network. +// Default: "my_host" +#define NET_HOST_NAME "my_host" + +// Memory Pool size <1536-262144:4><#/4> +// This is the size of a memory pool in bytes. Buffers for +// Network packets are allocated from this memory pool. +// Default: 12000 bytes +#define NET_MEM_SIZE 3000 + +// + +#include "..\RTE_Components.h" + +#ifdef RTE_Network_Interface_ETH_0 +#include "Net_Config_ETH_0.h" +#endif +#ifdef RTE_Network_Interface_ETH_1 +#include "Net_Config_ETH_1.h" +#endif + +#ifdef RTE_Network_Interface_PPP_0 +#include "Net_Config_PPP_0.h" +#endif +#ifdef RTE_Network_Interface_PPP_1 +#include "Net_Config_PPP_1.h" +#endif + +#ifdef RTE_Network_Interface_SLIP_0 +#include "Net_Config_SLIP_0.h" +#endif +#ifdef RTE_Network_Interface_SLIP_1 +#include "Net_Config_SLIP_1.h" +#endif + +#ifdef RTE_Network_Socket_UDP +#include "Net_Config_UDP.h" +#endif +#ifdef RTE_Network_Socket_TCP +#include "Net_Config_TCP.h" +#endif +#ifdef RTE_Network_Socket_BSD +#include "Net_Config_BSD.h" +#endif + +#ifdef RTE_Network_Web_Server_RO +#include "Net_Config_HTTP_Server.h" +#endif +#ifdef RTE_Network_Web_Server_FS +#include "Net_Config_HTTP_Server.h" +#endif + +#ifdef RTE_Network_Telnet_Server +#include "Net_Config_Telnet_Server.h" +#endif + +#ifdef RTE_Network_TFTP_Server +#include "Net_Config_TFTP_Server.h" +#endif +#ifdef RTE_Network_TFTP_Client +#include "Net_Config_TFTP_Client.h" +#endif + +#ifdef RTE_Network_FTP_Server +#include "Net_Config_FTP_Server.h" +#endif +#ifdef RTE_Network_FTP_Client +#include "Net_Config_FTP_Client.h" +#endif + +#ifdef RTE_Network_DNS_Client +#include "Net_Config_DNS_Client.h" +#endif + +#ifdef RTE_Network_SMTP_Client +#include "Net_Config_SMTP_Client.h" +#endif + +#ifdef RTE_Network_SNMP_Agent +#include "Net_Config_SNMP_Agent.h" +#endif + +#ifdef RTE_Network_SNTP_Client +#include "Net_Config_SNTP_Client.h" +#endif + +#include "net_config.h" + +/** +\addtogroup net_genFunc +@{ +*/ +/** + \fn void net_sys_error (ERROR_CODE error) + \ingroup net_cores + \brief Network system error handler. +*/ +void net_sys_error (ERROR_CODE error) { + /* This function is called when a fatal error is encountered. */ + /* The normal program execution is not possible anymore. */ + + switch (error) { + case ERR_MEM_ALLOC: + /* Out of memory */ + break; + + case ERR_MEM_FREE: + /* Trying to release non existing memory block */ + break; + + case ERR_MEM_CORRUPT: + /* Memory Link pointer Corrupted */ + /* More data written than the size of allocated mem block */ + break; + + case ERR_MEM_LOCK: + /* Locked Memory management function (alloc/free) re-entered */ + break; + + case ERR_UDP_ALLOC: + /* Out of UDP Sockets */ + break; + + case ERR_TCP_ALLOC: + /* Out of TCP Sockets */ + break; + + case ERR_TCP_STATE: + /* TCP State machine in undefined state */ + break; + } + + /* End-less loop */ + while (1); +} +/** +@} +*/ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h new file mode 100644 index 000000000..7d515a507 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_BSD.h @@ -0,0 +1,36 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_BSD.h + * Purpose: Network Configuration BSD Sockets + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Berkley (BSD) Sockets +#define BSD_ENABLE 1 + +// Number of BSD Sockets <1-20> +// Number of available Berkeley Sockets +// Default: 2 +#define BSD_NUM_SOCKS 10 + +// Number of Streaming Server Sockets <0-20> +// Defines a number of Streaming (TCP) Server sockets, +// that listen for an incoming connection from the client. +// Default: 1 +#define BSD_SERVER_SOCKS 1 + +// Receive Timeout in seconds <0-600> +// A timeout for socket receive in blocking mode. +// Timeout value of 0 means indefinite timeout. +// Default: 20 +#define BSD_RECEIVE_TOUT 20 + +// Hostname Resolver +// Enable or disable Berkeley style hostname resolver. +#define BSD_HOSTNAME_ENABLE 0 + +// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h new file mode 100644 index 000000000..d30b71807 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_DNS_Client.h @@ -0,0 +1,20 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Service + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_DNS_Client.h + * Purpose: Network Configuration DNS Client + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// DNS Client +#define DNS_CLIENT_ENABLE 1 + +// Cache Table size <5-100> +// Number of cached DNS host names/IP addresses +// Default: 20 +#define DNS_CLIENT_TAB_SIZE 20 + +// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h new file mode 100644 index 000000000..7be57ad6d --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_ETH_0.h @@ -0,0 +1,222 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Interface + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_ETH_0.h + * Purpose: Network Configuration ETH Interface + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Ethernet Network Interface 0 +#define ETH0_ENABLE 1 + +// Connect to hardware via Driver_ETH# <0-255> +// Select driver control block for MAC and PHY interface +#define ETH0_DRIVER 1 + +// MAC Address +// Local Ethernet MAC Address +// Value FF:FF:FF:FF:FF:FF is not allowed. +// It is an ethernet Broadcast MAC address. +// Address byte 1 <0x00-0xff:2> +// LSB is an ethernet Multicast bit. +// Must be 0 for local MAC address. +// Default: 0x1E +#define ETH0_MAC1 0x1E + +// Address byte 2 <0x00-0xff> +// Default: 0x30 +#define ETH0_MAC2 0x30 + +// Address byte 3 <0x00-0xff> +// Default: 0x6C +#define ETH0_MAC3 0x6C + +// Address byte 4 <0x00-0xff> +// Default: 0xA2 +#define ETH0_MAC4 0xA2 + +// Address byte 5 <0x00-0xff> +// Default: 0x45 +#define ETH0_MAC5 0x45 + +// Address byte 6 <0x00-0xff> +// Default: 0x5E +#define ETH0_MAC6 0x5E +// + +// IP Address +// Local Static IP Address +// Value 255.255.255.255 is not allowed. +// It is a Broadcast IP address. +// Address byte 1 <0-255> +// Default: 192 +#define ETH0_IP1 192 + +// Address byte 2 <0-255> +// Default: 168 +#define ETH0_IP2 168 + +// Address byte 3 <0-255> +// Default: 0 +#define ETH0_IP3 0 + +// Address byte 4 <0-255> +// Default: 100 +#define ETH0_IP4 100 +// + +// Subnet mask +// Local Subnet mask +// Mask byte 1 <0-255> +// Default: 255 +#define ETH0_MASK1 255 + +// Mask byte 2 <0-255> +// Default: 255 +#define ETH0_MASK2 255 + +// Mask byte 3 <0-255> +// Default: 255 +#define ETH0_MASK3 255 + +// Mask byte 4 <0-255> +// Default: 0 +#define ETH0_MASK4 0 +// + +// Default Gateway +// Default Gateway IP Address +// Address byte 1 <0-255> +// Default: 192 +#define ETH0_GW1 192 + +// Address byte 2 <0-255> +// Default: 168 +#define ETH0_GW2 168 + +// Address byte 3 <0-255> +// Default: 0 +#define ETH0_GW3 0 + +// Address byte 4 <0-255> +// Default: 254 +#define ETH0_GW4 254 +// + +// Primary DNS Server +// Primary DNS Server IP Address +// Address byte 1 <0-255> +// Default: 194 +#define ETH0_PRI_DNS1 194 + +// Address byte 2 <0-255> +// Default: 25 +#define ETH0_PRI_DNS2 25 + +// Address byte 3 <0-255> +// Default: 2 +#define ETH0_PRI_DNS3 2 + +// Address byte 4 <0-255> +// Default: 129 +#define ETH0_PRI_DNS4 129 +// + +// Secondary DNS Server +// Secondary DNS Server IP Address +// Address byte 1 <0-255> +// Default: 194 +#define ETH0_SEC_DNS1 194 + +// Address byte 2 <0-255> +// Default: 25 +#define ETH0_SEC_DNS2 25 + +// Address byte 3 <0-255> +// Default: 2 +#define ETH0_SEC_DNS3 2 + +// Address byte 4 <0-255> +// Default: 130 +#define ETH0_SEC_DNS4 130 +// + +// ARP Definitions +// Address Resolution Protocol Definitions +// Cache Table size <5-100> +// Number of cached hardware/IP addresses +// Default: 10 +#define ETH0_ARP_TAB_SIZE 10 + +// Cache Timeout in seconds <5-255> +// A timeout for a cached hardware/IP addresses +// Default: 150 +#define ETH0_ARP_CACHE_TOUT 150 + +// Number of Retries <0-20> +// Number of Retries to resolve an IP address +// before ARP module gives up +// Default: 4 +#define ETH0_ARP_MAX_RETRY 4 + +// Resend Timeout in seconds <1-10> +// A timeout to resend the ARP Request +// Default: 2 +#define ETH0_ARP_RESEND_TOUT 2 + +// Send Notification on Address changes +// When this option is enabled, the embedded host +// will send a Gratuitous ARP notification at startup, +// or when the device IP address has changed. +// Default: Disabled +#define ETH0_ARP_NOTIFY 0 +// + +// IGMP Group Management +// Enable or disable Internet Group Management Protocol +#define ETH0_IGMP_ENABLE 0 + +// Membership Table size <2-50> +// Number of Groups this host can join +// Default: 5 +#define ETH0_IGMP_TAB_SIZE 5 +// + +// NetBIOS Name Service +// When this option is enabled, the embedded host can be +// accessed by his name on the local LAN using NBNS protocol. +// You need to modify also the number of UDP Sockets, +// because NBNS protocol uses one UDP socket to run. +#define ETH0_NBNS_ENABLE 1 + +// Dynamic Host Configuration +// When this option is enabled, local IP address, Net Mask +// and Default Gateway are obtained automatically from +// the DHCP Server on local LAN. +// You need to modify also the number of UDP Sockets, +// because DHCP protocol uses one UDP socket to run. +#define ETH0_DHCP_ENABLE 1 + +// Vendor Class Identifier +// This value is optional. If specified, it is added +// to DHCP request message, identifying vendor type. +// Default: "" +#define ETH0_DHCP_VCID "" + +// Bootfile Name +// This value is optional. If enabled, the Bootfile Name +// (option 67) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_BOOTFILE 0 + +// NTP Servers +// This value is optional. If enabled, a list of NTP Servers +// (option 42) is also requested from DHCP server. +// Default: disabled +#define ETH0_DHCP_NTP_SERVERS 0 +// + +// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h new file mode 100644 index 000000000..e659ce921 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_TCP.h @@ -0,0 +1,61 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_TCP.h + * Purpose: Network Configuration TCP Sockets + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// TCP Sockets +#define TCP_ENABLE 1 + +// Number of TCP Sockets <1-20> +// Number of available TCP sockets +// Default: 5 +#define TCP_NUM_SOCKS 10 + +// Number of Retries <0-20> +// How many times TCP module will try to retransmit data +// before giving up. Increase this value for high-latency +// and low_throughput networks. +// Default: 5 +#define TCP_MAX_RETRY 5 + +// Retry Timeout in seconds <1-10> +// If data frame not acknowledged within this time frame, +// TCP module will try to resend the data again. +// Default: 4 +#define TCP_RETRY_TOUT 4 + +// Default Connect Timeout in seconds <1-600> +// Default TCP Socket Keep Alive timeout. When it expires +// with no TCP data frame send, TCP Connection is closed. +// Default: 120 +#define TCP_DEFAULT_TOUT 120 + +// Maximum Segment Size <536-1460> +// The Maximum Segment Size specifies the maximum +// number of bytes in the TCP segment's Data field. +// Default: 1460 +#define TCP_MAX_SEG_SIZE 1460 + +// Receive Window Size <536-65535> +// Receive Window Size specifies the size of data, +// that the socket is able to buffer in flow-control mode. +// Default: 4380 +#define TCP_RECEIVE_WIN_SIZE 4380 + +// + +// TCP Initial Retransmit period in seconds +#define TCP_INITIAL_RETRY_TOUT 1 + +// TCP SYN frame retransmit period in seconds +#define TCP_SYN_RETRY_TOUT 2 + +// Number of retries to establish a connection +#define TCP_CONNECT_RETRY 7 + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h new file mode 100644 index 000000000..55e7f21ba --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Config_UDP.h @@ -0,0 +1,20 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network:Socket + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Config_UDP.h + * Purpose: Network Configuration UDP Sockets + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// UDP Sockets +#define UDP_ENABLE 1 + +// Number of UDP Sockets <1-30> +// Number of available UDP sockets +// Default: 5 +#define UDP_NUM_SOCKS 15 + +// diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c new file mode 100644 index 000000000..735089a40 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/Network/Net_Debug.c @@ -0,0 +1,125 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::Network + * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: Net_Debug.c + * Purpose: Network Debug Configuration + * Rev.: V5.00 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Print Time Stamp +// Enable printing the time-info in debug messages +#define DBG_TIME 1 + +// TCPnet Debug Definitions +// Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Dynamic Memory debug messages +#define DBG_MEM 1 + +// Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Ethernet debug messages +#define DBG_ETH 0 + +// PPP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off PPP debug messages +#define DBG_PPP 0 + +// SLIP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off SLIP debug messages +#define DBG_SLIP 0 + +// ARP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off ARP debug messages +#define DBG_ARP 0 + +// IP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off IP debug messages +#define DBG_IP 1 + +// ICMP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off ICMP debug messages +#define DBG_ICMP 1 + +// IGMP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off IGMP debug messages +#define DBG_IGMP 1 + +// UDP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off UDP debug messages +#define DBG_UDP 1 + +// TCP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off TCP debug messages +#define DBG_TCP 1 + +// NBNS Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off NetBIOS Name Service debug messages +#define DBG_NBNS 1 + +// DHCP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Dynamic Host Configuration debug messages +#define DBG_DHCP 1 + +// DNS Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Domain Name Service debug messages +#define DBG_DNS 1 + +// SNMP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Simple Network Management debug messages +#define DBG_SNMP 1 + +// SNTP Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Simple Network Time debug messages +#define DBG_SNTP 1 + +// BSD Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off BSD Interface debug messages +#define DBG_BSD 1 +// + +// Application Debug Definitions +// HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Web Server debug messages +#define DBG_HTTP_SERVER 1 + +// FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off FTP Server debug messages +#define DBG_FTP_SERVER 1 + +// FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off FTP Client debug messages +#define DBG_FTP_CLIENT 1 + +// Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off Telnet Server debug messages +#define DBG_TELNET_SERVER 1 + +// TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off TFTP Server debug messages +#define DBG_TFTP_SERVER 1 + +// TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off TFTP Client debug messages +#define DBG_TFTP_CLIENT 1 + +// SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug +// Turn On/Off SMTP Client debug messages +#define DBG_SMTP_CLIENT 1 +// + + +#include "net_debug.h" + + +/** + \fn void net_debug_init (void) + \brief Initialize Network Debug Interface. +*/ +void net_debug_init (void) { + /* Add your code to initialize the Debug output. This is usually the */ + /* serial interface. The function is called at TCPnet system startup. */ + /* You may need to customize also the 'putchar()' function. */ + +} diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h new file mode 100644 index 000000000..07fef4e5e --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/RTE_Components.h @@ -0,0 +1,28 @@ + +/* + * Auto generated Run-Time-Environment Component Configuration File + * *** Do not modify ! *** + * + * Project: 'CyaSSL-Full' + * Target: 'CyaSSL-Full' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + +#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */ +#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */ +#define RTE_Drivers_MCI0 /* Driver MCI0 */ +#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */ +#define RTE_FileSystem_Core /* File System Core */ + #define RTE_FileSystem_LFN /* File System with Long Filename support */ +#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */ +#define RTE_Network_Core /* Network Core */ + #define RTE_Network_Debug /* Network Debug Version */ +#define RTE_Network_DNS_Client /* Network DNS Client */ +#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */ +#define RTE_Network_Socket_BSD /* Network Socket BSD */ +#define RTE_Network_Socket_TCP /* Network Socket TCP */ +#define RTE_Network_Socket_UDP /* Network Socket UDP */ + +#endif /* RTE_COMPONENTS_H */ diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini new file mode 100644 index 000000000..239abce37 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/STM32_SWO.ini @@ -0,0 +1,36 @@ +/******************************************************************************/ +/* STM32_SWO.ini: STM32 Debugger Initialization File */ +/******************************************************************************/ +// <<< Use Configuration Wizard in Context Menu >>> // +/******************************************************************************/ +/* This file is part of the uVision/ARM development tools. */ +/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */ +/* This software may only be used under the terms of a valid, current, */ +/* end user licence from KEIL for a compatible version of KEIL software */ +/* development tools. Nothing else gives you the right to use this software. */ +/******************************************************************************/ + + +FUNC void DebugSetup (void) { +// Debug MCU Configuration +// DBG_SLEEP Debug Sleep Mode +// DBG_STOP Debug Stop Mode +// DBG_STANDBY Debug Standby Mode +// TRACE_IOEN Trace I/O Enable +// TRACE_MODE Trace Mode +// <0=> Asynchronous +// <1=> Synchronous: TRACEDATA Size 1 +// <2=> Synchronous: TRACEDATA Size 2 +// <3=> Synchronous: TRACEDATA Size 4 +// DBG_IWDG_STOP Independant Watchdog Stopped when Core is halted +// DBG_WWDG_STOP Window Watchdog Stopped when Core is halted +// DBG_TIM1_STOP Timer 1 Stopped when Core is halted +// DBG_TIM2_STOP Timer 2 Stopped when Core is halted +// DBG_TIM3_STOP Timer 3 Stopped when Core is halted +// DBG_TIM4_STOP Timer 4 Stopped when Core is halted +// DBG_CAN_STOP CAN Stopped when Core is halted +// + _WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR +} + +DebugSetup(); // Debugger Setup diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c new file mode 100644 index 000000000..277e808fa --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/benchmark.c @@ -0,0 +1,1064 @@ +/* benchmark.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* CTaoCrypt benchmark */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#ifdef HAVE_CAVIUM + #include "cavium_sysdep.h" + #include "cavium_common.h" + #include "cavium_ioctl.h" +#endif +#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048) + /* include test cert and key buffers for use with NO_FILESYSTEM */ + #if defined(CYASSL_MDK_ARM) && !defined(SINGLE_THREADED) + #include "cert_data.h" /* use certs_test.c for initial data, + so other commands can share the data. */ + #else + #include + #endif +#endif + +#if defined(CYASSL_MDK_ARM) + #include + extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ; + #define fopen CyaSSL_fopen +#endif + +#ifdef HAVE_BLAKE2 + #include + void bench_blake2(void); +#endif + +#ifdef _MSC_VER + /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */ + #pragma warning(disable: 4996) +#endif + +void bench_des(void); +void bench_arc4(void); +void bench_hc128(void); +void bench_rabbit(void); +void bench_aes(int); +void bench_aesgcm(void); +void bench_aesccm(void); +void bench_camellia(void); + +void bench_md5(void); +void bench_sha(void); +void bench_sha256(void); +void bench_sha512(void); +void bench_ripemd(void); + +void bench_rsa(void); +void bench_rsaKeyGen(void); +void bench_dh(void); +#ifdef HAVE_ECC +void bench_eccKeyGen(void); +void bench_eccKeyAgree(void); +#endif + +double current_time(int); + + +#ifdef HAVE_CAVIUM + +static int OpenNitroxDevice(int dma_mode,int dev_id) +{ + Csp1CoreAssignment core_assign; + Uint32 device; + + if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID)) + return -1; + if (Csp1GetDevType(&device)) + return -1; + if (device != NPX_DEVICE) { + if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT, + (Uint32 *)&core_assign)!= 0) + return -1; + } + CspShutdown(CAVIUM_DEV_ID); + + return CspInitialize(dma_mode, dev_id); +} + +#endif + + +/* so embedded projects can pull in tests on their own */ +#if !defined(NO_MAIN_DRIVER) + +int main(int argc, char** argv) + +{ + (void)argc; + (void)argv; +#else +int benchmark_test(void *args) +{ +#endif + + #ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) { + printf("Cavium OpenNitroxDevice failed\n"); + exit(-1); + } +#endif /* HAVE_CAVIUM */ +#ifndef NO_AES + bench_aes(0); + bench_aes(1); +#endif +#ifdef HAVE_AESGCM + bench_aesgcm(); +#endif +#ifdef HAVE_AESCCM + bench_aesccm(); +#endif +#ifdef HAVE_CAMELLIA + bench_camellia(); +#endif +#ifndef NO_RC4 + bench_arc4(); +#endif +#ifdef HAVE_HC128 + bench_hc128(); +#endif +#ifndef NO_RABBIT + bench_rabbit(); +#endif +#ifndef NO_DES3 + bench_des(); +#endif + + printf("\n"); + +#ifndef NO_MD5 + bench_md5(); +#endif +#ifndef NO_SHA + bench_sha(); +#endif +#ifndef NO_SHA256 + bench_sha256(); +#endif +#ifdef CYASSL_SHA512 + bench_sha512(); +#endif +#ifdef CYASSL_RIPEMD + bench_ripemd(); +#endif +#ifdef HAVE_BLAKE2 + bench_blake2(); +#endif + + printf("\n"); + +#ifndef NO_RSA + bench_rsa(); +#endif + +#ifndef NO_DH + bench_dh(); +#endif + +#if defined(CYASSL_KEY_GEN) && !defined(NO_RSA) + bench_rsaKeyGen(); +#endif + +#ifdef HAVE_ECC + bench_eccKeyGen(); + bench_eccKeyAgree(); +#endif + + return 0; +} + + +#ifdef BENCH_EMBEDDED +const int numBlocks = 25; /* how many kB/megs to test (en/de)cryption */ +const char blockType[] = "kB"; /* used in printf output */ +const int times = 1; /* public key iterations */ +#else +const int numBlocks = 5; +const char blockType[] = "megs"; +const int times = 100; +#endif + +const byte key[] = +{ + 0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef, + 0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10, + 0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67 +}; + +const byte iv[] = +{ + 0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01, + 0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81 + +}; + + +/* use kB instead of mB for embedded benchmarking */ +#ifdef BENCH_EMBEDDED +byte plain [1024]; +byte cipher[1024]; +#else +byte plain [1024*1024]; +byte cipher[1024*1024]; +#endif + + +#ifndef NO_AES +void bench_aes(int show) +{ + Aes enc; + double start, total, persec; + int i; + +#ifdef HAVE_CAVIUM + if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0) + printf("aes init cavium failed\n"); +#endif + + AesSetKey(&enc, key, 16, iv, AES_ENCRYPTION); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesCbcEncrypt(&enc, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + if (show) + printf("AES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +#ifdef HAVE_CAVIUM + AesFreeCavium(&enc); +#endif +} +#endif + + +byte additional[13]; +byte tag[16]; + + +#ifdef HAVE_AESGCM +void bench_aesgcm(void) +{ + Aes enc; + double start, total, persec; + int i; + + AesGcmSetKey(&enc, key, 16); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesGcmEncrypt(&enc, cipher, plain, sizeof(plain), iv, 12, + tag, 16, additional, 13); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("AES-GCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifdef HAVE_AESCCM +void bench_aesccm(void) +{ + Aes enc; + double start, total, persec; + int i; + + AesCcmSetKey(&enc, key, 16); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + AesCcmEncrypt(&enc, cipher, plain, sizeof(plain), iv, 12, + tag, 16, additional, 13); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("AES-CCM %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifdef HAVE_CAMELLIA +void bench_camellia(void) +{ + Camellia cam; + double start, total, persec; + int i; + + CamelliaSetKey(&cam, key, 16, iv); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + CamelliaCbcEncrypt(&cam, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("Camellia %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifndef NO_DES3 +void bench_des(void) +{ + Des3 enc; + double start, total, persec; + int i; + +#ifdef HAVE_CAVIUM + if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0) + printf("des3 init cavium failed\n"); +#endif + Des3_SetKey(&enc, key, iv, DES_ENCRYPTION); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Des3_CbcEncrypt(&enc, plain, cipher, sizeof(plain)); + + total = current_time(0) - start; + + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("3DES %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +#ifdef HAVE_CAVIUM + Des3_FreeCavium(&enc); +#endif +} +#endif + + +#ifndef NO_RC4 +void bench_arc4(void) +{ + Arc4 enc; + double start, total, persec; + int i; + +#ifdef HAVE_CAVIUM + if (Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0) + printf("arc4 init cavium failed\n"); +#endif + + Arc4SetKey(&enc, key, 16); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Arc4Process(&enc, cipher, plain, sizeof(plain)); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("ARC4 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +#ifdef HAVE_CAVIUM + Arc4FreeCavium(&enc); +#endif +} +#endif + + +#ifdef HAVE_HC128 +void bench_hc128(void) +{ + HC128 enc; + double start, total, persec; + int i; + + Hc128_SetKey(&enc, key, iv); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Hc128_Process(&enc, cipher, plain, sizeof(plain)); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("HC128 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* HAVE_HC128 */ + + +#ifndef NO_RABBIT +void bench_rabbit(void) +{ + Rabbit enc; + double start, total, persec; + int i; + + RabbitSetKey(&enc, key, iv); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + RabbitProcess(&enc, cipher, plain, sizeof(plain)); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("RABBIT %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* NO_RABBIT */ + + +#ifndef NO_MD5 +void bench_md5(void) +{ + Md5 hash; + byte digest[MD5_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitMd5(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Md5Update(&hash, plain, sizeof(plain)); + + Md5Final(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("MD5 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* NO_MD5 */ + + +#ifndef NO_SHA +void bench_sha(void) +{ + Sha hash; + byte digest[SHA_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitSha(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + ShaUpdate(&hash, plain, sizeof(plain)); + + ShaFinal(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("SHA %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif /* NO_SHA */ + + +#ifndef NO_SHA256 +void bench_sha256(void) +{ + Sha256 hash; + byte digest[SHA256_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitSha256(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Sha256Update(&hash, plain, sizeof(plain)); + + Sha256Final(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("SHA-256 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + +#ifdef CYASSL_SHA512 +void bench_sha512(void) +{ + Sha512 hash; + byte digest[SHA512_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitSha512(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Sha512Update(&hash, plain, sizeof(plain)); + + Sha512Final(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("SHA-512 %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + +#ifdef CYASSL_RIPEMD +void bench_ripemd(void) +{ + RipeMd hash; + byte digest[RIPEMD_DIGEST_SIZE]; + double start, total, persec; + int i; + + InitRipeMd(&hash); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + RipeMdUpdate(&hash, plain, sizeof(plain)); + + RipeMdFinal(&hash, digest); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("RIPEMD %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#ifdef HAVE_BLAKE2 +void bench_blake2(void) +{ + Blake2b b2b; + byte digest[64]; + double start, total, persec; + int i; + + InitBlake2b(&b2b, 64); + start = current_time(1); + + for(i = 0; i < numBlocks; i++) + Blake2bUpdate(&b2b, plain, sizeof(plain)); + + Blake2bFinal(&b2b, digest, 64); + + total = current_time(0) - start; + persec = 1 / total * numBlocks; +#ifdef BENCH_EMBEDDED + /* since using kB, convert to MB/s */ + persec = persec / 1024; +#endif + + printf("BLAKE2b %d %s took %5.3f seconds, %6.2f MB/s\n", numBlocks, + blockType, total, persec); +} +#endif + + +#if !defined(NO_RSA) || !defined(NO_DH) \ + || defined(CYASSL_KEYGEN) || defined(HAVE_ECC) +RNG rng; +#endif + +#ifndef NO_RSA + + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && \ + defined(CYASSL_MDK_SHELL) +static char *certRSAname = "certs/rsa2048.der" ; +void set_Bench_RSA_File(char * cert) { certRSAname = cert ; } + /* set by shell command */ +#elif defined(CYASSL_MDK_SHELL) + /* nothing */ +#else +static const char *certRSAname = "certs/rsa2048.der" ; +#endif + +void bench_rsa(void) +{ + int i; + int ret; + byte tmp[3072]; + size_t bytes; + word32 idx = 0; + + byte message[] = "Everyone gets Friday off."; + byte enc[512]; /* for up to 4096 bit */ + const int len = (int)strlen((char*)message); + double start, total, each, milliEach; + + RsaKey rsaKey; + int rsaKeySz = 2048; /* used in printf */ + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, rsa_key_der_1024, sizeof_rsa_key_der_1024); + bytes = sizeof_rsa_key_der_1024; + rsaKeySz = 1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, rsa_key_der_2048, sizeof_rsa_key_der_2048); + bytes = sizeof_rsa_key_der_2048; +#else + FILE* file = fopen(certRSAname, "rb"); + + if (!file) { + printf("can't find %s, Please run from CyaSSL home dir\n", certRSAname); + return; + } + + bytes = fread(tmp, 1, sizeof(tmp), file); + fclose(file); +#endif /* USE_CERT_BUFFERS */ + + +#ifdef HAVE_CAVIUM + if (RsaInitCavium(&rsaKey, CAVIUM_DEV_ID) != 0) + printf("RSA init cavium failed\n"); +#endif + ret = InitRng(&rng); + if (ret < 0) { + printf("InitRNG failed\n"); + return; + } + InitRsaKey(&rsaKey, 0); + ret = RsaPrivateKeyDecode(tmp, &idx, &rsaKey, (word32)bytes); + + start = current_time(1); + + for (i = 0; i < times; i++) + ret = RsaPublicEncrypt(message,len,enc,sizeof(enc), &rsaKey, &rng); + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("RSA %d encryption took %6.2f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, times); + + if (ret < 0) { + printf("Rsa Public Encrypt failed\n"); + return; + } + + start = current_time(1); + + for (i = 0; i < times; i++) { + byte out[512]; /* for up to 4096 bit */ + RsaPrivateDecrypt(enc, (word32)ret, out, sizeof(out), &rsaKey); + } + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("RSA %d decryption took %6.2f milliseconds, avg over %d" + " iterations\n", rsaKeySz, milliEach, times); + + FreeRsaKey(&rsaKey); +#ifdef HAVE_CAVIUM + RsaFreeCavium(&rsaKey); +#endif +} +#endif + + +#ifndef NO_DH + + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && \ + defined(CYASSL_MDK_SHELL) +static char *certDHname = "certs/dh2048.der" ; +void set_Bench_DH_File(char * cert) { certDHname = cert ; } + /* set by shell command */ +#elif defined(CYASSL_MDK_SHELL) + /* nothing */ +#else +static const char *certDHname = "certs/dh2048.der" ; +#endif + +void bench_dh(void) +{ + int i; + byte tmp[1024]; + size_t bytes; + word32 idx = 0, pubSz, privSz, pubSz2, privSz2, agreeSz; + + byte pub[256]; /* for 2048 bit */ + byte priv[256]; /* for 2048 bit */ + byte pub2[256]; /* for 2048 bit */ + byte priv2[256]; /* for 2048 bit */ + byte agree[256]; /* for 2048 bit */ + + double start, total, each, milliEach; + DhKey dhKey; + int dhKeySz = 2048; /* used in printf */ + + +#ifdef USE_CERT_BUFFERS_1024 + XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024); + bytes = sizeof_dh_key_der_1024; + dhKeySz = 1024; +#elif defined(USE_CERT_BUFFERS_2048) + XMEMCPY(tmp, dh_key_der_2048, sizeof_dh_key_der_2048); + bytes = sizeof_dh_key_der_2048; +#else + FILE* file = fopen(certDHname, "rb"); + + if (!file) { + printf("can't find %s, Please run from CyaSSL home dir\n", certDHname); + return; + } + + bytes = fread(tmp, 1, sizeof(tmp), file); +#endif /* USE_CERT_BUFFERS */ + + + InitDhKey(&dhKey); + bytes = DhKeyDecode(tmp, &idx, &dhKey, (word32)bytes); + if (bytes != 0) { + printf("dhekydecode failed, can't benchmark\n"); + #if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + fclose(file); + #endif + return; + } + + start = current_time(1); + + for (i = 0; i < times; i++) + DhGenerateKeyPair(&dhKey, &rng, priv, &privSz, pub, &pubSz); + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("DH %d key generation %6.2f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, times); + + DhGenerateKeyPair(&dhKey, &rng, priv2, &privSz2, pub2, &pubSz2); + start = current_time(1); + + for (i = 0; i < times; i++) + DhAgree(&dhKey, agree, &agreeSz, priv, privSz, pub2, pubSz2); + + total = current_time(0) - start; + each = total / times; /* per second */ + milliEach = each * 1000; /* milliseconds */ + + printf("DH %d key agreement %6.2f milliseconds, avg over %d" + " iterations\n", dhKeySz, milliEach, times); + +#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) + fclose(file); +#endif + FreeDhKey(&dhKey); +} +#endif + +#if defined(CYASSL_KEY_GEN) && !defined(NO_RSA) +void bench_rsaKeyGen(void) +{ + RsaKey genKey; + double start, total, each, milliEach; + int i; + const int genTimes = 5; + + /* 1024 bit */ + start = current_time(1); + + for(i = 0; i < genTimes; i++) { + InitRsaKey(&genKey, 0); + MakeRsaKey(&genKey, 1024, 65537, &rng); + FreeRsaKey(&genKey); + } + + total = current_time(0) - start; + each = total / genTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("\n"); + printf("RSA 1024 key generation %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, genTimes); + + /* 2048 bit */ + start = current_time(1); + + for(i = 0; i < genTimes; i++) { + InitRsaKey(&genKey, 0); + MakeRsaKey(&genKey, 2048, 65537, &rng); + FreeRsaKey(&genKey); + } + + total = current_time(0) - start; + each = total / genTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("RSA 2048 key generation %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, genTimes); +} +#endif /* CYASSL_KEY_GEN */ + +#ifdef HAVE_ECC +void bench_eccKeyGen(void) +{ + ecc_key genKey; + double start, total, each, milliEach; + int i; + const int genTimes = 5; + + /* 256 bit */ + start = current_time(1); + + for(i = 0; i < genTimes; i++) { + ecc_make_key(&rng, 32, &genKey); + ecc_free(&genKey); + } + + total = current_time(0) - start; + each = total / genTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("\n"); + printf("ECC 256 key generation %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, genTimes); +} + + +void bench_eccKeyAgree(void) +{ + ecc_key genKey, genKey2; + double start, total, each, milliEach; + int i, ret; + const int agreeTimes = 5; + byte shared[1024]; + byte sig[1024]; + byte digest[32]; + word32 x; + + ecc_init(&genKey); + ecc_init(&genKey2); + + ret = ecc_make_key(&rng, 32, &genKey); + if (ret != 0) { + printf("ecc_make_key failed\n"); + return; + } + ret = ecc_make_key(&rng, 32, &genKey2); + if (ret != 0) { + printf("ecc_make_key failed\n"); + return; + } + + /* 256 bit */ + start = current_time(1); + + for(i = 0; i < agreeTimes; i++) { + x = sizeof(shared); + ecc_shared_secret(&genKey, &genKey2, shared, &x); + } + + total = current_time(0) - start; + each = total / agreeTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("EC-DHE key agreement %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, agreeTimes); + + /* make dummy digest */ + for (i = 0; i < (int)sizeof(digest); i++) + digest[i] = i; + + + start = current_time(1); + + for(i = 0; i < agreeTimes; i++) { + x = sizeof(sig); + ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &genKey); + } + + total = current_time(0) - start; + each = total / agreeTimes; /* per second */ + milliEach = each * 1000; /* millisconds */ + printf("EC-DSA sign time %6.2f milliseconds, avg over %d" + " iterations\n", milliEach, agreeTimes); + + ecc_free(&genKey2); + ecc_free(&genKey); +} +#endif /* HAVE_ECC */ + + +#ifdef _WIN32 + + #define WIN32_LEAN_AND_MEAN + #include + + double current_time(int reset) + { + (void)reset; + + static int init = 0; + static LARGE_INTEGER freq; + + LARGE_INTEGER count; + + if (!init) { + QueryPerformanceFrequency(&freq); + init = 1; + } + + QueryPerformanceCounter(&count); + + return (double)count.QuadPart / freq.QuadPart; + } + +#elif defined MICROCHIP_PIC32 + + #include + + double current_time(int reset) + { + /* NOTE: core timer tick rate = 40 Mhz, 1 tick = 25 ns */ + + unsigned int ns; + + /* should we reset our timer back to zero? Helps prevent timer + rollover */ + + if (reset) { + WriteCoreTimer(0); + } + + /* get timer in ns */ + ns = ReadCoreTimer() * 25; + + /* return seconds as a double */ + return ( ns / 1000000000.0 ); + } + +#elif defined CYASSL_MDK_ARM + extern double current_time(int reset) ; +#else + + #include + + double current_time(int reset) + { + (void) reset; + + struct timeval tv; + gettimeofday(&tv, 0); + + return (double)tv.tv_sec + (double)tv.tv_usec / 1000000; + } + +#endif /* _WIN32 */ + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/cert_data.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/cert_data.c new file mode 100644 index 000000000..398d85c70 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/cert_data.c @@ -0,0 +1,28 @@ +/* certs_test.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +/* Define initial data for cert buffers */ +#include + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c new file mode 100644 index 000000000..2fd81fe2a --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/client.c @@ -0,0 +1,755 @@ +/* client.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + #define CYASSL_MDK_ARM +#if defined(CYASSL_MDK_ARM) + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif + +#include + +#if !defined(CYASSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER) + /* in case memory tracker wants stats */ + #define CYASSL_TRACK_MEMORY +#endif + +#include + +#ifdef CYASSL_MDK_SHELL +extern void exit_command(void) ; +#define exit(code) exit_command() +#endif + +#include + +#include "examples/client/client.h" + +#define USE_CYASSL_MEMORY + +#ifdef CYASSL_CALLBACKS + int handShakeCB(HandShakeInfo*); + int timeoutCB(TimeoutInfo*); + Timeval timeout; +#endif + + +static void NonBlockingSSL_Connect(CYASSL* ssl) +{ +#ifndef CYASSL_CALLBACKS + int ret = CyaSSL_connect(ssl); +#else + int ret = CyaSSL_connect_ex(ssl, handShakeCB, timeoutCB, timeout); +#endif + int error = CyaSSL_get_error(ssl, 0); + SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl); + int select_ret; + + while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ || + error == SSL_ERROR_WANT_WRITE)) { + int currTimeout = 1; + + if (error == SSL_ERROR_WANT_READ) + printf("... client would read block\n"); + else + printf("... client would write block\n"); + +#ifdef CYASSL_DTLS + currTimeout = CyaSSL_dtls_get_current_timeout(ssl); +#endif + select_ret = tcp_select(sockfd, currTimeout); + + if ((select_ret == TEST_RECV_READY) || + (select_ret == TEST_ERROR_READY)) { + #ifndef CYASSL_CALLBACKS + ret = CyaSSL_connect(ssl); + #else + ret = CyaSSL_connect_ex(ssl,handShakeCB,timeoutCB,timeout); + #endif + error = CyaSSL_get_error(ssl, 0); + } + else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) { + error = SSL_ERROR_WANT_READ; + } +#ifdef CYASSL_DTLS + else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) && + CyaSSL_dtls_got_timeout(ssl) >= 0) { + error = SSL_ERROR_WANT_READ; + } +#endif + else { + error = SSL_FATAL_ERROR; + } + } + if (ret != SSL_SUCCESS) + err_sys("SSL_connect failed"); +} + + +static void Usage(void) +{ + printf("client " LIBCYASSL_VERSION_STRING + " NOTE: All files relative to CyaSSL home dir\n"); + printf("-? Help, print this usage\n"); + printf("-h Host to connect to, default %s\n", yasslIP); + printf("-p Port to connect on, not 0, default %d\n", yasslPort); + printf("-v SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n", + CLIENT_DEFAULT_VERSION); + printf("-l Cipher list\n"); + printf("-c Certificate file, default %s\n", cliCert); + printf("-k Key file, default %s\n", cliKey); + printf("-A Certificate Authority file, default %s\n", caCert); + printf("-b Benchmark connections and print stats\n"); + printf("-s Use pre Shared keys\n"); + printf("-t Track CyaSSL memory use\n"); + printf("-d Disable peer checks\n"); + printf("-g Send server HTTP GET\n"); + printf("-u Use UDP DTLS," + " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n"); + printf("-m Match domain name in cert\n"); + printf("-N Use Non-blocking sockets\n"); + printf("-r Resume session\n"); + printf("-f Fewer packets/group messages\n"); + printf("-x Disable client cert/key loading\n"); +#ifdef SHOW_SIZES + printf("-z Print structure sizes\n"); +#endif + printf("-S Use Host Name Indication\n"); +} + + +THREAD_RETURN CYASSL_THREAD client_test(void* args) +{ + SOCKET_T sockfd = 0; + + CYASSL_METHOD* method = 0; + CYASSL_CTX* ctx = 0; + CYASSL* ssl = 0; + + CYASSL* sslResume = 0; + CYASSL_SESSION* session = 0; + char resumeMsg[] = "resuming cyassl!"; + int resumeSz = sizeof(resumeMsg); + + char msg[32] = "hello cyassl!"; /* GET may make bigger */ + char reply[80]; + int input; + int msgSz = (int)strlen(msg); + + int port = yasslPort; + char* host = (char*)yasslIP; + char* domain = (char*)"www.yassl.com"; + + int ch; + int version = CLIENT_INVALID_VERSION; + int usePsk = 0; + int sendGET = 0; + int benchmark = 0; + int doDTLS = 0; + int matchName = 0; + int doPeerCheck = 1; + int nonBlocking = 0; + int resumeSession = 0; + int trackMemory = 0; + int useClientCert = 1; + int fewerPackets = 0; + char* cipherList = NULL; + char* verifyCert = (char*)caCert; + char* ourCert = (char*)cliCert; + char* ourKey = (char*)cliKey; + +#ifdef HAVE_SNI + char* sniHostName = NULL; +#endif + + int argc = ((func_args*)args)->argc; + char** argv = ((func_args*)args)->argv; + + ((func_args*)args)->return_code = -1; /* error state */ + +#ifdef NO_RSA + verifyCert = (char*)eccCert; + ourCert = (char*)cliEccCert; + ourKey = (char*)cliEccKey; +#endif + (void)resumeSz; + (void)session; + (void)sslResume; + (void)trackMemory; + + while ((ch = mygetopt(argc, argv, "?gdusmNrtfxh:p:v:l:A:c:k:b:zS:")) != -1){ + switch (ch) { + case '?' : + Usage(); + exit(EXIT_SUCCESS); + + case 'g' : + sendGET = 1; + break; + + case 'd' : + doPeerCheck = 0; + break; + + case 'u' : + doDTLS = 1; + break; + + case 's' : + usePsk = 1; + break; + + case 't' : + #ifdef USE_CYASSL_MEMORY + trackMemory = 1; + #endif + break; + + case 'm' : + matchName = 1; + break; + + case 'x' : + useClientCert = 0; + break; + + case 'f' : + fewerPackets = 1; + break; + + case 'h' : + host = myoptarg; + domain = myoptarg; + break; + + case 'p' : + port = atoi(myoptarg); + #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API) + if (port == 0) + err_sys("port number cannot be 0"); + #endif + break; + + case 'v' : + version = atoi(myoptarg); + if (version < 0 || version > 3) { + Usage(); + exit(MY_EX_USAGE); + } + break; + + case 'l' : + cipherList = myoptarg; + break; + + case 'A' : + verifyCert = myoptarg; + break; + + case 'c' : + ourCert = myoptarg; + break; + + case 'k' : + ourKey = myoptarg; + break; + + case 'b' : + benchmark = atoi(myoptarg); + if (benchmark < 0 || benchmark > 1000000) { + Usage(); + exit(MY_EX_USAGE); + } + break; + + case 'N' : + nonBlocking = 1; + break; + + case 'r' : + resumeSession = 1; + break; + + case 'z' : + #ifndef CYASSL_LEANPSK + CyaSSL_GetObjectSize(); + #endif + break; + + case 'S' : + #ifdef HAVE_SNI + sniHostName = myoptarg; + #endif + break; + + default: + Usage(); + exit(MY_EX_USAGE); + } + } + + myoptind = 0; /* reset for test cases */ + + /* sort out DTLS versus TLS versions */ + if (version == CLIENT_INVALID_VERSION) { + if (doDTLS) + version = CLIENT_DTLS_DEFAULT_VERSION; + else + version = CLIENT_DEFAULT_VERSION; + } + else { + if (doDTLS) { + if (version == 3) + version = -2; + else + version = -1; + } + } + +#ifdef USE_CYASSL_MEMORY + if (trackMemory) + InitMemoryTracker(); +#endif + + switch (version) { +#ifndef NO_OLD_TLS + case 0: + method = CyaSSLv3_client_method(); + break; + + + #ifndef NO_TLS + case 1: + method = CyaTLSv1_client_method(); + break; + + case 2: + method = CyaTLSv1_1_client_method(); + break; + #endif /* NO_TLS */ + +#endif /* NO_OLD_TLS */ + +#ifndef NO_TLS + case 3: + method = CyaTLSv1_2_client_method(); + break; +#endif + +#ifdef CYASSL_DTLS + case -1: + method = CyaDTLSv1_client_method(); + break; + + case -2: + method = CyaDTLSv1_2_client_method(); + break; +#endif + + default: + err_sys("Bad SSL version"); + break; + } + + if (method == NULL) + err_sys("unable to get method"); + + ctx = CyaSSL_CTX_new(method); + if (ctx == NULL) + err_sys("unable to get ctx"); + + if (cipherList) + if (CyaSSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS) + err_sys("client can't set cipher list 1"); + +#ifdef CYASSL_LEANPSK + usePsk = 1; +#endif + +#if defined(NO_RSA) && !defined(HAVE_ECC) + usePsk = 1; +#endif + + if (fewerPackets) + CyaSSL_CTX_set_group_messages(ctx); + + if (usePsk) { +#ifndef NO_PSK + CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb); + if (cipherList == NULL) { + const char *defaultCipherList; + #ifdef HAVE_NULL_CIPHER + defaultCipherList = "PSK-NULL-SHA256"; + #else + defaultCipherList = "PSK-AES128-CBC-SHA256"; + #endif + if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS) + err_sys("client can't set cipher list 2"); + } +#endif + useClientCert = 0; + } + +#ifdef OPENSSL_EXTRA + CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + +#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC) + if (cipherList == NULL) { + /* don't use EDH, can't sniff tmp keys */ + if (CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS) { + err_sys("client can't set cipher list 3"); + } + } +#endif + +#ifdef USER_CA_CB + CyaSSL_CTX_SetCACb(ctx, CaCb); +#endif + +#ifdef VERIFY_CALLBACK + CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_PEER, myVerify); +#endif +#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS) + if (useClientCert){ + if (CyaSSL_CTX_use_certificate_chain_file(ctx, ourCert) != SSL_SUCCESS) + err_sys("can't load client cert file, check file and run from" + " CyaSSL home dir"); + + if (CyaSSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load client private key file, check file and run " + "from CyaSSL home dir"); + } + + if (!usePsk) { + if (CyaSSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS) + err_sys("can't load ca file, Please run from CyaSSL home dir"); + } +#endif +#if !defined(NO_CERTS) + if (!usePsk && doPeerCheck == 0) + CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); +#endif + +#ifdef HAVE_CAVIUM + CyaSSL_CTX_UseCavium(ctx, CAVIUM_DEV_ID); +#endif + +#ifdef HAVE_SNI + if (sniHostName) + if (CyaSSL_CTX_UseSNI(ctx, 0, sniHostName, XSTRLEN(sniHostName))) + err_sys("UseSNI failed"); +#endif + + if (benchmark) { + /* time passed in number of connects give average */ + int times = benchmark; + int i = 0; + + double start = current_time(), avg; + + for (i = 0; i < times; i++) { + tcp_connect(&sockfd, host, port, doDTLS); + + ssl = CyaSSL_new(ctx); + CyaSSL_set_fd(ssl, sockfd); + if (CyaSSL_connect(ssl) != SSL_SUCCESS) + err_sys("SSL_connect failed"); + + CyaSSL_shutdown(ssl); + CyaSSL_free(ssl); + CloseSocket(sockfd); + } + avg = current_time() - start; + avg /= times; + avg *= 1000; /* milliseconds */ + printf("CyaSSL_connect avg took: %8.3f milliseconds\n", avg); + + CyaSSL_CTX_free(ctx); + ((func_args*)args)->return_code = 0; + + exit(EXIT_SUCCESS); + } + + #if defined(CYASSL_MDK_ARM) + CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + #endif + + ssl = CyaSSL_new(ctx); + if (ssl == NULL) + err_sys("unable to get SSL object"); + + CyaSSL_set_quiet_shutdown(ssl, 1) ; + + if (doDTLS) { + SOCKADDR_IN_T addr; + build_addr(&addr, host, port, 1); + CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr)); + tcp_socket(&sockfd, 1); + } + else { + tcp_connect(&sockfd, host, port, 0); + } + CyaSSL_set_fd(ssl, sockfd); +#ifdef HAVE_CRL + if (CyaSSL_EnableCRL(ssl, CYASSL_CRL_CHECKALL) != SSL_SUCCESS) + err_sys("can't enable crl check"); + if (CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, 0) != SSL_SUCCESS) + err_sys("can't load crl, check crlfile and date validity"); + if (CyaSSL_SetCRL_Cb(ssl, CRL_CallBack) != SSL_SUCCESS) + err_sys("can't set crl callback"); +#endif + if (matchName && doPeerCheck) + CyaSSL_check_domain_name(ssl, domain); +#ifndef CYASSL_CALLBACKS + if (nonBlocking) { + CyaSSL_set_using_nonblock(ssl, 1); + tcp_set_nonblocking(&sockfd); + NonBlockingSSL_Connect(ssl); + } + else if (CyaSSL_connect(ssl) != SSL_SUCCESS) { + /* see note at top of README */ + int err = CyaSSL_get_error(ssl, 0); + char buffer[80]; + printf("err = %d, %s\n", err, + CyaSSL_ERR_error_string(err, buffer)); + err_sys("SSL_connect failed"); + /* if you're getting an error here */ + } +#else + timeout.tv_sec = 2; + timeout.tv_usec = 0; + NonBlockingSSL_Connect(ssl); /* will keep retrying on timeout */ +#endif + showPeer(ssl); + + if (sendGET) { + printf("SSL connect ok, sending GET...\n"); + msgSz = 28; + strncpy(msg, "GET / HTTP/1.0\r\n\r\n", msgSz); + msg[msgSz] = '\0'; + } + if (CyaSSL_write(ssl, msg, msgSz) != msgSz) + err_sys("SSL_write failed"); + + input = CyaSSL_read(ssl, reply, sizeof(reply)-1); + if (input > 0) { + reply[input] = 0; + printf("Server response: %s", reply); + + if (sendGET && (input == (sizeof(reply)-1))) { /* get html */ + while (1) { + input = CyaSSL_read(ssl, reply, sizeof(reply)-1); + if (input > 0) { + reply[input] = 0; + printf("%s", reply); + if(input < sizeof(reply)-1) + break ; + } + else + break; + } + } + printf("\n"); + } + else if (input < 0) { + int readErr = CyaSSL_get_error(ssl, 0); + if (readErr != SSL_ERROR_WANT_READ) + err_sys("CyaSSL_read failed"); + } + +#ifdef CYASSL_CMSIS_RTOS + osDelay(5000) ; +#endif + +#ifndef NO_SESSION_CACHE + if (resumeSession) { + if (doDTLS) { + strncpy(msg, "break", 6); + msgSz = (int)strlen(msg); + /* try to send session close */ + CyaSSL_write(ssl, msg, msgSz); + } + session = CyaSSL_get_session(ssl); + sslResume = CyaSSL_new(ctx); + } +#endif + + if (doDTLS == 0) /* don't send alert after "break" command */ + CyaSSL_shutdown(ssl); /* echoserver will interpret as new conn */ + CyaSSL_free(ssl); + CloseSocket(sockfd); + +#ifndef NO_SESSION_CACHE + if (resumeSession) { + if (doDTLS) { + SOCKADDR_IN_T addr; + #ifdef USE_WINDOWS_API + Sleep(500); + #else + sleep(1); + #endif + build_addr(&addr, host, port, 1); + CyaSSL_dtls_set_peer(sslResume, &addr, sizeof(addr)); + tcp_socket(&sockfd, 1); + } + else { + tcp_connect(&sockfd, host, port, 0); + } + CyaSSL_set_fd(sslResume, sockfd); + CyaSSL_set_session(sslResume, session); + + showPeer(sslResume); +#ifndef CYASSL_CALLBACKS + if (nonBlocking) { + CyaSSL_set_using_nonblock(sslResume, 1); + tcp_set_nonblocking(&sockfd); + NonBlockingSSL_Connect(sslResume); + } + else if (CyaSSL_connect(sslResume) != SSL_SUCCESS) + err_sys("SSL resume failed"); +#else + timeout.tv_sec = 2; + timeout.tv_usec = 0; + NonBlockingSSL_Connect(ssl); /* will keep retrying on timeout */ +#endif + + if (CyaSSL_session_reused(sslResume)) + printf("reused session id\n"); + else + printf("didn't reuse session id!!!\n"); + + if (CyaSSL_write(sslResume, resumeMsg, resumeSz) != resumeSz) + err_sys("SSL_write failed"); + + if (nonBlocking) { + /* give server a chance to bounce a message back to client */ + #ifdef USE_WINDOWS_API + Sleep(500); + #else + sleep(1); + #endif + } + + input = CyaSSL_read(sslResume, reply, sizeof(reply)-1); + if (input > 0) { + reply[input] = 0; + printf("Server resume response: %s\n", reply); + } + + /* try to send session break */ + CyaSSL_write(sslResume, msg, msgSz); + + CyaSSL_shutdown(sslResume); + CyaSSL_free(sslResume); + CloseSocket(sockfd); + } +#endif /* NO_SESSION_CACHE */ + + CyaSSL_CTX_free(ctx); + + ((func_args*)args)->return_code = 0; + +#ifdef USE_CYASSL_MEMORY + if (trackMemory) + ShowMemoryTracker(); +#endif /* USE_CYASSL_MEMORY */ + + return 0; +} + + +/* so overall tests can pull in test function */ +#ifndef NO_MAIN_DRIVER + + int main(int argc, char** argv) + { + func_args args; + +#ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) + err_sys("Cavium OpenNitroxDevice failed"); +#endif /* HAVE_CAVIUM */ + + StartTCP(); + + args.argc = argc; + args.argv = argv; + + CyaSSL_Init(); +#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) + CyaSSL_Debugging_ON(); +#endif + if (CurrentDir("client") || CurrentDir("build")) + ChangeDirBack(2); + +#ifdef HAVE_STACK_SIZE + StackSizeCheck(&args, client_test); +#else + client_test(&args); +#endif + CyaSSL_Cleanup(); + +#ifdef HAVE_CAVIUM + CspShutdown(CAVIUM_DEV_ID); +#endif + return args.return_code; + } + + int myoptind = 0; + char* myoptarg = NULL; + +#endif /* NO_MAIN_DRIVER */ + + + +#ifdef CYASSL_CALLBACKS + + int handShakeCB(HandShakeInfo* info) + { + (void)info; + return 0; + } + + + int timeoutCB(TimeoutInfo* info) + { + (void)info; + return 0; + } + +#endif + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c new file mode 100644 index 000000000..bc7e26310 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoclient.c @@ -0,0 +1,287 @@ +/* echoclient.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +#include + +#if defined(CYASSL_MDK_ARM) + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif + +#include + +#include "examples/echoclient/echoclient.h" + +void echoclient_test(void* args) +{ + SOCKET_T sockfd = 0; + + FILE* fin = stdin ; + FILE* fout = stdout; + + int inCreated = 0; + int outCreated = 0; + + char msg[1024]; + char reply[1024+1]; + + SSL_METHOD* method = 0; + SSL_CTX* ctx = 0; + SSL* ssl = 0; + + int doDTLS = 0; + int doPSK = 0; + int sendSz; + int argc = 0; + char** argv = 0; + int port = yasslPort; + + ((func_args*)args)->return_code = -1; /* error state */ + +#ifndef CYASSL_MDK_ARM + argc = ((func_args*)args)->argc; + argv = ((func_args*)args)->argv; +#endif + + if (argc >= 2) { + fin = fopen(argv[1], "r"); + inCreated = 1; + } + if (argc >= 3) { + fout = fopen(argv[2], "w"); + outCreated = 1; + } + + if (!fin) err_sys("can't open input file"); + if (!fout) err_sys("can't open output file"); + +#ifdef CYASSL_DTLS + doDTLS = 1; +#endif + +#ifdef CYASSL_LEANPSK + doPSK = 1; +#endif + +#if defined(NO_RSA) && !defined(HAVE_ECC) + doPSK = 1; +#endif + +#if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && !defined(CYASSL_MDK_SHELL) + port = ((func_args*)args)->signal->port; +#endif +#if defined (CYASSL_CALLEE_PORT) + port = CYASSL_CALLEE_PORT ; +#endif + +#if defined(CYASSL_DTLS) + method = DTLSv1_client_method(); +#elif !defined(NO_TLS) + method = CyaSSLv23_client_method(); +#else + method = SSLv3_client_method(); +#endif + ctx = SSL_CTX_new(method); + +#ifndef NO_FILESYSTEM + #ifndef NO_RSA + if (SSL_CTX_load_verify_locations(ctx, caCert, 0) != SSL_SUCCESS) + err_sys("can't load ca file, Please run from CyaSSL home dir"); + #endif + #ifdef HAVE_ECC + if (SSL_CTX_load_verify_locations(ctx, eccCert, 0) != SSL_SUCCESS) + err_sys("can't load ca file, Please run from CyaSSL home dir"); + #endif +#elif !defined(NO_CERTS) + if (!doPSK) + load_buffer(ctx, caCert, CYASSL_CA); +#endif + +#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC) + /* don't use EDH, can't sniff tmp keys */ + SSL_CTX_set_cipher_list(ctx, "AES256-SHA"); +#endif + if (doPSK) { +#ifndef NO_PSK + const char *defaultCipherList; + + CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb); + #ifdef HAVE_NULL_CIPHER + defaultCipherList = "PSK-NULL-SHA256"; + #else + defaultCipherList = "PSK-AES128-CBC-SHA256"; + #endif + if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS) + err_sys("client can't set cipher list 2"); +#endif + } + +#ifdef OPENSSL_EXTRA + SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + + #if defined(CYASSL_MDK_ARM) + CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0); + #endif + + ssl = SSL_new(ctx); + CyaSSL_set_quiet_shutdown(ssl, 1) ; + + if (doDTLS) { + SOCKADDR_IN_T addr; + build_addr(&addr, yasslIP, port, 1); + CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr)); + tcp_socket(&sockfd, 1); + } + else { + tcp_connect(&sockfd, yasslIP, port, 0); + } + + SSL_set_fd(ssl, sockfd); +#if defined(USE_WINDOWS_API) && defined(CYASSL_DTLS) && defined(NO_MAIN_DRIVER) + /* let echoserver bind first, TODO: add Windows signal like pthreads does */ + Sleep(100); +#endif + + if (SSL_connect(ssl) != SSL_SUCCESS) err_sys("SSL_connect failed"); + + while (fgets(msg, sizeof(msg), fin) != 0) { + + sendSz = (int)strlen(msg); + + if (SSL_write(ssl, msg, sendSz) != sendSz) + err_sys("SSL_write failed"); + + if (strncmp(msg, "quit", 4) == 0) { + fputs("sending server shutdown command: quit!\n", fout); + break; + } + + if (strncmp(msg, "break", 5) == 0) { + fputs("sending server session close: break!\n", fout); + break; + } + + #ifndef CYASSL_MDK_SHELL + while (sendSz) { + int got; + if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) { + reply[got] = 0; + fputs(reply, fout); + fflush(fout) ; + sendSz -= got; + } + else + break; + } + #else + { + int got; + if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) { + reply[got] = 0; + fputs(reply, fout); + fflush(fout) ; + sendSz -= got; + } + } + #endif + } + +#ifdef CYASSL_CMSIS_RTOS + osDelay(5000) ; +#endif + + +#ifdef CYASSL_DTLS + strncpy(msg, "break", 6); + sendSz = (int)strlen(msg); + /* try to tell server done */ + SSL_write(ssl, msg, sendSz); +#else + SSL_shutdown(ssl); +#endif + + SSL_free(ssl); + SSL_CTX_free(ctx); + + fflush(fout); + if (inCreated) fclose(fin); + if (outCreated) fclose(fout); + + CloseSocket(sockfd); + ((func_args*)args)->return_code = 0; +} + + +/* so overall tests can pull in test function */ +#ifndef NO_MAIN_DRIVER + + int main(int argc, char** argv) + { + func_args args; + +#ifdef HAVE_CAVIUM + int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID); + if (ret != 0) + err_sys("Cavium OpenNitroxDevice failed"); +#endif /* HAVE_CAVIUM */ + + StartTCP(); + + args.argc = argc; + args.argv = argv; + + CyaSSL_Init(); +#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL) + CyaSSL_Debugging_ON(); +#endif + + if (CurrentDir("echoclient") || CurrentDir("build")) + ChangeDirBack(2); + echoclient_test(&args); + + CyaSSL_Cleanup(); + +#ifdef HAVE_CAVIUM + CspShutdown(CAVIUM_DEV_ID); +#endif + return args.return_code; + } + +#endif /* NO_MAIN_DRIVER */ + + diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c new file mode 100644 index 000000000..ba8e10f18 --- /dev/null +++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/echoserver.c @@ -0,0 +1,370 @@ +/* echoserver.c + * + * Copyright (C) 2006-2013 wolfSSL Inc. + * + * This file is part of CyaSSL. + * + * CyaSSL is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * CyaSSL is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +#ifdef HAVE_CONFIG_H + #include +#endif + +#include + +#if defined(CYASSL_MDK_ARM) + #include + #include + + #if defined(CYASSL_MDK5) + #include "cmsis_os.h" + #include "rl_fs.h" + #include "rl_net.h" + #else + #include "rtl.h" + #endif + + #include "cyassl_MDK_ARM.h" +#endif + +#include +#include + +#ifndef NO_MAIN_DRIVER + #define ECHO_OUT +#endif + +#include "examples/echoserver/echoserver.h" + + +#ifdef SESSION_STATS + CYASSL_API void PrintSessionStats(void); +#endif + +#define SVR_COMMAND_SIZE 256 + +static void SignalReady(void* args, int port) +{ +#if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__) + /* signal ready to tcp_accept */ + func_args* server_args = (func_args*)args; + tcp_ready* ready = server_args->signal; + pthread_mutex_lock(&ready->mutex); + ready->ready = 1; + ready->port = port; + pthread_cond_signal(&ready->cond); + pthread_mutex_unlock(&ready->mutex); +#endif + (void)args; + (void)port; +} + + +THREAD_RETURN CYASSL_THREAD echoserver_test(void* args) +{ + SOCKET_T sockfd = 0; + CYASSL_METHOD* method = 0; + CYASSL_CTX* ctx = 0; + + int doDTLS = 0; + int doPSK = 0; + int outCreated = 0; + int shutDown = 0; + int useAnyAddr = 0; + int port = yasslPort; + int argc = ((func_args*)args)->argc; + char** argv = ((func_args*)args)->argv; + +#ifdef ECHO_OUT + FILE* fout = stdout; + if (argc >= 2) { + fout = fopen(argv[1], "w"); + outCreated = 1; + } + if (!fout) err_sys("can't open output file"); +#endif + (void)outCreated; + (void)argc; + (void)argv; + + ((func_args*)args)->return_code = -1; /* error state */ + +#ifdef CYASSL_DTLS + doDTLS = 1; +#endif + +#ifdef CYASSL_LEANPSK + doPSK = 1; +#endif + +#if defined(NO_RSA) && !defined(HAVE_ECC) + doPSK = 1; +#endif + + #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \ + !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_ARM) + port = 0; + #endif + #if defined(USE_ANY_ADDR) + useAnyAddr = 1; + #endif + tcp_listen(&sockfd, &port, useAnyAddr, doDTLS); + +#if defined(CYASSL_DTLS) + method = CyaDTLSv1_server_method(); +#elif !defined(NO_TLS) + method = CyaSSLv23_server_method(); +#else + method = CyaSSLv3_server_method(); +#endif + ctx = CyaSSL_CTX_new(method); + /* CyaSSL_CTX_set_session_cache_mode(ctx, SSL_SESS_CACHE_OFF); */ + +#ifdef OPENSSL_EXTRA + CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack); +#endif + +#ifndef NO_FILESYSTEM + if (doPSK == 0) { + #ifdef HAVE_NTRU + /* ntru */ + if (CyaSSL_CTX_use_certificate_file(ctx, ntruCert, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load ntru cert file, " + "Please run from CyaSSL home dir"); + + if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ntruKey) + != SSL_SUCCESS) + err_sys("can't load ntru key file, " + "Please run from CyaSSL home dir"); + #elif defined(HAVE_ECC) + /* ecc */ + if (CyaSSL_CTX_use_certificate_file(ctx, eccCert, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server cert file, " + "Please run from CyaSSL home dir"); + + if (CyaSSL_CTX_use_PrivateKey_file(ctx, eccKey, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server key file, " + "Please run from CyaSSL home dir"); + #elif defined(NO_CERTS) + /* do nothing, just don't load cert files */ + #else + /* normal */ + if (CyaSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server cert file, " + "Please run from CyaSSL home dir"); + + if (CyaSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM) + != SSL_SUCCESS) + err_sys("can't load server key file, " + "Please run from CyaSSL home dir"); + #endif + } /* doPSK */ +#elif !defined(NO_CERTS) + if (!doPSK) { + load_buffer(ctx, svrCert, CYASSL_CERT); + load_buffer(ctx, svrKey, CYASSL_KEY); + } +#endif + +#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC) + /* don't use EDH, can't sniff tmp keys */ + CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA"); +#endif + + if (doPSK) { +#ifndef NO_PSK + const char *defaultCipherList; + + CyaSSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb); + CyaSSL_CTX_use_psk_identity_hint(ctx, "cyassl server"); + #ifdef HAVE_NULL_CIPHER + defaultCipherList = "PSK-NULL-SHA256"; + #else + defaultCipherList = "PSK-AES128-CBC-SHA256"; + #endif + if (CyaSSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS) + err_sys("server can't set cipher list 2"); +#endif + } + + SignalReady(args, port); + + while (!shutDown) { + CYASSL* ssl = 0; + char command[SVR_COMMAND_SIZE+1]; + int echoSz = 0; + int clientfd; + int firstRead = 1; + int gotFirstG = 0; + +#ifndef CYASSL_DTLS + SOCKADDR_IN_T client; + socklen_t client_len = sizeof(client); + clientfd = accept(sockfd, (struct sockaddr*)&client, + (ACCEPT_THIRD_T)&client_len); +#else + clientfd = udp_read_connect(sockfd); +#endif + if (clientfd == -1) err_sys("tcp accept failed"); + + ssl = CyaSSL_new(ctx); + if (ssl == NULL) err_sys("SSL_new failed"); + CyaSSL_set_quiet_shutdown(ssl, 1) ; + + CyaSSL_set_fd(ssl, clientfd); + #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA) + CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM); + #elif !defined(NO_CERTS) + SetDH(ssl); /* will repick suites with DHE, higher than PSK */ + #endif + if (CyaSSL_accept(ssl) != SSL_SUCCESS) { + printf("SSL_accept failed\n"); + CyaSSL_free(ssl); + CloseSocket(clientfd); + continue; + } +#if defined(PEER_INFO) + showPeer(ssl); +#endif + + while ( (echoSz = CyaSSL_read(ssl, command, sizeof(command)-1)) > 0) { + + if (firstRead == 1) { + firstRead = 0; /* browser may send 1 byte 'G' to start */ + if (echoSz == 1 && command[0] == 'G') { + gotFirstG = 1; + continue; + } + } + else if (gotFirstG == 1 && strncmp(command, "ET /", 4) == 0) { + strncpy(command, "GET", 4); + /* fall through to normal GET */ + } + + if ( strncmp(command, "quit", 4) == 0) { + printf("client sent quit command: shutting down!\n"); + shutDown = 1; + break; + } + if ( strncmp(command, "break", 5) == 0) { + printf("client sent break command: closing session!\n"); + break; + } +#ifdef SESSION_STATS + if ( strncmp(command, "printstats", 10) == 0) { + PrintSessionStats(); + break; + } +#endif + if ( strncmp(command, "GET", 3) == 0) { + char type[] = "HTTP/1.0 200 ok\r\nContent-type:" + " text/html\r\n\r\n"; + char header[] = "\n
\n";
+                char body[]   = "greetings from CyaSSL\n";
+                char footer[] = "\r\n\r\n";
+            
+                strncpy(command, type, sizeof(type));
+                echoSz = sizeof(type) - 1;
+
+                strncpy(&command[echoSz], header, sizeof(header));
+                echoSz += (int)sizeof(header) - 1;
+                strncpy(&command[echoSz], body, sizeof(body));
+                echoSz += (int)sizeof(body) - 1;
+                strncpy(&command[echoSz], footer, sizeof(footer));
+                echoSz += (int)sizeof(footer);
+
+                if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                    err_sys("SSL_write failed");
+                break;
+            }
+            command[echoSz] = 0;
+
+            #ifdef ECHO_OUT
+                fputs(command, fout);
+            #endif
+
+            if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                err_sys("SSL_write failed");
+        }
+#ifndef CYASSL_DTLS
+        CyaSSL_shutdown(ssl);
+#endif
+        CyaSSL_free(ssl);
+        CloseSocket(clientfd);
+#ifdef CYASSL_DTLS
+        tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+        SignalReady(args, port);
+#endif
+    }
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+    CloseSocket(sockfd);
+    CyaSSL_CTX_free(ctx);
+
+#ifdef ECHO_OUT
+    if (outCreated)
+        fclose(fout);
+#endif
+
+    ((func_args*)args)->return_code = 0;
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("echoserver") || CurrentDir("build"))
+            ChangeDirBack(2);
+        echoserver_test(&args);
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+        
+#endif /* NO_MAIN_DRIVER */
+
+
+
+
diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c
new file mode 100644
index 000000000..8f7bd1fd5
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/main.c
@@ -0,0 +1,94 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+#include "rl_net.h" 
+#include 
+#include "cyassl_MDK_ARM.h"
+#include 
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+  int32_t retv;
+
+  retv = finit ("M0:");
+  if (retv == 0) {
+    retv = fmount ("M0:");
+    if (retv == 0) {
+      printf ("Drive M0 ready!\n");
+    }
+    else {
+      printf ("Drive M0 mount failed!\n");
+    }
+  }
+  else {
+    printf ("Drive M0 initialization failed!\n");
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+void tcp_poll (void const *arg)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        net_main ();
+        osDelay(1) ;
+    }
+}
+
+extern void shell_main(void * args) ;
+extern void init_time(void) ;
+
+osThreadDef (tcp_poll, osPriorityHigh, 1, 0) ;
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+int myoptind = 0;
+char* myoptarg = NULL;
+
+int main() 
+{
+    void *arg = NULL ;
+    init_time() ;
+    init_filesystem ();
+    net_initialize() ;
+    osThreadCreate (osThread (tcp_poll), NULL); 
+    osDelay(10000) ;  /* wait for DHCP */
+    #if defined(DEBUG_CYASSL)
+         printf("Turning ON Debug message\n") ;
+         CyaSSL_Debugging_ON() ;
+    #endif
+
+    shell_main(arg) ;   
+
+}
diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c
new file mode 100644
index 000000000..8e155f30a
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/server.c
@@ -0,0 +1,561 @@
+/* server.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if !defined(CYASSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER)
+    /* in case memory tracker wants stats */
+    #define CYASSL_TRACK_MEMORY
+#endif
+
+#if defined(CYASSL_MDK_ARM)
+    #include 
+    #include 
+    
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+    
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include 
+
+#ifdef CYASSL_MDK_SHELL
+extern void exit_command(void) ;
+#define exit(code) exit_command() 
+#endif
+
+#include 
+
+#include "examples/server/server.h"
+
+
+#ifdef CYASSL_CALLBACKS
+    int srvHandShakeCB(HandShakeInfo*);
+    int srvTimeoutCB(TimeoutInfo*);
+    Timeval srvTo;
+#endif
+
+static void NonBlockingSSL_Accept(SSL* ssl)
+{
+#ifndef CYASSL_CALLBACKS
+    int ret = SSL_accept(ssl);
+#else
+    int ret = CyaSSL_accept_ex(ssl, srvHandShakeCB, srvTimeoutCB, srvTo);
+#endif
+    int error = SSL_get_error(ssl, 0);
+    SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl);
+    int select_ret;
+
+    while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ ||
+                                  error == SSL_ERROR_WANT_WRITE)) {
+        int currTimeout = 1;
+
+        if (error == SSL_ERROR_WANT_READ)
+            printf("... server would read block\n");
+        else
+            printf("... server would write block\n");
+
+#ifdef CYASSL_DTLS
+        currTimeout = CyaSSL_dtls_get_current_timeout(ssl);
+#endif
+        select_ret = tcp_select(sockfd, currTimeout);
+
+        if ((select_ret == TEST_RECV_READY) ||
+                                        (select_ret == TEST_ERROR_READY)) {
+            #ifndef CYASSL_CALLBACKS
+                ret = SSL_accept(ssl);
+            #else
+                ret = CyaSSL_accept_ex(ssl,
+                                    srvHandShakeCB, srvTimeoutCB, srvTo);
+            #endif
+            error = SSL_get_error(ssl, 0);
+        }
+        else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#ifdef CYASSL_DTLS
+        else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) &&
+                                            CyaSSL_dtls_got_timeout(ssl) >= 0) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#endif
+        else {
+            error = SSL_FATAL_ERROR;
+        }
+    }
+    if (ret != SSL_SUCCESS)
+        err_sys("SSL_accept failed");
+}
+
+
+static void Usage(void)
+{
+    printf("server "    LIBCYASSL_VERSION_STRING
+           " NOTE: All files relative to CyaSSL home dir\n");
+    printf("-?          Help, print this usage\n");
+    printf("-p     Port to listen on, not 0, default %d\n", yasslPort);
+    printf("-v     SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n",
+                                 SERVER_DEFAULT_VERSION);
+    printf("-l     Cipher list\n");
+    printf("-c    Certificate file,           default %s\n", svrCert);
+    printf("-k    Key file,                   default %s\n", svrKey);
+    printf("-A    Certificate Authority file, default %s\n", cliCert);
+    printf("-d          Disable client cert check\n");
+    printf("-b          Bind to any interface instead of localhost only\n");
+    printf("-s          Use pre Shared keys\n");
+    printf("-t          Track CyaSSL memory use\n");
+    printf("-u          Use UDP DTLS,"
+           " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n");
+    printf("-f          Fewer packets/group messages\n");
+    printf("-N          Use Non-blocking sockets\n");
+    printf("-S     Use Host Name Indication\n");
+}
+
+THREAD_RETURN CYASSL_THREAD server_test(void* args)
+{
+    SOCKET_T sockfd   = 0;
+    SOCKET_T clientfd = 0;
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+    char   msg[] = "I hear you fa shizzle!";
+    char   input[80];
+    int    idx;
+    int    ch;
+    int    version = SERVER_DEFAULT_VERSION;
+    int    doCliCertCheck = 1;
+    int    useAnyAddr = 0;
+    int    port = yasslPort;
+    int    usePsk = 0;
+    int    doDTLS = 0;
+    int    useNtruKey   = 0;
+    int    nonBlocking  = 0;
+    int    trackMemory  = 0;
+    int    fewerPackets = 0;
+    char*  cipherList = NULL;
+    char*  verifyCert = (char*)cliCert;
+    char*  ourCert    = (char*)svrCert;
+    char*  ourKey     = (char*)svrKey;
+    int    argc = ((func_args*)args)->argc;
+    char** argv = ((func_args*)args)->argv;
+
+#ifdef HAVE_SNI
+    char*  sniHostName = NULL;
+#endif
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef NO_RSA
+    verifyCert = (char*)cliEccCert;
+    ourCert    = (char*)eccCert;
+    ourKey     = (char*)eccKey;
+#endif
+    (void)trackMemory;
+
+    while ((ch = mygetopt(argc, argv, "?dbstnNufp:v:l:A:c:k:S:")) != -1) {
+        switch (ch) {
+            case '?' :
+                Usage();
+                exit(EXIT_SUCCESS);
+
+            case 'd' :
+                doCliCertCheck = 0;
+                break;
+
+            case 'b' :
+                useAnyAddr = 1;
+                break;
+
+            case 's' :
+                usePsk = 1;
+                break;
+
+            case 't' :
+            #ifdef USE_CYASSL_MEMORY
+                trackMemory = 1;
+            #endif
+                break;
+
+            case 'n' :
+                useNtruKey = 1;
+                break;
+
+            case 'u' :
+                doDTLS  = 1;
+                break;
+
+            case 'f' :
+                fewerPackets = 1;
+                break;
+
+            case 'p' :
+                port = atoi(myoptarg);
+                #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API)
+                    if (port == 0)
+                        err_sys("port number cannot be 0");
+                #endif
+                break;
+
+            case 'v' :
+                version = atoi(myoptarg);
+                if (version < 0 || version > 3) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'l' :
+                cipherList = myoptarg;
+                break;
+
+            case 'A' :
+                verifyCert = myoptarg;
+                break;
+
+            case 'c' :
+                ourCert = myoptarg;
+                break;
+
+            case 'k' :
+                ourKey = myoptarg;
+                break;
+
+            case 'N':
+                nonBlocking = 1;
+                break;
+
+            case 'S' :
+                #ifdef HAVE_SNI
+                    sniHostName = myoptarg;
+                #endif
+                break;
+
+            default:
+                Usage();
+                exit(MY_EX_USAGE);
+        }
+    }
+
+    myoptind = 0;      /* reset for test cases */
+
+    /* sort out DTLS versus TLS versions */
+    if (version == CLIENT_INVALID_VERSION) {
+        if (doDTLS)
+            version = CLIENT_DTLS_DEFAULT_VERSION;
+        else
+            version = CLIENT_DEFAULT_VERSION;
+    }
+    else {
+        if (doDTLS) {
+            if (version == 3)
+                version = -2;
+            else
+                version = -1;
+        }
+    }
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        InitMemoryTracker(); 
+#endif
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case 0:
+            method = SSLv3_server_method();
+            break;
+
+    #ifndef NO_TLS
+        case 1:
+            method = TLSv1_server_method();
+            break;
+
+
+        case 2:
+            method = TLSv1_1_server_method();
+            break;
+
+        #endif
+#endif
+
+#ifndef NO_TLS
+        case 3:
+            method = TLSv1_2_server_method();
+            break;
+#endif
+                
+#ifdef CYASSL_DTLS
+        case -1:
+            method = DTLSv1_server_method();
+            break;
+
+        case -2:
+            method = DTLSv1_2_server_method();
+            break;
+#endif
+
+        default:
+            err_sys("Bad SSL version");
+    }
+
+    if (method == NULL)
+        err_sys("unable to get method");
+
+    ctx = SSL_CTX_new(method);
+    if (ctx == NULL)
+        err_sys("unable to get ctx");
+
+    if (cipherList)
+        if (SSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS)
+            err_sys("server can't set cipher list 1");
+
+#ifdef CYASSL_LEANPSK
+    usePsk = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    usePsk = 1;
+#endif
+
+    if (fewerPackets)
+        CyaSSL_CTX_set_group_messages(ctx);
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!usePsk) {
+        if (SSL_CTX_use_certificate_file(ctx, ourCert, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                    " CyaSSL home dir");
+    }
+#endif
+
+#ifdef HAVE_NTRU
+    if (useNtruKey) {
+        if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ourKey)
+                                               != SSL_SUCCESS)
+            err_sys("can't load ntru key file, "
+                    "Please run from CyaSSL home dir");
+    }
+#endif
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!useNtruKey && !usePsk) {
+        if (SSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                " CyaSSL home dir");
+    }
+#endif
+
+    if (usePsk) {
+#ifndef NO_PSK
+        SSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb);
+        SSL_CTX_use_psk_identity_hint(ctx, "cyassl server");
+        if (cipherList == NULL) {
+            const char *defaultCipherList;
+            #ifdef HAVE_NULL_CIPHER
+                defaultCipherList = "PSK-NULL-SHA256";
+            #else
+                defaultCipherList = "PSK-AES128-CBC-SHA256";
+            #endif
+            if (SSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS)
+                err_sys("server can't set cipher list 2");
+        }
+#endif
+    }
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    /* if not using PSK, verify peer with certs */
+    if (doCliCertCheck && usePsk == 0) {
+        SSL_CTX_set_verify(ctx, SSL_VERIFY_PEER |
+                                SSL_VERIFY_FAIL_IF_NO_PEER_CERT,0);
+        if (SSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS)
+            err_sys("can't load ca file, Please run from CyaSSL home dir");
+    }
+#endif
+
+#ifdef OPENSSL_EXTRA
+    SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    if (cipherList == NULL) {
+        if (SSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS)
+            err_sys("server can't set cipher list 3");
+    }
+#endif
+
+#ifdef HAVE_SNI
+    if (sniHostName) {
+        if (CyaSSL_CTX_UseSNI(ctx, CYASSL_SNI_HOST_NAME, sniHostName,
+                                                          XSTRLEN(sniHostName)))
+            err_sys("UseSNI failed");
+        else
+            CyaSSL_CTX_SNI_SetOptions(ctx, CYASSL_SNI_HOST_NAME,
+                                                  CYASSL_SNI_ABORT_ON_MISMATCH);
+    }
+#endif
+
+    ssl = SSL_new(ctx);
+    if (ssl == NULL)
+        err_sys("unable to get SSL");
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+#ifdef HAVE_CRL
+    CyaSSL_EnableCRL(ssl, 0);
+    CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, CYASSL_CRL_MONITOR |
+                                                     CYASSL_CRL_START_MON);
+    CyaSSL_SetCRL_Cb(ssl, CRL_CallBack);
+#endif
+        osDelay(5000) ;
+    tcp_accept(&sockfd, &clientfd, (func_args*)args, port, useAnyAddr, doDTLS);
+    if (!doDTLS) 
+        CloseSocket(sockfd);
+
+    SSL_set_fd(ssl, clientfd);
+    if (usePsk == 0) {
+        #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA)
+            CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+        #elif !defined(NO_CERTS)
+            SetDH(ssl);  /* repick suites with DHE, higher priority than PSK */
+        #endif
+    }
+        osDelay(5000) ;
+#ifndef CYASSL_CALLBACKS
+    if (nonBlocking) {
+        CyaSSL_set_using_nonblock(ssl, 1);
+        tcp_set_nonblocking(&clientfd);
+        NonBlockingSSL_Accept(ssl);
+    } else if (SSL_accept(ssl) != SSL_SUCCESS) {
+        int err = SSL_get_error(ssl, 0);
+        char buffer[80];
+        printf("error = %d, %s\n", err, ERR_error_string(err, buffer));
+        err_sys("SSL_accept failed");
+    }
+#else
+    NonBlockingSSL_Accept(ssl);
+#endif
+    showPeer(ssl);
+        osDelay(5000) ;
+    idx = SSL_read(ssl, input, sizeof(input)-1);
+    if (idx > 0) {
+        input[idx] = 0;
+        printf("Client message: %s\n", input);
+
+    }
+    else if (idx < 0) {
+        int readErr = SSL_get_error(ssl, 0);
+        if (readErr != SSL_ERROR_WANT_READ)
+            err_sys("SSL_read failed");
+    }
+
+    if (SSL_write(ssl, msg, sizeof(msg)) != sizeof(msg))
+        err_sys("SSL_write failed");
+        
+    SSL_shutdown(ssl);
+    SSL_free(ssl);
+    SSL_CTX_free(ctx);
+    
+    CloseSocket(clientfd);
+    ((func_args*)args)->return_code = 0;
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        ShowMemoryTracker();
+#endif /* USE_CYASSL_MEMORY */
+
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("server") || CurrentDir("build"))
+            ChangeDirBack(2);
+   
+#ifdef HAVE_STACK_SIZE
+        StackSizeCheck(&args, server_test);
+#else 
+        server_test(&args);
+#endif
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#endif /* NO_MAIN_DRIVER */
+
+
+#ifdef CYASSL_CALLBACKS
+
+    int srvHandShakeCB(HandShakeInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+
+    int srvTimeoutCB(TimeoutInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+#endif
+
diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c
new file mode 100644
index 000000000..c79f276ff
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/shell.c
@@ -0,0 +1,661 @@
+/*shell.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+ /*** tiny Shell for CyaSSL apps ***/
+ 
+ #ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include "cyassl/internal.h"
+#undef RNG
+#include 
+
+#if defined(CYASSL_MDK_ARM)
+    #include 
+    #include 
+    #include 
+        #if defined(CYASSL_MDK5)
+            #include "cmsis_os.h"
+        #include "rl_fs.h" 
+    #else
+            #include 
+        #endif
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#ifdef CYASSL_KEIL_NET
+#include "cyassl/test.h"
+#else
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+#endif
+
+#ifdef NO_ECHOCLIENT
+#define echoclient_test command_not_found
+#endif
+#ifdef NO_ECHOSERVER
+#define echoserver_test command_not_found
+#endif
+#ifdef NO_SIMPLE_CLIENT
+#define client_test command_not_found
+#endif
+#ifdef NO_SIMPLE_SERVER
+#define server_test command_not_found
+#endif
+#ifdef NO_CRYPT_BENCHMARK
+#define benchmark_test command_not_found
+#endif
+#ifdef NO_CRYPT_TEST
+#define ctaocrypt_test command_not_found
+#endif
+
+#ifndef CYASSL_KEIL_NET
+#define ipaddr_comm command_not_found
+#endif
+
+#if !defined(HAVE_KEIL_RTX)
+#define stack_comm command_not_found
+#endif
+
+
+#if !defined(DEBUG_CYASSL)
+#define dbg_comm command_not_found
+#endif
+
+
+void command_not_found(void *argv) {
+        printf("Command not found\n") ;
+}
+
+extern void echoclient_test(void *args) ;
+extern void echoserver_test(void *args) ;
+extern void benchmark_test(void *args) ;
+extern void ctaocrypt_test(void *args) ;
+extern void client_test(void *args) ;
+extern void server_test(void *args) ;
+extern void kill_task(void *args) ;
+extern void time_main(void *args) ;
+extern void ipaddr_comm(void *args) ;
+extern void stack_comm(void *args) ;
+extern void for_command(void *args) ;
+extern void dbg_comm(void *arg) ;
+extern void help_comm(void *arg) ;
+
+#if !defined(NO_CRYPT_TEST)
+
+#ifndef NO_MD5
+extern void md5_test(void *arg) ;
+#endif
+#ifdef CYASSL_MD2
+extern void md2_test(void *arg) ;
+#endif
+#ifndef NO_MD4
+extern void md4_test(void *arg) ;
+#endif
+
+extern void sha_test(void *arg) ;
+
+#ifndef NO_SHA256
+extern void sha256_test(void *arg) ;
+#endif
+#ifdef CYASSL_SHA384
+extern void sha384_test(void *arg) ;
+#endif
+
+#ifdef CYASSL_SHA512
+extern void sha512_test(void *arg) ;
+#endif
+
+#ifdef CYASSL_RIPEMD
+extern void ripemd_test(void *arg) ;
+#endif
+#ifndef NO_HMAC
+    #ifndef NO_MD5
+extern void hmac_md5_test(void *arg) ;
+    #endif
+extern void hmac_sha_test(void *arg) ;
+
+    #ifndef NO_SHA256
+extern void hmac_sha256_test(void *arg) ;
+    #endif
+
+    #ifdef CYASSL_SHA384
+extern void hmac_sha384_test(void *arg) ;
+    #endif
+#endif
+#ifndef NO_RC4
+extern void arc4_test(void *arg) ;
+#endif
+
+#ifndef NO_HC128
+extern void hc128_test(void *arg) ;
+#endif
+
+#ifndef NO_RABBIT
+extern void rabbit_test(void *arg) ;
+#endif
+
+#ifndef NO_DES3
+extern void des_test(void *arg) ;
+extern void des3_test(void *arg) ;
+#endif
+
+#ifndef NO_AES
+extern void aes_test(void *arg) ;
+#ifdef HAVE_AESGCM
+extern void aesgcm_test(void *arg) ;
+#endif
+
+#ifdef HAVE_AESCCM
+extern void aesccm_test(void *arg) ;
+#endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+extern void camellia_test(void *arg) ;
+#endif
+extern void random_test(void *arg) ;
+
+#ifndef NO_RSA
+extern void rsa_test(void *arg) ;
+#endif
+
+#ifndef NO_DH
+extern void dh_test(void *arg) ;
+#endif
+
+#ifndef NO_DSA
+extern void dsa_test(void *arg) ;
+#endif
+    
+#ifndef NO_PWDBASED
+extern void pwdbased_test(void *arg) ;
+#endif
+
+#ifdef OPENSSL_EXTRA
+extern void openssl_test(void *arg) ;
+#endif
+
+#ifdef HAVE_ECC
+extern void ecc_test(void *arg) ;
+#endif
+
+#endif /* NO_CRYPT_TEST */
+
+static struct {
+  const char *command ;
+    void (*func)(void *args) ;
+}   commandTable[] = {
+    "echoclient", echoclient_test,
+    "echoserver", echoserver_test,
+    "benchmark", benchmark_test,
+    "test", ctaocrypt_test,
+    "client", client_test,
+    "server", server_test,
+    "time", time_main,          /* get/set RTC:  [-d mm/dd/yyyy] [-t hh:mm:ss]*/
+    "ipaddr", ipaddr_comm,      /* TBD */
+    "stack", stack_comm,        /* On/Off check stack size */
+    "for", for_command,         /* iterate next command X times */
+    "debug", dbg_comm,          /* On/Off debug message  */
+    "help", help_comm,          /* Breif description about the commands */
+
+    /** short name **/
+    "ec", echoclient_test,
+    "es", echoserver_test,
+    "bm", benchmark_test,
+    "te", ctaocrypt_test,
+    "cl", client_test,
+    "sv", server_test,
+    "ip", ipaddr_comm,
+    "st", stack_comm,
+  "dbg", dbg_comm,
+    "?",    help_comm,
+
+/*** test suites ****/
+#if !defined(NO_CRYPT_TEST)
+#ifndef NO_MD5
+  "md5",  md5_test,
+#endif
+#ifdef CYASSL_MD2
+  "md2",  md2_test,
+#endif
+#ifndef NO_MD4
+  "md4",  md4_test,
+#endif
+  "sha",  sha_test,
+#ifndef NO_SHA256
+  "sha256",  sha256_test,
+#endif
+#ifdef CYASSL_SHA384
+  "sha384",  sha384_test,
+#endif
+#ifdef CYASSL_SHA512
+  "sha512",  sha512_test,
+#endif
+#ifdef CYASSL_RIPEMD
+  "ripemd",  ripemd_test,
+#endif
+#ifndef NO_HMAC
+  #ifndef NO_MD5
+  "hmac_md5",  hmac_md5_test,
+    #endif
+  "hmac_sha",  hmac_sha_test,
+    #ifndef NO_SHA256
+  "hmac_sha256",  hmac_sha256_test,
+    #endif
+    #ifdef CYASSL_SHA384
+  "hmac_sha384",  hmac_sha384_test,
+  #endif
+#endif
+#ifndef NO_RC4
+    "arc4",  arc4_test,
+#endif
+#ifndef NO_HC128
+  "hc128",  hc128_test,
+#endif
+#ifndef NO_RABBIT
+  "rabbit",  rabbit_test,
+#endif
+#ifndef NO_DES3
+  "des",  des_test,
+  "des3",  des3_test,
+#endif  
+#ifndef NO_AES  
+  "aes",  aes_test,
+    #ifdef HAVE_AESGCM
+  "aesgcm",  aesgcm_test,
+    #endif
+    #ifdef HAVE_AESCCM
+  "aesccm",  aesccm_test,
+    #endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+  "camellia",  camellia_test,
+#endif
+  "random",  random_test,
+#ifndef NO_RSA
+  "rsa",  rsa_test,
+#endif
+#ifndef NO_DH
+  "dh",  dh_test,
+#endif
+#ifndef NO_DSA
+    "dsa",  dsa_test,
+#endif 
+#ifndef NO_PWDBASED
+  "pwdbased",  pwdbased_test,
+#endif  
+#ifdef OPENSSL_EXTRA
+  "openssl",  openssl_test,
+#endif
+#ifdef HAVE_ECC
+  "ecc",  ecc_test,
+#endif
+
+#endif /* NO_CRYPT_TEST */
+
+    "",  NULL
+} ;
+
+enum jobtype { FORGROUND, BACKGROUND }  ;
+
+#define IF_DELIMITER(ch) ((ch) == ' ' || (ch) == '\n')
+
+static int BackGround = 0 ; /* 1: background job is running */
+
+/*******  Get Command Line *****************************/
+static int getline(char * line, int sz, func_args *args, int*bf_flg) 
+{
+    char * ret ;
+    int i ;
+    
+    #define MAXARGS 10
+    #define MAXARGLEN 30
+    static char *argv[MAXARGS] ;
+    args->argv = argv ;
+    
+    putchar('>') ;
+    fflush(stdout) ;
+    ret = fgets(line, sz, stdin) ;
+    
+    #define SHELL_ERROR_FGETS -102
+    if(ret != line) return(SHELL_ERROR_FGETS) ;
+    
+    if(line[strlen(line)-2] == '&') {
+        (*bf_flg) = BACKGROUND ;
+        line[strlen(line)-2] = '\n' ;
+    } else {
+        (*bf_flg) = FORGROUND ;
+    }
+    args->argc = 0 ;
+    for(i=0; iargv[args->argc] = &(line[i]) ;
+        while(!IF_DELIMITER(line[i])) i++ ;
+        args->argc++ ;
+        if(line[i] == '\n') {
+            line[i]  = '\0' ;
+            break ;
+        } else {
+            line[i]  = '\0' ;
+        }
+    }
+    return i ;
+}
+
+
+/************* Embedded Shell Commands **********************************/
+#define IP_SIZE 16
+
+#ifdef CYASSL_KEIL_NET
+static void ipaddr_comm(void *args) 
+{
+    if(((func_args *)args)->argc == 1) {
+            printf("IP addr: %s, port %d\n", yasslIP, yasslPort) ;
+    } else {
+        if(BackGround != 0) {
+        printf("Cannot change IP addr while background server is running\n") ;
+        } else if(((func_args *)args)->argc == 3 && 
+                  ((func_args *)args)->argv[1][0] == '-'&& 
+                  ((func_args *)args)->argv[1][1] == 'a' ) {
+/*          strcpy(yasslIP, ((func_args *)args)->argv[2]) ; */
+        } else if(((func_args *)args)->argc == 3 && 
+                  ((func_args *)args)->argv[1][0] == '-' && 
+                  ((func_args *)args)->argv[1][1] == 'p' ) {
+/*          yasslPort = atoi(((func_args *)args)->argv[2]) ; */
+        } else printf("Invalid argument\n") ; 
+    }
+}
+
+#endif
+
+
+
+#if defined(HAVE_KEIL_RTX)
+static int stack_ck = 0 ;
+
+void stack_comm(void *args) 
+{
+    if(stack_ck) {
+        printf("Stack Check: Off\n") ;
+        stack_ck = 0 ;
+    } else {
+        printf("Stack Check: On\n") ;
+        stack_ck = 1 ;
+    }
+}
+    
+#define FILL_PATTERN 0xa596695a
+void stack_fill(char * stack, int size)
+{
+    int i ;
+
+    if(stack_ck == 0)return ;
+    for(i=1; iargc == 1) {
+        printf("For %d times\n", for_iteration) ;
+    } else if( args == NULL || ((func_args *)args)->argc == 2) {
+        for_iteration = atoi(((func_args *)args)->argv[1]) ;
+    } else printf("Invalid argument\n") ;
+}
+
+
+#if defined(DEBUG_CYASSL)
+
+static int CyasslDebug = 1 ;
+
+static void dbg_comm(void *args) 
+{
+    if(CyasslDebug == 1) {
+        CyasslDebug = 0 ;
+        printf("Turning OFF Debug message\n") ;
+        CyaSSL_Debugging_OFF() ;
+    } else {
+        CyasslDebug = 1 ;
+        printf("Turning ON Debug message\n") ;
+        CyaSSL_Debugging_ON() ;
+    }
+}
+#endif
+
+static void help_comm(void *args) 
+{
+    static char *commands[] = {
+        "time [-d mm/dd/yyyy][-t hh:mm:ss]  : set/get time, for cert validation",
+        "test", 
+        "benchmark",
+        "echoserver&            : simple echo server in background mode",
+        "echoclient             : simple echo client followed by any input string, or \"quit\", \"break\"",
+        "server&                : simple server in background mode",
+        "client                 : simple client",
+        "client -g -v [0123] -h xxx.xxx.xxx.xxx -p 443  : usage example",
+        "server/client -h        :  help for server/client command",
+        "help",
+        ""  
+    } ;
+
+    int i ;
+    printf("Commands:\n") ;
+    for(i=0; commands[i][0] ; i++)
+        printf("    %s\n", commands[i]) ;
+
+}
+
+
+
+#define BG_JOB_STACK_SIZE 8000
+#if (!defined(NO_SIMPLE_SERVER) && !defined(NO_ECHOSERVER)) && \
+                                                   defined(HAVE_KEIL_RTX)
+#if !defined(CYASSL_CMSIS_RTOS)
+static char bg_job_stack[BG_JOB_STACK_SIZE] ;
+#endif
+
+#endif
+
+#define COMMAND_STACK_SIZE 10000
+#if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+static char command_stack[COMMAND_STACK_SIZE] ;
+#endif
+
+
+#ifdef  HAVE_KEIL_RTX
+static   CyaSSL_Mutex command_mutex ;
+#endif
+
+void exit_command(void) {
+	  printf("Command Aborted\n") ;
+    #ifdef CYASSL_CMSIS_RTOS
+        osThreadTerminate(osThreadGetId()) ;
+    #else
+        os_tsk_delete_self() ;
+    #endif
+}
+
+
+/***********    Invoke Forground Command  *********************/
+static void command_invoke(void const *args) 
+{
+    void (*func)(void const * ) ;
+    int i,iteration ;
+    
+    func = (void(*)(void const *))((func_args *)args)->argv[0] ; 
+    #ifdef  HAVE_KEIL_RTX
+    LockMutex((CyaSSL_Mutex *)&command_mutex) ;
+    #endif
+    iteration = for_iteration ;
+    for(i=0; i< iteration; i++) {
+        if(iteration > 1) printf("--- Start for %d ---->\n", i) ;
+        #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+        stack_fill(command_stack, COMMAND_STACK_SIZE) ;
+        #endif
+                
+        func(args) ;        /* invoke command */
+                
+        #if defined(HAVE_KEIL_RTX)&& !defined(CYASSL_CMSIS_RTOS)
+        stack_check(command_stack, COMMAND_STACK_SIZE) ;
+        #endif
+    }
+
+    if(iteration > 1) 
+    for_iteration = 1 ;
+    osDelay(20000) ;
+    #ifdef HAVE_KEIL_RTX
+        UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+        #ifdef CYASSL_CMSIS_RTOS
+            osThreadTerminate(osThreadGetId()) ;
+        #else
+            os_tsk_delete_self() ;
+        #endif
+    #endif
+}
+
+#if defined(HAVE_KEIL_RTX)
+/*******  Invoke Background Job   *******************************/
+static void bg_job_invoke(void const *args) 
+{
+    void (*func)(void const * ) ;
+    BackGround = 1 ; 
+    #if defined(HAVE_KEIL_RTX)&& !defined(CYASSL_CMSIS_RTOS)
+    stack_fill(bg_job_stack, BG_JOB_STACK_SIZE) ;
+    #endif
+
+    func = (void(*)(void const *))((func_args *)args)->argv[0] ; 
+    func(args) ;        /* invoke command */
+    #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+    stack_check(bg_job_stack, BG_JOB_STACK_SIZE) ;
+    #endif
+    
+    osDelay(20000) ;
+    BackGround = 0 ;
+
+    #ifdef CYASSL_CMSIS_RTOS
+        osThreadTerminate(osThreadGetId()) ;
+    #else   
+        os_tsk_delete_self() ; ;
+    #endif
+}
+#endif
+
+#define LINESIZE 100
+static char line[LINESIZE] ;
+
+#if defined(CYASSL_CMSIS_RTOS)
+    osThreadDef (command_invoke, osPriorityAboveNormal , 1, COMMAND_STACK_SIZE) ;
+    osThreadDef (bg_job_invoke, osPriorityNormal , 1 , BG_JOB_STACK_SIZE) ;
+#endif
+/********* SHEULL MAIN LOOP ***********************************/
+void shell_main(void *arg) {
+    int i ; 
+    func_args args ;
+    int bf_flg ;
+   
+    i = BackGround ; 
+        /* Dummy for avoiding warning: BackGround is defined but not used. */
+    
+ #if defined(HAVE_KEIL_RTX)
+    InitMutex(&command_mutex) ;
+#endif
+    time_main(NULL) ;
+    help_comm(NULL) ;
+    
+    printf("Starting Shell\n") ;
+    while(1) {
+        if(getline(line,  LINESIZE, &args, &bf_flg) > 0) {
+        for(i=0; commandTable[i].func != NULL; i++) {
+            if(strcmp(commandTable[i].command, args.argv[0]) == 0) {
+            args.argv[0] = (char *) commandTable[i].func ;
+                if(bf_flg == FORGROUND) {
+                    #if defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+                        UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                        os_tsk_create_user_ex( (void(*)(void *))&command_invoke, 7,
+                             command_stack, COMMAND_STACK_SIZE, &args) ;
+                                      #else
+                                            #if defined(CYASSL_CMSIS_RTOS)
+                                UnLockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                          osThreadCreate (osThread (command_invoke) , &args);   
+                          #else
+                          command_invoke(&args) ;
+                                            #endif
+                    #endif
+                    #ifdef  HAVE_KEIL_RTX
+                    LockMutex((CyaSSL_Mutex *)&command_mutex) ;
+                    #endif
+                } else {
+                    #if (!defined(NO_SIMPLE_SERVER) && \
+                         !defined(NO_ECHOSERVER)) && \
+                         defined(HAVE_KEIL_RTX)
+                    if(BackGround != 0) {
+                        printf("Multiple background servers not supported.\n") ;
+                    } else {
+                        printf("\"%s\" is running with the background mode.\n", 
+                                                     commandTable[i].command) ;
+                        #if  defined(HAVE_KEIL_RTX) && !defined(CYASSL_CMSIS_RTOS)
+                             os_tsk_create_user_ex( (void(*)(void *))&bg_job_invoke, 
+                                   6, bg_job_stack, BG_JOB_STACK_SIZE, &args) ;
+                        #else
+                                osThreadCreate (osThread (bg_job_invoke),  &args); 
+                                osDelay (500) ;
+                        #endif
+                    }
+                    #else
+                    printf("Invalid Command: no background job\n") ;
+                    #endif
+                }
+                break ;
+            }
+        }
+        if(commandTable[i].func == NULL)
+            printf("Command not found\n") ;
+        }
+    }
+}
+
diff --git a/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c b/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c
new file mode 100644
index 000000000..6165cee31
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/CyaSSL-Full/test.c
@@ -0,0 +1,3391 @@
+/* test.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#ifndef NO_CRYPT_TEST
+
+#ifdef CYASSL_TEST_CERT
+    #include 
+#else
+    #include 
+#endif
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#ifdef HAVE_ECC
+    #include 
+#endif    
+#ifdef HAVE_BLAKE2
+    #include 
+#endif    
+#ifdef HAVE_LIBZ
+    #include 
+#endif
+
+#ifdef _MSC_VER
+    /* 4996 warning to use MS extensions e.g., strcpy_s instead of strncpy */
+    #pragma warning(disable: 4996)
+#endif
+
+#ifdef OPENSSL_EXTRA
+    #include 
+    #include 
+    #include 
+    #include 
+#endif
+
+#if defined(CYASSL_MDK_ARM)
+        #include 
+        #include 
+    extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ;
+    #define fopen CyaSSL_fopen
+#endif
+
+#if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048)
+    /* include test cert and key buffers for use with NO_FILESYSTEM */
+    #if defined(CYASSL_MDK_ARM) && !defined(SINGLE_THREADED)
+        #include "cert_data.h" 
+                        /* use certs_test.c for initial data, so other 
+                                               commands can share the data. */
+    #else
+        #include 
+    #endif
+#endif
+
+#ifdef HAVE_NTRU
+    #include "crypto_ntru.h"
+#endif
+#ifdef HAVE_CAVIUM
+    #include "cavium_sysdep.h"
+    #include "cavium_common.h"
+    #include "cavium_ioctl.h"
+#endif
+
+#ifdef FREESCALE_MQX
+    #include 
+    #include 
+#else
+    #include 
+#endif
+
+
+#ifdef THREADX
+    /* since just testing, use THREADX log printf instead */
+    int dc_log_printf(char*, ...);
+        #undef printf
+        #define printf dc_log_printf
+#endif
+
+#include "ctaocrypt/test/test.h"
+
+
+typedef struct testVector {
+    const char*  input;
+    const char*  output; 
+    size_t inLen;
+    size_t outLen;
+} testVector;
+
+int  md2_test(void);
+int  md5_test(void);
+int  md4_test(void);
+int  sha_test(void);
+int  sha256_test(void);
+int  sha512_test(void);
+int  sha384_test(void);
+int  hmac_md5_test(void);
+int  hmac_sha_test(void);
+int  hmac_sha256_test(void);
+int  hmac_sha384_test(void);
+int  hmac_sha512_test(void);
+int  arc4_test(void);
+int  hc128_test(void);
+int  rabbit_test(void);
+int  des_test(void);
+int  des3_test(void);
+int  aes_test(void);
+int  aesgcm_test(void);
+int  aesccm_test(void);
+int  camellia_test(void);
+int  rsa_test(void);
+int  dh_test(void);
+int  dsa_test(void);
+int  random_test(void);
+int  pwdbased_test(void);
+int  ripemd_test(void);
+int  openssl_test(void);   /* test mini api */
+int pbkdf1_test(void);
+int pkcs12_test(void);
+int pbkdf2_test(void);
+#ifdef HAVE_ECC
+    int  ecc_test(void);
+#endif
+#ifdef HAVE_BLAKE2
+    int  blake2b_test(void);
+#endif
+#ifdef HAVE_LIBZ
+    int compress_test(void);
+#endif
+
+
+
+static void err_sys(const char* msg, int es)
+{
+    printf("%s error = %d\n", msg, es);
+    #if !defined(THREADX) && !defined(CYASSL_MDK_ARM)
+    if (msg)
+        exit(es);
+    #endif
+    return;
+}
+
+/* func_args from test.h, so don't have to pull in other junk */
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+
+
+
+void ctaocrypt_test(void* args)
+{
+    int ret = 0;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#if !defined(NO_BIG_INT)
+    if (CheckCtcSettings() != 1)
+        err_sys("Build vs runtime math mismatch\n", -1234);
+
+#ifdef USE_FAST_MATH
+    if (CheckFastMathSettings() != 1)
+        err_sys("Build vs runtime fastmath FP_MAX_BITS mismatch\n", -1235);
+#endif /* USE_FAST_MATH */
+#endif /* !NO_BIG_INT */
+
+
+#ifndef NO_MD5
+    if ( (ret = md5_test()) != 0) 
+        err_sys("MD5      test failed!\n", ret);
+    else
+        printf( "MD5      test passed!\n");
+#endif
+
+#ifdef CYASSL_MD2
+    if ( (ret = md2_test()) != 0) 
+        err_sys("MD2      test failed!\n", ret);
+    else
+        printf( "MD2      test passed!\n");
+#endif
+
+#ifndef NO_MD4
+    if ( (ret = md4_test()) != 0) 
+        err_sys("MD4      test failed!\n", ret);
+    else
+        printf( "MD4      test passed!\n");
+#endif
+
+#ifndef NO_SHA
+    if ( (ret = sha_test()) != 0) 
+        err_sys("SHA      test failed!\n", ret);
+    else
+        printf( "SHA      test passed!\n");
+#endif
+
+#ifndef NO_SHA256
+    if ( (ret = sha256_test()) != 0) 
+        err_sys("SHA-256  test failed!\n", ret);
+    else
+        printf( "SHA-256  test passed!\n");
+#endif
+
+#ifdef CYASSL_SHA384
+    if ( (ret = sha384_test()) != 0) 
+        err_sys("SHA-384  test failed!\n", ret);
+    else
+        printf( "SHA-384  test passed!\n");
+#endif
+
+#ifdef CYASSL_SHA512
+    if ( (ret = sha512_test()) != 0) 
+        err_sys("SHA-512  test failed!\n", ret);
+    else
+        printf( "SHA-512  test passed!\n");
+#endif
+
+#ifdef CYASSL_RIPEMD
+    if ( (ret = ripemd_test()) != 0) 
+        err_sys("RIPEMD   test failed!\n", ret);
+    else
+        printf( "RIPEMD   test passed!\n");
+#endif
+
+#ifdef HAVE_BLAKE2 
+    if ( (ret = blake2b_test()) != 0) 
+        err_sys("BLAKE2b  test failed!\n", ret);
+    else
+        printf( "BLAKE2b  test passed!\n");
+#endif
+
+#ifndef NO_HMAC
+    #ifndef NO_MD5
+        if ( (ret = hmac_md5_test()) != 0) 
+            err_sys("HMAC-MD5 test failed!\n", ret);
+        else
+            printf( "HMAC-MD5 test passed!\n");
+    #endif
+
+    #ifndef NO_SHA
+    if ( (ret = hmac_sha_test()) != 0) 
+        err_sys("HMAC-SHA test failed!\n", ret);
+    else
+        printf( "HMAC-SHA test passed!\n");
+    #endif
+
+    #ifndef NO_SHA256
+        if ( (ret = hmac_sha256_test()) != 0) 
+            err_sys("HMAC-SHA256 test failed!\n", ret);
+        else
+            printf( "HMAC-SHA256 test passed!\n");
+    #endif
+
+    #ifdef CYASSL_SHA384
+        if ( (ret = hmac_sha384_test()) != 0) 
+            err_sys("HMAC-SHA384 test failed!\n", ret);
+        else
+            printf( "HMAC-SHA384 test passed!\n");
+    #endif
+
+    #ifdef CYASSL_SHA512
+        if ( (ret = hmac_sha512_test()) != 0) 
+            err_sys("HMAC-SHA512 test failed!\n", ret);
+        else
+            printf( "HMAC-SHA512 test passed!\n");
+    #endif
+
+#endif
+
+#ifndef NO_RC4
+    if ( (ret = arc4_test()) != 0)
+        err_sys("ARC4     test failed!\n", ret);
+    else
+        printf( "ARC4     test passed!\n");
+#endif
+
+#ifndef HAVE_HC128
+    if ( (ret = hc128_test()) != 0)
+        err_sys("HC-128   test failed!\n", ret);
+    else
+        printf( "HC-128   test passed!\n");
+#endif
+
+#ifndef NO_RABBIT
+    if ( (ret = rabbit_test()) != 0)
+        err_sys("Rabbit   test failed!\n", ret);
+    else
+        printf( "Rabbit   test passed!\n");
+#endif
+
+#ifndef NO_DES3
+    if ( (ret = des_test()) != 0)
+        err_sys("DES      test failed!\n", ret);
+    else
+        printf( "DES      test passed!\n");
+#endif
+
+#ifndef NO_DES3
+    if ( (ret = des3_test()) != 0)
+        err_sys("DES3     test failed!\n", ret);
+    else
+        printf( "DES3     test passed!\n");
+#endif
+
+#ifndef NO_AES
+    if ( (ret = aes_test()) != 0)
+        err_sys("AES      test failed!\n", ret);
+    else
+        printf( "AES      test passed!\n");
+
+#ifdef HAVE_AESGCM
+    if ( (ret = aesgcm_test()) != 0)
+        err_sys("AES-GCM  test failed!\n", ret);
+    else
+        printf( "AES-GCM  test passed!\n");
+#endif
+
+#ifdef HAVE_AESCCM
+    if ( (ret = aesccm_test()) != 0)
+        err_sys("AES-CCM  test failed!\n", ret);
+    else
+        printf( "AES-CCM  test passed!\n");
+#endif
+#endif
+
+#ifdef HAVE_CAMELLIA
+    if ( (ret = camellia_test()) != 0)
+        err_sys("CAMELLIA test failed!\n", ret);
+    else
+        printf( "CAMELLIA test passed!\n");
+#endif
+
+    if ( (ret = random_test()) != 0)
+        err_sys("RANDOM   test failed!\n", ret);
+    else
+        printf( "RANDOM   test passed!\n");
+
+#ifndef NO_RSA
+    if ( (ret = rsa_test()) != 0) 
+        err_sys("RSA      test failed!\n", ret);
+    else
+        printf( "RSA      test passed!\n");
+#endif
+
+#ifndef NO_DH
+    if ( (ret = dh_test()) != 0) 
+        err_sys("DH       test failed!\n", ret);
+    else
+        printf( "DH       test passed!\n");
+#endif
+
+#ifndef NO_DSA
+    if ( (ret = dsa_test()) != 0) 
+        err_sys("DSA      test failed!\n", ret);
+    else
+        printf( "DSA      test passed!\n");
+#endif
+    
+#ifndef NO_PWDBASED
+    if ( (ret = pwdbased_test()) != 0) 
+        err_sys("PWDBASED test failed!\n", ret);
+    else
+        printf( "PWDBASED test passed!\n");
+#endif
+    
+#ifdef OPENSSL_EXTRA
+    if ( (ret = openssl_test()) != 0) 
+        err_sys("OPENSSL  test failed!\n", ret);
+    else
+        printf( "OPENSSL  test passed!\n");
+#endif
+
+#ifdef HAVE_ECC
+    if ( (ret = ecc_test()) != 0) 
+        err_sys("ECC      test failed!\n", ret);
+    else
+        printf( "ECC      test passed!\n");
+#endif
+
+#ifdef HAVE_LIBZ
+    if ( (ret = compress_test()) != 0) 
+        err_sys("COMPRESS test failed!\n", ret);
+    else
+        printf( "COMPRESS test passed!\n");
+#endif
+
+    ((func_args*)args)->return_code = ret;
+}
+
+
+#ifndef NO_MAIN_DRIVER
+
+#ifdef HAVE_CAVIUM
+
+static int OpenNitroxDevice(int dma_mode,int dev_id)
+{
+   Csp1CoreAssignment core_assign;
+   Uint32             device;
+
+   if (CspInitialize(CAVIUM_DIRECT,CAVIUM_DEV_ID))
+      return -1;
+   if (Csp1GetDevType(&device))
+      return -1;
+   if (device != NPX_DEVICE) {
+      if (ioctl(gpkpdev_hdlr[CAVIUM_DEV_ID], IOCTL_CSP1_GET_CORE_ASSIGNMENT,
+                (Uint32 *)&core_assign)!= 0)
+         return -1;
+   }
+   CspShutdown(CAVIUM_DEV_ID);
+
+   return CspInitialize(dma_mode, dev_id);
+}
+
+#endif /* HAVE_CAVIUM */
+
+    /* so overall tests can pull in test function */
+
+    int main(int argc, char** argv)
+    {
+
+        func_args args;
+
+            
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed", -1236);
+#endif /* HAVE_CAVIUM */
+
+        args.argc = argc;
+        args.argv = argv;
+
+        ctaocrypt_test(&args);
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+                
+        return args.return_code;
+    }
+
+#endif /* NO_MAIN_DRIVER */
+
+
+#ifdef CYASSL_MD2
+int md2_test()
+{
+    Md2  md2;
+    byte hash[MD2_DIGEST_SIZE];
+
+    testVector a, b, c, d, e, f, g;
+    testVector test_md2[7];
+    int times = sizeof(test_md2) / sizeof(testVector), i;
+
+    a.input  = "";
+    a.output = "\x83\x50\xe5\xa3\xe2\x4c\x15\x3d\xf2\x27\x5c\x9f\x80\x69"
+               "\x27\x73";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD2_DIGEST_SIZE;
+
+    b.input  = "a";
+    b.output = "\x32\xec\x01\xec\x4a\x6d\xac\x72\xc0\xab\x96\xfb\x34\xc0"
+               "\xb5\xd1";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD2_DIGEST_SIZE;
+
+    c.input  = "abc";
+    c.output = "\xda\x85\x3b\x0d\x3f\x88\xd9\x9b\x30\x28\x3a\x69\xe6\xde"
+               "\xd6\xbb";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD2_DIGEST_SIZE;
+
+    d.input  = "message digest";
+    d.output = "\xab\x4f\x49\x6b\xfb\x2a\x53\x0b\x21\x9f\xf3\x30\x31\xfe"
+               "\x06\xb0";
+    d.inLen  = strlen(d.input);
+    d.outLen = MD2_DIGEST_SIZE;
+
+    e.input  = "abcdefghijklmnopqrstuvwxyz";
+    e.output = "\x4e\x8d\xdf\xf3\x65\x02\x92\xab\x5a\x41\x08\xc3\xaa\x47"
+               "\x94\x0b";
+    e.inLen  = strlen(e.input);
+    e.outLen = MD2_DIGEST_SIZE;
+
+    f.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    f.output = "\xda\x33\xde\xf2\xa4\x2d\xf1\x39\x75\x35\x28\x46\xc3\x03"
+               "\x38\xcd";
+    f.inLen  = strlen(f.input);
+    f.outLen = MD2_DIGEST_SIZE;
+
+    g.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    g.output = "\xd5\x97\x6f\x79\xd8\x3d\x3a\x0d\xc9\x80\x6c\x3c\x66\xf3"
+               "\xef\xd8";
+    g.inLen  = strlen(g.input);
+    g.outLen = MD2_DIGEST_SIZE;
+
+    test_md2[0] = a;
+    test_md2[1] = b;
+    test_md2[2] = c;
+    test_md2[3] = d;
+    test_md2[4] = e;
+    test_md2[5] = f;
+    test_md2[6] = g;
+
+    InitMd2(&md2);
+
+    for (i = 0; i < times; ++i) {
+        Md2Update(&md2, (byte*)test_md2[i].input, (word32)test_md2[i].inLen);
+        Md2Final(&md2, hash);
+
+        if (memcmp(hash, test_md2[i].output, MD2_DIGEST_SIZE) != 0)
+            return -155 - i;
+    }
+
+    return 0;
+}
+#endif 
+
+#ifndef NO_MD5
+int md5_test(void)
+{
+    Md5  md5;
+    byte hash[MD5_DIGEST_SIZE];
+
+    testVector a, b, c, d, e;
+    testVector test_md5[5];
+    int times = sizeof(test_md5) / sizeof(testVector), i;
+
+    a.input  = "abc";
+    a.output = "\x90\x01\x50\x98\x3c\xd2\x4f\xb0\xd6\x96\x3f\x7d\x28\xe1\x7f"
+               "\x72";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD5_DIGEST_SIZE;
+
+    b.input  = "message digest";
+    b.output = "\xf9\x6b\x69\x7d\x7c\xb7\x93\x8d\x52\x5a\x2f\x31\xaa\xf1\x61"
+               "\xd0";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD5_DIGEST_SIZE;
+
+    c.input  = "abcdefghijklmnopqrstuvwxyz";
+    c.output = "\xc3\xfc\xd3\xd7\x61\x92\xe4\x00\x7d\xfb\x49\x6c\xca\x67\xe1"
+               "\x3b";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD5_DIGEST_SIZE; 
+
+    d.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    d.output = "\xd1\x74\xab\x98\xd2\x77\xd9\xf5\xa5\x61\x1c\x2c\x9f\x41\x9d"
+               "\x9f";
+    d.inLen  = strlen(d.input);
+    d.outLen = MD5_DIGEST_SIZE; 
+
+    e.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    e.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6"
+               "\x7a";
+    e.inLen  = strlen(e.input);
+    e.outLen = MD5_DIGEST_SIZE; 
+
+    test_md5[0] = a;
+    test_md5[1] = b;
+    test_md5[2] = c;
+    test_md5[3] = d;
+    test_md5[4] = e;
+
+    InitMd5(&md5);
+
+    for (i = 0; i < times; ++i) {
+        Md5Update(&md5, (byte*)test_md5[i].input, (word32)test_md5[i].inLen);
+        Md5Final(&md5, hash);
+
+        if (memcmp(hash, test_md5[i].output, MD5_DIGEST_SIZE) != 0)
+            return -5 - i;
+    }
+
+    return 0;
+}
+#endif /* NO_MD5 */
+
+
+#ifndef NO_MD4
+
+int md4_test(void)
+{
+    Md4  md4;
+    byte hash[MD4_DIGEST_SIZE];
+
+    testVector a, b, c, d, e, f, g;
+    testVector test_md4[7];
+    int times = sizeof(test_md4) / sizeof(testVector), i;
+
+    a.input  = "";
+    a.output = "\x31\xd6\xcf\xe0\xd1\x6a\xe9\x31\xb7\x3c\x59\xd7\xe0\xc0\x89" 
+               "\xc0";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD4_DIGEST_SIZE;
+
+    b.input  = "a";
+    b.output = "\xbd\xe5\x2c\xb3\x1d\xe3\x3e\x46\x24\x5e\x05\xfb\xdb\xd6\xfb" 
+               "\x24";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD4_DIGEST_SIZE; 
+
+    c.input  = "abc";
+    c.output = "\xa4\x48\x01\x7a\xaf\x21\xd8\x52\x5f\xc1\x0a\xe8\x7a\xa6\x72" 
+               "\x9d";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD4_DIGEST_SIZE;
+
+    d.input  = "message digest";
+    d.output = "\xd9\x13\x0a\x81\x64\x54\x9f\xe8\x18\x87\x48\x06\xe1\xc7\x01" 
+               "\x4b";
+    d.inLen  = strlen(d.input);
+    d.outLen = MD4_DIGEST_SIZE;
+
+    e.input  = "abcdefghijklmnopqrstuvwxyz";
+    e.output = "\xd7\x9e\x1c\x30\x8a\xa5\xbb\xcd\xee\xa8\xed\x63\xdf\x41\x2d" 
+               "\xa9";
+    e.inLen  = strlen(e.input);
+    e.outLen = MD4_DIGEST_SIZE;
+
+    f.input  = "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz012345"
+               "6789";
+    f.output = "\x04\x3f\x85\x82\xf2\x41\xdb\x35\x1c\xe6\x27\xe1\x53\xe7\xf0" 
+               "\xe4";
+    f.inLen  = strlen(f.input);
+    f.outLen = MD4_DIGEST_SIZE;
+
+    g.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    g.output = "\xe3\x3b\x4d\xdc\x9c\x38\xf2\x19\x9c\x3e\x7b\x16\x4f\xcc\x05" 
+               "\x36";
+    g.inLen  = strlen(g.input);
+    g.outLen = MD4_DIGEST_SIZE;
+
+    test_md4[0] = a;
+    test_md4[1] = b;
+    test_md4[2] = c;
+    test_md4[3] = d;
+    test_md4[4] = e;
+    test_md4[5] = f;
+    test_md4[6] = g;
+
+    InitMd4(&md4);
+
+    for (i = 0; i < times; ++i) {
+        Md4Update(&md4, (byte*)test_md4[i].input, (word32)test_md4[i].inLen);
+        Md4Final(&md4, hash);
+
+        if (memcmp(hash, test_md4[i].output, MD4_DIGEST_SIZE) != 0)
+            return -205 - i;
+    }
+
+    return 0;
+}
+
+#endif /* NO_MD4 */
+
+#ifndef NO_SHA
+
+int sha_test(void)
+{
+    Sha  sha;
+    byte hash[SHA_DIGEST_SIZE];
+
+    testVector a, b, c, d;
+    testVector test_sha[4];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xA9\x99\x3E\x36\x47\x06\x81\x6A\xBA\x3E\x25\x71\x78\x50\xC2"
+               "\x6C\x9C\xD0\xD8\x9D";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA_DIGEST_SIZE;
+
+    b.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    b.output = "\x84\x98\x3E\x44\x1C\x3B\xD2\x6E\xBA\xAE\x4A\xA1\xF9\x51\x29"
+               "\xE5\xE5\x46\x70\xF1";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA_DIGEST_SIZE;
+
+    c.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaa";
+    c.output = "\x00\x98\xBA\x82\x4B\x5C\x16\x42\x7B\xD7\xA1\x12\x2A\x5A\x44"
+               "\x2A\x25\xEC\x64\x4D";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA_DIGEST_SIZE; 
+
+    d.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaa";
+    d.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7"
+               "\x53\x99\x5E\x26\xA0";
+    d.inLen  = strlen(d.input);
+    d.outLen = SHA_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+    test_sha[2] = c;
+    test_sha[3] = d;
+
+    InitSha(&sha);
+
+    for (i = 0; i < times; ++i) {
+        ShaUpdate(&sha, (byte*)test_sha[i].input, (word32)test_sha[i].inLen);
+        ShaFinal(&sha, hash);
+
+        if (memcmp(hash, test_sha[i].output, SHA_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+
+#endif /* NO_SHA */
+
+#ifdef CYASSL_RIPEMD
+int ripemd_test(void)
+{
+    RipeMd  ripemd;
+    byte hash[RIPEMD_DIGEST_SIZE];
+
+    testVector a, b, c, d;
+    testVector test_ripemd[4];
+    int times = sizeof(test_ripemd) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\x8e\xb2\x08\xf7\xe0\x5d\x98\x7a\x9b\x04\x4a\x8e\x98\xc6"
+               "\xb0\x87\xf1\x5a\x0b\xfc";
+    a.inLen  = strlen(a.input);
+    a.outLen = RIPEMD_DIGEST_SIZE;
+
+    b.input  = "message digest";
+    b.output = "\x5d\x06\x89\xef\x49\xd2\xfa\xe5\x72\xb8\x81\xb1\x23\xa8"
+               "\x5f\xfa\x21\x59\x5f\x36";
+    b.inLen  = strlen(b.input);
+    b.outLen = RIPEMD_DIGEST_SIZE;
+
+    c.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"; 
+    c.output = "\x12\xa0\x53\x38\x4a\x9c\x0c\x88\xe4\x05\xa0\x6c\x27\xdc"
+               "\xf4\x9a\xda\x62\xeb\x2b";
+    c.inLen  = strlen(c.input);
+    c.outLen = RIPEMD_DIGEST_SIZE;
+
+    d.input  = "12345678901234567890123456789012345678901234567890123456"
+               "789012345678901234567890";
+    d.output = "\x9b\x75\x2e\x45\x57\x3d\x4b\x39\xf4\xdb\xd3\x32\x3c\xab"
+               "\x82\xbf\x63\x32\x6b\xfb"; 
+    d.inLen  = strlen(d.input);
+    d.outLen = RIPEMD_DIGEST_SIZE;
+
+    test_ripemd[0] = a;
+    test_ripemd[1] = b;
+    test_ripemd[2] = c;
+    test_ripemd[3] = d;
+
+    InitRipeMd(&ripemd);
+
+    for (i = 0; i < times; ++i) {
+        RipeMdUpdate(&ripemd, (byte*)test_ripemd[i].input,
+                     (word32)test_ripemd[i].inLen);
+        RipeMdFinal(&ripemd, hash);
+
+        if (memcmp(hash, test_ripemd[i].output, RIPEMD_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif /* CYASSL_RIPEMD */
+
+
+#ifdef HAVE_BLAKE2
+
+
+#define BLAKE2_TESTS 3
+
+static const byte blake2b_vec[BLAKE2_TESTS][BLAKE2B_OUTBYTES] =
+{
+  {
+    0x78, 0x6A, 0x02, 0xF7, 0x42, 0x01, 0x59, 0x03,
+    0xC6, 0xC6, 0xFD, 0x85, 0x25, 0x52, 0xD2, 0x72,
+    0x91, 0x2F, 0x47, 0x40, 0xE1, 0x58, 0x47, 0x61,
+    0x8A, 0x86, 0xE2, 0x17, 0xF7, 0x1F, 0x54, 0x19,
+    0xD2, 0x5E, 0x10, 0x31, 0xAF, 0xEE, 0x58, 0x53,
+    0x13, 0x89, 0x64, 0x44, 0x93, 0x4E, 0xB0, 0x4B,
+    0x90, 0x3A, 0x68, 0x5B, 0x14, 0x48, 0xB7, 0x55,
+    0xD5, 0x6F, 0x70, 0x1A, 0xFE, 0x9B, 0xE2, 0xCE
+  },
+  {
+    0x2F, 0xA3, 0xF6, 0x86, 0xDF, 0x87, 0x69, 0x95,
+    0x16, 0x7E, 0x7C, 0x2E, 0x5D, 0x74, 0xC4, 0xC7,
+    0xB6, 0xE4, 0x8F, 0x80, 0x68, 0xFE, 0x0E, 0x44,
+    0x20, 0x83, 0x44, 0xD4, 0x80, 0xF7, 0x90, 0x4C,
+    0x36, 0x96, 0x3E, 0x44, 0x11, 0x5F, 0xE3, 0xEB,
+    0x2A, 0x3A, 0xC8, 0x69, 0x4C, 0x28, 0xBC, 0xB4,
+    0xF5, 0xA0, 0xF3, 0x27, 0x6F, 0x2E, 0x79, 0x48,
+    0x7D, 0x82, 0x19, 0x05, 0x7A, 0x50, 0x6E, 0x4B
+  },
+  {
+    0x1C, 0x08, 0x79, 0x8D, 0xC6, 0x41, 0xAB, 0xA9,
+    0xDE, 0xE4, 0x35, 0xE2, 0x25, 0x19, 0xA4, 0x72,
+    0x9A, 0x09, 0xB2, 0xBF, 0xE0, 0xFF, 0x00, 0xEF,
+    0x2D, 0xCD, 0x8E, 0xD6, 0xF8, 0xA0, 0x7D, 0x15,
+    0xEA, 0xF4, 0xAE, 0xE5, 0x2B, 0xBF, 0x18, 0xAB,
+    0x56, 0x08, 0xA6, 0x19, 0x0F, 0x70, 0xB9, 0x04,
+    0x86, 0xC8, 0xA7, 0xD4, 0x87, 0x37, 0x10, 0xB1,
+    0x11, 0x5D, 0x3D, 0xEB, 0xBB, 0x43, 0x27, 0xB5
+  }
+};
+
+
+
+int blake2b_test(void)
+{
+    Blake2b b2b;
+    byte    digest[64];
+    byte    input[64];
+    int     i;
+
+    for (i = 0; i < (int)sizeof(input); i++)
+        input[i] = (byte)i;
+
+    for (i = 0; i < BLAKE2_TESTS; i++) {
+        InitBlake2b(&b2b, 64);
+        Blake2bUpdate(&b2b, input, i);
+        Blake2bFinal(&b2b, digest, 64);
+
+        if (memcmp(digest, blake2b_vec[i], 64) != 0) {
+            return -300 - i;
+        }
+    }
+
+    return 0;
+}
+#endif /* HAVE_BLAKE2 */
+
+
+#ifndef NO_SHA256
+int sha256_test(void)
+{
+    Sha256 sha;
+    byte   hash[SHA256_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xBA\x78\x16\xBF\x8F\x01\xCF\xEA\x41\x41\x40\xDE\x5D\xAE\x22"
+               "\x23\xB0\x03\x61\xA3\x96\x17\x7A\x9C\xB4\x10\xFF\x61\xF2\x00"
+               "\x15\xAD";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA256_DIGEST_SIZE;
+
+    b.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    b.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60"
+               "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB"
+               "\x06\xC1";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA256_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    InitSha256(&sha);
+
+    for (i = 0; i < times; ++i) {
+        Sha256Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        Sha256Final(&sha, hash);
+
+        if (memcmp(hash, test_sha[i].output, SHA256_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#ifdef CYASSL_SHA512
+int sha512_test(void)
+{
+    Sha512 sha;
+    byte   hash[SHA512_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xdd\xaf\x35\xa1\x93\x61\x7a\xba\xcc\x41\x73\x49\xae\x20\x41"
+               "\x31\x12\xe6\xfa\x4e\x89\xa9\x7e\xa2\x0a\x9e\xee\xe6\x4b\x55"
+               "\xd3\x9a\x21\x92\x99\x2a\x27\x4f\xc1\xa8\x36\xba\x3c\x23\xa3"
+               "\xfe\xeb\xbd\x45\x4d\x44\x23\x64\x3c\xe8\x0e\x2a\x9a\xc9\x4f"
+               "\xa5\x4c\xa4\x9f";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA512_DIGEST_SIZE;
+
+    b.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    b.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14"
+               "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88"
+               "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4"
+               "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b"
+               "\x87\x4b\xe9\x09"; 
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA512_DIGEST_SIZE;
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    InitSha512(&sha);
+
+    for (i = 0; i < times; ++i) {
+        Sha512Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        Sha512Final(&sha, hash);
+
+        if (memcmp(hash, test_sha[i].output, SHA512_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#ifdef CYASSL_SHA384
+int sha384_test(void)
+{
+    Sha384 sha;
+    byte   hash[SHA384_DIGEST_SIZE];
+
+    testVector a, b;
+    testVector test_sha[2];
+    int times = sizeof(test_sha) / sizeof(struct testVector), i;
+
+    a.input  = "abc";
+    a.output = "\xcb\x00\x75\x3f\x45\xa3\x5e\x8b\xb5\xa0\x3d\x69\x9a\xc6\x50"
+               "\x07\x27\x2c\x32\xab\x0e\xde\xd1\x63\x1a\x8b\x60\x5a\x43\xff"
+               "\x5b\xed\x80\x86\x07\x2b\xa1\xe7\xcc\x23\x58\xba\xec\xa1\x34"
+               "\xc8\x25\xa7";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA384_DIGEST_SIZE;
+
+    b.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    b.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b"
+               "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0"
+               "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91"
+               "\x74\x60\x39";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA384_DIGEST_SIZE; 
+
+    test_sha[0] = a;
+    test_sha[1] = b;
+
+    InitSha384(&sha);
+
+    for (i = 0; i < times; ++i) {
+        Sha384Update(&sha, (byte*)test_sha[i].input,(word32)test_sha[i].inLen);
+        Sha384Final(&sha, hash);
+
+        if (memcmp(hash, test_sha[i].output, SHA384_DIGEST_SIZE) != 0)
+            return -10 - i;
+    }
+
+    return 0;
+}
+#endif /* CYASSL_SHA384 */
+
+
+#if !defined(NO_HMAC) && !defined(NO_MD5)
+int hmac_md5_test(void)
+{
+    Hmac hmac;
+    byte hash[MD5_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\x92\x94\x72\x7a\x36\x38\xbb\x1c\x13\xf4\x8e\xf8\x15\x8b\xfc"
+               "\x9d";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD5_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7"
+               "\x38";
+    b.inLen  = strlen(b.input);
+    b.outLen = MD5_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x56\xbe\x34\x52\x1d\x14\x4c\x88\xdb\xb8\xc7\x33\xf0\xe8\xb3"
+               "\xf6";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD5_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#ifdef HAVE_CAVIUM
+        if (i == 1)
+            continue; /* driver can't handle keys <= bytes */
+        if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20009; 
+#endif
+        HmacSetKey(&hmac, MD5, (byte*)keys[i], (word32)strlen(keys[i]));
+        HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        HmacFinal(&hmac, hash);
+
+        if (memcmp(hash, test_hmac[i].output, MD5_DIGEST_SIZE) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif /* NO_HMAC && NO_MD5 */
+
+#if !defined(NO_HMAC) && !defined(NO_SHA)
+int hmac_sha_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xb6\x17\x31\x86\x55\x05\x72\x64\xe2\x8b\xc0\xb6\xfb\x37\x8c"
+               "\x8e\xf1\x46\xbe\x00";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\xef\xfc\xdf\x6a\xe5\xeb\x2f\xa2\xd2\x74\x16\xd5\xf1\x84\xdf"
+               "\x9c\x25\x9a\x7c\x79";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x12\x5d\x73\x42\xb9\xac\x11\xcd\x91\xa3\x9a\xf4\x8a\xa1\x7b"
+               "\x4f\x63\xf1\x75\xd3";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#ifdef HAVE_CAVIUM
+        if (i == 1)
+            continue; /* driver can't handle keys <= bytes */
+        if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20010; 
+#endif
+        HmacSetKey(&hmac, SHA, (byte*)keys[i], (word32)strlen(keys[i]));
+        HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        HmacFinal(&hmac, hash);
+
+        if (memcmp(hash, test_hmac[i].output, SHA_DIGEST_SIZE) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && !defined(NO_SHA256)
+int hmac_sha256_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA256_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xb0\x34\x4c\x61\xd8\xdb\x38\x53\x5c\xa8\xaf\xce\xaf\x0b\xf1"
+               "\x2b\x88\x1d\xc2\x00\xc9\x83\x3d\xa7\x26\xe9\x37\x6c\x2e\x32"
+               "\xcf\xf7";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA256_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x5b\xdc\xc1\x46\xbf\x60\x75\x4e\x6a\x04\x24\x26\x08\x95\x75"
+               "\xc7\x5a\x00\x3f\x08\x9d\x27\x39\x83\x9d\xec\x58\xb9\x64\xec"
+               "\x38\x43";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA256_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x77\x3e\xa9\x1e\x36\x80\x0e\x46\x85\x4d\xb8\xeb\xd0\x91\x81"
+               "\xa7\x29\x59\x09\x8b\x3e\xf8\xc1\x22\xd9\x63\x55\x14\xce\xd5"
+               "\x65\xfe";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA256_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+#ifdef HAVE_CAVIUM
+        if (i == 1)
+            continue; /* driver can't handle keys <= bytes */
+        if (HmacInitCavium(&hmac, CAVIUM_DEV_ID) != 0)
+            return -20011; 
+#endif
+        HmacSetKey(&hmac, SHA256, (byte*)keys[i], (word32)strlen(keys[i]));
+        HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        HmacFinal(&hmac, hash);
+
+        if (memcmp(hash, test_hmac[i].output, SHA256_DIGEST_SIZE) != 0)
+            return -20 - i;
+#ifdef HAVE_CAVIUM
+        HmacFreeCavium(&hmac);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && defined(CYASSL_SHA384)
+int hmac_sha384_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA384_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\xaf\xd0\x39\x44\xd8\x48\x95\x62\x6b\x08\x25\xf4\xab\x46\x90"
+               "\x7f\x15\xf9\xda\xdb\xe4\x10\x1e\xc6\x82\xaa\x03\x4c\x7c\xeb"
+               "\xc5\x9c\xfa\xea\x9e\xa9\x07\x6e\xde\x7f\x4a\xf1\x52\xe8\xb2"
+               "\xfa\x9c\xb6";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA384_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\xaf\x45\xd2\xe3\x76\x48\x40\x31\x61\x7f\x78\xd2\xb5\x8a\x6b"
+               "\x1b\x9c\x7e\xf4\x64\xf5\xa0\x1b\x47\xe4\x2e\xc3\x73\x63\x22"
+               "\x44\x5e\x8e\x22\x40\xca\x5e\x69\xe2\xc7\x8b\x32\x39\xec\xfa"
+               "\xb2\x16\x49";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA384_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\x88\x06\x26\x08\xd3\xe6\xad\x8a\x0a\xa2\xac\xe0\x14\xc8\xa8"
+               "\x6f\x0a\xa6\x35\xd9\x47\xac\x9f\xeb\xe8\x3e\xf4\xe5\x59\x66"
+               "\x14\x4b\x2a\x5a\xb3\x9d\xc1\x38\x14\xb9\x4e\x3a\xb6\xe1\x01"
+               "\xa3\x4f\x27";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA384_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+        HmacSetKey(&hmac, SHA384, (byte*)keys[i], (word32)strlen(keys[i]));
+        HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        HmacFinal(&hmac, hash);
+
+        if (memcmp(hash, test_hmac[i].output, SHA384_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#if !defined(NO_HMAC) && defined(CYASSL_SHA512)
+int hmac_sha512_test(void)
+{
+    Hmac hmac;
+    byte hash[SHA512_DIGEST_SIZE];
+
+    const char* keys[]=
+    {
+        "\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b\x0b"
+                                                                "\x0b\x0b\x0b",
+        "Jefe",
+        "\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA\xAA"
+                                                                "\xAA\xAA\xAA"
+    };
+
+    testVector a, b, c;
+    testVector test_hmac[3];
+
+    int times = sizeof(test_hmac) / sizeof(testVector), i;
+
+    a.input  = "Hi There";
+    a.output = "\x87\xaa\x7c\xde\xa5\xef\x61\x9d\x4f\xf0\xb4\x24\x1a\x1d\x6c"
+               "\xb0\x23\x79\xf4\xe2\xce\x4e\xc2\x78\x7a\xd0\xb3\x05\x45\xe1"
+               "\x7c\xde\xda\xa8\x33\xb7\xd6\xb8\xa7\x02\x03\x8b\x27\x4e\xae"
+               "\xa3\xf4\xe4\xbe\x9d\x91\x4e\xeb\x61\xf1\x70\x2e\x69\x6c\x20"
+               "\x3a\x12\x68\x54";
+    a.inLen  = strlen(a.input);
+    a.outLen = SHA512_DIGEST_SIZE;
+
+    b.input  = "what do ya want for nothing?";
+    b.output = "\x16\x4b\x7a\x7b\xfc\xf8\x19\xe2\xe3\x95\xfb\xe7\x3b\x56\xe0"
+               "\xa3\x87\xbd\x64\x22\x2e\x83\x1f\xd6\x10\x27\x0c\xd7\xea\x25"
+               "\x05\x54\x97\x58\xbf\x75\xc0\x5a\x99\x4a\x6d\x03\x4f\x65\xf8"
+               "\xf0\xe6\xfd\xca\xea\xb1\xa3\x4d\x4a\x6b\x4b\x63\x6e\x07\x0a"
+               "\x38\xbc\xe7\x37";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA512_DIGEST_SIZE;
+
+    c.input  = "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD\xDD"
+               "\xDD\xDD\xDD\xDD\xDD\xDD";
+    c.output = "\xfa\x73\xb0\x08\x9d\x56\xa2\x84\xef\xb0\xf0\x75\x6c\x89\x0b"
+               "\xe9\xb1\xb5\xdb\xdd\x8e\xe8\x1a\x36\x55\xf8\x3e\x33\xb2\x27"
+               "\x9d\x39\xbf\x3e\x84\x82\x79\xa7\x22\xc8\x06\xb4\x85\xa4\x7e"
+               "\x67\xc8\x07\xb9\x46\xa3\x37\xbe\xe8\x94\x26\x74\x27\x88\x59"
+               "\xe1\x32\x92\xfb";
+    c.inLen  = strlen(c.input);
+    c.outLen = SHA512_DIGEST_SIZE;
+
+    test_hmac[0] = a;
+    test_hmac[1] = b;
+    test_hmac[2] = c;
+
+    for (i = 0; i < times; ++i) {
+        HmacSetKey(&hmac, SHA512, (byte*)keys[i], (word32)strlen(keys[i]));
+        HmacUpdate(&hmac, (byte*)test_hmac[i].input,
+                   (word32)test_hmac[i].inLen);
+        HmacFinal(&hmac, hash);
+
+        if (memcmp(hash, test_hmac[i].output, SHA512_DIGEST_SIZE) != 0)
+            return -20 - i;
+    }
+
+    return 0;
+}
+#endif
+
+
+#ifndef NO_RC4
+int arc4_test(void)
+{
+    byte cipher[16];
+    byte plain[16];
+
+    const char* keys[] = 
+    {           
+        "\x01\x23\x45\x67\x89\xab\xcd\xef",
+        "\x01\x23\x45\x67\x89\xab\xcd\xef",
+        "\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\xef\x01\x23\x45"
+    };
+
+    testVector a, b, c, d;
+    testVector test_arc4[4];
+
+    int times = sizeof(test_arc4) / sizeof(testVector), i;
+
+    a.input  = "\x01\x23\x45\x67\x89\xab\xcd\xef";
+    a.output = "\x75\xb7\x87\x80\x99\xe0\xc5\x96";
+    a.inLen  = 8;
+    a.outLen = 8;
+
+    b.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    b.output = "\x74\x94\xc2\xe7\x10\x4b\x08\x79";
+    b.inLen  = 8;
+    b.outLen = 8;
+
+    c.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    c.output = "\xde\x18\x89\x41\xa3\x37\x5d\x3a";
+    c.inLen  = 8;
+    c.outLen = 8;
+
+    d.input  = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
+    d.output = "\xd6\xa1\x41\xa7\xec\x3c\x38\xdf\xbd\x61";
+    d.inLen  = 10;
+    d.outLen = 10;
+
+    test_arc4[0] = a;
+    test_arc4[1] = b;
+    test_arc4[2] = c;
+    test_arc4[3] = d;
+
+    for (i = 0; i < times; ++i) {
+        Arc4 enc;
+        Arc4 dec;
+        int  keylen = 8;  /* strlen with key 0x00 not good */
+        if (i == 3)
+            keylen = 4;
+
+#ifdef HAVE_CAVIUM
+        if (Arc4InitCavium(&enc, CAVIUM_DEV_ID) != 0)
+            return -20001; 
+        if (Arc4InitCavium(&dec, CAVIUM_DEV_ID) != 0)
+            return -20002; 
+#endif
+
+        Arc4SetKey(&enc, (byte*)keys[i], keylen);
+        Arc4SetKey(&dec, (byte*)keys[i], keylen);
+
+        Arc4Process(&enc, cipher, (byte*)test_arc4[i].input,
+                    (word32)test_arc4[i].outLen);
+        Arc4Process(&dec, plain,  cipher, (word32)test_arc4[i].outLen);
+
+        if (memcmp(plain, test_arc4[i].input, test_arc4[i].outLen))
+            return -20 - i;
+
+        if (memcmp(cipher, test_arc4[i].output, test_arc4[i].outLen))
+            return -20 - 5 - i;
+
+#ifdef HAVE_CAVIUM
+        Arc4FreeCavium(&enc);
+        Arc4FreeCavium(&dec);
+#endif
+    }
+
+    return 0;
+}
+#endif
+
+
+int hc128_test(void)
+{
+#ifdef HAVE_HC128
+    byte cipher[16];
+    byte plain[16];
+
+    const char* keys[] = 
+    {           
+        "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x00\x53\xA6\xF9\x4C\x9F\xF2\x45\x98\xEB\x3E\x91\xE4\x37\x8A\xDD",
+        "\x0F\x62\xB5\x08\x5B\xAE\x01\x54\xA7\xFA\x4D\xA0\xF3\x46\x99\xEC"
+    };
+
+    const char* ivs[] =
+    {
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x80\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x0D\x74\xDB\x42\xA9\x10\x77\xDE\x45\xAC\x13\x7A\xE1\x48\xAF\x16",
+        "\x28\x8F\xF6\x5D\xC4\x2B\x92\xF9\x60\xC7\x2E\x95\xFC\x63\xCA\x31"
+    };
+
+
+    testVector a, b, c, d;
+    testVector test_hc128[4];
+
+    int times = sizeof(test_hc128) / sizeof(testVector), i;
+
+    a.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    a.output = "\x37\x86\x02\xB9\x8F\x32\xA7\x48";
+    a.inLen  = 8;
+    a.outLen = 8;
+
+    b.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    b.output = "\x33\x7F\x86\x11\xC6\xED\x61\x5F";
+    b.inLen  = 8;
+    b.outLen = 8;
+
+    c.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    c.output = "\x2E\x1E\xD1\x2A\x85\x51\xC0\x5A";
+    c.inLen  = 8;
+    c.outLen = 8;
+
+    d.input  = "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00";
+    d.output = "\x1C\xD8\xAE\xDD\xFE\x52\xE2\x17\xE8\x35\xD0\xB7\xE8\x4E\x29";
+    d.inLen  = 15;
+    d.outLen = 15;
+
+    test_hc128[0] = a;
+    test_hc128[1] = b;
+    test_hc128[2] = c;
+    test_hc128[3] = d;
+
+    for (i = 0; i < times; ++i) {
+        HC128 enc;
+        HC128 dec;
+
+        /* align keys/ivs in plain/cipher buffers */
+        memcpy(plain,  keys[i], 16); 
+        memcpy(cipher, ivs[i],  16); 
+
+        Hc128_SetKey(&enc, plain, cipher);
+        Hc128_SetKey(&dec, plain, cipher);
+
+        /* align input */
+        memcpy(plain, test_hc128[i].input, test_hc128[i].outLen);
+        Hc128_Process(&enc, cipher, plain,  (word32)test_hc128[i].outLen);
+        Hc128_Process(&dec, plain,  cipher, (word32)test_hc128[i].outLen);
+
+        if (memcmp(plain, test_hc128[i].input, test_hc128[i].outLen))
+            return -120 - i;
+
+        if (memcmp(cipher, test_hc128[i].output, test_hc128[i].outLen))
+            return -120 - 5 - i;
+    }
+
+#endif /* HAVE_HC128 */
+    return 0;
+}
+
+
+#ifndef NO_RABBIT
+int rabbit_test(void)
+{
+    byte cipher[16];
+    byte plain[16];
+
+    const char* keys[] = 
+    {           
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\xAC\xC3\x51\xDC\xF1\x62\xFC\x3B\xFE\x36\x3D\x2E\x29\x13\x28\x91"
+    };
+
+    const char* ivs[] =
+    {
+        "\x00\x00\x00\x00\x00\x00\x00\x00",
+        "\x59\x7E\x26\xC1\x75\xF5\x73\xC3",
+        0
+    };
+
+    testVector a, b, c;
+    testVector test_rabbit[3];
+
+    int times = sizeof(test_rabbit) / sizeof(testVector), i;
+
+    a.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    a.output = "\xED\xB7\x05\x67\x37\x5D\xCD\x7C";
+    a.inLen  = 8;
+    a.outLen = 8;
+
+    b.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    b.output = "\x6D\x7D\x01\x22\x92\xCC\xDC\xE0";
+    b.inLen  = 8;
+    b.outLen = 8;
+
+    c.input  = "\x00\x00\x00\x00\x00\x00\x00\x00";
+    c.output = "\x9C\x51\xE2\x87\x84\xC3\x7F\xE9";
+    c.inLen  = 8;
+    c.outLen = 8;
+
+    test_rabbit[0] = a;
+    test_rabbit[1] = b;
+    test_rabbit[2] = c;
+
+    for (i = 0; i < times; ++i) {
+        Rabbit enc;
+        Rabbit dec;
+        byte*  iv;
+
+        /* align keys/ivs in plain/cipher buffers */
+        memcpy(plain,  keys[i], 16);
+        if (ivs[i]) {
+            memcpy(cipher, ivs[i],   8);
+            iv = cipher;
+        } else
+            iv = NULL;
+        RabbitSetKey(&enc, plain, iv);
+        RabbitSetKey(&dec, plain, iv);
+
+        /* align input */
+        memcpy(plain, test_rabbit[i].input, test_rabbit[i].outLen);
+        RabbitProcess(&enc, cipher, plain,  (word32)test_rabbit[i].outLen);
+        RabbitProcess(&dec, plain,  cipher, (word32)test_rabbit[i].outLen);
+
+        if (memcmp(plain, test_rabbit[i].input, test_rabbit[i].outLen))
+            return -130 - i;
+
+        if (memcmp(cipher, test_rabbit[i].output, test_rabbit[i].outLen))
+            return -130 - 5 - i;
+    }
+
+    return 0;
+}
+#endif /* NO_RABBIT */
+
+
+#ifndef NO_DES3
+int des_test(void)
+{
+    const byte vector[] = { /* "now is the time for all " w/o trailing 0 */
+        0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    byte plain[24];
+    byte cipher[24];
+
+    Des enc;
+    Des dec;
+
+    const byte key[] = 
+    {
+        0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef
+    };
+
+    const byte iv[] = 
+    {
+        0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef
+    };
+
+    const byte verify[] = 
+    {
+        0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8,
+        0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73,
+        0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b
+    };
+
+
+    Des_SetKey(&enc, key, iv, DES_ENCRYPTION);
+    Des_CbcEncrypt(&enc, cipher, vector, sizeof(vector));
+    Des_SetKey(&dec, key, iv, DES_DECRYPTION);
+    Des_CbcDecrypt(&dec, plain, cipher, sizeof(cipher));
+
+    if (memcmp(plain, vector, sizeof(plain)))
+        return -31;
+
+    if (memcmp(cipher, verify, sizeof(cipher)))
+        return -32;
+
+    return 0;
+}
+#endif /* NO_DES3 */
+
+
+#ifndef NO_DES3
+int des3_test(void)
+{
+    const byte vector[] = { /* "Now is the time for all " w/o trailing 0 */
+        0x4e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    byte plain[24];
+    byte cipher[24];
+
+    Des3 enc;
+    Des3 dec;
+
+    const byte key3[] = 
+    {
+        0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef,
+        0xfe,0xde,0xba,0x98,0x76,0x54,0x32,0x10,
+        0x89,0xab,0xcd,0xef,0x01,0x23,0x45,0x67
+    };
+    const byte iv3[] = 
+    {
+        0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef,
+        0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
+        0x11,0x21,0x31,0x41,0x51,0x61,0x71,0x81
+        
+    };
+
+    const byte verify3[] = 
+    {
+        0x43,0xa0,0x29,0x7e,0xd1,0x84,0xf8,0x0e,
+        0x89,0x64,0x84,0x32,0x12,0xd5,0x08,0x98,
+        0x18,0x94,0x15,0x74,0x87,0x12,0x7d,0xb0
+    };
+
+
+#ifdef HAVE_CAVIUM
+    if (Des3_InitCavium(&enc, CAVIUM_DEV_ID) != 0)
+        return -20005; 
+    if (Des3_InitCavium(&dec, CAVIUM_DEV_ID) != 0)
+        return -20006; 
+#endif
+    Des3_SetKey(&enc, key3, iv3, DES_ENCRYPTION);
+    Des3_SetKey(&dec, key3, iv3, DES_DECRYPTION);
+    Des3_CbcEncrypt(&enc, cipher, vector, sizeof(vector));
+    Des3_CbcDecrypt(&dec, plain, cipher, sizeof(cipher));
+
+    if (memcmp(plain, vector, sizeof(plain)))
+        return -33;
+
+    if (memcmp(cipher, verify3, sizeof(cipher)))
+        return -34;
+
+#ifdef HAVE_CAVIUM
+    Des3_FreeCavium(&enc);
+    Des3_FreeCavium(&dec);
+#endif
+    return 0;
+}
+#endif /* NO_DES */
+
+
+#ifndef NO_AES
+int aes_test(void)
+{
+    Aes enc;
+    Aes dec;
+
+    const byte msg[] = { /* "Now is the time for all " w/o trailing 0 */
+        0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    const byte verify[] = 
+    {
+        0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53,
+        0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb
+    };
+
+    byte key[] = "0123456789abcdef   ";  /* align */
+    byte iv[]  = "1234567890abcdef   ";  /* align */
+
+    byte cipher[AES_BLOCK_SIZE * 4];
+    byte plain [AES_BLOCK_SIZE * 4];
+
+#ifdef HAVE_CAVIUM
+        if (AesInitCavium(&enc, CAVIUM_DEV_ID) != 0)
+            return -20003; 
+        if (AesInitCavium(&dec, CAVIUM_DEV_ID) != 0)
+            return -20004; 
+#endif
+    AesSetKey(&enc, key, AES_BLOCK_SIZE, iv, AES_ENCRYPTION);
+    AesSetKey(&dec, key, AES_BLOCK_SIZE, iv, AES_DECRYPTION);
+
+    AesCbcEncrypt(&enc, cipher, msg,   AES_BLOCK_SIZE);
+    AesCbcDecrypt(&dec, plain, cipher, AES_BLOCK_SIZE);
+
+    if (memcmp(plain, msg, AES_BLOCK_SIZE))
+        return -60;
+
+    if (memcmp(cipher, verify, AES_BLOCK_SIZE))
+        return -61;
+
+#ifdef HAVE_CAVIUM
+        AesFreeCavium(&enc);
+        AesFreeCavium(&dec);
+#endif
+#ifdef CYASSL_AES_COUNTER
+    {
+        const byte ctrKey[] = 
+        {
+            0x2b,0x7e,0x15,0x16,0x28,0xae,0xd2,0xa6,
+            0xab,0xf7,0x15,0x88,0x09,0xcf,0x4f,0x3c
+        };
+
+        const byte ctrIv[] =
+        {
+            0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,
+            0xf8,0xf9,0xfa,0xfb,0xfc,0xfd,0xfe,0xff
+        };
+
+
+        const byte ctrPlain[] =
+        {
+            0x6b,0xc1,0xbe,0xe2,0x2e,0x40,0x9f,0x96,
+            0xe9,0x3d,0x7e,0x11,0x73,0x93,0x17,0x2a,
+            0xae,0x2d,0x8a,0x57,0x1e,0x03,0xac,0x9c,
+            0x9e,0xb7,0x6f,0xac,0x45,0xaf,0x8e,0x51,
+            0x30,0xc8,0x1c,0x46,0xa3,0x5c,0xe4,0x11,
+            0xe5,0xfb,0xc1,0x19,0x1a,0x0a,0x52,0xef,
+            0xf6,0x9f,0x24,0x45,0xdf,0x4f,0x9b,0x17,
+            0xad,0x2b,0x41,0x7b,0xe6,0x6c,0x37,0x10
+        };
+
+        const byte ctrCipher[] =
+        {
+            0x87,0x4d,0x61,0x91,0xb6,0x20,0xe3,0x26,
+            0x1b,0xef,0x68,0x64,0x99,0x0d,0xb6,0xce,
+            0x98,0x06,0xf6,0x6b,0x79,0x70,0xfd,0xff,
+            0x86,0x17,0x18,0x7b,0xb9,0xff,0xfd,0xff,
+            0x5a,0xe4,0xdf,0x3e,0xdb,0xd5,0xd3,0x5e,
+            0x5b,0x4f,0x09,0x02,0x0d,0xb0,0x3e,0xab,
+            0x1e,0x03,0x1d,0xda,0x2f,0xbe,0x03,0xd1,
+            0x79,0x21,0x70,0xa0,0xf3,0x00,0x9c,0xee
+        };
+
+        AesSetKeyDirect(&enc, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION);
+        /* Ctr only uses encrypt, even on key setup */
+        AesSetKeyDirect(&dec, ctrKey, AES_BLOCK_SIZE, ctrIv, AES_ENCRYPTION);
+
+        AesCtrEncrypt(&enc, cipher, ctrPlain, AES_BLOCK_SIZE*4);
+        AesCtrEncrypt(&dec, plain, cipher, AES_BLOCK_SIZE*4);
+
+        if (memcmp(plain, ctrPlain, AES_BLOCK_SIZE*4))
+            return -66;
+
+        if (memcmp(cipher, ctrCipher, AES_BLOCK_SIZE*4))
+            return -67;
+    }
+#endif /* CYASSL_AES_COUNTER */
+
+    return 0;
+}
+
+#ifdef HAVE_AESGCM
+int aesgcm_test(void)
+{
+    Aes enc;
+
+    /*
+     * This is Test Case 16 from the document Galois/
+     * Counter Mode of Operation (GCM) by McGrew and
+     * Viega.
+     */
+    const byte k[] =
+    {
+        0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+        0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08,
+        0xfe, 0xff, 0xe9, 0x92, 0x86, 0x65, 0x73, 0x1c,
+        0x6d, 0x6a, 0x8f, 0x94, 0x67, 0x30, 0x83, 0x08
+    };
+
+    const byte iv[] =
+    {
+        0xca, 0xfe, 0xba, 0xbe, 0xfa, 0xce, 0xdb, 0xad,
+        0xde, 0xca, 0xf8, 0x88
+    };
+    
+    const byte p[] =
+    {
+        0xd9, 0x31, 0x32, 0x25, 0xf8, 0x84, 0x06, 0xe5,
+        0xa5, 0x59, 0x09, 0xc5, 0xaf, 0xf5, 0x26, 0x9a,
+        0x86, 0xa7, 0xa9, 0x53, 0x15, 0x34, 0xf7, 0xda,
+        0x2e, 0x4c, 0x30, 0x3d, 0x8a, 0x31, 0x8a, 0x72,
+        0x1c, 0x3c, 0x0c, 0x95, 0x95, 0x68, 0x09, 0x53,
+        0x2f, 0xcf, 0x0e, 0x24, 0x49, 0xa6, 0xb5, 0x25,
+        0xb1, 0x6a, 0xed, 0xf5, 0xaa, 0x0d, 0xe6, 0x57,
+        0xba, 0x63, 0x7b, 0x39
+    };
+    
+    const byte a[] =
+    {
+        0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
+        0xfe, 0xed, 0xfa, 0xce, 0xde, 0xad, 0xbe, 0xef,
+        0xab, 0xad, 0xda, 0xd2
+    };
+    
+    const byte c[] =
+    {
+        0x52, 0x2d, 0xc1, 0xf0, 0x99, 0x56, 0x7d, 0x07,
+        0xf4, 0x7f, 0x37, 0xa3, 0x2a, 0x84, 0x42, 0x7d,
+        0x64, 0x3a, 0x8c, 0xdc, 0xbf, 0xe5, 0xc0, 0xc9,
+        0x75, 0x98, 0xa2, 0xbd, 0x25, 0x55, 0xd1, 0xaa,
+        0x8c, 0xb0, 0x8e, 0x48, 0x59, 0x0d, 0xbb, 0x3d,
+        0xa7, 0xb0, 0x8b, 0x10, 0x56, 0x82, 0x88, 0x38,
+        0xc5, 0xf6, 0x1e, 0x63, 0x93, 0xba, 0x7a, 0x0a,
+        0xbc, 0xc9, 0xf6, 0x62
+    };
+
+    const byte t[] =
+    {
+        0x76, 0xfc, 0x6e, 0xce, 0x0f, 0x4e, 0x17, 0x68,
+        0xcd, 0xdf, 0x88, 0x53, 0xbb, 0x2d, 0x55, 0x1b
+    };
+
+    byte t2[sizeof(t)];
+    byte p2[sizeof(c)];
+    byte c2[sizeof(p)];
+
+    int result;
+
+    memset(t2, 0, sizeof(t2));
+    memset(c2, 0, sizeof(c2));
+    memset(p2, 0, sizeof(p2));
+
+    AesGcmSetKey(&enc, k, sizeof(k));
+    /* AES-GCM encrypt and decrypt both use AES encrypt internally */
+    AesGcmEncrypt(&enc, c2, p, sizeof(c2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (memcmp(c, c2, sizeof(c2)))
+        return -68;
+    if (memcmp(t, t2, sizeof(t2)))
+        return -69;
+
+    result = AesGcmDecrypt(&enc, p2, c2, sizeof(p2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (result != 0)
+        return -70;
+    if (memcmp(p, p2, sizeof(p2)))
+        return -71;
+
+    return 0;
+}
+#endif /* HAVE_AESGCM */
+
+#ifdef HAVE_AESCCM
+int aesccm_test(void)
+{
+    Aes enc;
+
+    /* key */
+    const byte k[] =
+    {
+        0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7,
+        0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf
+    };
+
+    /* nonce */
+    const byte iv[] =
+    {
+        0x00, 0x00, 0x00, 0x03, 0x02, 0x01, 0x00, 0xa0,
+        0xa1, 0xa2, 0xa3, 0xa4, 0xa5
+    };
+
+    /* plaintext */
+    const byte p[] =
+    {
+        0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+        0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+        0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e
+    };
+
+    const byte a[] =
+    {
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07
+    };
+
+    const byte c[] =
+    {
+        0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x63, 0xd2,
+        0xf0, 0x66, 0xd0, 0xc2, 0xc0, 0xf9, 0x89, 0x80,
+        0x6d, 0x5f, 0x6b, 0x61, 0xda, 0xc3, 0x84
+    };
+
+    const byte t[] =
+    {
+        0x17, 0xe8, 0xd1, 0x2c, 0xfd, 0xf9, 0x26, 0xe0 
+    };
+
+    byte t2[sizeof(t)];
+    byte p2[sizeof(p)];
+    byte c2[sizeof(c)];
+
+    int result;
+
+    memset(t2, 0, sizeof(t2));
+    memset(c2, 0, sizeof(c2));
+    memset(p2, 0, sizeof(p2));
+
+    AesCcmSetKey(&enc, k, sizeof(k));
+    /* AES-CCM encrypt and decrypt both use AES encrypt internally */
+    AesCcmEncrypt(&enc, c2, p, sizeof(c2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (memcmp(c, c2, sizeof(c2)))
+        return -107;
+    if (memcmp(t, t2, sizeof(t2)))
+        return -108;
+
+    result = AesCcmDecrypt(&enc, p2, c2, sizeof(p2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (result != 0)
+        return -109;
+    if (memcmp(p, p2, sizeof(p2)))
+        return -110;
+
+    /* Test the authentication failure */
+    t2[0]++; /* Corrupt the authentication tag. */
+    result = AesCcmDecrypt(&enc, p2, c, sizeof(p2), iv, sizeof(iv),
+                                                 t2, sizeof(t2), a, sizeof(a));
+    if (result == 0)
+        return -111;
+
+    /* Clear c2 to compare against p2. p2 should be set to zero in case of
+     * authentication fail. */
+    memset(c2, 0, sizeof(c2));
+    if (memcmp(p2, c2, sizeof(p2)))
+        return -112;
+
+    return 0;
+}
+#endif /* HAVE_AESCCM */
+
+
+#endif /* NO_AES */
+
+
+#ifdef HAVE_CAMELLIA
+
+enum {
+    CAM_ECB_ENC, CAM_ECB_DEC, CAM_CBC_ENC, CAM_CBC_DEC
+};
+
+typedef struct {
+    int type;
+    const byte* plaintext;
+    const byte* iv;
+    const byte* ciphertext;
+    const byte* key;
+    word32 keySz;
+    int errorCode;
+} test_vector_t;
+
+int camellia_test(void)
+{
+    /* Camellia ECB Test Plaintext */
+    static const byte pte[] = 
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10
+    };
+
+    /* Camellia ECB Test Initialization Vector */
+    static const byte ive[] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
+
+    /* Test 1: Camellia ECB 128-bit key */
+    static const byte k1[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10
+    };
+    static const byte c1[] =
+    {
+        0x67, 0x67, 0x31, 0x38, 0x54, 0x96, 0x69, 0x73,
+        0x08, 0x57, 0x06, 0x56, 0x48, 0xea, 0xbe, 0x43
+    };
+
+    /* Test 2: Camellia ECB 192-bit key */
+    static const byte k2[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
+        0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77
+    };
+    static const byte c2[] =
+    {
+        0xb4, 0x99, 0x34, 0x01, 0xb3, 0xe9, 0x96, 0xf8,
+        0x4e, 0xe5, 0xce, 0xe7, 0xd7, 0x9b, 0x09, 0xb9
+    };
+
+    /* Test 3: Camellia ECB 256-bit key */
+    static const byte k3[] =
+    {
+        0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
+        0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
+        0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+        0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+    };
+    static const byte c3[] =
+    {
+        0x9a, 0xcc, 0x23, 0x7d, 0xff, 0x16, 0xd7, 0x6c,
+        0x20, 0xef, 0x7c, 0x91, 0x9e, 0x3a, 0x75, 0x09
+    };
+
+    /* Camellia CBC Test Plaintext */
+    static const byte ptc[] =
+    {
+        0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96,
+        0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A 
+    };
+
+    /* Camellia CBC Test Initialization Vector */
+    static const byte ivc[] =
+    {
+        0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+        0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F 
+    };
+
+    /* Test 4: Camellia-CBC 128-bit key */
+    static const byte k4[] =
+    {
+        0x2B, 0x7E, 0x15, 0x16, 0x28, 0xAE, 0xD2, 0xA6,
+        0xAB, 0xF7, 0x15, 0x88, 0x09, 0xCF, 0x4F, 0x3C 
+    };
+    static const byte c4[] =
+    {
+        0x16, 0x07, 0xCF, 0x49, 0x4B, 0x36, 0xBB, 0xF0,
+        0x0D, 0xAE, 0xB0, 0xB5, 0x03, 0xC8, 0x31, 0xAB 
+    };
+
+    /* Test 5: Camellia-CBC 192-bit key */
+    static const byte k5[] =
+    {
+        0x8E, 0x73, 0xB0, 0xF7, 0xDA, 0x0E, 0x64, 0x52,
+        0xC8, 0x10, 0xF3, 0x2B, 0x80, 0x90, 0x79, 0xE5,
+        0x62, 0xF8, 0xEA, 0xD2, 0x52, 0x2C, 0x6B, 0x7B 
+    };
+    static const byte c5[] =
+    {
+        0x2A, 0x48, 0x30, 0xAB, 0x5A, 0xC4, 0xA1, 0xA2,
+        0x40, 0x59, 0x55, 0xFD, 0x21, 0x95, 0xCF, 0x93 
+    };
+
+    /* Test 6: CBC 256-bit key */
+    static const byte k6[] =
+    {
+        0x60, 0x3D, 0xEB, 0x10, 0x15, 0xCA, 0x71, 0xBE,
+        0x2B, 0x73, 0xAE, 0xF0, 0x85, 0x7D, 0x77, 0x81,
+        0x1F, 0x35, 0x2C, 0x07, 0x3B, 0x61, 0x08, 0xD7,
+        0x2D, 0x98, 0x10, 0xA3, 0x09, 0x14, 0xDF, 0xF4 
+    };
+    static const byte c6[] =
+    {
+        0xE6, 0xCF, 0xA3, 0x5F, 0xC0, 0x2B, 0x13, 0x4A,
+        0x4D, 0x2C, 0x0B, 0x67, 0x37, 0xAC, 0x3E, 0xDA 
+    };
+
+    byte out[CAMELLIA_BLOCK_SIZE];
+    Camellia cam;
+    int i, testsSz;
+    const test_vector_t testVectors[] =
+    {
+        {CAM_ECB_ENC, pte, ive, c1, k1, sizeof(k1), -114},
+        {CAM_ECB_ENC, pte, ive, c2, k2, sizeof(k2), -115},
+        {CAM_ECB_ENC, pte, ive, c3, k3, sizeof(k3), -116},
+        {CAM_ECB_DEC, pte, ive, c1, k1, sizeof(k1), -117},
+        {CAM_ECB_DEC, pte, ive, c2, k2, sizeof(k2), -118},
+        {CAM_ECB_DEC, pte, ive, c3, k3, sizeof(k3), -119},
+        {CAM_CBC_ENC, ptc, ivc, c4, k4, sizeof(k4), -120},
+        {CAM_CBC_ENC, ptc, ivc, c5, k5, sizeof(k5), -121},
+        {CAM_CBC_ENC, ptc, ivc, c6, k6, sizeof(k6), -122},
+        {CAM_CBC_DEC, ptc, ivc, c4, k4, sizeof(k4), -123},
+        {CAM_CBC_DEC, ptc, ivc, c5, k5, sizeof(k5), -124},
+        {CAM_CBC_DEC, ptc, ivc, c6, k6, sizeof(k6), -125}
+    };
+
+    if ((sizeof(pte) != CAMELLIA_BLOCK_SIZE) ||
+                                          (sizeof(ptc) != CAMELLIA_BLOCK_SIZE))
+        return -113;
+
+    testsSz = sizeof(testVectors)/sizeof(test_vector_t);
+    for (i = 0; i < testsSz; i++) {
+        CamelliaSetKey(&cam, testVectors[i].key, testVectors[i].keySz,
+                                                             testVectors[i].iv);
+
+        switch (testVectors[i].type) {
+            case CAM_ECB_ENC:
+                CamelliaEncryptDirect(&cam, out, testVectors[i].plaintext);
+                if (memcmp(out, testVectors[i].ciphertext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            case CAM_ECB_DEC:
+                CamelliaDecryptDirect(&cam, out, testVectors[i].ciphertext);
+                if (memcmp(out, testVectors[i].plaintext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            case CAM_CBC_ENC:
+                CamelliaCbcEncrypt(&cam, out, testVectors[i].plaintext,
+                                                           CAMELLIA_BLOCK_SIZE);
+                if (memcmp(out, testVectors[i].ciphertext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            case CAM_CBC_DEC:
+                CamelliaCbcDecrypt(&cam, out, testVectors[i].ciphertext,
+                                                           CAMELLIA_BLOCK_SIZE);
+                if (memcmp(out, testVectors[i].plaintext, CAMELLIA_BLOCK_SIZE))
+                    return testVectors[i].errorCode;
+                break;
+            default:
+                break;
+        }
+    }
+
+    /* Setting the IV and checking it was actually set. */
+    CamelliaSetIV(&cam, ivc);
+    if (XMEMCMP(cam.reg, ivc, CAMELLIA_BLOCK_SIZE))
+        return -1;
+
+    /* Setting the IV to NULL should leave the IV unchanged */
+    if (CamelliaSetIV(&cam, NULL) != 0 ||
+                                    XMEMCMP(cam.reg, ive, CAMELLIA_BLOCK_SIZE))
+        return -1;
+    
+    /* First parameter should never be null */
+    if (CamelliaSetIV(NULL, NULL) == 0)
+        return -1;
+
+    /* Key should have a size of 16, 24, or 32 */
+    if (CamelliaSetKey(&cam, k1, 0, NULL) == 0)
+        return -1;
+
+    return 0;
+}
+#endif /* HAVE_CAMELLIA */
+
+
+int random_test(void)
+{
+    RNG  rng;
+    byte block[32];
+    int ret;
+
+#ifdef HAVE_CAVIUM
+    ret = InitRngCavium(&rng, CAVIUM_DEV_ID);
+    if (ret != 0) return -2007;
+#endif
+    ret = InitRng(&rng);
+    if (ret != 0) return -39;
+
+    RNG_GenerateBlock(&rng, block, sizeof(block));
+
+    return 0;
+}
+
+
+#ifdef HAVE_NTRU
+
+byte GetEntropy(ENTROPY_CMD cmd, byte* out);
+
+byte GetEntropy(ENTROPY_CMD cmd, byte* out)
+{
+    static RNG rng;
+
+    if (cmd == INIT) {
+        int ret = InitRng(&rng);
+        if (ret == 0)
+            return 1;
+        else
+            return 0;
+    }
+
+    if (out == NULL)
+        return 0;
+
+    if (cmd == GET_BYTE_OF_ENTROPY) {
+        RNG_GenerateBlock(&rng, out, 1);
+        return 1;
+    }
+
+    if (cmd == GET_NUM_BYTES_PER_BYTE_OF_ENTROPY) {
+        *out = 1;
+        return 1;
+    }
+
+    return 0;
+}
+
+#endif /* HAVE_NTRU */
+
+#ifndef NO_RSA
+
+#ifdef FREESCALE_MQX
+    static const char* clientKey  = "a:\\certs\\client-key.der";
+    static const char* clientCert = "a:\\certs\\client-cert.der";
+    #ifdef CYASSL_CERT_GEN
+        static const char* caKeyFile  = "a:\\certs\\ca-key.der";
+        static const char* caCertFile = "a:\\certs\\ca-cert.pem";
+    #endif
+#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) && defined(CYASSL_MKD_SHELL) 
+    static char* clientKey = "certs/client-key.der";
+    static char* clientCert = "certs/client-cert.der";
+    void set_clientKey(char *key) {  clientKey = key ; }      /* set by shell command */
+    void set_clientCert(char *cert) {  clientCert = cert ; }  /* set by shell command */        
+    #ifdef CYASSL_CERT_GEN
+        static char* caKeyFile  = "certs/ca-key.der";
+        static char* caCertFile = "certs/ca-cert.pem";
+        void set_caKeyFile (char * key)  { caKeyFile   = key ; }     /* set by shell command */
+        void set_caCertFile(char * cert) { caCertFile = cert ; }     /* set by shell command */
+    #endif
+#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048) 
+    static const char* clientKey  = "./certs/client-key.der";
+    static const char* clientCert = "./certs/client-cert.der";
+    #ifdef CYASSL_CERT_GEN
+        static const char* caKeyFile  = "./certs/ca-key.der";
+        static const char* caCertFile = "./certs/ca-cert.pem";
+    #endif
+#endif
+
+
+
+#define FOURK_BUF 4096
+
+int rsa_test(void)
+{
+    byte*   tmp;
+    size_t bytes;
+    RsaKey key;
+    RNG    rng;
+    word32 idx = 0;
+    int    ret;
+    byte   in[] = "Everyone gets Friday off.";
+    word32 inLen = (word32)strlen((char*)in);
+    byte   out[256];
+    byte   plain[256];
+#if !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    FILE*  file, * file2;
+#endif
+#ifdef CYASSL_TEST_CERT
+    DecodedCert cert;
+#endif
+
+    tmp = (byte*)malloc(FOURK_BUF);
+    if (tmp == NULL)
+        return -40;
+
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, client_key_der_1024, sizeof_client_key_der_1024);
+    bytes = sizeof_client_key_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, client_key_der_2048, sizeof_client_key_der_2048);
+    bytes = sizeof_client_key_der_2048;
+#else
+    file = fopen(clientKey, "rb");
+
+    if (!file)
+        err_sys("can't open ./certs/client-key.der, "
+                "Please run from CyaSSL home dir", -40);
+
+    bytes = fread(tmp, 1, FOURK_BUF, file);
+    fclose(file);
+#endif /* USE_CERT_BUFFERS */
+ 
+#ifdef HAVE_CAVIUM
+    RsaInitCavium(&key, CAVIUM_DEV_ID);
+#endif 
+    InitRsaKey(&key, 0);  
+    ret = RsaPrivateKeyDecode(tmp, &idx, &key, (word32)bytes);
+    if (ret != 0) return -41;
+
+    ret = InitRng(&rng);
+    if (ret != 0) return -42;
+
+    ret = RsaPublicEncrypt(in, inLen, out, sizeof(out), &key, &rng);
+    if (ret < 0) return -43;
+
+    ret = RsaPrivateDecrypt(out, ret, plain, sizeof(plain), &key);
+    if (ret < 0) return -44;
+
+    if (memcmp(plain, in, inLen)) return -45;
+
+    ret = RsaSSL_Sign(in, inLen, out, sizeof(out), &key, &rng);
+    if (ret < 0) return -46;
+
+    memset(plain, 0, sizeof(plain));
+    ret = RsaSSL_Verify(out, ret, plain, sizeof(plain), &key);
+    if (ret < 0) return -47;
+
+    if (memcmp(plain, in, ret)) return -48;
+
+#if defined(CYASSL_MDK_ARM)
+    #define sizeof(s) strlen((char *)(s))
+#endif
+
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, client_cert_der_1024, sizeof_client_cert_der_1024);
+    bytes = sizeof_client_cert_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, client_cert_der_2048, sizeof_client_cert_der_2048);
+    bytes = sizeof_client_cert_der_2048;
+#else
+    file2 = fopen(clientCert, "rb");
+    if (!file2)
+        return -49;
+
+    bytes = fread(tmp, 1, FOURK_BUF, file2);
+    fclose(file2);
+#endif
+
+#ifdef sizeof
+        #undef sizeof
+#endif      
+
+#ifdef CYASSL_TEST_CERT
+    InitDecodedCert(&cert, tmp, (word32)bytes, 0);
+
+    ret = ParseCert(&cert, CERT_TYPE, NO_VERIFY, 0);
+    if (ret != 0) return -491;
+
+    FreeDecodedCert(&cert);
+#else
+    (void)bytes;
+#endif
+
+
+#ifdef CYASSL_KEY_GEN
+    {
+        byte*  der;
+        byte*  pem;
+        int    derSz = 0;
+        int    pemSz = 0;
+        RsaKey derIn;
+        RsaKey genKey;
+        FILE* keyFile;
+        FILE* pemFile;
+
+        InitRsaKey(&genKey, 0);
+        ret = MakeRsaKey(&genKey, 1024, 65537, &rng);
+        if (ret != 0)
+            return -301;
+
+        der = (byte*)malloc(FOURK_BUF);
+        if (der == NULL)
+            return -307;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL)
+            return -308;
+
+        derSz = RsaKeyToDer(&genKey, der, FOURK_BUF);
+        if (derSz < 0)
+            return -302;
+
+        keyFile = fopen("./key.der", "wb");
+        if (!keyFile)
+            return -303;
+        ret = (int)fwrite(der, derSz, 1, keyFile);
+        fclose(keyFile);
+
+        pemSz = DerToPem(der, derSz, pem, FOURK_BUF, PRIVATEKEY_TYPE);
+        if (pemSz < 0)
+            return -304;
+
+        pemFile = fopen("./key.pem", "wb");
+        if (!pemFile) 
+            return -305;
+        ret = (int)fwrite(pem, pemSz, 1, pemFile);
+        fclose(pemFile);
+
+        InitRsaKey(&derIn, 0);
+        idx = 0;
+        ret = RsaPrivateKeyDecode(der, &idx, &derIn, derSz);
+        if (ret != 0)
+            return -306;
+
+        FreeRsaKey(&derIn);
+        FreeRsaKey(&genKey);
+        free(pem);
+        free(der);
+    }
+#endif /* CYASSL_KEY_GEN */
+
+
+#ifdef CYASSL_CERT_GEN
+    /* self signed */
+    {
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        int         certSz;
+        int         pemSz;
+#ifdef CYASSL_TEST_CERT
+        DecodedCert decode;
+#endif
+
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -309;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL)
+            return -310;
+
+        InitCert(&myCert);
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+        myCert.isCA    = 1;
+        myCert.sigType = CTC_SHA256wRSA;
+
+        certSz = MakeSelfCert(&myCert, derCert, FOURK_BUF, &key, &rng); 
+        if (certSz < 0)
+            return -401;
+
+#ifdef CYASSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0)
+            return -402;
+        FreeDecodedCert(&decode);
+#endif
+        derFile = fopen("./cert.der", "wb");
+        if (!derFile)
+            return -403;
+        ret = (int)fwrite(derCert, certSz, 1, derFile);
+        fclose(derFile);
+
+        pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0)
+            return -404;
+
+        pemFile = fopen("./cert.pem", "wb");
+        if (!pemFile)
+            return -405;
+        ret = (int)fwrite(pem, pemSz, 1, pemFile);
+        fclose(pemFile);
+        free(pem);
+        free(derCert);
+    }
+    /* CA style */
+    {
+        RsaKey      caKey;
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        int         certSz;
+        int         pemSz;
+        size_t      bytes3;
+        word32      idx3 = 0;
+              FILE* file3 ;
+#ifdef CYASSL_TEST_CERT
+        DecodedCert decode;
+#endif
+
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -311;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL)
+            return -312;
+
+        file3 = fopen(caKeyFile, "rb");
+
+        if (!file3)
+            return -412;
+
+        bytes3 = fread(tmp, 1, FOURK_BUF, file3);
+        fclose(file3);
+  
+        InitRsaKey(&caKey, 0);  
+        ret = RsaPrivateKeyDecode(tmp, &idx3, &caKey, (word32)bytes3);
+        if (ret != 0) return -413;
+
+        InitCert(&myCert);
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+
+        ret = SetIssuer(&myCert, caCertFile);
+        if (ret < 0)
+            return -405;
+
+        certSz = MakeCert(&myCert, derCert, FOURK_BUF, &key, &rng); 
+        if (certSz < 0)
+            return -407;
+
+        certSz = SignCert(&myCert, derCert, FOURK_BUF, &caKey, &rng);
+        if (certSz < 0)
+            return -408;
+
+
+#ifdef CYASSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0)
+            return -409;
+        FreeDecodedCert(&decode);
+#endif
+
+        derFile = fopen("./othercert.der", "wb");
+        if (!derFile)
+            return -410;
+        ret = (int)fwrite(derCert, certSz, 1, derFile);
+        fclose(derFile);
+
+        pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0)
+            return -411;
+
+        pemFile = fopen("./othercert.pem", "wb");
+        if (!pemFile)
+            return -412;
+        ret = (int)fwrite(pem, pemSz, 1, pemFile);
+        fclose(pemFile);
+        free(pem);
+        free(derCert);
+        FreeRsaKey(&caKey);
+    }
+#ifdef HAVE_NTRU
+    {
+        RsaKey      caKey;
+        Cert        myCert;
+        byte*       derCert;
+        byte*       pem;
+        FILE*       derFile;
+        FILE*       pemFile;
+        FILE*       caFile;
+        FILE*       ntruPrivFile;
+        int         certSz;
+        int         pemSz;
+        size_t      bytes;
+        word32      idx = 0;
+#ifdef CYASSL_TEST_CERT
+        DecodedCert decode;
+#endif
+        derCert = (byte*)malloc(FOURK_BUF);
+        if (derCert == NULL)
+            return -311;
+        pem = (byte*)malloc(FOURK_BUF);
+        if (pem == NULL)
+            return -312;
+
+        byte   public_key[557];          /* sized for EES401EP2 */
+        word16 public_key_len;           /* no. of octets in public key */
+        byte   private_key[607];         /* sized for EES401EP2 */
+        word16 private_key_len;          /* no. of octets in private key */
+        DRBG_HANDLE drbg;
+        static uint8_t const pers_str[] = {
+                'C', 'y', 'a', 'S', 'S', 'L', ' ', 't', 'e', 's', 't'
+        };
+        word32 rc = crypto_drbg_instantiate(112, pers_str, sizeof(pers_str),
+                                            GetEntropy, &drbg);
+        if (rc != DRBG_OK)
+            return -450;
+
+        rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len,
+                                        NULL, &private_key_len, NULL);
+        if (rc != NTRU_OK)
+            return -451;
+
+        rc = crypto_ntru_encrypt_keygen(drbg, NTRU_EES401EP2, &public_key_len,
+                                     public_key, &private_key_len, private_key);
+        crypto_drbg_uninstantiate(drbg);
+
+        if (rc != NTRU_OK)
+            return -452;
+
+        caFile = fopen(caKeyFile, "rb");
+
+        if (!caFile)
+            return -453;
+
+        bytes = fread(tmp, 1, FOURK_BUF, caFile);
+        fclose(caFile);
+  
+        InitRsaKey(&caKey, 0);  
+        ret = RsaPrivateKeyDecode(tmp, &idx, &caKey, (word32)bytes);
+        if (ret != 0) return -454;
+
+        InitCert(&myCert);
+
+        strncpy(myCert.subject.country, "US", CTC_NAME_SIZE);
+        strncpy(myCert.subject.state, "OR", CTC_NAME_SIZE);
+        strncpy(myCert.subject.locality, "Portland", CTC_NAME_SIZE);
+        strncpy(myCert.subject.org, "yaSSL", CTC_NAME_SIZE);
+        strncpy(myCert.subject.unit, "Development", CTC_NAME_SIZE);
+        strncpy(myCert.subject.commonName, "www.yassl.com", CTC_NAME_SIZE);
+        strncpy(myCert.subject.email, "info@yassl.com", CTC_NAME_SIZE);
+
+        ret = SetIssuer(&myCert, caCertFile);
+        if (ret < 0)
+            return -455;
+
+        certSz = MakeNtruCert(&myCert, derCert, FOURK_BUF, public_key,
+                              public_key_len, &rng); 
+        if (certSz < 0)
+            return -456;
+
+        certSz = SignCert(&myCert, derCert, FOURK_BUF, &caKey, &rng);
+        if (certSz < 0)
+            return -457;
+
+
+#ifdef CYASSL_TEST_CERT
+        InitDecodedCert(&decode, derCert, certSz, 0);
+        ret = ParseCert(&decode, CERT_TYPE, NO_VERIFY, 0);
+        if (ret != 0)
+            return -458;
+        FreeDecodedCert(&decode);
+#endif
+        derFile = fopen("./ntru-cert.der", "wb");
+        if (!derFile)
+            return -459;
+        ret = fwrite(derCert, certSz, 1, derFile);
+        fclose(derFile);
+
+        pemSz = DerToPem(derCert, certSz, pem, FOURK_BUF, CERT_TYPE);
+        if (pemSz < 0)
+            return -460;
+
+        pemFile = fopen("./ntru-cert.pem", "wb");
+        if (!pemFile)
+            return -461;
+        ret = fwrite(pem, pemSz, 1, pemFile);
+        fclose(pemFile);
+
+        ntruPrivFile = fopen("./ntru-key.raw", "wb");
+        if (!ntruPrivFile)
+            return -462;
+        ret = fwrite(private_key, private_key_len, 1, ntruPrivFile);
+        fclose(ntruPrivFile);
+        free(pem);
+        free(derCert);
+        FreeRsaKey(&caKey);
+    }
+#endif /* HAVE_NTRU */
+#endif /* CYASSL_CERT_GEN */
+
+    FreeRsaKey(&key);
+#ifdef HAVE_CAVIUM
+    RsaFreeCavium(&key);
+#endif 
+    free(tmp);
+
+    return 0;
+}
+
+#endif
+
+
+#ifndef NO_DH
+
+#ifdef FREESCALE_MQX
+    static const char* dhKey = "a:\certs\\dh2048.der";
+#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    static const char* dhKey = "./certs/dh2048.der";
+#endif
+
+int dh_test(void)
+{
+    int    ret;
+    word32 bytes;
+    word32 idx = 0, privSz, pubSz, privSz2, pubSz2, agreeSz, agreeSz2;
+    byte   tmp[1024];
+    byte   priv[256];
+    byte   pub[256];
+    byte   priv2[256];
+    byte   pub2[256];
+    byte   agree[256];
+    byte   agree2[256];
+    DhKey  key;
+    DhKey  key2;
+    RNG    rng;
+    
+        
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, dh_key_der_1024, sizeof_dh_key_der_1024);
+    bytes = sizeof_dh_key_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, dh_key_der_2048, sizeof_dh_key_der_2048);
+    bytes = sizeof_dh_key_der_2048;
+#else
+    FILE*  file = fopen(dhKey, "rb");
+
+    if (!file)
+        return -50;
+
+    bytes = (word32) fread(tmp, 1, sizeof(tmp), file);
+    fclose(file);
+#endif /* USE_CERT_BUFFERS */
+
+    InitDhKey(&key);  
+    InitDhKey(&key2);  
+    ret = DhKeyDecode(tmp, &idx, &key, bytes);
+    if (ret != 0)
+        return -51;
+
+    idx = 0;
+    ret = DhKeyDecode(tmp, &idx, &key2, bytes);
+    if (ret != 0)
+        return -52;
+
+    ret = InitRng(&rng);
+    if (ret != 0)
+        return -53;
+    
+    ret =  DhGenerateKeyPair(&key, &rng, priv, &privSz, pub, &pubSz);
+    ret += DhGenerateKeyPair(&key2, &rng, priv2, &privSz2, pub2, &pubSz2);
+    if (ret != 0)
+        return -54;
+
+    ret =  DhAgree(&key, agree, &agreeSz, priv, privSz, pub2, pubSz2);
+    ret += DhAgree(&key2, agree2, &agreeSz2, priv2, privSz2, pub, pubSz);
+    if (ret != 0)
+        return -55;
+
+    if (memcmp(agree, agree2, agreeSz))
+        return -56;
+
+    FreeDhKey(&key);
+    FreeDhKey(&key2);
+
+    return 0;
+}
+
+#endif /* NO_DH */
+
+
+#ifndef NO_DSA
+
+#ifdef FREESCALE_MQX
+    static const char* dsaKey = "a:\\certs\\dsa2048.der";
+#elif !defined(USE_CERT_BUFFERS_1024) && !defined(USE_CERT_BUFFERS_2048)
+    static const char* dsaKey = "./certs/dsa2048.der";
+#endif
+
+int dsa_test(void)
+{
+    int    ret, answer;
+    word32 bytes;
+    word32 idx = 0;
+    byte   tmp[1024];
+    DsaKey key;
+    RNG    rng;
+    Sha    sha;
+    byte   hash[SHA_DIGEST_SIZE];
+    byte   signature[40];
+
+        
+#ifdef USE_CERT_BUFFERS_1024
+    XMEMCPY(tmp, dsa_key_der_1024, sizeof_dsa_key_der_1024);
+    bytes = sizeof_dsa_key_der_1024;
+#elif defined(USE_CERT_BUFFERS_2048)
+    XMEMCPY(tmp, dsa_key_der_2048, sizeof_dsa_key_der_2048);
+    bytes = sizeof_dsa_key_der_2048;
+#else
+    FILE*  file = fopen(dsaKey, "rb");
+
+    if (!file)
+        return -60;
+
+    bytes = (word32) fread(tmp, 1, sizeof(tmp), file);
+    fclose(file);
+#endif /* USE_CERT_BUFFERS */
+  
+    InitSha(&sha);
+    ShaUpdate(&sha, tmp, bytes);
+    ShaFinal(&sha, hash);
+
+    InitDsaKey(&key);
+    ret = DsaPrivateKeyDecode(tmp, &idx, &key, bytes);
+    if (ret != 0) return -61;
+
+    ret = InitRng(&rng);
+    if (ret != 0) return -62;
+
+    ret = DsaSign(hash, signature, &key, &rng);
+    if (ret != 0) return -63;
+
+    ret = DsaVerify(hash, signature, &key, &answer);
+    if (ret != 0) return -64;
+    if (answer != 1) return -65;
+    
+    FreeDsaKey(&key);
+    
+    return 0;
+}
+
+#endif /* NO_DSA */
+
+
+#ifdef OPENSSL_EXTRA
+
+int openssl_test(void)
+{
+    EVP_MD_CTX md_ctx;
+    testVector a, b, c, d, e, f;
+    byte       hash[SHA_DIGEST_SIZE*4];  /* max size */
+
+    (void)e;
+    (void)f;
+
+    a.input  = "1234567890123456789012345678901234567890123456789012345678"
+               "9012345678901234567890";
+    a.output = "\x57\xed\xf4\xa2\x2b\xe3\xc9\x55\xac\x49\xda\x2e\x21\x07\xb6"
+               "\x7a";
+    a.inLen  = strlen(a.input);
+    a.outLen = MD5_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_md5());
+
+    EVP_DigestUpdate(&md_ctx, a.input, a.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, a.output, MD5_DIGEST_SIZE) != 0)
+        return -71;
+
+    b.input  = "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa"
+               "aaaaaaaaaa";
+    b.output = "\xAD\x5B\x3F\xDB\xCB\x52\x67\x78\xC2\x83\x9D\x2F\x15\x1E\xA7"
+               "\x53\x99\x5E\x26\xA0";
+    b.inLen  = strlen(b.input);
+    b.outLen = SHA_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha1());
+
+    EVP_DigestUpdate(&md_ctx, b.input, b.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, b.output, SHA_DIGEST_SIZE) != 0)
+        return -72;
+
+
+    d.input  = "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq";
+    d.output = "\x24\x8D\x6A\x61\xD2\x06\x38\xB8\xE5\xC0\x26\x93\x0C\x3E\x60"
+               "\x39\xA3\x3C\xE4\x59\x64\xFF\x21\x67\xF6\xEC\xED\xD4\x19\xDB"
+               "\x06\xC1";
+    d.inLen  = strlen(d.input);
+    d.outLen = SHA256_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha256());
+
+    EVP_DigestUpdate(&md_ctx, d.input, d.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, d.output, SHA256_DIGEST_SIZE) != 0)
+        return -78;
+
+#ifdef CYASSL_SHA384
+
+    e.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    e.output = "\x09\x33\x0c\x33\xf7\x11\x47\xe8\x3d\x19\x2f\xc7\x82\xcd\x1b"
+               "\x47\x53\x11\x1b\x17\x3b\x3b\x05\xd2\x2f\xa0\x80\x86\xe3\xb0"
+               "\xf7\x12\xfc\xc7\xc7\x1a\x55\x7e\x2d\xb9\x66\xc3\xe9\xfa\x91"
+               "\x74\x60\x39";    
+    e.inLen  = strlen(e.input);
+    e.outLen = SHA384_DIGEST_SIZE;
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha384());
+
+    EVP_DigestUpdate(&md_ctx, e.input, e.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, e.output, SHA384_DIGEST_SIZE) != 0)
+        return -79;
+
+#endif /* CYASSL_SHA384 */
+
+
+#ifdef CYASSL_SHA512
+
+    f.input  = "abcdefghbcdefghicdefghijdefghijkefghijklfghijklmghijklmnhi"
+               "jklmnoijklmnopjklmnopqklmnopqrlmnopqrsmnopqrstnopqrstu";
+    f.output = "\x8e\x95\x9b\x75\xda\xe3\x13\xda\x8c\xf4\xf7\x28\x14\xfc\x14"
+               "\x3f\x8f\x77\x79\xc6\xeb\x9f\x7f\xa1\x72\x99\xae\xad\xb6\x88"
+               "\x90\x18\x50\x1d\x28\x9e\x49\x00\xf7\xe4\x33\x1b\x99\xde\xc4"
+               "\xb5\x43\x3a\xc7\xd3\x29\xee\xb6\xdd\x26\x54\x5e\x96\xe5\x5b"
+               "\x87\x4b\xe9\x09"; 
+    f.inLen  = strlen(f.input);
+    f.outLen = SHA512_DIGEST_SIZE; 
+
+    EVP_MD_CTX_init(&md_ctx);
+    EVP_DigestInit(&md_ctx, EVP_sha512());
+
+    EVP_DigestUpdate(&md_ctx, f.input, f.inLen);
+    EVP_DigestFinal(&md_ctx, hash, 0);
+
+    if (memcmp(hash, f.output, SHA512_DIGEST_SIZE) != 0)
+        return -80;
+
+#endif /* CYASSL_SHA512 */
+
+
+    if (RAND_bytes(hash, sizeof(hash)) != 1)
+        return -73;
+            
+    c.input  = "what do ya want for nothing?";
+    c.output = "\x75\x0c\x78\x3e\x6a\xb0\xb5\x03\xea\xa8\x6e\x31\x0a\x5d\xb7"
+               "\x38";
+    c.inLen  = strlen(c.input);
+    c.outLen = MD5_DIGEST_SIZE;
+
+    HMAC(EVP_md5(), "Jefe", 4, (byte*)c.input, (int)c.inLen, hash, 0);
+
+    if (memcmp(hash, c.output, MD5_DIGEST_SIZE) != 0)
+        return -74;
+
+    { /* des test */
+    const byte vector[] = { /* "now is the time for all " w/o trailing 0 */
+        0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+        0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+        0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+    };
+
+    byte plain[24];
+    byte cipher[24];
+
+    const_DES_cblock key = 
+    {
+        0x01,0x23,0x45,0x67,0x89,0xab,0xcd,0xef
+    };
+
+    DES_cblock iv = 
+    {
+        0x12,0x34,0x56,0x78,0x90,0xab,0xcd,0xef
+    };
+
+    DES_key_schedule sched;
+
+    const byte verify[] = 
+    {
+        0x8b,0x7c,0x52,0xb0,0x01,0x2b,0x6c,0xb8,
+        0x4f,0x0f,0xeb,0xf3,0xfb,0x5f,0x86,0x73,
+        0x15,0x85,0xb3,0x22,0x4b,0x86,0x2b,0x4b
+    };
+
+    DES_key_sched(&key, &sched);
+
+    DES_cbc_encrypt(vector, cipher, sizeof(vector), &sched, &iv, DES_ENCRYPT);
+    DES_cbc_encrypt(cipher, plain, sizeof(vector), &sched, &iv, DES_DECRYPT);
+
+    if (memcmp(plain, vector, sizeof(vector)) != 0)
+        return -75;
+
+    if (memcmp(cipher, verify, sizeof(verify)) != 0)
+        return -76;
+
+        /* test changing iv */
+    DES_ncbc_encrypt(vector, cipher, 8, &sched, &iv, DES_ENCRYPT);
+    DES_ncbc_encrypt(vector + 8, cipher + 8, 16, &sched, &iv, DES_ENCRYPT);
+
+    if (memcmp(cipher, verify, sizeof(verify)) != 0)
+        return -77;
+
+    }  /* end des test */
+
+    {  /* evp_cipher test */
+        EVP_CIPHER_CTX ctx;
+
+
+        const byte msg[] = { /* "Now is the time for all " w/o trailing 0 */
+            0x6e,0x6f,0x77,0x20,0x69,0x73,0x20,0x74,
+            0x68,0x65,0x20,0x74,0x69,0x6d,0x65,0x20,
+            0x66,0x6f,0x72,0x20,0x61,0x6c,0x6c,0x20
+        };
+
+        const byte verify[] = 
+        {
+            0x95,0x94,0x92,0x57,0x5f,0x42,0x81,0x53,
+            0x2c,0xcc,0x9d,0x46,0x77,0xa2,0x33,0xcb
+        };
+
+        byte key[] = "0123456789abcdef   ";  /* align */
+        byte iv[]  = "1234567890abcdef   ";  /* align */
+
+        byte cipher[AES_BLOCK_SIZE * 4];
+        byte plain [AES_BLOCK_SIZE * 4];
+
+        EVP_CIPHER_CTX_init(&ctx);
+        if (EVP_CipherInit(&ctx, EVP_aes_128_cbc(), key, iv, 1) == 0)
+            return -81;
+
+        if (EVP_Cipher(&ctx, cipher, (byte*)msg, 16) == 0)
+            return -82;
+
+        if (memcmp(cipher, verify, AES_BLOCK_SIZE))
+            return -83;
+
+        EVP_CIPHER_CTX_init(&ctx);
+        if (EVP_CipherInit(&ctx, EVP_aes_128_cbc(), key, iv, 0) == 0)
+            return -84;
+
+        if (EVP_Cipher(&ctx, plain, cipher, 16) == 0)
+            return -85;
+
+        if (memcmp(plain, msg, AES_BLOCK_SIZE))
+            return -86;
+
+
+    }  /* end evp_cipher test */
+
+    return 0;
+}
+
+#endif /* OPENSSL_EXTRA */
+
+
+#ifndef NO_PWDBASED
+
+int pkcs12_test(void)
+{
+    const byte passwd[] = { 0x00, 0x73, 0x00, 0x6d, 0x00, 0x65, 0x00, 0x67,
+                            0x00, 0x00 }; 
+    const byte salt[] =   { 0x0a, 0x58, 0xCF, 0x64, 0x53, 0x0d, 0x82, 0x3f };
+
+    const byte passwd2[] = { 0x00, 0x71, 0x00, 0x75, 0x00, 0x65, 0x00, 0x65,
+                             0x00, 0x67, 0x00, 0x00 }; 
+    const byte salt2[] =   { 0x16, 0x82, 0xC0, 0xfC, 0x5b, 0x3f, 0x7e, 0xc5 };
+    byte  derived[64];
+
+    const byte verify[] = {
+        0x8A, 0xAA, 0xE6, 0x29, 0x7B, 0x6C, 0xB0, 0x46,
+        0x42, 0xAB, 0x5B, 0x07, 0x78, 0x51, 0x28, 0x4E,
+        0xB7, 0x12, 0x8F, 0x1A, 0x2A, 0x7F, 0xBC, 0xA3
+    };
+
+    const byte verify2[] = {
+        0x48, 0x3D, 0xD6, 0xE9, 0x19, 0xD7, 0xDE, 0x2E,
+        0x8E, 0x64, 0x8B, 0xA8, 0xF8, 0x62, 0xF3, 0xFB,
+        0xFB, 0xDC, 0x2B, 0xCB, 0x2C, 0x02, 0x95, 0x7F
+    };
+
+    int id         =  1;
+    int kLen       = 24;
+    int iterations =  1;
+    int ret = PKCS12_PBKDF(derived, passwd, sizeof(passwd), salt, 8, iterations,
+                           kLen, SHA, id);
+
+    if (ret < 0)
+        return -103;
+
+    if ( (ret = memcmp(derived, verify, kLen)) != 0)
+        return -104;
+
+    iterations = 1000;
+    ret = PKCS12_PBKDF(derived, passwd2, sizeof(passwd2), salt2, 8, iterations, 
+                       kLen, SHA, id);
+    if (ret < 0)
+        return -105;
+
+    if ( (ret = memcmp(derived, verify2, 24)) != 0)
+        return -106;
+
+    return 0;
+}
+
+
+int pbkdf2_test(void)
+{
+    char passwd[] = "password";
+    const byte salt[] = { 0x78, 0x57, 0x8E, 0x5a, 0x5d, 0x63, 0xcb, 0x06 };
+    int   iterations = 2048;
+    int   kLen = 24;
+    byte  derived[64];
+
+    const byte verify[] = {
+        0xBF, 0xDE, 0x6B, 0xE9, 0x4D, 0xF7, 0xE1, 0x1D, 0xD4, 0x09, 0xBC, 0xE2,
+        0x0A, 0x02, 0x55, 0xEC, 0x32, 0x7C, 0xB9, 0x36, 0xFF, 0xE9, 0x36, 0x43
+
+    };
+
+    PBKDF2(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations,
+           kLen, SHA);
+
+    if (memcmp(derived, verify, sizeof(verify)) != 0)
+        return -102;
+
+    return 0;
+}
+
+
+int pbkdf1_test(void)
+{
+    char passwd[] = "password";
+    const byte salt[] = { 0x78, 0x57, 0x8E, 0x5a, 0x5d, 0x63, 0xcb, 0x06 };
+    int   iterations = 1000;
+    int   kLen = 16;
+    byte  derived[16];
+
+    const byte verify[] = {
+        0xDC, 0x19, 0x84, 0x7E, 0x05, 0xC6, 0x4D, 0x2F, 0xAF, 0x10, 0xEB, 0xFB,
+        0x4A, 0x3D, 0x2A, 0x20
+    };
+
+    PBKDF1(derived, (byte*)passwd, (int)strlen(passwd), salt, 8, iterations,
+           kLen, SHA);
+
+    if (memcmp(derived, verify, sizeof(verify)) != 0)
+        return -101;
+
+    return 0;
+}
+
+
+int pwdbased_test(void)
+{
+   int ret =  pbkdf1_test();
+   ret += pbkdf2_test();
+
+   return ret + pkcs12_test();
+}
+
+#endif /* NO_PWDBASED */
+
+
+#ifdef HAVE_ECC
+
+int ecc_test(void)
+{
+    RNG     rng;
+    byte    sharedA[1024];
+    byte    sharedB[1024];
+    byte    sig[1024];
+    byte    digest[20];
+    byte    exportBuf[1024];
+    word32  x, y;
+    int     i, verify, ret;
+    ecc_key userA, userB, pubKey;
+
+    ret = InitRng(&rng);
+    if (ret != 0)
+        return -1001;
+
+    ecc_init(&userA);
+    ecc_init(&userB);
+    ecc_init(&pubKey);
+
+    ret = ecc_make_key(&rng, 32, &userA);
+    ret = ecc_make_key(&rng, 32, &userB);
+
+    if (ret != 0)
+        return -1002;
+
+    x = sizeof(sharedA);
+    ret = ecc_shared_secret(&userA, &userB, sharedA, &x);
+   
+    y = sizeof(sharedB);
+    ret = ecc_shared_secret(&userB, &userA, sharedB, &y);
+    
+    if (ret != 0)
+        return -1003;
+
+    if (y != x)
+        return -1004;
+
+    if (memcmp(sharedA, sharedB, x))
+        return -1005;
+
+    x = sizeof(exportBuf);
+    ret = ecc_export_x963(&userA, exportBuf, &x);
+    if (ret != 0)
+        return -1006;
+
+    ret = ecc_import_x963(exportBuf, x, &pubKey);
+
+    if (ret != 0) 
+        return -1007;
+
+    y = sizeof(sharedB);
+    ret = ecc_shared_secret(&userB, &pubKey, sharedB, &y);
+   
+    if (ret != 0)
+        return -1008;
+
+    if (memcmp(sharedA, sharedB, y))
+        return -1010;
+
+    /* test DSA sign hash */
+    for (i = 0; i < (int)sizeof(digest); i++)
+        digest[i] = i;
+
+    x = sizeof(sig);
+    ret = ecc_sign_hash(digest, sizeof(digest), sig, &x, &rng, &userA);
+    
+    verify = 0;
+    ret = ecc_verify_hash(sig, x, digest, sizeof(digest), &verify, &userA);
+
+    if (ret != 0)
+        return -1011;
+
+    if (verify != 1)
+        return -1012;
+
+    ecc_free(&pubKey);
+    ecc_free(&userB);
+    ecc_free(&userA);
+
+    return 0;
+}
+
+#endif /* HAVE_ECC */
+
+#ifdef HAVE_LIBZ
+
+const byte sample_text[] =
+    "Biodiesel cupidatat marfa, cliche aute put a bird on it incididunt elit\n"
+    "polaroid. Sunt tattooed bespoke reprehenderit. Sint twee organic id\n"
+    "marfa. Commodo veniam ad esse gastropub. 3 wolf moon sartorial vero,\n"
+    "plaid delectus biodiesel squid +1 vice. Post-ironic keffiyeh leggings\n"
+    "selfies cray fap hoodie, forage anim. Carles cupidatat shoreditch, VHS\n"
+    "small batch meggings kogi dolore food truck bespoke gastropub.\n"
+    "\n"
+    "Terry richardson adipisicing actually typewriter tumblr, twee whatever\n"
+    "four loko you probably haven't heard of them high life. Messenger bag\n"
+    "whatever tattooed deep v mlkshk. Brooklyn pinterest assumenda chillwave\n"
+    "et, banksy ullamco messenger bag umami pariatur direct trade forage.\n"
+    "Typewriter culpa try-hard, pariatur sint brooklyn meggings. Gentrify\n"
+    "food truck next level, tousled irony non semiotics PBR ethical anim cred\n"
+    "readymade. Mumblecore brunch lomo odd future, portland organic terry\n"
+    "richardson elit leggings adipisicing ennui raw denim banjo hella. Godard\n"
+    "mixtape polaroid, pork belly readymade organic cray typewriter helvetica\n"
+    "four loko whatever street art yr farm-to-table.\n"
+    "\n"
+    "Vinyl keytar vice tofu. Locavore you probably haven't heard of them pug\n"
+    "pickled, hella tonx labore truffaut DIY mlkshk elit cosby sweater sint\n"
+    "et mumblecore. Elit swag semiotics, reprehenderit DIY sartorial nisi ugh\n"
+    "nesciunt pug pork belly wayfarers selfies delectus. Ethical hoodie\n"
+    "seitan fingerstache kale chips. Terry richardson artisan williamsburg,\n"
+    "eiusmod fanny pack irony tonx ennui lo-fi incididunt tofu YOLO\n"
+    "readymade. 8-bit sed ethnic beard officia. Pour-over iphone DIY butcher,\n"
+    "ethnic art party qui letterpress nisi proident jean shorts mlkshk\n"
+    "locavore.\n"
+    "\n"
+    "Narwhal flexitarian letterpress, do gluten-free voluptate next level\n"
+    "banh mi tonx incididunt carles DIY. Odd future nulla 8-bit beard ut\n"
+    "cillum pickled velit, YOLO officia you probably haven't heard of them\n"
+    "trust fund gastropub. Nisi adipisicing tattooed, Austin mlkshk 90's\n"
+    "small batch american apparel. Put a bird on it cosby sweater before they\n"
+    "sold out pork belly kogi hella. Street art mollit sustainable polaroid,\n"
+    "DIY ethnic ea pug beard dreamcatcher cosby sweater magna scenester nisi.\n"
+    "Sed pork belly skateboard mollit, labore proident eiusmod. Sriracha\n"
+    "excepteur cosby sweater, anim deserunt laborum eu aliquip ethical et\n"
+    "neutra PBR selvage.\n"
+    "\n"
+    "Raw denim pork belly truffaut, irony plaid sustainable put a bird on it\n"
+    "next level jean shorts exercitation. Hashtag keytar whatever, nihil\n"
+    "authentic aliquip disrupt laborum. Tattooed selfies deserunt trust fund\n"
+    "wayfarers. 3 wolf moon synth church-key sartorial, gastropub leggings\n"
+    "tattooed. Labore high life commodo, meggings raw denim fingerstache pug\n"
+    "trust fund leggings seitan forage. Nostrud ullamco duis, reprehenderit\n"
+    "incididunt flannel sustainable helvetica pork belly pug banksy you\n"
+    "probably haven't heard of them nesciunt farm-to-table. Disrupt nostrud\n"
+    "mollit magna, sriracha sartorial helvetica.\n"
+    "\n"
+    "Nulla kogi reprehenderit, skateboard sustainable duis adipisicing viral\n"
+    "ad fanny pack salvia. Fanny pack trust fund you probably haven't heard\n"
+    "of them YOLO vice nihil. Keffiyeh cray lo-fi pinterest cardigan aliqua,\n"
+    "reprehenderit aute. Culpa tousled williamsburg, marfa lomo actually anim\n"
+    "skateboard. Iphone aliqua ugh, semiotics pariatur vero readymade\n"
+    "organic. Marfa squid nulla, in laborum disrupt laboris irure gastropub.\n"
+    "Veniam sunt food truck leggings, sint vinyl fap.\n"
+    "\n"
+    "Hella dolore pork belly, truffaut carles you probably haven't heard of\n"
+    "them PBR helvetica in sapiente. Fashion axe ugh bushwick american\n"
+    "apparel. Fingerstache sed iphone, jean shorts blue bottle nisi bushwick\n"
+    "flexitarian officia veniam plaid bespoke fap YOLO lo-fi. Blog\n"
+    "letterpress mumblecore, food truck id cray brooklyn cillum ad sed.\n"
+    "Assumenda chambray wayfarers vinyl mixtape sustainable. VHS vinyl\n"
+    "delectus, culpa williamsburg polaroid cliche swag church-key synth kogi\n"
+    "magna pop-up literally. Swag thundercats ennui shoreditch vegan\n"
+    "pitchfork neutra truffaut etsy, sed single-origin coffee craft beer.\n"
+    "\n"
+    "Odio letterpress brooklyn elit. Nulla single-origin coffee in occaecat\n"
+    "meggings. Irony meggings 8-bit, chillwave lo-fi adipisicing cred\n"
+    "dreamcatcher veniam. Put a bird on it irony umami, trust fund bushwick\n"
+    "locavore kale chips. Sriracha swag thundercats, chillwave disrupt\n"
+    "tousled beard mollit mustache leggings portland next level. Nihil esse\n"
+    "est, skateboard art party etsy thundercats sed dreamcatcher ut iphone\n"
+    "swag consectetur et. Irure skateboard banjo, nulla deserunt messenger\n"
+    "bag dolor terry richardson sapiente.\n";
+
+
+int compress_test(void)
+{
+    int ret = 0;
+    word32 dSz = sizeof(sample_text);
+    word32 cSz = (dSz + (word32)(dSz * 0.001) + 12);
+    byte *c = NULL;
+    byte *d = NULL;
+
+    c = calloc(cSz, sizeof(byte));
+    d = calloc(dSz, sizeof(byte));
+
+    if (c == NULL || d == NULL)
+        ret = -300;
+
+    if (ret == 0 && (ret = Compress(c, cSz, sample_text, dSz, 0)) < 0)
+        ret = -301;
+
+    if (ret > 0) {
+        cSz = (word32)ret;
+        ret = 0;
+    }
+
+    if (ret == 0 && DeCompress(d, dSz, c, cSz) != (int)dSz)
+        ret = -302;
+
+    if (ret == 0 && memcmp(d, sample_text, dSz))
+        ret = -303;
+    
+    if (c) free(c);
+    if (d) free(d);
+
+    return ret;
+}
+
+#endif /* HAVE_LIBZ */
+
+#endif /* NO_CRYPT_TEST */
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt b/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt
new file mode 100644
index 000000000..2656e4033
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/Abstract.txt
@@ -0,0 +1,22 @@
+This program is echo client with CyaSSL/wolfCrypt library.
+
+In order to run this program, 
+Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+Set config-EchoClient.h configuration file for the Callee IP or Port number.
+
+For further configuration, refer config-Crypt.h and config-CyaSSL.h.
+
+When testing this client, it is recommended to test against one of the standard 
+CyaSSL example applications running on a desktop machine.  The standard CyaSSL 
+example applications are located in the CyaSSL root directory under the 
+/examples directory.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com
\ No newline at end of file
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx
new file mode 100644
index 000000000..7e61facf5
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvoptx
@@ -0,0 +1,1422 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    EchoClient
+    0x4
+    ARM-ADS
+    
+      120000000
+      
+        1
+        1
+        0
+        1
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\Object\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        SARMCM3.DLL
+        -REMAP -MPU
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
+        -REMAP -MPU
+        TCM.DLL
+        -pCM3
+      
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        0
+        8
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        .\STM32_SWO.ini
+        BIN\ULP2CM3.DLL
+      
+      
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          ULP2CM3
+          -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)
+        
+        
+          0
+          DLGUARM
+          
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+        
+      
+      
+      
+        
+          1
+          8
+          ((func_args*)args)->signal->port
+        
+      
+      
+        
+          2
+          8
+          0x8004dc8
+        
+      
+      
+        0
+      
+      
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source
+    1
+    0
+    0
+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\main.c
+      main.c
+      0
+      0
+    
+    
+      1
+      2
+      1
+      0
+      0
+      28
+      0
+      0
+      0
+      0
+      .\echoclient.c
+      echoclient.c
+      0
+      0
+    
+  
+
+  
+    Configuration
+    1
+    0
+    0
+    0
+    
+      2
+      3
+      5
+      0
+      0
+      24
+      0
+      0
+      0
+      0
+      .\config-EchoClient.h
+      config-EchoClient.h
+      0
+      0
+    
+    
+      2
+      4
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      0
+      0
+    
+    
+      2
+      5
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      0
+      0
+    
+  
+
+  
+    Dcumentation
+    1
+    0
+    0
+    0
+    
+      3
+      6
+      5
+      0
+      0
+      0
+      0
+      1
+      1
+      0
+      .\Abstract.txt
+      Abstract.txt
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
+    0
+    0
+    1
+    
+      4
+      7
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+      RTX_CM3.lib
+      1
+      0
+    
+    
+      4
+      8
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\CMSIS\RTX_Conf_CM.c
+      RTX_Conf_CM.c
+      1
+      0
+    
+  
+
+  
+    ::Device
+    0
+    0
+    0
+    1
+    
+      5
+      9
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c
+      DMA_STM32F2xx.c
+      1
+      0
+    
+    
+      5
+      10
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+      GPIO_STM32F2xx.c
+      1
+      0
+    
+    
+      5
+      11
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Device\STM32F207IG\RTE_Device.h
+      RTE_Device.h
+      1
+      0
+    
+    
+      5
+      12
+      2
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Device\STM32F207IG\startup_stm32f2xx.s
+      startup_stm32f2xx.s
+      1
+      0
+    
+    
+      5
+      13
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Device\STM32F207IG\system_stm32f2xx.c
+      system_stm32f2xx.c
+      1
+      0
+    
+  
+
+  
+    ::Drivers
+    0
+    0
+    0
+    1
+    
+      6
+      14
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+      PHY_ST802RT1.c
+      1
+      0
+    
+    
+      6
+      15
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c
+      EMAC_STM32F2xx.c
+      1
+      0
+    
+    
+      6
+      16
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c
+      MCI_STM32F2xx.c
+      1
+      0
+    
+  
+
+  
+    ::File System
+    0
+    0
+    0
+    1
+    
+      7
+      17
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib
+      FS_LFN_CM3_L.lib
+      1
+      0
+    
+    
+      7
+      18
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\File_System\FS_Config.c
+      FS_Config.c
+      1
+      0
+    
+    
+      7
+      19
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\File_System\FS_Config_MC_0.h
+      FS_Config_MC_0.h
+      1
+      0
+    
+  
+
+  
+    ::Network
+    0
+    0
+    0
+    1
+    
+      8
+      20
+      4
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib
+      Net_Dbg_CM3_L.lib
+      1
+      0
+    
+    
+      8
+      21
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config.c
+      Net_Config.c
+      1
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+    
+    
+      8
+      22
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config_BSD.h
+      Net_Config_BSD.h
+      1
+      0
+    
+    
+      8
+      23
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config_DNS_Client.h
+      Net_Config_DNS_Client.h
+      1
+      0
+    
+    
+      8
+      24
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config_ETH_0.h
+      Net_Config_ETH_0.h
+      1
+      0
+    
+    
+      8
+      25
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config_TCP.h
+      Net_Config_TCP.h
+      1
+      0
+    
+    
+      8
+      26
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config_UDP.h
+      Net_Config_UDP.h
+      1
+      0
+    
+    
+      8
+      27
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\Network\Net_Debug.c
+      Net_Debug.c
+      1
+      0
+    
+  
+
+  
+    ::wolfSSL
+    0
+    0
+    0
+    1
+    
+      9
+      28
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+      cyassl_MDK_ARM.c
+      1
+      0
+    
+    
+      9
+      29
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+      time-STM32F2xx.c
+      1
+      0
+    
+    
+      9
+      30
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c
+      aes.c
+      1
+      0
+    
+    
+      9
+      31
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c
+      arc4.c
+      1
+      0
+    
+    
+      9
+      32
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+      asm.c
+      1
+      0
+    
+    
+      9
+      33
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+      asn.c
+      1
+      0
+    
+    
+      9
+      34
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+      blake2b.c
+      1
+      0
+    
+    
+      9
+      35
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c
+      camellia.c
+      1
+      0
+    
+    
+      9
+      36
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+      coding.c
+      1
+      0
+    
+    
+      9
+      37
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c
+      compress.c
+      1
+      0
+    
+    
+      9
+      38
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
+      des3.c
+      1
+      0
+    
+    
+      9
+      39
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+      dh.c
+      1
+      0
+    
+    
+      9
+      40
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+      dsa.c
+      1
+      0
+    
+    
+      9
+      41
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+      ecc.c
+      1
+      0
+    
+    
+      9
+      42
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+      ecc_fp.c
+      1
+      0
+    
+    
+      9
+      43
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+      error.c
+      1
+      0
+    
+    
+      9
+      44
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+      hc128.c
+      1
+      0
+    
+    
+      9
+      45
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+      hmac.c
+      1
+      0
+    
+    
+      9
+      46
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+      integer.c
+      1
+      0
+    
+    
+      9
+      47
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+      logging.c
+      1
+      0
+    
+    
+      9
+      48
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+      md2.c
+      1
+      0
+    
+    
+      9
+      49
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+      md4.c
+      1
+      0
+    
+    
+      9
+      50
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+      md5.c
+      1
+      0
+    
+    
+      9
+      51
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+      memory.c
+      1
+      0
+    
+    
+      9
+      52
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+      misc.c
+      1
+      0
+    
+    
+      9
+      53
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+      pwdbased.c
+      1
+      0
+    
+    
+      9
+      54
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+      rabbit.c
+      1
+      0
+    
+    
+      9
+      55
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+      random.c
+      1
+      0
+    
+    
+      9
+      56
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+      ripemd.c
+      1
+      0
+    
+    
+      9
+      57
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+      rsa.c
+      1
+      0
+    
+    
+      9
+      58
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+      sha.c
+      1
+      0
+    
+    
+      9
+      59
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+      sha256.c
+      1
+      0
+    
+    
+      9
+      60
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+      sha512.c
+      1
+      0
+    
+    
+      9
+      61
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+      tfm.c
+      1
+      0
+    
+    
+      9
+      62
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+      crl.c
+      1
+      0
+    
+    
+      9
+      63
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+      internal.c
+      1
+      0
+    
+    
+      9
+      64
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+      io.c
+      1
+      0
+    
+    
+      9
+      65
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+      keys.c
+      1
+      0
+    
+    
+      9
+      66
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+      ocsp.c
+      1
+      0
+    
+    
+      9
+      67
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+      sniffer.c
+      1
+      0
+    
+    
+      9
+      68
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+      ssl.c
+      1
+      0
+    
+    
+      9
+      69
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+      tls.c
+      1
+      0
+    
+    
+      9
+      70
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      1
+      0
+    
+    
+      9
+      71
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      1
+      0
+    
+    
+      9
+      72
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config.h
+      config.h
+      1
+      0
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx
new file mode 100644
index 000000000..7b4076c60
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/EchoClient.uvprojx
@@ -0,0 +1,1106 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      EchoClient
+      0x4
+      ARM-ADS
+      
+        
+          STM32F207IG
+          STMicroelectronics
+          IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+          0
+          $$Device:STM32F207IG$Device\Include\stm32f2xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F207IG$SVD\STM32F20x.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Object\
+          EchoClient
+          1
+          0
+          0
+          1
+          1
+          .\Object\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          -REMAP -MPU
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          8
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            .\STM32_SWO.ini
+            BIN\ULP2CM3.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4100
+          
+          1
+          BIN\ULP2CM3.DLL
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M3"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              HAVE_CONFIG_H  MDK_CONF_EchoClient CYASSL_STM32F2xx
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source
+          
+            
+              main.c
+              1
+              .\main.c
+            
+            
+              echoclient.c
+              1
+              .\echoclient.c
+            
+          
+        
+        
+          Configuration
+          
+            
+              config-EchoClient.h
+              5
+              .\config-EchoClient.h
+            
+            
+              config-CyaSSL.h
+              5
+              .\RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config-Crypt.h
+              5
+              .\RTE\wolfSSL\config-Crypt.h
+            
+          
+        
+        
+          Dcumentation
+          
+            
+              Abstract.txt
+              5
+              .\Abstract.txt
+            
+          
+        
+        
+          ::CMSIS
+          
+            
+              RTX_CM3.lib
+              4
+              C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+            
+            
+              RTX_Conf_CM.c
+              1
+              RTE\CMSIS\RTX_Conf_CM.c
+            
+          
+        
+        
+          ::Device
+          
+            
+              DMA_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c
+            
+            
+              GPIO_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+            
+            
+              RTE_Device.h
+              5
+              RTE\Device\STM32F207IG\RTE_Device.h
+            
+            
+              startup_stm32f2xx.s
+              2
+              RTE\Device\STM32F207IG\startup_stm32f2xx.s
+            
+            
+              system_stm32f2xx.c
+              1
+              RTE\Device\STM32F207IG\system_stm32f2xx.c
+            
+          
+        
+        
+          ::Drivers
+          
+            
+              PHY_ST802RT1.c
+              1
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+            
+            
+              EMAC_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c
+            
+            
+              MCI_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c
+            
+          
+        
+        
+          ::File System
+          
+            
+              FS_LFN_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib
+            
+            
+              FS_Config.c
+              1
+              RTE\File_System\FS_Config.c
+            
+            
+              FS_Config_MC_0.h
+              5
+              RTE\File_System\FS_Config_MC_0.h
+            
+          
+        
+        
+          ::Network
+          
+            
+              Net_Dbg_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib
+            
+            
+              Net_Config.c
+              1
+              RTE\Network\Net_Config.c
+            
+            
+              Net_Config_BSD.h
+              5
+              RTE\Network\Net_Config_BSD.h
+            
+            
+              Net_Config_DNS_Client.h
+              5
+              RTE\Network\Net_Config_DNS_Client.h
+            
+            
+              Net_Config_ETH_0.h
+              5
+              RTE\Network\Net_Config_ETH_0.h
+            
+            
+              Net_Config_TCP.h
+              5
+              RTE\Network\Net_Config_TCP.h
+            
+            
+              Net_Config_UDP.h
+              5
+              RTE\Network\Net_Config_UDP.h
+            
+            
+              Net_Debug.c
+              1
+              RTE\Network\Net_Debug.c
+            
+          
+        
+        
+          ::wolfSSL
+          
+            
+              cyassl_MDK_ARM.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+            
+            
+              time-STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+            
+            
+              aes.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c
+            
+            
+              arc4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c
+            
+            
+              asm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+            
+            
+              asn.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+            
+            
+              blake2b.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+            
+            
+              camellia.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c
+            
+            
+              coding.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+            
+            
+              compress.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c
+            
+            
+              des3.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
+            
+            
+              dh.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+            
+            
+              dsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+            
+            
+              ecc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+            
+            
+              ecc_fp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+            
+            
+              error.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+            
+            
+              hc128.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+            
+            
+              hmac.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+            
+            
+              integer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+            
+            
+              logging.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+            
+            
+              md2.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+            
+            
+              md4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+            
+            
+              md5.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+            
+            
+              memory.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+            
+            
+              misc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+            
+            
+              pwdbased.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+            
+            
+              rabbit.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+            
+            
+              random.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+            
+            
+              ripemd.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+            
+            
+              rsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+            
+            
+              sha.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+            
+            
+              sha256.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+            
+            
+              sha512.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+            
+            
+              tfm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+            
+            
+              crl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+            
+            
+              internal.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+            
+            
+              io.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+            
+            
+              keys.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+            
+            
+              ocsp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+            
+            
+              sniffer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+            
+            
+              ssl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+            
+            
+              tls.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+            
+            
+              config-Crypt.h
+              5
+              RTE\wolfSSL\config-Crypt.h
+            
+            
+              config-CyaSSL.h
+              5
+              RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config.h
+              5
+              RTE\wolfSSL\config.h
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        RTE\CMSIS\RTX_Conf_CM.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\RTE_Device.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\startup_stm32f2xx.s
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\system_stm32f2xx.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config_MC_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_BSD.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_DNS_Client.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_ETH_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_TCP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_UDP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Debug.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Other\config-Crypt.h
+        
+        
+        
+      
+      
+        RTE\Other\config-CyaSSL.h
+        
+        
+        
+      
+      
+        RTE\Other\config-RTX-TCP-FS.h
+        
+        
+        
+      
+      
+        RTE\Other\config.h
+        
+        
+        
+      
+      
+        RTE\wolfSSL\config-Crypt.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config-CyaSSL.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config.h
+        
+        
+        
+          
+        
+      
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c
new file mode 100644
index 000000000..54b3e0bfc
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/CMSIS/RTX_Conf_CM.c
@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// Thread Configuration
+// =======================
+//
+//   Number of concurrent running threads <0-250>
+//    Defines max. number of threads that will run at the same time.
+//    Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     5
+#endif
+
+//   Default Thread stack size [bytes] <64-4096:8><#/4>
+//    Defines default stack size for threads with osThreadDef stacksz = 0
+//    Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     250
+#endif
+
+//   Main Thread stack size [bytes] <64-20000:8><#/4>
+//    Defines stack size for main thread.
+//    Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 2000
+#endif
+
+//   Number of threads with user-provided stack size <0-250>
+//    Defines the number of threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     2
+#endif
+
+//   Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4>
+//    Defines the combined stack size for threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 2500
+#endif
+
+// Check for stack overflow
+//  Includes the stack checking code for stack overflow.
+//  Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+//  Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// 
+
+// RTX Kernel Timer Tick Configuration
+// ======================================
+//  Use Cortex-M SysTick timer as RTX Kernel Timer
+//  Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   Timer clock value [Hz] <1-1000000000>
+//    Defines the timer clock value.
+//    Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   Timer tick value [us] <1-1000000>
+//    Defines the timer tick value.
+//    Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// 
+
+// System Configuration
+// =======================
+//
+// Round-Robin Thread switching
+// ===============================
+//
+//  Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   Round-Robin Timeout [ticks] <1-1000>
+//    Defines how long a thread will execute before a thread switch.
+//    Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// 
+
+// User Timers
+// ==============
+//    Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//    Defines priority for Timer Thread
+//    Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   Timer Thread stack size [bytes] <64-64000:8><#/4>
+//    Defines stack size for Timer thread.
+//    Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   Timer Callback Queue size <1-32>
+//    Number of concurrent active timer callback functions.
+//    Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// 
+
+//   ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//    ISR functions store requests to this buffer,
+//    when they are called from the interrupt handler.
+//    Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// 
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/RTE_Device.h
new file mode 100644
index 000000000..4a09246f3
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/RTE_Device.h
@@ -0,0 +1,3127 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *  
+ * $Date:        27. June 2013
+ * $Revision:    V1.01
+ *  
+ * Project:      RTE Device Configuration for ST STM32F2xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  (num == 7) ? GPIOH : \
+  (num == 8) ? GPIOI : \
+  NULL)
+
+
+//  Clock Configuration
+//    High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         16000000
+//    High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//    System Clock <1-999999999>
+#define RTE_SYSCLK                      120000000
+//    AHB Clock    <1-999999999>
+#define RTE_HCLK                        120000000
+//    APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       30000000
+//    APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       60000000
+//       48MHz Clock
+#define RTE_PLL48CK                     48000000
+// 
+
+
+//  USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1]
+//  Configuration settings for Driver_UART1 in component ::Drivers:UART
+#define RTE_USART1                      0
+
+//    USART1_TX Pin <0=>PA9 <1=>PB6
+#define RTE_USART1_TX_ID                0
+#if    (RTE_USART1_TX_ID == 0)
+#define RTE_USART1_TX_PORT              GPIOA
+#define RTE_USART1_TX_BIT               9
+#elif  (RTE_USART1_TX_ID == 1)
+#define RTE_USART1_TX_PORT              GPIOB
+#define RTE_USART1_TX_BIT               6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//    USART1_RX Pin <0=>PA10 <1=>PB7
+#define RTE_USART1_RX_ID                0
+#if    (RTE_USART1_RX_ID == 0)
+#define RTE_USART1_RX_PORT              GPIOA
+#define RTE_USART1_RX_BIT               10
+#elif  (RTE_USART1_RX_ID == 1)
+#define RTE_USART1_RX_PORT              GPIOB
+#define RTE_USART1_RX_BIT               7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART1_CK Pin <0=>PA8
+//     
+#define RTE_USART1_CK                   0
+#define RTE_USART1_CK_ID                0
+#if    (RTE_USART1_CK_ID == 0)
+#define RTE_USART1_CK_PORT              GPIOA
+#define RTE_USART1_CK_BIT               8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART1_CTS Pin <0=>PA11
+//        USART1_RTS Pin <0=>PA12
+//        Manual CTS/RTS
+//     
+#define RTE_USART1_HW_FLOW              0
+#define RTE_USART1_CTS_ID               0
+#define RTE_USART1_RTS_ID               0
+#define RTE_USART1_MANUAL_FLOW          0
+#if    (RTE_USART1_CTS_ID == 0)
+#define RTE_USART1_CTS_PORT             GPIOA
+#define RTE_USART1_CTS_BIT              11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART1_RTS_ID == 0)
+#define RTE_USART1_RTS_PORT             GPIOA
+#define RTE_USART1_RTS_BIT              12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <2=>2 <5=>5
+//       Selects DMA Stream (only Stream 2 or 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_RX_DMA               1
+#define RTE_USART1_RX_DMA_NUMBER        2
+#define RTE_USART1_RX_DMA_STREAM        2
+#define RTE_USART1_RX_DMA_CHANNEL       4
+#define RTE_USART1_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_TX_DMA               1
+#define RTE_USART1_TX_DMA_NUMBER        2
+#define RTE_USART1_TX_DMA_STREAM        7
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2]
+//  Configuration settings for Driver_UART2 in component ::Drivers:UART
+#define RTE_USART2                      0
+
+//    USART2_TX Pin <0=>PA2 <1=>PD5
+#define RTE_USART2_TX_ID                0
+#if    (RTE_USART2_TX_ID == 0)
+#define RTE_USART2_TX_PORT              GPIOA
+#define RTE_USART2_TX_BIT               2
+#elif  (RTE_USART2_TX_ID == 1)
+#define RTE_USART2_TX_PORT              GPIOD
+#define RTE_USART2_TX_BIT               5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//    USART2_RX Pin <0=>PA3 <1=>PD6
+#define RTE_USART2_RX_ID                0
+#if    (RTE_USART2_RX_ID == 0)
+#define RTE_USART2_RX_PORT              GPIOA
+#define RTE_USART2_RX_BIT               3
+#elif  (RTE_USART2_RX_ID == 1)
+#define RTE_USART2_RX_PORT              GPIOD
+#define RTE_USART2_RX_BIT               6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART2_CK Pin <0=>PA4 <1=>PD7
+//     
+#define RTE_USART2_CK                   0
+#define RTE_USART2_CK_ID                0
+#if    (RTE_USART2_CK_ID == 0)
+#define RTE_USART2_CK_PORT              GPIOA
+#define RTE_USART2_CK_BIT               4
+#elif  (RTE_USART2_CK_ID == 1)
+#define RTE_USART2_CK_PORT              GPIOD
+#define RTE_USART2_CK_BIT               7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART2_CTS Pin <0=>PA0 <1=>PD3
+//        USART2_RTS Pin <0=>PA1 <1=>PD4
+//        Manual CTS/RTS
+//     
+#define RTE_USART2_HW_FLOW              0
+#define RTE_USART2_CTS_ID               0
+#define RTE_USART2_RTS_ID               0
+#define RTE_USART2_MANUAL_FLOW          0
+#if    (RTE_USART2_CTS_ID == 0)
+#define RTE_USART2_CTS_PORT             GPIOA
+#define RTE_USART2_CTS_BIT              0
+#elif  (RTE_USART2_CTS_ID == 1)
+#define RTE_USART2_CTS_PORT             GPIOD
+#define RTE_USART2_CTS_BIT              3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART2_RTS_ID == 0)
+#define RTE_USART2_RTS_PORT             GPIOA
+#define RTE_USART2_RTS_BIT              1
+#elif  (RTE_USART2_RTS_ID == 1)
+#define RTE_USART2_RTS_PORT             GPIOD
+#define RTE_USART2_RTS_BIT              4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5
+//       Selects DMA Stream (only Stream 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_RX_DMA               1
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_STREAM        5
+#define RTE_USART2_RX_DMA_CHANNEL       4
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6
+//       Selects DMA Stream (only Stream 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_TX_DMA               1
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_STREAM        6
+#define RTE_USART2_TX_DMA_CHANNEL       4
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3]
+//  Configuration settings for Driver_UART3 in component ::Drivers:UART
+#define RTE_USART3                      0
+
+//    USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8
+#define RTE_USART3_TX_ID                0
+#if    (RTE_USART3_TX_ID == 0)
+#define RTE_USART3_TX_PORT              GPIOB
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 1)
+#define RTE_USART3_TX_PORT              GPIOC
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 2)
+#define RTE_USART3_TX_PORT              GPIOD
+#define RTE_USART3_TX_BIT               8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//    USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9
+#define RTE_USART3_RX_ID                0
+#if    (RTE_USART3_RX_ID == 0)
+#define RTE_USART3_RX_PORT              GPIOB
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 1)
+#define RTE_USART3_RX_PORT              GPIOC
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 2)
+#define RTE_USART3_RX_PORT              GPIOD
+#define RTE_USART3_RX_BIT               9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10
+//     
+#define RTE_USART3_CK                   0
+#define RTE_USART3_CK_ID                0
+#if    (RTE_USART3_CK_ID == 0)
+#define RTE_USART3_CK_PORT              GPIOB
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 1)
+#define RTE_USART3_CK_PORT              GPIOC
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 2)
+#define RTE_USART3_CK_PORT              GPIOD
+#define RTE_USART3_CK_BIT               10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART3_CTS Pin <0=>PB13 <1=>PD11
+//        USART3_RTS Pin <0=>PB14 <1=>PD12
+//        Manual CTS/RTS
+//     
+#define RTE_USART3_HW_FLOW              0
+#define RTE_USART3_CTS_ID               0
+#define RTE_USART3_RTS_ID               0
+#define RTE_USART3_MANUAL_FLOW          0
+#if    (RTE_USART3_CTS_ID == 0)
+#define RTE_USART3_CTS_PORT             GPIOB
+#define RTE_USART3_CTS_BIT              13
+#elif  (RTE_USART3_CTS_ID == 1)
+#define RTE_USART3_CTS_PORT             GPIOD
+#define RTE_USART3_CTS_BIT              11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART3_RTS_ID == 0)
+#define RTE_USART3_RTS_PORT             GPIOB
+#define RTE_USART3_RTS_BIT              14
+#elif  (RTE_USART3_RTS_ID == 1)
+#define RTE_USART3_RTS_PORT             GPIOD
+#define RTE_USART3_RTS_BIT              12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <1=>1
+//       Selects DMA Stream (only Stream 1 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_RX_DMA               1
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_STREAM        1
+#define RTE_USART3_RX_DMA_CHANNEL       4
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_TX_DMA               1
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_STREAM        3
+#define RTE_USART3_TX_DMA_CHANNEL       4
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  UART4 (Universal asynchronous receiver transmitter) [Driver_UART4]
+//  Configuration settings for Driver_UART4 in component ::Drivers:UART
+#define RTE_UART4                       0
+
+//    UART4_TX Pin <0=>PA0 <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX_PORT               GPIOA
+#define RTE_UART4_TX_BIT                0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//    UART4_RX Pin <0=>PA1 <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX_PORT               GPIOA
+#define RTE_UART4_RX_BIT                1
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_RX_DMA                1
+#define RTE_UART4_RX_DMA_NUMBER         1
+#define RTE_UART4_RX_DMA_STREAM         2
+#define RTE_UART4_RX_DMA_CHANNEL        4
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_TX_DMA                1
+#define RTE_UART4_TX_DMA_NUMBER         1
+#define RTE_UART4_TX_DMA_STREAM         4
+#define RTE_UART4_TX_DMA_CHANNEL        4
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  UART5 (Universal asynchronous receiver transmitter) [Driver_UART5]
+//  Configuration settings for Driver_UART5 in component ::Drivers:UART
+#define RTE_UART5                       0
+
+//    UART5_TX Pin <0=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//    UART5_RX Pin <0=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0
+//       Selects DMA Stream (only Stream 0 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_RX_DMA                1
+#define RTE_UART5_RX_DMA_NUMBER         1
+#define RTE_UART5_RX_DMA_STREAM         0
+#define RTE_UART5_RX_DMA_CHANNEL        4
+#define RTE_UART5_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_TX_DMA                1
+#define RTE_UART5_TX_DMA_NUMBER         1
+#define RTE_UART5_TX_DMA_STREAM         7
+#define RTE_UART5_TX_DMA_CHANNEL        4
+#define RTE_UART5_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6]
+//  Configuration settings for Driver_UART6 in component ::Drivers:UART
+#define RTE_USART6                      0
+
+//    USART6_TX Pin <0=>PC6 <1=>PG14
+#define RTE_USART6_TX_ID                0
+#if    (RTE_USART6_TX_ID == 0)
+#define RTE_USART6_TX_PORT              GPIOC
+#define RTE_USART6_TX_BIT               6
+#elif  (RTE_USART6_TX_ID == 1)
+#define RTE_USART6_TX_PORT              GPIOG
+#define RTE_USART6_TX_BIT               14
+#else
+#error "Invalid USART6_TX Pin Configuration!"
+#endif
+
+//    USART6_RX Pin <0=>PC7 <1=>PG9
+#define RTE_USART6_RX_ID                0
+#if    (RTE_USART6_RX_ID == 0)
+#define RTE_USART6_RX_PORT              GPIOC
+#define RTE_USART6_RX_BIT               7
+#elif  (RTE_USART6_RX_ID == 1)
+#define RTE_USART6_RX_PORT              GPIOG
+#define RTE_USART6_RX_BIT               9
+#else
+#error "Invalid USART6_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART6_CK Pin <0=>PC8 <1=>PG7
+//     
+#define RTE_USART6_CK                   0
+#define RTE_USART6_CK_ID                0
+#if    (RTE_USART6_CK_ID == 0)
+#define RTE_USART6_CK_PORT              GPIOC
+#define RTE_USART6_CK_BIT               8
+#elif  (RTE_USART6_CK_ID == 1)
+#define RTE_USART6_CK_PORT              GPIOG
+#define RTE_USART6_CK_BIT               7
+#else
+#error "Invalid USART6_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART6_CTS Pin <0=>PG13 <1=>PG15
+//        USART6_RTS Pin <0=>PG8  <1=>PG12
+//        Manual CTS/RTS
+//     
+#define RTE_USART6_HW_FLOW              0
+#define RTE_USART6_CTS_ID               0
+#define RTE_USART6_RTS_ID               0
+#define RTE_USART6_MANUAL_FLOW          0
+#if    (RTE_USART6_CTS_ID == 0)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              13
+#elif  (RTE_USART6_CTS_ID == 1)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              15
+#else
+#error "Invalid USART6_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART6_RTS_ID == 0)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              8
+#elif  (RTE_USART6_RTS_ID == 1)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              12
+#else
+#error "Invalid USART6_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <1=>1 <2=>2
+//       Selects DMA Stream (only Stream 1 or 2 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_RX_DMA               1
+#define RTE_USART6_RX_DMA_NUMBER        2
+#define RTE_USART6_RX_DMA_STREAM        1
+#define RTE_USART6_RX_DMA_CHANNEL       5
+#define RTE_USART6_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_TX_DMA               1
+#define RTE_USART6_TX_DMA_NUMBER        2
+#define RTE_USART6_TX_DMA_STREAM        6
+#define RTE_USART6_TX_DMA_CHANNEL       5
+#define RTE_USART6_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+//  Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1                        0
+
+//    I2C1_SCL Pin <0=>PB6 <1=>PB8
+#define RTE_I2C1_SCL_PORT_ID            0
+#if    (RTE_I2C1_SCL_PORT_ID == 0)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                6
+#elif  (RTE_I2C1_SCL_PORT_ID == 1)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//    I2C1_SDA Pin <0=>PB7 <1=>PB9
+#define RTE_I2C1_SDA_PORT_ID            0
+#if    (RTE_I2C1_SDA_PORT_ID == 0)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                7
+#elif  (RTE_I2C1_SDA_PORT_ID == 1)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                9
+#else
+#error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <5=>5
+//       Selects DMA Stream (only Stream 0 or 5 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_RX_DMA                 1
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_STREAM          0
+#define RTE_I2C1_RX_DMA_CHANNEL         1
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_TX_DMA                 1
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_STREAM          6
+#define RTE_I2C1_TX_DMA_CHANNEL         1
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+//  Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2                        0
+
+//    I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOF
+#define RTE_I2C2_SCL_BIT                1
+#elif  (RTE_I2C2_SCL_PORT_ID == 1)
+#define RTE_I2C2_SCL_PORT               GPIOH
+#define RTE_I2C2_SCL_BIT                4
+#elif  (RTE_I2C2_SCL_PORT_ID == 2)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOF
+#define RTE_I2C2_SDA_BIT                0
+#elif  (RTE_I2C2_SDA_PORT_ID == 1)
+#define RTE_I2C2_SDA_PORT               GPIOH
+#define RTE_I2C2_SDA_BIT                5
+#elif  (RTE_I2C2_SDA_PORT_ID == 2)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2 <3=>3
+//       Selects DMA Stream (only Stream 2 or 3 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 7 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_STREAM          2
+#define RTE_I2C2_RX_DMA_CHANNEL         7
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_STREAM          7
+#define RTE_I2C2_TX_DMA_CHANNEL         7
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3]
+//  Configuration settings for Driver_I2C3 in component ::Drivers:I2C
+#define RTE_I2C3                        0
+
+//    I2C3_SCL Pin <0=>PH7 <1=>PA8
+#define RTE_I2C3_SCL_PORT_ID            0
+#if    (RTE_I2C3_SCL_PORT_ID == 0)
+#define RTE_I2C3_SCL_PORT               GPIOH
+#define RTE_I2C3_SCL_BIT                7
+#elif  (RTE_I2C3_SCL_PORT_ID == 1)
+#define RTE_I2C3_SCL_PORT               GPIOA
+#define RTE_I2C3_SCL_BIT                8
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    I2C3_SDA Pin <0=>PH8 <1=>PC9
+#define RTE_I2C3_SDA_PORT_ID            0
+#if    (RTE_I2C3_SDA_PORT_ID == 0)
+#define RTE_I2C3_SDA_PORT               GPIOH
+#define RTE_I2C3_SDA_BIT                8
+#elif  (RTE_I2C3_SDA_PORT_ID == 1)
+#define RTE_I2C3_SDA_PORT               GPIOC
+#define RTE_I2C3_SDA_BIT                9
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_RX_DMA                 1
+#define RTE_I2C3_RX_DMA_NUMBER          1
+#define RTE_I2C3_RX_DMA_STREAM          2
+#define RTE_I2C3_RX_DMA_CHANNEL         3
+#define RTE_I2C3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_TX_DMA                 1
+#define RTE_I2C3_TX_DMA_NUMBER          1
+#define RTE_I2C3_TX_DMA_STREAM          4
+#define RTE_I2C3_TX_DMA_CHANNEL         3
+#define RTE_I2C3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+//  Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1                        0
+
+//    SPI1_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//    SPI1_SCK Pin <0=>PA5 <1=>PB3
+#define RTE_SPI1_SCL_PORT_ID            0
+#if    (RTE_SPI1_SCL_PORT_ID == 0)
+#define RTE_SPI1_SCL_PORT               GPIOA
+#define RTE_SPI1_SCL_BIT                5
+#elif  (RTE_SPI1_SCL_PORT_ID == 1)
+#define RTE_SPI1_SCL_PORT               GPIOB
+#define RTE_SPI1_SCL_BIT                3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//    SPI1_MISO Pin <0=>PA6 <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID           0
+#if    (RTE_SPI1_MISO_PORT_ID == 0)
+#define RTE_SPI1_MISO_PORT              GPIOA
+#define RTE_SPI1_MISO_BIT               6
+#elif  (RTE_SPI1_MISO_PORT_ID == 1)
+#define RTE_SPI1_MISO_PORT              GPIOB
+#define RTE_SPI1_MISO_BIT               4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    SPI1_MOSI Pin <0=>PA7 <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID           0
+#if    (RTE_SPI1_MOSI_PORT_ID == 0)
+#define RTE_SPI1_MOSI_PORT              GPIOA
+#define RTE_SPI1_MOSI_BIT               7
+#elif  (RTE_SPI1_MOSI_PORT_ID == 1)
+#define RTE_SPI1_MOSI_PORT              GPIOB
+#define RTE_SPI1_MOSI_BIT               5
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_RX_DMA                 1
+#define RTE_SPI1_RX_DMA_NUMBER          2
+#define RTE_SPI1_RX_DMA_STREAM          0
+#define RTE_SPI1_RX_DMA_CHANNEL         3
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <5=>5
+//       Selects DMA Stream (only Stream 3 or 5 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_TX_DMA                 1
+#define RTE_SPI1_TX_DMA_NUMBER          2
+#define RTE_SPI1_TX_DMA_STREAM          5
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+//  Configuration settings for Driver_SPI2 in component ::Drivers:SPI
+#define RTE_SPI2                        0
+
+//    SPI2_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//    SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1
+#define RTE_SPI2_SCL_PORT_ID            0
+#if    (RTE_SPI2_SCL_PORT_ID == 0)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                10
+#elif  (RTE_SPI2_SCL_PORT_ID == 1)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                13
+#elif  (RTE_SPI2_SCL_PORT_ID == 2)
+#define RTE_SPI2_SCL_PORT               GPIOI
+#define RTE_SPI2_SCL_BIT                1
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//    SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO_PORT              GPIOC
+#define RTE_SPI2_MISO_BIT               2
+#elif  (RTE_SPI2_MISO_PORT_ID == 2)
+#define RTE_SPI2_MISO_PORT              GPIOI
+#define RTE_SPI2_MISO_BIT               2
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI_PORT              GPIOC
+#define RTE_SPI2_MOSI_BIT               3
+#elif  (RTE_SPI2_MOSI_PORT_ID == 2)
+#define RTE_SPI2_MOSI_PORT              GPIOI
+#define RTE_SPI2_MOSI_BIT               3
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_RX_DMA                 1
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_STREAM          2
+#define RTE_SPI2_RX_DMA_CHANNEL         0
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_TX_DMA                 1
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_STREAM          3
+#define RTE_SPI2_TX_DMA_CHANNEL         0
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+//  Configuration settings for Driver_SPI3 in component ::Drivers:SPI
+#define RTE_SPI3                        0
+
+//    SPI3_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//    SPI3_SCK Pin <0=>PB3 <1=>PC10
+#define RTE_SPI3_SCL_PORT_ID            0
+#if    (RTE_SPI3_SCL_PORT_ID == 0)
+#define RTE_SPI3_SCL_PORT               GPIOB
+#define RTE_SPI3_SCL_BIT                3
+#elif  (RTE_SPI3_SCL_PORT_ID == 1)
+#define RTE_SPI3_SCL_PORT               GPIOC
+#define RTE_SPI3_SCL_BIT                10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//    SPI3_MISO Pin <0=>PB4 <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID           0
+#if    (RTE_SPI3_MISO_PORT_ID == 0)
+#define RTE_SPI3_MISO_PORT              GPIOB
+#define RTE_SPI3_MISO_BIT               4
+#elif  (RTE_SPI3_MISO_PORT_ID == 1)
+#define RTE_SPI3_MISO_PORT              GPIOC
+#define RTE_SPI3_MISO_BIT               11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    SPI3_MOSI Pin <0=>PB5 <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID           0
+#if    (RTE_SPI3_MOSI_PORT_ID == 0)
+#define RTE_SPI3_MOSI_PORT              GPIOB
+#define RTE_SPI3_MOSI_BIT               5
+#elif  (RTE_SPI3_MOSI_PORT_ID == 1)
+#define RTE_SPI3_MOSI_PORT              GPIOC
+#define RTE_SPI3_MOSI_BIT               12
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_RX_DMA                 1
+#define RTE_SPI3_RX_DMA_NUMBER          1
+#define RTE_SPI3_RX_DMA_STREAM          0
+#define RTE_SPI3_RX_DMA_CHANNEL         0
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5 <7=>7
+//       Selects DMA Stream (only Stream 5 or 7 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_TX_DMA                 1
+#define RTE_SPI3_TX_DMA_NUMBER          1
+#define RTE_SPI3_TX_DMA_STREAM          5
+#define RTE_SPI3_TX_DMA_CHANNEL         0
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SDIO (Secure Digital Input/Output) [Driver_MCI0]
+//  Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDIO                        1
+
+//    SDIO_CD (Card Detect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_CD_PIN                 1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(7)
+#define RTE_SDIO_CD_BIT                 15
+
+//    SDIO_WP (Write Protect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_WP_PIN                 0
+#define RTE_SDIO_WP_ACTIVE              0
+#define RTE_SDIO_WP_PORT                GPIO_PORT(7)
+#define RTE_SDIO_WP_BIT                 16
+
+//    SDIO Bus
+//      SDIO_CK Pin <0=>PC12
+#define RTE_SDIO_CK_PORT_ID             0
+#if    (RTE_SDIO_CK_PORT_ID == 0)
+#define RTE_SDIO_CK_PORT                GPIOC
+#define RTE_SDIO_CK_PIN                 12
+#else
+#error "Invalid SDIO_CK Pin Configuration!"
+#endif
+//      SDIO_CMD Pin <0=>PD2
+#define RTE_SDIO_CMD_PORT_ID            0
+#if    (RTE_SDIO_CMD_PORT_ID == 0)
+#define RTE_SDIO_CMD_PORT               GPIOD
+#define RTE_SDIO_CMD_PIN                2
+#else
+#error "Invalid SDIO_CDM Pin Configuration!"
+#endif
+//      SDIO_D0 Pin <0=>PC8
+#define RTE_SDIO_D0_PORT_ID             0
+#if    (RTE_SDIO_D0_PORT_ID == 0)
+#define RTE_SDIO_D0_PORT                GPIOC
+#define RTE_SDIO_D0_PIN                 8
+#else
+#error "Invalid SDIO_D0 Pin Configuration!"
+#endif
+//      SDIO_D1 Pin <0=>PC9
+#define RTE_SDIO_D1_PORT_ID             0
+#if    (RTE_SDIO_D1_PORT_ID == 0)
+#define RTE_SDIO_D1_PORT                GPIOC
+#define RTE_SDIO_D1_PIN                 9
+#else
+#error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//      SDIO_D2 Pin <0=>PC10
+#define RTE_SDIO_D2_PORT_ID             0
+#if    (RTE_SDIO_D2_PORT_ID == 0)
+#define RTE_SDIO_D2_PORT                GPIOC
+#define RTE_SDIO_D2_PIN                 10
+#else
+#error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//      SDIO_D3 Pin <0=>PC11
+#define RTE_SDIO_D3_PORT_ID             0
+#if    (RTE_SDIO_D3_PORT_ID == 0)
+#define RTE_SDIO_D3_PORT                GPIOC
+#define RTE_SDIO_D3_PIN                 11
+#else
+#error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//      SDIO_D4 Pin <0=>PB8
+#define RTE_SDIO_D4_PORT_ID             0
+#if    (RTE_SDIO_D4_PORT_ID == 0)
+#define RTE_SDIO_D4_PORT                GPIOB
+#define RTE_SDIO_D4_PIN                 8
+#else
+#error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//      SDIO_D5 Pin <0=>PB9
+#define RTE_SDIO_D5_PORT_ID             0
+#if    (RTE_SDIO_D5_PORT_ID == 0)
+#define RTE_SDIO_D5_PORT                GPIOB
+#define RTE_SDIO_D5_PIN                 9
+#else
+#error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//      SDIO_D6 Pin <0=>PC6
+#define RTE_SDIO_D6_PORT_ID             0
+#if    (RTE_SDIO_D6_PORT_ID == 0)
+#define RTE_SDIO_D6_PORT                GPIOC
+#define RTE_SDIO_D6_PIN                 6
+#else
+#error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//      SDIO_D7 Pin <0=>PC7
+#define RTE_SDIO_D7_PORT_ID             0
+#if    (RTE_SDIO_D7_PORT_ID == 0)
+#define RTE_SDIO_D7_PORT                GPIOC
+#define RTE_SDIO_D7_PIN                 7
+#else
+#error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//   
+
+//    DMA
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <6=>6
+//       Selects DMA Stream (only Stream 3 or 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SDIO_DMA                    1
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_STREAM             3
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// 
+
+
+//  ETH (Ethernet Interface) [Driver_ETH_MAC0]
+//  Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define RTE_ETH                         1
+
+//    MII (Media Independent Interface)
+#define RTE_ETH_MII                     0
+
+//      ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#elif  (RTE_ETH_MII_TXD0_PORT_ID == 1)
+#define RTE_ETH_MII_TXD0_PORT           GPIOG
+#define RTE_ETH_MII_TXD0_PIN            13
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//      ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#elif  (RTE_ETH_MII_TXD1_PORT_ID == 1)
+#define RTE_ETH_MII_TXD1_PORT           GPIOG
+#define RTE_ETH_MII_TXD1_PIN            14
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//      ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//      ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#elif  (RTE_ETH_MII_TXD3_PORT_ID == 1)
+#define RTE_ETH_MII_TXD3_PORT           GPIOE
+#define RTE_ETH_MII_TXD3_PIN            2
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//      ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#elif  (RTE_ETH_MII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOG
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//      ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_PORT_ID        0
+#if    (RTE_ETH_MII_RXD0_PORT_ID == 0)
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+//      ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_PORT_ID        0
+#if    (RTE_ETH_MII_RXD1_PORT_ID == 0)
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+//      ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6
+#define RTE_ETH_MII_RXD2_PORT_ID        0
+#if    (RTE_ETH_MII_RXD2_PORT_ID == 0)
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif  (RTE_ETH_MII_RXD2_PORT_ID == 1)
+#define RTE_ETH_MII_RXD2_PORT           GPIOH
+#define RTE_ETH_MII_RXD2_PIN            6
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+//      ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7
+#define RTE_ETH_MII_RXD3_PORT_ID        0
+#if    (RTE_ETH_MII_RXD3_PORT_ID == 0)
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RXD3_PORT           GPIOH
+#define RTE_ETH_MII_RXD3_PIN            7
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+//      ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_PORT_ID       0
+#if    (RTE_ETH_MII_RX_DV_PORT_ID == 0)
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+//      ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOI
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//      ETH_MII_CRS Pin <0=>PA0 <1=>PH2
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#elif  (RTE_ETH_MII_CRS_PORT_ID == 1)
+#define RTE_ETH_MII_CRS_PORT            GPIOH
+#define RTE_ETH_MII_CRS_PIN             2
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//      ETH_MII_COL Pin <0=>PA3 <1=>PH3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#elif  (RTE_ETH_MII_COL_PORT_ID == 1)
+#define RTE_ETH_MII_COL_PORT            GPIOH
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//   
+
+//    RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    1
+
+//      ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_RMII_TXD0_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#elif  (RTE_ETH_RMII_TXD0_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOG
+#define RTE_ETH_RMII_TXD0_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_RMII_TXD1_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#elif  (RTE_ETH_RMII_TXD1_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOG
+#define RTE_ETH_RMII_TXD1_PIN           14
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      1
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#elif  (RTE_ETH_RMII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOG
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//      ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//      ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_PORT_ID     0
+#if    (RTE_ETH_RMII_CRS_DV_PORT_ID == 0)
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   
+
+//    Management Data Interface
+//      ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//      ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   
+
+//    Reference 25MHz/50MHz Clock generation
+#define RTE_ETH_REF_CLOCK               0
+
+//      MCO Pin <0=>PA2 <1=>PC9
+#define RTE_ETH_REF_CLOCK_PORT_ID       0
+#if    (RTE_ETH_REF_CLOCK_PORT_ID == 0)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOA
+#define RTE_ETH_REF_CLOCK_PIN           8
+#elif  (RTE_ETH_REF_CLOCK_PORT_ID == 1)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOC
+#define RTE_ETH_REF_CLOCK_PIN           9
+#else
+#error "Invalid MCO Pin Configuration!"
+#endif
+
+//   
+
+// 
+
+
+//  USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//    Device [Driver_USBD0]
+//    Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_OTG_FS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_FS_DEV_EP           0x0000000F
+#define RTE_USB_OTG_FS_DEV_EP_BULK      0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_INT       0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_ISO       0x000E000E
+
+//   
+
+//    Host [Driver_USBH0]
+//    Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(7)
+#define RTE_OTG_FS_VBUS_BIT             5
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_FS_OC_BIT               11
+//   
+
+// 
+
+
+//  USB OTG High-speed
+#define RTE_USB_OTG_HS                  0
+
+//    PHY (Physical Layer)
+
+//      PHY Interface
+//       <0=>On-chip full-speed PHY
+//       <1=>External ULPI high-speed PHY
+#define RTE_USB_OTG_HS_PHY              1
+
+//      External ULPI Pins (UTMI+ Low Pin Interface)
+
+//        OTG_HS_ULPI_CK Pin <0=>PA5
+#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_CK_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_CK_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_CK Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOI
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     11
+#elif  (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     2
+#else
+#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_STP Pin <0=>PC0
+#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_STP_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_STP_PIN     0
+#else
+#error "Invalid OTG_HS_ULPI_STP Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1
+#if    (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     2
+#elif  (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOH
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     4
+#else
+#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D0 Pin <0=>PA3
+#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D0_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_D0_PIN      3
+#else
+#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D1 Pin <0=>PB0
+#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D1_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D1_PIN      0
+#else
+#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D2 Pin <0=>PB1
+#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D2_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D2_PIN      1
+#else
+#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D3 Pin <0=>PB10
+#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D3_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D3_PIN      10
+#else
+#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D4 Pin <0=>PB11
+#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D4_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D4_PIN      11
+#else
+#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D5 Pin <0=>PB12
+#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D5_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D5_PIN      12
+#else
+#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D6 Pin <0=>PB13
+#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D6_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D6_PIN      13
+#else
+#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D7 Pin <0=>PB5
+#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D7_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D7_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!"
+#endif
+
+//     
+
+//   
+
+//    Device [Driver_USBD1]
+//    Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+#define RTE_USB_OTG_HS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 4
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 5
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_HS_DEV_EP           0x0000003F
+#define RTE_USB_OTG_HS_DEV_EP_BULK      0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_INT       0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_ISO       0x003E003E
+
+//   
+
+//    Host [Driver_USBH1]
+//    Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define RTE_USB_OTG_HS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_VBUS_PIN             1
+#define RTE_OTG_HS_VBUS_ACTIVE          0
+#define RTE_OTG_HS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_HS_VBUS_BIT             2
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_OC_PIN               1
+#define RTE_OTG_HS_OC_ACTIVE            0
+#define RTE_OTG_HS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_HS_OC_BIT               12
+//   
+
+// 
+
+
+//  EXTI (External Interrupt/Event Controller)
+#define RTE_EXTI                        0
+
+//    EXTI0 Line
+#define RTE_EXTI0                       0
+//      Pin   <0=>PA0  <1=>PB0  <2=>PC0  <3=>PD0  <4=>PE0  <5=>PF0  <6=>PG0  <7=>PH0  <8=>PI0
+#define RTE_EXTI0_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI0_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI0_TRIGGER               0
+//   
+
+//    EXTI1 Line
+#define RTE_EXTI1                       0
+//      Pin   <0=>PA1  <1=>PB1  <2=>PC1  <3=>PD1  <4=>PE1  <5=>PF1  <6=>PG1  <7=>PH1  <8=>PI1
+#define RTE_EXTI1_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI1_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI1_TRIGGER               0
+//   
+
+//    EXTI2 Line
+#define RTE_EXTI2                       0
+//      Pin   <0=>PA2  <1=>PB2  <2=>PC2  <3=>PD2  <4=>PE2  <5=>PF2  <6=>PG2  <7=>PH2  <8=>PI2
+#define RTE_EXTI2_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI2_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI2_TRIGGER               0
+//   
+
+//    EXTI3 Line
+#define RTE_EXTI3                       0
+//      Pin   <0=>PA3  <1=>PB3  <2=>PC3  <3=>PD3  <4=>PE3  <5=>PF3  <6=>PG3  <7=>PH3  <8=>PI3
+#define RTE_EXTI3_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI3_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI3_TRIGGER               0
+//   
+
+//    EXTI4 Line
+#define RTE_EXTI4                       0
+//      Pin   <0=>PA4  <1=>PB4  <2=>PC4  <3=>PD4  <4=>PE4  <5=>PF4  <6=>PG4  <7=>PH4  <8=>PI4
+#define RTE_EXTI4_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI4_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI4_TRIGGER               0
+//   
+
+//    EXTI5 Line
+#define RTE_EXTI5                       0
+//      Pin   <0=>PA5  <1=>PB5  <2=>PC5  <3=>PD5  <4=>PE5  <5=>PF5  <6=>PG5  <7=>PH5  <8=>PI5
+#define RTE_EXTI5_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI5_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI5_TRIGGER               0
+//   
+
+//    EXTI6 Line
+#define RTE_EXTI6                       0
+//      Pin   <0=>PA6  <1=>PB6  <2=>PC6  <3=>PD6  <4=>PE6  <5=>PF6  <6=>PG6  <7=>PH6  <8=>PI6
+#define RTE_EXTI6_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI6_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI6_TRIGGER               0
+//   
+
+//    EXTI7 Line
+#define RTE_EXTI7                       0
+//      Pin   <0=>PA7  <1=>PB7  <2=>PC7  <3=>PD7  <4=>PE7  <5=>PF7  <6=>PG7  <7=>PH7  <8=>PI7
+#define RTE_EXTI7_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI7_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI7_TRIGGER               0
+//   
+
+//    EXTI8 Line
+#define RTE_EXTI8                       0
+//      Pin   <0=>PA8  <1=>PB8  <2=>PC8  <3=>PD8  <4=>PE8  <5=>PF8  <6=>PG8  <7=>PH8  <8=>PI8
+#define RTE_EXTI8_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI8_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI8_TRIGGER               0
+//   
+
+//    EXTI9 Line
+#define RTE_EXTI9                       0
+//      Pin   <0=>PA9  <1=>PB9  <2=>PC9  <3=>PD9  <4=>PE9  <5=>PF9  <6=>PG9  <7=>PH9  <8=>PI9
+#define RTE_EXTI9_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI9_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI9_TRIGGER               0
+//   
+
+//    EXTI10 Line
+#define RTE_EXTI10                      0
+//      Pin   <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10
+#define RTE_EXTI10_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI10_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI10_TRIGGER              0
+//   
+
+//    EXTI11 Line
+#define RTE_EXTI11                      0
+//      Pin   <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11
+#define RTE_EXTI11_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI11_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI11_TRIGGER              0
+//   
+
+//    EXTI12 Line
+#define RTE_EXTI12                      0
+//      Pin   <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12
+#define RTE_EXTI12_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI12_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI12_TRIGGER              0
+//   
+
+//    EXTI13 Line
+#define RTE_EXTI13                      0
+//      Pin   <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13
+#define RTE_EXTI13_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI13_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI13_TRIGGER              0
+//   
+
+//    EXTI14 Line
+#define RTE_EXTI14                      0
+//      Pin   <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14
+#define RTE_EXTI14_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI14_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI14_TRIGGER              0
+//   
+
+//    EXTI15 Line
+#define RTE_EXTI15                      0
+//      Pin   <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15
+#define RTE_EXTI15_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI15_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI15_TRIGGER              0
+//   
+
+//    EXTI16 Line: PVD Output
+#define RTE_EXTI16                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI16_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI16_TRIGGER              0
+//   
+
+//    EXTI17 Line: RTC Alarm
+#define RTE_EXTI17                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI17_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI17_TRIGGER              0
+//   
+
+//    EXTI18 Line: USB OTG FS Wakeup
+#define RTE_EXTI18                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI18_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI18_TRIGGER              0
+//   
+
+//    EXTI19 Line: Ethernet Wakeup
+#define RTE_EXTI19                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI19_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI19_TRIGGER              0
+//   
+
+//    EXTI20 Line: USB OTG HS Wakeup
+#define RTE_EXTI20                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI20_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI20_TRIGGER              0
+//   
+
+//    EXTI21 Line: RTC Tamper and TimeStamp
+#define RTE_EXTI21                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI21_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI21_TRIGGER              0
+//   
+
+//    EXTI22 Line: RTC Wakeup
+#define RTE_EXTI22                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI22_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI22_TRIGGER              0
+//   
+
+// 
+
+
+//  FSMC (Flexible Static Memory Controller)
+#define RTE_FSMC                        0
+
+//    Pin Configuration
+//    Configure Pins
+#define RTE_FSMC_PINS                   0
+
+//      Address Bus Pins
+//       <0=>A[17:16]
+//       <1=>A[10:0]   <2=>A[15:0]   <3=>A[16:0]   <4=>A[17:0]
+//       <5=>A[18:0]   <6=>A[19:0]   <7=>A[20:0]   <8=>A[21:0]
+//       <9=>A[22:0]  <10=>A[23:0]  <11=>A[24:0]  <12=>A[25:0]
+#define RTE_FSMC_ABUS_PINS              10
+//      Data Bus Pins  <0=>D[7:0] <1=>D[15:0]
+#define RTE_FSMC_DBUS_PINS              0
+//      FSMC_NOE Pin
+#define RTE_FSMC_NOE_PIN                0
+//      FSMC_NWE Pin
+#define RTE_FSMC_NWE_PIN                0
+//      FSMC_NBL0 Pin
+#define RTE_FSMC_NBL0_PIN               0
+//      FSMC_NBL1 Pin
+#define RTE_FSMC_NBL1_PIN               0
+//      FSMC_NL Pin
+#define RTE_FSMC_NL_PIN                 0
+//      FSMC_NWAIT Pin
+#define RTE_FSMC_NWAIT_PIN              0
+//      FSMC_CLK Pin
+#define RTE_FSMC_CLK_PIN                0
+//      FSMC_NE1/NCE2 Pin
+#define RTE_FSMC_NE1_PIN                0
+//      FSMC_NE2/NCE3 Pin
+#define RTE_FSMC_NE2_PIN                0
+//      FSMC_NE3/NCE4_1 Pin
+#define RTE_FSMC_NE3_PIN                0
+//      FSMC_NE4 Pin
+#define RTE_FSMC_NE4_PIN                0
+//      FSMC_NCE4_2 Pin
+#define RTE_FSMC_NCE42_PIN              0
+//      FSMC_INT2 Pin
+#define RTE_FSMC_INT2_PIN               0
+//      FSMC_INT3 Pin
+#define RTE_FSMC_INT3_PIN               0
+//      FSMC_INTR Pin
+#define RTE_FSMC_INTR_PIN               0
+//      FSMC_NIORD Pin
+#define RTE_FSMC_NIORD_PIN              0
+//      FSMC_NIOWR Pin
+#define RTE_FSMC_NIOWR_PIN              0
+//      FSMC_NREG Pin
+#define RTE_FSMC_NREG_PIN               0
+//      FSMC_CD Pin
+#define RTE_FSMC_CD_PIN                 0
+
+//   
+
+//    NOR Flash / PSRAM Controller
+
+//      FSMC_NE1 Chip Select
+//      Configure Device on Chip Select FSMC_NE1
+#define RTE_FSMC_NE1                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR1_CBURSTRW          0
+#define RTE_FSMC_BCR1_ASYNCWAIT         0
+#define RTE_FSMC_BCR1_EXTMOD            0
+#define RTE_FSMC_BCR1_WAITEN            1
+#define RTE_FSMC_BCR1_WREN              1
+#define RTE_FSMC_BCR1_WAITCFG           0
+#define RTE_FSMC_BCR1_WRAPMOD           0
+#define RTE_FSMC_BCR1_WAITPOL           0
+#define RTE_FSMC_BCR1_BURSTEN           0
+#define RTE_FSMC_BCR1_FACCEN            1
+#define RTE_FSMC_BCR1_MWID              1
+#define RTE_FSMC_BCR1_MTYP              2
+#define RTE_FSMC_BCR1_MUXEN             1
+#define RTE_FSMC_BCR1_MBKEN             1
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR1_ACCMOD            0
+#define RTE_FSMC_BTR1_DATLAT            15
+#define RTE_FSMC_BTR1_CLKDIV            15
+#define RTE_FSMC_BTR1_BUSTURN           15
+#define RTE_FSMC_BTR1_DATAST            255
+#define RTE_FSMC_BTR1_ADDHLD            15
+#define RTE_FSMC_BTR1_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR1_ACCMOD        0
+#define RTE_FSMC_BWTR1_DATLAT        15
+#define RTE_FSMC_BWTR1_CLKDIV        15
+#define RTE_FSMC_BWTR1_BUSTURN       15
+#define RTE_FSMC_BWTR1_DATAST        255
+#define RTE_FSMC_BWTR1_ADDHLD        15
+#define RTE_FSMC_BWTR1_ADDSET        15
+//       
+//     
+
+//      FSMC_NE2 Chip Select
+//      Configure Device on Chip Select FSMC_NE2
+#define RTE_FSMC_NE2                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR2_CBURSTRW          0
+#define RTE_FSMC_BCR2_ASYNCWAIT         0
+#define RTE_FSMC_BCR2_EXTMOD            0
+#define RTE_FSMC_BCR2_WAITEN            1
+#define RTE_FSMC_BCR2_WREN              1
+#define RTE_FSMC_BCR2_WAITCFG           0
+#define RTE_FSMC_BCR2_WRAPMOD           0
+#define RTE_FSMC_BCR2_WAITPOL           0
+#define RTE_FSMC_BCR2_BURSTEN           0
+#define RTE_FSMC_BCR2_FACCEN            1
+#define RTE_FSMC_BCR2_MWID              1
+#define RTE_FSMC_BCR2_MTYP              0
+#define RTE_FSMC_BCR2_MUXEN             1
+#define RTE_FSMC_BCR2_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR2_ACCMOD            0
+#define RTE_FSMC_BTR2_DATLAT            15
+#define RTE_FSMC_BTR2_CLKDIV            15
+#define RTE_FSMC_BTR2_BUSTURN           15
+#define RTE_FSMC_BTR2_DATAST            255
+#define RTE_FSMC_BTR2_ADDHLD            15
+#define RTE_FSMC_BTR2_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR2_ACCMOD        0
+#define RTE_FSMC_BWTR2_DATLAT        15
+#define RTE_FSMC_BWTR2_CLKDIV        15
+#define RTE_FSMC_BWTR2_BUSTURN       15
+#define RTE_FSMC_BWTR2_DATAST        255
+#define RTE_FSMC_BWTR2_ADDHLD        15
+#define RTE_FSMC_BWTR2_ADDSET        15
+//       
+//     
+
+//      FSMC_NE3 Chip Select
+//      Configure Device on Chip Select FSMC_NE3
+#define RTE_FSMC_NE3                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR3_CBURSTRW          0
+#define RTE_FSMC_BCR3_ASYNCWAIT         0
+#define RTE_FSMC_BCR3_EXTMOD            0
+#define RTE_FSMC_BCR3_WAITEN            1
+#define RTE_FSMC_BCR3_WREN              1
+#define RTE_FSMC_BCR3_WAITCFG           0
+#define RTE_FSMC_BCR3_WRAPMOD           0
+#define RTE_FSMC_BCR3_WAITPOL           0
+#define RTE_FSMC_BCR3_BURSTEN           0
+#define RTE_FSMC_BCR3_FACCEN            1
+#define RTE_FSMC_BCR3_MWID              1
+#define RTE_FSMC_BCR3_MTYP              0
+#define RTE_FSMC_BCR3_MUXEN             1
+#define RTE_FSMC_BCR3_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR3_ACCMOD            0
+#define RTE_FSMC_BTR3_DATLAT            15
+#define RTE_FSMC_BTR3_CLKDIV            15
+#define RTE_FSMC_BTR3_BUSTURN           15
+#define RTE_FSMC_BTR3_DATAST            255
+#define RTE_FSMC_BTR3_ADDHLD            15
+#define RTE_FSMC_BTR3_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR3_ACCMOD        0
+#define RTE_FSMC_BWTR3_DATLAT        15
+#define RTE_FSMC_BWTR3_CLKDIV        15
+#define RTE_FSMC_BWTR3_BUSTURN       15
+#define RTE_FSMC_BWTR3_DATAST        255
+#define RTE_FSMC_BWTR3_ADDHLD        15
+#define RTE_FSMC_BWTR3_ADDSET        15
+//       
+//     
+
+//      FSMC_NE4 Chip Select
+//      Configure Device on Chip Select FSMC_NE4
+#define RTE_FSMC_NE4                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR4_CBURSTRW          0
+#define RTE_FSMC_BCR4_ASYNCWAIT         0
+#define RTE_FSMC_BCR4_EXTMOD            0
+#define RTE_FSMC_BCR4_WAITEN            1
+#define RTE_FSMC_BCR4_WREN              1
+#define RTE_FSMC_BCR4_WAITCFG           0
+#define RTE_FSMC_BCR4_WRAPMOD           0
+#define RTE_FSMC_BCR4_WAITPOL           0
+#define RTE_FSMC_BCR4_BURSTEN           0
+#define RTE_FSMC_BCR4_FACCEN            1
+#define RTE_FSMC_BCR4_MWID              1
+#define RTE_FSMC_BCR4_MTYP              0
+#define RTE_FSMC_BCR4_MUXEN             1
+#define RTE_FSMC_BCR4_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR4_ACCMOD            0
+#define RTE_FSMC_BTR4_DATLAT            15
+#define RTE_FSMC_BTR4_CLKDIV            15
+#define RTE_FSMC_BTR4_BUSTURN           15
+#define RTE_FSMC_BTR4_DATAST            255
+#define RTE_FSMC_BTR4_ADDHLD            15
+#define RTE_FSMC_BTR4_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR4_ACCMOD        0
+#define RTE_FSMC_BWTR4_DATLAT        15
+#define RTE_FSMC_BWTR4_CLKDIV        15
+#define RTE_FSMC_BWTR4_BUSTURN       15
+#define RTE_FSMC_BWTR4_DATAST        255
+#define RTE_FSMC_BWTR4_ADDHLD        15
+#define RTE_FSMC_BWTR4_ADDSET        15
+//       
+//     
+
+//   
+
+//    NAND Flash Controller
+
+//      FSMC_NCE2 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE2
+#define RTE_FSMC_NCE2                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR2_ECCPS             0
+#define RTE_FSMC_PCR2_TAR               0
+#define RTE_FSMC_PCR2_TCLR              0
+#define RTE_FSMC_PCR2_ECCEN             0
+#define RTE_FSMC_PCR2_PWID              0
+#define RTE_FSMC_PCR2_PTYP              1
+#define RTE_FSMC_PCR2_PBKEN             0
+#define RTE_FSMC_PCR2_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR2_IFEN               0
+#define RTE_FSMC_SR2_ILEN               0
+#define RTE_FSMC_SR2_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM2_MEMHIZ           255
+#define RTE_FSMC_PMEM2_MEMHOLD          255
+#define RTE_FSMC_PMEM2_MEMWAIT          255
+#define RTE_FSMC_PMEM2_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT2_ATTHIZ           255
+#define RTE_FSMC_PATT2_ATTHOLD          255
+#define RTE_FSMC_PATT2_ATTWAIT          255
+#define RTE_FSMC_PATT2_ATTSET           255
+
+//       
+
+//     
+
+//      FSMC_NCE3 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE3
+#define RTE_FSMC_NCE3                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR3_ECCPS             0
+#define RTE_FSMC_PCR3_TAR               0
+#define RTE_FSMC_PCR3_TCLR              0
+#define RTE_FSMC_PCR3_ECCEN             0
+#define RTE_FSMC_PCR3_PWID              0
+#define RTE_FSMC_PCR3_PTYP              1
+#define RTE_FSMC_PCR3_PBKEN             0
+#define RTE_FSMC_PCR3_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR3_IFEN               0
+#define RTE_FSMC_SR3_ILEN               0
+#define RTE_FSMC_SR3_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM3_MEMHIZ           255
+#define RTE_FSMC_PMEM3_MEMHOLD          255
+#define RTE_FSMC_PMEM3_MEMWAIT          255
+#define RTE_FSMC_PMEM3_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT3_ATTHIZ           255
+#define RTE_FSMC_PATT3_ATTHOLD          255
+#define RTE_FSMC_PATT3_ATTWAIT          255
+#define RTE_FSMC_PATT3_ATTSET           255
+
+//       
+
+//     
+
+//   
+
+//    PC Card Controller
+
+//      FSMC_NCE4_x Chip Select
+//      Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2
+#define RTE_FSMC_NCE4              0
+
+//        PC Card Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: PC Card memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR4_ECCPS             0
+#define RTE_FSMC_PCR4_TAR               0
+#define RTE_FSMC_PCR4_TCLR              0
+#define RTE_FSMC_PCR4_ECCEN             0
+#define RTE_FSMC_PCR4_PWID              0
+#define RTE_FSMC_PCR4_PTYP              0
+#define RTE_FSMC_PCR4_PBKEN             0
+#define RTE_FSMC_PCR4_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR4_IFEN               0
+#define RTE_FSMC_SR4_ILEN               0
+#define RTE_FSMC_SR4_IREN               0
+
+//       
+
+//        Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM4_MEMHIZ           255
+#define RTE_FSMC_PMEM4_MEMHOLD          255
+#define RTE_FSMC_PMEM4_MEMWAIT          255
+#define RTE_FSMC_PMEM4_MEMSET           255
+
+//       
+
+//        Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT4_ATTHIZ           255
+#define RTE_FSMC_PATT4_ATTHOLD          255
+#define RTE_FSMC_PATT4_ATTWAIT          255
+#define RTE_FSMC_PATT4_ATTSET           255
+
+//       
+
+//        I/O space timing
+//          IOHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a PC Card write access. Only valid for write transaction.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE,
+//           SMNOE), for PC Card read or write access. The duration for command assertion is
+//           extended if the wait signal (NWAIT) is active (low) at the end of the
+//           programmed value of HCLK.
+//           0000 0000: reserved, do not use this value
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles
+//          IOSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PIO4_IOHIZ             255
+#define RTE_FSMC_PIO4_IOHOLD            255
+#define RTE_FSMC_PIO4_IOWAIT            255
+#define RTE_FSMC_PIO4_IOSET             255
+
+//       
+
+//     
+
+//   
+
+// 
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s
new file mode 100644
index 000000000..d398143ef
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s
@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00007000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c
new file mode 100644
index 000000000..da0e189c8
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c
@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2011 STMicroelectronics

+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c
new file mode 100644
index 000000000..78564b080
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config.c
@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// File System
+// Define File System global parameters
+
+//   Number of open files <4-16>
+//   Define number of files that can be
+//   opened at the same time.
+//   Default: 8
+#define NUM_FILES               8
+
+//   FAT Name Cache Size <0-1000000>
+//   Define number of cached FAT file or directory names.
+//   48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   Relocate FAT Name Cache Buffer
+//   Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h
new file mode 100644
index 000000000..0b1c6d3a7
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/File_System/FS_Config_MC_0.h
@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Memory Card Drive 0
+// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   Connect to hardware via Driver_MCI# <0-255>
+//   Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   Connect to hardware via Driver_SPI# <0-255>
+//   Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   Memory Card Interface Mode <0=>Native <1=>SPI
+//   Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   Drive Cache stores data sectors and may be increased to speed-up
+//   file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   Locate Drive Cache and Drive Buffer
+//   Some microcontrollers support DMA only in specific memory areas and
+//   require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   
+
+//   Use FAT Journal
+//   Protect File Allocation Table and Directory Entries for
+//   fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   Default Drive "M0:"
+//   Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c
new file mode 100644
index 000000000..6b9dc8e00
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config.c
@@ -0,0 +1,153 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// System Definitions
+//  Global Network System definitions
+//   Local Host Name
+//    This is the name under which embedded host can be
+//    accessed on a local area network.
+//    Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   Memory Pool size <1536-262144:4><#/4>
+//    This is the size of a memory pool in bytes. Buffers for
+//    Network packets are allocated from this memory pool.
+//    Default: 12000 bytes
+#define NET_MEM_SIZE            3000
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP_0
+#include "Net_Config_PPP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_PPP_1
+#include "Net_Config_PPP_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP_0
+#include "Net_Config_SLIP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_SLIP_1
+#include "Net_Config_SLIP_1.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (ERROR_CODE error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (ERROR_CODE error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer Corrupted */
+      /* More data written than the size of allocated mem block */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h
new file mode 100644
index 000000000..d7e6a614a
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_BSD.h
@@ -0,0 +1,36 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_BSD.h
+ * Purpose: Network Configuration BSD Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Berkley (BSD) Sockets
+#define BSD_ENABLE              1
+
+//   Number of BSD Sockets <1-20>
+//    Number of available Berkeley Sockets
+//    Default: 2
+#define BSD_NUM_SOCKS           7
+
+//   Number of Streaming Server Sockets <0-20>
+//    Defines a number of Streaming (TCP) Server sockets,
+//    that listen for an incoming connection from the client.
+//    Default: 1
+#define BSD_SERVER_SOCKS        1
+
+//   Receive Timeout in seconds <0-600>
+//    A timeout for socket receive in blocking mode.
+//    Timeout value of 0 means indefinite timeout.
+//    Default: 20
+#define BSD_RECEIVE_TOUT        20
+
+//   Hostname Resolver
+//    Enable or disable Berkeley style hostname resolver.
+#define BSD_HOSTNAME_ENABLE     0
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h
new file mode 100644
index 000000000..d30b71807
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Service
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_DNS_Client.h
+ * Purpose: Network Configuration DNS Client
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// DNS Client
+#define DNS_CLIENT_ENABLE       1
+
+//     Cache Table size <5-100>
+//      Number of cached DNS host names/IP addresses
+//      Default: 20
+#define DNS_CLIENT_TAB_SIZE     20
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_ETH_0.h
new file mode 100644
index 000000000..7be57ad6d
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_ETH_0.h
@@ -0,0 +1,222 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_ETH_0.h
+ * Purpose: Network Configuration ETH Interface
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Ethernet Network Interface 0
+#define ETH0_ENABLE             1
+
+//   Connect to hardware via Driver_ETH# <0-255>
+//   Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER             1
+
+//   MAC Address
+//    Local Ethernet MAC Address
+//    Value FF:FF:FF:FF:FF:FF is not allowed.
+//    It is an ethernet Broadcast MAC address.
+//     Address byte 1 <0x00-0xff:2>
+//      LSB is an ethernet Multicast bit.
+//      Must be 0 for local MAC address.
+//      Default: 0x1E
+#define ETH0_MAC1               0x1E
+
+//     Address byte 2 <0x00-0xff>
+//      Default: 0x30
+#define ETH0_MAC2               0x30
+
+//     Address byte 3 <0x00-0xff>
+//      Default: 0x6C
+#define ETH0_MAC3               0x6C
+
+//     Address byte 4 <0x00-0xff>
+//      Default: 0xA2
+#define ETH0_MAC4               0xA2
+
+//     Address byte 5 <0x00-0xff>
+//      Default: 0x45
+#define ETH0_MAC5               0x45
+
+//     Address byte 6 <0x00-0xff>
+//      Default: 0x5E
+#define ETH0_MAC6               0x5E
+//   
+
+//   IP Address
+//    Local Static IP Address
+//    Value 255.255.255.255 is not allowed.
+//    It is a Broadcast IP address.
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_IP1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_IP2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_IP3                0
+
+//     Address byte 4 <0-255>
+//      Default: 100
+#define ETH0_IP4                100
+//   
+
+//   Subnet mask
+//    Local Subnet mask
+//     Mask byte 1 <0-255>
+//      Default: 255
+#define ETH0_MASK1              255
+
+//     Mask byte 2 <0-255>
+//      Default: 255
+#define ETH0_MASK2              255
+
+//     Mask byte 3 <0-255>
+//      Default: 255
+#define ETH0_MASK3              255
+
+//     Mask byte 4 <0-255>
+//      Default: 0
+#define ETH0_MASK4              0
+//   
+
+//   Default Gateway
+//    Default Gateway IP Address
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_GW1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_GW2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_GW3                0
+
+//     Address byte 4 <0-255>
+//      Default: 254
+#define ETH0_GW4                254
+//   
+
+//   Primary DNS Server
+//    Primary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_PRI_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_PRI_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_PRI_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 129
+#define ETH0_PRI_DNS4           129
+//   
+
+//   Secondary DNS Server
+//    Secondary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_SEC_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_SEC_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_SEC_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 130
+#define ETH0_SEC_DNS4           130
+//   
+
+//   ARP Definitions
+//    Address Resolution Protocol Definitions
+//     Cache Table size <5-100>
+//      Number of cached hardware/IP addresses
+//      Default: 10
+#define ETH0_ARP_TAB_SIZE       10
+
+//     Cache Timeout in seconds <5-255>
+//      A timeout for a cached hardware/IP addresses
+//      Default: 150
+#define ETH0_ARP_CACHE_TOUT     150
+
+//     Number of Retries <0-20>
+//      Number of Retries to resolve an IP address
+//      before ARP module gives up
+//      Default: 4
+#define ETH0_ARP_MAX_RETRY      4
+
+//     Resend Timeout in seconds <1-10>
+//      A timeout to resend the ARP Request
+//      Default: 2
+#define ETH0_ARP_RESEND_TOUT    2
+
+//     Send Notification on Address changes
+//      When this option is enabled, the embedded host
+//      will send a Gratuitous ARP notification at startup,
+//      or when the device IP address has changed.
+//      Default: Disabled
+#define ETH0_ARP_NOTIFY         0
+//   
+
+//   IGMP Group Management
+//    Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE        0
+
+//     Membership Table size <2-50>
+//      Number of Groups this host can join
+//      Default: 5
+#define ETH0_IGMP_TAB_SIZE      5
+//   
+
+//   NetBIOS Name Service
+//    When this option is enabled, the embedded host can be
+//    accessed by his name on the local LAN using NBNS protocol.
+//    You need to modify also the number of UDP Sockets,
+//    because NBNS protocol uses one UDP socket to run.
+#define ETH0_NBNS_ENABLE        1
+
+//   Dynamic Host Configuration
+//    When this option is enabled, local IP address, Net Mask
+//    and Default Gateway are obtained automatically from
+//    the DHCP Server on local LAN.
+//    You need to modify also the number of UDP Sockets,
+//    because DHCP protocol uses one UDP socket to run.
+#define ETH0_DHCP_ENABLE        1
+
+//     Vendor Class Identifier
+//      This value is optional. If specified, it is added
+//      to DHCP request message, identifying vendor type.
+//      Default: ""
+#define ETH0_DHCP_VCID          ""
+
+//     Bootfile Name
+//      This value is optional. If enabled, the Bootfile Name
+//      (option 67) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_BOOTFILE      0
+
+//     NTP Servers
+//      This value is optional. If enabled, a list of NTP Servers
+//      (option 42) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_NTP_SERVERS   0
+//   
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_TCP.h
new file mode 100644
index 000000000..e659ce921
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_TCP.h
@@ -0,0 +1,61 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_TCP.h
+ * Purpose: Network Configuration TCP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// TCP Sockets
+#define TCP_ENABLE              1
+
+//   Number of TCP Sockets <1-20>
+//    Number of available TCP sockets
+//    Default: 5
+#define TCP_NUM_SOCKS           10
+
+//   Number of Retries <0-20>
+//    How many times TCP module will try to retransmit data
+//    before giving up. Increase this value for high-latency
+//    and low_throughput networks.
+//    Default: 5
+#define TCP_MAX_RETRY           5
+
+//   Retry Timeout in seconds <1-10>
+//    If data frame not acknowledged within this time frame,
+//    TCP module will try to resend the data again.
+//    Default: 4
+#define TCP_RETRY_TOUT          4
+
+//   Default Connect Timeout in seconds <1-600>
+//    Default TCP Socket Keep Alive timeout. When it expires
+//    with no TCP data frame send, TCP Connection is closed.
+//    Default: 120
+#define TCP_DEFAULT_TOUT        120
+
+//   Maximum Segment Size <536-1460>
+//    The Maximum Segment Size specifies the maximum
+//    number of bytes in the TCP segment's Data field.
+//    Default: 1460
+#define TCP_MAX_SEG_SIZE        1460
+
+//   Receive Window Size <536-65535>
+//    Receive Window Size specifies the size of data, 
+//    that the socket is able to buffer in flow-control mode.
+//    Default: 4380
+#define TCP_RECEIVE_WIN_SIZE    4380
+
+// 
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT  1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT      2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY       7
+
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_UDP.h
new file mode 100644
index 000000000..b7995c22d
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_UDP.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_UDP.h
+ * Purpose: Network Configuration UDP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// UDP Sockets
+#define UDP_ENABLE              1
+
+//   Number of UDP Sockets <1-20>
+//    Number of available UDP sockets
+//    Default: 5
+#define UDP_NUM_SOCKS           10
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Debug.c
new file mode 100644
index 000000000..735089a40
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Debug.c
@@ -0,0 +1,125 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Debug.c
+ * Purpose: Network Debug Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Print Time Stamp
+//    Enable printing the time-info in debug messages
+#define DBG_TIME                1
+
+// TCPnet Debug Definitions
+//   Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Memory debug messages
+#define DBG_MEM                 1
+
+//   Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Ethernet debug messages
+#define DBG_ETH                 0
+
+//   PPP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off PPP debug messages
+#define DBG_PPP                 0
+
+//   SLIP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SLIP debug messages
+#define DBG_SLIP                0
+
+//   ARP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ARP debug messages
+#define DBG_ARP                 0
+
+//   IP Debug    <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IP debug messages
+#define DBG_IP                  1
+
+//   ICMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ICMP debug messages
+#define DBG_ICMP                1
+
+//   IGMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IGMP debug messages
+#define DBG_IGMP                1
+
+//   UDP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off UDP debug messages
+#define DBG_UDP                 1
+
+//   TCP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TCP debug messages
+#define DBG_TCP                 1
+
+//   NBNS Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off NetBIOS Name Service debug messages
+#define DBG_NBNS                1
+
+//   DHCP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Host Configuration debug messages
+#define DBG_DHCP                1
+
+//   DNS Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Domain Name Service debug messages
+#define DBG_DNS                 1
+
+//   SNMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Management debug messages
+#define DBG_SNMP                1
+
+//   SNTP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Time debug messages
+#define DBG_SNTP                1
+
+//   BSD Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off BSD Interface debug messages
+#define DBG_BSD                 1
+// 
+
+// Application Debug Definitions
+//   HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Web Server debug messages
+#define DBG_HTTP_SERVER         1
+
+//   FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Server debug messages
+#define DBG_FTP_SERVER          1
+
+//   FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Client debug messages
+#define DBG_FTP_CLIENT          1
+
+//   Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Telnet Server debug messages
+#define DBG_TELNET_SERVER       1
+
+//   TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Server debug messages
+#define DBG_TFTP_SERVER         1
+
+//   TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Client debug messages
+#define DBG_TFTP_CLIENT         1
+
+//   SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SMTP Client debug messages
+#define DBG_SMTP_CLIENT         1
+// 
+
+
+#include "net_debug.h"
+
+
+/**
+  \fn          void net_debug_init (void)
+  \brief       Initialize Network Debug Interface.
+*/
+void net_debug_init (void) {
+  /* Add your code to initialize the Debug output. This is usually the  */
+  /* serial interface. The function is called at TCPnet system startup. */
+  /* You may need to customize also the 'putchar()' function.           */
+
+}
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/EchoClient/RTE/RTE_Components.h
new file mode 100644
index 000000000..631a77143
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/RTE/RTE_Components.h
@@ -0,0 +1,28 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'EchoClient' 
+ * Target:  'EchoClient' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_ETH_MAC0            /* Driver ETH_MAC0 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_Drivers_PHY_ST802RT1        /* Driver PHY ST802RT1 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+#define RTE_Network_Core                /* Network Core */
+          #define RTE_Network_Debug               /* Network Debug Version */
+#define RTE_Network_DNS_Client          /* Network DNS Client */
+#define RTE_Network_Interface_ETH_0     /* Network Interface ETH 0 */
+#define RTE_Network_Socket_BSD          /* Network Socket BSD */
+#define RTE_Network_Socket_TCP          /* Network Socket TCP */
+#define RTE_Network_Socket_UDP          /* Network Socket UDP */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini
new file mode 100644
index 000000000..239abce37
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini
@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+//  Debug MCU Configuration
+//       DBG_SLEEP      Debug Sleep Mode
+//       DBG_STOP       Debug Stop Mode
+//       DBG_STANDBY    Debug Standby Mode
+//       TRACE_IOEN     Trace I/O Enable 
+//    TRACE_MODE     Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//       DBG_IWDG_STOP  Independant Watchdog Stopped when Core is halted
+//       DBG_WWDG_STOP  Window Watchdog Stopped when Core is halted
+//      DBG_TIM1_STOP  Timer 1 Stopped when Core is halted
+//      DBG_TIM2_STOP  Timer 2 Stopped when Core is halted
+//      DBG_TIM3_STOP  Timer 3 Stopped when Core is halted
+//      DBG_TIM4_STOP  Timer 4 Stopped when Core is halted
+//      DBG_CAN_STOP   CAN Stopped when Core is halted
+// 
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c b/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c
new file mode 100644
index 000000000..bc7e26310
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/echoclient.c
@@ -0,0 +1,287 @@
+/* echoclient.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#include 
+
+#if defined(CYASSL_MDK_ARM)
+    #include 
+    #include 
+    
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+    
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include 
+
+#include "examples/echoclient/echoclient.h"
+
+void echoclient_test(void* args)
+{
+    SOCKET_T sockfd = 0;
+
+    FILE* fin   = stdin  ;
+    FILE* fout = stdout;
+
+    int inCreated  = 0;
+    int outCreated = 0;
+
+    char msg[1024];
+    char reply[1024+1];
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+    int doDTLS = 0;
+    int doPSK = 0;
+    int sendSz;
+    int argc    = 0;
+    char** argv = 0;
+    int port = yasslPort;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+    
+#ifndef CYASSL_MDK_ARM
+    argc = ((func_args*)args)->argc;
+    argv = ((func_args*)args)->argv;
+#endif
+
+    if (argc >= 2) {
+        fin  = fopen(argv[1], "r"); 
+        inCreated = 1;
+    }
+    if (argc >= 3) {
+        fout = fopen(argv[2], "w");
+        outCreated = 1;
+    }
+
+    if (!fin)  err_sys("can't open input file");
+    if (!fout) err_sys("can't open output file");
+
+#ifdef CYASSL_DTLS
+    doDTLS  = 1;
+#endif
+
+#ifdef CYASSL_LEANPSK 
+    doPSK = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    doPSK = 1;
+#endif
+
+#if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && !defined(CYASSL_MDK_SHELL)
+    port = ((func_args*)args)->signal->port;
+#endif
+#if defined (CYASSL_CALLEE_PORT)
+    port = CYASSL_CALLEE_PORT ;
+#endif
+
+#if defined(CYASSL_DTLS)
+    method  = DTLSv1_client_method();
+#elif  !defined(NO_TLS)
+    method = CyaSSLv23_client_method();
+#else
+    method = SSLv3_client_method();
+#endif
+    ctx    = SSL_CTX_new(method);
+
+#ifndef NO_FILESYSTEM
+    #ifndef NO_RSA
+    if (SSL_CTX_load_verify_locations(ctx, caCert, 0) != SSL_SUCCESS)
+        err_sys("can't load ca file, Please run from CyaSSL home dir");
+    #endif
+    #ifdef HAVE_ECC
+        if (SSL_CTX_load_verify_locations(ctx, eccCert, 0) != SSL_SUCCESS)
+            err_sys("can't load ca file, Please run from CyaSSL home dir");
+    #endif
+#elif !defined(NO_CERTS)
+    if (!doPSK)
+        load_buffer(ctx, caCert, CYASSL_CA);
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    SSL_CTX_set_cipher_list(ctx, "AES256-SHA");
+#endif
+    if (doPSK) {
+#ifndef NO_PSK
+        const char *defaultCipherList;
+
+        CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb);
+        #ifdef HAVE_NULL_CIPHER
+            defaultCipherList = "PSK-NULL-SHA256";
+        #else
+            defaultCipherList = "PSK-AES128-CBC-SHA256";
+        #endif
+        if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS)
+            err_sys("client can't set cipher list 2");
+#endif
+    }
+
+#ifdef OPENSSL_EXTRA
+    SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+    #if defined(CYASSL_MDK_ARM)
+    CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0);
+    #endif
+
+    ssl = SSL_new(ctx);
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+    
+    if (doDTLS) {
+        SOCKADDR_IN_T addr;
+        build_addr(&addr, yasslIP, port, 1);
+        CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr));
+        tcp_socket(&sockfd, 1);
+    }
+    else {
+        tcp_connect(&sockfd, yasslIP, port, 0);
+    }
+        
+    SSL_set_fd(ssl, sockfd);
+#if defined(USE_WINDOWS_API) && defined(CYASSL_DTLS) && defined(NO_MAIN_DRIVER)
+    /* let echoserver bind first, TODO: add Windows signal like pthreads does */
+    Sleep(100);
+#endif
+
+    if (SSL_connect(ssl) != SSL_SUCCESS) err_sys("SSL_connect failed");
+
+    while (fgets(msg, sizeof(msg), fin) != 0) {
+     
+        sendSz = (int)strlen(msg);
+
+        if (SSL_write(ssl, msg, sendSz) != sendSz)
+            err_sys("SSL_write failed");
+
+        if (strncmp(msg, "quit", 4) == 0) {
+            fputs("sending server shutdown command: quit!\n", fout);
+            break;
+        }
+
+        if (strncmp(msg, "break", 5) == 0) {
+            fputs("sending server session close: break!\n", fout);
+            break;
+        }
+
+        #ifndef CYASSL_MDK_SHELL
+        while (sendSz) {
+            int got;
+            if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) {
+                reply[got] = 0;
+                fputs(reply, fout);
+                fflush(fout) ;
+                sendSz -= got;
+            }
+            else
+                break;
+        }
+        #else
+        {
+            int got;
+            if ( (got = SSL_read(ssl, reply, sizeof(reply)-1)) > 0) {
+                reply[got] = 0;
+                fputs(reply, fout);
+                fflush(fout) ;
+                sendSz -= got;
+            }
+        }
+        #endif
+    }
+
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+
+
+#ifdef CYASSL_DTLS
+    strncpy(msg, "break", 6);
+    sendSz = (int)strlen(msg);
+    /* try to tell server done */
+    SSL_write(ssl, msg, sendSz);
+#else
+    SSL_shutdown(ssl);
+#endif
+
+    SSL_free(ssl);
+    SSL_CTX_free(ctx);
+
+    fflush(fout);
+    if (inCreated)  fclose(fin);
+    if (outCreated) fclose(fout);
+
+    CloseSocket(sockfd);
+    ((func_args*)args)->return_code = 0; 
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+
+        if (CurrentDir("echoclient") || CurrentDir("build"))
+            ChangeDirBack(2);
+        echoclient_test(&args);
+
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+        
+#endif /* NO_MAIN_DRIVER */
+
+
diff --git a/IDE/MDK5-ARM/Projects/EchoClient/main.c b/IDE/MDK5-ARM/Projects/EchoClient/main.c
new file mode 100644
index 000000000..6df113137
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoClient/main.c
@@ -0,0 +1,101 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+#include "rl_net.h" 
+#include 
+#include "cyassl_MDK_ARM.h"
+#include 
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+  int32_t retv;
+
+  retv = finit ("M0:");
+  if (retv == 0) {
+    retv = fmount ("M0:");
+    if (retv == 0) {
+      printf ("Drive M0 ready!\n");
+    }
+    else {
+      printf ("Drive M0 mount failed!\n");
+    }
+  }
+  else {
+    printf ("Drive M0 initialization failed!\n");
+  }
+}
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+void tcp_poll (void const *arg)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        net_main ();
+        osDelay(1) ;
+    }
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+} func_args;
+
+extern void echoclient_test(func_args * args) ;
+extern void init_time(void) ;
+
+    osThreadDef (tcp_poll, osPriorityHigh , 1, 0) ;
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+int myoptind = 0;
+char* myoptarg = NULL;
+
+#include "config-EchoClient.h"
+
+int main() 
+{
+    void *args = NULL ;
+    init_time() ;
+    init_filesystem ();
+    net_initialize() ;
+    osThreadCreate (osThread (tcp_poll), NULL); 
+    osDelay(30000) ;  /* wait for DHCP */
+    #if defined(DEBUG_CYASSL)
+         printf("Turning ON Debug message\n") ;
+         CyaSSL_Debugging_ON() ;
+    #endif
+
+    echoclient_test(args) ;
+
+}
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt b/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt
new file mode 100644
index 000000000..d43c94a38
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/Abstract.txt
@@ -0,0 +1,24 @@
+This program is echo server with CyaSSL/wolfCrypt library.
+
+In order to run this program, 
+Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+Set the server IP address in Net_Config_ETH_0.h
+The server default port is 11111, defined in test.h.
+
+For further configuration, refer config-Crypt.h and config-CyaSSL.h.
+
+When testing this server, it is recommended to test against one of the standard 
+CyaSSL example applications running on a desktop machine.  The standard CyaSSL 
+example applications are located in the CyaSSL root directory under the 
+/examples directory.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com
+ 
\ No newline at end of file
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx
new file mode 100644
index 000000000..ba35f0f5c
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvoptx
@@ -0,0 +1,1406 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    EchoServer
+    0x4
+    ARM-ADS
+    
+      120000000
+      
+        1
+        1
+        0
+        1
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\Object\
+      
+      
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        1
+        0
+        0
+        0
+        0
+      
+      
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        SARMCM3.DLL
+        -REMAP -MPU
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
+        -REMAP -MPU
+        TCM.DLL
+        -pCM3
+      
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        0
+        8
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        .\STM32_SWO.ini
+        BIN\ULP2CM3.DLL
+      
+      
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          ULP2CM3
+          -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)
+        
+        
+          0
+          DLGUARM
+          
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+        
+      
+      
+      
+        
+          1
+          8
+          0x20000408
+        
+      
+      
+        
+          2
+          8
+          0x8004dc8
+        
+      
+      
+        0
+      
+      
+        0
+        0
+        1
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+        0
+        0
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+        0
+        0
+        0
+        0
+        0
+        0
+        0
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+        0
+        0
+      
+      
+      
+    
+  
+
+  
+    Source
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+    0
+    
+      1
+      1
+      1
+      0
+      0
+      0
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+      0
+      0
+      0
+      .\main.c
+      main.c
+      0
+      0
+    
+    
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+      0
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+      echoserver.c
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+  
+
+  
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+      0
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+      .\RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      0
+      0
+    
+    
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+      0
+      0
+      0
+      .\RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      0
+      0
+    
+  
+
+  
+    Documentation
+    1
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+    0
+    0
+    
+      3
+      5
+      5
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+      0
+      0
+      0
+      1
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+      .\Abstract.txt
+      Abstract.txt
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
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+    
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+      0
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+      RTX_CM3.lib
+      1
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+    
+    
+      4
+      7
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+      0
+      RTE\CMSIS\RTX_Conf_CM.c
+      RTX_Conf_CM.c
+      1
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+    
+  
+
+  
+    ::Device
+    0
+    0
+    0
+    1
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+      0
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+      0
+      0
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+      DMA_STM32F2xx.c
+      1
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+    
+    
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+      GPIO_STM32F2xx.c
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+      RTE_Device.h
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+      system_stm32f2xx.c
+      1
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+    
+  
+
+  
+    ::Drivers
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+    0
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+      13
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+      0
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+      PHY_ST802RT1.c
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+      EMAC_STM32F2xx.c
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+      MCI_STM32F2xx.c
+      1
+      0
+    
+  
+
+  
+    ::File System
+    0
+    0
+    0
+    1
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+      0
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+      RTE\File_System\FS_Config_MC_0.h
+      FS_Config_MC_0.h
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+    
+  
+
+  
+    ::Network
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+      Net_Dbg_CM3_L.lib
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+      0
+      0
+      0
+      0
+      RTE\Network\Net_Config_DNS_Client.h
+      Net_Config_DNS_Client.h
+      1
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+    
+    
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+      5
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+      0
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+      Net_Config_ETH_0.h
+      1
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+    
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+      Net_Config_TCP.h
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+    
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+      0
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+      RTE\Network\Net_Debug.c
+      Net_Debug.c
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+    
+  
+
+  
+    ::wolfSSL
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+    0
+    0
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+    
+      9
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+      0
+      0
+      0
+      0
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+      cyassl_MDK_ARM.c
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+    
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+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+      time-STM32F2xx.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c
+      arc4.c
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+      asm.c
+      1
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+    
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+      asn.c
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+    
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+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+      blake2b.c
+      1
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+    
+    
+      9
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+      camellia.c
+      1
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+    
+    
+      9
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+      0
+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+      coding.c
+      1
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+    
+    
+      9
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+      0
+      0
+      0
+      0
+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c
+      compress.c
+      1
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+    
+    
+      9
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+      0
+      0
+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
+      des3.c
+      1
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+    
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+      0
+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+      dh.c
+      1
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+    
+    
+      9
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+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+      dsa.c
+      1
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+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+      ecc.c
+      1
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+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+      ecc_fp.c
+      1
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+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+      error.c
+      1
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+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+      hc128.c
+      1
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+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+      hmac.c
+      1
+      0
+    
+    
+      9
+      45
+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+      integer.c
+      1
+      0
+    
+    
+      9
+      46
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+      logging.c
+      1
+      0
+    
+    
+      9
+      47
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+      md2.c
+      1
+      0
+    
+    
+      9
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+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+      md4.c
+      1
+      0
+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+      md5.c
+      1
+      0
+    
+    
+      9
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+      1
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+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+      memory.c
+      1
+      0
+    
+    
+      9
+      51
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+      misc.c
+      1
+      0
+    
+    
+      9
+      52
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+      pwdbased.c
+      1
+      0
+    
+    
+      9
+      53
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+      rabbit.c
+      1
+      0
+    
+    
+      9
+      54
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+      random.c
+      1
+      0
+    
+    
+      9
+      55
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+      ripemd.c
+      1
+      0
+    
+    
+      9
+      56
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+      rsa.c
+      1
+      0
+    
+    
+      9
+      57
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+      sha.c
+      1
+      0
+    
+    
+      9
+      58
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+      sha256.c
+      1
+      0
+    
+    
+      9
+      59
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+      sha512.c
+      1
+      0
+    
+    
+      9
+      60
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+      tfm.c
+      1
+      0
+    
+    
+      9
+      61
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+      crl.c
+      1
+      0
+    
+    
+      9
+      62
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+      internal.c
+      1
+      0
+    
+    
+      9
+      63
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+      io.c
+      1
+      0
+    
+    
+      9
+      64
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+      keys.c
+      1
+      0
+    
+    
+      9
+      65
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+      ocsp.c
+      1
+      0
+    
+    
+      9
+      66
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+      sniffer.c
+      1
+      0
+    
+    
+      9
+      67
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+      ssl.c
+      1
+      0
+    
+    
+      9
+      68
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+      tls.c
+      1
+      0
+    
+    
+      9
+      69
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      1
+      0
+    
+    
+      9
+      70
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      1
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+    
+    
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+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config.h
+      config.h
+      1
+      0
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx
new file mode 100644
index 000000000..b8ce12e1e
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/EchoServer.uvprojx
@@ -0,0 +1,1101 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      EchoServer
+      0x4
+      ARM-ADS
+      
+        
+          STM32F207IG
+          STMicroelectronics
+          IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+          0
+          $$Device:STM32F207IG$Device\Include\stm32f2xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F207IG$SVD\STM32F20x.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Object\
+          EchoServer
+          1
+          0
+          0
+          1
+          1
+          .\Object\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          -REMAP -MPU
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          8
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            .\STM32_SWO.ini
+            BIN\ULP2CM3.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4100
+          
+          1
+          BIN\ULP2CM3.DLL
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M3"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            0
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+            3
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+            1
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+            
+              
+                0
+                0x0
+                0x0
+              
+              
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+                0x0
+                0x0
+              
+              
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+              
+              
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+                0x0
+              
+              
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+              
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+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
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+                0x0
+              
+              
+                0
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+                0x0
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+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              HAVE_CONFIG_H  MDK_CONF_SimpleClient CYASSL_STM32F2xx
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source
+          
+            
+              main.c
+              1
+              .\main.c
+            
+            
+              echoserver.c
+              1
+              .\echoserver.c
+            
+          
+        
+        
+          Configuration
+          
+            
+              config-CyaSSL.h
+              5
+              .\RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config-Crypt.h
+              5
+              .\RTE\wolfSSL\config-Crypt.h
+            
+          
+        
+        
+          Documentation
+          
+            
+              Abstract.txt
+              5
+              .\Abstract.txt
+            
+          
+        
+        
+          ::CMSIS
+          
+            
+              RTX_CM3.lib
+              4
+              C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+            
+            
+              RTX_Conf_CM.c
+              1
+              RTE\CMSIS\RTX_Conf_CM.c
+            
+          
+        
+        
+          ::Device
+          
+            
+              DMA_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c
+            
+            
+              GPIO_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+            
+            
+              RTE_Device.h
+              5
+              RTE\Device\STM32F207IG\RTE_Device.h
+            
+            
+              startup_stm32f2xx.s
+              2
+              RTE\Device\STM32F207IG\startup_stm32f2xx.s
+            
+            
+              system_stm32f2xx.c
+              1
+              RTE\Device\STM32F207IG\system_stm32f2xx.c
+            
+          
+        
+        
+          ::Drivers
+          
+            
+              PHY_ST802RT1.c
+              1
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+            
+            
+              EMAC_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c
+            
+            
+              MCI_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c
+            
+          
+        
+        
+          ::File System
+          
+            
+              FS_LFN_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib
+            
+            
+              FS_Config.c
+              1
+              RTE\File_System\FS_Config.c
+            
+            
+              FS_Config_MC_0.h
+              5
+              RTE\File_System\FS_Config_MC_0.h
+            
+          
+        
+        
+          ::Network
+          
+            
+              Net_Dbg_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib
+            
+            
+              Net_Config.c
+              1
+              RTE\Network\Net_Config.c
+            
+            
+              Net_Config_BSD.h
+              5
+              RTE\Network\Net_Config_BSD.h
+            
+            
+              Net_Config_DNS_Client.h
+              5
+              RTE\Network\Net_Config_DNS_Client.h
+            
+            
+              Net_Config_ETH_0.h
+              5
+              RTE\Network\Net_Config_ETH_0.h
+            
+            
+              Net_Config_TCP.h
+              5
+              RTE\Network\Net_Config_TCP.h
+            
+            
+              Net_Config_UDP.h
+              5
+              RTE\Network\Net_Config_UDP.h
+            
+            
+              Net_Debug.c
+              1
+              RTE\Network\Net_Debug.c
+            
+          
+        
+        
+          ::wolfSSL
+          
+            
+              cyassl_MDK_ARM.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+            
+            
+              time-STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+            
+            
+              aes.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c
+            
+            
+              arc4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c
+            
+            
+              asm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+            
+            
+              asn.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+            
+            
+              blake2b.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+            
+            
+              camellia.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c
+            
+            
+              coding.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+            
+            
+              compress.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c
+            
+            
+              des3.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
+            
+            
+              dh.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+            
+            
+              dsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+            
+            
+              ecc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+            
+            
+              ecc_fp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+            
+            
+              error.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+            
+            
+              hc128.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+            
+            
+              hmac.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+            
+            
+              integer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+            
+            
+              logging.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+            
+            
+              md2.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+            
+            
+              md4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+            
+            
+              md5.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+            
+            
+              memory.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+            
+            
+              misc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+            
+            
+              pwdbased.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+            
+            
+              rabbit.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+            
+            
+              random.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+            
+            
+              ripemd.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+            
+            
+              rsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+            
+            
+              sha.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+            
+            
+              sha256.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+            
+            
+              sha512.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+            
+            
+              tfm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+            
+            
+              crl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+            
+            
+              internal.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+            
+            
+              io.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+            
+            
+              keys.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+            
+            
+              ocsp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+            
+            
+              sniffer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+            
+            
+              ssl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+            
+            
+              tls.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+            
+            
+              config-Crypt.h
+              5
+              RTE\wolfSSL\config-Crypt.h
+            
+            
+              config-CyaSSL.h
+              5
+              RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config.h
+              5
+              RTE\wolfSSL\config.h
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        RTE\CMSIS\RTX_Conf_CM.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\RTE_Device.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\startup_stm32f2xx.s
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\system_stm32f2xx.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config_MC_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_BSD.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_DNS_Client.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_ETH_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_TCP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_UDP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Debug.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Other\config-Crypt.h
+        
+        
+        
+      
+      
+        RTE\Other\config-CyaSSL.h
+        
+        
+        
+      
+      
+        RTE\Other\config-RTX-TCP-FS.h
+        
+        
+        
+      
+      
+        RTE\Other\config.h
+        
+        
+        
+      
+      
+        RTE\wolfSSL\config-Crypt.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config-CyaSSL.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config.h
+        
+        
+        
+          
+        
+      
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/CMSIS/RTX_Conf_CM.c
new file mode 100644
index 000000000..54b3e0bfc
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/CMSIS/RTX_Conf_CM.c
@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// Thread Configuration
+// =======================
+//
+//   Number of concurrent running threads <0-250>
+//    Defines max. number of threads that will run at the same time.
+//    Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     5
+#endif
+
+//   Default Thread stack size [bytes] <64-4096:8><#/4>
+//    Defines default stack size for threads with osThreadDef stacksz = 0
+//    Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     250
+#endif
+
+//   Main Thread stack size [bytes] <64-20000:8><#/4>
+//    Defines stack size for main thread.
+//    Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 2000
+#endif
+
+//   Number of threads with user-provided stack size <0-250>
+//    Defines the number of threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     2
+#endif
+
+//   Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4>
+//    Defines the combined stack size for threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 2500
+#endif
+
+// Check for stack overflow
+//  Includes the stack checking code for stack overflow.
+//  Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+//  Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// 
+
+// RTX Kernel Timer Tick Configuration
+// ======================================
+//  Use Cortex-M SysTick timer as RTX Kernel Timer
+//  Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   Timer clock value [Hz] <1-1000000000>
+//    Defines the timer clock value.
+//    Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   Timer tick value [us] <1-1000000>
+//    Defines the timer tick value.
+//    Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// 
+
+// System Configuration
+// =======================
+//
+// Round-Robin Thread switching
+// ===============================
+//
+//  Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   Round-Robin Timeout [ticks] <1-1000>
+//    Defines how long a thread will execute before a thread switch.
+//    Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// 
+
+// User Timers
+// ==============
+//    Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//    Defines priority for Timer Thread
+//    Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   Timer Thread stack size [bytes] <64-64000:8><#/4>
+//    Defines stack size for Timer thread.
+//    Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   Timer Callback Queue size <1-32>
+//    Number of concurrent active timer callback functions.
+//    Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// 
+
+//   ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//    ISR functions store requests to this buffer,
+//    when they are called from the interrupt handler.
+//    Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// 
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h
new file mode 100644
index 000000000..4a09246f3
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h
@@ -0,0 +1,3127 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *  
+ * $Date:        27. June 2013
+ * $Revision:    V1.01
+ *  
+ * Project:      RTE Device Configuration for ST STM32F2xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  (num == 7) ? GPIOH : \
+  (num == 8) ? GPIOI : \
+  NULL)
+
+
+//  Clock Configuration
+//    High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         16000000
+//    High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//    System Clock <1-999999999>
+#define RTE_SYSCLK                      120000000
+//    AHB Clock    <1-999999999>
+#define RTE_HCLK                        120000000
+//    APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       30000000
+//    APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       60000000
+//       48MHz Clock
+#define RTE_PLL48CK                     48000000
+// 
+
+
+//  USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1]
+//  Configuration settings for Driver_UART1 in component ::Drivers:UART
+#define RTE_USART1                      0
+
+//    USART1_TX Pin <0=>PA9 <1=>PB6
+#define RTE_USART1_TX_ID                0
+#if    (RTE_USART1_TX_ID == 0)
+#define RTE_USART1_TX_PORT              GPIOA
+#define RTE_USART1_TX_BIT               9
+#elif  (RTE_USART1_TX_ID == 1)
+#define RTE_USART1_TX_PORT              GPIOB
+#define RTE_USART1_TX_BIT               6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//    USART1_RX Pin <0=>PA10 <1=>PB7
+#define RTE_USART1_RX_ID                0
+#if    (RTE_USART1_RX_ID == 0)
+#define RTE_USART1_RX_PORT              GPIOA
+#define RTE_USART1_RX_BIT               10
+#elif  (RTE_USART1_RX_ID == 1)
+#define RTE_USART1_RX_PORT              GPIOB
+#define RTE_USART1_RX_BIT               7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART1_CK Pin <0=>PA8
+//     
+#define RTE_USART1_CK                   0
+#define RTE_USART1_CK_ID                0
+#if    (RTE_USART1_CK_ID == 0)
+#define RTE_USART1_CK_PORT              GPIOA
+#define RTE_USART1_CK_BIT               8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART1_CTS Pin <0=>PA11
+//        USART1_RTS Pin <0=>PA12
+//        Manual CTS/RTS
+//     
+#define RTE_USART1_HW_FLOW              0
+#define RTE_USART1_CTS_ID               0
+#define RTE_USART1_RTS_ID               0
+#define RTE_USART1_MANUAL_FLOW          0
+#if    (RTE_USART1_CTS_ID == 0)
+#define RTE_USART1_CTS_PORT             GPIOA
+#define RTE_USART1_CTS_BIT              11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART1_RTS_ID == 0)
+#define RTE_USART1_RTS_PORT             GPIOA
+#define RTE_USART1_RTS_BIT              12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <2=>2 <5=>5
+//       Selects DMA Stream (only Stream 2 or 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_RX_DMA               1
+#define RTE_USART1_RX_DMA_NUMBER        2
+#define RTE_USART1_RX_DMA_STREAM        2
+#define RTE_USART1_RX_DMA_CHANNEL       4
+#define RTE_USART1_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_TX_DMA               1
+#define RTE_USART1_TX_DMA_NUMBER        2
+#define RTE_USART1_TX_DMA_STREAM        7
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2]
+//  Configuration settings for Driver_UART2 in component ::Drivers:UART
+#define RTE_USART2                      0
+
+//    USART2_TX Pin <0=>PA2 <1=>PD5
+#define RTE_USART2_TX_ID                0
+#if    (RTE_USART2_TX_ID == 0)
+#define RTE_USART2_TX_PORT              GPIOA
+#define RTE_USART2_TX_BIT               2
+#elif  (RTE_USART2_TX_ID == 1)
+#define RTE_USART2_TX_PORT              GPIOD
+#define RTE_USART2_TX_BIT               5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//    USART2_RX Pin <0=>PA3 <1=>PD6
+#define RTE_USART2_RX_ID                0
+#if    (RTE_USART2_RX_ID == 0)
+#define RTE_USART2_RX_PORT              GPIOA
+#define RTE_USART2_RX_BIT               3
+#elif  (RTE_USART2_RX_ID == 1)
+#define RTE_USART2_RX_PORT              GPIOD
+#define RTE_USART2_RX_BIT               6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART2_CK Pin <0=>PA4 <1=>PD7
+//     
+#define RTE_USART2_CK                   0
+#define RTE_USART2_CK_ID                0
+#if    (RTE_USART2_CK_ID == 0)
+#define RTE_USART2_CK_PORT              GPIOA
+#define RTE_USART2_CK_BIT               4
+#elif  (RTE_USART2_CK_ID == 1)
+#define RTE_USART2_CK_PORT              GPIOD
+#define RTE_USART2_CK_BIT               7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART2_CTS Pin <0=>PA0 <1=>PD3
+//        USART2_RTS Pin <0=>PA1 <1=>PD4
+//        Manual CTS/RTS
+//     
+#define RTE_USART2_HW_FLOW              0
+#define RTE_USART2_CTS_ID               0
+#define RTE_USART2_RTS_ID               0
+#define RTE_USART2_MANUAL_FLOW          0
+#if    (RTE_USART2_CTS_ID == 0)
+#define RTE_USART2_CTS_PORT             GPIOA
+#define RTE_USART2_CTS_BIT              0
+#elif  (RTE_USART2_CTS_ID == 1)
+#define RTE_USART2_CTS_PORT             GPIOD
+#define RTE_USART2_CTS_BIT              3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART2_RTS_ID == 0)
+#define RTE_USART2_RTS_PORT             GPIOA
+#define RTE_USART2_RTS_BIT              1
+#elif  (RTE_USART2_RTS_ID == 1)
+#define RTE_USART2_RTS_PORT             GPIOD
+#define RTE_USART2_RTS_BIT              4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5
+//       Selects DMA Stream (only Stream 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_RX_DMA               1
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_STREAM        5
+#define RTE_USART2_RX_DMA_CHANNEL       4
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6
+//       Selects DMA Stream (only Stream 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_TX_DMA               1
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_STREAM        6
+#define RTE_USART2_TX_DMA_CHANNEL       4
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3]
+//  Configuration settings for Driver_UART3 in component ::Drivers:UART
+#define RTE_USART3                      0
+
+//    USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8
+#define RTE_USART3_TX_ID                0
+#if    (RTE_USART3_TX_ID == 0)
+#define RTE_USART3_TX_PORT              GPIOB
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 1)
+#define RTE_USART3_TX_PORT              GPIOC
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 2)
+#define RTE_USART3_TX_PORT              GPIOD
+#define RTE_USART3_TX_BIT               8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//    USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9
+#define RTE_USART3_RX_ID                0
+#if    (RTE_USART3_RX_ID == 0)
+#define RTE_USART3_RX_PORT              GPIOB
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 1)
+#define RTE_USART3_RX_PORT              GPIOC
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 2)
+#define RTE_USART3_RX_PORT              GPIOD
+#define RTE_USART3_RX_BIT               9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10
+//     
+#define RTE_USART3_CK                   0
+#define RTE_USART3_CK_ID                0
+#if    (RTE_USART3_CK_ID == 0)
+#define RTE_USART3_CK_PORT              GPIOB
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 1)
+#define RTE_USART3_CK_PORT              GPIOC
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 2)
+#define RTE_USART3_CK_PORT              GPIOD
+#define RTE_USART3_CK_BIT               10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART3_CTS Pin <0=>PB13 <1=>PD11
+//        USART3_RTS Pin <0=>PB14 <1=>PD12
+//        Manual CTS/RTS
+//     
+#define RTE_USART3_HW_FLOW              0
+#define RTE_USART3_CTS_ID               0
+#define RTE_USART3_RTS_ID               0
+#define RTE_USART3_MANUAL_FLOW          0
+#if    (RTE_USART3_CTS_ID == 0)
+#define RTE_USART3_CTS_PORT             GPIOB
+#define RTE_USART3_CTS_BIT              13
+#elif  (RTE_USART3_CTS_ID == 1)
+#define RTE_USART3_CTS_PORT             GPIOD
+#define RTE_USART3_CTS_BIT              11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART3_RTS_ID == 0)
+#define RTE_USART3_RTS_PORT             GPIOB
+#define RTE_USART3_RTS_BIT              14
+#elif  (RTE_USART3_RTS_ID == 1)
+#define RTE_USART3_RTS_PORT             GPIOD
+#define RTE_USART3_RTS_BIT              12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <1=>1
+//       Selects DMA Stream (only Stream 1 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_RX_DMA               1
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_STREAM        1
+#define RTE_USART3_RX_DMA_CHANNEL       4
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_TX_DMA               1
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_STREAM        3
+#define RTE_USART3_TX_DMA_CHANNEL       4
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  UART4 (Universal asynchronous receiver transmitter) [Driver_UART4]
+//  Configuration settings for Driver_UART4 in component ::Drivers:UART
+#define RTE_UART4                       0
+
+//    UART4_TX Pin <0=>PA0 <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX_PORT               GPIOA
+#define RTE_UART4_TX_BIT                0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//    UART4_RX Pin <0=>PA1 <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX_PORT               GPIOA
+#define RTE_UART4_RX_BIT                1
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_RX_DMA                1
+#define RTE_UART4_RX_DMA_NUMBER         1
+#define RTE_UART4_RX_DMA_STREAM         2
+#define RTE_UART4_RX_DMA_CHANNEL        4
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_TX_DMA                1
+#define RTE_UART4_TX_DMA_NUMBER         1
+#define RTE_UART4_TX_DMA_STREAM         4
+#define RTE_UART4_TX_DMA_CHANNEL        4
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  UART5 (Universal asynchronous receiver transmitter) [Driver_UART5]
+//  Configuration settings for Driver_UART5 in component ::Drivers:UART
+#define RTE_UART5                       0
+
+//    UART5_TX Pin <0=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//    UART5_RX Pin <0=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0
+//       Selects DMA Stream (only Stream 0 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_RX_DMA                1
+#define RTE_UART5_RX_DMA_NUMBER         1
+#define RTE_UART5_RX_DMA_STREAM         0
+#define RTE_UART5_RX_DMA_CHANNEL        4
+#define RTE_UART5_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_TX_DMA                1
+#define RTE_UART5_TX_DMA_NUMBER         1
+#define RTE_UART5_TX_DMA_STREAM         7
+#define RTE_UART5_TX_DMA_CHANNEL        4
+#define RTE_UART5_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6]
+//  Configuration settings for Driver_UART6 in component ::Drivers:UART
+#define RTE_USART6                      0
+
+//    USART6_TX Pin <0=>PC6 <1=>PG14
+#define RTE_USART6_TX_ID                0
+#if    (RTE_USART6_TX_ID == 0)
+#define RTE_USART6_TX_PORT              GPIOC
+#define RTE_USART6_TX_BIT               6
+#elif  (RTE_USART6_TX_ID == 1)
+#define RTE_USART6_TX_PORT              GPIOG
+#define RTE_USART6_TX_BIT               14
+#else
+#error "Invalid USART6_TX Pin Configuration!"
+#endif
+
+//    USART6_RX Pin <0=>PC7 <1=>PG9
+#define RTE_USART6_RX_ID                0
+#if    (RTE_USART6_RX_ID == 0)
+#define RTE_USART6_RX_PORT              GPIOC
+#define RTE_USART6_RX_BIT               7
+#elif  (RTE_USART6_RX_ID == 1)
+#define RTE_USART6_RX_PORT              GPIOG
+#define RTE_USART6_RX_BIT               9
+#else
+#error "Invalid USART6_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART6_CK Pin <0=>PC8 <1=>PG7
+//     
+#define RTE_USART6_CK                   0
+#define RTE_USART6_CK_ID                0
+#if    (RTE_USART6_CK_ID == 0)
+#define RTE_USART6_CK_PORT              GPIOC
+#define RTE_USART6_CK_BIT               8
+#elif  (RTE_USART6_CK_ID == 1)
+#define RTE_USART6_CK_PORT              GPIOG
+#define RTE_USART6_CK_BIT               7
+#else
+#error "Invalid USART6_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART6_CTS Pin <0=>PG13 <1=>PG15
+//        USART6_RTS Pin <0=>PG8  <1=>PG12
+//        Manual CTS/RTS
+//     
+#define RTE_USART6_HW_FLOW              0
+#define RTE_USART6_CTS_ID               0
+#define RTE_USART6_RTS_ID               0
+#define RTE_USART6_MANUAL_FLOW          0
+#if    (RTE_USART6_CTS_ID == 0)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              13
+#elif  (RTE_USART6_CTS_ID == 1)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              15
+#else
+#error "Invalid USART6_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART6_RTS_ID == 0)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              8
+#elif  (RTE_USART6_RTS_ID == 1)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              12
+#else
+#error "Invalid USART6_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <1=>1 <2=>2
+//       Selects DMA Stream (only Stream 1 or 2 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_RX_DMA               1
+#define RTE_USART6_RX_DMA_NUMBER        2
+#define RTE_USART6_RX_DMA_STREAM        1
+#define RTE_USART6_RX_DMA_CHANNEL       5
+#define RTE_USART6_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_TX_DMA               1
+#define RTE_USART6_TX_DMA_NUMBER        2
+#define RTE_USART6_TX_DMA_STREAM        6
+#define RTE_USART6_TX_DMA_CHANNEL       5
+#define RTE_USART6_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+//  Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1                        0
+
+//    I2C1_SCL Pin <0=>PB6 <1=>PB8
+#define RTE_I2C1_SCL_PORT_ID            0
+#if    (RTE_I2C1_SCL_PORT_ID == 0)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                6
+#elif  (RTE_I2C1_SCL_PORT_ID == 1)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//    I2C1_SDA Pin <0=>PB7 <1=>PB9
+#define RTE_I2C1_SDA_PORT_ID            0
+#if    (RTE_I2C1_SDA_PORT_ID == 0)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                7
+#elif  (RTE_I2C1_SDA_PORT_ID == 1)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                9
+#else
+#error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <5=>5
+//       Selects DMA Stream (only Stream 0 or 5 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_RX_DMA                 1
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_STREAM          0
+#define RTE_I2C1_RX_DMA_CHANNEL         1
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_TX_DMA                 1
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_STREAM          6
+#define RTE_I2C1_TX_DMA_CHANNEL         1
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+//  Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2                        0
+
+//    I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOF
+#define RTE_I2C2_SCL_BIT                1
+#elif  (RTE_I2C2_SCL_PORT_ID == 1)
+#define RTE_I2C2_SCL_PORT               GPIOH
+#define RTE_I2C2_SCL_BIT                4
+#elif  (RTE_I2C2_SCL_PORT_ID == 2)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOF
+#define RTE_I2C2_SDA_BIT                0
+#elif  (RTE_I2C2_SDA_PORT_ID == 1)
+#define RTE_I2C2_SDA_PORT               GPIOH
+#define RTE_I2C2_SDA_BIT                5
+#elif  (RTE_I2C2_SDA_PORT_ID == 2)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2 <3=>3
+//       Selects DMA Stream (only Stream 2 or 3 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 7 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_STREAM          2
+#define RTE_I2C2_RX_DMA_CHANNEL         7
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_STREAM          7
+#define RTE_I2C2_TX_DMA_CHANNEL         7
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3]
+//  Configuration settings for Driver_I2C3 in component ::Drivers:I2C
+#define RTE_I2C3                        0
+
+//    I2C3_SCL Pin <0=>PH7 <1=>PA8
+#define RTE_I2C3_SCL_PORT_ID            0
+#if    (RTE_I2C3_SCL_PORT_ID == 0)
+#define RTE_I2C3_SCL_PORT               GPIOH
+#define RTE_I2C3_SCL_BIT                7
+#elif  (RTE_I2C3_SCL_PORT_ID == 1)
+#define RTE_I2C3_SCL_PORT               GPIOA
+#define RTE_I2C3_SCL_BIT                8
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    I2C3_SDA Pin <0=>PH8 <1=>PC9
+#define RTE_I2C3_SDA_PORT_ID            0
+#if    (RTE_I2C3_SDA_PORT_ID == 0)
+#define RTE_I2C3_SDA_PORT               GPIOH
+#define RTE_I2C3_SDA_BIT                8
+#elif  (RTE_I2C3_SDA_PORT_ID == 1)
+#define RTE_I2C3_SDA_PORT               GPIOC
+#define RTE_I2C3_SDA_BIT                9
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_RX_DMA                 1
+#define RTE_I2C3_RX_DMA_NUMBER          1
+#define RTE_I2C3_RX_DMA_STREAM          2
+#define RTE_I2C3_RX_DMA_CHANNEL         3
+#define RTE_I2C3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_TX_DMA                 1
+#define RTE_I2C3_TX_DMA_NUMBER          1
+#define RTE_I2C3_TX_DMA_STREAM          4
+#define RTE_I2C3_TX_DMA_CHANNEL         3
+#define RTE_I2C3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+//  Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1                        0
+
+//    SPI1_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//    SPI1_SCK Pin <0=>PA5 <1=>PB3
+#define RTE_SPI1_SCL_PORT_ID            0
+#if    (RTE_SPI1_SCL_PORT_ID == 0)
+#define RTE_SPI1_SCL_PORT               GPIOA
+#define RTE_SPI1_SCL_BIT                5
+#elif  (RTE_SPI1_SCL_PORT_ID == 1)
+#define RTE_SPI1_SCL_PORT               GPIOB
+#define RTE_SPI1_SCL_BIT                3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//    SPI1_MISO Pin <0=>PA6 <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID           0
+#if    (RTE_SPI1_MISO_PORT_ID == 0)
+#define RTE_SPI1_MISO_PORT              GPIOA
+#define RTE_SPI1_MISO_BIT               6
+#elif  (RTE_SPI1_MISO_PORT_ID == 1)
+#define RTE_SPI1_MISO_PORT              GPIOB
+#define RTE_SPI1_MISO_BIT               4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    SPI1_MOSI Pin <0=>PA7 <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID           0
+#if    (RTE_SPI1_MOSI_PORT_ID == 0)
+#define RTE_SPI1_MOSI_PORT              GPIOA
+#define RTE_SPI1_MOSI_BIT               7
+#elif  (RTE_SPI1_MOSI_PORT_ID == 1)
+#define RTE_SPI1_MOSI_PORT              GPIOB
+#define RTE_SPI1_MOSI_BIT               5
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_RX_DMA                 1
+#define RTE_SPI1_RX_DMA_NUMBER          2
+#define RTE_SPI1_RX_DMA_STREAM          0
+#define RTE_SPI1_RX_DMA_CHANNEL         3
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <5=>5
+//       Selects DMA Stream (only Stream 3 or 5 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_TX_DMA                 1
+#define RTE_SPI1_TX_DMA_NUMBER          2
+#define RTE_SPI1_TX_DMA_STREAM          5
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+//  Configuration settings for Driver_SPI2 in component ::Drivers:SPI
+#define RTE_SPI2                        0
+
+//    SPI2_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//    SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1
+#define RTE_SPI2_SCL_PORT_ID            0
+#if    (RTE_SPI2_SCL_PORT_ID == 0)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                10
+#elif  (RTE_SPI2_SCL_PORT_ID == 1)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                13
+#elif  (RTE_SPI2_SCL_PORT_ID == 2)
+#define RTE_SPI2_SCL_PORT               GPIOI
+#define RTE_SPI2_SCL_BIT                1
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//    SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO_PORT              GPIOC
+#define RTE_SPI2_MISO_BIT               2
+#elif  (RTE_SPI2_MISO_PORT_ID == 2)
+#define RTE_SPI2_MISO_PORT              GPIOI
+#define RTE_SPI2_MISO_BIT               2
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI_PORT              GPIOC
+#define RTE_SPI2_MOSI_BIT               3
+#elif  (RTE_SPI2_MOSI_PORT_ID == 2)
+#define RTE_SPI2_MOSI_PORT              GPIOI
+#define RTE_SPI2_MOSI_BIT               3
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_RX_DMA                 1
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_STREAM          2
+#define RTE_SPI2_RX_DMA_CHANNEL         0
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_TX_DMA                 1
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_STREAM          3
+#define RTE_SPI2_TX_DMA_CHANNEL         0
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+//  Configuration settings for Driver_SPI3 in component ::Drivers:SPI
+#define RTE_SPI3                        0
+
+//    SPI3_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//    SPI3_SCK Pin <0=>PB3 <1=>PC10
+#define RTE_SPI3_SCL_PORT_ID            0
+#if    (RTE_SPI3_SCL_PORT_ID == 0)
+#define RTE_SPI3_SCL_PORT               GPIOB
+#define RTE_SPI3_SCL_BIT                3
+#elif  (RTE_SPI3_SCL_PORT_ID == 1)
+#define RTE_SPI3_SCL_PORT               GPIOC
+#define RTE_SPI3_SCL_BIT                10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//    SPI3_MISO Pin <0=>PB4 <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID           0
+#if    (RTE_SPI3_MISO_PORT_ID == 0)
+#define RTE_SPI3_MISO_PORT              GPIOB
+#define RTE_SPI3_MISO_BIT               4
+#elif  (RTE_SPI3_MISO_PORT_ID == 1)
+#define RTE_SPI3_MISO_PORT              GPIOC
+#define RTE_SPI3_MISO_BIT               11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    SPI3_MOSI Pin <0=>PB5 <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID           0
+#if    (RTE_SPI3_MOSI_PORT_ID == 0)
+#define RTE_SPI3_MOSI_PORT              GPIOB
+#define RTE_SPI3_MOSI_BIT               5
+#elif  (RTE_SPI3_MOSI_PORT_ID == 1)
+#define RTE_SPI3_MOSI_PORT              GPIOC
+#define RTE_SPI3_MOSI_BIT               12
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_RX_DMA                 1
+#define RTE_SPI3_RX_DMA_NUMBER          1
+#define RTE_SPI3_RX_DMA_STREAM          0
+#define RTE_SPI3_RX_DMA_CHANNEL         0
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5 <7=>7
+//       Selects DMA Stream (only Stream 5 or 7 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_TX_DMA                 1
+#define RTE_SPI3_TX_DMA_NUMBER          1
+#define RTE_SPI3_TX_DMA_STREAM          5
+#define RTE_SPI3_TX_DMA_CHANNEL         0
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SDIO (Secure Digital Input/Output) [Driver_MCI0]
+//  Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDIO                        1
+
+//    SDIO_CD (Card Detect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_CD_PIN                 1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(7)
+#define RTE_SDIO_CD_BIT                 15
+
+//    SDIO_WP (Write Protect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_WP_PIN                 0
+#define RTE_SDIO_WP_ACTIVE              0
+#define RTE_SDIO_WP_PORT                GPIO_PORT(7)
+#define RTE_SDIO_WP_BIT                 16
+
+//    SDIO Bus
+//      SDIO_CK Pin <0=>PC12
+#define RTE_SDIO_CK_PORT_ID             0
+#if    (RTE_SDIO_CK_PORT_ID == 0)
+#define RTE_SDIO_CK_PORT                GPIOC
+#define RTE_SDIO_CK_PIN                 12
+#else
+#error "Invalid SDIO_CK Pin Configuration!"
+#endif
+//      SDIO_CMD Pin <0=>PD2
+#define RTE_SDIO_CMD_PORT_ID            0
+#if    (RTE_SDIO_CMD_PORT_ID == 0)
+#define RTE_SDIO_CMD_PORT               GPIOD
+#define RTE_SDIO_CMD_PIN                2
+#else
+#error "Invalid SDIO_CDM Pin Configuration!"
+#endif
+//      SDIO_D0 Pin <0=>PC8
+#define RTE_SDIO_D0_PORT_ID             0
+#if    (RTE_SDIO_D0_PORT_ID == 0)
+#define RTE_SDIO_D0_PORT                GPIOC
+#define RTE_SDIO_D0_PIN                 8
+#else
+#error "Invalid SDIO_D0 Pin Configuration!"
+#endif
+//      SDIO_D1 Pin <0=>PC9
+#define RTE_SDIO_D1_PORT_ID             0
+#if    (RTE_SDIO_D1_PORT_ID == 0)
+#define RTE_SDIO_D1_PORT                GPIOC
+#define RTE_SDIO_D1_PIN                 9
+#else
+#error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//      SDIO_D2 Pin <0=>PC10
+#define RTE_SDIO_D2_PORT_ID             0
+#if    (RTE_SDIO_D2_PORT_ID == 0)
+#define RTE_SDIO_D2_PORT                GPIOC
+#define RTE_SDIO_D2_PIN                 10
+#else
+#error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//      SDIO_D3 Pin <0=>PC11
+#define RTE_SDIO_D3_PORT_ID             0
+#if    (RTE_SDIO_D3_PORT_ID == 0)
+#define RTE_SDIO_D3_PORT                GPIOC
+#define RTE_SDIO_D3_PIN                 11
+#else
+#error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//      SDIO_D4 Pin <0=>PB8
+#define RTE_SDIO_D4_PORT_ID             0
+#if    (RTE_SDIO_D4_PORT_ID == 0)
+#define RTE_SDIO_D4_PORT                GPIOB
+#define RTE_SDIO_D4_PIN                 8
+#else
+#error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//      SDIO_D5 Pin <0=>PB9
+#define RTE_SDIO_D5_PORT_ID             0
+#if    (RTE_SDIO_D5_PORT_ID == 0)
+#define RTE_SDIO_D5_PORT                GPIOB
+#define RTE_SDIO_D5_PIN                 9
+#else
+#error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//      SDIO_D6 Pin <0=>PC6
+#define RTE_SDIO_D6_PORT_ID             0
+#if    (RTE_SDIO_D6_PORT_ID == 0)
+#define RTE_SDIO_D6_PORT                GPIOC
+#define RTE_SDIO_D6_PIN                 6
+#else
+#error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//      SDIO_D7 Pin <0=>PC7
+#define RTE_SDIO_D7_PORT_ID             0
+#if    (RTE_SDIO_D7_PORT_ID == 0)
+#define RTE_SDIO_D7_PORT                GPIOC
+#define RTE_SDIO_D7_PIN                 7
+#else
+#error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//   
+
+//    DMA
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <6=>6
+//       Selects DMA Stream (only Stream 3 or 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SDIO_DMA                    1
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_STREAM             3
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// 
+
+
+//  ETH (Ethernet Interface) [Driver_ETH_MAC0]
+//  Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define RTE_ETH                         1
+
+//    MII (Media Independent Interface)
+#define RTE_ETH_MII                     0
+
+//      ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#elif  (RTE_ETH_MII_TXD0_PORT_ID == 1)
+#define RTE_ETH_MII_TXD0_PORT           GPIOG
+#define RTE_ETH_MII_TXD0_PIN            13
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//      ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#elif  (RTE_ETH_MII_TXD1_PORT_ID == 1)
+#define RTE_ETH_MII_TXD1_PORT           GPIOG
+#define RTE_ETH_MII_TXD1_PIN            14
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//      ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//      ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#elif  (RTE_ETH_MII_TXD3_PORT_ID == 1)
+#define RTE_ETH_MII_TXD3_PORT           GPIOE
+#define RTE_ETH_MII_TXD3_PIN            2
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//      ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#elif  (RTE_ETH_MII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOG
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//      ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_PORT_ID        0
+#if    (RTE_ETH_MII_RXD0_PORT_ID == 0)
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+//      ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_PORT_ID        0
+#if    (RTE_ETH_MII_RXD1_PORT_ID == 0)
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+//      ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6
+#define RTE_ETH_MII_RXD2_PORT_ID        0
+#if    (RTE_ETH_MII_RXD2_PORT_ID == 0)
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif  (RTE_ETH_MII_RXD2_PORT_ID == 1)
+#define RTE_ETH_MII_RXD2_PORT           GPIOH
+#define RTE_ETH_MII_RXD2_PIN            6
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+//      ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7
+#define RTE_ETH_MII_RXD3_PORT_ID        0
+#if    (RTE_ETH_MII_RXD3_PORT_ID == 0)
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RXD3_PORT           GPIOH
+#define RTE_ETH_MII_RXD3_PIN            7
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+//      ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_PORT_ID       0
+#if    (RTE_ETH_MII_RX_DV_PORT_ID == 0)
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+//      ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOI
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//      ETH_MII_CRS Pin <0=>PA0 <1=>PH2
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#elif  (RTE_ETH_MII_CRS_PORT_ID == 1)
+#define RTE_ETH_MII_CRS_PORT            GPIOH
+#define RTE_ETH_MII_CRS_PIN             2
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//      ETH_MII_COL Pin <0=>PA3 <1=>PH3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#elif  (RTE_ETH_MII_COL_PORT_ID == 1)
+#define RTE_ETH_MII_COL_PORT            GPIOH
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//   
+
+//    RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    1
+
+//      ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_RMII_TXD0_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#elif  (RTE_ETH_RMII_TXD0_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOG
+#define RTE_ETH_RMII_TXD0_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_RMII_TXD1_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#elif  (RTE_ETH_RMII_TXD1_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOG
+#define RTE_ETH_RMII_TXD1_PIN           14
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      1
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#elif  (RTE_ETH_RMII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOG
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//      ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//      ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_PORT_ID     0
+#if    (RTE_ETH_RMII_CRS_DV_PORT_ID == 0)
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   
+
+//    Management Data Interface
+//      ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//      ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   
+
+//    Reference 25MHz/50MHz Clock generation
+#define RTE_ETH_REF_CLOCK               0
+
+//      MCO Pin <0=>PA2 <1=>PC9
+#define RTE_ETH_REF_CLOCK_PORT_ID       0
+#if    (RTE_ETH_REF_CLOCK_PORT_ID == 0)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOA
+#define RTE_ETH_REF_CLOCK_PIN           8
+#elif  (RTE_ETH_REF_CLOCK_PORT_ID == 1)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOC
+#define RTE_ETH_REF_CLOCK_PIN           9
+#else
+#error "Invalid MCO Pin Configuration!"
+#endif
+
+//   
+
+// 
+
+
+//  USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//    Device [Driver_USBD0]
+//    Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_OTG_FS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_FS_DEV_EP           0x0000000F
+#define RTE_USB_OTG_FS_DEV_EP_BULK      0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_INT       0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_ISO       0x000E000E
+
+//   
+
+//    Host [Driver_USBH0]
+//    Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(7)
+#define RTE_OTG_FS_VBUS_BIT             5
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_FS_OC_BIT               11
+//   
+
+// 
+
+
+//  USB OTG High-speed
+#define RTE_USB_OTG_HS                  0
+
+//    PHY (Physical Layer)
+
+//      PHY Interface
+//       <0=>On-chip full-speed PHY
+//       <1=>External ULPI high-speed PHY
+#define RTE_USB_OTG_HS_PHY              1
+
+//      External ULPI Pins (UTMI+ Low Pin Interface)
+
+//        OTG_HS_ULPI_CK Pin <0=>PA5
+#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_CK_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_CK_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_CK Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOI
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     11
+#elif  (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     2
+#else
+#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_STP Pin <0=>PC0
+#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_STP_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_STP_PIN     0
+#else
+#error "Invalid OTG_HS_ULPI_STP Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1
+#if    (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     2
+#elif  (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOH
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     4
+#else
+#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D0 Pin <0=>PA3
+#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D0_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_D0_PIN      3
+#else
+#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D1 Pin <0=>PB0
+#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D1_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D1_PIN      0
+#else
+#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D2 Pin <0=>PB1
+#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D2_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D2_PIN      1
+#else
+#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D3 Pin <0=>PB10
+#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D3_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D3_PIN      10
+#else
+#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D4 Pin <0=>PB11
+#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D4_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D4_PIN      11
+#else
+#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D5 Pin <0=>PB12
+#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D5_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D5_PIN      12
+#else
+#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D6 Pin <0=>PB13
+#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D6_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D6_PIN      13
+#else
+#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D7 Pin <0=>PB5
+#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D7_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D7_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!"
+#endif
+
+//     
+
+//   
+
+//    Device [Driver_USBD1]
+//    Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+#define RTE_USB_OTG_HS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 4
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 5
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_HS_DEV_EP           0x0000003F
+#define RTE_USB_OTG_HS_DEV_EP_BULK      0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_INT       0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_ISO       0x003E003E
+
+//   
+
+//    Host [Driver_USBH1]
+//    Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define RTE_USB_OTG_HS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_VBUS_PIN             1
+#define RTE_OTG_HS_VBUS_ACTIVE          0
+#define RTE_OTG_HS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_HS_VBUS_BIT             2
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_OC_PIN               1
+#define RTE_OTG_HS_OC_ACTIVE            0
+#define RTE_OTG_HS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_HS_OC_BIT               12
+//   
+
+// 
+
+
+//  EXTI (External Interrupt/Event Controller)
+#define RTE_EXTI                        0
+
+//    EXTI0 Line
+#define RTE_EXTI0                       0
+//      Pin   <0=>PA0  <1=>PB0  <2=>PC0  <3=>PD0  <4=>PE0  <5=>PF0  <6=>PG0  <7=>PH0  <8=>PI0
+#define RTE_EXTI0_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI0_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI0_TRIGGER               0
+//   
+
+//    EXTI1 Line
+#define RTE_EXTI1                       0
+//      Pin   <0=>PA1  <1=>PB1  <2=>PC1  <3=>PD1  <4=>PE1  <5=>PF1  <6=>PG1  <7=>PH1  <8=>PI1
+#define RTE_EXTI1_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI1_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI1_TRIGGER               0
+//   
+
+//    EXTI2 Line
+#define RTE_EXTI2                       0
+//      Pin   <0=>PA2  <1=>PB2  <2=>PC2  <3=>PD2  <4=>PE2  <5=>PF2  <6=>PG2  <7=>PH2  <8=>PI2
+#define RTE_EXTI2_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI2_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI2_TRIGGER               0
+//   
+
+//    EXTI3 Line
+#define RTE_EXTI3                       0
+//      Pin   <0=>PA3  <1=>PB3  <2=>PC3  <3=>PD3  <4=>PE3  <5=>PF3  <6=>PG3  <7=>PH3  <8=>PI3
+#define RTE_EXTI3_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI3_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI3_TRIGGER               0
+//   
+
+//    EXTI4 Line
+#define RTE_EXTI4                       0
+//      Pin   <0=>PA4  <1=>PB4  <2=>PC4  <3=>PD4  <4=>PE4  <5=>PF4  <6=>PG4  <7=>PH4  <8=>PI4
+#define RTE_EXTI4_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI4_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI4_TRIGGER               0
+//   
+
+//    EXTI5 Line
+#define RTE_EXTI5                       0
+//      Pin   <0=>PA5  <1=>PB5  <2=>PC5  <3=>PD5  <4=>PE5  <5=>PF5  <6=>PG5  <7=>PH5  <8=>PI5
+#define RTE_EXTI5_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI5_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI5_TRIGGER               0
+//   
+
+//    EXTI6 Line
+#define RTE_EXTI6                       0
+//      Pin   <0=>PA6  <1=>PB6  <2=>PC6  <3=>PD6  <4=>PE6  <5=>PF6  <6=>PG6  <7=>PH6  <8=>PI6
+#define RTE_EXTI6_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI6_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI6_TRIGGER               0
+//   
+
+//    EXTI7 Line
+#define RTE_EXTI7                       0
+//      Pin   <0=>PA7  <1=>PB7  <2=>PC7  <3=>PD7  <4=>PE7  <5=>PF7  <6=>PG7  <7=>PH7  <8=>PI7
+#define RTE_EXTI7_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI7_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI7_TRIGGER               0
+//   
+
+//    EXTI8 Line
+#define RTE_EXTI8                       0
+//      Pin   <0=>PA8  <1=>PB8  <2=>PC8  <3=>PD8  <4=>PE8  <5=>PF8  <6=>PG8  <7=>PH8  <8=>PI8
+#define RTE_EXTI8_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI8_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI8_TRIGGER               0
+//   
+
+//    EXTI9 Line
+#define RTE_EXTI9                       0
+//      Pin   <0=>PA9  <1=>PB9  <2=>PC9  <3=>PD9  <4=>PE9  <5=>PF9  <6=>PG9  <7=>PH9  <8=>PI9
+#define RTE_EXTI9_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI9_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI9_TRIGGER               0
+//   
+
+//    EXTI10 Line
+#define RTE_EXTI10                      0
+//      Pin   <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10
+#define RTE_EXTI10_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI10_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI10_TRIGGER              0
+//   
+
+//    EXTI11 Line
+#define RTE_EXTI11                      0
+//      Pin   <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11
+#define RTE_EXTI11_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI11_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI11_TRIGGER              0
+//   
+
+//    EXTI12 Line
+#define RTE_EXTI12                      0
+//      Pin   <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12
+#define RTE_EXTI12_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI12_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI12_TRIGGER              0
+//   
+
+//    EXTI13 Line
+#define RTE_EXTI13                      0
+//      Pin   <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13
+#define RTE_EXTI13_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI13_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI13_TRIGGER              0
+//   
+
+//    EXTI14 Line
+#define RTE_EXTI14                      0
+//      Pin   <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14
+#define RTE_EXTI14_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI14_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI14_TRIGGER              0
+//   
+
+//    EXTI15 Line
+#define RTE_EXTI15                      0
+//      Pin   <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15
+#define RTE_EXTI15_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI15_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI15_TRIGGER              0
+//   
+
+//    EXTI16 Line: PVD Output
+#define RTE_EXTI16                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI16_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI16_TRIGGER              0
+//   
+
+//    EXTI17 Line: RTC Alarm
+#define RTE_EXTI17                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI17_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI17_TRIGGER              0
+//   
+
+//    EXTI18 Line: USB OTG FS Wakeup
+#define RTE_EXTI18                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI18_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI18_TRIGGER              0
+//   
+
+//    EXTI19 Line: Ethernet Wakeup
+#define RTE_EXTI19                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI19_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI19_TRIGGER              0
+//   
+
+//    EXTI20 Line: USB OTG HS Wakeup
+#define RTE_EXTI20                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI20_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI20_TRIGGER              0
+//   
+
+//    EXTI21 Line: RTC Tamper and TimeStamp
+#define RTE_EXTI21                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI21_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI21_TRIGGER              0
+//   
+
+//    EXTI22 Line: RTC Wakeup
+#define RTE_EXTI22                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI22_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI22_TRIGGER              0
+//   
+
+// 
+
+
+//  FSMC (Flexible Static Memory Controller)
+#define RTE_FSMC                        0
+
+//    Pin Configuration
+//    Configure Pins
+#define RTE_FSMC_PINS                   0
+
+//      Address Bus Pins
+//       <0=>A[17:16]
+//       <1=>A[10:0]   <2=>A[15:0]   <3=>A[16:0]   <4=>A[17:0]
+//       <5=>A[18:0]   <6=>A[19:0]   <7=>A[20:0]   <8=>A[21:0]
+//       <9=>A[22:0]  <10=>A[23:0]  <11=>A[24:0]  <12=>A[25:0]
+#define RTE_FSMC_ABUS_PINS              10
+//      Data Bus Pins  <0=>D[7:0] <1=>D[15:0]
+#define RTE_FSMC_DBUS_PINS              0
+//      FSMC_NOE Pin
+#define RTE_FSMC_NOE_PIN                0
+//      FSMC_NWE Pin
+#define RTE_FSMC_NWE_PIN                0
+//      FSMC_NBL0 Pin
+#define RTE_FSMC_NBL0_PIN               0
+//      FSMC_NBL1 Pin
+#define RTE_FSMC_NBL1_PIN               0
+//      FSMC_NL Pin
+#define RTE_FSMC_NL_PIN                 0
+//      FSMC_NWAIT Pin
+#define RTE_FSMC_NWAIT_PIN              0
+//      FSMC_CLK Pin
+#define RTE_FSMC_CLK_PIN                0
+//      FSMC_NE1/NCE2 Pin
+#define RTE_FSMC_NE1_PIN                0
+//      FSMC_NE2/NCE3 Pin
+#define RTE_FSMC_NE2_PIN                0
+//      FSMC_NE3/NCE4_1 Pin
+#define RTE_FSMC_NE3_PIN                0
+//      FSMC_NE4 Pin
+#define RTE_FSMC_NE4_PIN                0
+//      FSMC_NCE4_2 Pin
+#define RTE_FSMC_NCE42_PIN              0
+//      FSMC_INT2 Pin
+#define RTE_FSMC_INT2_PIN               0
+//      FSMC_INT3 Pin
+#define RTE_FSMC_INT3_PIN               0
+//      FSMC_INTR Pin
+#define RTE_FSMC_INTR_PIN               0
+//      FSMC_NIORD Pin
+#define RTE_FSMC_NIORD_PIN              0
+//      FSMC_NIOWR Pin
+#define RTE_FSMC_NIOWR_PIN              0
+//      FSMC_NREG Pin
+#define RTE_FSMC_NREG_PIN               0
+//      FSMC_CD Pin
+#define RTE_FSMC_CD_PIN                 0
+
+//   
+
+//    NOR Flash / PSRAM Controller
+
+//      FSMC_NE1 Chip Select
+//      Configure Device on Chip Select FSMC_NE1
+#define RTE_FSMC_NE1                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR1_CBURSTRW          0
+#define RTE_FSMC_BCR1_ASYNCWAIT         0
+#define RTE_FSMC_BCR1_EXTMOD            0
+#define RTE_FSMC_BCR1_WAITEN            1
+#define RTE_FSMC_BCR1_WREN              1
+#define RTE_FSMC_BCR1_WAITCFG           0
+#define RTE_FSMC_BCR1_WRAPMOD           0
+#define RTE_FSMC_BCR1_WAITPOL           0
+#define RTE_FSMC_BCR1_BURSTEN           0
+#define RTE_FSMC_BCR1_FACCEN            1
+#define RTE_FSMC_BCR1_MWID              1
+#define RTE_FSMC_BCR1_MTYP              2
+#define RTE_FSMC_BCR1_MUXEN             1
+#define RTE_FSMC_BCR1_MBKEN             1
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR1_ACCMOD            0
+#define RTE_FSMC_BTR1_DATLAT            15
+#define RTE_FSMC_BTR1_CLKDIV            15
+#define RTE_FSMC_BTR1_BUSTURN           15
+#define RTE_FSMC_BTR1_DATAST            255
+#define RTE_FSMC_BTR1_ADDHLD            15
+#define RTE_FSMC_BTR1_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR1_ACCMOD        0
+#define RTE_FSMC_BWTR1_DATLAT        15
+#define RTE_FSMC_BWTR1_CLKDIV        15
+#define RTE_FSMC_BWTR1_BUSTURN       15
+#define RTE_FSMC_BWTR1_DATAST        255
+#define RTE_FSMC_BWTR1_ADDHLD        15
+#define RTE_FSMC_BWTR1_ADDSET        15
+//       
+//     
+
+//      FSMC_NE2 Chip Select
+//      Configure Device on Chip Select FSMC_NE2
+#define RTE_FSMC_NE2                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR2_CBURSTRW          0
+#define RTE_FSMC_BCR2_ASYNCWAIT         0
+#define RTE_FSMC_BCR2_EXTMOD            0
+#define RTE_FSMC_BCR2_WAITEN            1
+#define RTE_FSMC_BCR2_WREN              1
+#define RTE_FSMC_BCR2_WAITCFG           0
+#define RTE_FSMC_BCR2_WRAPMOD           0
+#define RTE_FSMC_BCR2_WAITPOL           0
+#define RTE_FSMC_BCR2_BURSTEN           0
+#define RTE_FSMC_BCR2_FACCEN            1
+#define RTE_FSMC_BCR2_MWID              1
+#define RTE_FSMC_BCR2_MTYP              0
+#define RTE_FSMC_BCR2_MUXEN             1
+#define RTE_FSMC_BCR2_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR2_ACCMOD            0
+#define RTE_FSMC_BTR2_DATLAT            15
+#define RTE_FSMC_BTR2_CLKDIV            15
+#define RTE_FSMC_BTR2_BUSTURN           15
+#define RTE_FSMC_BTR2_DATAST            255
+#define RTE_FSMC_BTR2_ADDHLD            15
+#define RTE_FSMC_BTR2_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR2_ACCMOD        0
+#define RTE_FSMC_BWTR2_DATLAT        15
+#define RTE_FSMC_BWTR2_CLKDIV        15
+#define RTE_FSMC_BWTR2_BUSTURN       15
+#define RTE_FSMC_BWTR2_DATAST        255
+#define RTE_FSMC_BWTR2_ADDHLD        15
+#define RTE_FSMC_BWTR2_ADDSET        15
+//       
+//     
+
+//      FSMC_NE3 Chip Select
+//      Configure Device on Chip Select FSMC_NE3
+#define RTE_FSMC_NE3                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR3_CBURSTRW          0
+#define RTE_FSMC_BCR3_ASYNCWAIT         0
+#define RTE_FSMC_BCR3_EXTMOD            0
+#define RTE_FSMC_BCR3_WAITEN            1
+#define RTE_FSMC_BCR3_WREN              1
+#define RTE_FSMC_BCR3_WAITCFG           0
+#define RTE_FSMC_BCR3_WRAPMOD           0
+#define RTE_FSMC_BCR3_WAITPOL           0
+#define RTE_FSMC_BCR3_BURSTEN           0
+#define RTE_FSMC_BCR3_FACCEN            1
+#define RTE_FSMC_BCR3_MWID              1
+#define RTE_FSMC_BCR3_MTYP              0
+#define RTE_FSMC_BCR3_MUXEN             1
+#define RTE_FSMC_BCR3_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR3_ACCMOD            0
+#define RTE_FSMC_BTR3_DATLAT            15
+#define RTE_FSMC_BTR3_CLKDIV            15
+#define RTE_FSMC_BTR3_BUSTURN           15
+#define RTE_FSMC_BTR3_DATAST            255
+#define RTE_FSMC_BTR3_ADDHLD            15
+#define RTE_FSMC_BTR3_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR3_ACCMOD        0
+#define RTE_FSMC_BWTR3_DATLAT        15
+#define RTE_FSMC_BWTR3_CLKDIV        15
+#define RTE_FSMC_BWTR3_BUSTURN       15
+#define RTE_FSMC_BWTR3_DATAST        255
+#define RTE_FSMC_BWTR3_ADDHLD        15
+#define RTE_FSMC_BWTR3_ADDSET        15
+//       
+//     
+
+//      FSMC_NE4 Chip Select
+//      Configure Device on Chip Select FSMC_NE4
+#define RTE_FSMC_NE4                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR4_CBURSTRW          0
+#define RTE_FSMC_BCR4_ASYNCWAIT         0
+#define RTE_FSMC_BCR4_EXTMOD            0
+#define RTE_FSMC_BCR4_WAITEN            1
+#define RTE_FSMC_BCR4_WREN              1
+#define RTE_FSMC_BCR4_WAITCFG           0
+#define RTE_FSMC_BCR4_WRAPMOD           0
+#define RTE_FSMC_BCR4_WAITPOL           0
+#define RTE_FSMC_BCR4_BURSTEN           0
+#define RTE_FSMC_BCR4_FACCEN            1
+#define RTE_FSMC_BCR4_MWID              1
+#define RTE_FSMC_BCR4_MTYP              0
+#define RTE_FSMC_BCR4_MUXEN             1
+#define RTE_FSMC_BCR4_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR4_ACCMOD            0
+#define RTE_FSMC_BTR4_DATLAT            15
+#define RTE_FSMC_BTR4_CLKDIV            15
+#define RTE_FSMC_BTR4_BUSTURN           15
+#define RTE_FSMC_BTR4_DATAST            255
+#define RTE_FSMC_BTR4_ADDHLD            15
+#define RTE_FSMC_BTR4_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR4_ACCMOD        0
+#define RTE_FSMC_BWTR4_DATLAT        15
+#define RTE_FSMC_BWTR4_CLKDIV        15
+#define RTE_FSMC_BWTR4_BUSTURN       15
+#define RTE_FSMC_BWTR4_DATAST        255
+#define RTE_FSMC_BWTR4_ADDHLD        15
+#define RTE_FSMC_BWTR4_ADDSET        15
+//       
+//     
+
+//   
+
+//    NAND Flash Controller
+
+//      FSMC_NCE2 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE2
+#define RTE_FSMC_NCE2                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR2_ECCPS             0
+#define RTE_FSMC_PCR2_TAR               0
+#define RTE_FSMC_PCR2_TCLR              0
+#define RTE_FSMC_PCR2_ECCEN             0
+#define RTE_FSMC_PCR2_PWID              0
+#define RTE_FSMC_PCR2_PTYP              1
+#define RTE_FSMC_PCR2_PBKEN             0
+#define RTE_FSMC_PCR2_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR2_IFEN               0
+#define RTE_FSMC_SR2_ILEN               0
+#define RTE_FSMC_SR2_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM2_MEMHIZ           255
+#define RTE_FSMC_PMEM2_MEMHOLD          255
+#define RTE_FSMC_PMEM2_MEMWAIT          255
+#define RTE_FSMC_PMEM2_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT2_ATTHIZ           255
+#define RTE_FSMC_PATT2_ATTHOLD          255
+#define RTE_FSMC_PATT2_ATTWAIT          255
+#define RTE_FSMC_PATT2_ATTSET           255
+
+//       
+
+//     
+
+//      FSMC_NCE3 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE3
+#define RTE_FSMC_NCE3                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR3_ECCPS             0
+#define RTE_FSMC_PCR3_TAR               0
+#define RTE_FSMC_PCR3_TCLR              0
+#define RTE_FSMC_PCR3_ECCEN             0
+#define RTE_FSMC_PCR3_PWID              0
+#define RTE_FSMC_PCR3_PTYP              1
+#define RTE_FSMC_PCR3_PBKEN             0
+#define RTE_FSMC_PCR3_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR3_IFEN               0
+#define RTE_FSMC_SR3_ILEN               0
+#define RTE_FSMC_SR3_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM3_MEMHIZ           255
+#define RTE_FSMC_PMEM3_MEMHOLD          255
+#define RTE_FSMC_PMEM3_MEMWAIT          255
+#define RTE_FSMC_PMEM3_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT3_ATTHIZ           255
+#define RTE_FSMC_PATT3_ATTHOLD          255
+#define RTE_FSMC_PATT3_ATTWAIT          255
+#define RTE_FSMC_PATT3_ATTSET           255
+
+//       
+
+//     
+
+//   
+
+//    PC Card Controller
+
+//      FSMC_NCE4_x Chip Select
+//      Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2
+#define RTE_FSMC_NCE4              0
+
+//        PC Card Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: PC Card memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR4_ECCPS             0
+#define RTE_FSMC_PCR4_TAR               0
+#define RTE_FSMC_PCR4_TCLR              0
+#define RTE_FSMC_PCR4_ECCEN             0
+#define RTE_FSMC_PCR4_PWID              0
+#define RTE_FSMC_PCR4_PTYP              0
+#define RTE_FSMC_PCR4_PBKEN             0
+#define RTE_FSMC_PCR4_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR4_IFEN               0
+#define RTE_FSMC_SR4_ILEN               0
+#define RTE_FSMC_SR4_IREN               0
+
+//       
+
+//        Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM4_MEMHIZ           255
+#define RTE_FSMC_PMEM4_MEMHOLD          255
+#define RTE_FSMC_PMEM4_MEMWAIT          255
+#define RTE_FSMC_PMEM4_MEMSET           255
+
+//       
+
+//        Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT4_ATTHIZ           255
+#define RTE_FSMC_PATT4_ATTHOLD          255
+#define RTE_FSMC_PATT4_ATTWAIT          255
+#define RTE_FSMC_PATT4_ATTSET           255
+
+//       
+
+//        I/O space timing
+//          IOHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a PC Card write access. Only valid for write transaction.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE,
+//           SMNOE), for PC Card read or write access. The duration for command assertion is
+//           extended if the wait signal (NWAIT) is active (low) at the end of the
+//           programmed value of HCLK.
+//           0000 0000: reserved, do not use this value
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles
+//          IOSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PIO4_IOHIZ             255
+#define RTE_FSMC_PIO4_IOHOLD            255
+#define RTE_FSMC_PIO4_IOWAIT            255
+#define RTE_FSMC_PIO4_IOSET             255
+
+//       
+
+//     
+
+//   
+
+// 
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s
new file mode 100644
index 000000000..c4e2ab9fa
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s
@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00002000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00007000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c
new file mode 100644
index 000000000..da0e189c8
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c
@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2011 STMicroelectronics

+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c
new file mode 100644
index 000000000..78564b080
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c
@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// File System
+// Define File System global parameters
+
+//   Number of open files <4-16>
+//   Define number of files that can be
+//   opened at the same time.
+//   Default: 8
+#define NUM_FILES               8
+
+//   FAT Name Cache Size <0-1000000>
+//   Define number of cached FAT file or directory names.
+//   48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   Relocate FAT Name Cache Buffer
+//   Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config_MC_0.h
new file mode 100644
index 000000000..0b1c6d3a7
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config_MC_0.h
@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Memory Card Drive 0
+// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   Connect to hardware via Driver_MCI# <0-255>
+//   Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   Connect to hardware via Driver_SPI# <0-255>
+//   Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   Memory Card Interface Mode <0=>Native <1=>SPI
+//   Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   Drive Cache stores data sectors and may be increased to speed-up
+//   file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   Locate Drive Cache and Drive Buffer
+//   Some microcontrollers support DMA only in specific memory areas and
+//   require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   
+
+//   Use FAT Journal
+//   Protect File Allocation Table and Directory Entries for
+//   fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   Default Drive "M0:"
+//   Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config.c
new file mode 100644
index 000000000..6b9dc8e00
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config.c
@@ -0,0 +1,153 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// System Definitions
+//  Global Network System definitions
+//   Local Host Name
+//    This is the name under which embedded host can be
+//    accessed on a local area network.
+//    Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   Memory Pool size <1536-262144:4><#/4>
+//    This is the size of a memory pool in bytes. Buffers for
+//    Network packets are allocated from this memory pool.
+//    Default: 12000 bytes
+#define NET_MEM_SIZE            3000
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP_0
+#include "Net_Config_PPP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_PPP_1
+#include "Net_Config_PPP_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP_0
+#include "Net_Config_SLIP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_SLIP_1
+#include "Net_Config_SLIP_1.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (ERROR_CODE error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (ERROR_CODE error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer Corrupted */
+      /* More data written than the size of allocated mem block */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_BSD.h
new file mode 100644
index 000000000..4166a0a2d
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_BSD.h
@@ -0,0 +1,36 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_BSD.h
+ * Purpose: Network Configuration BSD Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Berkley (BSD) Sockets
+#define BSD_ENABLE              1
+
+//   Number of BSD Sockets <1-20>
+//    Number of available Berkeley Sockets
+//    Default: 2
+#define BSD_NUM_SOCKS           15
+
+//   Number of Streaming Server Sockets <0-20>
+//    Defines a number of Streaming (TCP) Server sockets,
+//    that listen for an incoming connection from the client.
+//    Default: 1
+#define BSD_SERVER_SOCKS        1
+
+//   Receive Timeout in seconds <0-600>
+//    A timeout for socket receive in blocking mode.
+//    Timeout value of 0 means indefinite timeout.
+//    Default: 20
+#define BSD_RECEIVE_TOUT        20
+
+//   Hostname Resolver
+//    Enable or disable Berkeley style hostname resolver.
+#define BSD_HOSTNAME_ENABLE     0
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_DNS_Client.h
new file mode 100644
index 000000000..d30b71807
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_DNS_Client.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Service
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_DNS_Client.h
+ * Purpose: Network Configuration DNS Client
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// DNS Client
+#define DNS_CLIENT_ENABLE       1
+
+//     Cache Table size <5-100>
+//      Number of cached DNS host names/IP addresses
+//      Default: 20
+#define DNS_CLIENT_TAB_SIZE     20
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_ETH_0.h
new file mode 100644
index 000000000..9a49f3821
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_ETH_0.h
@@ -0,0 +1,222 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_ETH_0.h
+ * Purpose: Network Configuration ETH Interface
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Ethernet Network Interface 0
+#define ETH0_ENABLE             1
+
+//   Connect to hardware via Driver_ETH# <0-255>
+//   Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER             1
+
+//   MAC Address
+//    Local Ethernet MAC Address
+//    Value FF:FF:FF:FF:FF:FF is not allowed.
+//    It is an ethernet Broadcast MAC address.
+//     Address byte 1 <0x00-0xff:2>
+//      LSB is an ethernet Multicast bit.
+//      Must be 0 for local MAC address.
+//      Default: 0x1E
+#define ETH0_MAC1               0x1E
+
+//     Address byte 2 <0x00-0xff>
+//      Default: 0x30
+#define ETH0_MAC2               0x30
+
+//     Address byte 3 <0x00-0xff>
+//      Default: 0x6C
+#define ETH0_MAC3               0x6C
+
+//     Address byte 4 <0x00-0xff>
+//      Default: 0xA2
+#define ETH0_MAC4               0xA2
+
+//     Address byte 5 <0x00-0xff>
+//      Default: 0x45
+#define ETH0_MAC5               0x45
+
+//     Address byte 6 <0x00-0xff>
+//      Default: 0x5E
+#define ETH0_MAC6               0x5E
+//   
+
+//   IP Address
+//    Local Static IP Address
+//    Value 255.255.255.255 is not allowed.
+//    It is a Broadcast IP address.
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_IP1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_IP2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_IP3                0
+
+//     Address byte 4 <0-255>
+//      Default: 100
+#define ETH0_IP4                100
+//   
+
+//   Subnet mask
+//    Local Subnet mask
+//     Mask byte 1 <0-255>
+//      Default: 255
+#define ETH0_MASK1              255
+
+//     Mask byte 2 <0-255>
+//      Default: 255
+#define ETH0_MASK2              255
+
+//     Mask byte 3 <0-255>
+//      Default: 255
+#define ETH0_MASK3              255
+
+//     Mask byte 4 <0-255>
+//      Default: 0
+#define ETH0_MASK4              0
+//   
+
+//   Default Gateway
+//    Default Gateway IP Address
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_GW1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_GW2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_GW3                0
+
+//     Address byte 4 <0-255>
+//      Default: 254
+#define ETH0_GW4                254
+//   
+
+//   Primary DNS Server
+//    Primary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_PRI_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_PRI_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_PRI_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 129
+#define ETH0_PRI_DNS4           129
+//   
+
+//   Secondary DNS Server
+//    Secondary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_SEC_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_SEC_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_SEC_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 130
+#define ETH0_SEC_DNS4           130
+//   
+
+//   ARP Definitions
+//    Address Resolution Protocol Definitions
+//     Cache Table size <5-100>
+//      Number of cached hardware/IP addresses
+//      Default: 10
+#define ETH0_ARP_TAB_SIZE       10
+
+//     Cache Timeout in seconds <5-255>
+//      A timeout for a cached hardware/IP addresses
+//      Default: 150
+#define ETH0_ARP_CACHE_TOUT     150
+
+//     Number of Retries <0-20>
+//      Number of Retries to resolve an IP address
+//      before ARP module gives up
+//      Default: 4
+#define ETH0_ARP_MAX_RETRY      4
+
+//     Resend Timeout in seconds <1-10>
+//      A timeout to resend the ARP Request
+//      Default: 2
+#define ETH0_ARP_RESEND_TOUT    2
+
+//     Send Notification on Address changes
+//      When this option is enabled, the embedded host
+//      will send a Gratuitous ARP notification at startup,
+//      or when the device IP address has changed.
+//      Default: Disabled
+#define ETH0_ARP_NOTIFY         0
+//   
+
+//   IGMP Group Management
+//    Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE        0
+
+//     Membership Table size <2-50>
+//      Number of Groups this host can join
+//      Default: 5
+#define ETH0_IGMP_TAB_SIZE      5
+//   
+
+//   NetBIOS Name Service
+//    When this option is enabled, the embedded host can be
+//    accessed by his name on the local LAN using NBNS protocol.
+//    You need to modify also the number of UDP Sockets,
+//    because NBNS protocol uses one UDP socket to run.
+#define ETH0_NBNS_ENABLE        1
+
+//   Dynamic Host Configuration
+//    When this option is enabled, local IP address, Net Mask
+//    and Default Gateway are obtained automatically from
+//    the DHCP Server on local LAN.
+//    You need to modify also the number of UDP Sockets,
+//    because DHCP protocol uses one UDP socket to run.
+#define ETH0_DHCP_ENABLE        0
+
+//     Vendor Class Identifier
+//      This value is optional. If specified, it is added
+//      to DHCP request message, identifying vendor type.
+//      Default: ""
+#define ETH0_DHCP_VCID          ""
+
+//     Bootfile Name
+//      This value is optional. If enabled, the Bootfile Name
+//      (option 67) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_BOOTFILE      0
+
+//     NTP Servers
+//      This value is optional. If enabled, a list of NTP Servers
+//      (option 42) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_NTP_SERVERS   0
+//   
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_TCP.h
new file mode 100644
index 000000000..9d5b419e4
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_TCP.h
@@ -0,0 +1,61 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_TCP.h
+ * Purpose: Network Configuration TCP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// TCP Sockets
+#define TCP_ENABLE              1
+
+//   Number of TCP Sockets <1-20>
+//    Number of available TCP sockets
+//    Default: 5
+#define TCP_NUM_SOCKS           15
+
+//   Number of Retries <0-20>
+//    How many times TCP module will try to retransmit data
+//    before giving up. Increase this value for high-latency
+//    and low_throughput networks.
+//    Default: 5
+#define TCP_MAX_RETRY           5
+
+//   Retry Timeout in seconds <1-10>
+//    If data frame not acknowledged within this time frame,
+//    TCP module will try to resend the data again.
+//    Default: 4
+#define TCP_RETRY_TOUT          4
+
+//   Default Connect Timeout in seconds <1-600>
+//    Default TCP Socket Keep Alive timeout. When it expires
+//    with no TCP data frame send, TCP Connection is closed.
+//    Default: 120
+#define TCP_DEFAULT_TOUT        120
+
+//   Maximum Segment Size <536-1460>
+//    The Maximum Segment Size specifies the maximum
+//    number of bytes in the TCP segment's Data field.
+//    Default: 1460
+#define TCP_MAX_SEG_SIZE        1460
+
+//   Receive Window Size <536-65535>
+//    Receive Window Size specifies the size of data, 
+//    that the socket is able to buffer in flow-control mode.
+//    Default: 4380
+#define TCP_RECEIVE_WIN_SIZE    4380
+
+// 
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT  1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT      2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY       7
+
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_UDP.h
new file mode 100644
index 000000000..113f314a9
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Config_UDP.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_UDP.h
+ * Purpose: Network Configuration UDP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// UDP Sockets
+#define UDP_ENABLE              1
+
+//   Number of UDP Sockets <1-20>
+//    Number of available UDP sockets
+//    Default: 5
+#define UDP_NUM_SOCKS           20
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Debug.c
new file mode 100644
index 000000000..735089a40
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/Network/Net_Debug.c
@@ -0,0 +1,125 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Debug.c
+ * Purpose: Network Debug Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Print Time Stamp
+//    Enable printing the time-info in debug messages
+#define DBG_TIME                1
+
+// TCPnet Debug Definitions
+//   Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Memory debug messages
+#define DBG_MEM                 1
+
+//   Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Ethernet debug messages
+#define DBG_ETH                 0
+
+//   PPP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off PPP debug messages
+#define DBG_PPP                 0
+
+//   SLIP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SLIP debug messages
+#define DBG_SLIP                0
+
+//   ARP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ARP debug messages
+#define DBG_ARP                 0
+
+//   IP Debug    <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IP debug messages
+#define DBG_IP                  1
+
+//   ICMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ICMP debug messages
+#define DBG_ICMP                1
+
+//   IGMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IGMP debug messages
+#define DBG_IGMP                1
+
+//   UDP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off UDP debug messages
+#define DBG_UDP                 1
+
+//   TCP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TCP debug messages
+#define DBG_TCP                 1
+
+//   NBNS Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off NetBIOS Name Service debug messages
+#define DBG_NBNS                1
+
+//   DHCP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Host Configuration debug messages
+#define DBG_DHCP                1
+
+//   DNS Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Domain Name Service debug messages
+#define DBG_DNS                 1
+
+//   SNMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Management debug messages
+#define DBG_SNMP                1
+
+//   SNTP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Time debug messages
+#define DBG_SNTP                1
+
+//   BSD Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off BSD Interface debug messages
+#define DBG_BSD                 1
+// 
+
+// Application Debug Definitions
+//   HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Web Server debug messages
+#define DBG_HTTP_SERVER         1
+
+//   FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Server debug messages
+#define DBG_FTP_SERVER          1
+
+//   FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Client debug messages
+#define DBG_FTP_CLIENT          1
+
+//   Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Telnet Server debug messages
+#define DBG_TELNET_SERVER       1
+
+//   TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Server debug messages
+#define DBG_TFTP_SERVER         1
+
+//   TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Client debug messages
+#define DBG_TFTP_CLIENT         1
+
+//   SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SMTP Client debug messages
+#define DBG_SMTP_CLIENT         1
+// 
+
+
+#include "net_debug.h"
+
+
+/**
+  \fn          void net_debug_init (void)
+  \brief       Initialize Network Debug Interface.
+*/
+void net_debug_init (void) {
+  /* Add your code to initialize the Debug output. This is usually the  */
+  /* serial interface. The function is called at TCPnet system startup. */
+  /* You may need to customize also the 'putchar()' function.           */
+
+}
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/EchoServer/RTE/RTE_Components.h
new file mode 100644
index 000000000..20773df02
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/RTE/RTE_Components.h
@@ -0,0 +1,28 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'EchoServer' 
+ * Target:  'EchoServer' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_ETH_MAC0            /* Driver ETH_MAC0 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_Drivers_PHY_ST802RT1        /* Driver PHY ST802RT1 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+#define RTE_Network_Core                /* Network Core */
+          #define RTE_Network_Debug               /* Network Debug Version */
+#define RTE_Network_DNS_Client          /* Network DNS Client */
+#define RTE_Network_Interface_ETH_0     /* Network Interface ETH 0 */
+#define RTE_Network_Socket_BSD          /* Network Socket BSD */
+#define RTE_Network_Socket_TCP          /* Network Socket TCP */
+#define RTE_Network_Socket_UDP          /* Network Socket UDP */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini
new file mode 100644
index 000000000..239abce37
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini
@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+//  Debug MCU Configuration
+//       DBG_SLEEP      Debug Sleep Mode
+//       DBG_STOP       Debug Stop Mode
+//       DBG_STANDBY    Debug Standby Mode
+//       TRACE_IOEN     Trace I/O Enable 
+//    TRACE_MODE     Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//       DBG_IWDG_STOP  Independant Watchdog Stopped when Core is halted
+//       DBG_WWDG_STOP  Window Watchdog Stopped when Core is halted
+//      DBG_TIM1_STOP  Timer 1 Stopped when Core is halted
+//      DBG_TIM2_STOP  Timer 2 Stopped when Core is halted
+//      DBG_TIM3_STOP  Timer 3 Stopped when Core is halted
+//      DBG_TIM4_STOP  Timer 4 Stopped when Core is halted
+//      DBG_CAN_STOP   CAN Stopped when Core is halted
+// 
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c b/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c
new file mode 100644
index 000000000..ba8e10f18
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/echoserver.c
@@ -0,0 +1,370 @@
+/* echoserver.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if defined(CYASSL_MDK_ARM)
+    #include 
+    #include 
+
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include 
+#include 
+
+#ifndef NO_MAIN_DRIVER
+    #define ECHO_OUT
+#endif
+
+#include "examples/echoserver/echoserver.h"
+
+
+#ifdef SESSION_STATS
+    CYASSL_API void PrintSessionStats(void);
+#endif
+
+#define SVR_COMMAND_SIZE 256
+
+static void SignalReady(void* args, int port)
+{
+#if defined(_POSIX_THREADS) && defined(NO_MAIN_DRIVER) && !defined(__MINGW32__)
+    /* signal ready to tcp_accept */
+    func_args* server_args = (func_args*)args;
+    tcp_ready* ready = server_args->signal;
+    pthread_mutex_lock(&ready->mutex);
+    ready->ready = 1;
+    ready->port = port;
+    pthread_cond_signal(&ready->cond);
+    pthread_mutex_unlock(&ready->mutex);
+#endif
+    (void)args;
+    (void)port;
+}
+
+
+THREAD_RETURN CYASSL_THREAD echoserver_test(void* args)
+{
+    SOCKET_T       sockfd = 0;
+    CYASSL_METHOD* method = 0;
+    CYASSL_CTX*    ctx    = 0;
+
+    int    doDTLS = 0;
+    int    doPSK = 0;
+    int    outCreated = 0;
+    int    shutDown = 0;
+    int    useAnyAddr = 0;
+    int    port = yasslPort;
+    int    argc = ((func_args*)args)->argc;
+    char** argv = ((func_args*)args)->argv;
+
+#ifdef ECHO_OUT
+    FILE* fout = stdout;
+    if (argc >= 2) {
+        fout = fopen(argv[1], "w");
+        outCreated = 1;
+    }
+    if (!fout) err_sys("can't open output file");
+#endif
+    (void)outCreated;
+    (void)argc;
+    (void)argv;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef CYASSL_DTLS
+    doDTLS  = 1;
+#endif
+
+#ifdef CYASSL_LEANPSK
+    doPSK = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    doPSK = 1;
+#endif
+
+    #if defined(NO_MAIN_DRIVER) && !defined(USE_WINDOWS_API) && \
+                      !defined(CYASSL_SNIFFER) && !defined(CYASSL_MDK_ARM)
+        port = 0;
+    #endif
+    #if defined(USE_ANY_ADDR)
+        useAnyAddr = 1;
+    #endif
+    tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+
+#if defined(CYASSL_DTLS)
+    method  = CyaDTLSv1_server_method();
+#elif  !defined(NO_TLS)
+    method = CyaSSLv23_server_method();
+#else
+    method = CyaSSLv3_server_method();
+#endif
+    ctx    = CyaSSL_CTX_new(method);
+    /* CyaSSL_CTX_set_session_cache_mode(ctx, SSL_SESS_CACHE_OFF); */
+
+#ifdef OPENSSL_EXTRA
+    CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#ifndef NO_FILESYSTEM
+    if (doPSK == 0) {
+    #ifdef HAVE_NTRU
+        /* ntru */
+        if (CyaSSL_CTX_use_certificate_file(ctx, ntruCert, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load ntru cert file, "
+                    "Please run from CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ntruKey)
+                != SSL_SUCCESS)
+            err_sys("can't load ntru key file, "
+                    "Please run from CyaSSL home dir");
+    #elif defined(HAVE_ECC)
+        /* ecc */
+        if (CyaSSL_CTX_use_certificate_file(ctx, eccCert, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server cert file, "
+                    "Please run from CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_PrivateKey_file(ctx, eccKey, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server key file, "
+                    "Please run from CyaSSL home dir");
+    #elif defined(NO_CERTS)
+        /* do nothing, just don't load cert files */
+    #else
+        /* normal */
+        if (CyaSSL_CTX_use_certificate_file(ctx, svrCert, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server cert file, "
+                    "Please run from CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_PrivateKey_file(ctx, svrKey, SSL_FILETYPE_PEM)
+                != SSL_SUCCESS)
+            err_sys("can't load server key file, "
+                    "Please run from CyaSSL home dir");
+    #endif
+    } /* doPSK */
+#elif !defined(NO_CERTS)
+    if (!doPSK) {
+        load_buffer(ctx, svrCert, CYASSL_CERT);
+        load_buffer(ctx, svrKey,  CYASSL_KEY);
+    }
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA");
+#endif
+
+    if (doPSK) {
+#ifndef NO_PSK
+        const char *defaultCipherList;
+
+        CyaSSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb);
+        CyaSSL_CTX_use_psk_identity_hint(ctx, "cyassl server");
+        #ifdef HAVE_NULL_CIPHER
+            defaultCipherList = "PSK-NULL-SHA256";
+        #else
+            defaultCipherList = "PSK-AES128-CBC-SHA256";
+        #endif
+        if (CyaSSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS)
+            err_sys("server can't set cipher list 2");
+#endif
+    }
+
+    SignalReady(args, port);
+
+    while (!shutDown) {
+        CYASSL* ssl = 0;
+        char    command[SVR_COMMAND_SIZE+1];
+        int     echoSz = 0;
+        int     clientfd;
+        int     firstRead = 1;
+        int     gotFirstG = 0;
+                
+#ifndef CYASSL_DTLS 
+        SOCKADDR_IN_T client;
+        socklen_t     client_len = sizeof(client);
+        clientfd = accept(sockfd, (struct sockaddr*)&client,
+                         (ACCEPT_THIRD_T)&client_len);
+#else
+        clientfd = udp_read_connect(sockfd);
+#endif
+        if (clientfd == -1) err_sys("tcp accept failed");
+
+        ssl = CyaSSL_new(ctx);
+        if (ssl == NULL) err_sys("SSL_new failed");
+              CyaSSL_set_quiet_shutdown(ssl, 1) ;
+            
+        CyaSSL_set_fd(ssl, clientfd);
+        #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA)
+            CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+        #elif !defined(NO_CERTS)
+            SetDH(ssl);  /* will repick suites with DHE, higher than PSK */
+        #endif
+        if (CyaSSL_accept(ssl) != SSL_SUCCESS) {
+            printf("SSL_accept failed\n");
+            CyaSSL_free(ssl);
+            CloseSocket(clientfd);
+            continue;
+        }
+#if defined(PEER_INFO)
+        showPeer(ssl);
+#endif
+
+        while ( (echoSz = CyaSSL_read(ssl, command, sizeof(command)-1)) > 0) {
+
+            if (firstRead == 1) {
+                firstRead = 0;  /* browser may send 1 byte 'G' to start */
+                if (echoSz == 1 && command[0] == 'G') {
+                    gotFirstG = 1;
+                    continue;
+                }
+            }
+            else if (gotFirstG == 1 && strncmp(command, "ET /", 4) == 0) {
+                strncpy(command, "GET", 4);
+                /* fall through to normal GET */
+            }
+           
+            if ( strncmp(command, "quit", 4) == 0) {
+                printf("client sent quit command: shutting down!\n");
+                shutDown = 1;
+                break;
+            }
+            if ( strncmp(command, "break", 5) == 0) {
+                printf("client sent break command: closing session!\n");
+                break;
+            }
+#ifdef SESSION_STATS
+            if ( strncmp(command, "printstats", 10) == 0) {
+                PrintSessionStats();
+                break;
+            }
+#endif
+            if ( strncmp(command, "GET", 3) == 0) {
+                char type[]   = "HTTP/1.0 200 ok\r\nContent-type:"
+                                " text/html\r\n\r\n";
+                char header[] = "\n
\n";
+                char body[]   = "greetings from CyaSSL\n";
+                char footer[] = "\r\n\r\n";
+            
+                strncpy(command, type, sizeof(type));
+                echoSz = sizeof(type) - 1;
+
+                strncpy(&command[echoSz], header, sizeof(header));
+                echoSz += (int)sizeof(header) - 1;
+                strncpy(&command[echoSz], body, sizeof(body));
+                echoSz += (int)sizeof(body) - 1;
+                strncpy(&command[echoSz], footer, sizeof(footer));
+                echoSz += (int)sizeof(footer);
+
+                if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                    err_sys("SSL_write failed");
+                break;
+            }
+            command[echoSz] = 0;
+
+            #ifdef ECHO_OUT
+                fputs(command, fout);
+            #endif
+
+            if (CyaSSL_write(ssl, command, echoSz) != echoSz)
+                err_sys("SSL_write failed");
+        }
+#ifndef CYASSL_DTLS
+        CyaSSL_shutdown(ssl);
+#endif
+        CyaSSL_free(ssl);
+        CloseSocket(clientfd);
+#ifdef CYASSL_DTLS
+        tcp_listen(&sockfd, &port, useAnyAddr, doDTLS);
+        SignalReady(args, port);
+#endif
+    }
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+    CloseSocket(sockfd);
+    CyaSSL_CTX_free(ctx);
+
+#ifdef ECHO_OUT
+    if (outCreated)
+        fclose(fout);
+#endif
+
+    ((func_args*)args)->return_code = 0;
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("echoserver") || CurrentDir("build"))
+            ChangeDirBack(2);
+        echoserver_test(&args);
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+        
+#endif /* NO_MAIN_DRIVER */
+
+
+
+
diff --git a/IDE/MDK5-ARM/Projects/EchoServer/main.c b/IDE/MDK5-ARM/Projects/EchoServer/main.c
new file mode 100644
index 000000000..09ff15d4a
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/EchoServer/main.c
@@ -0,0 +1,99 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+#include "rl_net.h" 
+#include 
+#include "cyassl_MDK_ARM.h"
+#include 
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+    int32_t retv;
+
+    retv = finit ("M0:");
+    if (retv == 0) {
+        retv = fmount ("M0:");
+        if (retv == 0) {
+            printf ("Drive M0 ready!\n");
+        }
+        else {
+          printf ("Drive M0 mount failed!\n");
+        }
+    } else {
+        printf ("Drive M0 initialization failed!\n");
+    }
+}
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+void tcp_poll (void const *arg)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        net_main ();
+        osDelay(1) ;
+    }
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+} func_args;
+
+extern void echoserver_test(func_args * args) ;
+extern void init_time(void) ;
+
+    osThreadDef (tcp_poll, osPriorityHigh, 1, 0) ;
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+int myoptind = 0;
+char* myoptarg = NULL;
+
+int main() 
+{
+    void *args = NULL ;
+    init_time() ;
+    init_filesystem ();
+    net_initialize() ;
+    osThreadCreate (osThread (tcp_poll), NULL); 
+    osDelay(10000) ;  /* wait for DHCP */
+    #if defined(DEBUG_CYASSL)
+        printf("Turning ON Debug message\n") ;
+        CyaSSL_Debugging_ON() ;
+    #endif
+
+        printf("echoserver: Started\n") ;
+    echoserver_test(args) ;
+    printf("echoserver: Terminated\n") ;
+}
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt b/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt
new file mode 100644
index 000000000..39ab9e9ef
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/Abstract.txt
@@ -0,0 +1,22 @@
+This program is a simple client example with CyaSSL/wolfCrypt library.
+
+In order to run this program,
+Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+Set config-SimpleClient.h configuration file for the Callee IP or Port number.
+
+For further configuration, refer config-Crypt.h and config-CyaSSL.h.
+
+When testing this client, it is recommended to test against one of the standard 
+CyaSSL example applications running on a desktop machine.  The standard CyaSSL 
+example applications are located in the CyaSSL root directory under the 
+/examples directory.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com
\ No newline at end of file
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c
new file mode 100644
index 000000000..54b3e0bfc
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c
@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// Thread Configuration
+// =======================
+//
+//   Number of concurrent running threads <0-250>
+//    Defines max. number of threads that will run at the same time.
+//    Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     5
+#endif
+
+//   Default Thread stack size [bytes] <64-4096:8><#/4>
+//    Defines default stack size for threads with osThreadDef stacksz = 0
+//    Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     250
+#endif
+
+//   Main Thread stack size [bytes] <64-20000:8><#/4>
+//    Defines stack size for main thread.
+//    Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 2000
+#endif
+
+//   Number of threads with user-provided stack size <0-250>
+//    Defines the number of threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     2
+#endif
+
+//   Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4>
+//    Defines the combined stack size for threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 2500
+#endif
+
+// Check for stack overflow
+//  Includes the stack checking code for stack overflow.
+//  Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+//  Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// 
+
+// RTX Kernel Timer Tick Configuration
+// ======================================
+//  Use Cortex-M SysTick timer as RTX Kernel Timer
+//  Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   Timer clock value [Hz] <1-1000000000>
+//    Defines the timer clock value.
+//    Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   Timer tick value [us] <1-1000000>
+//    Defines the timer tick value.
+//    Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// 
+
+// System Configuration
+// =======================
+//
+// Round-Robin Thread switching
+// ===============================
+//
+//  Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   Round-Robin Timeout [ticks] <1-1000>
+//    Defines how long a thread will execute before a thread switch.
+//    Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// 
+
+// User Timers
+// ==============
+//    Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//    Defines priority for Timer Thread
+//    Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   Timer Thread stack size [bytes] <64-64000:8><#/4>
+//    Defines stack size for Timer thread.
+//    Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   Timer Callback Queue size <1-32>
+//    Number of concurrent active timer callback functions.
+//    Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// 
+
+//   ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//    ISR functions store requests to this buffer,
+//    when they are called from the interrupt handler.
+//    Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// 
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h
new file mode 100644
index 000000000..4a09246f3
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h
@@ -0,0 +1,3127 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *  
+ * $Date:        27. June 2013
+ * $Revision:    V1.01
+ *  
+ * Project:      RTE Device Configuration for ST STM32F2xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  (num == 7) ? GPIOH : \
+  (num == 8) ? GPIOI : \
+  NULL)
+
+
+//  Clock Configuration
+//    High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         16000000
+//    High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//    System Clock <1-999999999>
+#define RTE_SYSCLK                      120000000
+//    AHB Clock    <1-999999999>
+#define RTE_HCLK                        120000000
+//    APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       30000000
+//    APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       60000000
+//       48MHz Clock
+#define RTE_PLL48CK                     48000000
+// 
+
+
+//  USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1]
+//  Configuration settings for Driver_UART1 in component ::Drivers:UART
+#define RTE_USART1                      0
+
+//    USART1_TX Pin <0=>PA9 <1=>PB6
+#define RTE_USART1_TX_ID                0
+#if    (RTE_USART1_TX_ID == 0)
+#define RTE_USART1_TX_PORT              GPIOA
+#define RTE_USART1_TX_BIT               9
+#elif  (RTE_USART1_TX_ID == 1)
+#define RTE_USART1_TX_PORT              GPIOB
+#define RTE_USART1_TX_BIT               6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//    USART1_RX Pin <0=>PA10 <1=>PB7
+#define RTE_USART1_RX_ID                0
+#if    (RTE_USART1_RX_ID == 0)
+#define RTE_USART1_RX_PORT              GPIOA
+#define RTE_USART1_RX_BIT               10
+#elif  (RTE_USART1_RX_ID == 1)
+#define RTE_USART1_RX_PORT              GPIOB
+#define RTE_USART1_RX_BIT               7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART1_CK Pin <0=>PA8
+//     
+#define RTE_USART1_CK                   0
+#define RTE_USART1_CK_ID                0
+#if    (RTE_USART1_CK_ID == 0)
+#define RTE_USART1_CK_PORT              GPIOA
+#define RTE_USART1_CK_BIT               8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART1_CTS Pin <0=>PA11
+//        USART1_RTS Pin <0=>PA12
+//        Manual CTS/RTS
+//     
+#define RTE_USART1_HW_FLOW              0
+#define RTE_USART1_CTS_ID               0
+#define RTE_USART1_RTS_ID               0
+#define RTE_USART1_MANUAL_FLOW          0
+#if    (RTE_USART1_CTS_ID == 0)
+#define RTE_USART1_CTS_PORT             GPIOA
+#define RTE_USART1_CTS_BIT              11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART1_RTS_ID == 0)
+#define RTE_USART1_RTS_PORT             GPIOA
+#define RTE_USART1_RTS_BIT              12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <2=>2 <5=>5
+//       Selects DMA Stream (only Stream 2 or 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_RX_DMA               1
+#define RTE_USART1_RX_DMA_NUMBER        2
+#define RTE_USART1_RX_DMA_STREAM        2
+#define RTE_USART1_RX_DMA_CHANNEL       4
+#define RTE_USART1_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_TX_DMA               1
+#define RTE_USART1_TX_DMA_NUMBER        2
+#define RTE_USART1_TX_DMA_STREAM        7
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2]
+//  Configuration settings for Driver_UART2 in component ::Drivers:UART
+#define RTE_USART2                      0
+
+//    USART2_TX Pin <0=>PA2 <1=>PD5
+#define RTE_USART2_TX_ID                0
+#if    (RTE_USART2_TX_ID == 0)
+#define RTE_USART2_TX_PORT              GPIOA
+#define RTE_USART2_TX_BIT               2
+#elif  (RTE_USART2_TX_ID == 1)
+#define RTE_USART2_TX_PORT              GPIOD
+#define RTE_USART2_TX_BIT               5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//    USART2_RX Pin <0=>PA3 <1=>PD6
+#define RTE_USART2_RX_ID                0
+#if    (RTE_USART2_RX_ID == 0)
+#define RTE_USART2_RX_PORT              GPIOA
+#define RTE_USART2_RX_BIT               3
+#elif  (RTE_USART2_RX_ID == 1)
+#define RTE_USART2_RX_PORT              GPIOD
+#define RTE_USART2_RX_BIT               6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART2_CK Pin <0=>PA4 <1=>PD7
+//     
+#define RTE_USART2_CK                   0
+#define RTE_USART2_CK_ID                0
+#if    (RTE_USART2_CK_ID == 0)
+#define RTE_USART2_CK_PORT              GPIOA
+#define RTE_USART2_CK_BIT               4
+#elif  (RTE_USART2_CK_ID == 1)
+#define RTE_USART2_CK_PORT              GPIOD
+#define RTE_USART2_CK_BIT               7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART2_CTS Pin <0=>PA0 <1=>PD3
+//        USART2_RTS Pin <0=>PA1 <1=>PD4
+//        Manual CTS/RTS
+//     
+#define RTE_USART2_HW_FLOW              0
+#define RTE_USART2_CTS_ID               0
+#define RTE_USART2_RTS_ID               0
+#define RTE_USART2_MANUAL_FLOW          0
+#if    (RTE_USART2_CTS_ID == 0)
+#define RTE_USART2_CTS_PORT             GPIOA
+#define RTE_USART2_CTS_BIT              0
+#elif  (RTE_USART2_CTS_ID == 1)
+#define RTE_USART2_CTS_PORT             GPIOD
+#define RTE_USART2_CTS_BIT              3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART2_RTS_ID == 0)
+#define RTE_USART2_RTS_PORT             GPIOA
+#define RTE_USART2_RTS_BIT              1
+#elif  (RTE_USART2_RTS_ID == 1)
+#define RTE_USART2_RTS_PORT             GPIOD
+#define RTE_USART2_RTS_BIT              4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5
+//       Selects DMA Stream (only Stream 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_RX_DMA               1
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_STREAM        5
+#define RTE_USART2_RX_DMA_CHANNEL       4
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6
+//       Selects DMA Stream (only Stream 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_TX_DMA               1
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_STREAM        6
+#define RTE_USART2_TX_DMA_CHANNEL       4
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3]
+//  Configuration settings for Driver_UART3 in component ::Drivers:UART
+#define RTE_USART3                      0
+
+//    USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8
+#define RTE_USART3_TX_ID                0
+#if    (RTE_USART3_TX_ID == 0)
+#define RTE_USART3_TX_PORT              GPIOB
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 1)
+#define RTE_USART3_TX_PORT              GPIOC
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 2)
+#define RTE_USART3_TX_PORT              GPIOD
+#define RTE_USART3_TX_BIT               8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//    USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9
+#define RTE_USART3_RX_ID                0
+#if    (RTE_USART3_RX_ID == 0)
+#define RTE_USART3_RX_PORT              GPIOB
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 1)
+#define RTE_USART3_RX_PORT              GPIOC
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 2)
+#define RTE_USART3_RX_PORT              GPIOD
+#define RTE_USART3_RX_BIT               9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10
+//     
+#define RTE_USART3_CK                   0
+#define RTE_USART3_CK_ID                0
+#if    (RTE_USART3_CK_ID == 0)
+#define RTE_USART3_CK_PORT              GPIOB
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 1)
+#define RTE_USART3_CK_PORT              GPIOC
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 2)
+#define RTE_USART3_CK_PORT              GPIOD
+#define RTE_USART3_CK_BIT               10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART3_CTS Pin <0=>PB13 <1=>PD11
+//        USART3_RTS Pin <0=>PB14 <1=>PD12
+//        Manual CTS/RTS
+//     
+#define RTE_USART3_HW_FLOW              0
+#define RTE_USART3_CTS_ID               0
+#define RTE_USART3_RTS_ID               0
+#define RTE_USART3_MANUAL_FLOW          0
+#if    (RTE_USART3_CTS_ID == 0)
+#define RTE_USART3_CTS_PORT             GPIOB
+#define RTE_USART3_CTS_BIT              13
+#elif  (RTE_USART3_CTS_ID == 1)
+#define RTE_USART3_CTS_PORT             GPIOD
+#define RTE_USART3_CTS_BIT              11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART3_RTS_ID == 0)
+#define RTE_USART3_RTS_PORT             GPIOB
+#define RTE_USART3_RTS_BIT              14
+#elif  (RTE_USART3_RTS_ID == 1)
+#define RTE_USART3_RTS_PORT             GPIOD
+#define RTE_USART3_RTS_BIT              12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <1=>1
+//       Selects DMA Stream (only Stream 1 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_RX_DMA               1
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_STREAM        1
+#define RTE_USART3_RX_DMA_CHANNEL       4
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_TX_DMA               1
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_STREAM        3
+#define RTE_USART3_TX_DMA_CHANNEL       4
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  UART4 (Universal asynchronous receiver transmitter) [Driver_UART4]
+//  Configuration settings for Driver_UART4 in component ::Drivers:UART
+#define RTE_UART4                       0
+
+//    UART4_TX Pin <0=>PA0 <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX_PORT               GPIOA
+#define RTE_UART4_TX_BIT                0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//    UART4_RX Pin <0=>PA1 <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX_PORT               GPIOA
+#define RTE_UART4_RX_BIT                1
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_RX_DMA                1
+#define RTE_UART4_RX_DMA_NUMBER         1
+#define RTE_UART4_RX_DMA_STREAM         2
+#define RTE_UART4_RX_DMA_CHANNEL        4
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_TX_DMA                1
+#define RTE_UART4_TX_DMA_NUMBER         1
+#define RTE_UART4_TX_DMA_STREAM         4
+#define RTE_UART4_TX_DMA_CHANNEL        4
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  UART5 (Universal asynchronous receiver transmitter) [Driver_UART5]
+//  Configuration settings for Driver_UART5 in component ::Drivers:UART
+#define RTE_UART5                       0
+
+//    UART5_TX Pin <0=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//    UART5_RX Pin <0=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0
+//       Selects DMA Stream (only Stream 0 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_RX_DMA                1
+#define RTE_UART5_RX_DMA_NUMBER         1
+#define RTE_UART5_RX_DMA_STREAM         0
+#define RTE_UART5_RX_DMA_CHANNEL        4
+#define RTE_UART5_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_TX_DMA                1
+#define RTE_UART5_TX_DMA_NUMBER         1
+#define RTE_UART5_TX_DMA_STREAM         7
+#define RTE_UART5_TX_DMA_CHANNEL        4
+#define RTE_UART5_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6]
+//  Configuration settings for Driver_UART6 in component ::Drivers:UART
+#define RTE_USART6                      0
+
+//    USART6_TX Pin <0=>PC6 <1=>PG14
+#define RTE_USART6_TX_ID                0
+#if    (RTE_USART6_TX_ID == 0)
+#define RTE_USART6_TX_PORT              GPIOC
+#define RTE_USART6_TX_BIT               6
+#elif  (RTE_USART6_TX_ID == 1)
+#define RTE_USART6_TX_PORT              GPIOG
+#define RTE_USART6_TX_BIT               14
+#else
+#error "Invalid USART6_TX Pin Configuration!"
+#endif
+
+//    USART6_RX Pin <0=>PC7 <1=>PG9
+#define RTE_USART6_RX_ID                0
+#if    (RTE_USART6_RX_ID == 0)
+#define RTE_USART6_RX_PORT              GPIOC
+#define RTE_USART6_RX_BIT               7
+#elif  (RTE_USART6_RX_ID == 1)
+#define RTE_USART6_RX_PORT              GPIOG
+#define RTE_USART6_RX_BIT               9
+#else
+#error "Invalid USART6_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART6_CK Pin <0=>PC8 <1=>PG7
+//     
+#define RTE_USART6_CK                   0
+#define RTE_USART6_CK_ID                0
+#if    (RTE_USART6_CK_ID == 0)
+#define RTE_USART6_CK_PORT              GPIOC
+#define RTE_USART6_CK_BIT               8
+#elif  (RTE_USART6_CK_ID == 1)
+#define RTE_USART6_CK_PORT              GPIOG
+#define RTE_USART6_CK_BIT               7
+#else
+#error "Invalid USART6_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART6_CTS Pin <0=>PG13 <1=>PG15
+//        USART6_RTS Pin <0=>PG8  <1=>PG12
+//        Manual CTS/RTS
+//     
+#define RTE_USART6_HW_FLOW              0
+#define RTE_USART6_CTS_ID               0
+#define RTE_USART6_RTS_ID               0
+#define RTE_USART6_MANUAL_FLOW          0
+#if    (RTE_USART6_CTS_ID == 0)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              13
+#elif  (RTE_USART6_CTS_ID == 1)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              15
+#else
+#error "Invalid USART6_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART6_RTS_ID == 0)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              8
+#elif  (RTE_USART6_RTS_ID == 1)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              12
+#else
+#error "Invalid USART6_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <1=>1 <2=>2
+//       Selects DMA Stream (only Stream 1 or 2 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_RX_DMA               1
+#define RTE_USART6_RX_DMA_NUMBER        2
+#define RTE_USART6_RX_DMA_STREAM        1
+#define RTE_USART6_RX_DMA_CHANNEL       5
+#define RTE_USART6_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_TX_DMA               1
+#define RTE_USART6_TX_DMA_NUMBER        2
+#define RTE_USART6_TX_DMA_STREAM        6
+#define RTE_USART6_TX_DMA_CHANNEL       5
+#define RTE_USART6_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+//  Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1                        0
+
+//    I2C1_SCL Pin <0=>PB6 <1=>PB8
+#define RTE_I2C1_SCL_PORT_ID            0
+#if    (RTE_I2C1_SCL_PORT_ID == 0)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                6
+#elif  (RTE_I2C1_SCL_PORT_ID == 1)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//    I2C1_SDA Pin <0=>PB7 <1=>PB9
+#define RTE_I2C1_SDA_PORT_ID            0
+#if    (RTE_I2C1_SDA_PORT_ID == 0)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                7
+#elif  (RTE_I2C1_SDA_PORT_ID == 1)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                9
+#else
+#error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <5=>5
+//       Selects DMA Stream (only Stream 0 or 5 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_RX_DMA                 1
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_STREAM          0
+#define RTE_I2C1_RX_DMA_CHANNEL         1
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_TX_DMA                 1
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_STREAM          6
+#define RTE_I2C1_TX_DMA_CHANNEL         1
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+//  Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2                        0
+
+//    I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOF
+#define RTE_I2C2_SCL_BIT                1
+#elif  (RTE_I2C2_SCL_PORT_ID == 1)
+#define RTE_I2C2_SCL_PORT               GPIOH
+#define RTE_I2C2_SCL_BIT                4
+#elif  (RTE_I2C2_SCL_PORT_ID == 2)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOF
+#define RTE_I2C2_SDA_BIT                0
+#elif  (RTE_I2C2_SDA_PORT_ID == 1)
+#define RTE_I2C2_SDA_PORT               GPIOH
+#define RTE_I2C2_SDA_BIT                5
+#elif  (RTE_I2C2_SDA_PORT_ID == 2)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2 <3=>3
+//       Selects DMA Stream (only Stream 2 or 3 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 7 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_STREAM          2
+#define RTE_I2C2_RX_DMA_CHANNEL         7
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_STREAM          7
+#define RTE_I2C2_TX_DMA_CHANNEL         7
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3]
+//  Configuration settings for Driver_I2C3 in component ::Drivers:I2C
+#define RTE_I2C3                        0
+
+//    I2C3_SCL Pin <0=>PH7 <1=>PA8
+#define RTE_I2C3_SCL_PORT_ID            0
+#if    (RTE_I2C3_SCL_PORT_ID == 0)
+#define RTE_I2C3_SCL_PORT               GPIOH
+#define RTE_I2C3_SCL_BIT                7
+#elif  (RTE_I2C3_SCL_PORT_ID == 1)
+#define RTE_I2C3_SCL_PORT               GPIOA
+#define RTE_I2C3_SCL_BIT                8
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    I2C3_SDA Pin <0=>PH8 <1=>PC9
+#define RTE_I2C3_SDA_PORT_ID            0
+#if    (RTE_I2C3_SDA_PORT_ID == 0)
+#define RTE_I2C3_SDA_PORT               GPIOH
+#define RTE_I2C3_SDA_BIT                8
+#elif  (RTE_I2C3_SDA_PORT_ID == 1)
+#define RTE_I2C3_SDA_PORT               GPIOC
+#define RTE_I2C3_SDA_BIT                9
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_RX_DMA                 1
+#define RTE_I2C3_RX_DMA_NUMBER          1
+#define RTE_I2C3_RX_DMA_STREAM          2
+#define RTE_I2C3_RX_DMA_CHANNEL         3
+#define RTE_I2C3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_TX_DMA                 1
+#define RTE_I2C3_TX_DMA_NUMBER          1
+#define RTE_I2C3_TX_DMA_STREAM          4
+#define RTE_I2C3_TX_DMA_CHANNEL         3
+#define RTE_I2C3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+//  Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1                        0
+
+//    SPI1_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//    SPI1_SCK Pin <0=>PA5 <1=>PB3
+#define RTE_SPI1_SCL_PORT_ID            0
+#if    (RTE_SPI1_SCL_PORT_ID == 0)
+#define RTE_SPI1_SCL_PORT               GPIOA
+#define RTE_SPI1_SCL_BIT                5
+#elif  (RTE_SPI1_SCL_PORT_ID == 1)
+#define RTE_SPI1_SCL_PORT               GPIOB
+#define RTE_SPI1_SCL_BIT                3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//    SPI1_MISO Pin <0=>PA6 <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID           0
+#if    (RTE_SPI1_MISO_PORT_ID == 0)
+#define RTE_SPI1_MISO_PORT              GPIOA
+#define RTE_SPI1_MISO_BIT               6
+#elif  (RTE_SPI1_MISO_PORT_ID == 1)
+#define RTE_SPI1_MISO_PORT              GPIOB
+#define RTE_SPI1_MISO_BIT               4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    SPI1_MOSI Pin <0=>PA7 <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID           0
+#if    (RTE_SPI1_MOSI_PORT_ID == 0)
+#define RTE_SPI1_MOSI_PORT              GPIOA
+#define RTE_SPI1_MOSI_BIT               7
+#elif  (RTE_SPI1_MOSI_PORT_ID == 1)
+#define RTE_SPI1_MOSI_PORT              GPIOB
+#define RTE_SPI1_MOSI_BIT               5
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_RX_DMA                 1
+#define RTE_SPI1_RX_DMA_NUMBER          2
+#define RTE_SPI1_RX_DMA_STREAM          0
+#define RTE_SPI1_RX_DMA_CHANNEL         3
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <5=>5
+//       Selects DMA Stream (only Stream 3 or 5 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_TX_DMA                 1
+#define RTE_SPI1_TX_DMA_NUMBER          2
+#define RTE_SPI1_TX_DMA_STREAM          5
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+//  Configuration settings for Driver_SPI2 in component ::Drivers:SPI
+#define RTE_SPI2                        0
+
+//    SPI2_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//    SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1
+#define RTE_SPI2_SCL_PORT_ID            0
+#if    (RTE_SPI2_SCL_PORT_ID == 0)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                10
+#elif  (RTE_SPI2_SCL_PORT_ID == 1)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                13
+#elif  (RTE_SPI2_SCL_PORT_ID == 2)
+#define RTE_SPI2_SCL_PORT               GPIOI
+#define RTE_SPI2_SCL_BIT                1
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//    SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO_PORT              GPIOC
+#define RTE_SPI2_MISO_BIT               2
+#elif  (RTE_SPI2_MISO_PORT_ID == 2)
+#define RTE_SPI2_MISO_PORT              GPIOI
+#define RTE_SPI2_MISO_BIT               2
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI_PORT              GPIOC
+#define RTE_SPI2_MOSI_BIT               3
+#elif  (RTE_SPI2_MOSI_PORT_ID == 2)
+#define RTE_SPI2_MOSI_PORT              GPIOI
+#define RTE_SPI2_MOSI_BIT               3
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_RX_DMA                 1
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_STREAM          2
+#define RTE_SPI2_RX_DMA_CHANNEL         0
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_TX_DMA                 1
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_STREAM          3
+#define RTE_SPI2_TX_DMA_CHANNEL         0
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+//  Configuration settings for Driver_SPI3 in component ::Drivers:SPI
+#define RTE_SPI3                        0
+
+//    SPI3_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//    SPI3_SCK Pin <0=>PB3 <1=>PC10
+#define RTE_SPI3_SCL_PORT_ID            0
+#if    (RTE_SPI3_SCL_PORT_ID == 0)
+#define RTE_SPI3_SCL_PORT               GPIOB
+#define RTE_SPI3_SCL_BIT                3
+#elif  (RTE_SPI3_SCL_PORT_ID == 1)
+#define RTE_SPI3_SCL_PORT               GPIOC
+#define RTE_SPI3_SCL_BIT                10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//    SPI3_MISO Pin <0=>PB4 <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID           0
+#if    (RTE_SPI3_MISO_PORT_ID == 0)
+#define RTE_SPI3_MISO_PORT              GPIOB
+#define RTE_SPI3_MISO_BIT               4
+#elif  (RTE_SPI3_MISO_PORT_ID == 1)
+#define RTE_SPI3_MISO_PORT              GPIOC
+#define RTE_SPI3_MISO_BIT               11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    SPI3_MOSI Pin <0=>PB5 <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID           0
+#if    (RTE_SPI3_MOSI_PORT_ID == 0)
+#define RTE_SPI3_MOSI_PORT              GPIOB
+#define RTE_SPI3_MOSI_BIT               5
+#elif  (RTE_SPI3_MOSI_PORT_ID == 1)
+#define RTE_SPI3_MOSI_PORT              GPIOC
+#define RTE_SPI3_MOSI_BIT               12
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_RX_DMA                 1
+#define RTE_SPI3_RX_DMA_NUMBER          1
+#define RTE_SPI3_RX_DMA_STREAM          0
+#define RTE_SPI3_RX_DMA_CHANNEL         0
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5 <7=>7
+//       Selects DMA Stream (only Stream 5 or 7 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_TX_DMA                 1
+#define RTE_SPI3_TX_DMA_NUMBER          1
+#define RTE_SPI3_TX_DMA_STREAM          5
+#define RTE_SPI3_TX_DMA_CHANNEL         0
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SDIO (Secure Digital Input/Output) [Driver_MCI0]
+//  Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDIO                        1
+
+//    SDIO_CD (Card Detect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_CD_PIN                 1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(7)
+#define RTE_SDIO_CD_BIT                 15
+
+//    SDIO_WP (Write Protect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_WP_PIN                 0
+#define RTE_SDIO_WP_ACTIVE              0
+#define RTE_SDIO_WP_PORT                GPIO_PORT(7)
+#define RTE_SDIO_WP_BIT                 16
+
+//    SDIO Bus
+//      SDIO_CK Pin <0=>PC12
+#define RTE_SDIO_CK_PORT_ID             0
+#if    (RTE_SDIO_CK_PORT_ID == 0)
+#define RTE_SDIO_CK_PORT                GPIOC
+#define RTE_SDIO_CK_PIN                 12
+#else
+#error "Invalid SDIO_CK Pin Configuration!"
+#endif
+//      SDIO_CMD Pin <0=>PD2
+#define RTE_SDIO_CMD_PORT_ID            0
+#if    (RTE_SDIO_CMD_PORT_ID == 0)
+#define RTE_SDIO_CMD_PORT               GPIOD
+#define RTE_SDIO_CMD_PIN                2
+#else
+#error "Invalid SDIO_CDM Pin Configuration!"
+#endif
+//      SDIO_D0 Pin <0=>PC8
+#define RTE_SDIO_D0_PORT_ID             0
+#if    (RTE_SDIO_D0_PORT_ID == 0)
+#define RTE_SDIO_D0_PORT                GPIOC
+#define RTE_SDIO_D0_PIN                 8
+#else
+#error "Invalid SDIO_D0 Pin Configuration!"
+#endif
+//      SDIO_D1 Pin <0=>PC9
+#define RTE_SDIO_D1_PORT_ID             0
+#if    (RTE_SDIO_D1_PORT_ID == 0)
+#define RTE_SDIO_D1_PORT                GPIOC
+#define RTE_SDIO_D1_PIN                 9
+#else
+#error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//      SDIO_D2 Pin <0=>PC10
+#define RTE_SDIO_D2_PORT_ID             0
+#if    (RTE_SDIO_D2_PORT_ID == 0)
+#define RTE_SDIO_D2_PORT                GPIOC
+#define RTE_SDIO_D2_PIN                 10
+#else
+#error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//      SDIO_D3 Pin <0=>PC11
+#define RTE_SDIO_D3_PORT_ID             0
+#if    (RTE_SDIO_D3_PORT_ID == 0)
+#define RTE_SDIO_D3_PORT                GPIOC
+#define RTE_SDIO_D3_PIN                 11
+#else
+#error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//      SDIO_D4 Pin <0=>PB8
+#define RTE_SDIO_D4_PORT_ID             0
+#if    (RTE_SDIO_D4_PORT_ID == 0)
+#define RTE_SDIO_D4_PORT                GPIOB
+#define RTE_SDIO_D4_PIN                 8
+#else
+#error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//      SDIO_D5 Pin <0=>PB9
+#define RTE_SDIO_D5_PORT_ID             0
+#if    (RTE_SDIO_D5_PORT_ID == 0)
+#define RTE_SDIO_D5_PORT                GPIOB
+#define RTE_SDIO_D5_PIN                 9
+#else
+#error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//      SDIO_D6 Pin <0=>PC6
+#define RTE_SDIO_D6_PORT_ID             0
+#if    (RTE_SDIO_D6_PORT_ID == 0)
+#define RTE_SDIO_D6_PORT                GPIOC
+#define RTE_SDIO_D6_PIN                 6
+#else
+#error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//      SDIO_D7 Pin <0=>PC7
+#define RTE_SDIO_D7_PORT_ID             0
+#if    (RTE_SDIO_D7_PORT_ID == 0)
+#define RTE_SDIO_D7_PORT                GPIOC
+#define RTE_SDIO_D7_PIN                 7
+#else
+#error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//   
+
+//    DMA
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <6=>6
+//       Selects DMA Stream (only Stream 3 or 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SDIO_DMA                    1
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_STREAM             3
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// 
+
+
+//  ETH (Ethernet Interface) [Driver_ETH_MAC0]
+//  Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define RTE_ETH                         1
+
+//    MII (Media Independent Interface)
+#define RTE_ETH_MII                     0
+
+//      ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#elif  (RTE_ETH_MII_TXD0_PORT_ID == 1)
+#define RTE_ETH_MII_TXD0_PORT           GPIOG
+#define RTE_ETH_MII_TXD0_PIN            13
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//      ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#elif  (RTE_ETH_MII_TXD1_PORT_ID == 1)
+#define RTE_ETH_MII_TXD1_PORT           GPIOG
+#define RTE_ETH_MII_TXD1_PIN            14
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//      ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//      ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#elif  (RTE_ETH_MII_TXD3_PORT_ID == 1)
+#define RTE_ETH_MII_TXD3_PORT           GPIOE
+#define RTE_ETH_MII_TXD3_PIN            2
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//      ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#elif  (RTE_ETH_MII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOG
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//      ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_PORT_ID        0
+#if    (RTE_ETH_MII_RXD0_PORT_ID == 0)
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+//      ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_PORT_ID        0
+#if    (RTE_ETH_MII_RXD1_PORT_ID == 0)
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+//      ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6
+#define RTE_ETH_MII_RXD2_PORT_ID        0
+#if    (RTE_ETH_MII_RXD2_PORT_ID == 0)
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif  (RTE_ETH_MII_RXD2_PORT_ID == 1)
+#define RTE_ETH_MII_RXD2_PORT           GPIOH
+#define RTE_ETH_MII_RXD2_PIN            6
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+//      ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7
+#define RTE_ETH_MII_RXD3_PORT_ID        0
+#if    (RTE_ETH_MII_RXD3_PORT_ID == 0)
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RXD3_PORT           GPIOH
+#define RTE_ETH_MII_RXD3_PIN            7
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+//      ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_PORT_ID       0
+#if    (RTE_ETH_MII_RX_DV_PORT_ID == 0)
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+//      ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOI
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//      ETH_MII_CRS Pin <0=>PA0 <1=>PH2
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#elif  (RTE_ETH_MII_CRS_PORT_ID == 1)
+#define RTE_ETH_MII_CRS_PORT            GPIOH
+#define RTE_ETH_MII_CRS_PIN             2
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//      ETH_MII_COL Pin <0=>PA3 <1=>PH3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#elif  (RTE_ETH_MII_COL_PORT_ID == 1)
+#define RTE_ETH_MII_COL_PORT            GPIOH
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//   
+
+//    RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    1
+
+//      ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_RMII_TXD0_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#elif  (RTE_ETH_RMII_TXD0_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOG
+#define RTE_ETH_RMII_TXD0_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_RMII_TXD1_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#elif  (RTE_ETH_RMII_TXD1_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOG
+#define RTE_ETH_RMII_TXD1_PIN           14
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      1
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#elif  (RTE_ETH_RMII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOG
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//      ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//      ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_PORT_ID     0
+#if    (RTE_ETH_RMII_CRS_DV_PORT_ID == 0)
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   
+
+//    Management Data Interface
+//      ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//      ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   
+
+//    Reference 25MHz/50MHz Clock generation
+#define RTE_ETH_REF_CLOCK               0
+
+//      MCO Pin <0=>PA2 <1=>PC9
+#define RTE_ETH_REF_CLOCK_PORT_ID       0
+#if    (RTE_ETH_REF_CLOCK_PORT_ID == 0)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOA
+#define RTE_ETH_REF_CLOCK_PIN           8
+#elif  (RTE_ETH_REF_CLOCK_PORT_ID == 1)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOC
+#define RTE_ETH_REF_CLOCK_PIN           9
+#else
+#error "Invalid MCO Pin Configuration!"
+#endif
+
+//   
+
+// 
+
+
+//  USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//    Device [Driver_USBD0]
+//    Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_OTG_FS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_FS_DEV_EP           0x0000000F
+#define RTE_USB_OTG_FS_DEV_EP_BULK      0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_INT       0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_ISO       0x000E000E
+
+//   
+
+//    Host [Driver_USBH0]
+//    Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(7)
+#define RTE_OTG_FS_VBUS_BIT             5
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_FS_OC_BIT               11
+//   
+
+// 
+
+
+//  USB OTG High-speed
+#define RTE_USB_OTG_HS                  0
+
+//    PHY (Physical Layer)
+
+//      PHY Interface
+//       <0=>On-chip full-speed PHY
+//       <1=>External ULPI high-speed PHY
+#define RTE_USB_OTG_HS_PHY              1
+
+//      External ULPI Pins (UTMI+ Low Pin Interface)
+
+//        OTG_HS_ULPI_CK Pin <0=>PA5
+#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_CK_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_CK_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_CK Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOI
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     11
+#elif  (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     2
+#else
+#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_STP Pin <0=>PC0
+#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_STP_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_STP_PIN     0
+#else
+#error "Invalid OTG_HS_ULPI_STP Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1
+#if    (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     2
+#elif  (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOH
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     4
+#else
+#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D0 Pin <0=>PA3
+#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D0_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_D0_PIN      3
+#else
+#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D1 Pin <0=>PB0
+#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D1_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D1_PIN      0
+#else
+#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D2 Pin <0=>PB1
+#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D2_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D2_PIN      1
+#else
+#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D3 Pin <0=>PB10
+#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D3_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D3_PIN      10
+#else
+#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D4 Pin <0=>PB11
+#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D4_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D4_PIN      11
+#else
+#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D5 Pin <0=>PB12
+#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D5_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D5_PIN      12
+#else
+#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D6 Pin <0=>PB13
+#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D6_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D6_PIN      13
+#else
+#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D7 Pin <0=>PB5
+#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D7_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D7_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!"
+#endif
+
+//     
+
+//   
+
+//    Device [Driver_USBD1]
+//    Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+#define RTE_USB_OTG_HS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 4
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 5
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_HS_DEV_EP           0x0000003F
+#define RTE_USB_OTG_HS_DEV_EP_BULK      0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_INT       0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_ISO       0x003E003E
+
+//   
+
+//    Host [Driver_USBH1]
+//    Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define RTE_USB_OTG_HS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_VBUS_PIN             1
+#define RTE_OTG_HS_VBUS_ACTIVE          0
+#define RTE_OTG_HS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_HS_VBUS_BIT             2
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_OC_PIN               1
+#define RTE_OTG_HS_OC_ACTIVE            0
+#define RTE_OTG_HS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_HS_OC_BIT               12
+//   
+
+// 
+
+
+//  EXTI (External Interrupt/Event Controller)
+#define RTE_EXTI                        0
+
+//    EXTI0 Line
+#define RTE_EXTI0                       0
+//      Pin   <0=>PA0  <1=>PB0  <2=>PC0  <3=>PD0  <4=>PE0  <5=>PF0  <6=>PG0  <7=>PH0  <8=>PI0
+#define RTE_EXTI0_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI0_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI0_TRIGGER               0
+//   
+
+//    EXTI1 Line
+#define RTE_EXTI1                       0
+//      Pin   <0=>PA1  <1=>PB1  <2=>PC1  <3=>PD1  <4=>PE1  <5=>PF1  <6=>PG1  <7=>PH1  <8=>PI1
+#define RTE_EXTI1_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI1_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI1_TRIGGER               0
+//   
+
+//    EXTI2 Line
+#define RTE_EXTI2                       0
+//      Pin   <0=>PA2  <1=>PB2  <2=>PC2  <3=>PD2  <4=>PE2  <5=>PF2  <6=>PG2  <7=>PH2  <8=>PI2
+#define RTE_EXTI2_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI2_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI2_TRIGGER               0
+//   
+
+//    EXTI3 Line
+#define RTE_EXTI3                       0
+//      Pin   <0=>PA3  <1=>PB3  <2=>PC3  <3=>PD3  <4=>PE3  <5=>PF3  <6=>PG3  <7=>PH3  <8=>PI3
+#define RTE_EXTI3_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI3_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI3_TRIGGER               0
+//   
+
+//    EXTI4 Line
+#define RTE_EXTI4                       0
+//      Pin   <0=>PA4  <1=>PB4  <2=>PC4  <3=>PD4  <4=>PE4  <5=>PF4  <6=>PG4  <7=>PH4  <8=>PI4
+#define RTE_EXTI4_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI4_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI4_TRIGGER               0
+//   
+
+//    EXTI5 Line
+#define RTE_EXTI5                       0
+//      Pin   <0=>PA5  <1=>PB5  <2=>PC5  <3=>PD5  <4=>PE5  <5=>PF5  <6=>PG5  <7=>PH5  <8=>PI5
+#define RTE_EXTI5_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI5_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI5_TRIGGER               0
+//   
+
+//    EXTI6 Line
+#define RTE_EXTI6                       0
+//      Pin   <0=>PA6  <1=>PB6  <2=>PC6  <3=>PD6  <4=>PE6  <5=>PF6  <6=>PG6  <7=>PH6  <8=>PI6
+#define RTE_EXTI6_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI6_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI6_TRIGGER               0
+//   
+
+//    EXTI7 Line
+#define RTE_EXTI7                       0
+//      Pin   <0=>PA7  <1=>PB7  <2=>PC7  <3=>PD7  <4=>PE7  <5=>PF7  <6=>PG7  <7=>PH7  <8=>PI7
+#define RTE_EXTI7_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI7_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI7_TRIGGER               0
+//   
+
+//    EXTI8 Line
+#define RTE_EXTI8                       0
+//      Pin   <0=>PA8  <1=>PB8  <2=>PC8  <3=>PD8  <4=>PE8  <5=>PF8  <6=>PG8  <7=>PH8  <8=>PI8
+#define RTE_EXTI8_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI8_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI8_TRIGGER               0
+//   
+
+//    EXTI9 Line
+#define RTE_EXTI9                       0
+//      Pin   <0=>PA9  <1=>PB9  <2=>PC9  <3=>PD9  <4=>PE9  <5=>PF9  <6=>PG9  <7=>PH9  <8=>PI9
+#define RTE_EXTI9_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI9_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI9_TRIGGER               0
+//   
+
+//    EXTI10 Line
+#define RTE_EXTI10                      0
+//      Pin   <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10
+#define RTE_EXTI10_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI10_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI10_TRIGGER              0
+//   
+
+//    EXTI11 Line
+#define RTE_EXTI11                      0
+//      Pin   <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11
+#define RTE_EXTI11_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI11_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI11_TRIGGER              0
+//   
+
+//    EXTI12 Line
+#define RTE_EXTI12                      0
+//      Pin   <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12
+#define RTE_EXTI12_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI12_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI12_TRIGGER              0
+//   
+
+//    EXTI13 Line
+#define RTE_EXTI13                      0
+//      Pin   <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13
+#define RTE_EXTI13_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI13_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI13_TRIGGER              0
+//   
+
+//    EXTI14 Line
+#define RTE_EXTI14                      0
+//      Pin   <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14
+#define RTE_EXTI14_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI14_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI14_TRIGGER              0
+//   
+
+//    EXTI15 Line
+#define RTE_EXTI15                      0
+//      Pin   <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15
+#define RTE_EXTI15_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI15_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI15_TRIGGER              0
+//   
+
+//    EXTI16 Line: PVD Output
+#define RTE_EXTI16                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI16_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI16_TRIGGER              0
+//   
+
+//    EXTI17 Line: RTC Alarm
+#define RTE_EXTI17                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI17_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI17_TRIGGER              0
+//   
+
+//    EXTI18 Line: USB OTG FS Wakeup
+#define RTE_EXTI18                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI18_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI18_TRIGGER              0
+//   
+
+//    EXTI19 Line: Ethernet Wakeup
+#define RTE_EXTI19                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI19_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI19_TRIGGER              0
+//   
+
+//    EXTI20 Line: USB OTG HS Wakeup
+#define RTE_EXTI20                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI20_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI20_TRIGGER              0
+//   
+
+//    EXTI21 Line: RTC Tamper and TimeStamp
+#define RTE_EXTI21                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI21_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI21_TRIGGER              0
+//   
+
+//    EXTI22 Line: RTC Wakeup
+#define RTE_EXTI22                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI22_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI22_TRIGGER              0
+//   
+
+// 
+
+
+//  FSMC (Flexible Static Memory Controller)
+#define RTE_FSMC                        0
+
+//    Pin Configuration
+//    Configure Pins
+#define RTE_FSMC_PINS                   0
+
+//      Address Bus Pins
+//       <0=>A[17:16]
+//       <1=>A[10:0]   <2=>A[15:0]   <3=>A[16:0]   <4=>A[17:0]
+//       <5=>A[18:0]   <6=>A[19:0]   <7=>A[20:0]   <8=>A[21:0]
+//       <9=>A[22:0]  <10=>A[23:0]  <11=>A[24:0]  <12=>A[25:0]
+#define RTE_FSMC_ABUS_PINS              10
+//      Data Bus Pins  <0=>D[7:0] <1=>D[15:0]
+#define RTE_FSMC_DBUS_PINS              0
+//      FSMC_NOE Pin
+#define RTE_FSMC_NOE_PIN                0
+//      FSMC_NWE Pin
+#define RTE_FSMC_NWE_PIN                0
+//      FSMC_NBL0 Pin
+#define RTE_FSMC_NBL0_PIN               0
+//      FSMC_NBL1 Pin
+#define RTE_FSMC_NBL1_PIN               0
+//      FSMC_NL Pin
+#define RTE_FSMC_NL_PIN                 0
+//      FSMC_NWAIT Pin
+#define RTE_FSMC_NWAIT_PIN              0
+//      FSMC_CLK Pin
+#define RTE_FSMC_CLK_PIN                0
+//      FSMC_NE1/NCE2 Pin
+#define RTE_FSMC_NE1_PIN                0
+//      FSMC_NE2/NCE3 Pin
+#define RTE_FSMC_NE2_PIN                0
+//      FSMC_NE3/NCE4_1 Pin
+#define RTE_FSMC_NE3_PIN                0
+//      FSMC_NE4 Pin
+#define RTE_FSMC_NE4_PIN                0
+//      FSMC_NCE4_2 Pin
+#define RTE_FSMC_NCE42_PIN              0
+//      FSMC_INT2 Pin
+#define RTE_FSMC_INT2_PIN               0
+//      FSMC_INT3 Pin
+#define RTE_FSMC_INT3_PIN               0
+//      FSMC_INTR Pin
+#define RTE_FSMC_INTR_PIN               0
+//      FSMC_NIORD Pin
+#define RTE_FSMC_NIORD_PIN              0
+//      FSMC_NIOWR Pin
+#define RTE_FSMC_NIOWR_PIN              0
+//      FSMC_NREG Pin
+#define RTE_FSMC_NREG_PIN               0
+//      FSMC_CD Pin
+#define RTE_FSMC_CD_PIN                 0
+
+//   
+
+//    NOR Flash / PSRAM Controller
+
+//      FSMC_NE1 Chip Select
+//      Configure Device on Chip Select FSMC_NE1
+#define RTE_FSMC_NE1                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR1_CBURSTRW          0
+#define RTE_FSMC_BCR1_ASYNCWAIT         0
+#define RTE_FSMC_BCR1_EXTMOD            0
+#define RTE_FSMC_BCR1_WAITEN            1
+#define RTE_FSMC_BCR1_WREN              1
+#define RTE_FSMC_BCR1_WAITCFG           0
+#define RTE_FSMC_BCR1_WRAPMOD           0
+#define RTE_FSMC_BCR1_WAITPOL           0
+#define RTE_FSMC_BCR1_BURSTEN           0
+#define RTE_FSMC_BCR1_FACCEN            1
+#define RTE_FSMC_BCR1_MWID              1
+#define RTE_FSMC_BCR1_MTYP              2
+#define RTE_FSMC_BCR1_MUXEN             1
+#define RTE_FSMC_BCR1_MBKEN             1
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR1_ACCMOD            0
+#define RTE_FSMC_BTR1_DATLAT            15
+#define RTE_FSMC_BTR1_CLKDIV            15
+#define RTE_FSMC_BTR1_BUSTURN           15
+#define RTE_FSMC_BTR1_DATAST            255
+#define RTE_FSMC_BTR1_ADDHLD            15
+#define RTE_FSMC_BTR1_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR1_ACCMOD        0
+#define RTE_FSMC_BWTR1_DATLAT        15
+#define RTE_FSMC_BWTR1_CLKDIV        15
+#define RTE_FSMC_BWTR1_BUSTURN       15
+#define RTE_FSMC_BWTR1_DATAST        255
+#define RTE_FSMC_BWTR1_ADDHLD        15
+#define RTE_FSMC_BWTR1_ADDSET        15
+//       
+//     
+
+//      FSMC_NE2 Chip Select
+//      Configure Device on Chip Select FSMC_NE2
+#define RTE_FSMC_NE2                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR2_CBURSTRW          0
+#define RTE_FSMC_BCR2_ASYNCWAIT         0
+#define RTE_FSMC_BCR2_EXTMOD            0
+#define RTE_FSMC_BCR2_WAITEN            1
+#define RTE_FSMC_BCR2_WREN              1
+#define RTE_FSMC_BCR2_WAITCFG           0
+#define RTE_FSMC_BCR2_WRAPMOD           0
+#define RTE_FSMC_BCR2_WAITPOL           0
+#define RTE_FSMC_BCR2_BURSTEN           0
+#define RTE_FSMC_BCR2_FACCEN            1
+#define RTE_FSMC_BCR2_MWID              1
+#define RTE_FSMC_BCR2_MTYP              0
+#define RTE_FSMC_BCR2_MUXEN             1
+#define RTE_FSMC_BCR2_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR2_ACCMOD            0
+#define RTE_FSMC_BTR2_DATLAT            15
+#define RTE_FSMC_BTR2_CLKDIV            15
+#define RTE_FSMC_BTR2_BUSTURN           15
+#define RTE_FSMC_BTR2_DATAST            255
+#define RTE_FSMC_BTR2_ADDHLD            15
+#define RTE_FSMC_BTR2_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR2_ACCMOD        0
+#define RTE_FSMC_BWTR2_DATLAT        15
+#define RTE_FSMC_BWTR2_CLKDIV        15
+#define RTE_FSMC_BWTR2_BUSTURN       15
+#define RTE_FSMC_BWTR2_DATAST        255
+#define RTE_FSMC_BWTR2_ADDHLD        15
+#define RTE_FSMC_BWTR2_ADDSET        15
+//       
+//     
+
+//      FSMC_NE3 Chip Select
+//      Configure Device on Chip Select FSMC_NE3
+#define RTE_FSMC_NE3                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR3_CBURSTRW          0
+#define RTE_FSMC_BCR3_ASYNCWAIT         0
+#define RTE_FSMC_BCR3_EXTMOD            0
+#define RTE_FSMC_BCR3_WAITEN            1
+#define RTE_FSMC_BCR3_WREN              1
+#define RTE_FSMC_BCR3_WAITCFG           0
+#define RTE_FSMC_BCR3_WRAPMOD           0
+#define RTE_FSMC_BCR3_WAITPOL           0
+#define RTE_FSMC_BCR3_BURSTEN           0
+#define RTE_FSMC_BCR3_FACCEN            1
+#define RTE_FSMC_BCR3_MWID              1
+#define RTE_FSMC_BCR3_MTYP              0
+#define RTE_FSMC_BCR3_MUXEN             1
+#define RTE_FSMC_BCR3_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR3_ACCMOD            0
+#define RTE_FSMC_BTR3_DATLAT            15
+#define RTE_FSMC_BTR3_CLKDIV            15
+#define RTE_FSMC_BTR3_BUSTURN           15
+#define RTE_FSMC_BTR3_DATAST            255
+#define RTE_FSMC_BTR3_ADDHLD            15
+#define RTE_FSMC_BTR3_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR3_ACCMOD        0
+#define RTE_FSMC_BWTR3_DATLAT        15
+#define RTE_FSMC_BWTR3_CLKDIV        15
+#define RTE_FSMC_BWTR3_BUSTURN       15
+#define RTE_FSMC_BWTR3_DATAST        255
+#define RTE_FSMC_BWTR3_ADDHLD        15
+#define RTE_FSMC_BWTR3_ADDSET        15
+//       
+//     
+
+//      FSMC_NE4 Chip Select
+//      Configure Device on Chip Select FSMC_NE4
+#define RTE_FSMC_NE4                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR4_CBURSTRW          0
+#define RTE_FSMC_BCR4_ASYNCWAIT         0
+#define RTE_FSMC_BCR4_EXTMOD            0
+#define RTE_FSMC_BCR4_WAITEN            1
+#define RTE_FSMC_BCR4_WREN              1
+#define RTE_FSMC_BCR4_WAITCFG           0
+#define RTE_FSMC_BCR4_WRAPMOD           0
+#define RTE_FSMC_BCR4_WAITPOL           0
+#define RTE_FSMC_BCR4_BURSTEN           0
+#define RTE_FSMC_BCR4_FACCEN            1
+#define RTE_FSMC_BCR4_MWID              1
+#define RTE_FSMC_BCR4_MTYP              0
+#define RTE_FSMC_BCR4_MUXEN             1
+#define RTE_FSMC_BCR4_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR4_ACCMOD            0
+#define RTE_FSMC_BTR4_DATLAT            15
+#define RTE_FSMC_BTR4_CLKDIV            15
+#define RTE_FSMC_BTR4_BUSTURN           15
+#define RTE_FSMC_BTR4_DATAST            255
+#define RTE_FSMC_BTR4_ADDHLD            15
+#define RTE_FSMC_BTR4_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR4_ACCMOD        0
+#define RTE_FSMC_BWTR4_DATLAT        15
+#define RTE_FSMC_BWTR4_CLKDIV        15
+#define RTE_FSMC_BWTR4_BUSTURN       15
+#define RTE_FSMC_BWTR4_DATAST        255
+#define RTE_FSMC_BWTR4_ADDHLD        15
+#define RTE_FSMC_BWTR4_ADDSET        15
+//       
+//     
+
+//   
+
+//    NAND Flash Controller
+
+//      FSMC_NCE2 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE2
+#define RTE_FSMC_NCE2                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR2_ECCPS             0
+#define RTE_FSMC_PCR2_TAR               0
+#define RTE_FSMC_PCR2_TCLR              0
+#define RTE_FSMC_PCR2_ECCEN             0
+#define RTE_FSMC_PCR2_PWID              0
+#define RTE_FSMC_PCR2_PTYP              1
+#define RTE_FSMC_PCR2_PBKEN             0
+#define RTE_FSMC_PCR2_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR2_IFEN               0
+#define RTE_FSMC_SR2_ILEN               0
+#define RTE_FSMC_SR2_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM2_MEMHIZ           255
+#define RTE_FSMC_PMEM2_MEMHOLD          255
+#define RTE_FSMC_PMEM2_MEMWAIT          255
+#define RTE_FSMC_PMEM2_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT2_ATTHIZ           255
+#define RTE_FSMC_PATT2_ATTHOLD          255
+#define RTE_FSMC_PATT2_ATTWAIT          255
+#define RTE_FSMC_PATT2_ATTSET           255
+
+//       
+
+//     
+
+//      FSMC_NCE3 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE3
+#define RTE_FSMC_NCE3                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR3_ECCPS             0
+#define RTE_FSMC_PCR3_TAR               0
+#define RTE_FSMC_PCR3_TCLR              0
+#define RTE_FSMC_PCR3_ECCEN             0
+#define RTE_FSMC_PCR3_PWID              0
+#define RTE_FSMC_PCR3_PTYP              1
+#define RTE_FSMC_PCR3_PBKEN             0
+#define RTE_FSMC_PCR3_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR3_IFEN               0
+#define RTE_FSMC_SR3_ILEN               0
+#define RTE_FSMC_SR3_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM3_MEMHIZ           255
+#define RTE_FSMC_PMEM3_MEMHOLD          255
+#define RTE_FSMC_PMEM3_MEMWAIT          255
+#define RTE_FSMC_PMEM3_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT3_ATTHIZ           255
+#define RTE_FSMC_PATT3_ATTHOLD          255
+#define RTE_FSMC_PATT3_ATTWAIT          255
+#define RTE_FSMC_PATT3_ATTSET           255
+
+//       
+
+//     
+
+//   
+
+//    PC Card Controller
+
+//      FSMC_NCE4_x Chip Select
+//      Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2
+#define RTE_FSMC_NCE4              0
+
+//        PC Card Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: PC Card memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR4_ECCPS             0
+#define RTE_FSMC_PCR4_TAR               0
+#define RTE_FSMC_PCR4_TCLR              0
+#define RTE_FSMC_PCR4_ECCEN             0
+#define RTE_FSMC_PCR4_PWID              0
+#define RTE_FSMC_PCR4_PTYP              0
+#define RTE_FSMC_PCR4_PBKEN             0
+#define RTE_FSMC_PCR4_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR4_IFEN               0
+#define RTE_FSMC_SR4_ILEN               0
+#define RTE_FSMC_SR4_IREN               0
+
+//       
+
+//        Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM4_MEMHIZ           255
+#define RTE_FSMC_PMEM4_MEMHOLD          255
+#define RTE_FSMC_PMEM4_MEMWAIT          255
+#define RTE_FSMC_PMEM4_MEMSET           255
+
+//       
+
+//        Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT4_ATTHIZ           255
+#define RTE_FSMC_PATT4_ATTHOLD          255
+#define RTE_FSMC_PATT4_ATTWAIT          255
+#define RTE_FSMC_PATT4_ATTSET           255
+
+//       
+
+//        I/O space timing
+//          IOHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a PC Card write access. Only valid for write transaction.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE,
+//           SMNOE), for PC Card read or write access. The duration for command assertion is
+//           extended if the wait signal (NWAIT) is active (low) at the end of the
+//           programmed value of HCLK.
+//           0000 0000: reserved, do not use this value
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles
+//          IOSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PIO4_IOHIZ             255
+#define RTE_FSMC_PIO4_IOHOLD            255
+#define RTE_FSMC_PIO4_IOWAIT            255
+#define RTE_FSMC_PIO4_IOSET             255
+
+//       
+
+//     
+
+//   
+
+// 
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s
new file mode 100644
index 000000000..d398143ef
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s
@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00007000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/system_stm32f2xx.c
new file mode 100644
index 000000000..da0e189c8
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/system_stm32f2xx.c
@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2011 STMicroelectronics

+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config.c
new file mode 100644
index 000000000..78564b080
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config.c
@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// File System
+// Define File System global parameters
+
+//   Number of open files <4-16>
+//   Define number of files that can be
+//   opened at the same time.
+//   Default: 8
+#define NUM_FILES               8
+
+//   FAT Name Cache Size <0-1000000>
+//   Define number of cached FAT file or directory names.
+//   48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   Relocate FAT Name Cache Buffer
+//   Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config_MC_0.h
new file mode 100644
index 000000000..0b1c6d3a7
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/File_System/FS_Config_MC_0.h
@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Memory Card Drive 0
+// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   Connect to hardware via Driver_MCI# <0-255>
+//   Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   Connect to hardware via Driver_SPI# <0-255>
+//   Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   Memory Card Interface Mode <0=>Native <1=>SPI
+//   Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   Drive Cache stores data sectors and may be increased to speed-up
+//   file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   Locate Drive Cache and Drive Buffer
+//   Some microcontrollers support DMA only in specific memory areas and
+//   require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   
+
+//   Use FAT Journal
+//   Protect File Allocation Table and Directory Entries for
+//   fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   Default Drive "M0:"
+//   Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config.c
new file mode 100644
index 000000000..6b9dc8e00
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config.c
@@ -0,0 +1,153 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// System Definitions
+//  Global Network System definitions
+//   Local Host Name
+//    This is the name under which embedded host can be
+//    accessed on a local area network.
+//    Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   Memory Pool size <1536-262144:4><#/4>
+//    This is the size of a memory pool in bytes. Buffers for
+//    Network packets are allocated from this memory pool.
+//    Default: 12000 bytes
+#define NET_MEM_SIZE            3000
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP_0
+#include "Net_Config_PPP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_PPP_1
+#include "Net_Config_PPP_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP_0
+#include "Net_Config_SLIP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_SLIP_1
+#include "Net_Config_SLIP_1.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (ERROR_CODE error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (ERROR_CODE error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer Corrupted */
+      /* More data written than the size of allocated mem block */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_BSD.h
new file mode 100644
index 000000000..d7e6a614a
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_BSD.h
@@ -0,0 +1,36 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_BSD.h
+ * Purpose: Network Configuration BSD Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Berkley (BSD) Sockets
+#define BSD_ENABLE              1
+
+//   Number of BSD Sockets <1-20>
+//    Number of available Berkeley Sockets
+//    Default: 2
+#define BSD_NUM_SOCKS           7
+
+//   Number of Streaming Server Sockets <0-20>
+//    Defines a number of Streaming (TCP) Server sockets,
+//    that listen for an incoming connection from the client.
+//    Default: 1
+#define BSD_SERVER_SOCKS        1
+
+//   Receive Timeout in seconds <0-600>
+//    A timeout for socket receive in blocking mode.
+//    Timeout value of 0 means indefinite timeout.
+//    Default: 20
+#define BSD_RECEIVE_TOUT        20
+
+//   Hostname Resolver
+//    Enable or disable Berkeley style hostname resolver.
+#define BSD_HOSTNAME_ENABLE     0
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_DNS_Client.h
new file mode 100644
index 000000000..d30b71807
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_DNS_Client.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Service
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_DNS_Client.h
+ * Purpose: Network Configuration DNS Client
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// DNS Client
+#define DNS_CLIENT_ENABLE       1
+
+//     Cache Table size <5-100>
+//      Number of cached DNS host names/IP addresses
+//      Default: 20
+#define DNS_CLIENT_TAB_SIZE     20
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_ETH_0.h
new file mode 100644
index 000000000..7be57ad6d
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_ETH_0.h
@@ -0,0 +1,222 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_ETH_0.h
+ * Purpose: Network Configuration ETH Interface
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Ethernet Network Interface 0
+#define ETH0_ENABLE             1
+
+//   Connect to hardware via Driver_ETH# <0-255>
+//   Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER             1
+
+//   MAC Address
+//    Local Ethernet MAC Address
+//    Value FF:FF:FF:FF:FF:FF is not allowed.
+//    It is an ethernet Broadcast MAC address.
+//     Address byte 1 <0x00-0xff:2>
+//      LSB is an ethernet Multicast bit.
+//      Must be 0 for local MAC address.
+//      Default: 0x1E
+#define ETH0_MAC1               0x1E
+
+//     Address byte 2 <0x00-0xff>
+//      Default: 0x30
+#define ETH0_MAC2               0x30
+
+//     Address byte 3 <0x00-0xff>
+//      Default: 0x6C
+#define ETH0_MAC3               0x6C
+
+//     Address byte 4 <0x00-0xff>
+//      Default: 0xA2
+#define ETH0_MAC4               0xA2
+
+//     Address byte 5 <0x00-0xff>
+//      Default: 0x45
+#define ETH0_MAC5               0x45
+
+//     Address byte 6 <0x00-0xff>
+//      Default: 0x5E
+#define ETH0_MAC6               0x5E
+//   
+
+//   IP Address
+//    Local Static IP Address
+//    Value 255.255.255.255 is not allowed.
+//    It is a Broadcast IP address.
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_IP1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_IP2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_IP3                0
+
+//     Address byte 4 <0-255>
+//      Default: 100
+#define ETH0_IP4                100
+//   
+
+//   Subnet mask
+//    Local Subnet mask
+//     Mask byte 1 <0-255>
+//      Default: 255
+#define ETH0_MASK1              255
+
+//     Mask byte 2 <0-255>
+//      Default: 255
+#define ETH0_MASK2              255
+
+//     Mask byte 3 <0-255>
+//      Default: 255
+#define ETH0_MASK3              255
+
+//     Mask byte 4 <0-255>
+//      Default: 0
+#define ETH0_MASK4              0
+//   
+
+//   Default Gateway
+//    Default Gateway IP Address
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_GW1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_GW2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_GW3                0
+
+//     Address byte 4 <0-255>
+//      Default: 254
+#define ETH0_GW4                254
+//   
+
+//   Primary DNS Server
+//    Primary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_PRI_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_PRI_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_PRI_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 129
+#define ETH0_PRI_DNS4           129
+//   
+
+//   Secondary DNS Server
+//    Secondary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_SEC_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_SEC_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_SEC_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 130
+#define ETH0_SEC_DNS4           130
+//   
+
+//   ARP Definitions
+//    Address Resolution Protocol Definitions
+//     Cache Table size <5-100>
+//      Number of cached hardware/IP addresses
+//      Default: 10
+#define ETH0_ARP_TAB_SIZE       10
+
+//     Cache Timeout in seconds <5-255>
+//      A timeout for a cached hardware/IP addresses
+//      Default: 150
+#define ETH0_ARP_CACHE_TOUT     150
+
+//     Number of Retries <0-20>
+//      Number of Retries to resolve an IP address
+//      before ARP module gives up
+//      Default: 4
+#define ETH0_ARP_MAX_RETRY      4
+
+//     Resend Timeout in seconds <1-10>
+//      A timeout to resend the ARP Request
+//      Default: 2
+#define ETH0_ARP_RESEND_TOUT    2
+
+//     Send Notification on Address changes
+//      When this option is enabled, the embedded host
+//      will send a Gratuitous ARP notification at startup,
+//      or when the device IP address has changed.
+//      Default: Disabled
+#define ETH0_ARP_NOTIFY         0
+//   
+
+//   IGMP Group Management
+//    Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE        0
+
+//     Membership Table size <2-50>
+//      Number of Groups this host can join
+//      Default: 5
+#define ETH0_IGMP_TAB_SIZE      5
+//   
+
+//   NetBIOS Name Service
+//    When this option is enabled, the embedded host can be
+//    accessed by his name on the local LAN using NBNS protocol.
+//    You need to modify also the number of UDP Sockets,
+//    because NBNS protocol uses one UDP socket to run.
+#define ETH0_NBNS_ENABLE        1
+
+//   Dynamic Host Configuration
+//    When this option is enabled, local IP address, Net Mask
+//    and Default Gateway are obtained automatically from
+//    the DHCP Server on local LAN.
+//    You need to modify also the number of UDP Sockets,
+//    because DHCP protocol uses one UDP socket to run.
+#define ETH0_DHCP_ENABLE        1
+
+//     Vendor Class Identifier
+//      This value is optional. If specified, it is added
+//      to DHCP request message, identifying vendor type.
+//      Default: ""
+#define ETH0_DHCP_VCID          ""
+
+//     Bootfile Name
+//      This value is optional. If enabled, the Bootfile Name
+//      (option 67) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_BOOTFILE      0
+
+//     NTP Servers
+//      This value is optional. If enabled, a list of NTP Servers
+//      (option 42) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_NTP_SERVERS   0
+//   
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_TCP.h
new file mode 100644
index 000000000..e659ce921
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_TCP.h
@@ -0,0 +1,61 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_TCP.h
+ * Purpose: Network Configuration TCP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// TCP Sockets
+#define TCP_ENABLE              1
+
+//   Number of TCP Sockets <1-20>
+//    Number of available TCP sockets
+//    Default: 5
+#define TCP_NUM_SOCKS           10
+
+//   Number of Retries <0-20>
+//    How many times TCP module will try to retransmit data
+//    before giving up. Increase this value for high-latency
+//    and low_throughput networks.
+//    Default: 5
+#define TCP_MAX_RETRY           5
+
+//   Retry Timeout in seconds <1-10>
+//    If data frame not acknowledged within this time frame,
+//    TCP module will try to resend the data again.
+//    Default: 4
+#define TCP_RETRY_TOUT          4
+
+//   Default Connect Timeout in seconds <1-600>
+//    Default TCP Socket Keep Alive timeout. When it expires
+//    with no TCP data frame send, TCP Connection is closed.
+//    Default: 120
+#define TCP_DEFAULT_TOUT        120
+
+//   Maximum Segment Size <536-1460>
+//    The Maximum Segment Size specifies the maximum
+//    number of bytes in the TCP segment's Data field.
+//    Default: 1460
+#define TCP_MAX_SEG_SIZE        1460
+
+//   Receive Window Size <536-65535>
+//    Receive Window Size specifies the size of data, 
+//    that the socket is able to buffer in flow-control mode.
+//    Default: 4380
+#define TCP_RECEIVE_WIN_SIZE    4380
+
+// 
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT  1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT      2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY       7
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_UDP.h
new file mode 100644
index 000000000..b7995c22d
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Config_UDP.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_UDP.h
+ * Purpose: Network Configuration UDP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// UDP Sockets
+#define UDP_ENABLE              1
+
+//   Number of UDP Sockets <1-20>
+//    Number of available UDP sockets
+//    Default: 5
+#define UDP_NUM_SOCKS           10
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Debug.c
new file mode 100644
index 000000000..735089a40
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/Network/Net_Debug.c
@@ -0,0 +1,125 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Debug.c
+ * Purpose: Network Debug Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Print Time Stamp
+//    Enable printing the time-info in debug messages
+#define DBG_TIME                1
+
+// TCPnet Debug Definitions
+//   Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Memory debug messages
+#define DBG_MEM                 1
+
+//   Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Ethernet debug messages
+#define DBG_ETH                 0
+
+//   PPP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off PPP debug messages
+#define DBG_PPP                 0
+
+//   SLIP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SLIP debug messages
+#define DBG_SLIP                0
+
+//   ARP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ARP debug messages
+#define DBG_ARP                 0
+
+//   IP Debug    <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IP debug messages
+#define DBG_IP                  1
+
+//   ICMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ICMP debug messages
+#define DBG_ICMP                1
+
+//   IGMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IGMP debug messages
+#define DBG_IGMP                1
+
+//   UDP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off UDP debug messages
+#define DBG_UDP                 1
+
+//   TCP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TCP debug messages
+#define DBG_TCP                 1
+
+//   NBNS Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off NetBIOS Name Service debug messages
+#define DBG_NBNS                1
+
+//   DHCP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Host Configuration debug messages
+#define DBG_DHCP                1
+
+//   DNS Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Domain Name Service debug messages
+#define DBG_DNS                 1
+
+//   SNMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Management debug messages
+#define DBG_SNMP                1
+
+//   SNTP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Time debug messages
+#define DBG_SNTP                1
+
+//   BSD Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off BSD Interface debug messages
+#define DBG_BSD                 1
+// 
+
+// Application Debug Definitions
+//   HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Web Server debug messages
+#define DBG_HTTP_SERVER         1
+
+//   FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Server debug messages
+#define DBG_FTP_SERVER          1
+
+//   FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Client debug messages
+#define DBG_FTP_CLIENT          1
+
+//   Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Telnet Server debug messages
+#define DBG_TELNET_SERVER       1
+
+//   TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Server debug messages
+#define DBG_TFTP_SERVER         1
+
+//   TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Client debug messages
+#define DBG_TFTP_CLIENT         1
+
+//   SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SMTP Client debug messages
+#define DBG_SMTP_CLIENT         1
+// 
+
+
+#include "net_debug.h"
+
+
+/**
+  \fn          void net_debug_init (void)
+  \brief       Initialize Network Debug Interface.
+*/
+void net_debug_init (void) {
+  /* Add your code to initialize the Debug output. This is usually the  */
+  /* serial interface. The function is called at TCPnet system startup. */
+  /* You may need to customize also the 'putchar()' function.           */
+
+}
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/RTE_Components.h
new file mode 100644
index 000000000..938bd18ea
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/RTE/RTE_Components.h
@@ -0,0 +1,28 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'simpleClient' 
+ * Target:  'SimpleClient' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_ETH_MAC0            /* Driver ETH_MAC0 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_Drivers_PHY_ST802RT1        /* Driver PHY ST802RT1 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+#define RTE_Network_Core                /* Network Core */
+          #define RTE_Network_Debug               /* Network Debug Version */
+#define RTE_Network_DNS_Client          /* Network DNS Client */
+#define RTE_Network_Interface_ETH_0     /* Network Interface ETH 0 */
+#define RTE_Network_Socket_BSD          /* Network Socket BSD */
+#define RTE_Network_Socket_TCP          /* Network Socket TCP */
+#define RTE_Network_Socket_UDP          /* Network Socket UDP */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/SimpleClient/STM32_SWO.ini
new file mode 100644
index 000000000..239abce37
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/STM32_SWO.ini
@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+//  Debug MCU Configuration
+//       DBG_SLEEP      Debug Sleep Mode
+//       DBG_STOP       Debug Stop Mode
+//       DBG_STANDBY    Debug Standby Mode
+//       TRACE_IOEN     Trace I/O Enable 
+//    TRACE_MODE     Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//       DBG_IWDG_STOP  Independant Watchdog Stopped when Core is halted
+//       DBG_WWDG_STOP  Window Watchdog Stopped when Core is halted
+//      DBG_TIM1_STOP  Timer 1 Stopped when Core is halted
+//      DBG_TIM2_STOP  Timer 2 Stopped when Core is halted
+//      DBG_TIM3_STOP  Timer 3 Stopped when Core is halted
+//      DBG_TIM4_STOP  Timer 4 Stopped when Core is halted
+//      DBG_CAN_STOP   CAN Stopped when Core is halted
+// 
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx b/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx
new file mode 100644
index 000000000..93fced476
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/SimpleClient.uvoptx
@@ -0,0 +1,1422 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    SimpleClient
+    0x4
+    ARM-ADS
+    
+      120000000
+      
+        1
+        1
+        0
+        1
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\Object\
+      
+      
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+        1
+        1
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+        1
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+        0
+        0
+        0
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+      
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+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        SARMCM3.DLL
+        -REMAP -MPU
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
+        -REMAP -MPU
+        TCM.DLL
+        -pCM3
+      
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
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+        1
+        1
+        0
+        0
+        8
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        .\STM32_SWO.ini
+        BIN\ULP2CM3.DLL
+      
+      
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          ULP2CM3
+          -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)
+        
+        
+          0
+          DLGUARM
+          
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+        
+      
+      
+      
+        
+          1
+          8
+          0x20000408
+        
+      
+      
+        
+          2
+          8
+          0x8004dc8
+        
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+  
+
+  
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+    
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+      1
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+      .\main.c
+      main.c
+      0
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+    
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+      client.c
+      0
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+
+  
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+      .\config-SimpleClient.h
+      config-SimpleClient.h
+      0
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+    
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+      .\RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
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+    
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+      0
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+      0
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+      .\RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      0
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+  
+
+  
+    Documentation
+    1
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+      3
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+      .\Abstract.txt
+      Abstract.txt
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
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+      C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+      RTX_CM3.lib
+      1
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+    
+    
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+      RTX_Conf_CM.c
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+
+  
+    ::Device
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+      DMA_STM32F2xx.c
+      1
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+    
+    
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+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+      GPIO_STM32F2xx.c
+      1
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+      RTE_Device.h
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+      RTE\Device\STM32F207IG\startup_stm32f2xx.s
+      startup_stm32f2xx.s
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+      system_stm32f2xx.c
+      1
+      0
+    
+  
+
+  
+    ::Drivers
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+    
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+      14
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+      0
+      0
+      0
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+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+      PHY_ST802RT1.c
+      1
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+    
+    
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+      EMAC_STM32F2xx.c
+      1
+      0
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+    
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+      MCI_STM32F2xx.c
+      1
+      0
+    
+  
+
+  
+    ::File System
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+      0
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+      FS_LFN_CM3_L.lib
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+      FS_Config.c
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+      FS_Config_MC_0.h
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+  
+
+  
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+      0
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+      RTE\Network\Net_Config_DNS_Client.h
+      Net_Config_DNS_Client.h
+      1
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+    
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+      Net_Config_ETH_0.h
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+      RTE\Network\Net_Config_TCP.h
+      Net_Config_TCP.h
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+    
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+      RTE\Network\Net_Config_UDP.h
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+      Net_Debug.c
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+  
+
+  
+    ::wolfSSL
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+      0
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+      cyassl_MDK_ARM.c
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+    
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+      time-STM32F2xx.c
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+      aes.c
+      1
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+    
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+      arc4.c
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+    
+      9
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+      1
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+      0
+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+      asm.c
+      1
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+    
+    
+      9
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+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+      asn.c
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+    
+    
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+      blake2b.c
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+      camellia.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+      coding.c
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+      compress.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
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+    
+      9
+      39
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+      dh.c
+      1
+      0
+    
+    
+      9
+      40
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+      dsa.c
+      1
+      0
+    
+    
+      9
+      41
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+      ecc.c
+      1
+      0
+    
+    
+      9
+      42
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+      ecc_fp.c
+      1
+      0
+    
+    
+      9
+      43
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+      error.c
+      1
+      0
+    
+    
+      9
+      44
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+      hc128.c
+      1
+      0
+    
+    
+      9
+      45
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+      hmac.c
+      1
+      0
+    
+    
+      9
+      46
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+      integer.c
+      1
+      0
+    
+    
+      9
+      47
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+      logging.c
+      1
+      0
+    
+    
+      9
+      48
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+      md2.c
+      1
+      0
+    
+    
+      9
+      49
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+      md4.c
+      1
+      0
+    
+    
+      9
+      50
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+      md5.c
+      1
+      0
+    
+    
+      9
+      51
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+      memory.c
+      1
+      0
+    
+    
+      9
+      52
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+      misc.c
+      1
+      0
+    
+    
+      9
+      53
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+      pwdbased.c
+      1
+      0
+    
+    
+      9
+      54
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+      rabbit.c
+      1
+      0
+    
+    
+      9
+      55
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+      random.c
+      1
+      0
+    
+    
+      9
+      56
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+      ripemd.c
+      1
+      0
+    
+    
+      9
+      57
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+      rsa.c
+      1
+      0
+    
+    
+      9
+      58
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+      sha.c
+      1
+      0
+    
+    
+      9
+      59
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+      sha256.c
+      1
+      0
+    
+    
+      9
+      60
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+      sha512.c
+      1
+      0
+    
+    
+      9
+      61
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+      tfm.c
+      1
+      0
+    
+    
+      9
+      62
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+      crl.c
+      1
+      0
+    
+    
+      9
+      63
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+      internal.c
+      1
+      0
+    
+    
+      9
+      64
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+      io.c
+      1
+      0
+    
+    
+      9
+      65
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+      keys.c
+      1
+      0
+    
+    
+      9
+      66
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+      ocsp.c
+      1
+      0
+    
+    
+      9
+      67
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+      sniffer.c
+      1
+      0
+    
+    
+      9
+      68
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+      ssl.c
+      1
+      0
+    
+    
+      9
+      69
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+      tls.c
+      1
+      0
+    
+    
+      9
+      70
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      1
+      0
+    
+    
+      9
+      71
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      1
+      0
+    
+    
+      9
+      72
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config.h
+      config.h
+      1
+      0
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/client.c b/IDE/MDK5-ARM/Projects/SimpleClient/client.c
new file mode 100644
index 000000000..07cf20bea
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/client.c
@@ -0,0 +1,757 @@
+/* client.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+        #include 
+#endif
+ #define CYASSL_MDK_ARM
+#if defined(CYASSL_MDK_ARM)
+        #include 
+        #include 
+
+        #if defined(CYASSL_MDK5)
+            #include "cmsis_os.h"
+            #include "rl_fs.h" 
+            #include "rl_net.h" 
+        #else
+            #include "rtl.h"
+        #endif
+
+        #include "cyassl_MDK_ARM.h"
+#endif
+
+#include 
+
+#if !defined(CYASSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER)
+    /* in case memory tracker wants stats */
+    #define CYASSL_TRACK_MEMORY
+#endif
+
+#include 
+#include 
+
+#include "examples/client/client.h"
+
+#define USE_CYASSL_MEMORY
+
+#ifdef CYASSL_CALLBACKS
+    int handShakeCB(HandShakeInfo*);
+    int timeoutCB(TimeoutInfo*);
+    Timeval timeout;
+#endif
+
+
+static void NonBlockingSSL_Connect(CYASSL* ssl)
+{
+#ifndef CYASSL_CALLBACKS
+    int ret = CyaSSL_connect(ssl);
+#else
+    int ret = CyaSSL_connect_ex(ssl, handShakeCB, timeoutCB, timeout);
+#endif
+    int error = CyaSSL_get_error(ssl, 0);
+    SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl);
+    int select_ret;
+
+    while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ ||
+                                  error == SSL_ERROR_WANT_WRITE)) {
+        int currTimeout = 1;
+
+        if (error == SSL_ERROR_WANT_READ)
+            printf("... client would read block\n");
+        else
+            printf("... client would write block\n");
+
+#ifdef CYASSL_DTLS
+        currTimeout = CyaSSL_dtls_get_current_timeout(ssl);
+#endif
+        select_ret = tcp_select(sockfd, currTimeout);
+
+        if ((select_ret == TEST_RECV_READY) ||
+                                        (select_ret == TEST_ERROR_READY)) {
+            #ifndef CYASSL_CALLBACKS
+                    ret = CyaSSL_connect(ssl);
+            #else
+                ret = CyaSSL_connect_ex(ssl,handShakeCB,timeoutCB,timeout);
+            #endif
+            error = CyaSSL_get_error(ssl, 0);
+        }
+        else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#ifdef CYASSL_DTLS
+        else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) &&
+                                            CyaSSL_dtls_got_timeout(ssl) >= 0) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#endif
+        else {
+            error = SSL_FATAL_ERROR;
+        }
+    }
+    if (ret != SSL_SUCCESS)
+        err_sys("SSL_connect failed");
+}
+
+
+static void Usage(void)
+{
+    printf("client "    LIBCYASSL_VERSION_STRING
+           " NOTE: All files relative to CyaSSL home dir\n");
+    printf("-?          Help, print this usage\n");
+    printf("-h    Host to connect to, default %s\n", yasslIP);
+    printf("-p     Port to connect on, not 0, default %d\n", yasslPort);
+    printf("-v     SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n",
+                                 CLIENT_DEFAULT_VERSION);
+    printf("-l     Cipher list\n");
+    printf("-c    Certificate file,           default %s\n", cliCert);
+    printf("-k    Key file,                   default %s\n", cliKey);
+    printf("-A    Certificate Authority file, default %s\n", caCert);
+    printf("-b     Benchmark  connections and print stats\n");
+    printf("-s          Use pre Shared keys\n");
+    printf("-t          Track CyaSSL memory use\n");
+    printf("-d          Disable peer checks\n");
+    printf("-g          Send server HTTP GET\n");
+    printf("-u          Use UDP DTLS,"
+           " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n");
+    printf("-m          Match domain name in cert\n");
+    printf("-N          Use Non-blocking sockets\n");
+    printf("-r          Resume session\n");
+    printf("-f          Fewer packets/group messages\n");
+    printf("-x          Disable client cert/key loading\n");
+#ifdef SHOW_SIZES
+    printf("-z          Print structure sizes\n");
+#endif
+    printf("-S     Use Host Name Indication\n");
+}
+
+#ifdef CYASSL_MDK_SHELL
+#define exit(code) return(code)
+#endif
+
+#ifdef CYASSL_MDK_SHELL
+    #define exit(code) return(code)
+#endif
+
+
+THREAD_RETURN CYASSL_THREAD client_test(void* args)
+{
+    SOCKET_T sockfd = 0;
+
+    CYASSL_METHOD*  method  = 0;
+    CYASSL_CTX*     ctx     = 0;
+    CYASSL*         ssl     = 0;
+    
+    CYASSL*         sslResume = 0;
+    CYASSL_SESSION* session = 0;
+    char         resumeMsg[] = "resuming cyassl!";
+    int          resumeSz    = sizeof(resumeMsg);
+
+    char msg[32] = "hello cyassl!";   /* GET may make bigger */
+    char reply[80];
+    int  input;
+    int  msgSz = (int)strlen(msg);
+
+    int   port   = yasslPort;
+    char* host   = (char*)yasslIP;
+    char* domain = (char*)"www.yassl.com";
+
+    int    ch;
+    int    version = CLIENT_INVALID_VERSION;
+    int    usePsk   = 0;
+    int    sendGET  = 0;
+    int    benchmark = 0;
+    int    doDTLS    = 0;
+    int    matchName = 0;
+    int    doPeerCheck = 1;
+    int    nonBlocking = 0;
+    int    resumeSession = 0;
+    int    trackMemory   = 0;
+    int    useClientCert = 1;
+    int    fewerPackets  = 0;
+    char*  cipherList = NULL;
+    char*  verifyCert = (char*)caCert;
+    char*  ourCert    = (char*)cliCert;
+    char*  ourKey     = (char*)cliKey;
+
+#ifdef HAVE_SNI
+    char*  sniHostName = NULL;
+#endif
+
+    int     argc = ((func_args*)args)->argc;
+    char**  argv = ((func_args*)args)->argv;
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef NO_RSA
+    verifyCert = (char*)eccCert;
+    ourCert    = (char*)cliEccCert;
+    ourKey     = (char*)cliEccKey;
+#endif
+    (void)resumeSz;
+    (void)session;
+    (void)sslResume;
+    (void)trackMemory;
+
+    while ((ch = mygetopt(argc, argv, "?gdusmNrtfxh:p:v:l:A:c:k:b:zS:")) != -1){
+        switch (ch) {
+            case '?' :
+                Usage();
+                exit(EXIT_SUCCESS);
+
+            case 'g' :
+                sendGET = 1;
+                break;
+
+            case 'd' :
+                doPeerCheck = 0;
+                break;
+
+            case 'u' :
+                doDTLS  = 1;
+                break;
+
+            case 's' :
+                usePsk = 1;
+                break;
+
+            case 't' :
+            #ifdef USE_CYASSL_MEMORY
+                trackMemory = 1;
+            #endif
+                break;
+
+            case 'm' :
+                matchName = 1;
+                break;
+
+            case 'x' :
+                useClientCert = 0;
+                break;
+
+            case 'f' :
+                fewerPackets = 1;
+                break;
+
+            case 'h' :
+                host   = myoptarg;
+                domain = myoptarg;
+                break;
+
+            case 'p' :
+                port = atoi(myoptarg);
+                #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API)
+                    if (port == 0)
+                        err_sys("port number cannot be 0");
+                #endif
+                break;
+
+            case 'v' :
+                version = atoi(myoptarg);
+                if (version < 0 || version > 3) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'l' :
+                cipherList = myoptarg;
+                break;
+
+            case 'A' :
+                verifyCert = myoptarg;
+                break;
+
+            case 'c' :
+                ourCert = myoptarg;
+                break;
+
+            case 'k' :
+                ourKey = myoptarg;
+                break;
+
+            case 'b' :
+                benchmark = atoi(myoptarg);
+                if (benchmark < 0 || benchmark > 1000000) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'N' :
+                nonBlocking = 1;
+                break;
+
+            case 'r' :
+                resumeSession = 1;
+                break;
+
+            case 'z' :
+                #ifndef CYASSL_LEANPSK
+                    CyaSSL_GetObjectSize();
+                #endif
+                break;
+
+            case 'S' :
+                #ifdef HAVE_SNI
+                    sniHostName = myoptarg;
+                #endif
+                break;
+
+            default:
+                Usage();
+                exit(MY_EX_USAGE);
+        }
+    }
+
+    myoptind = 0;      /* reset for test cases */
+
+    /* sort out DTLS versus TLS versions */
+    if (version == CLIENT_INVALID_VERSION) {
+        if (doDTLS)
+            version = CLIENT_DTLS_DEFAULT_VERSION;
+        else
+            version = CLIENT_DEFAULT_VERSION;
+    }
+    else {
+        if (doDTLS) {
+            if (version == 3)
+                version = -2;
+            else
+                version = -1;
+        }
+    }
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        InitMemoryTracker(); 
+#endif
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case 0:
+            method = CyaSSLv3_client_method();
+            break;
+                
+                
+    #ifndef NO_TLS
+        case 1:
+            method = CyaTLSv1_client_method();
+            break;
+
+        case 2:
+            method = CyaTLSv1_1_client_method();
+            break;
+    #endif /* NO_TLS */
+                
+#endif  /* NO_OLD_TLS */
+                
+#ifndef NO_TLS
+        case 3:
+            method = CyaTLSv1_2_client_method();
+            break;
+#endif
+
+#ifdef CYASSL_DTLS
+        case -1:
+            method = CyaDTLSv1_client_method();
+            break;
+
+        case -2:
+            method = CyaDTLSv1_2_client_method();
+            break;
+#endif
+
+        default:
+            err_sys("Bad SSL version");
+            break;
+    }
+
+    if (method == NULL)
+        err_sys("unable to get method");
+
+    ctx = CyaSSL_CTX_new(method);
+    if (ctx == NULL)
+        err_sys("unable to get ctx");
+		
+    if (cipherList)
+        if (CyaSSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS)
+            err_sys("client can't set cipher list 1");
+
+#ifdef CYASSL_LEANPSK
+    usePsk = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    usePsk = 1;
+#endif
+
+    if (fewerPackets)
+        CyaSSL_CTX_set_group_messages(ctx);
+
+    if (usePsk) {
+#ifndef NO_PSK
+        CyaSSL_CTX_set_psk_client_callback(ctx, my_psk_client_cb);
+        if (cipherList == NULL) {
+            const char *defaultCipherList;
+            #ifdef HAVE_NULL_CIPHER
+                defaultCipherList = "PSK-NULL-SHA256";
+            #else
+                defaultCipherList = "PSK-AES128-CBC-SHA256";
+            #endif
+            if (CyaSSL_CTX_set_cipher_list(ctx,defaultCipherList) !=SSL_SUCCESS)
+                err_sys("client can't set cipher list 2");
+        }
+#endif
+        useClientCert = 0;
+    }
+
+#ifdef OPENSSL_EXTRA
+    CyaSSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    if (cipherList == NULL) {
+        /* don't use EDH, can't sniff tmp keys */
+        if (CyaSSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS) {
+            err_sys("client can't set cipher list 3");
+        }
+    }
+#endif
+
+#ifdef USER_CA_CB
+    CyaSSL_CTX_SetCACb(ctx, CaCb);
+#endif
+
+#ifdef VERIFY_CALLBACK
+    CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_PEER, myVerify);
+#endif
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (useClientCert){
+        if (CyaSSL_CTX_use_certificate_chain_file(ctx, ourCert) != SSL_SUCCESS)
+            err_sys("can't load client cert file, check file and run from"
+                    " CyaSSL home dir");
+
+        if (CyaSSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load client private key file, check file and run "
+                    "from CyaSSL home dir");
+    }
+
+    if (!usePsk) {
+        if (CyaSSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS)
+                err_sys("can't load ca file, Please run from CyaSSL home dir");
+    }
+#endif
+#if !defined(NO_CERTS)
+    if (!usePsk && doPeerCheck == 0)
+        CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0);
+#endif
+
+#ifdef HAVE_CAVIUM
+    CyaSSL_CTX_UseCavium(ctx, CAVIUM_DEV_ID);
+#endif
+
+#ifdef HAVE_SNI
+    if (sniHostName)
+        if (CyaSSL_CTX_UseSNI(ctx, 0, sniHostName, XSTRLEN(sniHostName)))
+            err_sys("UseSNI failed");
+#endif
+
+    if (benchmark) {
+        /* time passed in number of connects give average */
+        int times = benchmark;
+        int i = 0;
+
+        double start = current_time(), avg;
+
+        for (i = 0; i < times; i++) {
+            tcp_connect(&sockfd, host, port, doDTLS);
+
+            ssl = CyaSSL_new(ctx);
+            CyaSSL_set_fd(ssl, sockfd);
+            if (CyaSSL_connect(ssl) != SSL_SUCCESS)
+                err_sys("SSL_connect failed");
+
+            CyaSSL_shutdown(ssl);
+            CyaSSL_free(ssl);
+            CloseSocket(sockfd);
+        }
+        avg = current_time() - start;
+        avg /= times;
+        avg *= 1000;   /* milliseconds */
+        printf("CyaSSL_connect avg took: %8.3f milliseconds\n", avg);
+
+        CyaSSL_CTX_free(ctx);
+        ((func_args*)args)->return_code = 0;
+
+        exit(EXIT_SUCCESS);
+    }
+    
+    #if defined(CYASSL_MDK_ARM)
+    CyaSSL_CTX_set_verify(ctx, SSL_VERIFY_NONE, 0);
+    #endif
+    
+    ssl = CyaSSL_new(ctx);
+    if (ssl == NULL)
+        err_sys("unable to get SSL object");
+
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+
+    if (doDTLS) {
+        SOCKADDR_IN_T addr;
+        build_addr(&addr, host, port, 1);
+        CyaSSL_dtls_set_peer(ssl, &addr, sizeof(addr));
+        tcp_socket(&sockfd, 1);
+    }
+    else {
+        tcp_connect(&sockfd, host, port, 0);
+    }
+    CyaSSL_set_fd(ssl, sockfd);
+#ifdef HAVE_CRL
+    if (CyaSSL_EnableCRL(ssl, CYASSL_CRL_CHECKALL) != SSL_SUCCESS)
+        err_sys("can't enable crl check");
+    if (CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, 0) != SSL_SUCCESS)
+        err_sys("can't load crl, check crlfile and date validity");
+    if (CyaSSL_SetCRL_Cb(ssl, CRL_CallBack) != SSL_SUCCESS)
+        err_sys("can't set crl callback");
+#endif
+    if (matchName && doPeerCheck)
+        CyaSSL_check_domain_name(ssl, domain);
+#ifndef CYASSL_CALLBACKS
+    if (nonBlocking) {
+        CyaSSL_set_using_nonblock(ssl, 1);
+        tcp_set_nonblocking(&sockfd);
+        NonBlockingSSL_Connect(ssl);
+    }
+    else if (CyaSSL_connect(ssl) != SSL_SUCCESS) {
+        /* see note at top of README */
+        int  err = CyaSSL_get_error(ssl, 0);
+        char buffer[80];
+        printf("err = %d, %s\n", err,
+                                CyaSSL_ERR_error_string(err, buffer));
+        err_sys("SSL_connect failed");
+        /* if you're getting an error here  */
+    }
+#else
+    timeout.tv_sec  = 2;
+    timeout.tv_usec = 0;
+    NonBlockingSSL_Connect(ssl);  /* will keep retrying on timeout */
+#endif
+    showPeer(ssl);
+
+    if (sendGET) {
+        printf("SSL connect ok, sending GET...\n");
+        msgSz = 28;
+        strncpy(msg, "GET /index.html HTTP/1.0\r\n\r\n", msgSz);
+        msg[msgSz] = '\0';
+    }
+    if (CyaSSL_write(ssl, msg, msgSz) != msgSz)
+        err_sys("SSL_write failed");
+
+    input = CyaSSL_read(ssl, reply, sizeof(reply)-1);
+    if (input > 0) {
+        reply[input] = 0;
+        printf("Server response: %s", reply);
+
+        if (sendGET && (input == (sizeof(reply)-1))) {  /* get html */
+            while (1) {
+                input = CyaSSL_read(ssl, reply, sizeof(reply)-1);
+                if (input > 0) {
+                    reply[input] = 0;
+                    printf("%s", reply);
+                    if(input < sizeof(reply)-1)
+                        break ;
+                }
+                else
+                    break;
+            }
+        }
+        printf("\n");
+    }
+    else if (input < 0) {
+        int readErr = CyaSSL_get_error(ssl, 0);
+        if (readErr != SSL_ERROR_WANT_READ)
+            err_sys("CyaSSL_read failed");
+    }
+    
+#ifdef CYASSL_CMSIS_RTOS
+    osDelay(5000) ;
+#endif
+
+#ifndef NO_SESSION_CACHE
+    if (resumeSession) {
+        if (doDTLS) {
+            strncpy(msg, "break", 6);
+            msgSz = (int)strlen(msg);
+            /* try to send session close */
+            CyaSSL_write(ssl, msg, msgSz);
+        }
+        session   = CyaSSL_get_session(ssl);
+        sslResume = CyaSSL_new(ctx);
+    }
+#endif
+
+    if (doDTLS == 0)            /* don't send alert after "break" command */
+        CyaSSL_shutdown(ssl);  /* echoserver will interpret as new conn */
+    CyaSSL_free(ssl);
+    CloseSocket(sockfd);
+
+#ifndef NO_SESSION_CACHE
+    if (resumeSession) {
+        if (doDTLS) {
+            SOCKADDR_IN_T addr;
+            #ifdef USE_WINDOWS_API 
+                Sleep(500);
+            #else
+                sleep(1);
+            #endif
+            build_addr(&addr, host, port, 1);
+            CyaSSL_dtls_set_peer(sslResume, &addr, sizeof(addr));
+            tcp_socket(&sockfd, 1);
+        }
+        else {
+            tcp_connect(&sockfd, host, port, 0);
+        }
+        CyaSSL_set_fd(sslResume, sockfd);
+        CyaSSL_set_session(sslResume, session);
+       
+        showPeer(sslResume);
+#ifndef CYASSL_CALLBACKS
+        if (nonBlocking) {
+            CyaSSL_set_using_nonblock(sslResume, 1);
+            tcp_set_nonblocking(&sockfd);
+            NonBlockingSSL_Connect(sslResume);
+        }
+        else if (CyaSSL_connect(sslResume) != SSL_SUCCESS)
+            err_sys("SSL resume failed");
+#else
+        timeout.tv_sec  = 2;
+        timeout.tv_usec = 0;
+        NonBlockingSSL_Connect(ssl);  /* will keep retrying on timeout */
+#endif
+
+        if (CyaSSL_session_reused(sslResume))
+            printf("reused session id\n");
+        else
+            printf("didn't reuse session id!!!\n");
+
+        if (CyaSSL_write(sslResume, resumeMsg, resumeSz) != resumeSz)
+            err_sys("SSL_write failed");
+
+        if (nonBlocking) {
+            /* give server a chance to bounce a message back to client */
+            #ifdef USE_WINDOWS_API
+                Sleep(500);
+            #else
+                sleep(1);
+            #endif
+        }
+
+        input = CyaSSL_read(sslResume, reply, sizeof(reply)-1);
+        if (input > 0) {
+            reply[input] = 0;
+            printf("Server resume response: %s\n", reply);
+        }
+
+        /* try to send session break */
+        CyaSSL_write(sslResume, msg, msgSz); 
+
+        CyaSSL_shutdown(sslResume);
+        CyaSSL_free(sslResume);
+        CloseSocket(sockfd);
+    }
+#endif /* NO_SESSION_CACHE */
+
+    CyaSSL_CTX_free(ctx);
+
+    ((func_args*)args)->return_code = 0;
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        ShowMemoryTracker();
+#endif /* USE_CYASSL_MEMORY */
+
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("client") || CurrentDir("build"))
+            ChangeDirBack(2);
+  
+#ifdef HAVE_STACK_SIZE
+        StackSizeCheck(&args, client_test);
+#else 
+        client_test(&args);
+#endif
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#endif /* NO_MAIN_DRIVER */
+
+
+
+#ifdef CYASSL_CALLBACKS
+
+    int handShakeCB(HandShakeInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+
+    int timeoutCB(TimeoutInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+#endif
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/main.c b/IDE/MDK5-ARM/Projects/SimpleClient/main.c
new file mode 100644
index 000000000..7eda03912
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/main.c
@@ -0,0 +1,115 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+#include "rl_net.h" 
+#include 
+#include "cyassl_MDK_ARM.h"
+#include 
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+    int32_t retv;
+
+    retv = finit ("M0:");
+    if (retv == 0) {
+        retv = fmount ("M0:");
+        if (retv == 0) {
+            printf ("Drive M0 ready!\n");
+        }
+        else {
+          printf ("Drive M0 mount failed!\n");
+        }
+    } else {
+        printf ("Drive M0 initialization failed!\n");
+    }
+}
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+void tcp_poll (void const *arg)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        net_main ();
+        osDelay(100) ;
+    }
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+} func_args;
+
+extern void client_test(func_args * args) ;
+extern void init_time(void) ;
+
+    osThreadDef (tcp_poll, osPriorityHigh , 1, 0) ;
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+int myoptind = 0;
+char* myoptarg = NULL;
+
+#include "config-SimpleClient.h"
+
+int main() 
+{
+    static char *argv[] = 
+          {   "client",   "-h", CYASSL_CALLEE_IP, "-p", CYASSL_CALLEE_PORT, 
+                                   "-v",  CYASSL_SSL_VER,  CYASSL_HTTP_GET } ;
+    static   func_args args  = 
+          {  7 + CYASSL_HTTP_GET_COUNT, argv } ; 
+        
+    init_time() ;
+    init_filesystem ();
+    net_initialize() ;
+    osThreadCreate (osThread (tcp_poll), NULL); 
+    osDelay(50000) ;  /* wait for DHCP */
+    #if defined(DEBUG_CYASSL)
+         printf("Turning ON Debug message\n") ;
+         CyaSSL_Debugging_ON() ;
+    #endif
+        
+    if(args.argc == 7)
+        printf("Simple SSL/TLS, ") ;
+    else
+        printf("HTTP GET, ") ;
+
+    printf("Callee IP: %s, Port: %s, Version:%s\n", argv[2], argv[4], argv[6]) ; 
+
+    while(1) {
+          client_test(&args) ;
+          printf("Enter any key to iterate.\n") ;
+          getchar() ;
+    }
+}
diff --git a/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx b/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx
new file mode 100644
index 000000000..fb0174c76
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleClient/simpleClient.uvprojx
@@ -0,0 +1,1106 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      SimpleClient
+      0x4
+      ARM-ADS
+      
+        
+          STM32F207IG
+          STMicroelectronics
+          IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+          0
+          $$Device:STM32F207IG$Device\Include\stm32f2xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F207IG$SVD\STM32F20x.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Object\
+          SimpleClient
+          1
+          0
+          0
+          1
+          1
+          .\Object\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          -REMAP -MPU
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          8
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            .\STM32_SWO.ini
+            BIN\ULP2CM3.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4100
+          
+          1
+          BIN\ULP2CM3.DLL
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M3"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              HAVE_CONFIG_H  MDK_CONF_SimpleClient CYASSL_STM32F2xx
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source
+          
+            
+              main.c
+              1
+              .\main.c
+            
+            
+              client.c
+              1
+              .\client.c
+            
+          
+        
+        
+          Configuration
+          
+            
+              config-SimpleClient.h
+              5
+              .\config-SimpleClient.h
+            
+            
+              config-CyaSSL.h
+              5
+              .\RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config-Crypt.h
+              5
+              .\RTE\wolfSSL\config-Crypt.h
+            
+          
+        
+        
+          Documentation
+          
+            
+              Abstract.txt
+              5
+              .\Abstract.txt
+            
+          
+        
+        
+          ::CMSIS
+          
+            
+              RTX_CM3.lib
+              4
+              C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+            
+            
+              RTX_Conf_CM.c
+              1
+              RTE\CMSIS\RTX_Conf_CM.c
+            
+          
+        
+        
+          ::Device
+          
+            
+              DMA_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c
+            
+            
+              GPIO_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+            
+            
+              RTE_Device.h
+              5
+              RTE\Device\STM32F207IG\RTE_Device.h
+            
+            
+              startup_stm32f2xx.s
+              2
+              RTE\Device\STM32F207IG\startup_stm32f2xx.s
+            
+            
+              system_stm32f2xx.c
+              1
+              RTE\Device\STM32F207IG\system_stm32f2xx.c
+            
+          
+        
+        
+          ::Drivers
+          
+            
+              PHY_ST802RT1.c
+              1
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+            
+            
+              EMAC_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c
+            
+            
+              MCI_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c
+            
+          
+        
+        
+          ::File System
+          
+            
+              FS_LFN_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib
+            
+            
+              FS_Config.c
+              1
+              RTE\File_System\FS_Config.c
+            
+            
+              FS_Config_MC_0.h
+              5
+              RTE\File_System\FS_Config_MC_0.h
+            
+          
+        
+        
+          ::Network
+          
+            
+              Net_Dbg_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib
+            
+            
+              Net_Config.c
+              1
+              RTE\Network\Net_Config.c
+            
+            
+              Net_Config_BSD.h
+              5
+              RTE\Network\Net_Config_BSD.h
+            
+            
+              Net_Config_DNS_Client.h
+              5
+              RTE\Network\Net_Config_DNS_Client.h
+            
+            
+              Net_Config_ETH_0.h
+              5
+              RTE\Network\Net_Config_ETH_0.h
+            
+            
+              Net_Config_TCP.h
+              5
+              RTE\Network\Net_Config_TCP.h
+            
+            
+              Net_Config_UDP.h
+              5
+              RTE\Network\Net_Config_UDP.h
+            
+            
+              Net_Debug.c
+              1
+              RTE\Network\Net_Debug.c
+            
+          
+        
+        
+          ::wolfSSL
+          
+            
+              cyassl_MDK_ARM.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+            
+            
+              time-STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+            
+            
+              aes.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c
+            
+            
+              arc4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c
+            
+            
+              asm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+            
+            
+              asn.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+            
+            
+              blake2b.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+            
+            
+              camellia.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c
+            
+            
+              coding.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+            
+            
+              compress.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c
+            
+            
+              des3.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
+            
+            
+              dh.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+            
+            
+              dsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+            
+            
+              ecc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+            
+            
+              ecc_fp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+            
+            
+              error.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+            
+            
+              hc128.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+            
+            
+              hmac.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+            
+            
+              integer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+            
+            
+              logging.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+            
+            
+              md2.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+            
+            
+              md4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+            
+            
+              md5.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+            
+            
+              memory.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+            
+            
+              misc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+            
+            
+              pwdbased.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+            
+            
+              rabbit.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+            
+            
+              random.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+            
+            
+              ripemd.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+            
+            
+              rsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+            
+            
+              sha.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+            
+            
+              sha256.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+            
+            
+              sha512.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+            
+            
+              tfm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+            
+            
+              crl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+            
+            
+              internal.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+            
+            
+              io.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+            
+            
+              keys.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+            
+            
+              ocsp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+            
+            
+              sniffer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+            
+            
+              ssl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+            
+            
+              tls.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+            
+            
+              config-Crypt.h
+              5
+              RTE\wolfSSL\config-Crypt.h
+            
+            
+              config-CyaSSL.h
+              5
+              RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config.h
+              5
+              RTE\wolfSSL\config.h
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        RTE\CMSIS\RTX_Conf_CM.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\RTE_Device.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\startup_stm32f2xx.s
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\system_stm32f2xx.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config_MC_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_BSD.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_DNS_Client.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_ETH_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_TCP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_UDP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Debug.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Other\config-Crypt.h
+        
+        
+        
+      
+      
+        RTE\Other\config-CyaSSL.h
+        
+        
+        
+      
+      
+        RTE\Other\config-RTX-TCP-FS.h
+        
+        
+        
+      
+      
+        RTE\Other\config.h
+        
+        
+        
+      
+      
+        RTE\wolfSSL\config-Crypt.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config-CyaSSL.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config.h
+        
+        
+        
+          
+        
+      
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt b/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt
new file mode 100644
index 000000000..ea3ec6412
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/Abstract.txt
@@ -0,0 +1,23 @@
+This program is a simple server example with CyaSSL/wolfCrypt library.
+
+In order to run this program,
+Copy {PACK}\wolfSSL\CyaSSL\2.8.0\cyassl\certs folder and files to the SD memory.
+Set the server IP address in Net_Config_ETH_0.h
+The default server listning port is 11111, defined in test.h
+
+For further configuration, refer config-Crypt.h and config-CyaSSL.h.
+
+When testing this server, it is recommended to test against one of the standard 
+CyaSSL example applications running on a desktop machine.  The standard CyaSSL 
+example applications are located in the CyaSSL root directory under the 
+/examples directory.
+
+For the hardware crypt on config-Crypt.h, download 
+STSW-STM32062: STM32F2xx standard peripherals library at 
+http://www.st.com/. Copy Libraries\STM32F2xx_StdPeriph_Driver\{inc,src} to 
+ {PACK}\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib
+
+
+Support
+-------
+Please send questions or comments to support@wolfssl.com
\ No newline at end of file
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/CMSIS/RTX_Conf_CM.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/CMSIS/RTX_Conf_CM.c
new file mode 100644
index 000000000..2298f7ddb
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/CMSIS/RTX_Conf_CM.c
@@ -0,0 +1,276 @@
+/*----------------------------------------------------------------------------
+ *      RL-ARM - RTX
+ *----------------------------------------------------------------------------
+ *      Name:    RTX_Conf_CM.C
+ *      Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
+ *      Rev.:    V4.70
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
+ * All rights reserved.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *  - Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  - Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  - Neither the name of ARM  nor the names of its contributors may be used 
+ *    to endorse or promote products derived from this software without 
+ *    specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *---------------------------------------------------------------------------*/
+
+#include "cmsis_os.h"
+
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part BEGIN
+ *---------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// Thread Configuration
+// =======================
+//
+//   Number of concurrent running threads <0-250>
+//    Defines max. number of threads that will run at the same time.
+//    Default: 6
+#ifndef OS_TASKCNT
+ #define OS_TASKCNT     5
+#endif
+
+//   Default Thread stack size [bytes] <64-4096:8><#/4>
+//    Defines default stack size for threads with osThreadDef stacksz = 0
+//    Default: 200
+#ifndef OS_STKSIZE
+ #define OS_STKSIZE     250
+#endif
+
+//   Main Thread stack size [bytes] <64-20000:8><#/4>
+//    Defines stack size for main thread.
+//    Default: 200
+#ifndef OS_MAINSTKSIZE
+ #define OS_MAINSTKSIZE 3000
+#endif
+
+//   Number of threads with user-provided stack size <0-250>
+//    Defines the number of threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVCNT
+ #define OS_PRIVCNT     0
+#endif
+
+//   Total stack size [bytes] for threads with user-provided stack size <0-0x10000:8><#/4>
+//    Defines the combined stack size for threads with user-provided stack size.
+//    Default: 0
+#ifndef OS_PRIVSTKSIZE
+ #define OS_PRIVSTKSIZE 4500
+#endif
+
+// Check for stack overflow
+//  Includes the stack checking code for stack overflow.
+//  Note that additional code reduces the Kernel performance.
+#ifndef OS_STKCHECK
+ #define OS_STKCHECK    1
+#endif
+
+// Processor mode for thread execution 
+//   <0=> Unprivileged mode 
+//   <1=> Privileged mode
+//  Default: Privileged mode
+#ifndef OS_RUNPRIV
+ #define OS_RUNPRIV     1
+#endif
+
+// 
+
+// RTX Kernel Timer Tick Configuration
+// ======================================
+//  Use Cortex-M SysTick timer as RTX Kernel Timer
+//  Use the Cortex-M SysTick timer as a time-base for RTX.
+#ifndef OS_SYSTICK
+ #define OS_SYSTICK     1
+#endif
+//
+//   Timer clock value [Hz] <1-1000000000>
+//    Defines the timer clock value.
+//    Default: 12000000  (12MHz)
+#ifndef OS_CLOCK
+ #define OS_CLOCK       12000000
+#endif
+
+//   Timer tick value [us] <1-1000000>
+//    Defines the timer tick value.
+//    Default: 1000  (1ms)
+#ifndef OS_TICK
+ #define OS_TICK        1000
+#endif
+
+// 
+
+// System Configuration
+// =======================
+//
+// Round-Robin Thread switching
+// ===============================
+//
+//  Enables Round-Robin Thread switching.
+#ifndef OS_ROBIN
+ #define OS_ROBIN       1
+#endif
+
+//   Round-Robin Timeout [ticks] <1-1000>
+//    Defines how long a thread will execute before a thread switch.
+//    Default: 5
+#ifndef OS_ROBINTOUT
+ #define OS_ROBINTOUT   5
+#endif
+
+// 
+
+// User Timers
+// ==============
+//    Enables user Timers
+#ifndef OS_TIMERS
+ #define OS_TIMERS      1
+#endif
+
+//   Timer Thread Priority
+//                        <1=> Low
+//     <2=> Below Normal  <3=> Normal  <4=> Above Normal
+//                        <5=> High
+//                        <6=> Realtime (highest)
+//    Defines priority for Timer Thread
+//    Default: High
+#ifndef OS_TIMERPRIO
+ #define OS_TIMERPRIO   5
+#endif
+
+//   Timer Thread stack size [bytes] <64-64000:8><#/4>
+//    Defines stack size for Timer thread.
+//    Default: 200
+#ifndef OS_TIMERSTKSZ
+ #define OS_TIMERSTKSZ  50
+#endif
+
+//   Timer Callback Queue size <1-32>
+//    Number of concurrent active timer callback functions.
+//    Default: 4
+#ifndef OS_TIMERCBQS
+ #define OS_TIMERCBQS   4
+#endif
+
+// 
+
+//   ISR FIFO Queue size<4=>   4 entries  <8=>   8 entries
+//                         <12=> 12 entries  <16=> 16 entries
+//                         <24=> 24 entries  <32=> 32 entries
+//                         <48=> 48 entries  <64=> 64 entries
+//                         <96=> 96 entries
+//    ISR functions store requests to this buffer,
+//    when they are called from the interrupt handler.
+//    Default: 16 entries
+#ifndef OS_FIFOSZ
+ #define OS_FIFOSZ      16
+#endif
+
+// 
+
+//------------- <<< end of configuration section >>> -----------------------
+
+// Standard library system mutexes
+// ===============================
+//  Define max. number system mutexes that are used to protect 
+//  the arm standard runtime library. For microlib they are not used.
+#ifndef OS_MUTEXCNT
+ #define OS_MUTEXCNT    8
+#endif
+
+/*----------------------------------------------------------------------------
+ *      RTX User configuration part END
+ *---------------------------------------------------------------------------*/
+
+#define OS_TRV          ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
+
+
+/*----------------------------------------------------------------------------
+ *      Global Functions
+ *---------------------------------------------------------------------------*/
+
+/*--------------------------- os_idle_demon ---------------------------------*/
+
+void os_idle_demon (void) {
+  /* The idle demon is a system thread, running when no other thread is      */
+  /* ready to run.                                                           */
+
+  for (;;) {
+    /* HERE: include optional user code to be executed when no thread runs.*/
+  }
+}
+
+#if (OS_SYSTICK == 0)   // Functions for alternative timer as RTX kernel timer
+
+/*--------------------------- os_tick_init ----------------------------------*/
+
+// Initialize alternative hardware timer as RTX kernel timer
+// Return: IRQ number of the alternative hardware timer
+int os_tick_init (void) {
+  return (-1);  /* Return IRQ number of timer (0..239) */
+}
+
+/*--------------------------- os_tick_val -----------------------------------*/
+
+// Get alternative hardware timer current value (0 .. OS_TRV)
+uint32_t os_tick_val (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_ovf -----------------------------------*/
+
+// Get alternative hardware timer overflow flag
+// Return: 1 - overflow, 0 - no overflow
+uint32_t os_tick_ovf (void) {
+  return (0);
+}
+
+/*--------------------------- os_tick_irqack --------------------------------*/
+
+// Acknowledge alternative hardware timer interrupt
+void os_tick_irqack (void) {
+  /* ... */
+}
+
+#endif   // (OS_SYSTICK == 0)
+
+/*--------------------------- os_error --------------------------------------*/
+
+void os_error (uint32_t err_code) {
+  /* This function is called when a runtime error is detected. Parameter */
+  /* 'err_code' holds the runtime error code (defined in RTL.H).         */
+
+  /* HERE: include optional code to be executed on runtime error. */
+  for (;;);
+}
+
+
+/*----------------------------------------------------------------------------
+ *      RTX Configuration Functions
+ *---------------------------------------------------------------------------*/
+
+#include "RTX_CM_lib.h"
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/RTE_Device.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/RTE_Device.h
new file mode 100644
index 000000000..4a09246f3
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/RTE_Device.h
@@ -0,0 +1,3127 @@
+/* -----------------------------------------------------------------------------
+ * Copyright (C) 2013 ARM Limited. All rights reserved.
+ *  
+ * $Date:        27. June 2013
+ * $Revision:    V1.01
+ *  
+ * Project:      RTE Device Configuration for ST STM32F2xx
+ * -------------------------------------------------------------------------- */
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+#ifndef __RTE_DEVICE_H
+#define __RTE_DEVICE_H
+
+
+#define GPIO_PORT(num) \
+ ((num == 0) ? GPIOA : \
+  (num == 1) ? GPIOB : \
+  (num == 2) ? GPIOC : \
+  (num == 3) ? GPIOD : \
+  (num == 4) ? GPIOE : \
+  (num == 5) ? GPIOF : \
+  (num == 6) ? GPIOG : \
+  (num == 7) ? GPIOH : \
+  (num == 8) ? GPIOI : \
+  NULL)
+
+
+//  Clock Configuration
+//    High-speed Internal Clock <1-999999999>
+#define RTE_HSI                         16000000
+//    High-speed External Clock <1-999999999>
+#define RTE_HSE                         25000000
+//    System Clock <1-999999999>
+#define RTE_SYSCLK                      120000000
+//    AHB Clock    <1-999999999>
+#define RTE_HCLK                        120000000
+//    APB1 Clock   <1-999999999>
+#define RTE_PCLK1                       30000000
+//    APB2 Clock   <1-999999999>
+#define RTE_PCLK2                       60000000
+//       48MHz Clock
+#define RTE_PLL48CK                     48000000
+// 
+
+
+//  USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_UART1]
+//  Configuration settings for Driver_UART1 in component ::Drivers:UART
+#define RTE_USART1                      0
+
+//    USART1_TX Pin <0=>PA9 <1=>PB6
+#define RTE_USART1_TX_ID                0
+#if    (RTE_USART1_TX_ID == 0)
+#define RTE_USART1_TX_PORT              GPIOA
+#define RTE_USART1_TX_BIT               9
+#elif  (RTE_USART1_TX_ID == 1)
+#define RTE_USART1_TX_PORT              GPIOB
+#define RTE_USART1_TX_BIT               6
+#else
+#error "Invalid USART1_TX Pin Configuration!"
+#endif
+
+//    USART1_RX Pin <0=>PA10 <1=>PB7
+#define RTE_USART1_RX_ID                0
+#if    (RTE_USART1_RX_ID == 0)
+#define RTE_USART1_RX_PORT              GPIOA
+#define RTE_USART1_RX_BIT               10
+#elif  (RTE_USART1_RX_ID == 1)
+#define RTE_USART1_RX_PORT              GPIOB
+#define RTE_USART1_RX_BIT               7
+#else
+#error "Invalid USART1_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART1_CK Pin <0=>PA8
+//     
+#define RTE_USART1_CK                   0
+#define RTE_USART1_CK_ID                0
+#if    (RTE_USART1_CK_ID == 0)
+#define RTE_USART1_CK_PORT              GPIOA
+#define RTE_USART1_CK_BIT               8
+#else
+#error "Invalid USART1_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART1_CTS Pin <0=>PA11
+//        USART1_RTS Pin <0=>PA12
+//        Manual CTS/RTS
+//     
+#define RTE_USART1_HW_FLOW              0
+#define RTE_USART1_CTS_ID               0
+#define RTE_USART1_RTS_ID               0
+#define RTE_USART1_MANUAL_FLOW          0
+#if    (RTE_USART1_CTS_ID == 0)
+#define RTE_USART1_CTS_PORT             GPIOA
+#define RTE_USART1_CTS_BIT              11
+#else
+#error "Invalid USART1_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART1_RTS_ID == 0)
+#define RTE_USART1_RTS_PORT             GPIOA
+#define RTE_USART1_RTS_BIT              12
+#else
+#error "Invalid USART1_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <2=>2 <5=>5
+//       Selects DMA Stream (only Stream 2 or 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_RX_DMA               1
+#define RTE_USART1_RX_DMA_NUMBER        2
+#define RTE_USART1_RX_DMA_STREAM        2
+#define RTE_USART1_RX_DMA_CHANNEL       4
+#define RTE_USART1_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART1_TX_DMA               1
+#define RTE_USART1_TX_DMA_NUMBER        2
+#define RTE_USART1_TX_DMA_STREAM        7
+#define RTE_USART1_TX_DMA_CHANNEL       4
+#define RTE_USART1_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_UART2]
+//  Configuration settings for Driver_UART2 in component ::Drivers:UART
+#define RTE_USART2                      0
+
+//    USART2_TX Pin <0=>PA2 <1=>PD5
+#define RTE_USART2_TX_ID                0
+#if    (RTE_USART2_TX_ID == 0)
+#define RTE_USART2_TX_PORT              GPIOA
+#define RTE_USART2_TX_BIT               2
+#elif  (RTE_USART2_TX_ID == 1)
+#define RTE_USART2_TX_PORT              GPIOD
+#define RTE_USART2_TX_BIT               5
+#else
+#error "Invalid USART2_TX Pin Configuration!"
+#endif
+
+//    USART2_RX Pin <0=>PA3 <1=>PD6
+#define RTE_USART2_RX_ID                0
+#if    (RTE_USART2_RX_ID == 0)
+#define RTE_USART2_RX_PORT              GPIOA
+#define RTE_USART2_RX_BIT               3
+#elif  (RTE_USART2_RX_ID == 1)
+#define RTE_USART2_RX_PORT              GPIOD
+#define RTE_USART2_RX_BIT               6
+#else
+#error "Invalid USART2_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART2_CK Pin <0=>PA4 <1=>PD7
+//     
+#define RTE_USART2_CK                   0
+#define RTE_USART2_CK_ID                0
+#if    (RTE_USART2_CK_ID == 0)
+#define RTE_USART2_CK_PORT              GPIOA
+#define RTE_USART2_CK_BIT               4
+#elif  (RTE_USART2_CK_ID == 1)
+#define RTE_USART2_CK_PORT              GPIOD
+#define RTE_USART2_CK_BIT               7
+#else
+#error "Invalid USART2_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART2_CTS Pin <0=>PA0 <1=>PD3
+//        USART2_RTS Pin <0=>PA1 <1=>PD4
+//        Manual CTS/RTS
+//     
+#define RTE_USART2_HW_FLOW              0
+#define RTE_USART2_CTS_ID               0
+#define RTE_USART2_RTS_ID               0
+#define RTE_USART2_MANUAL_FLOW          0
+#if    (RTE_USART2_CTS_ID == 0)
+#define RTE_USART2_CTS_PORT             GPIOA
+#define RTE_USART2_CTS_BIT              0
+#elif  (RTE_USART2_CTS_ID == 1)
+#define RTE_USART2_CTS_PORT             GPIOD
+#define RTE_USART2_CTS_BIT              3
+#else
+#error "Invalid USART2_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART2_RTS_ID == 0)
+#define RTE_USART2_RTS_PORT             GPIOA
+#define RTE_USART2_RTS_BIT              1
+#elif  (RTE_USART2_RTS_ID == 1)
+#define RTE_USART2_RTS_PORT             GPIOD
+#define RTE_USART2_RTS_BIT              4
+#else
+#error "Invalid USART2_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5
+//       Selects DMA Stream (only Stream 5 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_RX_DMA               1
+#define RTE_USART2_RX_DMA_NUMBER        1
+#define RTE_USART2_RX_DMA_STREAM        5
+#define RTE_USART2_RX_DMA_CHANNEL       4
+#define RTE_USART2_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6
+//       Selects DMA Stream (only Stream 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART2_TX_DMA               1
+#define RTE_USART2_TX_DMA_NUMBER        1
+#define RTE_USART2_TX_DMA_STREAM        6
+#define RTE_USART2_TX_DMA_CHANNEL       4
+#define RTE_USART2_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_UART3]
+//  Configuration settings for Driver_UART3 in component ::Drivers:UART
+#define RTE_USART3                      0
+
+//    USART3_TX Pin <0=>PB10 <1=>PC10 <2=>PD8
+#define RTE_USART3_TX_ID                0
+#if    (RTE_USART3_TX_ID == 0)
+#define RTE_USART3_TX_PORT              GPIOB
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 1)
+#define RTE_USART3_TX_PORT              GPIOC
+#define RTE_USART3_TX_BIT               10
+#elif  (RTE_USART3_TX_ID == 2)
+#define RTE_USART3_TX_PORT              GPIOD
+#define RTE_USART3_TX_BIT               8
+#else
+#error "Invalid USART3_TX Pin Configuration!"
+#endif
+
+//    USART3_RX Pin <0=>PB11 <1=>PC11 <2=>PD9
+#define RTE_USART3_RX_ID                0
+#if    (RTE_USART3_RX_ID == 0)
+#define RTE_USART3_RX_PORT              GPIOB
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 1)
+#define RTE_USART3_RX_PORT              GPIOC
+#define RTE_USART3_RX_BIT               11
+#elif  (RTE_USART3_RX_ID == 2)
+#define RTE_USART3_RX_PORT              GPIOD
+#define RTE_USART3_RX_BIT               9
+#else
+#error "Invalid USART3_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART3_CK Pin <0=>PB12 <1=>PC12 <2=>PD10
+//     
+#define RTE_USART3_CK                   0
+#define RTE_USART3_CK_ID                0
+#if    (RTE_USART3_CK_ID == 0)
+#define RTE_USART3_CK_PORT              GPIOB
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 1)
+#define RTE_USART3_CK_PORT              GPIOC
+#define RTE_USART3_CK_BIT               12
+#elif  (RTE_USART3_CK_ID == 2)
+#define RTE_USART3_CK_PORT              GPIOD
+#define RTE_USART3_CK_BIT               10
+#else
+#error "Invalid USART3_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART3_CTS Pin <0=>PB13 <1=>PD11
+//        USART3_RTS Pin <0=>PB14 <1=>PD12
+//        Manual CTS/RTS
+//     
+#define RTE_USART3_HW_FLOW              0
+#define RTE_USART3_CTS_ID               0
+#define RTE_USART3_RTS_ID               0
+#define RTE_USART3_MANUAL_FLOW          0
+#if    (RTE_USART3_CTS_ID == 0)
+#define RTE_USART3_CTS_PORT             GPIOB
+#define RTE_USART3_CTS_BIT              13
+#elif  (RTE_USART3_CTS_ID == 1)
+#define RTE_USART3_CTS_PORT             GPIOD
+#define RTE_USART3_CTS_BIT              11
+#else
+#error "Invalid USART3_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART3_RTS_ID == 0)
+#define RTE_USART3_RTS_PORT             GPIOB
+#define RTE_USART3_RTS_BIT              14
+#elif  (RTE_USART3_RTS_ID == 1)
+#define RTE_USART3_RTS_PORT             GPIOD
+#define RTE_USART3_RTS_BIT              12
+#else
+#error "Invalid USART3_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <1=>1
+//       Selects DMA Stream (only Stream 1 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_RX_DMA               1
+#define RTE_USART3_RX_DMA_NUMBER        1
+#define RTE_USART3_RX_DMA_STREAM        1
+#define RTE_USART3_RX_DMA_CHANNEL       4
+#define RTE_USART3_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART3_TX_DMA               1
+#define RTE_USART3_TX_DMA_NUMBER        1
+#define RTE_USART3_TX_DMA_STREAM        3
+#define RTE_USART3_TX_DMA_CHANNEL       4
+#define RTE_USART3_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  UART4 (Universal asynchronous receiver transmitter) [Driver_UART4]
+//  Configuration settings for Driver_UART4 in component ::Drivers:UART
+#define RTE_UART4                       0
+
+//    UART4_TX Pin <0=>PA0 <1=>PC10
+#define RTE_UART4_TX_ID                 0
+#if    (RTE_UART4_TX_ID == 0)
+#define RTE_UART4_TX_PORT               GPIOA
+#define RTE_UART4_TX_BIT                0
+#elif  (RTE_UART4_TX_ID == 1)
+#define RTE_UART4_TX_PORT               GPIOC
+#define RTE_UART4_TX_BIT                10
+#else
+#error "Invalid UART4_TX Pin Configuration!"
+#endif
+
+//    UART4_RX Pin <0=>PA1 <1=>PC11
+#define RTE_UART4_RX_ID                 0
+#if    (RTE_UART4_RX_ID == 0)
+#define RTE_UART4_RX_PORT               GPIOA
+#define RTE_UART4_RX_BIT                1
+#elif  (RTE_UART4_RX_ID == 1)
+#define RTE_UART4_RX_PORT               GPIOC
+#define RTE_UART4_RX_BIT                11
+#else
+#error "Invalid UART4_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_RX_DMA                1
+#define RTE_UART4_RX_DMA_NUMBER         1
+#define RTE_UART4_RX_DMA_STREAM         2
+#define RTE_UART4_RX_DMA_CHANNEL        4
+#define RTE_UART4_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART4_TX_DMA                1
+#define RTE_UART4_TX_DMA_NUMBER         1
+#define RTE_UART4_TX_DMA_STREAM         4
+#define RTE_UART4_TX_DMA_CHANNEL        4
+#define RTE_UART4_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  UART5 (Universal asynchronous receiver transmitter) [Driver_UART5]
+//  Configuration settings for Driver_UART5 in component ::Drivers:UART
+#define RTE_UART5                       0
+
+//    UART5_TX Pin <0=>PC12
+#define RTE_UART5_TX_ID                 0
+#if    (RTE_UART5_TX_ID == 0)
+#define RTE_UART5_TX_PORT               GPIOC
+#define RTE_UART5_TX_BIT                12
+#else
+#error "Invalid UART5_TX Pin Configuration!"
+#endif
+
+//    UART5_RX Pin <0=>PD2
+#define RTE_UART5_RX_ID                 0
+#if    (RTE_UART5_RX_ID == 0)
+#define RTE_UART5_RX_PORT               GPIOD
+#define RTE_UART5_RX_BIT                2
+#else
+#error "Invalid UART5_RX Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0
+//       Selects DMA Stream (only Stream 0 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_RX_DMA                1
+#define RTE_UART5_RX_DMA_NUMBER         1
+#define RTE_UART5_RX_DMA_STREAM         0
+#define RTE_UART5_RX_DMA_CHANNEL        4
+#define RTE_UART5_RX_DMA_PRIORITY       0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_UART5_TX_DMA                1
+#define RTE_UART5_TX_DMA_NUMBER         1
+#define RTE_UART5_TX_DMA_STREAM         7
+#define RTE_UART5_TX_DMA_CHANNEL        4
+#define RTE_UART5_TX_DMA_PRIORITY       0
+
+// 
+
+
+//  USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_UART6]
+//  Configuration settings for Driver_UART6 in component ::Drivers:UART
+#define RTE_USART6                      0
+
+//    USART6_TX Pin <0=>PC6 <1=>PG14
+#define RTE_USART6_TX_ID                0
+#if    (RTE_USART6_TX_ID == 0)
+#define RTE_USART6_TX_PORT              GPIOC
+#define RTE_USART6_TX_BIT               6
+#elif  (RTE_USART6_TX_ID == 1)
+#define RTE_USART6_TX_PORT              GPIOG
+#define RTE_USART6_TX_BIT               14
+#else
+#error "Invalid USART6_TX Pin Configuration!"
+#endif
+
+//    USART6_RX Pin <0=>PC7 <1=>PG9
+#define RTE_USART6_RX_ID                0
+#if    (RTE_USART6_RX_ID == 0)
+#define RTE_USART6_RX_PORT              GPIOC
+#define RTE_USART6_RX_BIT               7
+#elif  (RTE_USART6_RX_ID == 1)
+#define RTE_USART6_RX_PORT              GPIOG
+#define RTE_USART6_RX_BIT               9
+#else
+#error "Invalid USART6_RX Pin Configuration!"
+#endif
+
+//      Synchronous
+//        USART6_CK Pin <0=>PC8 <1=>PG7
+//     
+#define RTE_USART6_CK                   0
+#define RTE_USART6_CK_ID                0
+#if    (RTE_USART6_CK_ID == 0)
+#define RTE_USART6_CK_PORT              GPIOC
+#define RTE_USART6_CK_BIT               8
+#elif  (RTE_USART6_CK_ID == 1)
+#define RTE_USART6_CK_PORT              GPIOG
+#define RTE_USART6_CK_BIT               7
+#else
+#error "Invalid USART6_CK Pin Configuration!"
+#endif
+
+//      Hardware flow control
+//        USART6_CTS Pin <0=>PG13 <1=>PG15
+//        USART6_RTS Pin <0=>PG8  <1=>PG12
+//        Manual CTS/RTS
+//     
+#define RTE_USART6_HW_FLOW              0
+#define RTE_USART6_CTS_ID               0
+#define RTE_USART6_RTS_ID               0
+#define RTE_USART6_MANUAL_FLOW          0
+#if    (RTE_USART6_CTS_ID == 0)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              13
+#elif  (RTE_USART6_CTS_ID == 1)
+#define RTE_USART6_CTS_PORT             GPIOG
+#define RTE_USART6_CTS_BIT              15
+#else
+#error "Invalid USART6_CTS Pin Configuration!"
+#endif
+#if    (RTE_USART6_RTS_ID == 0)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              8
+#elif  (RTE_USART6_RTS_ID == 1)
+#define RTE_USART6_RTS_PORT             GPIOG
+#define RTE_USART6_RTS_BIT              12
+#else
+#error "Invalid USART6_RTS Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <1=>1 <2=>2
+//       Selects DMA Stream (only Stream 1 or 2 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_RX_DMA               1
+#define RTE_USART6_RX_DMA_NUMBER        2
+#define RTE_USART6_RX_DMA_STREAM        1
+#define RTE_USART6_RX_DMA_CHANNEL       5
+#define RTE_USART6_RX_DMA_PRIORITY      0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <5=>5
+//       Selects DMA Channel (only Channel 5 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_USART6_TX_DMA               1
+#define RTE_USART6_TX_DMA_NUMBER        2
+#define RTE_USART6_TX_DMA_STREAM        6
+#define RTE_USART6_TX_DMA_CHANNEL       5
+#define RTE_USART6_TX_DMA_PRIORITY      0
+
+// 
+
+
+//  I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1]
+//  Configuration settings for Driver_I2C1 in component ::Drivers:I2C
+#define RTE_I2C1                        0
+
+//    I2C1_SCL Pin <0=>PB6 <1=>PB8
+#define RTE_I2C1_SCL_PORT_ID            0
+#if    (RTE_I2C1_SCL_PORT_ID == 0)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                6
+#elif  (RTE_I2C1_SCL_PORT_ID == 1)
+#define RTE_I2C1_SCL_PORT               GPIOB
+#define RTE_I2C1_SCL_BIT                8
+#else
+#error "Invalid I2C1_SCL Pin Configuration!"
+#endif
+
+//    I2C1_SDA Pin <0=>PB7 <1=>PB9
+#define RTE_I2C1_SDA_PORT_ID            0
+#if    (RTE_I2C1_SDA_PORT_ID == 0)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                7
+#elif  (RTE_I2C1_SDA_PORT_ID == 1)
+#define RTE_I2C1_SDA_PORT               GPIOB
+#define RTE_I2C1_SDA_BIT                9
+#else
+#error "Invalid I2C1_SDA Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <5=>5
+//       Selects DMA Stream (only Stream 0 or 5 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_RX_DMA                 1
+#define RTE_I2C1_RX_DMA_NUMBER          1
+#define RTE_I2C1_RX_DMA_STREAM          0
+#define RTE_I2C1_RX_DMA_CHANNEL         1
+#define RTE_I2C1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <6=>6 <7=>7
+//       Selects DMA Stream (only Stream 6 or 7 can be used)
+//      Channel <1=>1
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C1_TX_DMA                 1
+#define RTE_I2C1_TX_DMA_NUMBER          1
+#define RTE_I2C1_TX_DMA_STREAM          6
+#define RTE_I2C1_TX_DMA_CHANNEL         1
+#define RTE_I2C1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2]
+//  Configuration settings for Driver_I2C2 in component ::Drivers:I2C
+#define RTE_I2C2                        0
+
+//    I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10
+#define RTE_I2C2_SCL_PORT_ID            0
+#if    (RTE_I2C2_SCL_PORT_ID == 0)
+#define RTE_I2C2_SCL_PORT               GPIOF
+#define RTE_I2C2_SCL_BIT                1
+#elif  (RTE_I2C2_SCL_PORT_ID == 1)
+#define RTE_I2C2_SCL_PORT               GPIOH
+#define RTE_I2C2_SCL_BIT                4
+#elif  (RTE_I2C2_SCL_PORT_ID == 2)
+#define RTE_I2C2_SCL_PORT               GPIOB
+#define RTE_I2C2_SCL_BIT                10
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11
+#define RTE_I2C2_SDA_PORT_ID            0
+#if    (RTE_I2C2_SDA_PORT_ID == 0)
+#define RTE_I2C2_SDA_PORT               GPIOF
+#define RTE_I2C2_SDA_BIT                0
+#elif  (RTE_I2C2_SDA_PORT_ID == 1)
+#define RTE_I2C2_SDA_PORT               GPIOH
+#define RTE_I2C2_SDA_BIT                5
+#elif  (RTE_I2C2_SDA_PORT_ID == 2)
+#define RTE_I2C2_SDA_PORT               GPIOB
+#define RTE_I2C2_SDA_BIT                11
+#else
+#error "Invalid I2C2_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2 <3=>3
+//       Selects DMA Stream (only Stream 2 or 3 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 7 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_RX_DMA                 1
+#define RTE_I2C2_RX_DMA_NUMBER          1
+#define RTE_I2C2_RX_DMA_STREAM          2
+#define RTE_I2C2_RX_DMA_CHANNEL         7
+#define RTE_I2C2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <7=>7
+//       Selects DMA Stream (only Stream 7 can be used)
+//      Channel <7=>7
+//       Selects DMA Channel (only Channel 1 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C2_TX_DMA                 1
+#define RTE_I2C2_TX_DMA_NUMBER          1
+#define RTE_I2C2_TX_DMA_STREAM          7
+#define RTE_I2C2_TX_DMA_CHANNEL         7
+#define RTE_I2C2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3]
+//  Configuration settings for Driver_I2C3 in component ::Drivers:I2C
+#define RTE_I2C3                        0
+
+//    I2C3_SCL Pin <0=>PH7 <1=>PA8
+#define RTE_I2C3_SCL_PORT_ID            0
+#if    (RTE_I2C3_SCL_PORT_ID == 0)
+#define RTE_I2C3_SCL_PORT               GPIOH
+#define RTE_I2C3_SCL_BIT                7
+#elif  (RTE_I2C3_SCL_PORT_ID == 1)
+#define RTE_I2C3_SCL_PORT               GPIOA
+#define RTE_I2C3_SCL_BIT                8
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    I2C3_SDA Pin <0=>PH8 <1=>PC9
+#define RTE_I2C3_SDA_PORT_ID            0
+#if    (RTE_I2C3_SDA_PORT_ID == 0)
+#define RTE_I2C3_SDA_PORT               GPIOH
+#define RTE_I2C3_SDA_BIT                8
+#elif  (RTE_I2C3_SDA_PORT_ID == 1)
+#define RTE_I2C3_SDA_PORT               GPIOC
+#define RTE_I2C3_SDA_BIT                9
+#else
+#error "Invalid I2C3_SCL Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_RX_DMA                 1
+#define RTE_I2C3_RX_DMA_NUMBER          1
+#define RTE_I2C3_RX_DMA_STREAM          2
+#define RTE_I2C3_RX_DMA_CHANNEL         3
+#define RTE_I2C3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <4=>4
+//       Selects DMA Stream (only Stream 4 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_I2C3_TX_DMA                 1
+#define RTE_I2C3_TX_DMA_NUMBER          1
+#define RTE_I2C3_TX_DMA_STREAM          4
+#define RTE_I2C3_TX_DMA_CHANNEL         3
+#define RTE_I2C3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI1 (Serial Peripheral Interface 1) [Driver_SPI1]
+//  Configuration settings for Driver_SPI1 in component ::Drivers:SPI
+#define RTE_SPI1                        0
+
+//    SPI1_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI1_NSS_PIN                1
+#define RTE_SPI1_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI1_NSS_BIT                4
+
+//    SPI1_SCK Pin <0=>PA5 <1=>PB3
+#define RTE_SPI1_SCL_PORT_ID            0
+#if    (RTE_SPI1_SCL_PORT_ID == 0)
+#define RTE_SPI1_SCL_PORT               GPIOA
+#define RTE_SPI1_SCL_BIT                5
+#elif  (RTE_SPI1_SCL_PORT_ID == 1)
+#define RTE_SPI1_SCL_PORT               GPIOB
+#define RTE_SPI1_SCL_BIT                3
+#else
+#error "Invalid SPI1_SCK Pin Configuration!"
+#endif
+
+//    SPI1_MISO Pin <0=>PA6 <1=>PB4
+#define RTE_SPI1_MISO_PORT_ID           0
+#if    (RTE_SPI1_MISO_PORT_ID == 0)
+#define RTE_SPI1_MISO_PORT              GPIOA
+#define RTE_SPI1_MISO_BIT               6
+#elif  (RTE_SPI1_MISO_PORT_ID == 1)
+#define RTE_SPI1_MISO_PORT              GPIOB
+#define RTE_SPI1_MISO_BIT               4
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    SPI1_MOSI Pin <0=>PA7 <1=>PB5
+#define RTE_SPI1_MOSI_PORT_ID           0
+#if    (RTE_SPI1_MOSI_PORT_ID == 0)
+#define RTE_SPI1_MOSI_PORT              GPIOA
+#define RTE_SPI1_MOSI_BIT               7
+#elif  (RTE_SPI1_MOSI_PORT_ID == 1)
+#define RTE_SPI1_MOSI_PORT              GPIOB
+#define RTE_SPI1_MOSI_BIT               5
+#else
+#error "Invalid SPI1_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_RX_DMA                 1
+#define RTE_SPI1_RX_DMA_NUMBER          2
+#define RTE_SPI1_RX_DMA_STREAM          0
+#define RTE_SPI1_RX_DMA_CHANNEL         3
+#define RTE_SPI1_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <5=>5
+//       Selects DMA Stream (only Stream 3 or 5 can be used)
+//      Channel <3=>3
+//       Selects DMA Channel (only Channel 3 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI1_TX_DMA                 1
+#define RTE_SPI1_TX_DMA_NUMBER          2
+#define RTE_SPI1_TX_DMA_STREAM          5
+#define RTE_SPI1_TX_DMA_CHANNEL         3
+#define RTE_SPI1_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI2 (Serial Peripheral Interface 2) [Driver_SPI2]
+//  Configuration settings for Driver_SPI2 in component ::Drivers:SPI
+#define RTE_SPI2                        0
+
+//    SPI2_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI2_NSS_PIN                1
+#define RTE_SPI2_NSS_PORT               GPIO_PORT(1)
+#define RTE_SPI2_NSS_BIT                12
+
+//    SPI2_SCK Pin <0=>PB10 <1=>PB13 <2=>PI1
+#define RTE_SPI2_SCL_PORT_ID            0
+#if    (RTE_SPI2_SCL_PORT_ID == 0)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                10
+#elif  (RTE_SPI2_SCL_PORT_ID == 1)
+#define RTE_SPI2_SCL_PORT               GPIOB
+#define RTE_SPI2_SCL_BIT                13
+#elif  (RTE_SPI2_SCL_PORT_ID == 2)
+#define RTE_SPI2_SCL_PORT               GPIOI
+#define RTE_SPI2_SCL_BIT                1
+#else
+#error "Invalid SPI2_SCK Pin Configuration!"
+#endif
+
+//    SPI2_MISO Pin <0=>PB14 <1=>PC2 <2=>PI2
+#define RTE_SPI2_MISO_PORT_ID           0
+#if    (RTE_SPI2_MISO_PORT_ID == 0)
+#define RTE_SPI2_MISO_PORT              GPIOB
+#define RTE_SPI2_MISO_BIT               14
+#elif  (RTE_SPI2_MISO_PORT_ID == 1)
+#define RTE_SPI2_MISO_PORT              GPIOC
+#define RTE_SPI2_MISO_BIT               2
+#elif  (RTE_SPI2_MISO_PORT_ID == 2)
+#define RTE_SPI2_MISO_PORT              GPIOI
+#define RTE_SPI2_MISO_BIT               2
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    SPI2_MOSI Pin <0=>PB15 <1=>PC3 <2=>OI3
+#define RTE_SPI2_MOSI_PORT_ID           0
+#if    (RTE_SPI2_MOSI_PORT_ID == 0)
+#define RTE_SPI2_MOSI_PORT              GPIOB
+#define RTE_SPI2_MOSI_BIT               15
+#elif  (RTE_SPI2_MOSI_PORT_ID == 1)
+#define RTE_SPI2_MOSI_PORT              GPIOC
+#define RTE_SPI2_MOSI_BIT               3
+#elif  (RTE_SPI2_MOSI_PORT_ID == 2)
+#define RTE_SPI2_MOSI_PORT              GPIOI
+#define RTE_SPI2_MOSI_BIT               3
+#else
+#error "Invalid SPI2_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <2=>2
+//       Selects DMA Stream (only Stream 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_RX_DMA                 1
+#define RTE_SPI2_RX_DMA_NUMBER          1
+#define RTE_SPI2_RX_DMA_STREAM          2
+#define RTE_SPI2_RX_DMA_CHANNEL         0
+#define RTE_SPI2_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <3=>3
+//       Selects DMA Stream (only Stream 3 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI2_TX_DMA                 1
+#define RTE_SPI2_TX_DMA_NUMBER          1
+#define RTE_SPI2_TX_DMA_STREAM          3
+#define RTE_SPI2_TX_DMA_CHANNEL         0
+#define RTE_SPI2_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SPI3 (Serial Peripheral Interface 3) [Driver_SPI3]
+//  Configuration settings for Driver_SPI3 in component ::Drivers:SPI
+#define RTE_SPI3                        0
+
+//    SPI3_NSS Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SPI3_NSS_PIN                1
+#define RTE_SPI3_NSS_PORT               GPIO_PORT(0)
+#define RTE_SPI3_NSS_BIT                15
+
+//    SPI3_SCK Pin <0=>PB3 <1=>PC10
+#define RTE_SPI3_SCL_PORT_ID            0
+#if    (RTE_SPI3_SCL_PORT_ID == 0)
+#define RTE_SPI3_SCL_PORT               GPIOB
+#define RTE_SPI3_SCL_BIT                3
+#elif  (RTE_SPI3_SCL_PORT_ID == 1)
+#define RTE_SPI3_SCL_PORT               GPIOC
+#define RTE_SPI3_SCL_BIT                10
+#else
+#error "Invalid SPI3_SCK Pin Configuration!"
+#endif
+
+//    SPI3_MISO Pin <0=>PB4 <1=>PC11
+#define RTE_SPI3_MISO_PORT_ID           0
+#if    (RTE_SPI3_MISO_PORT_ID == 0)
+#define RTE_SPI3_MISO_PORT              GPIOB
+#define RTE_SPI3_MISO_BIT               4
+#elif  (RTE_SPI3_MISO_PORT_ID == 1)
+#define RTE_SPI3_MISO_PORT              GPIOC
+#define RTE_SPI3_MISO_BIT               11
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    SPI3_MOSI Pin <0=>PB5 <1=>PC12
+#define RTE_SPI3_MOSI_PORT_ID           0
+#if    (RTE_SPI3_MOSI_PORT_ID == 0)
+#define RTE_SPI3_MOSI_PORT              GPIOB
+#define RTE_SPI3_MOSI_BIT               5
+#elif  (RTE_SPI3_MOSI_PORT_ID == 1)
+#define RTE_SPI3_MOSI_PORT              GPIOC
+#define RTE_SPI3_MOSI_BIT               12
+#else
+#error "Invalid SPI3_MISO Pin Configuration!"
+#endif
+
+//    DMA Rx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <0=>0 <2=>2
+//       Selects DMA Stream (only Stream 0 or 2 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_RX_DMA                 1
+#define RTE_SPI3_RX_DMA_NUMBER          1
+#define RTE_SPI3_RX_DMA_STREAM          0
+#define RTE_SPI3_RX_DMA_CHANNEL         0
+#define RTE_SPI3_RX_DMA_PRIORITY        0
+
+//    DMA Tx
+//      Number <1=>1
+//       Selects DMA Number (only DMA1 can be used)
+//      Stream <5=>5 <7=>7
+//       Selects DMA Stream (only Stream 5 or 7 can be used)
+//      Channel <0=>0
+//       Selects DMA Channel (only Channel 0 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SPI3_TX_DMA                 1
+#define RTE_SPI3_TX_DMA_NUMBER          1
+#define RTE_SPI3_TX_DMA_STREAM          5
+#define RTE_SPI3_TX_DMA_CHANNEL         0
+#define RTE_SPI3_TX_DMA_PRIORITY        0
+
+// 
+
+
+//  SDIO (Secure Digital Input/Output) [Driver_MCI0]
+//  Configuration settings for Driver_MCI0 in component ::Drivers:MCI
+#define RTE_SDIO                        1
+
+//    SDIO_CD (Card Detect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_CD_PIN                 1
+#define RTE_SDIO_CD_ACTIVE              0
+#define RTE_SDIO_CD_PORT                GPIO_PORT(7)
+#define RTE_SDIO_CD_BIT                 15
+
+//    SDIO_WP (Write Protect) Pin
+//    Configure Pin if exists
+//    GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//      Active State <0=>Low <1=>High
+//       Selects Active State Logical Level
+//      Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//               <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//       Selects Port Name
+//      Bit <0-15>
+//       Selects Port Bit
+//   
+#define RTE_SDIO_WP_PIN                 0
+#define RTE_SDIO_WP_ACTIVE              0
+#define RTE_SDIO_WP_PORT                GPIO_PORT(7)
+#define RTE_SDIO_WP_BIT                 16
+
+//    SDIO Bus
+//      SDIO_CK Pin <0=>PC12
+#define RTE_SDIO_CK_PORT_ID             0
+#if    (RTE_SDIO_CK_PORT_ID == 0)
+#define RTE_SDIO_CK_PORT                GPIOC
+#define RTE_SDIO_CK_PIN                 12
+#else
+#error "Invalid SDIO_CK Pin Configuration!"
+#endif
+//      SDIO_CMD Pin <0=>PD2
+#define RTE_SDIO_CMD_PORT_ID            0
+#if    (RTE_SDIO_CMD_PORT_ID == 0)
+#define RTE_SDIO_CMD_PORT               GPIOD
+#define RTE_SDIO_CMD_PIN                2
+#else
+#error "Invalid SDIO_CDM Pin Configuration!"
+#endif
+//      SDIO_D0 Pin <0=>PC8
+#define RTE_SDIO_D0_PORT_ID             0
+#if    (RTE_SDIO_D0_PORT_ID == 0)
+#define RTE_SDIO_D0_PORT                GPIOC
+#define RTE_SDIO_D0_PIN                 8
+#else
+#error "Invalid SDIO_D0 Pin Configuration!"
+#endif
+//      SDIO_D1 Pin <0=>PC9
+#define RTE_SDIO_D1_PORT_ID             0
+#if    (RTE_SDIO_D1_PORT_ID == 0)
+#define RTE_SDIO_D1_PORT                GPIOC
+#define RTE_SDIO_D1_PIN                 9
+#else
+#error "Invalid SDIO_D1 Pin Configuration!"
+#endif
+//      SDIO_D2 Pin <0=>PC10
+#define RTE_SDIO_D2_PORT_ID             0
+#if    (RTE_SDIO_D2_PORT_ID == 0)
+#define RTE_SDIO_D2_PORT                GPIOC
+#define RTE_SDIO_D2_PIN                 10
+#else
+#error "Invalid SDIO_D2 Pin Configuration!"
+#endif
+//      SDIO_D3 Pin <0=>PC11
+#define RTE_SDIO_D3_PORT_ID             0
+#if    (RTE_SDIO_D3_PORT_ID == 0)
+#define RTE_SDIO_D3_PORT                GPIOC
+#define RTE_SDIO_D3_PIN                 11
+#else
+#error "Invalid SDIO_D3 Pin Configuration!"
+#endif
+//      SDIO_D4 Pin <0=>PB8
+#define RTE_SDIO_D4_PORT_ID             0
+#if    (RTE_SDIO_D4_PORT_ID == 0)
+#define RTE_SDIO_D4_PORT                GPIOB
+#define RTE_SDIO_D4_PIN                 8
+#else
+#error "Invalid SDIO_D4 Pin Configuration!"
+#endif
+//      SDIO_D5 Pin <0=>PB9
+#define RTE_SDIO_D5_PORT_ID             0
+#if    (RTE_SDIO_D5_PORT_ID == 0)
+#define RTE_SDIO_D5_PORT                GPIOB
+#define RTE_SDIO_D5_PIN                 9
+#else
+#error "Invalid SDIO_D5 Pin Configuration!"
+#endif
+//      SDIO_D6 Pin <0=>PC6
+#define RTE_SDIO_D6_PORT_ID             0
+#if    (RTE_SDIO_D6_PORT_ID == 0)
+#define RTE_SDIO_D6_PORT                GPIOC
+#define RTE_SDIO_D6_PIN                 6
+#else
+#error "Invalid SDIO_D6 Pin Configuration!"
+#endif
+//      SDIO_D7 Pin <0=>PC7
+#define RTE_SDIO_D7_PORT_ID             0
+#if    (RTE_SDIO_D7_PORT_ID == 0)
+#define RTE_SDIO_D7_PORT                GPIOC
+#define RTE_SDIO_D7_PIN                 7
+#else
+#error "Invalid SDIO_D7 Pin Configuration!"
+#endif
+//   
+
+//    DMA
+//      Number <2=>2
+//       Selects DMA Number (only DMA2 can be used)
+//      Stream <3=>3 <6=>6
+//       Selects DMA Stream (only Stream 3 or 6 can be used)
+//      Channel <4=>4
+//       Selects DMA Channel (only Channel 4 can be used)
+//      Priority <0=>Low <1=>Medium <2=>High <3=>Very High
+//       Selects DMA Priority
+//   
+#define RTE_SDIO_DMA                    1
+#define RTE_SDIO_DMA_NUMBER             2
+#define RTE_SDIO_DMA_STREAM             3
+#define RTE_SDIO_DMA_CHANNEL            4
+#define RTE_SDIO_DMA_PRIORITY           0
+
+// 
+
+
+//  ETH (Ethernet Interface) [Driver_ETH_MAC0]
+//  Configuration settings for Driver_ETH_MAC0 in component ::Drivers:Ethernet MAC
+#define RTE_ETH                         1
+
+//    MII (Media Independent Interface)
+#define RTE_ETH_MII                     0
+
+//      ETH_MII_TX_CLK Pin <0=>PC3
+#define RTE_ETH_MII_TX_CLK_PORT_ID      0
+#if    (RTE_ETH_MII_TX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_TX_CLK_PORT         GPIOC
+#define RTE_ETH_MII_TX_CLK_PIN          3
+#else
+#error "Invalid ETH_MII_TX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_MII_TXD0_PORT_ID        0
+#if    (RTE_ETH_MII_TXD0_PORT_ID == 0)
+#define RTE_ETH_MII_TXD0_PORT           GPIOB
+#define RTE_ETH_MII_TXD0_PIN            12
+#elif  (RTE_ETH_MII_TXD0_PORT_ID == 1)
+#define RTE_ETH_MII_TXD0_PORT           GPIOG
+#define RTE_ETH_MII_TXD0_PIN            13
+#else
+#error "Invalid ETH_MII_TXD0 Pin Configuration!"
+#endif
+//      ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_MII_TXD1_PORT_ID        0
+#if    (RTE_ETH_MII_TXD1_PORT_ID == 0)
+#define RTE_ETH_MII_TXD1_PORT           GPIOB
+#define RTE_ETH_MII_TXD1_PIN            13
+#elif  (RTE_ETH_MII_TXD1_PORT_ID == 1)
+#define RTE_ETH_MII_TXD1_PORT           GPIOG
+#define RTE_ETH_MII_TXD1_PIN            14
+#else
+#error "Invalid ETH_MII_TXD1 Pin Configuration!"
+#endif
+//      ETH_MII_TXD2 Pin <0=>PC2
+#define RTE_ETH_MII_TXD2_PORT_ID        0
+#if    (RTE_ETH_MII_TXD2_PORT_ID == 0)
+#define RTE_ETH_MII_TXD2_PORT           GPIOC
+#define RTE_ETH_MII_TXD2_PIN            2
+#else
+#error "Invalid ETH_MII_TXD2 Pin Configuration!"
+#endif
+//      ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2
+#define RTE_ETH_MII_TXD3_PORT_ID        0
+#if    (RTE_ETH_MII_TXD3_PORT_ID == 0)
+#define RTE_ETH_MII_TXD3_PORT           GPIOB
+#define RTE_ETH_MII_TXD3_PIN            8
+#elif  (RTE_ETH_MII_TXD3_PORT_ID == 1)
+#define RTE_ETH_MII_TXD3_PORT           GPIOE
+#define RTE_ETH_MII_TXD3_PIN            2
+#else
+#error "Invalid ETH_MII_TXD3 Pin Configuration!"
+#endif
+//      ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_MII_TX_EN_PORT_ID       0
+#if    (RTE_ETH_MII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOB
+#define RTE_ETH_MII_TX_EN_PIN           11
+#elif  (RTE_ETH_MII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_MII_TX_EN_PORT          GPIOG
+#define RTE_ETH_MII_TX_EN_PIN           11
+#else
+#error "Invalid ETH_MII_TX_EN Pin Configuration!"
+#endif
+//      ETH_MII_RX_CLK Pin <0=>PA1
+#define RTE_ETH_MII_RX_CLK_PORT_ID        0
+#if    (RTE_ETH_MII_RX_CLK_PORT_ID == 0)
+#define RTE_ETH_MII_RX_CLK_PORT         GPIOA
+#define RTE_ETH_MII_RX_CLK_PIN          1
+#else
+#error "Invalid ETH_MII_RX_CLK Pin Configuration!"
+#endif
+//      ETH_MII_RXD0 Pin <0=>PC4
+#define RTE_ETH_MII_RXD0_PORT_ID        0
+#if    (RTE_ETH_MII_RXD0_PORT_ID == 0)
+#define RTE_ETH_MII_RXD0_PORT           GPIOC
+#define RTE_ETH_MII_RXD0_PIN            4
+#else
+#error "Invalid ETH_MII_RXD0 Pin Configuration!"
+#endif
+//      ETH_MII_RXD1 Pin <0=>PC5
+#define RTE_ETH_MII_RXD1_PORT_ID        0
+#if    (RTE_ETH_MII_RXD1_PORT_ID == 0)
+#define RTE_ETH_MII_RXD1_PORT           GPIOC
+#define RTE_ETH_MII_RXD1_PIN            5
+#else
+#error "Invalid ETH_MII_RXD1 Pin Configuration!"
+#endif
+//      ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6
+#define RTE_ETH_MII_RXD2_PORT_ID        0
+#if    (RTE_ETH_MII_RXD2_PORT_ID == 0)
+#define RTE_ETH_MII_RXD2_PORT           GPIOB
+#define RTE_ETH_MII_RXD2_PIN            0
+#elif  (RTE_ETH_MII_RXD2_PORT_ID == 1)
+#define RTE_ETH_MII_RXD2_PORT           GPIOH
+#define RTE_ETH_MII_RXD2_PIN            6
+#else
+#error "Invalid ETH_MII_RXD2 Pin Configuration!"
+#endif
+//      ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7
+#define RTE_ETH_MII_RXD3_PORT_ID        0
+#if    (RTE_ETH_MII_RXD3_PORT_ID == 0)
+#define RTE_ETH_MII_RXD3_PORT           GPIOB
+#define RTE_ETH_MII_RXD3_PIN            1
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RXD3_PORT           GPIOH
+#define RTE_ETH_MII_RXD3_PIN            7
+#else
+#error "Invalid ETH_MII_RXD3 Pin Configuration!"
+#endif
+//      ETH_MII_RX_DV Pin <0=>PA7
+#define RTE_ETH_MII_RX_DV_PORT_ID       0
+#if    (RTE_ETH_MII_RX_DV_PORT_ID == 0)
+#define RTE_ETH_MII_RX_DV_PORT          GPIOA
+#define RTE_ETH_MII_RX_DV_PIN           7
+#else
+#error "Invalid ETH_MII_RX_DV Pin Configuration!"
+#endif
+//      ETH_MII_RX_ER Pin <0=>PB10 <1=>PI10
+#define RTE_ETH_MII_RX_ER_PORT_ID       0
+#if    (RTE_ETH_MII_RX_ER_PORT_ID == 0)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOB
+#define RTE_ETH_MII_RX_ER_PIN           10
+#elif  (RTE_ETH_MII_RXD3_PORT_ID == 1)
+#define RTE_ETH_MII_RX_ER_PORT          GPIOI
+#define RTE_ETH_MII_RX_ER_PIN           10
+#else
+#error "Invalid ETH_MII_RX_ER Pin Configuration!"
+#endif
+//      ETH_MII_CRS Pin <0=>PA0 <1=>PH2
+#define RTE_ETH_MII_CRS_PORT_ID       0
+#if    (RTE_ETH_MII_CRS_PORT_ID == 0)
+#define RTE_ETH_MII_CRS_PORT            GPIOA
+#define RTE_ETH_MII_CRS_PIN             0
+#elif  (RTE_ETH_MII_CRS_PORT_ID == 1)
+#define RTE_ETH_MII_CRS_PORT            GPIOH
+#define RTE_ETH_MII_CRS_PIN             2
+#else
+#error "Invalid ETH_MII_CRS Pin Configuration!"
+#endif
+//      ETH_MII_COL Pin <0=>PA3 <1=>PH3
+#define RTE_ETH_MII_COL_PORT_ID       0
+#if    (RTE_ETH_MII_COL_PORT_ID == 0)
+#define RTE_ETH_MII_COL_PORT            GPIOA
+#define RTE_ETH_MII_COL_PIN             3
+#elif  (RTE_ETH_MII_COL_PORT_ID == 1)
+#define RTE_ETH_MII_COL_PORT            GPIOH
+#define RTE_ETH_MII_COL_PIN             3
+#else
+#error "Invalid ETH_MII_COL Pin Configuration!"
+#endif
+
+//   
+
+//    RMII (Reduced Media Independent Interface)
+#define RTE_ETH_RMII                    1
+
+//      ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13
+#define RTE_ETH_RMII_TXD0_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOB
+#define RTE_ETH_RMII_TXD0_PIN           12
+#elif  (RTE_ETH_RMII_TXD0_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD0_PORT          GPIOG
+#define RTE_ETH_RMII_TXD0_PIN           13
+#else
+#error "Invalid ETH_RMII_TXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14
+#define RTE_ETH_RMII_TXD1_PORT_ID       1
+#if    (RTE_ETH_RMII_TXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOB
+#define RTE_ETH_RMII_TXD1_PIN           13
+#elif  (RTE_ETH_RMII_TXD1_PORT_ID == 1)
+#define RTE_ETH_RMII_TXD1_PORT          GPIOG
+#define RTE_ETH_RMII_TXD1_PIN           14
+#else
+#error "Invalid ETH_RMII_TXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11
+#define RTE_ETH_RMII_TX_EN_PORT_ID      1
+#if    (RTE_ETH_RMII_TX_EN_PORT_ID == 0)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOB
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#elif  (RTE_ETH_RMII_TX_EN_PORT_ID == 1)
+#define RTE_ETH_RMII_TX_EN_PORT         GPIOG
+#define RTE_ETH_RMII_TX_EN_PIN          11
+#else
+#error "Invalid ETH_RMII_TX_EN Pin Configuration!"
+#endif
+//      ETH_RMII_RXD0 Pin <0=>PC4
+#define RTE_ETH_RMII_RXD0_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD0_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD0_PORT          GPIOC
+#define RTE_ETH_RMII_RXD0_PIN           4
+#else
+#error "Invalid ETH_RMII_RXD0 Pin Configuration!"
+#endif
+//      ETH_RMII_RXD1 Pin <0=>PC5
+#define RTE_ETH_RMII_RXD1_PORT_ID       0
+#if    (RTE_ETH_RMII_RXD1_PORT_ID == 0)
+#define RTE_ETH_RMII_RXD1_PORT          GPIOC
+#define RTE_ETH_RMII_RXD1_PIN           5
+#else
+#error "Invalid ETH_RMII_RXD1 Pin Configuration!"
+#endif
+//      ETH_RMII_REF_CLK Pin <0=>PA1
+#define RTE_ETH_RMII_REF_CLK_PORT_ID    0
+#if    (RTE_ETH_RMII_REF_CLK_PORT_ID == 0)
+#define RTE_ETH_RMII_REF_CLK_PORT       GPIOA
+#define RTE_ETH_RMII_REF_CLK_PIN        1
+#else
+#error "Invalid ETH_RMII_REF_CLK Pin Configuration!"
+#endif
+//      ETH_RMII_CRS_DV Pin <0=>PA7
+#define RTE_ETH_RMII_CRS_DV_PORT_ID     0
+#if    (RTE_ETH_RMII_CRS_DV_PORT_ID == 0)
+#define RTE_ETH_RMII_CRS_DV_PORT        GPIOA
+#define RTE_ETH_RMII_CRS_DV_PIN         7
+#else
+#error "Invalid ETH_RMII_CRS_DV Pin Configuration!"
+#endif
+
+//   
+
+//    Management Data Interface
+//      ETH_MDC Pin <0=>PC1
+#define RTE_ETH_MDI_MDC_PORT_ID         0
+#if    (RTE_ETH_MDI_MDC_PORT_ID == 0)
+#define RTE_ETH_MDI_MDC_PORT            GPIOC
+#define RTE_ETH_MDI_MDC_PIN             1
+#else
+#error "Invalid ETH_MDC Pin Configuration!"
+#endif
+//      ETH_MDIO Pin <0=>PA2
+#define RTE_ETH_MDI_MDIO_PORT_ID        0
+#if    (RTE_ETH_MDI_MDIO_PORT_ID == 0)
+#define RTE_ETH_MDI_MDIO_PORT           GPIOA
+#define RTE_ETH_MDI_MDIO_PIN            2
+#else
+#error "Invalid ETH_MDIO Pin Configuration!"
+#endif
+//   
+
+//    Reference 25MHz/50MHz Clock generation
+#define RTE_ETH_REF_CLOCK               0
+
+//      MCO Pin <0=>PA2 <1=>PC9
+#define RTE_ETH_REF_CLOCK_PORT_ID       0
+#if    (RTE_ETH_REF_CLOCK_PORT_ID == 0)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOA
+#define RTE_ETH_REF_CLOCK_PIN           8
+#elif  (RTE_ETH_REF_CLOCK_PORT_ID == 1)
+#define RTE_ETH_REF_CLOCK_PORT          GPIOC
+#define RTE_ETH_REF_CLOCK_PIN           9
+#else
+#error "Invalid MCO Pin Configuration!"
+#endif
+
+//   
+
+// 
+
+
+//  USB OTG Full-speed
+#define RTE_USB_OTG_FS                  0
+
+//    Device [Driver_USBD0]
+//    Configuration settings for Driver_USBD0 in component ::Drivers:USB Device
+#define RTE_USB_OTG_FS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_FS_DEV_EP           0x0000000F
+#define RTE_USB_OTG_FS_DEV_EP_BULK      0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_INT       0x000E000E
+#define RTE_USB_OTG_FS_DEV_EP_ISO       0x000E000E
+
+//   
+
+//    Host [Driver_USBH0]
+//    Configuration settings for Driver_USBH0 in component ::Drivers:USB Host
+
+#define RTE_USB_OTG_FS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_VBUS_PIN             1
+#define RTE_OTG_FS_VBUS_ACTIVE          0
+#define RTE_OTG_FS_VBUS_PORT            GPIO_PORT(7)
+#define RTE_OTG_FS_VBUS_BIT             5
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_FS_OC_PIN               1
+#define RTE_OTG_FS_OC_ACTIVE            0
+#define RTE_OTG_FS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_FS_OC_BIT               11
+//   
+
+// 
+
+
+//  USB OTG High-speed
+#define RTE_USB_OTG_HS                  0
+
+//    PHY (Physical Layer)
+
+//      PHY Interface
+//       <0=>On-chip full-speed PHY
+//       <1=>External ULPI high-speed PHY
+#define RTE_USB_OTG_HS_PHY              1
+
+//      External ULPI Pins (UTMI+ Low Pin Interface)
+
+//        OTG_HS_ULPI_CK Pin <0=>PA5
+#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_CK_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_CK_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_CK Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOI
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     11
+#elif  (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_DIR_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_DIR_PIN     2
+#else
+#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_STP Pin <0=>PC0
+#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0
+#if    (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_STP_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_STP_PIN     0
+#else
+#error "Invalid OTG_HS_ULPI_STP Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_NXT Pin <0=>PC2 <1=>PH4
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1
+#if    (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOC
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     2
+#elif  (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1)
+#define RTE_USB_OTG_HS_ULPI_NXT_PORT    GPIOH
+#define RTE_USB_OTG_HS_ULPI_NXT_PIN     4
+#else
+#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D0 Pin <0=>PA3
+#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D0_PORT     GPIOA
+#define RTE_USB_OTG_HS_ULPI_D0_PIN      3
+#else
+#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D1 Pin <0=>PB0
+#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D1_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D1_PIN      0
+#else
+#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D2 Pin <0=>PB1
+#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D2_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D2_PIN      1
+#else
+#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D3 Pin <0=>PB10
+#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D3_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D3_PIN      10
+#else
+#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D4 Pin <0=>PB11
+#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D4_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D4_PIN      11
+#else
+#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D5 Pin <0=>PB12
+#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D5_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D5_PIN      12
+#else
+#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D6 Pin <0=>PB13
+#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D6_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D6_PIN      13
+#else
+#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!"
+#endif
+//        OTG_HS_ULPI_D7 Pin <0=>PB5
+#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID  0
+#if    (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0)
+#define RTE_USB_OTG_HS_ULPI_D7_PORT     GPIOB
+#define RTE_USB_OTG_HS_ULPI_D7_PIN      5
+#else
+#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!"
+#endif
+
+//     
+
+//   
+
+//    Device [Driver_USBD1]
+//    Configuration settings for Driver_USBD1 in component ::Drivers:USB Device
+#define RTE_USB_OTG_HS_DEV              1
+
+//      Endpoints
+//      Reduce memory requirements of Driver by disabling unused endpoints
+//        Endpoint 1
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 2
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 3
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 4
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//        Endpoint 5
+//           Bulk OUT
+//          Bulk IN
+//           Interrupt OUT
+//          Interrupt IN
+//           Isochronous OUT
+//          Isochronous IN
+//       
+//     
+#define RTE_USB_OTG_HS_DEV_EP           0x0000003F
+#define RTE_USB_OTG_HS_DEV_EP_BULK      0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_INT       0x003E003E
+#define RTE_USB_OTG_HS_DEV_EP_ISO       0x003E003E
+
+//   
+
+//    Host [Driver_USBH1]
+//    Configuration settings for Driver_USBH1 in component ::Drivers:USB Host
+#define RTE_USB_OTG_HS_HOST             1
+
+//      VBUS Power On/Off Pin
+//      Configure Pin for driving VBUS
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_VBUS_PIN             1
+#define RTE_OTG_HS_VBUS_ACTIVE          0
+#define RTE_OTG_HS_VBUS_PORT            GPIO_PORT(2)
+#define RTE_OTG_HS_VBUS_BIT             2
+
+//      Overcurrent Detection Pin
+//      Configure Pin for overcurrent detection
+//      GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11)
+//        Active State <0=>Low <1=>High
+//         Selects Active State Logical Level
+//        Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD
+//                 <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI
+//         Selects Port Name
+//        Bit <0-15>
+//         Selects Port Bit
+//     
+#define RTE_OTG_HS_OC_PIN               1
+#define RTE_OTG_HS_OC_ACTIVE            0
+#define RTE_OTG_HS_OC_PORT              GPIO_PORT(5)
+#define RTE_OTG_HS_OC_BIT               12
+//   
+
+// 
+
+
+//  EXTI (External Interrupt/Event Controller)
+#define RTE_EXTI                        0
+
+//    EXTI0 Line
+#define RTE_EXTI0                       0
+//      Pin   <0=>PA0  <1=>PB0  <2=>PC0  <3=>PD0  <4=>PE0  <5=>PF0  <6=>PG0  <7=>PH0  <8=>PI0
+#define RTE_EXTI0_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI0_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI0_TRIGGER               0
+//   
+
+//    EXTI1 Line
+#define RTE_EXTI1                       0
+//      Pin   <0=>PA1  <1=>PB1  <2=>PC1  <3=>PD1  <4=>PE1  <5=>PF1  <6=>PG1  <7=>PH1  <8=>PI1
+#define RTE_EXTI1_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI1_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI1_TRIGGER               0
+//   
+
+//    EXTI2 Line
+#define RTE_EXTI2                       0
+//      Pin   <0=>PA2  <1=>PB2  <2=>PC2  <3=>PD2  <4=>PE2  <5=>PF2  <6=>PG2  <7=>PH2  <8=>PI2
+#define RTE_EXTI2_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI2_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI2_TRIGGER               0
+//   
+
+//    EXTI3 Line
+#define RTE_EXTI3                       0
+//      Pin   <0=>PA3  <1=>PB3  <2=>PC3  <3=>PD3  <4=>PE3  <5=>PF3  <6=>PG3  <7=>PH3  <8=>PI3
+#define RTE_EXTI3_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI3_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI3_TRIGGER               0
+//   
+
+//    EXTI4 Line
+#define RTE_EXTI4                       0
+//      Pin   <0=>PA4  <1=>PB4  <2=>PC4  <3=>PD4  <4=>PE4  <5=>PF4  <6=>PG4  <7=>PH4  <8=>PI4
+#define RTE_EXTI4_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI4_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI4_TRIGGER               0
+//   
+
+//    EXTI5 Line
+#define RTE_EXTI5                       0
+//      Pin   <0=>PA5  <1=>PB5  <2=>PC5  <3=>PD5  <4=>PE5  <5=>PF5  <6=>PG5  <7=>PH5  <8=>PI5
+#define RTE_EXTI5_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI5_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI5_TRIGGER               0
+//   
+
+//    EXTI6 Line
+#define RTE_EXTI6                       0
+//      Pin   <0=>PA6  <1=>PB6  <2=>PC6  <3=>PD6  <4=>PE6  <5=>PF6  <6=>PG6  <7=>PH6  <8=>PI6
+#define RTE_EXTI6_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI6_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI6_TRIGGER               0
+//   
+
+//    EXTI7 Line
+#define RTE_EXTI7                       0
+//      Pin   <0=>PA7  <1=>PB7  <2=>PC7  <3=>PD7  <4=>PE7  <5=>PF7  <6=>PG7  <7=>PH7  <8=>PI7
+#define RTE_EXTI7_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI7_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI7_TRIGGER               0
+//   
+
+//    EXTI8 Line
+#define RTE_EXTI8                       0
+//      Pin   <0=>PA8  <1=>PB8  <2=>PC8  <3=>PD8  <4=>PE8  <5=>PF8  <6=>PG8  <7=>PH8  <8=>PI8
+#define RTE_EXTI8_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI8_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI8_TRIGGER               0
+//   
+
+//    EXTI9 Line
+#define RTE_EXTI9                       0
+//      Pin   <0=>PA9  <1=>PB9  <2=>PC9  <3=>PD9  <4=>PE9  <5=>PF9  <6=>PG9  <7=>PH9  <8=>PI9
+#define RTE_EXTI9_PIN                   0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI9_MODE                  0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI9_TRIGGER               0
+//   
+
+//    EXTI10 Line
+#define RTE_EXTI10                      0
+//      Pin   <0=>PA10 <1=>PB10 <2=>PC10 <3=>PD10 <4=>PE10 <5=>PF10 <6=>PG10 <7=>PH10 <8=>PI10
+#define RTE_EXTI10_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI10_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI10_TRIGGER              0
+//   
+
+//    EXTI11 Line
+#define RTE_EXTI11                      0
+//      Pin   <0=>PA11 <1=>PB11 <2=>PC11 <3=>PD11 <4=>PE11 <5=>PF11 <6=>PG11 <7=>PH11 <8=>PI11
+#define RTE_EXTI11_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI11_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI11_TRIGGER              0
+//   
+
+//    EXTI12 Line
+#define RTE_EXTI12                      0
+//      Pin   <0=>PA12 <1=>PB12 <2=>PC12 <3=>PD12 <4=>PE12 <5=>PF12 <6=>PG12 <7=>PH12
+#define RTE_EXTI12_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI12_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI12_TRIGGER              0
+//   
+
+//    EXTI13 Line
+#define RTE_EXTI13                      0
+//      Pin   <0=>PA13 <1=>PB13 <2=>PC13 <3=>PD13 <4=>PE13 <5=>PF13 <6=>PG13 <7=>PH13
+#define RTE_EXTI13_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI13_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI13_TRIGGER              0
+//   
+
+//    EXTI14 Line
+#define RTE_EXTI14                      0
+//      Pin   <0=>PA14 <1=>PB14 <2=>PC14 <3=>PD14 <4=>PE14 <5=>PF14 <6=>PG14 <7=>PH14
+#define RTE_EXTI14_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI14_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI14_TRIGGER              0
+//   
+
+//    EXTI15 Line
+#define RTE_EXTI15                      0
+//      Pin   <0=>PA15 <1=>PB15 <2=>PC15 <3=>PD15 <4=>PE15 <5=>PF15 <6=>PG15 <7=>PH15
+#define RTE_EXTI15_PIN                  0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI15_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI15_TRIGGER              0
+//   
+
+//    EXTI16 Line: PVD Output
+#define RTE_EXTI16                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI16_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI16_TRIGGER              0
+//   
+
+//    EXTI17 Line: RTC Alarm
+#define RTE_EXTI17                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI17_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI17_TRIGGER              0
+//   
+
+//    EXTI18 Line: USB OTG FS Wakeup
+#define RTE_EXTI18                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI18_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI18_TRIGGER              0
+//   
+
+//    EXTI19 Line: Ethernet Wakeup
+#define RTE_EXTI19                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI19_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI19_TRIGGER              0
+//   
+
+//    EXTI20 Line: USB OTG HS Wakeup
+#define RTE_EXTI20                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI20_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI20_TRIGGER              0
+//   
+
+//    EXTI21 Line: RTC Tamper and TimeStamp
+#define RTE_EXTI21                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI21_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI21_TRIGGER              0
+//   
+
+//    EXTI22 Line: RTC Wakeup
+#define RTE_EXTI22                      0
+//      Mode  <0=>Interrupt  <1=>Event
+#define RTE_EXTI22_MODE                 0
+//      Trigger  <0=>None  <1=>Raising edge <2=>Falling edge <3=>Any edge
+#define RTE_EXTI22_TRIGGER              0
+//   
+
+// 
+
+
+//  FSMC (Flexible Static Memory Controller)
+#define RTE_FSMC                        0
+
+//    Pin Configuration
+//    Configure Pins
+#define RTE_FSMC_PINS                   0
+
+//      Address Bus Pins
+//       <0=>A[17:16]
+//       <1=>A[10:0]   <2=>A[15:0]   <3=>A[16:0]   <4=>A[17:0]
+//       <5=>A[18:0]   <6=>A[19:0]   <7=>A[20:0]   <8=>A[21:0]
+//       <9=>A[22:0]  <10=>A[23:0]  <11=>A[24:0]  <12=>A[25:0]
+#define RTE_FSMC_ABUS_PINS              10
+//      Data Bus Pins  <0=>D[7:0] <1=>D[15:0]
+#define RTE_FSMC_DBUS_PINS              0
+//      FSMC_NOE Pin
+#define RTE_FSMC_NOE_PIN                0
+//      FSMC_NWE Pin
+#define RTE_FSMC_NWE_PIN                0
+//      FSMC_NBL0 Pin
+#define RTE_FSMC_NBL0_PIN               0
+//      FSMC_NBL1 Pin
+#define RTE_FSMC_NBL1_PIN               0
+//      FSMC_NL Pin
+#define RTE_FSMC_NL_PIN                 0
+//      FSMC_NWAIT Pin
+#define RTE_FSMC_NWAIT_PIN              0
+//      FSMC_CLK Pin
+#define RTE_FSMC_CLK_PIN                0
+//      FSMC_NE1/NCE2 Pin
+#define RTE_FSMC_NE1_PIN                0
+//      FSMC_NE2/NCE3 Pin
+#define RTE_FSMC_NE2_PIN                0
+//      FSMC_NE3/NCE4_1 Pin
+#define RTE_FSMC_NE3_PIN                0
+//      FSMC_NE4 Pin
+#define RTE_FSMC_NE4_PIN                0
+//      FSMC_NCE4_2 Pin
+#define RTE_FSMC_NCE42_PIN              0
+//      FSMC_INT2 Pin
+#define RTE_FSMC_INT2_PIN               0
+//      FSMC_INT3 Pin
+#define RTE_FSMC_INT3_PIN               0
+//      FSMC_INTR Pin
+#define RTE_FSMC_INTR_PIN               0
+//      FSMC_NIORD Pin
+#define RTE_FSMC_NIORD_PIN              0
+//      FSMC_NIOWR Pin
+#define RTE_FSMC_NIOWR_PIN              0
+//      FSMC_NREG Pin
+#define RTE_FSMC_NREG_PIN               0
+//      FSMC_CD Pin
+#define RTE_FSMC_CD_PIN                 0
+
+//   
+
+//    NOR Flash / PSRAM Controller
+
+//      FSMC_NE1 Chip Select
+//      Configure Device on Chip Select FSMC_NE1
+#define RTE_FSMC_NE1                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR1_CBURSTRW          0
+#define RTE_FSMC_BCR1_ASYNCWAIT         0
+#define RTE_FSMC_BCR1_EXTMOD            0
+#define RTE_FSMC_BCR1_WAITEN            1
+#define RTE_FSMC_BCR1_WREN              1
+#define RTE_FSMC_BCR1_WAITCFG           0
+#define RTE_FSMC_BCR1_WRAPMOD           0
+#define RTE_FSMC_BCR1_WAITPOL           0
+#define RTE_FSMC_BCR1_BURSTEN           0
+#define RTE_FSMC_BCR1_FACCEN            1
+#define RTE_FSMC_BCR1_MWID              1
+#define RTE_FSMC_BCR1_MTYP              2
+#define RTE_FSMC_BCR1_MUXEN             1
+#define RTE_FSMC_BCR1_MBKEN             1
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR1_ACCMOD            0
+#define RTE_FSMC_BTR1_DATLAT            15
+#define RTE_FSMC_BTR1_CLKDIV            15
+#define RTE_FSMC_BTR1_BUSTURN           15
+#define RTE_FSMC_BTR1_DATAST            255
+#define RTE_FSMC_BTR1_ADDHLD            15
+#define RTE_FSMC_BTR1_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR1_ACCMOD        0
+#define RTE_FSMC_BWTR1_DATLAT        15
+#define RTE_FSMC_BWTR1_CLKDIV        15
+#define RTE_FSMC_BWTR1_BUSTURN       15
+#define RTE_FSMC_BWTR1_DATAST        255
+#define RTE_FSMC_BWTR1_ADDHLD        15
+#define RTE_FSMC_BWTR1_ADDSET        15
+//       
+//     
+
+//      FSMC_NE2 Chip Select
+//      Configure Device on Chip Select FSMC_NE2
+#define RTE_FSMC_NE2                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR2_CBURSTRW          0
+#define RTE_FSMC_BCR2_ASYNCWAIT         0
+#define RTE_FSMC_BCR2_EXTMOD            0
+#define RTE_FSMC_BCR2_WAITEN            1
+#define RTE_FSMC_BCR2_WREN              1
+#define RTE_FSMC_BCR2_WAITCFG           0
+#define RTE_FSMC_BCR2_WRAPMOD           0
+#define RTE_FSMC_BCR2_WAITPOL           0
+#define RTE_FSMC_BCR2_BURSTEN           0
+#define RTE_FSMC_BCR2_FACCEN            1
+#define RTE_FSMC_BCR2_MWID              1
+#define RTE_FSMC_BCR2_MTYP              0
+#define RTE_FSMC_BCR2_MUXEN             1
+#define RTE_FSMC_BCR2_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR2_ACCMOD            0
+#define RTE_FSMC_BTR2_DATLAT            15
+#define RTE_FSMC_BTR2_CLKDIV            15
+#define RTE_FSMC_BTR2_BUSTURN           15
+#define RTE_FSMC_BTR2_DATAST            255
+#define RTE_FSMC_BTR2_ADDHLD            15
+#define RTE_FSMC_BTR2_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR2_ACCMOD        0
+#define RTE_FSMC_BWTR2_DATLAT        15
+#define RTE_FSMC_BWTR2_CLKDIV        15
+#define RTE_FSMC_BWTR2_BUSTURN       15
+#define RTE_FSMC_BWTR2_DATAST        255
+#define RTE_FSMC_BWTR2_ADDHLD        15
+#define RTE_FSMC_BWTR2_ADDSET        15
+//       
+//     
+
+//      FSMC_NE3 Chip Select
+//      Configure Device on Chip Select FSMC_NE3
+#define RTE_FSMC_NE3                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR3_CBURSTRW          0
+#define RTE_FSMC_BCR3_ASYNCWAIT         0
+#define RTE_FSMC_BCR3_EXTMOD            0
+#define RTE_FSMC_BCR3_WAITEN            1
+#define RTE_FSMC_BCR3_WREN              1
+#define RTE_FSMC_BCR3_WAITCFG           0
+#define RTE_FSMC_BCR3_WRAPMOD           0
+#define RTE_FSMC_BCR3_WAITPOL           0
+#define RTE_FSMC_BCR3_BURSTEN           0
+#define RTE_FSMC_BCR3_FACCEN            1
+#define RTE_FSMC_BCR3_MWID              1
+#define RTE_FSMC_BCR3_MTYP              0
+#define RTE_FSMC_BCR3_MUXEN             1
+#define RTE_FSMC_BCR3_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR3_ACCMOD            0
+#define RTE_FSMC_BTR3_DATLAT            15
+#define RTE_FSMC_BTR3_CLKDIV            15
+#define RTE_FSMC_BTR3_BUSTURN           15
+#define RTE_FSMC_BTR3_DATAST            255
+#define RTE_FSMC_BTR3_ADDHLD            15
+#define RTE_FSMC_BTR3_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR3_ACCMOD        0
+#define RTE_FSMC_BWTR3_DATLAT        15
+#define RTE_FSMC_BWTR3_CLKDIV        15
+#define RTE_FSMC_BWTR3_BUSTURN       15
+#define RTE_FSMC_BWTR3_DATAST        255
+#define RTE_FSMC_BWTR3_ADDHLD        15
+#define RTE_FSMC_BWTR3_ADDSET        15
+//       
+//     
+
+//      FSMC_NE4 Chip Select
+//      Configure Device on Chip Select FSMC_NE4
+#define RTE_FSMC_NE4                    0
+
+//        Chip-select control
+//          CBURSTRW: Write burst enable <0=>Asynchronous write <1=>Synchronous write
+//          For Cellular RAM, this enables synchronous burst protocol during write operations. For Flash
+//          memory access in burst mode, this enables/disables the wait state insertion via the NWAIT signal.
+//          ASYNCWAIT: Wait signal during asynchronous transfer
+//          Enables the FSMC to use the wait signal even during an asynchronous protocol.
+//          EXTMOD: Extended mode enable
+//          Enables the FSMC to program inside the write timing register, so it allows different timings for read and write.
+//          WAITEN: Wait enable
+//          For Flash memory access in burst mode, this enables/disables wait-state insertion via the NWAIT signal.
+//          WREN: Write enable
+//          Enable/disable write operations in the current bank by the FSMC
+//          WAITCFG: Wait timing configuration <0=> NWAIT active before wait state <1=>NWAIT active during wait state
+//          For memory access in burst mode, the NWAIT signal indicates whether the data from the memory
+//          are valid or if a wait state must be inserted. This configuration bit determines if NWAIT is asserted
+//          by the memory one clock cycle before the wait state or during the wait state
+//          WAITPOL: Wait signal polarity <0=>NWAIT active low <1=>NWAIT active high
+//          Defines the polarity of the wait signal from memory. Valid only when accessing the memory in burst mode.
+//          BURSTEN: Burst enable
+//          Enables the burst access mode for the memory. Valid only with synchronous burst memories.
+//          FACCEN: Flash access enable
+//          Enables NOR Flash memory access operations.
+//          MWID: Memory databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width, valid for all type of memories.
+//          MTYP: Memory type <0=>SRAM, ROM <1=>PSRAM (Cellular RAM: CRAM) <2=>NOR Flash/OneNAND Flash
+//          Defines the type of external memory attached to the corresponding memory bank.
+//          MUXEN: Address/data multiplexing enable
+//          When enabled, the address and data values are multiplexed on the databus, valid only with NOR and PSRAM memories.
+//          MBKEN: Memory bank enable
+//          Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
+//          disabled bank causes an ERROR on AHB bus.
+#define RTE_FSMC_BCR4_CBURSTRW          0
+#define RTE_FSMC_BCR4_ASYNCWAIT         0
+#define RTE_FSMC_BCR4_EXTMOD            0
+#define RTE_FSMC_BCR4_WAITEN            1
+#define RTE_FSMC_BCR4_WREN              1
+#define RTE_FSMC_BCR4_WAITCFG           0
+#define RTE_FSMC_BCR4_WRAPMOD           0
+#define RTE_FSMC_BCR4_WAITPOL           0
+#define RTE_FSMC_BCR4_BURSTEN           0
+#define RTE_FSMC_BCR4_FACCEN            1
+#define RTE_FSMC_BCR4_MWID              1
+#define RTE_FSMC_BCR4_MTYP              0
+#define RTE_FSMC_BCR4_MUXEN             1
+#define RTE_FSMC_BCR4_MBKEN             0
+//       
+
+//        Chip-select timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with synchronous burst mode enabled, defines the number of memory clock
+//          cycles (+2) to issue to the memory before getting the first data:
+//          0000: Data latency of 2 CLK clock cycles for first burst access
+//          1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK)
+//          periods. In asynchronous NOR Flash, SRAM or ROM accesses, this value is don't care.
+//          In the case of CRAM, this field must be set to ‘0’.
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles:
+//          0000: Reserved
+//          0001: CLK period = 2 × HCLK periods
+//          0010: CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Define the bus turnaround delay after a read access only
+//          from multiplexed NOR Flash memory to avoid bus contention if the controller needs to drive
+//          addresses on the databus for the next side-by-side transaction. BUSTURN can be set to the
+//          minimum if the slowest memory does not take more than 6 HCLK clock cycles to put the
+//          databus in Hi-Z state.
+//          These bits are written by software to add a delay at the end of a write/read transaction. This
+//          delay allows to match the minimum time between consecutive transactions (tEHEL from NEx
+//          high to NEx low) and the maximum time needed by the memory to free the data bus after a
+//          read access (tEHQZ):
+//          (BUSTRUN + 1)HCLK period = tEHELmin and (BUSTRUN + 2)HCLK period = tEHQZmax if
+//          EXTMOD = ‘0’
+//          (BUSTRUN + 2)HCLK period = max (tEHELmin, tEHQZmax) if EXTMOD = ‘1’.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 × HCLK clock cycles (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Define the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Define the duration of the address hold phase used in mode D and multiplexed accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration =1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is not used, the address hold phase is always 1
+//          memory clock period duration.
+//          ADDSET: Address setup phase duration <0-15>
+//          Define the duration of the address setup phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 1615 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don’t care.
+#define RTE_FSMC_BTR4_ACCMOD            0
+#define RTE_FSMC_BTR4_DATLAT            15
+#define RTE_FSMC_BTR4_CLKDIV            15
+#define RTE_FSMC_BTR4_BUSTURN           15
+#define RTE_FSMC_BTR4_DATAST            255
+#define RTE_FSMC_BTR4_ADDHLD            15
+#define RTE_FSMC_BTR4_ADDSET            15
+//       
+
+//        Write timing
+//          ACCMOD: Access mode <0=>Mode A <1=>Mode B <2=>Mode C <3=>Mode D
+//          Specifies the asynchronous access modes. Access mode is taken into account only when
+//          Extended mode is enabled in the Chip-select control register.
+//          DATLAT: Data latency <0-15>
+//          For NOR Flash with Synchronous burst mode enabled, defines the number of memory clock cycles
+//          (+2) to issue to the memory before getting the first data.
+//          0000: (0x0) Data latency of 2 CLK clock cycles for first burst access
+//          ...
+//          1111: (0xF) Data latency of 17 CLK clock cycles for first burst access (default value after reset)
+//          Note: This timing parameter is not expressed in HCLK periods, but in Flash clock (CLK) periods. In
+//          asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care. In case of
+//          CRAM, this field must be set to 0
+//          CLKDIV: Clock divide ratio (for CLK signal) <1-15>
+//          Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+//          0000: Reserved
+//          0001 CLK period = 2 × HCLK periods
+//          0010 CLK period = 3 × HCLK periods
+//          1111: CLK period = 16 × HCLK periods (default value after reset)
+//          In asynchronous NOR Flash, SRAM or ROM accesses, this value is don’t care.
+//          BUSTURN: Bus turnaround phase duration <0-15>
+//          Defines a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low).
+//          (BUSTRUN + 1) HCLK period = tEHELmin.
+//          0000: BUSTURN phase duration = 0 HCLK clock cycle added
+//          ...
+//          1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
+//          DATAST: Data phase duration <1-255>
+//          Defines the duration of the data phase used in SRAMs, ROMs and asynchronous NOR Flash accesses.
+//          0000 0000: Reserved
+//          0000 0001: DATAST phase duration = 1 × HCLK clock cycles
+//          0000 0010: DATAST phase duration = 2 × HCLK clock cycles
+//          ...
+//          1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous accesses, this value is don't care.
+//          ADDHLD: Address hold phase duration <1-15>
+//          Defines the duration of the address hold phase used in SRAMs, ROMs and asynchronous multiplexed NOR Flash accesses.
+//          0000: Reserved
+//          0001: ADDHLD phase duration = 1 × HCLK clock cycle
+//          0010: ADDHLD phase duration = 2 × HCLK clock cycle
+//          ...
+//          1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
+//          ADDSET: Address setup phase duration <1-15>
+//          Defines the duration of the address setup phase in HCLK cycles used in SRAMs, ROMs and asynchronous NOR Flash accessed.
+//          0000: ADDSET phase duration = 0 × HCLK clock cycle
+//          ...
+//          1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
+//          Note: In synchronous NOR Flash accesses, this value is don’t care.
+#define RTE_FSMC_BWTR4_ACCMOD        0
+#define RTE_FSMC_BWTR4_DATLAT        15
+#define RTE_FSMC_BWTR4_CLKDIV        15
+#define RTE_FSMC_BWTR4_BUSTURN       15
+#define RTE_FSMC_BWTR4_DATAST        255
+#define RTE_FSMC_BWTR4_ADDHLD        15
+#define RTE_FSMC_BWTR4_ADDSET        15
+//       
+//     
+
+//   
+
+//    NAND Flash Controller
+
+//      FSMC_NCE2 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE2
+#define RTE_FSMC_NCE2                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR2_ECCPS             0
+#define RTE_FSMC_PCR2_TAR               0
+#define RTE_FSMC_PCR2_TCLR              0
+#define RTE_FSMC_PCR2_ECCEN             0
+#define RTE_FSMC_PCR2_PWID              0
+#define RTE_FSMC_PCR2_PTYP              1
+#define RTE_FSMC_PCR2_PBKEN             0
+#define RTE_FSMC_PCR2_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR2_IFEN               0
+#define RTE_FSMC_SR2_ILEN               0
+#define RTE_FSMC_SR2_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM2_MEMHIZ           255
+#define RTE_FSMC_PMEM2_MEMHOLD          255
+#define RTE_FSMC_PMEM2_MEMWAIT          255
+#define RTE_FSMC_PMEM2_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT2_ATTHIZ           255
+#define RTE_FSMC_PATT2_ATTHOLD          255
+#define RTE_FSMC_PATT2_ATTWAIT          255
+#define RTE_FSMC_PATT2_ATTSET           255
+
+//       
+
+//     
+
+//      FSMC_NCE3 Chip Select
+//      Configure NAND Device on Chip Select FSMC_NCE3
+#define RTE_FSMC_NCE3                   0
+
+//        NAND Flash Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable 
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <1=>NAND Flash
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: NAND Flash memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR3_ECCPS             0
+#define RTE_FSMC_PCR3_TAR               0
+#define RTE_FSMC_PCR3_TCLR              0
+#define RTE_FSMC_PCR3_ECCEN             0
+#define RTE_FSMC_PCR3_PWID              0
+#define RTE_FSMC_PCR3_PTYP              1
+#define RTE_FSMC_PCR3_PBKEN             0
+#define RTE_FSMC_PCR3_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR3_IFEN               0
+#define RTE_FSMC_SR3_ILEN               0
+#define RTE_FSMC_SR3_IREN               0
+
+//       
+
+//       Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM3_MEMHIZ           255
+#define RTE_FSMC_PMEM3_MEMHOLD          255
+#define RTE_FSMC_PMEM3_MEMWAIT          255
+#define RTE_FSMC_PMEM3_MEMSET           255
+
+//       
+
+//       Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT3_ATTHIZ           255
+#define RTE_FSMC_PATT3_ATTHOLD          255
+#define RTE_FSMC_PATT3_ATTWAIT          255
+#define RTE_FSMC_PATT3_ATTSET           255
+
+//       
+
+//     
+
+//   
+
+//    PC Card Controller
+
+//      FSMC_NCE4_x Chip Select
+//      Configure PC Card/CompactFlash Device on Chip Select FSMC_NCE4_1/FSMC_NCE4_2
+#define RTE_FSMC_NCE4              0
+
+//        PC Card Control
+//          ECCPS: ECC page size <0=> 256 bytes <1=> 512 bytes <2=> 1024 bytes <3=> 2048 bytes <4=> 4096 bytes <5=> 8192 bytes
+//          Defines the page size for the extended ECC.
+//          TAR: ALE to RE delay <0-15>
+//          Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          TCLR: CLE to RE delay <0-15>
+//          Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
+//          Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
+//          0000: 1 HCLK cycle (default)
+//          1111: 16 HCLK cycles
+//          Note: SET is MEMSET or ATTSET according to the addressed space.
+//          ECCEN: ECC computation logic enable
+//         PWID: Databus width <0=>8 bits <1=>16 bits
+//          Defines the external memory device width.
+//          PTYP: Memory type <0=>PC Card, CompactFlash, CF+ or PCMCIOA
+//          Defines the type of device attached to the corresponding memory bank.
+//          PBKEN: PC Card memory bank enable
+//          Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB bus.
+//          PWAITEN: Wait feature enable
+//          Enables the Wait feature for the PC Card/NAND Flash memory bank.
+#define RTE_FSMC_PCR4_ECCPS             0
+#define RTE_FSMC_PCR4_TAR               0
+#define RTE_FSMC_PCR4_TCLR              0
+#define RTE_FSMC_PCR4_ECCEN             0
+#define RTE_FSMC_PCR4_PWID              0
+#define RTE_FSMC_PCR4_PTYP              0
+#define RTE_FSMC_PCR4_PBKEN             0
+#define RTE_FSMC_PCR4_PWAITEN           0
+
+//       
+
+//        Interrupt configuration
+//         IFEN: Falling edge detection enable
+//         ILEN: High-level detection enable
+//         IREN: Rising edge detection enable
+#define RTE_FSMC_SR4_IFEN               0
+#define RTE_FSMC_SR4_ILEN               0
+#define RTE_FSMC_SR4_IREN               0
+
+//       
+
+//        Common memory space timing
+//          MEMHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          MEMWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access to. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the Card deasserting NWAIT) (default value after reset)
+//          MEMSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 2 HCLK cycles (for NAND Flash)
+//           1111 1111: 257 HCLK cycles (for NAND Flash) (default value after reset)
+#define RTE_FSMC_PMEM4_MEMHIZ           255
+#define RTE_FSMC_PMEM4_MEMHOLD          255
+#define RTE_FSMC_PMEM4_MEMWAIT          255
+#define RTE_FSMC_PMEM4_MEMSET           255
+
+//       
+
+//        Attribute memory space timing
+//          ATTHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a NAND Flash write access.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          ATTWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
+//           NOE), for NAND Flash read or write access. The duration for command assertion
+//           is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value.
+//           0000 0000: reserved
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles (+ wait cycle introduced by the card deasserting NWAIT)
+//          ATTSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up address before the command
+//           assertion (NWE, NOE), for NAND Flash read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PATT4_ATTHIZ           255
+#define RTE_FSMC_PATT4_ATTHOLD          255
+#define RTE_FSMC_PATT4_ATTWAIT          255
+#define RTE_FSMC_PATT4_ATTSET           255
+
+//       
+
+//        I/O space timing
+//          IOHIZ: Databus HiZ time <0-255>
+//           Defines the number of HCLK clock cycles during which the databus is kept in HiZ after the
+//           start of a PC Card write access. Only valid for write transaction.
+//           0000 0000: 0 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOHOLD: Hold time <1-255>
+//           Defines the number of HCLK clock cycles to hold address (and data for write access) after
+//           the command deassertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: reserved
+//           0000 0001: 1 HCLK cycle
+//           1111 1111: 255 HCLK cycles (default value after reset)
+//          IOWAIT: Wait time <1-255>
+//           Defines the minimum number of HCLK (+1) clock cycles to assert the command (SMNWE,
+//           SMNOE), for PC Card read or write access. The duration for command assertion is
+//           extended if the wait signal (NWAIT) is active (low) at the end of the
+//           programmed value of HCLK.
+//           0000 0000: reserved, do not use this value
+//           0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
+//           1111 1111: 256 HCLK cycles
+//          IOSET: Setup time <0-255>
+//           Defines the number of HCLK (+1) clock cycles to set up the address before the command
+//           assertion (NWE, NOE), for PC Card read or write access.
+//           0000 0000: 1 HCLK cycle
+//           1111 1111: 256 HCLK cycles (default value after reset)
+#define RTE_FSMC_PIO4_IOHIZ             255
+#define RTE_FSMC_PIO4_IOHOLD            255
+#define RTE_FSMC_PIO4_IOWAIT            255
+#define RTE_FSMC_PIO4_IOSET             255
+
+//       
+
+//     
+
+//   
+
+// 
+
+
+#endif  /* __RTE_DEVICE_H */
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s
new file mode 100644
index 000000000..b2a3fc40f
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s
@@ -0,0 +1,419 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f2xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0
+;* Date               : 18-April-2011
+;* Description        : STM32F2xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM3 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00004000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x0000A000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng 
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler                                               
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/system_stm32f2xx.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/system_stm32f2xx.c
new file mode 100644
index 000000000..da0e189c8
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Device/STM32F207IG/system_stm32f2xx.c
@@ -0,0 +1,536 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f2xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    18-April-2011
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F2xx devices,
+  *          and is generated by the clock configuration tool
+  *          "STM32f2xx_Clock_Configuration_V1.0.0.xls"
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f2xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F2xx device revision    | Rev B and Y
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 120000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 120000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 240
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 5
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 3
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | ON
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
© COPYRIGHT 2011 STMicroelectronics

+  ******************************************************************************  
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f2xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F2xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f2xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM322xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      240
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 120000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F2xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+  * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f2xx.s
+  *         before jump to __main
+  * @param  None
+  * @retval None
+  */
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f2xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM322xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                  +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
+ | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
+ | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
+ | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
+ | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
+ | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
+ | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
+ | PD14 <-> FSMC_D0  | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
+ | PD15 <-> FSMC_D1  | PE15 <-> FSMC_D12  |------------------+
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xa2aa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xf3ff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00000cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa800a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc00f;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config.c
new file mode 100644
index 000000000..78564b080
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config.c
@@ -0,0 +1,72 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config.c
+ * Purpose: File System Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// File System
+// Define File System global parameters
+
+//   Number of open files <4-16>
+//   Define number of files that can be
+//   opened at the same time.
+//   Default: 8
+#define NUM_FILES               8
+
+//   FAT Name Cache Size <0-1000000>
+//   Define number of cached FAT file or directory names.
+//   48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACHE_SIZE     0
+
+//   Relocate FAT Name Cache Buffer
+//   Locate Cache Buffer at a specific address.
+#define FAT_NAME_CACHE_RELOC    0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Define the Cache buffer base address.
+#define FAT_NAME_CACHE_ADDR     0x60000000
+
+//   
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_FileSystem_Drive_RAM
+#include "FS_Config_RAM.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NOR_0
+#include "FS_Config_NOR_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NOR_1
+#include "FS_Config_NOR_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_NAND_0
+#include "FS_Config_NAND_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_NAND_1
+#include "FS_Config_NAND_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_MC_0
+#include "FS_Config_MC_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_MC_1
+#include "FS_Config_MC_1.h"
+#endif
+
+#ifdef  RTE_FileSystem_Drive_USB_0
+#include "FS_Config_USB_0.h"
+#endif
+#ifdef  RTE_FileSystem_Drive_USB_1
+#include "FS_Config_USB_1.h"
+#endif
+
+#include "fs_config.h"
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config_MC_0.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config_MC_0.h
new file mode 100644
index 000000000..0b1c6d3a7
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/File_System/FS_Config_MC_0.h
@@ -0,0 +1,57 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::File System:Drive
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    FS_Config_MC_0.h
+ * Purpose: File System Configuration for Memory Card Drive
+ * Rev.:    V5.01
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Memory Card Drive 0
+// Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
+#define MC0_ENABLE              1
+
+//   Connect to hardware via Driver_MCI# <0-255>
+//   Select driver control block for hardware interface
+#define MC0_MCI_DRIVER          0
+
+//   Connect to hardware via Driver_SPI# <0-255>
+//   Select driver control block for hardware interface when in SPI mode
+#define MC0_SPI_DRIVER          0
+
+//   Memory Card Interface Mode <0=>Native <1=>SPI
+//   Native uses a SD Bus with up to 8 data lines, CLK, and CMD
+//   SPI uses 2 data lines (MOSI and MISO), SCLK and CS
+//   When using SPI both Driver_SPI# and Driver_MCI# must be specified
+//   since the MCI driver provides the control interface lines.
+#define MC0_SPI                 0
+          
+//   Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+//                       <8=>8 KB <16=>16 KB <32=>32 KB
+//   Drive Cache stores data sectors and may be increased to speed-up
+//   file read/write operations on this drive (default: 4 KB)
+#define MC0_CACHE_SIZE          4
+
+//   Locate Drive Cache and Drive Buffer
+//   Some microcontrollers support DMA only in specific memory areas and
+//   require to locate the drive buffers at a fixed address.
+#define MC0_CACHE_RELOC         0
+
+//     Base address <0x0000-0xFFFFFE00:0x200>
+//     Set buffer base address to RAM areas that support DMA with the drive.
+#define MC0_CACHE_ADDR          0x7FD00000
+
+//   
+
+//   Use FAT Journal
+//   Protect File Allocation Table and Directory Entries for
+//   fail-safe operation.
+#define MC0_FAT_JOURNAL         0
+
+//   Default Drive "M0:"
+//   Use this drive when no drive letter is specified.
+#define MC0_DEFAULT_DRIVE       1
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config.c
new file mode 100644
index 000000000..6b9dc8e00
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config.c
@@ -0,0 +1,153 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config.c
+ * Purpose: Network Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// System Definitions
+//  Global Network System definitions
+//   Local Host Name
+//    This is the name under which embedded host can be
+//    accessed on a local area network.
+//    Default: "my_host"
+#define NET_HOST_NAME           "my_host"
+
+//   Memory Pool size <1536-262144:4><#/4>
+//    This is the size of a memory pool in bytes. Buffers for
+//    Network packets are allocated from this memory pool.
+//    Default: 12000 bytes
+#define NET_MEM_SIZE            3000
+
+// 
+
+#include "..\RTE_Components.h"
+
+#ifdef  RTE_Network_Interface_ETH_0
+#include "Net_Config_ETH_0.h"
+#endif
+#ifdef  RTE_Network_Interface_ETH_1
+#include "Net_Config_ETH_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_PPP_0
+#include "Net_Config_PPP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_PPP_1
+#include "Net_Config_PPP_1.h"
+#endif
+
+#ifdef  RTE_Network_Interface_SLIP_0
+#include "Net_Config_SLIP_0.h"
+#endif
+#ifdef  RTE_Network_Interface_SLIP_1
+#include "Net_Config_SLIP_1.h"
+#endif
+
+#ifdef  RTE_Network_Socket_UDP
+#include "Net_Config_UDP.h"
+#endif
+#ifdef  RTE_Network_Socket_TCP
+#include "Net_Config_TCP.h"
+#endif
+#ifdef  RTE_Network_Socket_BSD
+#include "Net_Config_BSD.h"
+#endif
+
+#ifdef  RTE_Network_Web_Server_RO
+#include "Net_Config_HTTP_Server.h"
+#endif
+#ifdef  RTE_Network_Web_Server_FS
+#include "Net_Config_HTTP_Server.h"
+#endif
+
+#ifdef  RTE_Network_Telnet_Server
+#include "Net_Config_Telnet_Server.h"
+#endif
+
+#ifdef  RTE_Network_TFTP_Server
+#include "Net_Config_TFTP_Server.h"
+#endif
+#ifdef  RTE_Network_TFTP_Client
+#include "Net_Config_TFTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_FTP_Server
+#include "Net_Config_FTP_Server.h"
+#endif
+#ifdef  RTE_Network_FTP_Client
+#include "Net_Config_FTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_DNS_Client
+#include "Net_Config_DNS_Client.h"
+#endif
+
+#ifdef  RTE_Network_SMTP_Client
+#include "Net_Config_SMTP_Client.h"
+#endif
+
+#ifdef  RTE_Network_SNMP_Agent
+#include "Net_Config_SNMP_Agent.h"
+#endif
+
+#ifdef  RTE_Network_SNTP_Client
+#include "Net_Config_SNTP_Client.h"
+#endif
+
+#include "net_config.h"
+
+/**
+\addtogroup net_genFunc
+@{
+*/
+/**
+  \fn          void net_sys_error (ERROR_CODE error)
+  \ingroup     net_cores
+  \brief       Network system error handler.
+*/
+void net_sys_error (ERROR_CODE error) {
+  /* This function is called when a fatal error is encountered. */
+  /* The normal program execution is not possible anymore.      */
+
+  switch (error) {
+    case ERR_MEM_ALLOC:
+      /* Out of memory */
+      break;
+
+    case ERR_MEM_FREE:
+      /* Trying to release non existing memory block */
+      break;
+
+    case ERR_MEM_CORRUPT:
+      /* Memory Link pointer Corrupted */
+      /* More data written than the size of allocated mem block */
+      break;
+
+    case ERR_MEM_LOCK:
+      /* Locked Memory management function (alloc/free) re-entered */
+      break;
+
+    case ERR_UDP_ALLOC:
+      /* Out of UDP Sockets */
+      break;
+
+    case ERR_TCP_ALLOC:
+      /* Out of TCP Sockets */
+      break;
+
+    case ERR_TCP_STATE:
+      /* TCP State machine in undefined state */
+      break;
+  }
+
+  /* End-less loop */
+  while (1);
+}
+/**
+@}
+*/
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_BSD.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_BSD.h
new file mode 100644
index 000000000..4166a0a2d
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_BSD.h
@@ -0,0 +1,36 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_BSD.h
+ * Purpose: Network Configuration BSD Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Berkley (BSD) Sockets
+#define BSD_ENABLE              1
+
+//   Number of BSD Sockets <1-20>
+//    Number of available Berkeley Sockets
+//    Default: 2
+#define BSD_NUM_SOCKS           15
+
+//   Number of Streaming Server Sockets <0-20>
+//    Defines a number of Streaming (TCP) Server sockets,
+//    that listen for an incoming connection from the client.
+//    Default: 1
+#define BSD_SERVER_SOCKS        1
+
+//   Receive Timeout in seconds <0-600>
+//    A timeout for socket receive in blocking mode.
+//    Timeout value of 0 means indefinite timeout.
+//    Default: 20
+#define BSD_RECEIVE_TOUT        20
+
+//   Hostname Resolver
+//    Enable or disable Berkeley style hostname resolver.
+#define BSD_HOSTNAME_ENABLE     0
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_DNS_Client.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_DNS_Client.h
new file mode 100644
index 000000000..d30b71807
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_DNS_Client.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Service
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_DNS_Client.h
+ * Purpose: Network Configuration DNS Client
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// DNS Client
+#define DNS_CLIENT_ENABLE       1
+
+//     Cache Table size <5-100>
+//      Number of cached DNS host names/IP addresses
+//      Default: 20
+#define DNS_CLIENT_TAB_SIZE     20
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_ETH_0.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_ETH_0.h
new file mode 100644
index 000000000..9a49f3821
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_ETH_0.h
@@ -0,0 +1,222 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Interface
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_ETH_0.h
+ * Purpose: Network Configuration ETH Interface
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Ethernet Network Interface 0
+#define ETH0_ENABLE             1
+
+//   Connect to hardware via Driver_ETH# <0-255>
+//   Select driver control block for MAC and PHY interface
+#define ETH0_DRIVER             1
+
+//   MAC Address
+//    Local Ethernet MAC Address
+//    Value FF:FF:FF:FF:FF:FF is not allowed.
+//    It is an ethernet Broadcast MAC address.
+//     Address byte 1 <0x00-0xff:2>
+//      LSB is an ethernet Multicast bit.
+//      Must be 0 for local MAC address.
+//      Default: 0x1E
+#define ETH0_MAC1               0x1E
+
+//     Address byte 2 <0x00-0xff>
+//      Default: 0x30
+#define ETH0_MAC2               0x30
+
+//     Address byte 3 <0x00-0xff>
+//      Default: 0x6C
+#define ETH0_MAC3               0x6C
+
+//     Address byte 4 <0x00-0xff>
+//      Default: 0xA2
+#define ETH0_MAC4               0xA2
+
+//     Address byte 5 <0x00-0xff>
+//      Default: 0x45
+#define ETH0_MAC5               0x45
+
+//     Address byte 6 <0x00-0xff>
+//      Default: 0x5E
+#define ETH0_MAC6               0x5E
+//   
+
+//   IP Address
+//    Local Static IP Address
+//    Value 255.255.255.255 is not allowed.
+//    It is a Broadcast IP address.
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_IP1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_IP2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_IP3                0
+
+//     Address byte 4 <0-255>
+//      Default: 100
+#define ETH0_IP4                100
+//   
+
+//   Subnet mask
+//    Local Subnet mask
+//     Mask byte 1 <0-255>
+//      Default: 255
+#define ETH0_MASK1              255
+
+//     Mask byte 2 <0-255>
+//      Default: 255
+#define ETH0_MASK2              255
+
+//     Mask byte 3 <0-255>
+//      Default: 255
+#define ETH0_MASK3              255
+
+//     Mask byte 4 <0-255>
+//      Default: 0
+#define ETH0_MASK4              0
+//   
+
+//   Default Gateway
+//    Default Gateway IP Address
+//     Address byte 1 <0-255>
+//      Default: 192
+#define ETH0_GW1                192
+
+//     Address byte 2 <0-255>
+//      Default: 168
+#define ETH0_GW2                168
+
+//     Address byte 3 <0-255>
+//      Default: 0
+#define ETH0_GW3                0
+
+//     Address byte 4 <0-255>
+//      Default: 254
+#define ETH0_GW4                254
+//   
+
+//   Primary DNS Server
+//    Primary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_PRI_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_PRI_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_PRI_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 129
+#define ETH0_PRI_DNS4           129
+//   
+
+//   Secondary DNS Server
+//    Secondary DNS Server IP Address
+//     Address byte 1 <0-255>
+//      Default: 194
+#define ETH0_SEC_DNS1           194
+
+//     Address byte 2 <0-255>
+//      Default: 25
+#define ETH0_SEC_DNS2           25
+
+//     Address byte 3 <0-255>
+//      Default: 2
+#define ETH0_SEC_DNS3           2
+
+//     Address byte 4 <0-255>
+//      Default: 130
+#define ETH0_SEC_DNS4           130
+//   
+
+//   ARP Definitions
+//    Address Resolution Protocol Definitions
+//     Cache Table size <5-100>
+//      Number of cached hardware/IP addresses
+//      Default: 10
+#define ETH0_ARP_TAB_SIZE       10
+
+//     Cache Timeout in seconds <5-255>
+//      A timeout for a cached hardware/IP addresses
+//      Default: 150
+#define ETH0_ARP_CACHE_TOUT     150
+
+//     Number of Retries <0-20>
+//      Number of Retries to resolve an IP address
+//      before ARP module gives up
+//      Default: 4
+#define ETH0_ARP_MAX_RETRY      4
+
+//     Resend Timeout in seconds <1-10>
+//      A timeout to resend the ARP Request
+//      Default: 2
+#define ETH0_ARP_RESEND_TOUT    2
+
+//     Send Notification on Address changes
+//      When this option is enabled, the embedded host
+//      will send a Gratuitous ARP notification at startup,
+//      or when the device IP address has changed.
+//      Default: Disabled
+#define ETH0_ARP_NOTIFY         0
+//   
+
+//   IGMP Group Management
+//    Enable or disable Internet Group Management Protocol
+#define ETH0_IGMP_ENABLE        0
+
+//     Membership Table size <2-50>
+//      Number of Groups this host can join
+//      Default: 5
+#define ETH0_IGMP_TAB_SIZE      5
+//   
+
+//   NetBIOS Name Service
+//    When this option is enabled, the embedded host can be
+//    accessed by his name on the local LAN using NBNS protocol.
+//    You need to modify also the number of UDP Sockets,
+//    because NBNS protocol uses one UDP socket to run.
+#define ETH0_NBNS_ENABLE        1
+
+//   Dynamic Host Configuration
+//    When this option is enabled, local IP address, Net Mask
+//    and Default Gateway are obtained automatically from
+//    the DHCP Server on local LAN.
+//    You need to modify also the number of UDP Sockets,
+//    because DHCP protocol uses one UDP socket to run.
+#define ETH0_DHCP_ENABLE        0
+
+//     Vendor Class Identifier
+//      This value is optional. If specified, it is added
+//      to DHCP request message, identifying vendor type.
+//      Default: ""
+#define ETH0_DHCP_VCID          ""
+
+//     Bootfile Name
+//      This value is optional. If enabled, the Bootfile Name
+//      (option 67) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_BOOTFILE      0
+
+//     NTP Servers
+//      This value is optional. If enabled, a list of NTP Servers
+//      (option 42) is also requested from DHCP server.
+//      Default: disabled
+#define ETH0_DHCP_NTP_SERVERS   0
+//   
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_TCP.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_TCP.h
new file mode 100644
index 000000000..9d5b419e4
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_TCP.h
@@ -0,0 +1,61 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_TCP.h
+ * Purpose: Network Configuration TCP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// TCP Sockets
+#define TCP_ENABLE              1
+
+//   Number of TCP Sockets <1-20>
+//    Number of available TCP sockets
+//    Default: 5
+#define TCP_NUM_SOCKS           15
+
+//   Number of Retries <0-20>
+//    How many times TCP module will try to retransmit data
+//    before giving up. Increase this value for high-latency
+//    and low_throughput networks.
+//    Default: 5
+#define TCP_MAX_RETRY           5
+
+//   Retry Timeout in seconds <1-10>
+//    If data frame not acknowledged within this time frame,
+//    TCP module will try to resend the data again.
+//    Default: 4
+#define TCP_RETRY_TOUT          4
+
+//   Default Connect Timeout in seconds <1-600>
+//    Default TCP Socket Keep Alive timeout. When it expires
+//    with no TCP data frame send, TCP Connection is closed.
+//    Default: 120
+#define TCP_DEFAULT_TOUT        120
+
+//   Maximum Segment Size <536-1460>
+//    The Maximum Segment Size specifies the maximum
+//    number of bytes in the TCP segment's Data field.
+//    Default: 1460
+#define TCP_MAX_SEG_SIZE        1460
+
+//   Receive Window Size <536-65535>
+//    Receive Window Size specifies the size of data, 
+//    that the socket is able to buffer in flow-control mode.
+//    Default: 4380
+#define TCP_RECEIVE_WIN_SIZE    4380
+
+// 
+
+// TCP Initial Retransmit period in seconds
+#define TCP_INITIAL_RETRY_TOUT  1
+
+// TCP SYN frame retransmit period in seconds
+#define TCP_SYN_RETRY_TOUT      2
+
+// Number of retries to establish a connection
+#define TCP_CONNECT_RETRY       7
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_UDP.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_UDP.h
new file mode 100644
index 000000000..113f314a9
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Config_UDP.h
@@ -0,0 +1,20 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network:Socket
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Config_UDP.h
+ * Purpose: Network Configuration UDP Sockets
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// UDP Sockets
+#define UDP_ENABLE              1
+
+//   Number of UDP Sockets <1-20>
+//    Number of available UDP sockets
+//    Default: 5
+#define UDP_NUM_SOCKS           20
+
+// 
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Debug.c b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Debug.c
new file mode 100644
index 000000000..735089a40
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/Network/Net_Debug.c
@@ -0,0 +1,125 @@
+/*------------------------------------------------------------------------------
+ * MDK Middleware - Component ::Network
+ * Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
+ *------------------------------------------------------------------------------
+ * Name:    Net_Debug.c
+ * Purpose: Network Debug Configuration
+ * Rev.:    V5.00
+ *----------------------------------------------------------------------------*/
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
+
+// Print Time Stamp
+//    Enable printing the time-info in debug messages
+#define DBG_TIME                1
+
+// TCPnet Debug Definitions
+//   Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Memory debug messages
+#define DBG_MEM                 1
+
+//   Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Ethernet debug messages
+#define DBG_ETH                 0
+
+//   PPP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off PPP debug messages
+#define DBG_PPP                 0
+
+//   SLIP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SLIP debug messages
+#define DBG_SLIP                0
+
+//   ARP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ARP debug messages
+#define DBG_ARP                 0
+
+//   IP Debug    <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IP debug messages
+#define DBG_IP                  1
+
+//   ICMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off ICMP debug messages
+#define DBG_ICMP                1
+
+//   IGMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off IGMP debug messages
+#define DBG_IGMP                1
+
+//   UDP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off UDP debug messages
+#define DBG_UDP                 1
+
+//   TCP Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TCP debug messages
+#define DBG_TCP                 1
+
+//   NBNS Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off NetBIOS Name Service debug messages
+#define DBG_NBNS                1
+
+//   DHCP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Dynamic Host Configuration debug messages
+#define DBG_DHCP                1
+
+//   DNS Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Domain Name Service debug messages
+#define DBG_DNS                 1
+
+//   SNMP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Management debug messages
+#define DBG_SNMP                1
+
+//   SNTP Debug  <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Simple Network Time debug messages
+#define DBG_SNTP                1
+
+//   BSD Debug   <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off BSD Interface debug messages
+#define DBG_BSD                 1
+// 
+
+// Application Debug Definitions
+//   HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Web Server debug messages
+#define DBG_HTTP_SERVER         1
+
+//   FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Server debug messages
+#define DBG_FTP_SERVER          1
+
+//   FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off FTP Client debug messages
+#define DBG_FTP_CLIENT          1
+
+//   Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off Telnet Server debug messages
+#define DBG_TELNET_SERVER       1
+
+//   TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Server debug messages
+#define DBG_TFTP_SERVER         1
+
+//   TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off TFTP Client debug messages
+#define DBG_TFTP_CLIENT         1
+
+//   SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
+//    Turn On/Off SMTP Client debug messages
+#define DBG_SMTP_CLIENT         1
+// 
+
+
+#include "net_debug.h"
+
+
+/**
+  \fn          void net_debug_init (void)
+  \brief       Initialize Network Debug Interface.
+*/
+void net_debug_init (void) {
+  /* Add your code to initialize the Debug output. This is usually the  */
+  /* serial interface. The function is called at TCPnet system startup. */
+  /* You may need to customize also the 'putchar()' function.           */
+
+}
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/RTE/RTE_Components.h b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/RTE_Components.h
new file mode 100644
index 000000000..dc29d6c59
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/RTE/RTE_Components.h
@@ -0,0 +1,28 @@
+
+/*
+ * Auto generated Run-Time-Environment Component Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'SimpleServer' 
+ * Target:  'SimpleServer' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#define RTE_DEVICE_STARTUP_STM32F2xx    /* Device Startup for STM32F2 */
+#define RTE_Drivers_ETH_MAC0            /* Driver ETH_MAC0 */
+#define RTE_Drivers_MCI0                /* Driver MCI0 */
+#define RTE_Drivers_PHY_ST802RT1        /* Driver PHY ST802RT1 */
+#define RTE_FileSystem_Core             /* File System Core */
+          #define RTE_FileSystem_LFN              /* File System with Long Filename support */
+#define RTE_FileSystem_Drive_MC_0       /* File System Memory Card Drive 0 */
+#define RTE_Network_Core                /* Network Core */
+          #define RTE_Network_Debug               /* Network Debug Version */
+#define RTE_Network_DNS_Client          /* Network DNS Client */
+#define RTE_Network_Interface_ETH_0     /* Network Interface ETH 0 */
+#define RTE_Network_Socket_BSD          /* Network Socket BSD */
+#define RTE_Network_Socket_TCP          /* Network Socket TCP */
+#define RTE_Network_Socket_UDP          /* Network Socket UDP */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/STM32_SWO.ini b/IDE/MDK5-ARM/Projects/SimpleServer/STM32_SWO.ini
new file mode 100644
index 000000000..239abce37
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/STM32_SWO.ini
@@ -0,0 +1,36 @@
+/******************************************************************************/
+/* STM32_SWO.ini: STM32 Debugger Initialization File                           */
+/******************************************************************************/
+// <<< Use Configuration Wizard in Context Menu >>>                           // 
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools.                    */
+/* Copyright (c) 2004-2013 Keil Software. All rights reserved.                */
+/* This software may only be used under the terms of a valid, current,        */
+/* end user licence from KEIL for a compatible version of KEIL software       */
+/* development tools. Nothing else gives you the right to use this software.  */
+/******************************************************************************/
+
+
+FUNC void DebugSetup (void) {
+//  Debug MCU Configuration
+//       DBG_SLEEP      Debug Sleep Mode
+//       DBG_STOP       Debug Stop Mode
+//       DBG_STANDBY    Debug Standby Mode
+//       TRACE_IOEN     Trace I/O Enable 
+//    TRACE_MODE     Trace Mode
+//             <0=> Asynchronous
+//             <1=> Synchronous: TRACEDATA Size 1
+//             <2=> Synchronous: TRACEDATA Size 2
+//             <3=> Synchronous: TRACEDATA Size 4
+//       DBG_IWDG_STOP  Independant Watchdog Stopped when Core is halted
+//       DBG_WWDG_STOP  Window Watchdog Stopped when Core is halted
+//      DBG_TIM1_STOP  Timer 1 Stopped when Core is halted
+//      DBG_TIM2_STOP  Timer 2 Stopped when Core is halted
+//      DBG_TIM3_STOP  Timer 3 Stopped when Core is halted
+//      DBG_TIM4_STOP  Timer 4 Stopped when Core is halted
+//      DBG_CAN_STOP   CAN Stopped when Core is halted
+// 
+  _WDWORD(0xE0042004, 0x00000027);  // DBGMCU_CR
+}
+
+DebugSetup();                       // Debugger Setup
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx
new file mode 100644
index 000000000..b3a8b8dbb
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvoptx
@@ -0,0 +1,1406 @@
+
+
+
+  1.0
+
+  
### uVision Project, (C) Keil Software

+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    SimpleServer
+    0x4
+    ARM-ADS
+    
+      120000000
+      
+        1
+        1
+        0
+        1
+      
+      
+        1
+        65535
+        0
+        0
+        0
+      
+      
+        79
+        66
+        8
+        .\Object\
+      
+      
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+        1
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+        1
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+        0
+        0
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+      
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+        1
+        1
+        1
+        1
+        0
+        0
+      
+      
+        1
+        0
+        1
+      
+      255
+      
+        SARMCM3.DLL
+        -REMAP -MPU
+        DCM.DLL
+        -pCM3
+        SARMCM3.DLL
+        -REMAP -MPU
+        TCM.DLL
+        -pCM3
+      
+      
+        0
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        1
+        0
+        1
+        1
+        0
+        0
+        8
+        
+        
+        
+        
+        
+        
+        
+        
+        
+        .\STM32_SWO.ini
+        BIN\ULP2CM3.DLL
+      
+      
+        
+          0
+          DLGTARM
+          (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+        
+        
+          0
+          ARMDBGFLAGS
+          
+        
+        
+          0
+          ULP2CM3
+          -UP1135060 -O206 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO19 -TC120000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIE1 -TIP1 -FO7 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024.flm -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm)
+        
+        
+          0
+          DLGUARM
+          
+        
+        
+          0
+          UL2CM3
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+        
+      
+      
+      
+        
+          1
+          8
+          0x20000408
+        
+      
+      
+        
+          2
+          8
+          0x8004dc8
+        
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+      
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+      
+      
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+  
+
+  
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+      .\main.c
+      main.c
+      0
+      0
+    
+    
+      1
+      2
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+      0
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+      0
+      0
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+      .\server.c
+      server.c
+      0
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+  
+
+  
+    Configuration
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+      0
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+      .\RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      0
+      0
+    
+    
+      2
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+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      .\RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      0
+      0
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+  
+
+  
+    Documentation
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+      0
+      0
+      0
+      1
+      1
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+      .\Abstract.txt
+      Abstract.txt
+      0
+      0
+    
+  
+
+  
+    ::CMSIS
+    0
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+    
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+      0
+      0
+      0
+      0
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+      C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+      RTX_CM3.lib
+      1
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+    
+    
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+      RTE\CMSIS\RTX_Conf_CM.c
+      RTX_Conf_CM.c
+      1
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+
+  
+    ::Device
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+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c
+      DMA_STM32F2xx.c
+      1
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+    
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+      C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+      GPIO_STM32F2xx.c
+      1
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+      RTE_Device.h
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+      RTE\Device\STM32F207IG\system_stm32f2xx.c
+      system_stm32f2xx.c
+      1
+      0
+    
+  
+
+  
+    ::Drivers
+    0
+    0
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+    1
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+      6
+      13
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+      0
+      0
+      0
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+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+      PHY_ST802RT1.c
+      1
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+    
+    
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+      EMAC_STM32F2xx.c
+      1
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+      MCI_STM32F2xx.c
+      1
+      0
+    
+  
+
+  
+    ::File System
+    0
+    0
+    0
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+      0
+      0
+      0
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+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib
+      FS_LFN_CM3_L.lib
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+      FS_Config.c
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+      RTE\File_System\FS_Config_MC_0.h
+      FS_Config_MC_0.h
+      1
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+    
+  
+
+  
+    ::Network
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+      0
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+      C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib
+      Net_Dbg_CM3_L.lib
+      1
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+      Net_Config.c
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+      Net_Config_BSD.h
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+      0
+      0
+      0
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+      RTE\Network\Net_Config_DNS_Client.h
+      Net_Config_DNS_Client.h
+      1
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+    
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+      RTE\Network\Net_Config_ETH_0.h
+      Net_Config_ETH_0.h
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+      Net_Config_TCP.h
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+      RTE\Network\Net_Config_UDP.h
+      Net_Config_UDP.h
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+      RTE\Network\Net_Debug.c
+      Net_Debug.c
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+  
+
+  
+    ::wolfSSL
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+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+      cyassl_MDK_ARM.c
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+    
+      9
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+      time-STM32F2xx.c
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+      aes.c
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+    
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+      arc4.c
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+    
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+      asm.c
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+    
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+      asn.c
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+    
+    
+      9
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+      0
+      0
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+      blake2b.c
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+    
+    
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c
+      camellia.c
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+      coding.c
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+      compress.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+      dh.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+      ecc_fp.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+      error.c
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+    
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
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+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
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+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+      integer.c
+      1
+      0
+    
+    
+      9
+      46
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+      logging.c
+      1
+      0
+    
+    
+      9
+      47
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+      md2.c
+      1
+      0
+    
+    
+      9
+      48
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+      md4.c
+      1
+      0
+    
+    
+      9
+      49
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+      md5.c
+      1
+      0
+    
+    
+      9
+      50
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+      memory.c
+      1
+      0
+    
+    
+      9
+      51
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+      misc.c
+      1
+      0
+    
+    
+      9
+      52
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+      pwdbased.c
+      1
+      0
+    
+    
+      9
+      53
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+      rabbit.c
+      1
+      0
+    
+    
+      9
+      54
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+      random.c
+      1
+      0
+    
+    
+      9
+      55
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+      ripemd.c
+      1
+      0
+    
+    
+      9
+      56
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+      rsa.c
+      1
+      0
+    
+    
+      9
+      57
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+      sha.c
+      1
+      0
+    
+    
+      9
+      58
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+      sha256.c
+      1
+      0
+    
+    
+      9
+      59
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+      sha512.c
+      1
+      0
+    
+    
+      9
+      60
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+      tfm.c
+      1
+      0
+    
+    
+      9
+      61
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+      crl.c
+      1
+      0
+    
+    
+      9
+      62
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+      internal.c
+      1
+      0
+    
+    
+      9
+      63
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+      io.c
+      1
+      0
+    
+    
+      9
+      64
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+      keys.c
+      1
+      0
+    
+    
+      9
+      65
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+      ocsp.c
+      1
+      0
+    
+    
+      9
+      66
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+      sniffer.c
+      1
+      0
+    
+    
+      9
+      67
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+      ssl.c
+      1
+      0
+    
+    
+      9
+      68
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+      tls.c
+      1
+      0
+    
+    
+      9
+      69
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-Crypt.h
+      config-Crypt.h
+      1
+      0
+    
+    
+      9
+      70
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config-CyaSSL.h
+      config-CyaSSL.h
+      1
+      0
+    
+    
+      9
+      71
+      5
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      RTE\wolfSSL\config.h
+      config.h
+      1
+      0
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx
new file mode 100644
index 000000000..d354efbe4
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/SimpleServer.uvprojx
@@ -0,0 +1,1101 @@
+
+
+
+  2.1
+
+  
### uVision Project, (C) Keil Software

+
+  
+    
+      SimpleServer
+      0x4
+      ARM-ADS
+      
+        
+          STM32F207IG
+          STMicroelectronics
+          IRAM(0x20000000,0x20000) IROM(0x08000000,0x100000) CPUTYPE("Cortex-M3") CLOCK(120000000) ELITTLE
+          
+          
+          UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000 -FP0($$Device:STM32F207IG$Flash\STM32F2xx_1024.flm))
+          0
+          $$Device:STM32F207IG$Device\Include\stm32f2xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          $$Device:STM32F207IG$SVD\STM32F20x.svd
+          0
+          0
+          
+          
+          
+          
+          
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\Object\
+          SimpleServer
+          1
+          0
+          0
+          1
+          1
+          .\Object\
+          1
+          0
+          0
+          
+            0
+            0
+            
+            
+            0
+            0
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          
+            0
+            0
+            
+            
+            0
+            0
+          
+          0
+          
+        
+        
+          0
+          0
+          0
+          0
+          0
+          1
+          0
+          0
+          0
+          0
+          3
+          
+          
+          1
+        
+        
+          SARMCM3.DLL
+          -REMAP -MPU
+          DCM.DLL
+          -pCM3
+          SARMCM3.DLL
+          -REMAP -MPU
+          TCM.DLL
+          -pCM3
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+          
+          
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+          
+          0
+          8
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            .\STM32_SWO.ini
+            BIN\ULP2CM3.DLL
+          
+        
+        
+          
+            1
+            0
+            0
+            1
+            1
+            4100
+          
+          1
+          BIN\ULP2CM3.DLL
+          "" ()
+          
+          
+          
+          
+          0
+        
+        
+          
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            1
+            1
+            0
+            1
+            1
+            0
+            0
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            1
+            0
+            0
+            "Cortex-M3"
+            
+            0
+            0
+            0
+            1
+            1
+            0
+            0
+            0
+            0
+            0
+            8
+            0
+            0
+            0
+            3
+            3
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            1
+            0
+            0
+            0
+            0
+            1
+            0
+            
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                1
+                0x8000000
+                0x100000
+              
+              
+                1
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x0
+                0x0
+              
+              
+                0
+                0x20000000
+                0x20000
+              
+              
+                0
+                0x0
+                0x0
+              
+            
+            
+          
+          
+            1
+            4
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              HAVE_CONFIG_H  MDK_CONF_SimpleServer  CYASSL_STM32F2xx
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
+              
+              
+            
+          
+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+            
+            
+            
+          
+        
+      
+      
+        
+          Source
+          
+            
+              main.c
+              1
+              .\main.c
+            
+            
+              server.c
+              1
+              .\server.c
+            
+          
+        
+        
+          Configuration
+          
+            
+              config-CyaSSL.h
+              5
+              .\RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config-Crypt.h
+              5
+              .\RTE\wolfSSL\config-Crypt.h
+            
+          
+        
+        
+          Documentation
+          
+            
+              Abstract.txt
+              5
+              .\Abstract.txt
+            
+          
+        
+        
+          ::CMSIS
+          
+            
+              RTX_CM3.lib
+              4
+              C:\Keil5\ARM\PACK\ARM\CMSIS\3.20.3\CMSIS_RTX\Lib\ARM\RTX_CM3.lib
+            
+            
+              RTX_Conf_CM.c
+              1
+              RTE\CMSIS\RTX_Conf_CM.c
+            
+          
+        
+        
+          ::Device
+          
+            
+              DMA_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\DMA_STM32F2xx.c
+            
+            
+              GPIO_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\GPIO_STM32F2xx.c
+            
+            
+              RTE_Device.h
+              5
+              RTE\Device\STM32F207IG\RTE_Device.h
+            
+            
+              startup_stm32f2xx.s
+              2
+              RTE\Device\STM32F207IG\startup_stm32f2xx.s
+            
+            
+              system_stm32f2xx.c
+              1
+              RTE\Device\STM32F207IG\system_stm32f2xx.c
+            
+          
+        
+        
+          ::Drivers
+          
+            
+              PHY_ST802RT1.c
+              1
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Driver\PHY_ST802RT1.c
+            
+            
+              EMAC_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\EMAC_STM32F2xx.c
+            
+            
+              MCI_STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\Keil\STM32F2xx_DFP\1.0.4\RTE_Driver\MCI_STM32F2xx.c
+            
+          
+        
+        
+          ::File System
+          
+            
+              FS_LFN_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\FileSystem\Lib\ARM\FS_LFN_CM3_L.lib
+            
+            
+              FS_Config.c
+              1
+              RTE\File_System\FS_Config.c
+            
+            
+              FS_Config_MC_0.h
+              5
+              RTE\File_System\FS_Config_MC_0.h
+            
+          
+        
+        
+          ::Network
+          
+            
+              Net_Dbg_CM3_L.lib
+              4
+              C:\Keil5\ARM\PACK\Keil\MDK-Middleware\5.1.2\Network\Lib\ARM\Net_Dbg_CM3_L.lib
+            
+            
+              Net_Config.c
+              1
+              RTE\Network\Net_Config.c
+            
+            
+              Net_Config_BSD.h
+              5
+              RTE\Network\Net_Config_BSD.h
+            
+            
+              Net_Config_DNS_Client.h
+              5
+              RTE\Network\Net_Config_DNS_Client.h
+            
+            
+              Net_Config_ETH_0.h
+              5
+              RTE\Network\Net_Config_ETH_0.h
+            
+            
+              Net_Config_TCP.h
+              5
+              RTE\Network\Net_Config_TCP.h
+            
+            
+              Net_Config_UDP.h
+              5
+              RTE\Network\Net_Config_UDP.h
+            
+            
+              Net_Debug.c
+              1
+              RTE\Network\Net_Debug.c
+            
+          
+        
+        
+          ::wolfSSL
+          
+            
+              cyassl_MDK_ARM.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+            
+            
+              time-STM32F2xx.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\IDE\MDK5-ARM\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+            
+            
+              aes.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\aes.c
+            
+            
+              arc4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\arc4.c
+            
+            
+              asm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asm.c
+            
+            
+              asn.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\asn.c
+            
+            
+              blake2b.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\blake2b.c
+            
+            
+              camellia.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\camellia.c
+            
+            
+              coding.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\coding.c
+            
+            
+              compress.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\compress.c
+            
+            
+              des3.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\des3.c
+            
+            
+              dh.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dh.c
+            
+            
+              dsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\dsa.c
+            
+            
+              ecc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc.c
+            
+            
+              ecc_fp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ecc_fp.c
+            
+            
+              error.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\error.c
+            
+            
+              hc128.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hc128.c
+            
+            
+              hmac.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\hmac.c
+            
+            
+              integer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\integer.c
+            
+            
+              logging.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\logging.c
+            
+            
+              md2.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md2.c
+            
+            
+              md4.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md4.c
+            
+            
+              md5.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\md5.c
+            
+            
+              memory.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\memory.c
+            
+            
+              misc.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\misc.c
+            
+            
+              pwdbased.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\pwdbased.c
+            
+            
+              rabbit.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rabbit.c
+            
+            
+              random.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\random.c
+            
+            
+              ripemd.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\ripemd.c
+            
+            
+              rsa.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\rsa.c
+            
+            
+              sha.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha.c
+            
+            
+              sha256.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha256.c
+            
+            
+              sha512.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\sha512.c
+            
+            
+              tfm.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\ctaocrypt\src\tfm.c
+            
+            
+              crl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\crl.c
+            
+            
+              internal.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\internal.c
+            
+            
+              io.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\io.c
+            
+            
+              keys.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\keys.c
+            
+            
+              ocsp.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ocsp.c
+            
+            
+              sniffer.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\sniffer.c
+            
+            
+              ssl.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\ssl.c
+            
+            
+              tls.c
+              1
+              C:\Keil5\ARM\PACK\wolfSSL\CyaSSL\2.8.0\cyassl\src\tls.c
+            
+            
+              config-Crypt.h
+              5
+              RTE\wolfSSL\config-Crypt.h
+            
+            
+              config-CyaSSL.h
+              5
+              RTE\wolfSSL\config-CyaSSL.h
+            
+            
+              config.h
+              5
+              RTE\wolfSSL\config.h
+            
+          
+        
+      
+    
+  
+
+  
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+      
+        
+        
+          
+        
+      
+    
+    
+      
+        RTE\CMSIS\RTX_Conf_CM.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\RTE_Device.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\startup_stm32f2xx.s
+        
+        
+        
+          
+        
+      
+      
+        RTE\Device\STM32F207IG\system_stm32f2xx.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\File_System\FS_Config_MC_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_BSD.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_DNS_Client.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_ETH_0.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_TCP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Config_UDP.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\Network\Net_Debug.c
+        
+        
+        
+          
+        
+      
+      
+        RTE\Other\config-Crypt.h
+        
+        
+        
+      
+      
+        RTE\Other\config-CyaSSL.h
+        
+        
+        
+      
+      
+        RTE\Other\config-RTX-TCP-FS.h
+        
+        
+        
+      
+      
+        RTE\Other\config.h
+        
+        
+        
+      
+      
+        RTE\wolfSSL\config-Crypt.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config-CyaSSL.h
+        
+        
+        
+          
+        
+      
+      
+        RTE\wolfSSL\config.h
+        
+        
+        
+          
+        
+      
+    
+  
+
+
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/main.c b/IDE/MDK5-ARM/Projects/SimpleServer/main.c
new file mode 100644
index 000000000..d42ef2f88
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/main.c
@@ -0,0 +1,104 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+#include 
+
+#include "cmsis_os.h"
+#include "rl_fs.h" 
+#include "rl_net.h" 
+#include 
+#include "cyassl_MDK_ARM.h"
+#include 
+
+/*-----------------------------------------------------------------------------
+ *        Initialize a Flash Memory Card
+ *----------------------------------------------------------------------------*/
+static void init_filesystem (void) {
+    int32_t retv;
+
+    retv = finit ("M0:");
+    if (retv == 0) {
+        retv = fmount ("M0:");
+        if (retv == 0) {
+            printf ("Drive M0 ready!\n");
+        }
+        else {
+          printf ("Drive M0 mount failed!\n");
+        }
+    } else {
+        printf ("Drive M0 initialization failed!\n");
+    }
+}
+
+/*-----------------------------------------------------------------------------
+ *        TCP/IP tasks
+ *----------------------------------------------------------------------------*/
+void tcp_poll (void const *arg)
+{
+    CYASSL_MSG("TCP polling started.\n") ;
+    while (1) {
+        net_main ();
+        osDelay(1) ;
+    }
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+} func_args;
+
+extern void server_test(func_args * args) ;
+extern void init_time(void) ;
+
+    osThreadDef (tcp_poll, osPriorityHigh , 1, 0) ;
+/*-----------------------------------------------------------------------------
+ *       mian entry 
+ *----------------------------------------------------------------------------*/
+int myoptind = 0;
+char* myoptarg = NULL;
+
+int main() 
+{
+    static char *argv[]    = {  "client",   ""} ;
+    static func_args args  = {  2, argv } ; 
+        
+    init_time() ;
+    init_filesystem ();
+    net_initialize() ;
+    osThreadCreate (osThread (tcp_poll), NULL); 
+    osDelay(10000) ;  /* wait for DHCP */
+    #if defined(DEBUG_CYASSL)
+         printf("Turning ON Debug message\n") ;
+         CyaSSL_Debugging_ON() ;
+    #endif
+        
+    printf("Simple Server: Started\n") ;
+    while(1) {
+       server_test(&args) ;
+       printf("Enter any key to iterate.\n") ;
+       getchar() ;
+   }
+}
diff --git a/IDE/MDK5-ARM/Projects/SimpleServer/server.c b/IDE/MDK5-ARM/Projects/SimpleServer/server.c
new file mode 100644
index 000000000..de53738e8
--- /dev/null
+++ b/IDE/MDK5-ARM/Projects/SimpleServer/server.c
@@ -0,0 +1,560 @@
+/* server.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include 
+
+#if !defined(CYASSL_TRACK_MEMORY) && !defined(NO_MAIN_DRIVER)
+    /* in case memory tracker wants stats */
+    #define CYASSL_TRACK_MEMORY
+#endif
+
+#if defined(CYASSL_MDK_ARM)
+    #include 
+    #include 
+    
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+        #include "rl_fs.h" 
+        #include "rl_net.h" 
+    #else
+        #include "rtl.h"
+    #endif
+    
+    #include "cyassl_MDK_ARM.h"
+#endif
+
+#include 
+#include 
+
+#include "examples/server/server.h"
+
+
+#ifdef CYASSL_CALLBACKS
+    int srvHandShakeCB(HandShakeInfo*);
+    int srvTimeoutCB(TimeoutInfo*);
+    Timeval srvTo;
+#endif
+
+static void NonBlockingSSL_Accept(SSL* ssl)
+{
+#ifndef CYASSL_CALLBACKS
+    int ret = SSL_accept(ssl);
+#else
+    int ret = CyaSSL_accept_ex(ssl, srvHandShakeCB, srvTimeoutCB, srvTo);
+#endif
+    int error = SSL_get_error(ssl, 0);
+    SOCKET_T sockfd = (SOCKET_T)CyaSSL_get_fd(ssl);
+    int select_ret;
+
+    while (ret != SSL_SUCCESS && (error == SSL_ERROR_WANT_READ ||
+                                  error == SSL_ERROR_WANT_WRITE)) {
+        int currTimeout = 1;
+
+        if (error == SSL_ERROR_WANT_READ)
+            printf("... server would read block\n");
+        else
+            printf("... server would write block\n");
+
+#ifdef CYASSL_DTLS
+        currTimeout = CyaSSL_dtls_get_current_timeout(ssl);
+#endif
+        select_ret = tcp_select(sockfd, currTimeout);
+
+        if ((select_ret == TEST_RECV_READY) ||
+                                        (select_ret == TEST_ERROR_READY)) {
+            #ifndef CYASSL_CALLBACKS
+                ret = SSL_accept(ssl);
+            #else
+                ret = CyaSSL_accept_ex(ssl,
+                                    srvHandShakeCB, srvTimeoutCB, srvTo);
+            #endif
+            error = SSL_get_error(ssl, 0);
+        }
+        else if (select_ret == TEST_TIMEOUT && !CyaSSL_dtls(ssl)) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#ifdef CYASSL_DTLS
+        else if (select_ret == TEST_TIMEOUT && CyaSSL_dtls(ssl) &&
+                                            CyaSSL_dtls_got_timeout(ssl) >= 0) {
+            error = SSL_ERROR_WANT_READ;
+        }
+#endif
+        else {
+            error = SSL_FATAL_ERROR;
+        }
+    }
+    if (ret != SSL_SUCCESS)
+        err_sys("SSL_accept failed");
+}
+
+
+static void Usage(void)
+{
+    printf("server "    LIBCYASSL_VERSION_STRING
+           " NOTE: All files relative to CyaSSL home dir\n");
+    printf("-?          Help, print this usage\n");
+    printf("-p     Port to listen on, not 0, default %d\n", yasslPort);
+    printf("-v     SSL version [0-3], SSLv3(0) - TLS1.2(3)), default %d\n",
+                                 SERVER_DEFAULT_VERSION);
+    printf("-l     Cipher list\n");
+    printf("-c    Certificate file,           default %s\n", svrCert);
+    printf("-k    Key file,                   default %s\n", svrKey);
+    printf("-A    Certificate Authority file, default %s\n", cliCert);
+    printf("-d          Disable client cert check\n");
+    printf("-b          Bind to any interface instead of localhost only\n");
+    printf("-s          Use pre Shared keys\n");
+    printf("-t          Track CyaSSL memory use\n");
+    printf("-u          Use UDP DTLS,"
+           " add -v 2 for DTLSv1 (default), -v 3 for DTLSv1.2\n");
+    printf("-f          Fewer packets/group messages\n");
+    printf("-N          Use Non-blocking sockets\n");
+    printf("-S     Use Host Name Indication\n");
+}
+
+#ifdef CYASSL_MDK_SHELL
+#define exit(code) return(code)
+#endif
+
+
+THREAD_RETURN CYASSL_THREAD server_test(void* args)
+{
+    SOCKET_T sockfd   = 0;
+    SOCKET_T clientfd = 0;
+
+    SSL_METHOD* method = 0;
+    SSL_CTX*    ctx    = 0;
+    SSL*        ssl    = 0;
+
+    char   msg[] = "I hear you fa shizzle!";
+    char   input[80];
+    int    idx;
+    int    ch;
+    int    version = SERVER_DEFAULT_VERSION;
+    int    doCliCertCheck = 1;
+    int    useAnyAddr = 0;
+    int    port = yasslPort;
+    int    usePsk = 0;
+    int    doDTLS = 0;
+    int    useNtruKey   = 0;
+    int    nonBlocking  = 0;
+    int    trackMemory  = 0;
+    int    fewerPackets = 0;
+    char*  cipherList = NULL;
+    char*  verifyCert = (char*)cliCert;
+    char*  ourCert    = (char*)svrCert;
+    char*  ourKey     = (char*)svrKey;
+    int    argc = ((func_args*)args)->argc;
+    char** argv = ((func_args*)args)->argv;
+
+#ifdef HAVE_SNI
+    char*  sniHostName = NULL;
+#endif
+
+    ((func_args*)args)->return_code = -1; /* error state */
+
+#ifdef NO_RSA
+    verifyCert = (char*)cliEccCert;
+    ourCert    = (char*)eccCert;
+    ourKey     = (char*)eccKey;
+#endif
+    (void)trackMemory;
+
+    while ((ch = mygetopt(argc, argv, "?dbstnNufp:v:l:A:c:k:S:")) != -1) {
+        switch (ch) {
+            case '?' :
+                Usage();
+                exit(EXIT_SUCCESS);
+
+            case 'd' :
+                doCliCertCheck = 0;
+                break;
+
+            case 'b' :
+                useAnyAddr = 1;
+                break;
+
+            case 's' :
+                usePsk = 1;
+                break;
+
+            case 't' :
+            #ifdef USE_CYASSL_MEMORY
+                trackMemory = 1;
+            #endif
+                break;
+
+            case 'n' :
+                useNtruKey = 1;
+                break;
+
+            case 'u' :
+                doDTLS  = 1;
+                break;
+
+            case 'f' :
+                fewerPackets = 1;
+                break;
+
+            case 'p' :
+                port = atoi(myoptarg);
+                #if !defined(NO_MAIN_DRIVER) || defined(USE_WINDOWS_API)
+                    if (port == 0)
+                        err_sys("port number cannot be 0");
+                #endif
+                break;
+
+            case 'v' :
+                version = atoi(myoptarg);
+                if (version < 0 || version > 3) {
+                    Usage();
+                    exit(MY_EX_USAGE);
+                }
+                break;
+
+            case 'l' :
+                cipherList = myoptarg;
+                break;
+
+            case 'A' :
+                verifyCert = myoptarg;
+                break;
+
+            case 'c' :
+                ourCert = myoptarg;
+                break;
+
+            case 'k' :
+                ourKey = myoptarg;
+                break;
+
+            case 'N':
+                nonBlocking = 1;
+                break;
+
+            case 'S' :
+                #ifdef HAVE_SNI
+                    sniHostName = myoptarg;
+                #endif
+                break;
+
+            default:
+                Usage();
+                exit(MY_EX_USAGE);
+        }
+    }
+
+    myoptind = 0;      /* reset for test cases */
+
+    /* sort out DTLS versus TLS versions */
+    if (version == CLIENT_INVALID_VERSION) {
+        if (doDTLS)
+            version = CLIENT_DTLS_DEFAULT_VERSION;
+        else
+            version = CLIENT_DEFAULT_VERSION;
+    }
+    else {
+        if (doDTLS) {
+            if (version == 3)
+                version = -2;
+            else
+                version = -1;
+        }
+    }
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        InitMemoryTracker(); 
+#endif
+
+    switch (version) {
+#ifndef NO_OLD_TLS
+        case 0:
+            method = SSLv3_server_method();
+            break;
+
+    #ifndef NO_TLS
+        case 1:
+            method = TLSv1_server_method();
+            break;
+
+
+        case 2:
+            method = TLSv1_1_server_method();
+            break;
+
+        #endif
+#endif
+
+#ifndef NO_TLS
+        case 3:
+            method = TLSv1_2_server_method();
+            break;
+#endif
+                
+#ifdef CYASSL_DTLS
+        case -1:
+            method = DTLSv1_server_method();
+            break;
+
+        case -2:
+            method = DTLSv1_2_server_method();
+            break;
+#endif
+
+        default:
+            err_sys("Bad SSL version");
+    }
+
+    if (method == NULL)
+        err_sys("unable to get method");
+
+    ctx = SSL_CTX_new(method);
+    if (ctx == NULL)
+        err_sys("unable to get ctx");
+
+    if (cipherList)
+        if (SSL_CTX_set_cipher_list(ctx, cipherList) != SSL_SUCCESS)
+            err_sys("server can't set cipher list 1");
+
+#ifdef CYASSL_LEANPSK
+    usePsk = 1;
+#endif
+
+#if defined(NO_RSA) && !defined(HAVE_ECC)
+    usePsk = 1;
+#endif
+
+    if (fewerPackets)
+        CyaSSL_CTX_set_group_messages(ctx);
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!usePsk) {
+        if (SSL_CTX_use_certificate_file(ctx, ourCert, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                    " CyaSSL home dir");
+    }
+#endif
+
+#ifdef HAVE_NTRU
+    if (useNtruKey) {
+        if (CyaSSL_CTX_use_NTRUPrivateKey_file(ctx, ourKey)
+                                               != SSL_SUCCESS)
+            err_sys("can't load ntru key file, "
+                    "Please run from CyaSSL home dir");
+    }
+#endif
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    if (!useNtruKey && !usePsk) {
+        if (SSL_CTX_use_PrivateKey_file(ctx, ourKey, SSL_FILETYPE_PEM)
+                                         != SSL_SUCCESS)
+            err_sys("can't load server cert file, check file and run from"
+                " CyaSSL home dir");
+    }
+#endif
+
+    if (usePsk) {
+#ifndef NO_PSK
+        SSL_CTX_set_psk_server_callback(ctx, my_psk_server_cb);
+        SSL_CTX_use_psk_identity_hint(ctx, "cyassl server");
+        if (cipherList == NULL) {
+            const char *defaultCipherList;
+            #ifdef HAVE_NULL_CIPHER
+                defaultCipherList = "PSK-NULL-SHA256";
+            #else
+                defaultCipherList = "PSK-AES128-CBC-SHA256";
+            #endif
+            if (SSL_CTX_set_cipher_list(ctx, defaultCipherList) != SSL_SUCCESS)
+                err_sys("server can't set cipher list 2");
+        }
+#endif
+    }
+
+#if !defined(NO_FILESYSTEM) && !defined(NO_CERTS)
+    /* if not using PSK, verify peer with certs */
+    if (doCliCertCheck && usePsk == 0) {
+        SSL_CTX_set_verify(ctx, SSL_VERIFY_PEER |
+                                SSL_VERIFY_FAIL_IF_NO_PEER_CERT,0);
+        if (SSL_CTX_load_verify_locations(ctx, verifyCert, 0) != SSL_SUCCESS)
+            err_sys("can't load ca file, Please run from CyaSSL home dir");
+    }
+#endif
+
+#ifdef OPENSSL_EXTRA
+    SSL_CTX_set_default_passwd_cb(ctx, PasswordCallBack);
+#endif
+
+#if defined(CYASSL_SNIFFER) && !defined(HAVE_NTRU) && !defined(HAVE_ECC)
+    /* don't use EDH, can't sniff tmp keys */
+    if (cipherList == NULL) {
+        if (SSL_CTX_set_cipher_list(ctx, "AES256-SHA256") != SSL_SUCCESS)
+            err_sys("server can't set cipher list 3");
+    }
+#endif
+
+#ifdef HAVE_SNI
+    if (sniHostName) {
+        if (CyaSSL_CTX_UseSNI(ctx, CYASSL_SNI_HOST_NAME, sniHostName,
+                                                          XSTRLEN(sniHostName)))
+            err_sys("UseSNI failed");
+        else
+            CyaSSL_CTX_SNI_SetOptions(ctx, CYASSL_SNI_HOST_NAME,
+                                                  CYASSL_SNI_ABORT_ON_MISMATCH);
+    }
+#endif
+
+    ssl = SSL_new(ctx);
+    if (ssl == NULL)
+        err_sys("unable to get SSL");
+    CyaSSL_set_quiet_shutdown(ssl, 1) ;
+#ifdef HAVE_CRL
+    CyaSSL_EnableCRL(ssl, 0);
+    CyaSSL_LoadCRL(ssl, crlPemDir, SSL_FILETYPE_PEM, CYASSL_CRL_MONITOR |
+                                                     CYASSL_CRL_START_MON);
+    CyaSSL_SetCRL_Cb(ssl, CRL_CallBack);
+#endif
+        osDelay(5000) ;
+    tcp_accept(&sockfd, &clientfd, (func_args*)args, port, useAnyAddr, doDTLS);
+    if (!doDTLS) 
+        CloseSocket(sockfd);
+
+    SSL_set_fd(ssl, clientfd);
+    if (usePsk == 0) {
+        #if !defined(NO_FILESYSTEM) && defined(OPENSSL_EXTRA)
+            CyaSSL_SetTmpDH_file(ssl, dhParam, SSL_FILETYPE_PEM);
+        #elif !defined(NO_CERTS)
+            SetDH(ssl);  /* repick suites with DHE, higher priority than PSK */
+        #endif
+    }
+        osDelay(5000) ;
+#ifndef CYASSL_CALLBACKS
+    if (nonBlocking) {
+        CyaSSL_set_using_nonblock(ssl, 1);
+        tcp_set_nonblocking(&clientfd);
+        NonBlockingSSL_Accept(ssl);
+    } else if (SSL_accept(ssl) != SSL_SUCCESS) {
+        int err = SSL_get_error(ssl, 0);
+        char buffer[80];
+        printf("error = %d, %s\n", err, ERR_error_string(err, buffer));
+        err_sys("SSL_accept failed");
+    }
+#else
+    NonBlockingSSL_Accept(ssl);
+#endif
+    showPeer(ssl);
+        osDelay(5000) ;
+    idx = SSL_read(ssl, input, sizeof(input)-1);
+    if (idx > 0) {
+        input[idx] = 0;
+        printf("Client message: %s\n", input);
+
+    }
+    else if (idx < 0) {
+        int readErr = SSL_get_error(ssl, 0);
+        if (readErr != SSL_ERROR_WANT_READ)
+            err_sys("SSL_read failed");
+    }
+
+    if (SSL_write(ssl, msg, sizeof(msg)) != sizeof(msg))
+        err_sys("SSL_write failed");
+        
+    SSL_shutdown(ssl);
+    SSL_free(ssl);
+    SSL_CTX_free(ctx);
+    
+    CloseSocket(clientfd);
+    ((func_args*)args)->return_code = 0;
+
+#ifdef USE_CYASSL_MEMORY
+    if (trackMemory)
+        ShowMemoryTracker();
+#endif /* USE_CYASSL_MEMORY */
+
+    return 0;
+}
+
+
+/* so overall tests can pull in test function */
+#ifndef NO_MAIN_DRIVER
+
+    int main(int argc, char** argv)
+    {
+        func_args args;
+
+#ifdef HAVE_CAVIUM
+        int ret = OpenNitroxDevice(CAVIUM_DIRECT, CAVIUM_DEV_ID);
+        if (ret != 0)
+            err_sys("Cavium OpenNitroxDevice failed");
+#endif /* HAVE_CAVIUM */
+
+        StartTCP();
+
+        args.argc = argc;
+        args.argv = argv;
+
+        CyaSSL_Init();
+#if defined(DEBUG_CYASSL) && !defined(CYASSL_MDK_SHELL)
+        CyaSSL_Debugging_ON();
+#endif
+        if (CurrentDir("server") || CurrentDir("build"))
+            ChangeDirBack(2);
+   
+#ifdef HAVE_STACK_SIZE
+        StackSizeCheck(&args, server_test);
+#else 
+        server_test(&args);
+#endif
+        CyaSSL_Cleanup();
+
+#ifdef HAVE_CAVIUM
+        CspShutdown(CAVIUM_DEV_ID);
+#endif
+        return args.return_code;
+    }
+
+    int myoptind = 0;
+    char* myoptarg = NULL;
+
+#endif /* NO_MAIN_DRIVER */
+
+
+#ifdef CYASSL_CALLBACKS
+
+    int srvHandShakeCB(HandShakeInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+
+    int srvTimeoutCB(TimeoutInfo* info)
+    {
+        (void)info;
+        return 0;
+    }
+
+#endif
+
diff --git a/IDE/MDK5-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c b/IDE/MDK5-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c
new file mode 100644
index 000000000..37154d136
--- /dev/null
+++ b/IDE/MDK5-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c
@@ -0,0 +1,299 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+ 
+#ifdef HAVE_CONFIG_H
+    #include 
+#endif
+
+#include "time.h"
+
+#define PERIPH_BASE           ((uint32_t)0x40000000) 
+/*-----------------------------------------------------------------------------
+ *        initialize RTC 
+ *----------------------------------------------------------------------------*/
+#include "stm32f2xx.h"
+
+#define assert_param(a)
+
+#define RTC_RSF_MASK         ((uint32_t)0xFFFFFF5F)
+#define SYNCHRO_TIMEOUT      ((uint32_t) 0x00008000)
+#define Bcd2ToByte(v) \
+   ((((uint8_t)(v & (uint8_t)0xF0) >> (uint8_t)0x4) * 10) + (v & (uint8_t)0x0F))
+#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
+#define RTC_TR_MNT           ((uint32_t)0x00007000)
+#define RTC_TR_MNU           ((uint32_t)0x00000F00)
+
+#define PWR_OFFSET           (PWR_BASE - PERIPH_BASE)
+#define CR_OFFSET            (PWR_OFFSET + 0x00)
+#define DBP_BitNumber        0x08
+#define CR_DBP_BB     (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+#define RTC_INIT_MASK        ((uint32_t)0xFFFFFFFF)  
+#define INITMODE_TIMEOUT     ((uint32_t) 0x00010000)
+
+static void init_RTC() 
+{
+    __IO uint32_t initcounter =  0x00 ;
+    uint32_t initstatus = 0x00;    /* Enable the PWR clock : RCC_APB1Periph_PWR  */       
+    ((uint32_t *)RCC)[0x10] |= ((uint32_t)0x10000000) ;
+    
+    /* Allow access to RTC */
+    *(__IO uint32_t *) CR_DBP_BB = ENABLE ;
+      /* RCC_LSEConfig(RCC_LSE_ON) */
+    *(__IO uint8_t *) (RCC_BASE + 0x70) =  ((uint8_t)0x00);
+    /* Reset LSEBYP bit */
+    *(__IO uint8_t *) (RCC_BASE + 0x70) =  ((uint8_t)0x00);
+    *(__IO uint8_t *) (RCC_BASE + 0x70) =  ((uint8_t)0x01);
+    /* Wait till LSE is ready */  
+        while((RCC->BDCR << 0x2) == 0x0) { }
+      /* Select the RTC clock source: RCC_RTCCLKSource_LSE */
+    ((RCC_TypeDef *)RCC)->BDCR |= (uint32_t)0x00000100;
+
+    /* Enable the RTC Clock */
+    *(__IO uint32_t *)  (PERIPH_BB_BASE + (((RCC_BASE - PERIPH_BASE)+ 0x70) * 32) + (0x0F* 4)) = (uint32_t)ENABLE;
+
+    *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 
+    RTC->ISR = (uint32_t) RTC_INIT_MASK;
+    do {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));   /* Clear RTC CR FMT Bit */
+    /* Set RTC_CR register */
+    RTC->CR |=   ((uint32_t)0x00000000) ;   /* RTC_HourFormat_24 */
+
+    /* Configure the RTC PRER */
+    RTC->PRER = 0x7f ; 
+    RTC->PRER |= (uint32_t)(0xff << 16);
+
+    /* Exit Initialization mode */
+    RTC->ISR &= (uint32_t)~RTC_ISR_INIT; 
+
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF; 
+}
+
+/*-----------------------------------------------------------------------------
+ *        initialize TIM
+ *----------------------------------------------------------------------------*/
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+
+static void init_TIM()
+{
+      uint16_t tmpcr1 = 0;
+
+    ((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ;
+
+    tmpcr1 = TIM2->CR1 ;
+    tmpcr1 &=   (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) )); 
+                                     /* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */
+    tmpcr1 |= (uint16_t)0x0000  ;    /* CR1 |= TIM_CounterMode_Up */
+    TIM2->CR1=  tmpcr1 ;
+
+    TIM2->ARR = 0xffffffff ;         /* ARR= TIM_Period */
+    TIM2->PSC = 60 ;                 /* PSC = TIM_Prescaler */
+    TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */      
+
+    *(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ; 
+                                     /* TIM_Cmd(TIM2, ENABLE) ; */
+}
+
+void init_time(void) {
+      init_RTC() ;
+    init_TIM() ;
+}
+
+static void GetTime(uint8_t *h, uint8_t *m, uint8_t *s)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+    *h = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16));
+    *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8));
+    *s = (uint8_t)Bcd2ToByte((tmpreg & (RTC_TR_ST | RTC_TR_SU))); 
+}
+
+static uint32_t ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  while (Value >= 10)  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+static void SetTime(uint8_t h, uint8_t m, uint8_t s)
+{
+     __IO uint32_t synchrocounter = 0;
+     uint32_t synchrostatus = 0x00;
+     __IO uint32_t initcounter = 0;
+     uint32_t initstatus = 0x00;
+     uint32_t tmpreg ;  
+
+     tmpreg = ((ByteToBcd2(h) << 16) | (ByteToBcd2(m) << 8) |  ByteToBcd2(s)) ;
+     /* Disable the write protection for RTC registers */
+     RTC->WPR = 0xCA;
+     RTC->WPR = 0x53;
+     RTC->ISR &= (uint32_t)~RTC_ISR_INIT; 
+
+     RTC->ISR = (uint32_t)RTC_INIT_MASK;
+
+     /* Wait till RTC is in INIT state and if Time out is reached exit */
+     do {
+         initstatus = RTC->ISR & RTC_ISR_INITF;
+         initcounter++;  
+     } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+     RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+    
+     RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+     /* Wait the registers to be synchronised */
+     do {
+         synchrostatus = RTC->ISR & RTC_ISR_RSF;
+         synchrocounter++;  
+     } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+     RTC->WPR = 0xFF;
+}
+
+static void GetDate(uint8_t *y, uint8_t *m, uint8_t *d)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = (uint32_t)(RTC->DR & RTC_TR_RESERVED_MASK); 
+    *y = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_YT|RTC_DR_YU)) >>16));
+    *m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_MT|RTC_DR_MU)) >> 8));
+    *d = (uint8_t)Bcd2ToByte((uint8_t)(tmpreg & (RTC_DR_DT |RTC_DR_DU)));
+}
+
+static void SetDate(uint8_t y, uint8_t m, uint8_t d)
+{
+     __IO uint32_t synchrocounter = 0;
+     uint32_t synchrostatus = 0x00;
+     __IO uint32_t initcounter = 0;
+     uint32_t initstatus = 0x00;
+     uint32_t tmpreg = 0 ;  
+    
+    tmpreg = ((ByteToBcd2(y) << 16) | (ByteToBcd2(m) << 8) |  ByteToBcd2(d)) ;
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;
+    RTC->ISR &= (uint32_t)~RTC_ISR_INIT; 
+
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do {
+        initstatus = RTC->ISR & RTC_ISR_INITF;
+        initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+
+    RTC->DR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+    /* Wait the registers to be synchronised */
+    do {
+        synchrostatus = RTC->ISR & RTC_ISR_RSF;
+        synchrocounter++;  
+    } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+
+    RTC->WPR = 0xFF;
+}
+
+
+#include 
+void CYASSL_MSG(const char *msg) ;
+
+struct tm *Cyassl_MDK_gmtime(const time_t *c) 
+{ 
+    uint8_t h, m, s ;
+    uint8_t y, mo, d ;
+    static struct tm date ; 
+
+    GetTime(&h, &m, &s) ;
+    GetDate(&y, &mo, &d) ;
+
+    date.tm_year = y + 100 ;
+    date.tm_mon = mo - 1 ;
+    date.tm_mday = d ;
+    date.tm_hour = h ;
+    date.tm_min = m ;
+    date.tm_sec = s ;
+
+    #if defined(DEBUG_CYASSL) 
+    {
+        char msg[100] ;
+        sprintf(msg, 
+        "Debug::Cyassl_KEIL_gmtime(DATE=/%2d/%02d/%04d TIME=%02d:%02d:%02d)\n",
+                d,  mo,  y+2000, h,  m,  s) ; 
+        CYASSL_MSG(msg) ;   
+    }
+    #endif
+    
+    return(&date) ;
+}
+
+double current_time() 
+{
+      return ((double)TIM2->CNT/1000000.0) ;
+}
+
+typedef struct func_args {
+    int    argc;
+    char** argv;
+    int    return_code;
+} func_args;
+
+void time_main(void *args) 
+{
+    char * datetime ;
+    uint8_t h, m, s ;
+    uint8_t y, mo, d ;
+    
+    if( args == NULL || ((func_args *)args)->argc == 1) {
+        GetTime(&h, &m, &s) ;
+        GetDate(&y, &mo, &d) ;
+        printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n", 
+             mo, d, y+2000, h, m, s) ;              
+    } else if(((func_args *)args)->argc == 3 && 
+              ((func_args *)args)->argv[1][0] == '-' && 
+              ((func_args *)args)->argv[1][1] == 'd' ) {
+        datetime = ((func_args *)args)->argv[2];
+        sscanf(datetime, "%d/%d/%d", (int *)&mo, (int *)&d, (int *) &y) ;
+        SetDate(y-2000, mo, d) ;        
+    } else if(((func_args *)args)->argc == 3 && 
+              ((func_args *)args)->argv[1][0] == '-' && 
+              ((func_args *)args)->argv[1][1] == 't' ) {
+        datetime = ((func_args *)args)->argv[2];
+        sscanf(datetime, "%d:%d:%d",            
+            (int *)&h, (int *)&m, (int *)&s) ;
+        SetTime(h, m, s) ;
+    } else printf("Invalid argument\n") ; 
+}
+
+
+/*******************************************************************
+      time()                                                                      
+********************************************************************/
+time_t time(time_t * t) { return 0 ; }
diff --git a/IDE/MDK5-ARM/wolfSSL.CyaSSL.pdsc b/IDE/MDK5-ARM/wolfSSL.CyaSSL.pdsc
new file mode 100644
index 000000000..25a3dd8bb
--- /dev/null
+++ b/IDE/MDK5-ARM/wolfSSL.CyaSSL.pdsc
@@ -0,0 +1,281 @@
+
+    
+
+  CyaSSL                                                   
+  Light weight SSL/TLS and Crypt Library for Embedded Systems  
+  wolfSSL                                                  
+  http://www.wolfSSL.com/files/ide                              
+  cyassl\IDE\MDK5-ARM\Docs\CyaSSL-Licnese.txt
+  
+    wolfSSL: SSL/TLS and Crypt Library
+    CyaSSL: SSL/TLS Library
+    wolfCrypt: Crypt Library
+  
+
+                                                                  
+                                                   
+      Oct/7/2013, Initial release of CyaSSL pack
+    
+  
+  
+                                                                   
+    CyaSSL
+    wolfSSL
+    Security
+    Crypt
+    Cipher
+    SSL
+    TLS
+  
+
+  
+   
+    
+    
+      
+      The condition is true if the package is used with a Cortex-Mx based device
+      
+      
+      
+      
+    
+    
+      CMSIS Core with Cortex-M processor
+      
+      
+    
+    
+    
+      CMSIS Core with RTOS for Cortex-M processor
+      
+      
+      
+    
+    
+      File System on Memory Card
+      
+      
+    
+    
+      Network UDP/TCP and CORE component
+      
+      
+      
+      
+      
+    
+
+    
+      
+            
+          
+    
+    
+        
+          
+      
+      
+      
+    
+  
+
+  
+    
+      wolfSSL: SSL/TLS and Crypt Library
+      cyassl\IDE\MDK5-ARM\Docs\CyaSSLManual-TableofContents.htm
+      
+        CyaSSL, Light weight SSL/TLS library
+        
+        
+        
+          
+          
+          
+
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+      
+      
+        wolfCrypt Core, Light weight Crypt/Cipher Library
+        
+        
+        
+          
+          
+          
+
+          
+          
+
+          
+
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          
+        
+      
+      
+        Dummy file for Crypt alone use
+        
+        
+        
+          
+        
+      
+      
+        Device depend Timer functions
+        
+        
+        
+          
+        
+      
+    
+  
+
+  
+    
+      CyaSSL Demo, SSL/TLS Server/Client Examples, Simple test suites, Benchmark
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        SSL
+        TLS
+      
+    
+    
+      wolfCrypt Simple Test Suite
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        Crypt
+        Cipher
+      
+    
+    
+      wolfCrypt Benchmark Suite
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        Crypt
+        Cipher
+      
+    
+    
+      CyaSSL Simple Client Example
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        Crypt
+        Cipher
+      
+    
+    
+      CyaSSL Simple Server Example
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        Crypt
+        Cipher
+      
+    
+    
+      CyaSSL Echo Client Example
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        Crypt
+        Cipher
+      
+    
+    
+      CyaSSL Echo Server Example
+      
+      
+        
+      
+      
+        
+        Middleware
+        Security
+        Crypt
+        Cipher
+      
+    
+
+
diff --git a/ctaocrypt/benchmark/benchmark.c b/ctaocrypt/benchmark/benchmark.c
index 7b36dab51..f219cd727 100644
--- a/ctaocrypt/benchmark/benchmark.c
+++ b/ctaocrypt/benchmark/benchmark.c
@@ -51,6 +51,12 @@
     #include "cavium_common.h"
     #include "cavium_ioctl.h"
 #endif
+
+#if defined(CYASSL_MDK_ARM)
+    extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ;
+    #define fopen CyaSSL_fopen
+#endif
+
 #if defined(USE_CERT_BUFFERS_1024) || defined(USE_CERT_BUFFERS_2048)
     /* include test cert and key buffers for use with NO_FILESYSTEM */
     #if defined(CYASSL_MDK_ARM)
@@ -215,11 +221,15 @@ int benchmark_test(void *args)
 #ifdef BENCH_EMBEDDED
 const int numBlocks = 25;       /* how many kB/megs to test (en/de)cryption */
 const char blockType[] = "kB";  /* used in printf output */
-const int times     = 1;        /* public key iterations */
+const int times      = 1;        /* public key iterations */
+const int genTimes   = 5;
+const int agreeTimes = 5;
 #else
 const int numBlocks = 5;
 const char blockType[] = "megs";
-const int times     = 100;
+const int times      = 100;
+const int genTimes   = 100;
+const int agreeTimes = 100;
 #endif
 
 const byte key[] = 
@@ -873,7 +883,6 @@ void bench_rsaKeyGen(void)
     RsaKey genKey;
     double start, total, each, milliEach;
     int    i;
-    const int genTimes = 5;
   
     /* 1024 bit */ 
     start = current_time(1);
@@ -914,7 +923,6 @@ void bench_eccKeyGen(void)
     ecc_key genKey;
     double start, total, each, milliEach;
     int    i, ret;
-    const int genTimes = 100;
   
     ret = InitRng(&rng);
     if (ret < 0) {
@@ -943,7 +951,6 @@ void bench_eccKeyAgree(void)
     ecc_key genKey, genKey2;
     double start, total, each, milliEach;
     int    i, ret;
-    const int agreeTimes = 100;
     byte   shared[1024];
     byte   sig[1024];
     byte   digest[32];
@@ -1090,7 +1097,7 @@ void bench_eccKeyAgree(void)
     {
         struct timeval tv;
 
-        (void) reset;
+        (void)reset;
 
         gettimeofday(&tv, 0);
 
diff --git a/ctaocrypt/src/asn.c b/ctaocrypt/src/asn.c
index 87be7b2e5..65ff0a660 100644
--- a/ctaocrypt/src/asn.c
+++ b/ctaocrypt/src/asn.c
@@ -106,7 +106,11 @@
     #define XGMTIME(c) gmtime((c))
     #define XVALIDATE_DATE(d, f, t) ValidateDate((d), (f), (t))
 #elif defined(CYASSL_MDK_ARM)
-    #include 
+    #if defined(CYASSL_MDK5)
+        #include "cmsis_os.h"
+    #else
+        #include 
+    #endif
     #undef RNG
     #include "cyassl_MDK_ARM.h"
     #undef RNG
diff --git a/ctaocrypt/src/memory.c b/ctaocrypt/src/memory.c
index 3638e081a..1058e6bc1 100644
--- a/ctaocrypt/src/memory.c
+++ b/ctaocrypt/src/memory.c
@@ -75,7 +75,7 @@ void* CyaSSL_Malloc(size_t size)
 
     #ifdef CYASSL_MALLOC_CHECK
         if (res == NULL)
-            printf("CyaSSL_malloc failed\n");
+            puts("CyaSSL_malloc failed");
     #endif
 				
     return res;
diff --git a/ctaocrypt/src/port.c b/ctaocrypt/src/port.c
index 92328408f..ea9b78d4b 100644
--- a/ctaocrypt/src/port.c
+++ b/ctaocrypt/src/port.c
@@ -353,6 +353,60 @@ int UnLockMutex(CyaSSL_Mutex *m)
         }
         
     #elif defined(CYASSL_MDK_ARM)
+    
+        #if defined(CYASSL_CMSIS_RTOS)
+            #include "cmsis_os.h"
+            #define CMSIS_NMUTEX 10
+            osMutexDef(CyaSSL_mt0) ;  osMutexDef(CyaSSL_mt1) ;  osMutexDef(CyaSSL_mt2) ;
+            osMutexDef(CyaSSL_mt3) ;  osMutexDef(CyaSSL_mt4) ;  osMutexDef(CyaSSL_mt5) ;  
+            osMutexDef(CyaSSL_mt6) ;  osMutexDef(CyaSSL_mt7) ;  osMutexDef(CyaSSL_mt8) ;  
+            osMutexDef(CyaSSL_mt9) ;  
+            
+            static const osMutexDef_t *CMSIS_mutex[] = { osMutex(CyaSSL_mt0),   
+                osMutex(CyaSSL_mt1),    osMutex(CyaSSL_mt2),   osMutex(CyaSSL_mt3),    
+                osMutex(CyaSSL_mt4),    osMutex(CyaSSL_mt5),   osMutex(CyaSSL_mt6),
+                osMutex(CyaSSL_mt7),    osMutex(CyaSSL_mt8),    osMutex(CyaSSL_mt9) } ;                 
+            
+            static osMutexId CMSIS_mutexID[CMSIS_NMUTEX] = {0} ;
+
+            int InitMutex(CyaSSL_Mutex* m)
+            {
+                int i ;
+                for (i=0; i
+        #include 
+    extern FILE * CyaSSL_fopen(const char *fname, const char *mode) ;
+    #define fopen CyaSSL_fopen
+#endif
 
 #ifdef HAVE_NTRU
     #include "crypto_ntru.h"
diff --git a/cyassl/ctaocrypt/port.h b/cyassl/ctaocrypt/port.h
index 28ec413b6..1591d4c8b 100644
--- a/cyassl/ctaocrypt/port.h
+++ b/cyassl/ctaocrypt/port.h
@@ -55,7 +55,11 @@
 #elif defined(FREESCALE_MQX)
     /* do nothing */
 #elif defined(CYASSL_MDK_ARM)
-    #include 
+    #if defined(CYASSL_MDK5)
+         #include "cmsis_os.h"
+    #else
+        #include 
+    #endif
 #else
     #ifndef SINGLE_THREADED
         #define CYASSL_PTHREADS
@@ -91,7 +95,11 @@
     #elif defined(FREESCALE_MQX)
         typedef MUTEX_STRUCT CyaSSL_Mutex;
     #elif defined(CYASSL_MDK_ARM)
-        typedef OS_MUT CyaSSL_Mutex;
+        #if defined(CYASSL_CMSIS_RTOS)
+            typedef osMutexId CyaSSL_Mutex;
+        #else
+            typedef OS_MUT CyaSSL_Mutex;
+        #endif
     #else
         #error Need a mutex type in multithreaded mode
     #endif /* USE_WINDOWS_API */
diff --git a/cyassl/internal.h b/cyassl/internal.h
index 8fe14fe45..32b8964bf 100644
--- a/cyassl/internal.h
+++ b/cyassl/internal.h
@@ -90,7 +90,11 @@
 #elif defined(FREESCALE_MQX)
     /* do nothing */
 #elif defined(CYASSL_MDK_ARM)
-    #include 
+    #if defined(CYASSL_MDK5)
+         #include "cmsis_os.h"
+    #else
+        #include 
+    #endif
 #else
     #ifndef SINGLE_THREADED
         #define CYASSL_PTHREADS
@@ -1662,6 +1666,9 @@ struct CYASSL_X509 {
     byte             notBefore[MAX_DATE_SZ];
     int              notAfterSz;
     byte             notAfter[MAX_DATE_SZ];
+    int              sigOID;
+    buffer           sig;
+    int              pubKeyOID;
     buffer           pubKey;
     buffer           derCert;                        /* may need  */
     DNS_entry*       altNames;                       /* alt names list */
diff --git a/cyassl/ssl.h b/cyassl/ssl.h
index 245cdebf4..e2645c99e 100644
--- a/cyassl/ssl.h
+++ b/cyassl/ssl.h
@@ -418,6 +418,8 @@ CYASSL_API int CyaSSL_X509_NAME_get_text_by_NID(
                                             CYASSL_X509_NAME*, int, char*, int);
 CYASSL_API int         CyaSSL_X509_verify_cert(CYASSL_X509_STORE_CTX*);
 CYASSL_API const char* CyaSSL_X509_verify_cert_error_string(long);
+CYASSL_API int CyaSSL_X509_get_signature_type(CYASSL_X509*);
+CYASSL_API int CyaSSL_X509_get_signature(CYASSL_X509*, unsigned char*, int*);
 
 CYASSL_API int CyaSSL_X509_LOOKUP_add_dir(CYASSL_X509_LOOKUP*,const char*,long);
 CYASSL_API int CyaSSL_X509_LOOKUP_load_file(CYASSL_X509_LOOKUP*, const char*,
diff --git a/cyassl/test.h b/cyassl/test.h
index e0943a7b9..c5e2799d0 100644
--- a/cyassl/test.h
+++ b/cyassl/test.h
@@ -208,10 +208,8 @@ static const word16      yasslPort = 11111;
 static INLINE void err_sys(const char* msg)
 {
     printf("yassl error: %s\n", msg);
-    #ifndef CYASSL_MDK_SHELL
     if (msg)
         exit(EXIT_FAILURE);
-    #endif
 }
 
 
diff --git a/src/internal.c b/src/internal.c
index 94d50d7fa..92194f5de 100644
--- a/src/internal.c
+++ b/src/internal.c
@@ -1266,6 +1266,7 @@ void InitX509(CYASSL_X509* x509, int dynamicFlag)
     InitX509Name(&x509->subject, 0);
     x509->version        = 0;
     x509->pubKey.buffer  = NULL;
+    x509->sig.buffer     = NULL;
     x509->derCert.buffer = NULL;
     x509->altNames       = NULL;
     x509->altNamesNext   = NULL;
@@ -1284,6 +1285,7 @@ void FreeX509(CYASSL_X509* x509)
     if (x509->pubKey.buffer)
         XFREE(x509->pubKey.buffer, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
     XFREE(x509->derCert.buffer, NULL, DYNAMIC_TYPE_SUBJECT_CN);
+    XFREE(x509->sig.buffer, NULL, 0);
     if (x509->altNames)
         FreeAltNames(x509->altNames, NULL);
     if (x509->dynamicMemory)
@@ -3121,6 +3123,7 @@ int CopyDecodedToX509(CYASSL_X509* x509, DecodedCert* dCert)
         x509->pubKey.buffer = (byte*)XMALLOC(
                               dCert->pubKeySize, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
         if (x509->pubKey.buffer != NULL) {
+            x509->pubKeyOID = dCert->keyOID;
             x509->pubKey.length = dCert->pubKeySize;
             XMEMCPY(x509->pubKey.buffer, dCert->publicKey, dCert->pubKeySize);
         }
@@ -3128,6 +3131,17 @@ int CopyDecodedToX509(CYASSL_X509* x509, DecodedCert* dCert)
             ret = MEMORY_E;
     }
 
+    x509->sig.buffer = (byte*)XMALLOC(dCert->sigLength, NULL, 0);
+    if (x509->sig.buffer == NULL) {
+        ret = MEMORY_E;
+    }
+    else {
+        XMEMCPY(x509->sig.buffer,
+                             &dCert->source[dCert->sigIndex], dCert->sigLength);
+        x509->sig.length = dCert->sigLength;
+        x509->sigOID = dCert->signatureOID;
+    }
+
     /* store cert for potential retrieval */
     x509->derCert.buffer = (byte*)XMALLOC(dCert->maxIdx, NULL,
                                           DYNAMIC_TYPE_CERT);
@@ -3919,7 +3933,6 @@ static INLINE int Encrypt(CYASSL* ssl, byte* out, const byte* input, word16 sz)
         #ifdef BUILD_AES
             case cyassl_aes:
                 return AesCbcEncrypt(ssl->encrypt.aes, out, input, sz);
-                break;
         #endif
 
         #ifdef BUILD_AESGCM
@@ -4015,7 +4028,6 @@ static INLINE int Encrypt(CYASSL* ssl, byte* out, const byte* input, word16 sz)
         #ifdef HAVE_HC128
             case cyassl_hc128:
                 return Hc128_Process(ssl->encrypt.hc128, out, input, sz);
-                break;
         #endif
 
         #ifdef BUILD_RABBIT
@@ -4070,7 +4082,6 @@ static INLINE int Decrypt(CYASSL* ssl, byte* plain, const byte* input,
         #ifdef BUILD_AES
             case cyassl_aes:
                 return AesCbcDecrypt(ssl->decrypt.aes, plain, input, sz);
-                break;
         #endif
 
         #ifdef BUILD_AESGCM
@@ -4154,7 +4165,6 @@ static INLINE int Decrypt(CYASSL* ssl, byte* plain, const byte* input,
         #ifdef HAVE_HC128
             case cyassl_hc128:
                 return Hc128_Process(ssl->decrypt.hc128, plain, input, sz);
-                break;
         #endif
 
         #ifdef BUILD_RABBIT
@@ -8433,22 +8443,16 @@ static void PickHashSigAlgo(CYASSL* ssl,
         switch(size) {
             case 20:
                 return secp160r1;
-                break;
             case 24:
                 return secp192r1;
-                break;
             case 28:
                 return secp224r1;
-                break;
             case 32:
                 return secp256r1;
-                break;
             case 48:
                 return secp384r1;
-                break;
             case 66:
                 return secp521r1;
-                break;
             default:
                 return 0;
         }        
diff --git a/src/io.c b/src/io.c
index 070bc8c63..ca620d4ad 100644
--- a/src/io.c
+++ b/src/io.c
@@ -56,7 +56,13 @@
         #include 
         #include 
     #elif defined(CYASSL_MDK_ARM)
-        #include 
+        #if defined(CYASSL_MDK5)
+            #include "cmsis_os.h"
+            #include "rl_fs.h" 
+            #include "rl_net.h" 
+        #else
+            #include 
+        #endif
         #undef RNG
         #include "CYASSL_MDK_ARM.h"
         #undef RNG
@@ -126,13 +132,23 @@
     #define SOCKET_ECONNREFUSED RTCSERR_TCP_CONN_REFUSED
     #define SOCKET_ECONNABORTED RTCSERR_TCP_CONN_ABORTED
 #elif defined(CYASSL_MDK_ARM)
-    #define SOCKET_EWOULDBLOCK SCK_EWOULDBLOCK
-    #define SOCKET_EAGAIN      SCK_ELOCKED
-    #define SOCKET_ECONNRESET  SCK_ECLOSED
-    #define SOCKET_EINTR       SCK_ERROR
-    #define SOCKET_EPIPE       SCK_ERROR
-    #define SOCKET_ECONNREFUSED SCK_ERROR
-    #define SOCKET_ECONNABORTED SCK_ERROR
+    #if defined(CYASSL_MDK5)
+        #define SOCKET_EWOULDBLOCK BSD_ERROR_WOULDBLOCK
+        #define SOCKET_EAGAIN      BSD_ERROR_LOCKED
+        #define SOCKET_ECONNRESET  BSD_ERROR_CLOSED
+        #define SOCKET_EINTR       BSD_ERROR
+        #define SOCKET_EPIPE       BSD_ERROR
+        #define SOCKET_ECONNREFUSED BSD_ERROR
+        #define SOCKET_ECONNABORTED BSD_ERROR
+    #else
+        #define SOCKET_EWOULDBLOCK SCK_EWOULDBLOCK
+        #define SOCKET_EAGAIN      SCK_ELOCKED
+        #define SOCKET_ECONNRESET  SCK_ECLOSED
+        #define SOCKET_EINTR       SCK_ERROR
+        #define SOCKET_EPIPE       SCK_ERROR
+        #define SOCKET_ECONNREFUSED SCK_ERROR
+        #define SOCKET_ECONNABORTED SCK_ERROR
+    #endif
 #else
     #define SOCKET_EWOULDBLOCK EWOULDBLOCK
     #define SOCKET_EAGAIN      EAGAIN
diff --git a/src/ssl.c b/src/ssl.c
index cc21ba2a7..f17449376 100644
--- a/src/ssl.c
+++ b/src/ssl.c
@@ -89,12 +89,12 @@
 #endif /* min */
 
 #ifndef max
-
+#ifdef CYASSL_DTLS
     static INLINE word32 max(word32 a, word32 b)
     {
         return a > b ? a : b;
     }
-
+#endif
 #endif /* min */
 
 
@@ -2095,7 +2095,12 @@ int CyaSSL_CertManagerVerifyBuffer(CYASSL_CERT_MANAGER* cm, const byte* buff,
 #else
     /* stdio, default case */
     #define XFILE      FILE*
-    #define XFOPEN     fopen 
+    #if defined(CYASSL_MDK_ARM)
+        extern FILE * CyaSSL_fopen(const char *name, const char *mode) ;
+        #define XFOPEN     CyaSSL_fopen
+    #else
+        #define XFOPEN     fopen
+    #endif
     #define XFSEEK     fseek
     #define XFTELL     ftell
     #define XREWIND    rewind
@@ -5757,6 +5762,7 @@ int CyaSSL_set_compression(CYASSL* ssl)
     #define CloseSocket(s) closesocket(s)
 #elif defined(CYASSL_MDK_ARM)
     #define CloseSocket(s) closesocket(s)
+    extern int closesocket(int) ;
 #else
     #define CloseSocket(s) close(s)
 #endif
@@ -7137,13 +7143,42 @@ int CyaSSL_set_compression(CYASSL* ssl)
     }
 
 
+    int CyaSSL_X509_get_signature_type(CYASSL_X509* x509)
+    {
+        int type = 0;
+
+        CYASSL_ENTER("CyaSSL_X509_get_signature_type");
+
+        if (x509 != NULL)
+            type = x509->sigOID;
+
+        return type;
+    }
+
+
+    int CyaSSL_X509_get_signature(CYASSL_X509* x509,
+                                                 unsigned char* buf, int* bufSz)
+    {
+        CYASSL_ENTER("CyaSSL_X509_get_signature");
+        if (x509 == NULL || bufSz == NULL || *bufSz < (int)x509->sig.length)
+            return SSL_FATAL_ERROR;
+
+        if (buf != NULL)
+            XMEMCPY(buf, x509->sig.buffer, x509->sig.length);
+        *bufSz = x509->sig.length;
+
+        return SSL_SUCCESS;
+    }
+
+
     /* write X509 serial number in unsigned binary to buffer 
        buffer needs to be at least EXTERNAL_SERIAL_SIZE (32) for all cases
        return SSL_SUCCESS on success */
     int CyaSSL_X509_get_serial_number(CYASSL_X509* x509, byte* in, int* inOutSz)
     {
         CYASSL_ENTER("CyaSSL_X509_get_serial_number");
-        if (x509 == NULL || in == NULL || *inOutSz < x509->serialSz)
+        if (x509 == NULL || in == NULL ||
+                                   inOutSz == NULL || *inOutSz < x509->serialSz)
             return BAD_FUNC_ARG;
 
         XMEMCPY(in, x509->serial, x509->serialSz);
@@ -8283,7 +8318,7 @@ CYASSL_X509* CyaSSL_X509_load_certificate_file(const char* fname, int format)
             key = (CYASSL_EVP_PKEY*)XMALLOC(
                         sizeof(CYASSL_EVP_PKEY), NULL, DYNAMIC_TYPE_PUBLIC_KEY);
             if (key != NULL) {
-                key->type = 0;
+                key->type = x509->pubKeyOID;
                 key->save_type = 0;
                 key->pkey.ptr = (char*)XMALLOC(
                             x509->pubKey.length, NULL, DYNAMIC_TYPE_PUBLIC_KEY);
@@ -10177,7 +10212,6 @@ static int initGlobalRNG = 0;
                 case ARC4_TYPE:
                     CYASSL_MSG("returning arc4 state");
                     return (void*)&ctx->cipher.arc4.x;
-                    break;
 
                 default:
                     CYASSL_MSG("bad x state type");
@@ -10198,7 +10232,6 @@ static int initGlobalRNG = 0;
                 case ARC4_TYPE:
                     CYASSL_MSG("returning arc4 state size");
                     return sizeof(Arc4);
-                    break;
 
                 default:
                     CYASSL_MSG("bad x state type");
@@ -10301,7 +10334,6 @@ static int initGlobalRNG = 0;
             case AES_256_CBC_TYPE :
                 CYASSL_MSG("AES CBC");
                 return AES_BLOCK_SIZE;
-                break;
 
 #ifdef CYASSL_AES_COUNTER
             case AES_128_CTR_TYPE :
@@ -10309,28 +10341,23 @@ static int initGlobalRNG = 0;
             case AES_256_CTR_TYPE :
                 CYASSL_MSG("AES CTR");
                 return AES_BLOCK_SIZE;
-                break;
 #endif
 
             case DES_CBC_TYPE :
                 CYASSL_MSG("DES CBC");
                 return DES_BLOCK_SIZE;
-                break;
                 
             case DES_EDE3_CBC_TYPE :
                 CYASSL_MSG("DES EDE3 CBC");
                 return DES_BLOCK_SIZE;
-                break;
 
             case ARC4_TYPE :
                 CYASSL_MSG("ARC4");
                 return 0;
-                break;
 
             case NULL_CIPHER_TYPE :
                 CYASSL_MSG("NULL");
                 return 0;
-                break;
 
             default: {
                 CYASSL_MSG("bad type");
diff --git a/src/tls.c b/src/tls.c
index ab139c7ff..878e2e003 100644
--- a/src/tls.c
+++ b/src/tls.c
@@ -370,12 +370,13 @@ static INLINE void c16toa(word16 u16, byte* c)
     c[1] =  u16 & 0xff;
 }
 
+#ifdef HAVE_TLS_EXTENSIONS
 /* convert opaque to 16 bit integer */
 static INLINE void ato16(const byte* c, word16* u16)
 {
     *u16 = (c[0] << 8) | (c[1]);
 }
-
+#endif
 
 /* convert 32 bit integer to opaque */
 static INLINE void c32toa(word32 u32, byte* c)
@@ -432,41 +433,36 @@ int CyaSSL_GetHmacType(CYASSL* ssl)
         {
             return MD5;
         }
-        break;
         #endif
         #ifndef NO_SHA256
         case sha256_mac:
         {
             return SHA256;
         }
-        break;
         #endif
         #ifdef CYASSL_SHA384
         case sha384_mac:
         {
             return SHA384;
         }
-        break;
+
         #endif
         #ifndef NO_SHA
         case sha_mac:
         {
             return SHA;
         }
-        break;
         #endif
         #ifdef HAVE_BLAKE2 
         case blake2b_mac:
         {
             return BLAKE2B_ID; 
         }
-        break;
         #endif
         default:
         {
             return SSL_FATAL_ERROR;
         }
-        break;
     }
 }