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wolfssl/IDE/XilinxSDK/include.am

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Added wolfCrypt Xilinx SDK project. Fix for stsafe.h inclusion of ssl.h with `WOLFCRYPT_ONLY`.
2020-03-20 14:40:17 -07:00
# vim:ft=automake
# included from Top Level Makefile.am
# All paths should be given relative to the root
EXTRA_DIST+= IDE/XilinxSDK/README.md
Integrate Xilinx Versal * add Versal specific glue The same structure of an "XSecure client" is used throughout the API's, therefor define it once and re-use in all clients. * integrate Versal AES-GCM engine * integrate Versal SHA3-384 engine * add versal support to tests - There's no intermediate-hash API for Versal. * add specific test with large AAD Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the hardware engine. * add specific test with misaligned AES-GCM arguments * integrate Versal RSA engine * disable failing RSA test-case when Xilinx Crypto is enabled * introduce define `WOLFSSL_XILINX_CRYPT_VERSAL` * integrate Versal TRNG engine * allow using Versal TRNG w/o wolfcrypt DRBG Versal TRNG already provides a HRNG mode which does the same as the wolfcrypt DRBG implementation. * add support for user-supplied nonce to Versal TRNG * add `wc_XsecureErrorToString()` to map PLM error codes to messages. * integrate Versal EcDSA engine * update tests to work with Versal EcDSA If deterministic K is enabled, the tests failed here since the Versal EcDSA engine doesn't support the SECP256R1 curve yet. * Xilinx crypto engines like aligned memory very much Make this a default choice, not via the user configuration. * add Xilinx-specific `WOLFSSL_MSG()` equivalent `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for 1 second before printing to stdout, since the PLM maybe prints to same and outputs would be mixed up. This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`. * add option to enable DPA CounterMeasures in AES-GCM crypto engine * add "command mode" to Xilinx bare-metal example * update Xilinx default user settings * add script to execute benchmarks * add scripts to create graphics * add Vitis 2022.1 example projects Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-05-20 14:28:39 +02:00
EXTRA_DIST+= IDE/XilinxSDK/bench.sh
EXTRA_DIST+= IDE/XilinxSDK/combine.sh
EXTRA_DIST+= IDE/XilinxSDK/eclipse_formatter_profile.xml
EXTRA_DIST+= IDE/XilinxSDK/graph.sh
Added wolfCrypt Xilinx SDK project. Fix for stsafe.h inclusion of ssl.h with `WOLFCRYPT_ONLY`.
2020-03-20 14:40:17 -07:00
EXTRA_DIST+= IDE/XilinxSDK/user_settings.h
EXTRA_DIST+= IDE/XilinxSDK/wolfssl_example.c
add 2019.2 Xilinx example and update README fix to remove xml extension add missing project file update project update dist include rm prj files
2020-04-30 15:56:50 -06:00
EXTRA_DIST+= IDE/XilinxSDK/2018_2/lscript.ld
EXTRA_DIST+= IDE/XilinxSDK/2018_2/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2018_2/.project
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example/.project
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example/src/lscript.ld
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example_system/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example_system/.project
add sprj file
2020-05-06 12:13:22 -07:00
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example_system/wolfCrypt_example_system.sprj
Integrate Xilinx Versal * add Versal specific glue The same structure of an "XSecure client" is used throughout the API's, therefor define it once and re-use in all clients. * integrate Versal AES-GCM engine * integrate Versal SHA3-384 engine * add versal support to tests - There's no intermediate-hash API for Versal. * add specific test with large AAD Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the hardware engine. * add specific test with misaligned AES-GCM arguments * integrate Versal RSA engine * disable failing RSA test-case when Xilinx Crypto is enabled * introduce define `WOLFSSL_XILINX_CRYPT_VERSAL` * integrate Versal TRNG engine * allow using Versal TRNG w/o wolfcrypt DRBG Versal TRNG already provides a HRNG mode which does the same as the wolfcrypt DRBG implementation. * add support for user-supplied nonce to Versal TRNG * add `wc_XsecureErrorToString()` to map PLM error codes to messages. * integrate Versal EcDSA engine * update tests to work with Versal EcDSA If deterministic K is enabled, the tests failed here since the Versal EcDSA engine doesn't support the SECP256R1 curve yet. * Xilinx crypto engines like aligned memory very much Make this a default choice, not via the user configuration. * add Xilinx-specific `WOLFSSL_MSG()` equivalent `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for 1 second before printing to stdout, since the PLM maybe prints to same and outputs would be mixed up. This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`. * add option to enable DPA CounterMeasures in AES-GCM crypto engine * add "command mode" to Xilinx bare-metal example * update Xilinx default user settings * add script to execute benchmarks * add scripts to create graphics * add Vitis 2022.1 example projects Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-05-20 14:28:39 +02:00
EXTRA_DIST+= IDE/XilinxSDK/2022_1/.gitignore
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_example/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_example/.project
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_example/wolfCrypt_example.prj
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_example_system/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_example_system/.project
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_example_system/wolfCrypt_example_system.sprj
add FreeRTOS example to include.am
2022-09-29 09:57:23 -06:00
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_FreeRTOS_example/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_FreeRTOS_example/.project
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_FreeRTOS_example/wolfCrypt_FreeRTOS_example.prj
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_FreeRTOS_example_system/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_FreeRTOS_example_system/.project
EXTRA_DIST+= IDE/XilinxSDK/2022_1/wolfCrypt_FreeRTOS_example_system/wolfCrypt_FreeRTOS_example_system.sprj
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