diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_test/main/main.c b/IDE/Espressif/ESP-IDF/examples/wolfssl_test/main/main.c index d0d86bec1..9bab06653 100644 --- a/IDE/Espressif/ESP-IDF/examples/wolfssl_test/main/main.c +++ b/IDE/Espressif/ESP-IDF/examples/wolfssl_test/main/main.c @@ -151,18 +151,37 @@ void app_main(void) #endif + /* some interesting settings are target specific (ESP32, -C3, -S3, etc */ #if defined(CONFIG_IDF_TARGET_ESP32C3) /* not available for C3 at this time */ -#else - // ESP_LOGI(TAG, "CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ = %u MHz", CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ); +#elif defined(CONFIG_IDF_TARGET_ESP32S3) + ESP_LOGI(TAG, "CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ = %u MHz", + CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ + ); + ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount); +#else + ESP_LOGI(TAG, "CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ = %u MHz", + CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ + ); ESP_LOGI(TAG, "Xthal_have_ccount = %u", Xthal_have_ccount); #endif + + /* all platforms: stack high water mark check */ ESP_LOGI(TAG, "Stack HWM: %d\n", uxTaskGetStackHighWaterMark(NULL)); + /* check to see if we are using hardware encryption */ #if defined(NO_ESP32WROOM32_CRYPT) ESP_LOGI(TAG, "NO_ESP32WROOM32_CRYPT defined! HW acceleration DISABLED."); #else - ESP_LOGI(TAG, "ESP32WROOM32_CRYPT is enabled."); + #if defined(CONFIG_IDF_TARGET_ESP32C3) + #error "ESP32WROOM32_CRYPT not yet supported on ESP32-C3" + #elif defined(CONFIG_IDF_TARGET_ESP32S2) + #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S2" + #elif defined(CONFIG_IDF_TARGET_ESP32S3) + #error "ESP32WROOM32_CRYPT not yet supported on ESP32-S3" + #else + ESP_LOGI(TAG, "ESP32WROOM32_CRYPT is enabled."); + #endif #endif diff --git a/IDE/Espressif/ESP-IDF/examples/wolfssl_test/sdkconfig.defaults b/IDE/Espressif/ESP-IDF/examples/wolfssl_test/sdkconfig.defaults index 7a1edc8c3..640ff4e9f 100644 --- a/IDE/Espressif/ESP-IDF/examples/wolfssl_test/sdkconfig.defaults +++ b/IDE/Espressif/ESP-IDF/examples/wolfssl_test/sdkconfig.defaults @@ -6,7 +6,7 @@ CONFIG_ESP_MAIN_TASK_STACK_SIZE=55000 # Legacy stack size for older ESP-IDF versions -CONFIG_MAIN_TASK_STACK_SIZE=11000 +CONFIG_MAIN_TASK_STACK_SIZE=55000 # # Watchdog Timers @@ -24,4 +24,12 @@ CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_ENABLE=y CONFIG_COMPILER_OPTIMIZATION_ASSERTION_LEVEL=2 CONFIG_COMPILER_HIDE_PATHS_MACROS=y CONFIG_COMPILER_STACK_CHECK_MODE_NORM=y -CONFIG_COMPILER_STACK_CHECK=y \ No newline at end of file +CONFIG_COMPILER_STACK_CHECK=y + +# minimum C3 chip revision known to work is 2. +# rev 0 and 1 not available for testing. +# all revisions expected to work. +CONFIG_ESP32C3_REV_MIN_0= +CONFIG_ESP32C3_REV_MIN_1= +CONFIG_ESP32C3_REV_MIN_2=y +CONFIG_ESP32C3_REV_MIN_3=