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TakayukiMatsuo
2020-07-06 10:58:58 +09:00
parent 464cd49e45 655022cfc5
commit 9554e54e8f
372 changed files with 38271 additions and 64331 deletions
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152
ChangeLog.md
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@ -1,15 +1,153 @@
# wolfSSL Release X.X.X (To Be Determined / Work in Progress)
# wolfSSL Release 4.4.1 (XX/XX/2020) **IN DEVELOPMENT**
If you have questions about this release, then feel free to contact us on our info@ address.
If you have questions about this release, then feel free to contact us on our
info@ address.
Release X.X.X of wolfSSL embedded TLS has bug fixes and new features including:
Release 4.4.1 of wolfSSL embedded TLS has bug fixes and new features including:
##### New Feature Additions
## New Feature Additions
##### Fixes
* Fix for RSA public encrypt / private sign with RSA key sizes over 2048-bit. PR #2755
* Place holder.
##### Improvements/Optimizations
## Fixes
* Place holder.
## Improvements/Optimizations
* Place holder.
## This release of wolfSSL includes fixes for X security vulnerabilities.
* Place holder.
For additional vulnerability information visit the vulnerability page at
https://www.wolfssl.com/docs/security-vulnerabilities/
See INSTALL file for build instructions.
More info can be found on-line at https://wolfssl.com/wolfSSL/Docs.html
# wolfSSL Release 4.4.0 (04/22/2020)
If you have questions about this release, then feel free to contact us on our
info@ address.
Release 4.4.0 of wolfSSL embedded TLS has bug fixes and new features including:
## New Feature Additions
* Hexagon support.
* DSP builds to offload ECC verify operations.
* Certificate Manager callback support.
* New APIs for running updates to ChaCha20/Poly1305 AEAD.
* Support for use with Apache.
* Add support for IBM s390x.
* PKCS8 support for ED25519.
* OpenVPN support.
* Add P384 curve support to SP.
* Add BIO and EVP API.
* Add AES-OFB mode.
* Add AES-CFB mode.
* Add Curve448, X448, and Ed448.
* Add Renesas Synergy S7G2 build and hardware acceleration.
## Fixes
* Fix for RSA public encrypt / private sign with RSA key sizes over 2048-bit.
* Correct misspellings.
* Secure renegotiation fix.
* Fix memory leak when using ATECC and non-SECP256R1 curves for sign, verify,
or shared secret.
* Fix for K64 MMCAU with `WOLFSSL_SMALL_STACK_CACHE`.
* Fix the RSA verify only build.
* Fix in SP C implementation for small stack.
* Fix using the auth key id extension is set, hash might not be present.
* Fix when flattening certificate structure to include the subject alt names.
* Fixes for building with ECC sign/verify only.
* Fix for ECC and no cache resistance.
* Fix memory leak in DSA.
* Fix build on minGW.
* Fix `PemToDer()` call in `ProcessBuffer()` to set more than ECC.
* Fix for using RSA without SHA-512.
* Add some close tags to the echoserver HTTP example output.
* Miscellaneous fixes and updates for static analysis reports.
* Fixes for time structure support.
* Fixes for VxWorks support.
* Fixes for Async crypto support.
* Fix cache resist compile to work with SP C code.
* Fixes for Curve25519 x64 asm.
* Fix for SP x64 div.
* Fix for DTLS edge case where CCS and Finished come out of order and the
retransmit pool gets flushed.
* Fix for infinite loop in SHA-1 with small inputs. Thanks to Peter W.
* Fix for FIPS Hmac where `wc_HmacInit()` isn't used. `wc_HmacSetKey()` needs
to initialize the Hmac structure. Type is set to NONE, and checked against
NONE, not 0.
* Fixes for SP RSA private operations.
* Fixes for Xilinx SDK and Zynq UltraScale+ MPSoC
* Fix leak when building with HAVE_AESGCM and NO_AES_DECRYPT. Thanks G.G.
* Fixes for building ECC without ASN.
* Fix for async TLSv1.3 issues.
* Fix `wc_KeyPemToDer()` with PKCS1 and empty key.
* Omit `-fomit-frame-pointer` from CFLAGS in configure.ac.
## Improvements/Optimizations
* Qt 5.12 and 5.13 support.
* Added more digest types to Cryptocell RSA sign/verify.
* Some memory usage improvements.
* Speed improvements for mp_rand.
* Improvements to CRL and OCSP support.
* Refactor Poly1305 AEAD/MAC to reduce duplicate code.
* Add blinding to RSA key gen.
* Improvements to blinding.
* Improvement and expansion of OpenSSL Compatibility Layer.
* Improvements to ChaCha20.
* Improvements to X.509 processing.
* Improvements to ECC support.
* Improvement in detecting 64-bit support.
* Refactor to combine duplicate ECC parameter parsing code.
* Improve keyFormat to be set by algId and let later key parsing produce fail.
* Add test cases for 3072-bit and 4096-bit RSA keys.
* Improve signature wrapper and DH test cases.
* Improvements to the configure.ac script.
* Added constant time RSA q modinv p.
* Improve performance of SP Intel 64-bit asm.
* Added a few more functions to the ABI list.
* Improve TLS bidirectional shutdown behavior.
* OpenSSH 8.1 support.
* Improve performance of RSA/DH operations on x64.
* Add support for PKCS7/CMS Enveloped data with fragmented encrypted content.
* Example linker description for FIPS builds to enforce object ordering.
* C# wrapper improvements. Added TLS client example and TLSv1.3 methods.
* Allow setting MTU in DTLS.
* Improve PKCS12 create for outputting encrypted bundles.
* Constant time EC map to affine for private operations.
* Improve performance of RSA public key ops with TFM.
* Smaller table version of AES encrypt/decrypt.
* Support IAR with position independent code (ROPI).
* Improve speed of AArch64 assembly.
* Support AES-CTR on esp32.
* Add a no malloc option for small SP math.
## This release of wolfSSL includes fixes for 2 security vulnerabilities.
* For fast math, use a constant time modular inverse when mapping to affine
when operation involves a private key - keygen, calc shared secret, sign.
Thank you to Alejandro Cabrera Aldaya, Cesar Pereida García and
Billy Bob Brumley from the Network and Information Security Group (NISEC)
at Tampere University for the report.
* Change constant time and cache resistant ECC mulmod. Ensure points being
operated on change to make constant time. Thank you to Pietro Borrello at
Sapienza University of Rome.
For additional vulnerability information visit the vulnerability page at
https://www.wolfssl.com/docs/security-vulnerabilities/
See INSTALL file for build instructions.
More info can be found on-line at https://wolfssl.com/wolfSSL/Docs.html

7
IDE/GCC-ARM/Header/user_settings.h
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@ -189,14 +189,17 @@ extern "C" {
/* Use alternate ECC size for ECC math */
#ifdef USE_FAST_MATH
/* MAX ECC BITS = ROUND8(MAX ECC) * 2 */
#ifdef NO_RSA
/* Custom fastmath size if not using RSA */
/* MAX = ROUND32(ECC BITS 256) + SIZE_OF_MP_DIGIT(32) */
#undef FP_MAX_BITS
#define FP_MAX_BITS (256 + 32)
#define FP_MAX_BITS (256 * 2)
#else
#undef ALT_ECC_SIZE
#define ALT_ECC_SIZE
/* wolfSSL will compute the FP_MAX_BITS_ECC, but it can be overriden */
//#undef FP_MAX_BITS_ECC
//#define FP_MAX_BITS_ECC (256 * 2)
#endif
/* Speedups specific to curve */

6
IDE/IAR-EWARM/embOS/SAMV71_XULT/embOS_SAMV71_XULT_user_settings/user_settings.h
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@ -34,11 +34,11 @@
#undef ECC_USER_CURVES
#define ECC_USER_CURVES
#undef ECC_ALT_SIZE
#define ECC_ALT_SIZE
#undef ALT_ECC_SIZE
#define ALT_ECC_SIZE
#undef FP_MAX_BITS_ECC
#define FP_MAX_BITS_ECC 528
#define FP_MAX_BITS_ECC (256 * 2)
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT

8
IDE/IAR-EWARM/embOS/SAMV71_XULT/embOS_SAMV71_XULT_user_settings/user_settings_verbose_example.h
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@ -84,11 +84,13 @@
#define ECC_TIMING_RESISTANT
#ifdef USE_FAST_MATH
/* Max ECC bits (curve size * 8). ECC521 is (66*8) = 528. */
#undef ALT_ECC_SIZE
#define ALT_ECC_SIZE
#undef FP_MAX_BITS_ECC
#define FP_MAX_BITS_ECC 528
/* wolfSSL will compute the FP_MAX_BITS_ECC, but it can be overriden */
/* MAX ECC BITS = ROUND8(MAX ECC) * 2 */
//#undef FP_MAX_BITS_ECC
//#define FP_MAX_BITS_ECC (528 * 2)
/* Enable TFM optimizations for ECC */
#define TFM_ECC192

6
IDE/IAR-EWARM/embOS/custom_port/custom_port_user_settings/user_settings.h
View File

@ -31,11 +31,11 @@
#undef ECC_USER_CURVES
#define ECC_USER_CURVES
#undef ECC_ALT_SIZE
#define ECC_ALT_SIZE
#undef ALT_ECC_SIZE
#define ALT_ECC_SIZE
#undef FP_MAX_BITS_ECC
#define FP_MAX_BITS_ECC 528
#define FP_MAX_BITS_ECC (256 * 2)
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT

4
IDE/LPCXPRESSO/lib_wolfssl/user_settings.h
View File

@ -22,7 +22,8 @@
#define FP_LUT 4
#define FP_MAX_BITS 2048 /* 4096 */
#define FP_MAX_BITS_ECC 512
#define ECC_USER_CURVES /* Disables P-112, P-128, P-160, P-192, P-224, P-384, P-521 but leaves P-256 enabled */
#define FP_MAX_BITS_ECC (256 * 2)
#define ALT_ECC_SIZE
#define USE_FAST_MATH
#define SMALL_SESSION_CACHE
@ -52,7 +53,6 @@
#define NO_64BIT
#define NO_WOLFSSL_SERVER
#define NO_OLD_TLS
#define ECC_USER_CURVES /* Disables P-112, P-128, P-160, P-192, P-224, P-384, P-521 but leaves P-256 enabled */
#define NO_DES3
#define NO_MD5
#define NO_RC4

323
IDE/OPENSTM32/.cproject
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@ -1,323 +0,0 @@
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473
IDE/OPENSTM32/Inc/user_settings.h
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@ -1,473 +0,0 @@
/* user_settings.h
*
* Copyright (C) 2006-2020 wolfSSL Inc.
*
* This file is part of wolfSSL.
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
/* Example wolfSSL user settings for STM32F4 with CubeMX */
#ifndef WOLFSSL_USER_SETTINGS_H
#define WOLFSSL_USER_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------------------------------------------------------- */
/* Platform */
/* ------------------------------------------------------------------------- */
#undef WOLFSSL_GENERAL_ALIGNMENT
#define WOLFSSL_GENERAL_ALIGNMENT 4
#undef SINGLE_THREADED
//#define SINGLE_THREADED
#undef WOLFSSL_SMALL_STACK
#define WOLFSSL_SMALL_STACK
#undef WOLFSSL_STM32F4
#define WOLFSSL_STM32F4
#undef WOLFSSL_STM32_CUBEMX
#define WOLFSSL_STM32_CUBEMX
#undef FREERTOS
#define FREERTOS
#undef WOLFSSL_USER_IO
#define WOLFSSL_USER_IO
#undef WOLFSSL_NO_SOCK
#define WOLFSSL_NO_SOCK
/* ------------------------------------------------------------------------- */
/* HW Crypto Acceleration */
/* ------------------------------------------------------------------------- */
// See settings.h STM32F4 section
/* Optionally Disable Hardware Hashing Support */
//#define NO_STM32_HASH
//#define NO_STM32_RNG
//#define NO_STM32_CRYPTO
/* ------------------------------------------------------------------------- */
/* Math Configuration */
/* ------------------------------------------------------------------------- */
#undef USE_FAST_MATH
#define USE_FAST_MATH
#ifdef USE_FAST_MATH
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#undef TFM_NO_ASM
//#define TFM_NO_ASM
/* Optimizations (TFM_ARM, TFM_ASM or none) */
//#define TFM_ASM
#endif
/* Wolf Single Precision Math */
#undef WOLFSSL_SP
#if 0
#define WOLFSSL_SP
#define WOLFSSL_SP_SMALL /* use smaller version of code */
#define WOLFSSL_HAVE_SP_RSA
//#define WOLFSSL_HAVE_SP_DH
#define WOLFSSL_HAVE_SP_ECC
#define WOLFSSL_SP_CACHE_RESISTANT
#define WOLFSSL_SP_MATH /* only SP math - eliminates fast math code */
//#define WOLFSSL_SP_ASM /* required if using the ASM versions */
//#define WOLFSSL_SP_ARM_CORTEX_M_ASM
#endif
/* ------------------------------------------------------------------------- */
/* Crypto */
/* ------------------------------------------------------------------------- */
/* RSA */
#undef NO_RSA
#if 1
#ifdef USE_FAST_MATH
/* Maximum math bits (Max RSA key bits * 2) */
#undef FP_MAX_BITS
#define FP_MAX_BITS 4096
#endif
/* half as much memory but twice as slow */
#undef RSA_LOW_MEM
//#define RSA_LOW_MEM
/* Enables blinding mode, to prevent timing attacks */
#undef WC_RSA_BLINDING
#define WC_RSA_BLINDING
/* RSA PSS Support (required for TLS v1.3)*/
#if 0
#define WC_RSA_PSS
#endif
#else
#define NO_RSA
#endif
/* ECC */
#if 1
#undef HAVE_ECC
#define HAVE_ECC
/* Manually define enabled curves */
#undef ECC_USER_CURVES
#define ECC_USER_CURVES
//#define HAVE_ECC192
//#define HAVE_ECC224
#undef NO_ECC256
//#define HAVE_ECC384
//#define HAVE_ECC521
/* Fixed point cache (speeds repeated operations against same private key) */
#undef FP_ECC
//#define FP_ECC
#ifdef FP_ECC
/* Bits / Entries */
#undef FP_ENTRIES
#define FP_ENTRIES 2
#undef FP_LUT
#define FP_LUT 4
#endif
/* Optional ECC calculation method */
/* Note: doubles heap usage, but slightly faster */
#undef ECC_SHAMIR
#define ECC_SHAMIR
/* Reduces heap usage, but slower */
#undef ECC_TIMING_RESISTANT
#define ECC_TIMING_RESISTANT
#ifdef USE_FAST_MATH
#ifdef NO_RSA
/* Custom fastmath size if not using RSA */
/* MAX = ROUND32(ECC BITS 256) + SIZE_OF_MP_DIGIT(32) */
#undef FP_MAX_BITS
#define FP_MAX_BITS (256 + 32)
#else
#undef ALT_ECC_SIZE
#define ALT_ECC_SIZE
#endif
/* Enable TFM optimizations for ECC */
//#define TFM_ECC192
//#define TFM_ECC224
#define TFM_ECC256
//#define TFM_ECC384
//#define TFM_ECC521
#endif
#endif
/* DH */
#undef NO_DH
#if 0
#define HAVE_DH /* freeRTOS settings.h requires this */
#else
//#define NO_DH
#endif
/* AES */
#undef NO_AES
#if 1
#undef HAVE_AESGCM
#define HAVE_AESGCM
/* GCM Method: GCM_SMALL, GCM_WORD32 or GCM_TABLE */
#undef GCM_SMALL
#define GCM_SMALL
#undef WOLFSSL_AES_COUNTER
#define WOLFSSL_AES_COUNTER
#undef WOLFSSL_AES_DIRECT
#define WOLFSSL_AES_DIRECT
#undef HAVE_AES_ECB
#define HAVE_AES_ECB
#else
#define NO_AES
#endif
/* DES */
#undef NO_DES3
#if 1
#else
#define NO_DES3
#endif
/* ChaCha20 / Poly1305 */
#undef HAVE_CHACHA
#undef HAVE_POLY1305
#if 1
#define HAVE_CHACHA
#define HAVE_POLY1305
/* Needed for Poly1305 */
#undef HAVE_ONE_TIME_AUTH
#define HAVE_ONE_TIME_AUTH
#endif
/* Ed25519 / Curve25519 */
#undef HAVE_CURVE25519
#undef HAVE_ED25519
#if 0
#define HAVE_CURVE25519
#define HAVE_ED25519
/* Optionally use small math (less flash usage, but much slower) */
#if 0
#define CURVED25519_SMALL
#endif
#endif
/* ------------------------------------------------------------------------- */
/* Hashing */
/* ------------------------------------------------------------------------- */
/* Sha */
#undef NO_SHA
#if 1
/* 1k smaller, but 25% slower */
//#define USE_SLOW_SHA
#else
#define NO_SHA
#endif
/* Sha256 */
#undef NO_SHA256
#if 1
/* not unrolled - ~2k smaller and ~25% slower */
//#define USE_SLOW_SHA256
/* Sha224 */
#if 0
#define WOLFSSL_SHA224
#endif
#else
#define NO_SHA256
#endif
/* Sha512 */
#undef WOLFSSL_SHA512
#if 1
/* over twice as small, but 50% slower */
//#define USE_SLOW_SHA512
#define WOLFSSL_SHA512
#define HAVE_SHA512 /* freeRTOS settings.h requires this */
/* Sha384 */
#undef WOLFSSL_SHA384
#if 1
#define WOLFSSL_SHA384
#endif
#endif
/* MD5 */
#if 1
/* enabled */
#else
#define NO_MD5
#endif
/* ------------------------------------------------------------------------- */
/* Benchmark / Test */
/* ------------------------------------------------------------------------- */
/* Use reduced benchmark / test sizes */
#undef BENCH_EMBEDDED
#define BENCH_EMBEDDED
#undef USE_CERT_BUFFERS_2048
#define USE_CERT_BUFFERS_2048
#undef USE_CERT_BUFFERS_256
#define USE_CERT_BUFFERS_256
/* ------------------------------------------------------------------------- */
/* Debugging */
/* ------------------------------------------------------------------------- */
#undef DEBUG_WOLFSSL
//#define DEBUG_WOLFSSL
#ifdef DEBUG_WOLFSSL
/* Use this to measure / print heap usage */
#if 0
#undef USE_WOLFSSL_MEMORY
#define USE_WOLFSSL_MEMORY
#undef WOLFSSL_TRACK_MEMORY
#define WOLFSSL_TRACK_MEMORY
#define WOLFSSL_DEBUG_MEMORY
#define WOLFSSL_DEBUG_MEMORY_PRINT
#endif
#else
#undef NO_WOLFSSL_MEMORY
//#define NO_WOLFSSL_MEMORY
#undef NO_ERROR_STRINGS
//#define NO_ERROR_STRINGS
#endif
/* ------------------------------------------------------------------------- */
/* Port */
/* ------------------------------------------------------------------------- */
/* Override Current Time */
/* Allows custom "custom_time()" function to be used for benchmark */
#define WOLFSSL_USER_CURRTIME
/* ------------------------------------------------------------------------- */
/* RNG */
/* ------------------------------------------------------------------------- */
/* Size of returned HW RNG value */
#define NO_OLD_RNGNAME
/* Choose RNG method */
#if 1
#ifndef STM32_RNG
#define WOLFSSL_GENSEED_FORTEST
#endif
/* Use built-in P-RNG (SHA256 based) with HW RNG */
/* P-RNG + HW RNG (P-RNG is ~8K) */
#undef HAVE_HASHDRBG
#define HAVE_HASHDRBG
#else
/* Bypass P-RNG and use only HW RNG */
extern int custom_rand_generate_block(unsigned char* output, unsigned int sz);
#undef CUSTOM_RAND_GENERATE_BLOCK
#define CUSTOM_RAND_GENERATE_BLOCK custom_rand_generate_block
#endif
/* ------------------------------------------------------------------------- */
/* Enable Features */
/* ------------------------------------------------------------------------- */
#undef WOLFSSL_TLS13
#if 0
#define WOLFSSL_TLS13
#endif
#undef KEEP_PEER_CERT
//#define KEEP_PEER_CERT
#undef HAVE_COMP_KEY
//#define HAVE_COMP_KEY
#undef HAVE_TLS_EXTENSIONS
#define HAVE_TLS_EXTENSIONS
#undef HAVE_SUPPORTED_CURVES
#define HAVE_SUPPORTED_CURVES
#undef WOLFSSL_BASE64_ENCODE
//#define WOLFSSL_BASE64_ENCODE
/* TLS Session Cache */
#if 0
#define SMALL_SESSION_CACHE
#else
#define NO_SESSION_CACHE
#endif
/* ------------------------------------------------------------------------- */
/* Disable Features */
/* ------------------------------------------------------------------------- */
#undef NO_WOLFSSL_SERVER
//#define NO_WOLFSSL_SERVER
#undef NO_WOLFSSL_CLIENT
//#define NO_WOLFSSL_CLIENT
#undef NO_CRYPT_TEST
//#define NO_CRYPT_TEST
#undef NO_CRYPT_BENCHMARK
//#define NO_CRYPT_BENCHMARK
/* In-lining of misc.c functions */
/* If defined, must include wolfcrypt/src/misc.c in build */
/* Slower, but about 1k smaller */
#undef NO_INLINE
//#define NO_INLINE
#undef NO_FILESYSTEM
#define NO_FILESYSTEM
#undef NO_WRITEV
#define NO_WRITEV
#undef NO_MAIN_DRIVER
#define NO_MAIN_DRIVER
#undef NO_DEV_RANDOM
#define NO_DEV_RANDOM
#undef NO_DSA
#define NO_DSA
#undef NO_RC4
#define NO_RC4
#undef NO_OLD_TLS
#define NO_OLD_TLS
#undef NO_HC128
#define NO_HC128
#undef NO_RABBIT
#define NO_RABBIT
#undef NO_PSK
#define NO_PSK
#undef NO_MD4
#define NO_MD4
#undef NO_PWDBASED
#define NO_PWDBASED
#undef NO_CODING
//#define NO_CODING
/* bypass certificate date checking, due to lack of properly configured RTC source */
#undef NO_ASN_TIME
#define NO_ASN_TIME
#ifdef __cplusplus
}
#endif
#endif /* WOLFSSL_USER_SETTINGS_H */

58
IDE/OPENSTM32/README.md
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@ -1,58 +0,0 @@
# wolfSSL STM32 Example for System Workbench for STM32 (Open STM32 Tools)
This example includes:
* wolfCrypt test
* wolfCrypt benchmark
* wolfSSL TLS client/server test using in-memory transfers
These examples use the CubeMX Hal for STM32. If you'd like to use the older Standard Peripheral library undefine `WOLFSSL_STM32_CUBEMX` in `user_settings.h`.
## Requirements
* STM32CubeMX: STM32 CubeMX HAL code generation tool - [http://www.st.com/en/development-tools/stm32cubemx.html](http://www.st.com/en/development-tools/stm32cubemx.html)
* SystemWorkbench for STM32 - [http://www.st.com/en/development-tools/sw4stm32.html](http://www.st.com/en/development-tools/sw4stm32.html)
## Setup
1. Using the STM32CubeMX tool, load the `<wolfssl-root>/IDE/OPENSTM32/wolfSTM32.ioc` file.
2. Adjust the HAL options based on your specific micro-controller.
3. Generate source code.
4. Run `SystemWorkbench` and choose a new workspace location for this project.
5. Import `wolfSTM32` project from `<wolfssl-root>/IDE/OPENSTM32/`.
6. Adjust the micro-controller define in `Project Settings -> C/C++ General -> Paths and Symbols -> Symbols -> GNU C`. Example uses `STM32F437xx`, but should be changed to reflect your micro-controller type.
7. Build and Run
If you hardware support crypto acceleration then:
1. Manually copy over the CubeMX HAL files for `stm32f4xx_hal_cryp.c`, `stm32f4xx_hal_cryp_ex.c`, `stm32f4xx_hal_cryp.h`, `stm32f4xx_hal_cryp_ex.h`.
2. Uncomment the `#define HAL_CRYP_MODULE_ENABLED` line in `stm32f4xx_hal_conf.h`.
## Configuration
The settings for the wolfSTM32 project are located in `<wolfssl-root>/IDE/OPENSTM32/Inc/user_settings.h`.
* To enable STM32F2 support define `WOLFSSL_STM32F2`.
* To enable STM32F4 support define `WOLFSSL_STM32F4`.
* To enable STM32F7 support define `WOLFSSL_STM32F7`.
* To enable STM32L4 support define `WOLFSSL_STM32L4`.
If you are using FreeRTOS make sure your `FreeRTOSConfig.h` has its `configTOTAL_HEAP_SIZE` increased.
The TLS client/server benchmark example requires about 76 KB for allocated tasks (with stack) and peak heap.
## Example Output
```
....MENU
.t. WolfCrypt Test
.b. WolfCrypt Benchmark
.l. WolfSSL TLS Bench
.e. Show Cipher List
Please select one of the above options:
```
## Support
For questions please email [support@wolfssl.com](mailto:support@wolfssl.com)

353
IDE/OPENSTM32/Src/main.c
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/* main.c
*
* Copyright (C) 2006-2020 wolfSSL Inc.
*
* This file is part of wolfSSL.
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
/* Includes ------------------------------------------------------------------*/
#include "wolfssl_example.h"
/* Private variables ---------------------------------------------------------*/
RNG_HandleTypeDef hrng;
RTC_HandleTypeDef hrtc;
SPI_HandleTypeDef hspi1;
UART_HandleTypeDef huart4;
CRYP_HandleTypeDef CrypHandle;
HASH_HandleTypeDef HashHandle;
osThreadId defaultTaskHandle;
int __errno;
/* Private function prototypes -----------------------------------------------*/
static void SystemClock_Config(void);
static void Error_Handler(void);
static void MX_GPIO_Init(void);
static void MX_RNG_Init(void);
static void MX_RTC_Init(void);
static void MX_SPI1_Init(void);
static void MX_UART4_Init(void);
int main(void)
{
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* Configure the system clock */
SystemClock_Config();
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_RNG_Init();
MX_RTC_Init();
MX_SPI1_Init();
MX_UART4_Init();
#ifndef FREERTOS
wolfCryptDemo(NULL);
#else
/* Create the thread(s) */
/* definition and creation of defaultTask */
osThreadDef(defaultTask, wolfCryptDemo, osPriorityNormal, 0, WOLF_EXAMPLES_STACK);
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
/* Start scheduler */
osKernelStart();
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
while (1) {}
#endif
}
/** System Clock Configuration
*/
static void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE|RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 15;
RCC_OscInitStruct.PLL.PLLN = 144;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 5;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
}
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
{
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
{
Error_Handler();
}
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
/* SysTick_IRQn interrupt configuration */
HAL_NVIC_SetPriority(SysTick_IRQn, 15, 0);
}
/* RNG init function */
static void MX_RNG_Init(void)
{
hrng.Instance = RNG;
if (HAL_RNG_Init(&hrng) != HAL_OK)
{
Error_Handler();
}
}
/* RTC init function */
#define RTC_ASYNCH_PREDIV 0x7F /* LSE as RTC clock */
#define RTC_SYNCH_PREDIV 0x00FF /* LSE as RTC clock */
static void MX_RTC_Init(void)
{
RTC_TimeTypeDef sTime;
RTC_DateTypeDef sDate;
/**Initialize RTC and set the Time and Date
*/
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
hrtc.Init.SynchPrediv = RTC_SYNCH_PREDIV;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if (HAL_RTC_Init(&hrtc) != HAL_OK)
{
Error_Handler();
}
sTime.Hours = 0x0;
sTime.Minutes = 0x0;
sTime.Seconds = 0x0;
sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
sTime.StoreOperation = RTC_STOREOPERATION_RESET;
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
sDate.WeekDay = RTC_WEEKDAY_MONDAY;
sDate.Month = RTC_MONTH_JANUARY;
sDate.Date = 0x1;
sDate.Year = 0x0;
if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK)
{
Error_Handler();
}
/**Enable the TimeStamp
*/
if (HAL_RTCEx_SetTimeStamp(&hrtc, RTC_TIMESTAMPEDGE_RISING, RTC_TIMESTAMPPIN_DEFAULT) != HAL_OK)
{
Error_Handler();
}
/**Enable the reference Clock input
*/
if (HAL_RTCEx_SetRefClock(&hrtc) != HAL_OK)
{
Error_Handler();
}
}
/* SPI1 init function */
static void MX_SPI1_Init(void)
{
hspi1.Instance = SPI1;
hspi1.Init.Mode = SPI_MODE_MASTER;
hspi1.Init.Direction = SPI_DIRECTION_2LINES;
hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_HARD_OUTPUT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
hspi1.Init.CRCPolynomial = 10;
if (HAL_SPI_Init(&hspi1) != HAL_OK)
{
Error_Handler();
}
}
/* UART4 init function */
static void MX_UART4_Init(void)
{
huart4.Instance = UART4;
huart4.Init.BaudRate = 115200;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart4) != HAL_OK)
{
Error_Handler();
}
// Turn off buffers, so I/O occurs immediately
setvbuf(stdin, NULL, _IONBF, 0);
setvbuf(stdout, NULL, _IONBF, 0);
setvbuf(stderr, NULL, _IONBF, 0);
}
int _write (int fd, char *ptr, int len)
{
(void)fd;
/* Write "len" of char from "ptr" to file id "fd"
* Return number of char written.
* Need implementing with UART here. */
HAL_UART_Transmit(&huart4, (uint8_t *)ptr, len, 0xFFFF);
return len;
}
int _read (int fd, char *ptr, int len)
{
/* Read "len" of char to "ptr" from file id "fd"
* Return number of char read.
* Need implementing with UART here. */
(void)fd;
return HAL_UART_Receive(&huart4, (uint8_t*)ptr, len, 0xFFFF);
}
void _ttywrch(int ch) {
/* Write one char "ch" to the default console
* Need implementing with UART here. */
_write(0, (char*)&ch, 1);
}
/** Configure pins as
* Analog
* Input
* Output
* EVENT_OUT
* EXTI
*/
static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOE_CLK_ENABLE();
__HAL_RCC_GPIOG_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
__HAL_RCC_GPIOC_CLK_ENABLE();
__HAL_RCC_GPIOH_CLK_ENABLE();
}
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM1 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
if (htim->Instance == TIM1) {
HAL_IncTick();
}
}
/**
* @brief This function is executed in case of error occurrence.
* @param None
* @retval None
*/
static void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler */
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
/* USER CODE END Error_Handler */
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t* file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif

14
IDE/OPENSTM32/include.am
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@ -1,14 +0,0 @@
# vim:ft=automake
# included from Top Level Makefile.am
# All paths should be given relative to the root
EXTRA_DIST+= IDE/OPENSTM32/README.md
EXTRA_DIST+= IDE/OPENSTM32/.cproject
EXTRA_DIST+= IDE/OPENSTM32/.project
EXTRA_DIST+= IDE/OPENSTM32/wolfSTM32.cfg
EXTRA_DIST+= IDE/OPENSTM32/wolfSTM32.ioc
EXTRA_DIST+= IDE/OPENSTM32/wolfSTM32.xml
EXTRA_DIST+= IDE/OPENSTM32/Src/main.c
EXTRA_DIST+= IDE/OPENSTM32/Src/wolfssl_example.c
EXTRA_DIST+= IDE/OPENSTM32/Inc/user_settings.h
EXTRA_DIST+= IDE/OPENSTM32/Inc/wolfssl_example.h

13
IDE/OPENSTM32/wolfSTM32.cfg
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@ -1,13 +0,0 @@
# This is an wolfSTM32 board with a single STM32F437IIHx chip.
# Generated by System Workbench for STM32
source [find interface/stlink-v2-1.cfg]
set WORKAREASIZE 0x30000
transport select "hla_jtag"
set CPUTAPID 0x4ba00477
source [find target/stm32f4x_stlink.cfg]
# use hardware reset, connect under reset
reset_config srst_only srst_nogate

213
IDE/OPENSTM32/wolfSTM32.ioc
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@ -1,213 +0,0 @@
#MicroXplorer Configuration settings - do not modify
FREERTOS.IPParameters=Tasks01
FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default
File.Version=6
KeepUserPlacement=false
LWIP.Version=v1.5.0_RC0_20160211_Cube
Mcu.Family=STM32F4
Mcu.IP0=CRC
Mcu.IP1=ETH
Mcu.IP2=FREERTOS
Mcu.IP3=LWIP
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SYS
Mcu.IP9=UART4
Mcu.IPNb=10
Mcu.Name=STM32F437I(G-I)Hx
Mcu.Package=UFBGA176
Mcu.Pin0=PE2
Mcu.Pin1=PG14
Mcu.Pin10=PC10
Mcu.Pin11=PC13
Mcu.Pin12=PC14/OSC32_IN
Mcu.Pin13=PC15/OSC32_OUT
Mcu.Pin14=PH2
Mcu.Pin15=PH0/OSC_IN
Mcu.Pin16=PH3
Mcu.Pin17=PH1/OSC_OUT
Mcu.Pin18=PC1
Mcu.Pin19=PC2
Mcu.Pin2=PG13
Mcu.Pin20=PC3
Mcu.Pin21=PH6
Mcu.Pin22=PA1
Mcu.Pin23=PC4
Mcu.Pin24=PH7
Mcu.Pin25=PA2
Mcu.Pin26=PC5
Mcu.Pin27=PA7
Mcu.Pin28=PB15
Mcu.Pin29=VP_CRC_VS_CRC
Mcu.Pin3=PB4
Mcu.Pin30=VP_FREERTOS_VS_ENABLE
Mcu.Pin31=VP_LWIP_VS_Enabled
Mcu.Pin32=VP_RNG_VS_RNG
Mcu.Pin33=VP_SYS_VS_tim1
Mcu.Pin4=PB3
Mcu.Pin5=PA15
Mcu.Pin6=PA14
Mcu.Pin7=PA13
Mcu.Pin8=PG11
Mcu.Pin9=PC11
Mcu.PinsNb=34
Mcu.UserConstants=
Mcu.UserName=STM32F437IIHx
MxCube.Version=4.16.1
MxDb.Version=DB.4.0.161
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.ETH_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:true
NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:true\:false
NVIC.TimeBase=TIM1_UP_TIM10_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false
PA1.Mode=MII
PA1.Signal=ETH_RX_CLK
PA13.Mode=JTAG_5_pins
PA13.Signal=SYS_JTMS-SWDIO
PA14.Mode=JTAG_5_pins
PA14.Signal=SYS_JTCK-SWCLK
PA15.Mode=JTAG_5_pins
PA15.Signal=SYS_JTDI
PA2.Mode=MII
PA2.Signal=ETH_MDIO
PA7.Mode=MII
PA7.Signal=ETH_RX_DV
PB15.Mode=Reference_Clock_Detection_Activate
PB15.Signal=RTC_REFIN
PB3.Mode=JTAG_5_pins
PB3.Signal=SYS_JTDO-SWO
PB4.Mode=JTAG_5_pins
PB4.Signal=SYS_JTRST
PC1.Mode=MII
PC1.Signal=ETH_MDC
PC10.Mode=Asynchronous
PC10.Signal=UART4_TX
PC11.Mode=Asynchronous
PC11.Signal=UART4_RX
PC13.Mode=Timestamp enabled - Input Enabled to AF1
PC13.Signal=RTC_AF1
PC14/OSC32_IN.Mode=LSE-External-Oscillator
PC14/OSC32_IN.Signal=RCC_OSC32_IN
PC15/OSC32_OUT.Mode=LSE-External-Oscillator
PC15/OSC32_OUT.Signal=RCC_OSC32_OUT
PC2.Mode=MII
PC2.Signal=ETH_TXD2
PC3.Mode=MII
PC3.Signal=ETH_TX_CLK
PC4.Mode=MII
PC4.Signal=ETH_RXD0
PC5.Mode=MII
PC5.Signal=ETH_RXD1
PCC.Checker=false
PCC.Line=STM32F427/437
PCC.MCU=STM32F437I(G-I)Hx
PCC.MXVersion=4.16.1
PCC.PartNumber=STM32F437IIHx
PCC.Seq0=0
PCC.Series=STM32F4
PCC.Temperature=25
PCC.Vdd=null
PE2.Mode=MII
PE2.Signal=ETH_TXD3
PG11.Mode=MII
PG11.Signal=ETH_TX_EN
PG13.Mode=MII
PG13.Signal=ETH_TXD0
PG14.Mode=MII
PG14.Signal=ETH_TXD1
PH0/OSC_IN.Mode=HSE-External-Oscillator
PH0/OSC_IN.Signal=RCC_OSC_IN
PH1/OSC_OUT.Mode=HSE-External-Oscillator
PH1/OSC_OUT.Signal=RCC_OSC_OUT
PH2.Mode=MII
PH2.Signal=ETH_CRS
PH3.Mode=MII
PH3.Signal=ETH_COL
PH6.Mode=MII
PH6.Signal=ETH_RXD2
PH7.Mode=MII
PH7.Signal=ETH_RXD3
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=2
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F437IIHx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.13.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x10000
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.PreviousToolchain=SW4STM32
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=wolfSTM32.ioc
ProjectManager.ProjectName=wolfSTM32
ProjectManager.StackSize=0x4000
ProjectManager.TargetToolchain=SW4STM32
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false,2-MX_CRC_Init-CRC-false,3-MX_RNG_Init-RNG-false,4-MX_UART4_Init-UART4-false,5-MX_LWIP_Init-LWIP-false,6-MX_RTC_Init-RTC-false
RCC.48MHZClocksFreq_Value=48000000
RCC.AHBFreq_Value=120000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=30000000
RCC.APB1TimFreq_Value=60000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=60000000
RCC.APB2TimFreq_Value=120000000
RCC.CortexFreq_Value=120000000
RCC.EthernetFreq_Value=120000000
RCC.FCLKCortexFreq_Value=120000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=120000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=160000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLSourceVirtual,RCC_RTC_Clock_Source,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=120000000
RCC.PLLCLKFreq_Value=120000000
RCC.PLLM=15
RCC.PLLN=144
RCC.PLLQ=5
RCC.PLLQCLKFreq_Value=48000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.RCC_RTC_Clock_Source=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.RTCHSEDivFreq_Value=12500000
RCC.SAI_AClocksFreq_Value=20416666.666666668
RCC.SAI_BClocksFreq_Value=20416666.666666668
RCC.SYSCLKFreq_VALUE=120000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.VCOI2SOutputFreq_Value=320000000
RCC.VCOInputFreq_Value=1666666.6666666667
RCC.VCOOutputFreq_Value=240000000
RCC.VCOSAIOutputFreq_Value=81666666.66666667
RCC.VCOSAIOutputFreq_ValueQ=20416666.666666668
RCC.VcooutputI2S=160000000
RCC.VcooutputI2SQ=160000000
VP_CRC_VS_CRC.Mode=CRC_Activate
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
VP_FREERTOS_VS_ENABLE.Mode=Enabled
VP_FREERTOS_VS_ENABLE.Signal=FREERTOS_VS_ENABLE
VP_LWIP_VS_Enabled.Mode=Enabled
VP_LWIP_VS_Enabled.Signal=LWIP_VS_Enabled
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
board=wolfSTM32

9
IDE/OPENSTM32/wolfSTM32.xml
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@ -1,9 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<targetDefinitions xmlns="http://openstm32.org/stm32TargetDefinitions" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://openstm32.org/stm32TargetDefinitions stm32TargetDefinitions.xsd">
<board id="wolfstm32">
<name>wolfSTM32</name>
<mcuId>stm32f437iihx</mcuId>
<dbgIF>JTAG</dbgIF>
<dbgDEV>ST-LinkV2-1</dbgDEV>
</board>
</targetDefinitions>

175
IDE/Renesas/e2studio/RA6M3/README.md Normal file
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@ -0,0 +1,175 @@
wolfSSL for Renesas RA Evaluation Kit (EK-RA6M3G)
=================================================
## Description
This directory contains e2studio projects targeted at the Renesas RA 32-bit MCUs.\
The example projects include a wolfSSL TLS 1.2 client and server.\
They also include benchmark and cryptography tests for the wolfCrypt library.
The wolfssl project contains both the wolfSSL and wolfCrypt libraries.\
It is built as a `Renesas RA C Library Project` and contains the Renesas RA\
configuration.
The other projects (benchmark, client, server and test) are built as a\
`Renesas RA C Project Using RA Library`, where the RA library is the wolfssl project.\
The wolfssl Project Summary is listed below and is relevant for every project.
#### Project Summary
`Board: EK-RA6M3G`\
`Device: R7FA6M3AH3CFC`\
`Toolchain: GCC ARM Embedded`\
`FSP Version: 0.8.0`
##### Selected software components
`Board Support Package Common Files v0.8.0`\
`Arm CMSIS Version 5 - Core (M) v5.5.1`\
`Amazon FreeRTOS v0.8.0`\
`RA6M3G-EK Board Support Files v0.8.0`\
`Board support package for R7FA6M3AH3CFC v0.8.0`\
`Board support package for RA6M3 v0.8.0`\
`Board support package for RA6M3 v0.8.0`\
`Amazon FreeRTOS - Memory Management - Heap 4 v0.8.0`\
`r_ether to FreeRTOS+TCP Wrapper v0.8.0`\
`Ethernet v0.8.0`\
`Ethernet PHY v0.8.0`\
`FreeRTOS+TCP v0.8.0`\
`Amazon FreeRTOS - Buffer Allocation 2 v0.8.0`
## Setup Steps
The project directories are missing files necessary to build the project.\
These files can be generated when creating a new Renesas RA Project.\
The following steps explain how to generate the missing files and where to place them.
1.) Create a 'dummy' Renesas RA C Library Project.
+ Click File->New->`RA C/C++ Project`
+ Click `Renesas RA C Library Project`. Click Next
+ Enter `dummy_library` as the project name. Click Next.
+ Under `Board: Custom User Board`, select `EK-RA6M3G`.
+ Under `RTOS: No RTOS`, select `Amazon FreeRTOS`.
+ Click Next. Select `Amazon FreeRTOS - Minimal - Static Allocation`
+ Click Finish.
2.) Create a 'dummy' Renesas RA C Project Using RA Library.
+ Click File->New->`RA C/C++ Project`
+ Click `Renesas RA C Project Using RA Library`. Click Next
+ Enter `dummy_app` as the project name. Click Next.
+ Under `RA library project`, select `dummy_library`.
+ Click Finish.
3.) Import all the wolfSSL Projects into e2studio workspace.
+ Click File->`Open Projects from File System`
+ Click `Directory...` to the right of Import source
+ Select the RA6M3G folder location that contains the projects\
example path: wolfssl/IDE/Renesas/e2studio/RA6M3
+ Deselect the Non-Eclipse project, RA6M3G, by clicking the checkbox\
Only the folders with 'Eclipse project' under 'Import as' need to be selected.
+ Click Finish.
4.) Copy files from `dummy_library` into `wolfSSL_RA6M3G`
+ Expand the dummy_library and wolfSSL_RA6M3G projects\
(Click the drop-down arrow to the left of the project name.)
+ Select and Copy the following folders/files inside dummy_library\
` ra/`\
` ra_gen/`\
` ra_cfg/`\
` script/`\
` R7FA6M3AH3CFC.pincfg`\
` RA6M3G-EK.pingcfg`
+ Paste the copied folders/files into wolfSSL_RA6M3G
+ The `dummy_library` project can now be deleted.
+ Generate Project Content.
+ Click `Open RA Configuration` in the top bar (Grey Settings Cog)
+ Click `Generate Project Content` at top right (Green Icon)
+ Build wolfSSL_RA6M3G.
5.) Copy files from `dummy_app` into `./IDE/Renesas/e2studio/RA6M3/common/ra6m3g/`\
**NOTE:** This may need to be done outside of the e2studio environment (e.g. File Explorer).
+ Select and Copy the followng folder inside dummy_app\
` src/`\
` script/`
+ Paste the copied folders into `./IDE/Renesas/e2studio/RA6M3/common/ra6m3g/`\
` (The test, benchmark, client and server projects link to this folder.)`
+ The `dummy_app` project can now be deleted.
6.) Setup Network Environment
The client and server projects have defines inside their wolfssl_thread_entry.h.
These defines (ucIPAddress ... ucDNSServerAddress) may need to be changed
based on your internal network environment. The g_ether0_mac_address is the default
mac address found inside the RA configuration inside the wolfssl project.
The client wolfssl_thread_entry.h has defines (SERVER_IP and DEFAULT_PORT) that
will need to be changed based on the server you're trying to connect to over
the ethernet connection.
## Build and Run
### Build Each Project
Right-Click each Project and select Build.
### Run wolfCrypt Test and Benchmark
1.) Right-Click the Project name.\
2.) Select `Debug As` -> `Renesas GDB Hardware Debugging`\
3.) Select J-Link ARM. Click OK.\
4.) Select R7Fa6M3AH. Click OK.
### Run the wolfSSL TLS Server Example.
1.) Right-Click the Project name.\
2.) Select `Debug As` -> `Renesas GDB Hardware Debugging`\
3.) Select J-Link ARM. Click OK.\
4.) Select R7Fa6M3AH. Click OK.\
5.) Run the following wolfSSL example client command inside the base of the wolfssl directory.
```
./examples/client/client -h "ucIPAddress" -p 11111 -A ./certs/1024/ca-cert.pem
```
**NOTE:** "ucIPAddress" is "192.168.1.241" by default. (See wolfssl_thread_entry.h)
### Run the wolfSSL TLS Client Example.
1.) Run the following wolfSSL example server command inside the base of the wolfssl directory.
```
./examples/server/server -b -d -p 11111 -c ./certs/1024/server-cert.pem -k ./certs/1024/server-key.pem
```
**NOTE:** The port 11111 is the DEFAULT_PORT inside wolfssl_thread_entry.h.\
If DEFAULT_PORT was changed then the above command will need to match it.
2.) Right-Click the Project name.\
3.) Select `Debug As` -> `Renesas GDB Hardware Debugging`\
4.) Select J-Link ARM. Click OK.\
5.) Select R7Fa6M3AH. Click OK.
## Troubleshooting
* The commands for the example client/server assumes it is being run from the
base directory of wolfssl.
* Enter "#define DEBUG_WOLFSSL" inside user_settings.h or wolfssl_thread_entry.c\
to enable wolfssl debug messages to the Renesas Virtual Debug Console.
* Some linking errors can be caused by the e2studio project files needing to be rebuilt and freshened.
Right-Click a project, select Index, click Rebuild and then click Freshen Files. Repeat for each project.
[Support Forum](https://www.wolfssl.com/forums/)
Support Email: support@wolfssl.com
## Resources
[wolfSSL Website](https://www.wolfssl.com/)
[wolfSSL Wiki](https://github.com/wolfSSL/wolfssl/wiki)
[wolfSSL Manual](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-toc.html)
[wolfSSL API Reference](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-17-wolfssl-api-reference.html)
[wolfCrypt API Reference](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-18-wolfcrypt-api-reference.html)
[TLS 1.3](https://www.wolfssl.com/docs/tls13/)

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# vim:ft=automake
# included from Top Level Makefile.am
# All paths should be given relative to the root
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/benchmark-wolfcrypt/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/benchmark-wolfcrypt/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/benchmark-wolfcrypt/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/client-wolfssl/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/client-wolfssl/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/client-wolfssl/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/client-wolfssl/wolfssl_thread_entry.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/common/ra6m3g/README.md
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/common/src/freertos_tcp_port.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/common/user_settings.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/common/util.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/server-wolfssl/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/server-wolfssl/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/server-wolfssl/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/server-wolfssl/wolfssl_thread_entry.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/test-wolfcrypt/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/test-wolfcrypt/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/test-wolfcrypt/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/wolfssl/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/wolfssl/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/wolfssl/configuration.xml
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3/README.md
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/README.md

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wolfSSL for Renesas RA Evaluation Kit (EK-RA6M3G)
=================================================
## Description
This directory contains e2studio projects targeted at the Renesas RA 32-bit MCUs.\
The example projects include a wolfSSL TLS 1.2 client and server.\
They also include benchmark and cryptography tests for the wolfCrypt library.
The wolfssl project contains both the wolfSSL and wolfCrypt libraries.\
It is built as a `Renesas RA C Library Project` and contains the Renesas RA\
configuration.
The other projects (benchmark, client, server and test) are built as a\
`Renesas RA C Project Using RA Library`, where the RA library is the wolfssl project.\
The wolfssl Project Summary is listed below and is relevant for every project.
#### Project Summary
`Board: EK-RA6M3G`\
`Device: R7FA6M3AH3CFC`\
`Toolchain: GCC ARM Embedded`\
`FSP Version: 0.8.0`
##### Selected software components
`Board Support Package Common Files v0.8.0`\
`Arm CMSIS Version 5 - Core (M) v5.5.1`\
`Amazon FreeRTOS v0.8.0`\
`RA6M3G-EK Board Support Files v0.8.0`\
`Board support package for R7FA6M3AH3CFC v0.8.0`\
`Board support package for RA6M3 v0.8.0`\
`Board support package for RA6M3 v0.8.0`\
`Amazon FreeRTOS - Memory Management - Heap 4 v0.8.0`\
`r_ether to FreeRTOS+TCP Wrapper v0.8.0`\
`Ethernet v0.8.0`\
`Ethernet PHY v0.8.0`\
`FreeRTOS+TCP v0.8.0`\
`Amazon FreeRTOS - Buffer Allocation 2 v0.8.0`
## Setup Steps
The project directories are missing files necessary to build the project.\
These files can be generated when creating a new Renesas RA Project.\
The following steps explain how to generate the missing files and where to place them.
1.) Create a 'dummy' Renesas RA C Library Project.
+ Click File->New->`RA C/C++ Project`
+ Click `Renesas RA C Library Project`. Click Next
+ Enter `dummy_library` as the project name. Click Next.
+ Under `Board: Custom User Board`, select `EK-RA6M3G`.
+ Under `RTOS: No RTOS`, select `Amazon FreeRTOS`.
+ Click Next. Select `Amazon FreeRTOS - Minimal - Static Allocation`
+ Click Finish.
2.) Create a 'dummy' Renesas RA C Project Using RA Library.
+ Click File->New->`RA C/C++ Project`
+ Click `Renesas RA C Project Using RA Library`. Click Next
+ Enter `dummy_app` as the project name. Click Next.
+ Under `RA library project`, select `dummy_library`.
+ Click Finish.
3.) Import all the wolfSSL Projects into e2studio workspace.
+ Click File->`Open Projects from File System`
+ Click `Directory...` to the right of Import source
+ Select the RA6M3G folder location that contains the projects\
example path: wolfssl/IDE/Renesas/e2studio/RA6M3G
+ Deselect the Non-Eclipse project, RA6M3G, by clicking the checkbox\
Only the folders with 'Eclipse project' under 'Import as' need to be selected.
+ Click Finish.
4.) Copy files from `dummy_library` into `wolfSSL_RA6M3G`
+ Expand the dummy_library and wolfSSL_RA6M3G projects\
(Click the drop-down arrow to the left of the project name.)
+ Select and Copy the following folders/files inside dummy_library\
` ra/`\
` ra_gen/`\
` ra_cfg/`\
` script/`\
` R7FA6M3AH3CFC.pincfg`\
` RA6M3G-EK.pingcfg`
+ Paste the copied folders/files into wolfSSL_RA6M3G
+ The `dummy_library` project can now be deleted.
+ Generate Project Content.
+ Click `Open RA Configuration` in the top bar (Grey Settings Cog)
+ Click `Generate Project Content` at top right (Green Icon)
+ Build wolfSSL_RA6M3G.
5.) Copy files from `dummy_app` into `./IDE/Renesas/e2studio/RA6M3G/common/ra6m3g/`\
**NOTE:** This may need to be done outside of the e2studio environment (e.g. File Explorer).
+ Select and Copy the followng folder inside dummy_app\
` src/`\
` script/`
+ Paste the copied folders into `./IDE/Renesas/e2studio/RA6M3G/common/ra6m3g/`\
` (The test, benchmark, client and server projects link to this folder.)`
+ The `dummy_app` project can now be deleted.
6.) Setup Network Environment
The client and server projects have defines inside their wolfssl_thread_entry.h.
These defines (ucIPAddress ... ucDNSServerAddress) may need to be changed
based on your internal network environment. The g_ether0_mac_address is the default
mac address found inside the RA configuration inside the wolfssl project.
The client wolfssl_thread_entry.h has defines (SERVER_IP and DEFAULT_PORT) that
will need to be changed based on the server you're trying to connect to over
the ethernet connection.
## Build and Run
### Build Each Project
Right-Click each Project and select Build.
### Run wolfCrypt Test and Benchmark
1.) Right-Click the Project name.\
2.) Select `Debug As` -> `Renesas GDB Hardware Debugging`\
3.) Select J-Link ARM. Click OK.\
4.) Select R7Fa6M3AH. Click OK.
### Run the wolfSSL TLS Server Example.
1.) Right-Click the Project name.\
2.) Select `Debug As` -> `Renesas GDB Hardware Debugging`\
3.) Select J-Link ARM. Click OK.\
4.) Select R7Fa6M3AH. Click OK.\
5.) Run the following wolfSSL example client command inside the base of the wolfssl directory.
```
./examples/client/client -h "ucIPAddress" -p 11111 -A ./certs/1024/ca-cert.pem
```
**NOTE:** "ucIPAddress" is "192.168.1.241" by default. (See wolfssl_thread_entry.h)
### Run the wolfSSL TLS Client Example.
1.) Run the following wolfSSL example server command inside the base of the wolfssl directory.
```
./examples/server/server -b -d -p 11111 -c ./certs/1024/server-cert.pem -k ./certs/1024/server-key.pem
```
**NOTE:** The port 11111 is the DEFAULT_PORT inside wolfssl_thread_entry.h.\
If DEFAULT_PORT was changed then the above command will need to match it.
2.) Right-Click the Project name.\
3.) Select `Debug As` -> `Renesas GDB Hardware Debugging`\
4.) Select J-Link ARM. Click OK.\
5.) Select R7Fa6M3AH. Click OK.
## Troubleshooting
* The commands for the example client/server assumes it is being run from the
base directory of wolfssl.
* Enter "#define DEBUG_WOLFSSL" inside user_settings.h or wolfssl_thread_entry.c\
to enable wolfssl debug messages to the Renesas Virtual Debug Console.
* Some linking errors can be caused by the e2studio project files needing to be rebuilt and freshened.
Right-Click a project, select Index, click Rebuild and then click Freshen Files. Repeat for each project.
[Support Forum](https://www.wolfssl.com/forums/)
Support Email: support@wolfssl.com
## Resources
[wolfSSL Website](https://www.wolfssl.com/)
[wolfSSL Wiki](https://github.com/wolfSSL/wolfssl/wiki)
[wolfSSL Manual](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-toc.html)
[wolfSSL API Reference](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-17-wolfssl-api-reference.html)
[wolfCrypt API Reference](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-18-wolfcrypt-api-reference.html)
[TLS 1.3](https://www.wolfssl.com/docs/tls13/)
[Moved to ../RA6M3/README.md](../RA6M3/README.md)

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# vim:ft=automake
# included from Top Level Makefile.am
# All paths should be given relative to the root
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/benchmark-wolfcrypt/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/benchmark-wolfcrypt/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/benchmark-wolfcrypt/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/client-wolfssl/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/client-wolfssl/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/client-wolfssl/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/client-wolfssl/wolfssl_thread_entry.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/common/ra6m3g/README.md
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/common/src/freertos_tcp_port.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/common/user_settings.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/common/util.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/server-wolfssl/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/server-wolfssl/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/server-wolfssl/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/server-wolfssl/wolfssl_thread_entry.h
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/test-wolfcrypt/src/wolfssl_thread_entry.c
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/test-wolfcrypt/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/test-wolfcrypt/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/wolfssl/.cproject
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/wolfssl/.project
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/wolfssl/configuration.xml
EXTRA_DIST+= IDE/Renesas/e2studio/RA6M3G/README.md

128
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#MicroXplorer Configuration settings - do not modify
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=122880
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=FREERTOS
Mcu.IP1=NVIC
Mcu.IP2=RCC
Mcu.IP3=RNG
Mcu.IP4=RTC
Mcu.IP5=SYS
Mcu.IP6=USART2
Mcu.IPNb=7
Mcu.Name=STM32F407V(E-G)Tx
Mcu.Package=LQFP100
Mcu.Pin0=PA2
Mcu.Pin1=PA3
Mcu.Pin2=PC10
Mcu.Pin3=PC11
Mcu.Pin4=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin5=VP_RNG_VS_RNG
Mcu.Pin6=VP_RTC_VS_RTC_Activate
Mcu.Pin7=VP_SYS_VS_tim1
Mcu.Pin8=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.PinsNb=9
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32F407VGTx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_TIM10_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA2.Mode=Asynchronous
PA2.Signal=USART2_TX
PA3.Mode=Asynchronous
PA3.Signal=USART2_RX
PC10.Locked=true
PC10.Signal=UART4_TX
PC11.Locked=true
PC11.Signal=UART4_RX
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F407VGTx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32F407.ioc
ProjectManager.ProjectName=STM32F407
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=2-SystemClock_Config-RCC-false-HAL-false
RCC.AHBFreq_Value=16000000
RCC.APB1Freq_Value=16000000
RCC.APB2Freq_Value=16000000
RCC.CortexFreq_Value=16000000
RCC.FamilyName=M
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=96000000
RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,CortexFreq_Value,FamilyName,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.PLLCLKFreq_Value=96000000
RCC.PLLQCLKFreq_Value=48000000
RCC.RTCFreq_Value=32000
RCC.RTCHSEDivFreq_Value=12500000
RCC.SYSCLKFreq_VALUE=16000000
RCC.VCOI2SOutputFreq_Value=192000000
RCC.VCOInputFreq_Value=1000000
RCC.VCOOutputFreq_Value=192000000
RCC.VcooutputI2S=96000000
USART2.IPParameters=VirtualMode
USART2.VirtualMode=VM_ASYNC
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=custom
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

308
IDE/STM32Cube/Boards/STM32F437.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=131072
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F4
Mcu.IP0=CRYP
Mcu.IP1=FMC
Mcu.IP2=FREERTOS
Mcu.IP3=HASH
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SYS
Mcu.IP9=UART4
Mcu.IPNb=10
Mcu.Name=STM32F437I(G-I)Hx
Mcu.Package=UFBGA176
Mcu.Pin0=PE3
Mcu.Pin1=PD7
Mcu.Pin10=PF1
Mcu.Pin11=PF3
Mcu.Pin12=PF4
Mcu.Pin13=PF5
Mcu.Pin14=PG5
Mcu.Pin15=PG4
Mcu.Pin16=PG3
Mcu.Pin17=PD15
Mcu.Pin18=PG2
Mcu.Pin19=PG1
Mcu.Pin2=PD0
Mcu.Pin20=PD14
Mcu.Pin21=PD13
Mcu.Pin22=PF13
Mcu.Pin23=PG0
Mcu.Pin24=PE13
Mcu.Pin25=PD12
Mcu.Pin26=PD11
Mcu.Pin27=PD10
Mcu.Pin28=PF12
Mcu.Pin29=PF15
Mcu.Pin3=PC11
Mcu.Pin30=PE8
Mcu.Pin31=PE9
Mcu.Pin32=PE11
Mcu.Pin33=PE14
Mcu.Pin34=PD9
Mcu.Pin35=PD8
Mcu.Pin36=PF14
Mcu.Pin37=PE7
Mcu.Pin38=PE10
Mcu.Pin39=PE12
Mcu.Pin4=PC10
Mcu.Pin40=PE15
Mcu.Pin41=VP_CRYP_VS_CRYP
Mcu.Pin42=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin43=VP_HASH_VS_HASH
Mcu.Pin44=VP_RNG_VS_RNG
Mcu.Pin45=VP_RTC_VS_RTC_Activate
Mcu.Pin46=VP_RTC_VS_RTC_Calendar
Mcu.Pin47=VP_SYS_VS_tim1
Mcu.Pin48=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.Pin5=PD5
Mcu.Pin6=PD1
Mcu.Pin7=PD4
Mcu.Pin8=PF0
Mcu.Pin9=PF2
Mcu.PinsNb=49
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32F437IIHx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_TIM10_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PC10.Mode=Asynchronous
PC10.Signal=UART4_TX
PC11.Mode=Asynchronous
PC11.Signal=UART4_RX
PD0.Signal=FMC_D2_DA2
PD1.Signal=FMC_D3_DA3
PD10.Signal=FMC_D15_DA15
PD11.Signal=FMC_A16_CLE
PD12.Signal=FMC_A17_ALE
PD13.Signal=FMC_A18
PD14.Signal=FMC_D0_DA0
PD15.Signal=FMC_D1_DA1
PD4.Signal=FMC_NOE
PD5.Signal=FMC_NWE
PD7.Mode=NorPsramChipSelect1_1
PD7.Signal=FMC_NE1
PD8.Signal=FMC_D13_DA13
PD9.Signal=FMC_D14_DA14
PE10.Signal=FMC_D7_DA7
PE11.Signal=FMC_D8_DA8
PE12.Signal=FMC_D9_DA9
PE13.Signal=FMC_D10_DA10
PE14.Signal=FMC_D11_DA11
PE15.Signal=FMC_D12_DA12
PE3.Signal=FMC_A19
PE7.Signal=FMC_D4_DA4
PE8.Signal=FMC_D5_DA5
PE9.Signal=FMC_D6_DA6
PF0.Signal=FMC_A0
PF1.Signal=FMC_A1
PF12.Signal=FMC_A6
PF13.Signal=FMC_A7
PF14.Signal=FMC_A8
PF15.Signal=FMC_A9
PF2.Signal=FMC_A2
PF3.Signal=FMC_A3
PF4.Signal=FMC_A4
PF5.Signal=FMC_A5
PG0.Signal=FMC_A10
PG1.Signal=FMC_A11
PG2.Signal=FMC_A12
PG3.Signal=FMC_A13
PG4.Signal=FMC_A14_BA0
PG5.Signal=FMC_A15_BA1
PinOutPanel.CurrentBGAView=Top
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F437IIHx
ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.25.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x2000
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32F437.ioc
ProjectManager.ProjectName=STM32F437
ProjectManager.StackSize=0x4000
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CRYP_Init-CRYP-false-HAL-true,4-MX_HASH_Init-HASH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,6-MX_UART4_Init-UART4-false-HAL-true,7-MX_RTC_Init-RTC-false-HAL-true,8-MX_FMC_Init-FMC-false-HAL-true
RCC.48MHZClocksFreq_Value=45714285.71428572
RCC.AHBFreq_Value=160000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=40000000
RCC.APB1TimFreq_Value=80000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=80000000
RCC.APB2TimFreq_Value=160000000
RCC.CortexFreq_Value=160000000
RCC.EthernetFreq_Value=160000000
RCC.FCLKCortexFreq_Value=160000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=160000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2SClocksFreq_Value=192000000
RCC.IPParameters=48MHZClocksFreq_Value,AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SAI_AClocksFreq_Value,SAI_BClocksFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value,VCOSAIOutputFreq_ValueQ,VcooutputI2S,VcooutputI2SQ
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=160000000
RCC.PLLCLKFreq_Value=160000000
RCC.PLLM=8
RCC.PLLN=160
RCC.PLLQ=7
RCC.PLLQCLKFreq_Value=45714285.71428572
RCC.RTCFreq_Value=32000
RCC.RTCHSEDivFreq_Value=12500000
RCC.SAI_AClocksFreq_Value=24500000
RCC.SAI_BClocksFreq_Value=24500000
RCC.SYSCLKFreq_VALUE=160000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=320000000
RCC.VCOSAIOutputFreq_Value=98000000
RCC.VCOSAIOutputFreq_ValueQ=24500000
RCC.VcooutputI2S=192000000
RCC.VcooutputI2SQ=192000000
SH.FMC_A0.0=FMC_A0,20b-a1
SH.FMC_A0.ConfNb=1
SH.FMC_A1.0=FMC_A1,20b-a1
SH.FMC_A1.ConfNb=1
SH.FMC_A10.0=FMC_A10,20b-a1
SH.FMC_A10.ConfNb=1
SH.FMC_A11.0=FMC_A11,20b-a1
SH.FMC_A11.ConfNb=1
SH.FMC_A12.0=FMC_A12,20b-a1
SH.FMC_A12.ConfNb=1
SH.FMC_A13.0=FMC_A13,20b-a1
SH.FMC_A13.ConfNb=1
SH.FMC_A14_BA0.0=FMC_A14,20b-a1
SH.FMC_A14_BA0.ConfNb=1
SH.FMC_A15_BA1.0=FMC_A15,20b-a1
SH.FMC_A15_BA1.ConfNb=1
SH.FMC_A16_CLE.0=FMC_A16,20b-a1
SH.FMC_A16_CLE.ConfNb=1
SH.FMC_A17_ALE.0=FMC_A17,20b-a1
SH.FMC_A17_ALE.ConfNb=1
SH.FMC_A18.0=FMC_A18,20b-a1
SH.FMC_A18.ConfNb=1
SH.FMC_A19.0=FMC_A19,20b-a1
SH.FMC_A19.ConfNb=1
SH.FMC_A2.0=FMC_A2,20b-a1
SH.FMC_A2.ConfNb=1
SH.FMC_A3.0=FMC_A3,20b-a1
SH.FMC_A3.ConfNb=1
SH.FMC_A4.0=FMC_A4,20b-a1
SH.FMC_A4.ConfNb=1
SH.FMC_A5.0=FMC_A5,20b-a1
SH.FMC_A5.ConfNb=1
SH.FMC_A6.0=FMC_A6,20b-a1
SH.FMC_A6.ConfNb=1
SH.FMC_A7.0=FMC_A7,20b-a1
SH.FMC_A7.ConfNb=1
SH.FMC_A8.0=FMC_A8,20b-a1
SH.FMC_A8.ConfNb=1
SH.FMC_A9.0=FMC_A9,20b-a1
SH.FMC_A9.ConfNb=1
SH.FMC_D0_DA0.0=FMC_D0,16b-d1
SH.FMC_D0_DA0.ConfNb=1
SH.FMC_D10_DA10.0=FMC_D10,16b-d1
SH.FMC_D10_DA10.ConfNb=1
SH.FMC_D11_DA11.0=FMC_D11,16b-d1
SH.FMC_D11_DA11.ConfNb=1
SH.FMC_D12_DA12.0=FMC_D12,16b-d1
SH.FMC_D12_DA12.ConfNb=1
SH.FMC_D13_DA13.0=FMC_D13,16b-d1
SH.FMC_D13_DA13.ConfNb=1
SH.FMC_D14_DA14.0=FMC_D14,16b-d1
SH.FMC_D14_DA14.ConfNb=1
SH.FMC_D15_DA15.0=FMC_D15,16b-d1
SH.FMC_D15_DA15.ConfNb=1
SH.FMC_D1_DA1.0=FMC_D1,16b-d1
SH.FMC_D1_DA1.ConfNb=1
SH.FMC_D2_DA2.0=FMC_D2,16b-d1
SH.FMC_D2_DA2.ConfNb=1
SH.FMC_D3_DA3.0=FMC_D3,16b-d1
SH.FMC_D3_DA3.ConfNb=1
SH.FMC_D4_DA4.0=FMC_D4,16b-d1
SH.FMC_D4_DA4.ConfNb=1
SH.FMC_D5_DA5.0=FMC_D5,16b-d1
SH.FMC_D5_DA5.ConfNb=1
SH.FMC_D6_DA6.0=FMC_D6,16b-d1
SH.FMC_D6_DA6.ConfNb=1
SH.FMC_D7_DA7.0=FMC_D7,16b-d1
SH.FMC_D7_DA7.ConfNb=1
SH.FMC_D8_DA8.0=FMC_D8,16b-d1
SH.FMC_D8_DA8.ConfNb=1
SH.FMC_D9_DA9.0=FMC_D9,16b-d1
SH.FMC_D9_DA9.ConfNb=1
SH.FMC_NOE.0=FMC_NOE,Sram1
SH.FMC_NOE.ConfNb=1
SH.FMC_NWE.0=FMC_NWE,Sram1
SH.FMC_NWE.ConfNb=1
UART4.IPParameters=VirtualMode
UART4.VirtualMode=Asynchronous
VP_CRYP_VS_CRYP.Mode=CRYP_Activate
VP_CRYP_VS_CRYP.Signal=CRYP_VS_CRYP
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_HASH_VS_HASH.Mode=HASH_Activate
VP_HASH_VS_HASH.Signal=HASH_VS_HASH
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=custom
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLFCRYPT_ONLY,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLFCRYPT_ONLY=False
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

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IDE/STM32Cube/Boards/STM32F777.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=131072
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32F7
Mcu.IP0=CORTEX_M7
Mcu.IP1=CRYP
Mcu.IP10=USART3
Mcu.IP2=FREERTOS
Mcu.IP3=HASH
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SYS
Mcu.IP9=USART2
Mcu.IPNb=11
Mcu.Name=STM32F777NIHx
Mcu.Package=TFBGA216
Mcu.Pin0=PD6
Mcu.Pin1=PI8
Mcu.Pin10=VP_RTC_VS_RTC_Calendar
Mcu.Pin11=VP_SYS_VS_tim1
Mcu.Pin12=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.Pin2=PD5
Mcu.Pin3=PD9
Mcu.Pin4=PD8
Mcu.Pin5=VP_CRYP_VS_CRYP
Mcu.Pin6=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin7=VP_HASH_VS_HASH
Mcu.Pin8=VP_RNG_VS_RNG
Mcu.Pin9=VP_RTC_VS_RTC_Activate
Mcu.PinsNb=13
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32F777NIHx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_TIM10_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_TIM10_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PD5.Mode=Asynchronous
PD5.Signal=USART2_TX
PD6.Mode=Asynchronous
PD6.Signal=USART2_RX
PD8.Locked=true
PD8.Mode=Asynchronous
PD8.Signal=USART3_TX
PD9.Locked=true
PD9.Mode=Asynchronous
PD9.Signal=USART3_RX
PI8.Mode=Timestamp enabled - Input Enabled to TS
PI8.Signal=RTC_TS
PinOutPanel.CurrentBGAView=Top
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32F777NIHx
ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.16.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32F777.ioc
ProjectManager.ProjectName=STM32F777
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_CRYP_Init-CRYP-false-HAL-true,4-MX_HASH_Init-HASH-false-HAL-true,5-MX_RNG_Init-RNG-false-HAL-true,6-MX_USART3_UART_Init-USART3-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
RCC.AHBFreq_Value=216000000
RCC.APB1CLKDivider=RCC_HCLK_DIV4
RCC.APB1Freq_Value=54000000
RCC.APB1TimFreq_Value=108000000
RCC.APB2CLKDivider=RCC_HCLK_DIV2
RCC.APB2Freq_Value=108000000
RCC.APB2TimFreq_Value=216000000
RCC.CECFreq_Value=32786.88524590164
RCC.CortexFreq_Value=216000000
RCC.DFSDMAudioFreq_Value=192000000
RCC.DFSDMFreq_Value=108000000
RCC.EthernetFreq_Value=216000000
RCC.FCLKCortexFreq_Value=216000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=216000000
RCC.HSE_VALUE=25000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=54000000
RCC.I2C2Freq_Value=54000000
RCC.I2C3Freq_Value=54000000
RCC.I2C4Freq_Value=54000000
RCC.I2SFreq_Value=192000000
RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFTFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLRFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value
RCC.LCDTFTFreq_Value=96000000
RCC.LPTIM1Freq_Value=54000000
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO2PinFreq_Value=216000000
RCC.PLLCLKFreq_Value=216000000
RCC.PLLI2SPCLKFreq_Value=192000000
RCC.PLLI2SQCLKFreq_Value=192000000
RCC.PLLI2SRCLKFreq_Value=192000000
RCC.PLLI2SRoutputFreq_Value=192000000
RCC.PLLM=8
RCC.PLLN=216
RCC.PLLQ=9
RCC.PLLQCLKFreq_Value=48000000
RCC.PLLQoutputFreq_Value=48000000
RCC.PLLRFreq_Value=216000000
RCC.PLLSAIPCLKFreq_Value=192000000
RCC.PLLSAIQCLKFreq_Value=192000000
RCC.PLLSAIRCLKFreq_Value=192000000
RCC.PLLSAIoutputFreq_Value=192000000
RCC.RNGFreq_Value=48000000
RCC.SAI1Freq_Value=192000000
RCC.SAI2Freq_Value=192000000
RCC.SDMMC2Freq_Value=216000000
RCC.SDMMCFreq_Value=216000000
RCC.SPDIFRXFreq_Value=192000000
RCC.SYSCLKFreq_VALUE=216000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=54000000
RCC.UART5Freq_Value=54000000
RCC.UART7Freq_Value=54000000
RCC.UART8Freq_Value=54000000
RCC.USART1Freq_Value=108000000
RCC.USART2Freq_Value=54000000
RCC.USART3Freq_Value=54000000
RCC.USART6Freq_Value=108000000
RCC.USBFreq_Value=48000000
RCC.VCOI2SOutputFreq_Value=384000000
RCC.VCOInputFreq_Value=2000000
RCC.VCOOutputFreq_Value=432000000
RCC.VCOSAIOutputFreq_Value=384000000
USART2.IPParameters=VirtualMode-Asynchronous
USART2.VirtualMode-Asynchronous=VM_ASYNC
USART3.IPParameters=VirtualMode-Asynchronous
USART3.VirtualMode-Asynchronous=VM_ASYNC
VP_CRYP_VS_CRYP.Mode=CRYP_Activate
VP_CRYP_VS_CRYP.Signal=CRYP_VS_CRYP
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_HASH_VS_HASH.Mode=HASH_Activate
VP_HASH_VS_HASH.Signal=HASH_VS_HASH
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=custom
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

338
IDE/STM32Cube/Boards/STM32H753.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
CORTEX_M7.CPU_DCache=Disabled
CORTEX_M7.CPU_ICache=Disabled
CORTEX_M7.IPParameters=CPU_ICache,CPU_DCache,MPU_Control
CORTEX_M7.MPU_Control=__NULL
ETH.ETH_RX_DESC_CNT=4
ETH.ETH_TX_DESC_CNT=4
ETH.IPParameters=MACAddr,MediaInterface,ETH_TX_DESC_CNT,TxDescAddress,ETH_RX_DESC_CNT,RxDescAddress,RxBuffAddress,RxBuffLen
ETH.MACAddr=00\:80\:E1\:00\:00\:00
ETH.MediaInterface=HAL_ETH_RMII_MODE
ETH.RxBuffAddress=0x30040200
ETH.RxBuffLen=1524
ETH.RxDescAddress=0x30040000
ETH.TxDescAddress=0x30040060
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=180000
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32H7
Mcu.IP0=CORTEX_M7
Mcu.IP1=CRYP
Mcu.IP10=USART3
Mcu.IP11=USB_OTG_FS
Mcu.IP2=ETH
Mcu.IP3=FREERTOS
Mcu.IP4=HASH
Mcu.IP5=NVIC
Mcu.IP6=RCC
Mcu.IP7=RNG
Mcu.IP8=RTC
Mcu.IP9=SYS
Mcu.IPNb=12
Mcu.Name=STM32H753ZITx
Mcu.Package=LQFP144
Mcu.Pin0=PC13
Mcu.Pin1=PC14-OSC32_IN (OSC32_IN)
Mcu.Pin10=PC5
Mcu.Pin11=PB0
Mcu.Pin12=PB13
Mcu.Pin13=PB14
Mcu.Pin14=PD8
Mcu.Pin15=PD9
Mcu.Pin16=PD10
Mcu.Pin17=PG7
Mcu.Pin18=PA8
Mcu.Pin19=PA9
Mcu.Pin2=PC15-OSC32_OUT (OSC32_OUT)
Mcu.Pin20=PA11
Mcu.Pin21=PA12
Mcu.Pin22=PG11
Mcu.Pin23=PG13
Mcu.Pin24=PE1
Mcu.Pin25=VP_CRYP_VS_CRYP
Mcu.Pin26=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin27=VP_HASH_VS_HASH
Mcu.Pin28=VP_RNG_VS_RNG
Mcu.Pin29=VP_RTC_VS_RTC_Activate
Mcu.Pin3=PH0-OSC_IN (PH0)
Mcu.Pin30=VP_SYS_VS_tim1
Mcu.Pin31=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.Pin4=PH1-OSC_OUT (PH1)
Mcu.Pin5=PC1
Mcu.Pin6=PA1
Mcu.Pin7=PA2
Mcu.Pin8=PA7
Mcu.Pin9=PC4
Mcu.PinsNb=32
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32H753ZITx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA1.Locked=true
PA1.Mode=RMII
PA1.Signal=ETH_REF_CLK
PA11.Locked=true
PA11.Mode=Device_Only
PA11.Signal=USB_OTG_FS_DM
PA12.Locked=true
PA12.Mode=Device_Only
PA12.Signal=USB_OTG_FS_DP
PA2.Locked=true
PA2.Mode=RMII
PA2.Signal=ETH_MDIO
PA7.Locked=true
PA7.Mode=RMII
PA7.Signal=ETH_CRS_DV
PA8.Locked=true
PA8.Mode=Activate_SOF_FS
PA8.Signal=USB_OTG_FS_SOF
PA9.Locked=true
PA9.Mode=Activate_VBUS
PA9.Signal=USB_OTG_FS_VBUS
PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=LD1 [Green Led]
PB0.Locked=true
PB0.Signal=GPIO_Output
PB13.Locked=true
PB13.Mode=RMII
PB13.Signal=ETH_TXD1
PB14.GPIOParameters=GPIO_Label
PB14.GPIO_Label=LD3 [Red Led]
PB14.Locked=true
PB14.Signal=GPIO_Output
PC1.Locked=true
PC1.Mode=RMII
PC1.Signal=ETH_MDC
PC13.GPIOParameters=GPIO_Label
PC13.GPIO_Label=B1 [Blue PushButton]
PC13.Locked=true
PC13.Signal=GPIO_Input
PC14-OSC32_IN\ (OSC32_IN).Locked=true
PC14-OSC32_IN\ (OSC32_IN).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (OSC32_IN).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (OSC32_OUT).Locked=true
PC15-OSC32_OUT\ (OSC32_OUT).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (OSC32_OUT).Signal=RCC_OSC32_OUT
PC4.Locked=true
PC4.Mode=RMII
PC4.Signal=ETH_RXD0
PC5.Locked=true
PC5.Mode=RMII
PC5.Signal=ETH_RXD1
PD10.GPIOParameters=GPIO_Label
PD10.GPIO_Label=USB_OTG_FS_PWR_EN
PD10.Locked=true
PD10.Signal=GPIO_Output
PD8.GPIOParameters=GPIO_Label
PD8.GPIO_Label=STLINK_RX
PD8.Locked=true
PD8.Mode=Asynchronous
PD8.Signal=USART3_TX
PD9.GPIOParameters=GPIO_Label
PD9.GPIO_Label=STLINK_TX
PD9.Locked=true
PD9.Mode=Asynchronous
PD9.Signal=USART3_RX
PE1.GPIOParameters=GPIO_Label
PE1.GPIO_Label=LD2 [Yellow Led]
PE1.Locked=true
PE1.Signal=GPIO_Output
PG11.Locked=true
PG11.Mode=RMII
PG11.Signal=ETH_TX_EN
PG13.Locked=true
PG13.Mode=RMII
PG13.Signal=ETH_TXD0
PG7.GPIOParameters=GPIO_Label
PG7.GPIO_Label=USB_OTG_FS_OVCR
PG7.Locked=true
PG7.Signal=GPXTI7
PH0-OSC_IN\ (PH0).Locked=true
PH0-OSC_IN\ (PH0).Mode=HSE-External-Clock-Source
PH0-OSC_IN\ (PH0).Signal=RCC_OSC_IN
PH1-OSC_OUT\ (PH1).Locked=true
PH1-OSC_OUT\ (PH1).Signal=RCC_OSC_OUT
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32H753ZITx
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.7.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32H753.ioc
ProjectManager.ProjectName=STM32H753
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ETH_Init-ETH-false-HAL-true,4-MX_USART3_UART_Init-USART3-false-HAL-true,5-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
RCC.ADCFreq_Value=16125000
RCC.AHB12Freq_Value=240000000
RCC.AHB4Freq_Value=240000000
RCC.APB1Freq_Value=120000000
RCC.APB2Freq_Value=120000000
RCC.APB3Freq_Value=120000000
RCC.APB4Freq_Value=120000000
RCC.AXIClockFreq_Value=240000000
RCC.CECFreq_Value=32000
RCC.CKPERFreq_Value=64000000
RCC.CortexFreq_Value=480000000
RCC.CpuClockFreq_Value=480000000
RCC.D1CPREFreq_Value=480000000
RCC.D1PPRE=RCC_APB3_DIV2
RCC.D2PPRE1=RCC_APB1_DIV2
RCC.D2PPRE2=RCC_APB2_DIV2
RCC.D3PPRE=RCC_APB4_DIV2
RCC.DFSDMACLkFreq_Value=48000000
RCC.DFSDMFreq_Value=120000000
RCC.DIVM1=1
RCC.DIVN1=120
RCC.DIVP1Freq_Value=480000000
RCC.DIVP2Freq_Value=16125000
RCC.DIVP3Freq_Value=16125000
RCC.DIVQ1=20
RCC.DIVQ1Freq_Value=48000000
RCC.DIVQ2Freq_Value=16125000
RCC.DIVQ3Freq_Value=16125000
RCC.DIVR1Freq_Value=480000000
RCC.DIVR2Freq_Value=16125000
RCC.DIVR3Freq_Value=16125000
RCC.FDCANFreq_Value=48000000
RCC.FMCFreq_Value=240000000
RCC.FamilyName=M
RCC.HCLK3ClockFreq_Value=240000000
RCC.HCLKFreq_Value=240000000
RCC.HPRE=RCC_HCLK_DIV2
RCC.HRTIMFreq_Value=240000000
RCC.HSE_VALUE=8000000
RCC.I2C123Freq_Value=120000000
RCC.I2C4Freq_Value=120000000
RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,D1PPRE,D2PPRE1,D2PPRE2,D3PPRE,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVN1,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HPRE,HRTIMFreq_Value,HSE_VALUE,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL2FRACN,PLL3FRACN,PLLFRACN,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI23Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
RCC.LPTIM1Freq_Value=120000000
RCC.LPTIM2Freq_Value=120000000
RCC.LPTIM345Freq_Value=120000000
RCC.LPUART1Freq_Value=120000000
RCC.LTDCFreq_Value=16125000
RCC.MCO1PinFreq_Value=64000000
RCC.MCO2PinFreq_Value=480000000
RCC.PLL2FRACN=0
RCC.PLL3FRACN=0
RCC.PLLFRACN=0
RCC.QSPIFreq_Value=240000000
RCC.RNGFreq_Value=48000000
RCC.RTCFreq_Value=32000
RCC.SAI1Freq_Value=48000000
RCC.SAI23Freq_Value=48000000
RCC.SAI4AFreq_Value=48000000
RCC.SAI4BFreq_Value=48000000
RCC.SDMMCFreq_Value=48000000
RCC.SPDIFRXFreq_Value=48000000
RCC.SPI123Freq_Value=48000000
RCC.SPI45Freq_Value=120000000
RCC.SPI6Freq_Value=120000000
RCC.SWPMI1Freq_Value=120000000
RCC.SYSCLKFreq_VALUE=480000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.Tim1OutputFreq_Value=240000000
RCC.Tim2OutputFreq_Value=240000000
RCC.TraceFreq_Value=64000000
RCC.USART16Freq_Value=120000000
RCC.USART234578Freq_Value=120000000
RCC.USBFreq_Value=48000000
RCC.VCO1OutputFreq_Value=960000000
RCC.VCO2OutputFreq_Value=32250000
RCC.VCO3OutputFreq_Value=32250000
RCC.VCOInput1Freq_Value=8000000
RCC.VCOInput2Freq_Value=250000
RCC.VCOInput3Freq_Value=250000
SH.GPXTI7.0=GPIO_EXTI7
SH.GPXTI7.ConfNb=1
USART3.AutoBaudRateEnableParam=UART_ADVFEATURE_AUTOBAUDRATE_DISABLE
USART3.BaudRate=115200
USART3.ClockPrescaler=PRESCALER_DIV1
USART3.DMADisableonRxErrorParam=ADVFEATURE_DMA_ENABLEONRXERROR
USART3.DataInvertParam=ADVFEATURE_DATAINV_DISABLE
USART3.FIFOMode=FIFOMODE_DISABLE
USART3.IPParameters=BaudRate,VirtualMode-Asynchronous,WordLength,Parity,StopBits,Mode,OverSampling,OneBitSampling,ClockPrescaler,FIFOMode,TXFIFOThreshold,RXFIFOThreshold,AutoBaudRateEnableParam,TxPinLevelInvertParam,RxPinLevelInvertParam,DataInvertParam,SwapParam,OverrunDisableParam,DMADisableonRxErrorParam,MSBFirstParam
USART3.MSBFirstParam=ADVFEATURE_MSBFIRST_DISABLE
USART3.Mode=MODE_TX_RX
USART3.OneBitSampling=UART_ONE_BIT_SAMPLE_DISABLE
USART3.OverSampling=UART_OVERSAMPLING_16
USART3.OverrunDisableParam=ADVFEATURE_OVERRUN_ENABLE
USART3.Parity=PARITY_NONE
USART3.RXFIFOThreshold=RXFIFO_THRESHOLD_1EIGHTHFULL
USART3.RxPinLevelInvertParam=ADVFEATURE_RXINV_DISABLE
USART3.StopBits=STOPBITS_1
USART3.SwapParam=ADVFEATURE_SWAP_DISABLE
USART3.TXFIFOThreshold=TXFIFO_THRESHOLD_1EIGHTHFULL
USART3.TxPinLevelInvertParam=ADVFEATURE_TXINV_DISABLE
USART3.VirtualMode-Asynchronous=VM_ASYNC
USART3.WordLength=WORDLENGTH_8B
USB_OTG_FS.IPParameters=low_power_enable,VirtualMode,battery_charging_enable,lpm_enable,use_dedicated_ep1,vbus_sensing_enable,Sof_enable
USB_OTG_FS.Sof_enable=ENABLE
USB_OTG_FS.VirtualMode=Device_Only
USB_OTG_FS.battery_charging_enable=ENABLE
USB_OTG_FS.low_power_enable=DISABLE
USB_OTG_FS.lpm_enable=DISABLE
USB_OTG_FS.use_dedicated_ep1=DISABLE
USB_OTG_FS.vbus_sensing_enable=ENABLE
VP_CRYP_VS_CRYP.Mode=CRYP_Activate
VP_CRYP_VS_CRYP.Signal=CRYP_VS_CRYP
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_HASH_VS_HASH.Mode=HASH_Activate
VP_HASH_VS_HASH.Signal=HASH_VS_HASH
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=NUCLEO-H753ZI
boardIOC=true
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

636
IDE/STM32Cube/Boards/STM32L475.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,FootprintOK,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=88000
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32L4
Mcu.IP0=DFSDM1
Mcu.IP1=FREERTOS
Mcu.IP10=USART1
Mcu.IP11=USART3
Mcu.IP12=USB_OTG_FS
Mcu.IP2=I2C2
Mcu.IP3=NVIC
Mcu.IP4=QUADSPI
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SPI3
Mcu.IP9=SYS
Mcu.IPNb=13
Mcu.Name=STM32L475V(C-E-G)Tx
Mcu.Package=LQFP100
Mcu.Pin0=PE2
Mcu.Pin1=PE3
Mcu.Pin10=PC2
Mcu.Pin11=PC3
Mcu.Pin12=PA0
Mcu.Pin13=PA1
Mcu.Pin14=PA2
Mcu.Pin15=PA3
Mcu.Pin16=PA4
Mcu.Pin17=PA5
Mcu.Pin18=PA6
Mcu.Pin19=PA7
Mcu.Pin2=PE4
Mcu.Pin20=PC4
Mcu.Pin21=PC5
Mcu.Pin22=PB0
Mcu.Pin23=PB1
Mcu.Pin24=PB2
Mcu.Pin25=PE7
Mcu.Pin26=PE8
Mcu.Pin27=PE9
Mcu.Pin28=PE10
Mcu.Pin29=PE11
Mcu.Pin3=PE5
Mcu.Pin30=PE12
Mcu.Pin31=PE13
Mcu.Pin32=PE14
Mcu.Pin33=PE15
Mcu.Pin34=PB10
Mcu.Pin35=PB11
Mcu.Pin36=PB12
Mcu.Pin37=PB13
Mcu.Pin38=PB14
Mcu.Pin39=PB15
Mcu.Pin4=PE6
Mcu.Pin40=PD8
Mcu.Pin41=PD9
Mcu.Pin42=PD10
Mcu.Pin43=PD11
Mcu.Pin44=PD12
Mcu.Pin45=PD13
Mcu.Pin46=PD14
Mcu.Pin47=PD15
Mcu.Pin48=PC6
Mcu.Pin49=PC7
Mcu.Pin5=PC13
Mcu.Pin50=PC8
Mcu.Pin51=PC9
Mcu.Pin52=PA8
Mcu.Pin53=PA9
Mcu.Pin54=PA10
Mcu.Pin55=PA11
Mcu.Pin56=PA12
Mcu.Pin57=PA13 (JTMS-SWDIO)
Mcu.Pin58=PA14 (JTCK-SWCLK)
Mcu.Pin59=PA15 (JTDI)
Mcu.Pin6=PC14-OSC32_IN (PC14)
Mcu.Pin60=PC10
Mcu.Pin61=PC11
Mcu.Pin62=PC12
Mcu.Pin63=PD0
Mcu.Pin64=PD1
Mcu.Pin65=PD2
Mcu.Pin66=PD3
Mcu.Pin67=PD4
Mcu.Pin68=PD5
Mcu.Pin69=PD6
Mcu.Pin7=PC15-OSC32_OUT (PC15)
Mcu.Pin70=PD7
Mcu.Pin71=PB3 (JTDO-TRACESWO)
Mcu.Pin72=PB4 (NJTRST)
Mcu.Pin73=PB5
Mcu.Pin74=PB6
Mcu.Pin75=PB7
Mcu.Pin76=PB8
Mcu.Pin77=PB9
Mcu.Pin78=PE0
Mcu.Pin79=PE1
Mcu.Pin8=PC0
Mcu.Pin80=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin81=VP_RNG_VS_RNG
Mcu.Pin82=VP_RTC_VS_RTC_Activate
Mcu.Pin83=VP_SYS_VS_tim1
Mcu.Pin84=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.Pin9=PC1
Mcu.PinsNb=85
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32L475VGTx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.EXTI15_10_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
NVIC.EXTI9_5_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:true\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:true\:false
NVIC.TIM1_UP_TIM16_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_TIM16_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false
PA0.GPIOParameters=GPIO_Label
PA0.GPIO_Label=ARD_D1 [UART4_TX]
PA0.Locked=true
PA0.Signal=UART4_TX
PA1.GPIOParameters=GPIO_Label
PA1.GPIO_Label=ARD_D0 [UART4_RX]
PA1.Locked=true
PA1.Signal=UART4_RX
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=USB_OTG_FS_ID
PA10.Locked=true
PA10.Signal=USB_OTG_FS_ID
PA11.GPIOParameters=GPIO_Label
PA11.GPIO_Label=USB_OTG_FS_DM
PA11.Locked=true
PA11.Mode=Device_Only
PA11.Signal=USB_OTG_FS_DM
PA12.GPIOParameters=GPIO_Label
PA12.GPIO_Label=USB_OTG_FS_DP
PA12.Locked=true
PA12.Mode=Device_Only
PA12.Signal=USB_OTG_FS_DP
PA13\ (JTMS-SWDIO).GPIOParameters=GPIO_Label
PA13\ (JTMS-SWDIO).GPIO_Label=SYS_JTMS_SWDIO
PA13\ (JTMS-SWDIO).Locked=true
PA13\ (JTMS-SWDIO).Mode=Serial_Wire
PA13\ (JTMS-SWDIO).Signal=SYS_JTMS-SWDIO
PA14\ (JTCK-SWCLK).GPIOParameters=GPIO_Label
PA14\ (JTCK-SWCLK).GPIO_Label=SYS_JTCK_SWCLK
PA14\ (JTCK-SWCLK).Locked=true
PA14\ (JTCK-SWCLK).Mode=Serial_Wire
PA14\ (JTCK-SWCLK).Signal=SYS_JTCK-SWCLK
PA15\ (JTDI).GPIOParameters=GPIO_Label
PA15\ (JTDI).GPIO_Label=ARD_D9
PA15\ (JTDI).Locked=true
PA15\ (JTDI).Signal=GPIO_Output
PA2.GPIOParameters=GPIO_Label
PA2.GPIO_Label=ARD_D10 [SPI_SSN]
PA2.Locked=true
PA2.Signal=GPIO_Output
PA3.GPIOParameters=GPIO_Label
PA3.GPIO_Label=ARD_D4
PA3.Locked=true
PA3.Signal=S_TIM2_CH4
PA4.GPIOParameters=GPIO_Label
PA4.GPIO_Label=ARD_D7
PA4.Locked=true
PA4.Signal=ADCx_IN9
PA5.GPIOParameters=GPIO_Label
PA5.GPIO_Label=ARD_D13 [SPI1_SCK]
PA5.Locked=true
PA5.Signal=SPI1_SCK
PA6.GPIOParameters=GPIO_Label
PA6.GPIO_Label=ARD_D12 [SPI1_MISO]
PA6.Locked=true
PA6.Signal=SPI1_MISO
PA7.GPIOParameters=GPIO_Label
PA7.GPIO_Label=ARD_D11 [SPI1_MOSI]
PA7.Locked=true
PA7.Signal=SPI1_MOSI
PA8.GPIOParameters=GPIO_Label
PA8.GPIO_Label=SPBTLE_RF_RST
PA8.Locked=true
PA8.Signal=GPIO_Output
PA9.GPIOParameters=GPIO_Label
PA9.GPIO_Label=USB_OTG_FS_VBUS [STMPS2141STR_OUT]
PA9.Locked=true
PA9.Signal=USB_OTG_FS_VBUS
PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=ARD_D3 [INT_EXT10]
PB0.Locked=true
PB0.Signal=GPXTI0
PB1.GPIOParameters=GPIO_Label
PB1.GPIO_Label=ARD_D6 [ADC1_IN6]
PB1.Locked=true
PB1.Signal=ADCx_IN16
PB10.GPIOParameters=GPIO_Label
PB10.GPIO_Label=INTERNAL_I2C2_SCL [VL53L0X_SCL]
PB10.Locked=true
PB10.Mode=I2C
PB10.Signal=I2C2_SCL
PB11.GPIOParameters=GPIO_Label
PB11.GPIO_Label=INTERNAL_I2C2_SDA [VL53L0X_SDA]
PB11.Locked=true
PB11.Mode=I2C
PB11.Signal=I2C2_SDA
PB12.GPIOParameters=GPIO_Label
PB12.GPIO_Label=ISM43362_BOOT0 [ISM43362_BOOT]
PB12.Locked=true
PB12.Signal=GPIO_Output
PB13.GPIOParameters=GPIO_Label
PB13.GPIO_Label=ISM43362_WAKEUP [ISM43362_WKUP]
PB13.Locked=true
PB13.Signal=GPIO_Output
PB14.GPIOParameters=GPIO_Label
PB14.GPIO_Label=LED2 [LED_GREEN]
PB14.Locked=true
PB14.Signal=GPIO_Output
PB15.GPIOParameters=GPIO_Label
PB15.GPIO_Label=SPSGRF_915_SDN [SPSGRF_SDN]
PB15.Locked=true
PB15.Signal=GPIO_Output
PB2.GPIOParameters=GPIO_Label
PB2.GPIO_Label=ARD_D8
PB2.Locked=true
PB2.Signal=GPIO_Output
PB3\ (JTDO-TRACESWO).GPIOParameters=GPIO_Label
PB3\ (JTDO-TRACESWO).GPIO_Label=SYS_JTD0_SWO
PB3\ (JTDO-TRACESWO).Locked=true
PB3\ (JTDO-TRACESWO).Signal=SYS_JTDO-SWO
PB4\ (NJTRST).GPIOParameters=GPIO_Label
PB4\ (NJTRST).GPIO_Label=ARD_D5
PB4\ (NJTRST).Locked=true
PB4\ (NJTRST).Signal=GPIO_Output
PB5.GPIOParameters=PinState,GPIO_Label
PB5.GPIO_Label=SPSGRF_915_SPI3_CSN [SPSGRF_SPI_CS]
PB5.Locked=true
PB5.PinState=GPIO_PIN_SET
PB5.Signal=GPIO_Output
PB6.GPIOParameters=GPIO_Label
PB6.GPIO_Label=ST_LINK_UART1_TX
PB6.Locked=true
PB6.Mode=Asynchronous
PB6.Signal=USART1_TX
PB7.GPIOParameters=GPIO_Label
PB7.GPIO_Label=ST_LINK_UART1_RX
PB7.Locked=true
PB7.Mode=Asynchronous
PB7.Signal=USART1_RX
PB8.GPIOParameters=GPIO_Label
PB8.GPIO_Label=ARD_D15 [I2C1_SCL]
PB8.Locked=true
PB8.Signal=I2C1_SCL
PB9.GPIOParameters=GPIO_Label
PB9.GPIO_Label=ARD_D14 [I2C1_SDA]
PB9.Locked=true
PB9.Signal=I2C1_SDA
PC0.GPIOParameters=GPIO_Label
PC0.GPIO_Label=ARD_A5 [ADC]
PC0.Locked=true
PC0.Signal=ADCx_IN1
PC1.GPIOParameters=GPIO_Label
PC1.GPIO_Label=ARD_A4 [ADC]
PC1.Locked=true
PC1.Signal=ADCx_IN2
PC10.GPIOParameters=GPIO_Label
PC10.GPIO_Label=INTERNAL_SPI3_SCK [BT module_SPI_SCLK] [ISM43362_SCK]
PC10.Locked=true
PC10.Mode=Full_Duplex_Master
PC10.Signal=SPI3_SCK
PC11.GPIOParameters=GPIO_Label
PC11.GPIO_Label=INTERNAL_SPI3_MISO [BT module_SPI_MISO] [ISM43362_MISO]
PC11.Locked=true
PC11.Mode=Full_Duplex_Master
PC11.Signal=SPI3_MISO
PC12.GPIOParameters=GPIO_Label
PC12.GPIO_Label=INTERNAL_SPI3_MOSI [BT module_SPI_MOSI] [ISM43362_MOSI]
PC12.Locked=true
PC12.Mode=Full_Duplex_Master
PC12.Signal=SPI3_MOSI
PC13.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
PC13.GPIO_Label=BUTTON_EXTI13 [B2]
PC13.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
PC13.Locked=true
PC13.Signal=GPXTI13
PC14-OSC32_IN\ (PC14).Locked=true
PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (PC15).Locked=true
PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
PC2.GPIOParameters=GPIO_Label
PC2.GPIO_Label=ARD_A3 [ADC]
PC2.Locked=true
PC2.Signal=ADCx_IN3
PC3.GPIOParameters=GPIO_Label
PC3.GPIO_Label=ARD_A2 [ADC]
PC3.Locked=true
PC3.Signal=ADCx_IN4
PC4.GPIOParameters=GPIO_Label
PC4.GPIO_Label=ARD_A1 [ADC]
PC4.Locked=true
PC4.Signal=ADCx_IN13
PC5.GPIOParameters=GPIO_Label
PC5.GPIO_Label=ARD_A0 [ADC]
PC5.Locked=true
PC5.Signal=ADCx_IN14
PC6.GPIOParameters=GPIO_Label
PC6.GPIO_Label=VL53L0X_XSHUT [Read_XSHUT]
PC6.Locked=true
PC6.Signal=GPIO_Output
PC7.GPIOParameters=GPIO_Label
PC7.GPIO_Label=VL53L0X_GPIO1_EXTI7 [VL53L0X_GPIO1]
PC7.Locked=true
PC7.Signal=GPXTI7
PC8.GPIOParameters=GPIO_Label
PC8.GPIO_Label=LSM3MDL_DRDY_EXTI8 [LIS3MDL_DRDY]
PC8.Locked=true
PC8.Signal=GPXTI8
PC9.GPIOParameters=GPIO_Label
PC9.GPIO_Label=LED3_WIFI_ LED4_BLE
PC9.Locked=true
PC9.Signal=GPIO_Output
PD0.GPIOParameters=GPIO_Label
PD0.GPIO_Label=PMOD_RESET
PD0.Locked=true
PD0.Signal=GPIO_Output
PD1.GPIOParameters=GPIO_Label
PD1.GPIO_Label=PMOD_SPI2_SCK
PD1.Locked=true
PD1.Signal=SPI2_SCK
PD10.GPIOParameters=GPIO_Label
PD10.GPIO_Label=LPS22HB_INT_DRDY_EXTI0 [LPS22HB_INT_DRDY]
PD10.Locked=true
PD10.Signal=GPXTI10
PD11.GPIOParameters=GPIO_Label
PD11.GPIO_Label=LSM6DSL_INT1_EXTI11 [LSM6DSL_INT1]
PD11.Locked=true
PD11.Signal=GPXTI11
PD12.GPIOParameters=GPIO_Label
PD12.GPIO_Label=USB_OTG_FS_PWR_EN [STMPS2141STR_EN]
PD12.Locked=true
PD12.Signal=GPIO_Output
PD13.GPIOParameters=PinState,GPIO_Label
PD13.GPIO_Label=SPBTLE_RF_SPI3_CSN [BT module_SPI_CS]
PD13.Locked=true
PD13.PinState=GPIO_PIN_SET
PD13.Signal=GPIO_Output
PD14.GPIOParameters=GPIO_Label
PD14.GPIO_Label=ARD_D2 [INT0_EXTI14]
PD14.Locked=true
PD14.Signal=GPXTI14
PD15.GPIOParameters=GPIO_Label
PD15.GPIO_Label=HTS221_DRDY_EXTI15 [HTS221_DRDY]
PD15.Locked=true
PD15.Signal=GPXTI15
PD2.GPIOParameters=GPIO_Label
PD2.GPIO_Label=PMOD_IRQ_EXTI12
PD2.Locked=true
PD2.Signal=GPXTI2
PD3.GPIOParameters=GPIO_Label
PD3.GPIO_Label=PMOD_UART2_CTS
PD3.Locked=true
PD3.Signal=USART2_CTS
PD4.GPIOParameters=GPIO_Label
PD4.GPIO_Label=PMOD_UART2_RTS
PD4.Locked=true
PD4.Signal=USART2_RTS
PD5.GPIOParameters=GPIO_Label
PD5.GPIO_Label=PMOD_UART2_TX
PD5.Locked=true
PD5.Signal=USART2_TX
PD6.GPIOParameters=GPIO_Label
PD6.GPIO_Label=PMOD_UART2_RX
PD6.Locked=true
PD6.Signal=USART2_RX
PD7.GPIOParameters=GPIO_Label
PD7.GPIO_Label=STSAFE_A100_RESET [STSAFE-A100_RESET]
PD7.Locked=true
PD7.Signal=GPIO_Output
PD8.GPIOParameters=GPIO_Label
PD8.GPIO_Label=INTERNAL_UART3_TX [ISM43362_RX]
PD8.Locked=true
PD8.Mode=Asynchronous
PD8.Signal=USART3_TX
PD9.GPIOParameters=GPIO_Label
PD9.GPIO_Label=INTERNAL_UART3_RX [ISM43362_TX]
PD9.Locked=true
PD9.Mode=Asynchronous
PD9.Signal=USART3_RX
PE0.GPIOParameters=PinState,GPIO_Label
PE0.GPIO_Label=ISM43362_SPI3_CSN [ISM43362_SSN]
PE0.Locked=true
PE0.PinState=GPIO_PIN_SET
PE0.Signal=GPIO_Output
PE1.GPIOParameters=GPIO_Label
PE1.GPIO_Label=ISM43362_DRDY_EXTI1 [ISM43362_DATARDY]
PE1.Locked=true
PE1.Signal=GPXTI1
PE10.GPIOParameters=GPIO_Label
PE10.GPIO_Label=QUADSPI_CLK [MX25R6435F_SCLK]
PE10.Locked=true
PE10.Mode=Single Bank
PE10.Signal=QUADSPI_CLK
PE11.GPIOParameters=GPIO_Label
PE11.GPIO_Label=QUADSPI_NCS [MX25R6435F_SCLK]
PE11.Locked=true
PE11.Mode=Single Bank
PE11.Signal=QUADSPI_NCS
PE12.GPIOParameters=GPIO_Label
PE12.GPIO_Label=OQUADSPI_BK1_IO0 [MX25R6435F_IO0]
PE12.Locked=true
PE12.Mode=Single Bank
PE12.Signal=QUADSPI_BK1_IO0
PE13.GPIOParameters=GPIO_Label
PE13.GPIO_Label=QUADSPI_BK1_IO1 [MX25R6435F_IO1]
PE13.Locked=true
PE13.Mode=Single Bank
PE13.Signal=QUADSPI_BK1_IO1
PE14.GPIOParameters=GPIO_Label
PE14.GPIO_Label=QUAD_SPI_BK1_IO2 [MX25R6435F_IO2]
PE14.Locked=true
PE14.Mode=Single Bank
PE14.Signal=QUADSPI_BK1_IO2
PE15.GPIOParameters=GPIO_Label
PE15.GPIO_Label=QUAD_SPI_BK1_IO3 [MX25R6435F_IO3]
PE15.Locked=true
PE15.Mode=Single Bank
PE15.Signal=QUADSPI_BK1_IO3
PE2.GPIOParameters=GPIO_Label
PE2.GPIO_Label=M24SR64_Y_RF_DISABLE [M24SR64_RFDIS]
PE2.Locked=true
PE2.Signal=GPIO_Output
PE3.GPIOParameters=GPIO_Label
PE3.GPIO_Label=USB_OTG_FS_OVRCR_EXTI3 [STMPS2141STR_FAULT]
PE3.Locked=true
PE3.Signal=GPXTI3
PE4.GPIOParameters=GPIO_Label
PE4.GPIO_Label=M24SR64_Y_GPO [M24SR64_GPO]
PE4.Locked=true
PE4.Signal=GPIO_Output
PE5.GPIOParameters=GPIO_Label
PE5.GPIO_Label=SPSGRF_915_GPIO3_EXTI5 [SPSGRF_GPIO_3]
PE5.Locked=true
PE5.Signal=GPXTI5
PE6.GPIOParameters=GPIO_Label
PE6.GPIO_Label=SPBTLE_RF_IRQ_EXTI6 [BT module_SPI_IRQ]
PE6.Locked=true
PE6.Signal=GPXTI6
PE7.GPIOParameters=GPIO_Label
PE7.GPIO_Label=DFSDM1_DATIN2 [MP34DT01_DOUT]
PE7.Locked=true
PE7.Signal=S_DATAIN2DFSDM1
PE8.GPIOParameters=GPIO_Label
PE8.GPIO_Label=ISM43362_RST [ISM43362_RSTN]
PE8.Locked=true
PE8.Signal=GPIO_Output
PE9.GPIOParameters=GPIO_Label
PE9.GPIO_Label=DFSDM1_CKOUT [MP34DT01_CLK]
PE9.Locked=true
PE9.Signal=S_CKOUTDFSDM1
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32L475VGTx
ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32L475.ioc
ProjectManager.ProjectName=STM32L475
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DFSDM1_Init-DFSDM1-false-HAL-true,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_QUADSPI_Init-QUADSPI-false-HAL-true,6-MX_SPI3_Init-SPI3-false-HAL-true,7-MX_USART1_UART_Init-USART1-false-HAL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true
RCC.ADCFreq_Value=48000000
RCC.AHBFreq_Value=80000000
RCC.APB1Freq_Value=80000000
RCC.APB1TimFreq_Value=80000000
RCC.APB2Freq_Value=80000000
RCC.APB2TimFreq_Value=80000000
RCC.CortexFreq_Value=80000000
RCC.DFSDMFreq_Value=80000000
RCC.FCLKCortexFreq_Value=80000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=80000000
RCC.HSE_VALUE=8000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=80000000
RCC.I2C2Freq_Value=80000000
RCC.I2C3Freq_Value=80000000
RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
RCC.LPTIM1Freq_Value=80000000
RCC.LPTIM2Freq_Value=80000000
RCC.LPUART1Freq_Value=80000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=80000000
RCC.MSI_VALUE=4000000
RCC.PLLN=40
RCC.PLLPoutputFreq_Value=22857142.85714286
RCC.PLLQoutputFreq_Value=80000000
RCC.PLLRCLKFreq_Value=80000000
RCC.PLLSAI1N=24
RCC.PLLSAI1PoutputFreq_Value=13714285.714285715
RCC.PLLSAI1QoutputFreq_Value=48000000
RCC.PLLSAI1RoutputFreq_Value=48000000
RCC.PLLSAI2PoutputFreq_Value=4571428.571428572
RCC.PLLSAI2RoutputFreq_Value=16000000
RCC.PWRFreq_Value=80000000
RCC.RNGFreq_Value=48000000
RCC.SAI1Freq_Value=13714285.714285715
RCC.SAI2Freq_Value=13714285.714285715
RCC.SDMMCFreq_Value=48000000
RCC.SWPMI1Freq_Value=80000000
RCC.SYSCLKFreq_VALUE=80000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=80000000
RCC.UART5Freq_Value=80000000
RCC.USART1Freq_Value=80000000
RCC.USART2Freq_Value=80000000
RCC.USART3Freq_Value=80000000
RCC.USBFreq_Value=48000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=160000000
RCC.VCOSAI1OutputFreq_Value=96000000
RCC.VCOSAI2OutputFreq_Value=32000000
SH.ADCx_IN1.0=ADC1_IN1
SH.ADCx_IN1.ConfNb=1
SH.ADCx_IN13.0=ADC1_IN13
SH.ADCx_IN13.ConfNb=1
SH.ADCx_IN14.0=ADC1_IN14
SH.ADCx_IN14.ConfNb=1
SH.ADCx_IN16.0=ADC1_IN16
SH.ADCx_IN16.ConfNb=1
SH.ADCx_IN2.0=ADC1_IN2
SH.ADCx_IN2.ConfNb=1
SH.ADCx_IN3.0=ADC1_IN3
SH.ADCx_IN3.ConfNb=1
SH.ADCx_IN4.0=ADC1_IN4
SH.ADCx_IN4.ConfNb=1
SH.ADCx_IN9.0=ADC1_IN9
SH.ADCx_IN9.ConfNb=1
SH.GPXTI0.0=GPIO_EXTI0
SH.GPXTI0.ConfNb=1
SH.GPXTI1.0=GPIO_EXTI1
SH.GPXTI1.ConfNb=1
SH.GPXTI10.0=GPIO_EXTI10
SH.GPXTI10.ConfNb=1
SH.GPXTI11.0=GPIO_EXTI11
SH.GPXTI11.ConfNb=1
SH.GPXTI13.0=GPIO_EXTI13
SH.GPXTI13.ConfNb=1
SH.GPXTI14.0=GPIO_EXTI14
SH.GPXTI14.ConfNb=1
SH.GPXTI15.0=GPIO_EXTI15
SH.GPXTI15.ConfNb=1
SH.GPXTI2.0=GPIO_EXTI2
SH.GPXTI2.ConfNb=1
SH.GPXTI3.0=GPIO_EXTI3
SH.GPXTI3.ConfNb=1
SH.GPXTI5.0=GPIO_EXTI5
SH.GPXTI5.ConfNb=1
SH.GPXTI6.0=GPIO_EXTI6
SH.GPXTI6.ConfNb=1
SH.GPXTI7.0=GPIO_EXTI7
SH.GPXTI7.ConfNb=1
SH.GPXTI8.0=GPIO_EXTI8
SH.GPXTI8.ConfNb=1
SH.S_CKOUTDFSDM1.0=DFSDM1_CKOUT,CKOUT
SH.S_CKOUTDFSDM1.1=DFSDM1_CKOUT,PDM_SPI_Input_from_ch12_and_Internal_Clock
SH.S_CKOUTDFSDM1.ConfNb=2
SH.S_DATAIN2DFSDM1.0=DFSDM1_DATIN2,PDM_SPI_Input_from_ch12_and_Internal_Clock
SH.S_DATAIN2DFSDM1.ConfNb=1
SH.S_TIM2_CH4.0=TIM2_CH4
SH.S_TIM2_CH4.ConfNb=1
SPI3.CalculateBaudRate=40.0 MBits/s
SPI3.Direction=SPI_DIRECTION_2LINES
SPI3.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate
SPI3.Mode=SPI_MODE_MASTER
SPI3.VirtualType=VM_MASTER
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
USART3.IPParameters=VirtualMode-Asynchronous
USART3.VirtualMode-Asynchronous=VM_ASYNC
USB_OTG_FS.IPParameters=VirtualMode
USB_OTG_FS.VirtualMode=Device_Only
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=B-L475E-IOT01A1
boardIOC=true
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

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IDE/STM32Cube/Boards/STM32L4A6.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=131072
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
LPUART1.BaudRate=115200
LPUART1.IPParameters=BaudRate,WordLength
LPUART1.WordLength=UART_WORDLENGTH_8B
Mcu.Family=STM32L4
Mcu.IP0=AES
Mcu.IP1=FREERTOS
Mcu.IP2=HASH
Mcu.IP3=LPUART1
Mcu.IP4=NVIC
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SYS
Mcu.IPNb=9
Mcu.Name=STM32L4A6ZGTx
Mcu.Package=LQFP144
Mcu.Pin0=PG7
Mcu.Pin1=PG8
Mcu.Pin2=VP_AES_VS_AES
Mcu.Pin3=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin4=VP_HASH_VS_HASH
Mcu.Pin5=VP_RNG_VS_RNG
Mcu.Pin6=VP_RTC_VS_RTC_Activate
Mcu.Pin7=VP_RTC_VS_RTC_Calendar
Mcu.Pin8=VP_SYS_VS_tim1
Mcu.Pin9=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.PinsNb=10
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32L4A6ZGTx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_TIM16_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_TIM16_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PG7.Locked=true
PG7.Mode=Asynchronous
PG7.Signal=LPUART1_TX
PG8.Locked=true
PG8.Mode=Asynchronous
PG8.Signal=LPUART1_RX
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32L4A6ZGTx
ProjectManager.FirmwarePackage=STM32Cube FW_L4 V1.15.1
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32L4A6.ioc
ProjectManager.ProjectName=STM32L4A6
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=2-SystemClock_Config-RCC-false-HAL-false
RCC.ADCFreq_Value=32000000
RCC.AHBFreq_Value=80000000
RCC.APB1Freq_Value=80000000
RCC.APB1TimFreq_Value=80000000
RCC.APB2Freq_Value=80000000
RCC.APB2TimFreq_Value=80000000
RCC.CortexFreq_Value=80000000
RCC.DFSDMFreq_Value=80000000
RCC.FCLKCortexFreq_Value=80000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=80000000
RCC.HSE_VALUE=8000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=80000000
RCC.I2C2Freq_Value=80000000
RCC.I2C3Freq_Value=80000000
RCC.I2C4Freq_Value=80000000
RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PLLSAI2RoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
RCC.LPTIM1Freq_Value=80000000
RCC.LPTIM2Freq_Value=80000000
RCC.LPUART1Freq_Value=80000000
RCC.LSCOPinFreq_Value=32000
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=80000000
RCC.MSI_VALUE=4000000
RCC.PLLN=40
RCC.PLLPoutputFreq_Value=80000000
RCC.PLLQoutputFreq_Value=80000000
RCC.PLLRCLKFreq_Value=80000000
RCC.PLLSAI1N=16
RCC.PLLSAI1PoutputFreq_Value=32000000
RCC.PLLSAI1QoutputFreq_Value=32000000
RCC.PLLSAI1RoutputFreq_Value=32000000
RCC.PLLSAI2PoutputFreq_Value=16000000
RCC.PLLSAI2RoutputFreq_Value=16000000
RCC.PWRFreq_Value=80000000
RCC.RNGFreq_Value=32000000
RCC.SAI1Freq_Value=32000000
RCC.SAI2Freq_Value=32000000
RCC.SDMMCFreq_Value=32000000
RCC.SWPMI1Freq_Value=80000000
RCC.SYSCLKFreq_VALUE=80000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=80000000
RCC.UART5Freq_Value=80000000
RCC.USART1Freq_Value=80000000
RCC.USART2Freq_Value=80000000
RCC.USART3Freq_Value=80000000
RCC.USBFreq_Value=32000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=160000000
RCC.VCOSAI1OutputFreq_Value=64000000
RCC.VCOSAI2OutputFreq_Value=32000000
VP_AES_VS_AES.Mode=AES_Activate
VP_AES_VS_AES.Signal=AES_VS_AES
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_HASH_VS_HASH.Mode=HASH_Activate
VP_HASH_VS_HASH.Signal=HASH_VS_HASH
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_RTC_VS_RTC_Calendar.Mode=RTC_Calendar
VP_RTC_VS_RTC_Calendar.Signal=RTC_VS_RTC_Calendar
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=custom
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,WOLFCRYPT_ONLY,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLFCRYPT_ONLY=False
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

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#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag,master
ADC1.NbrOfConversionFlag=1
ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
ADC1.master=1
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,35840,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=180000
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
LPUART1.BaudRate=115200
LPUART1.IPParameters=BaudRate
Mcu.Family=STM32L5
Mcu.IP0=ADC1
Mcu.IP1=DEBUG
Mcu.IP10=SYS
Mcu.IP11=UCPD1
Mcu.IP12=USB
Mcu.IP2=FREERTOS
Mcu.IP3=HASH
Mcu.IP4=LPUART1
Mcu.IP5=NVIC
Mcu.IP6=PWR
Mcu.IP7=RCC
Mcu.IP8=RNG
Mcu.IP9=RTC
Mcu.IPNb=13
Mcu.Name=STM32L552Z(C-E)TxQ
Mcu.Package=LQFP144
Mcu.Pin0=PC13
Mcu.Pin1=PC14-OSC32_IN (PC14)
Mcu.Pin10=PA11
Mcu.Pin11=PA12
Mcu.Pin12=PA13 (JTMS/SWDIO)
Mcu.Pin13=PA14 (JTCK/SWCLK)
Mcu.Pin14=PA15 (JTDI)
Mcu.Pin15=PB3 (JTDO/TRACESWO)
Mcu.Pin16=PB5
Mcu.Pin17=PB7
Mcu.Pin18=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin19=VP_HASH_VS_HASH
Mcu.Pin2=PC15-OSC32_OUT (PC15)
Mcu.Pin20=VP_PWR_VS_DBSignals
Mcu.Pin21=VP_RNG_VS_RNG
Mcu.Pin22=VP_RTC_VS_RTC_Activate
Mcu.Pin23=VP_SYS_VS_tim1
Mcu.Pin24=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.Pin3=PC2
Mcu.Pin4=PB14
Mcu.Pin5=PB15
Mcu.Pin6=PG7
Mcu.Pin7=PG8
Mcu.Pin8=PC7
Mcu.Pin9=PA9
Mcu.PinsNb=25
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.TrustZone=disable
Mcu.UserConstants=
Mcu.UserName=STM32L552ZETxQ
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_3
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA11.Locked=true
PA11.Mode=Device
PA11.Signal=USB_DM
PA12.Mode=Device
PA12.Signal=USB_DP
PA13\ (JTMS/SWDIO).Locked=true
PA13\ (JTMS/SWDIO).Mode=Trace_Asynchronous_SW
PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
PA14\ (JTCK/SWCLK).Locked=true
PA14\ (JTCK/SWCLK).Mode=Trace_Asynchronous_SW
PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
PA15\ (JTDI).Locked=true
PA15\ (JTDI).Mode=Source_AllSignals
PA15\ (JTDI).Signal=UCPD1_CC1
PA9.GPIOParameters=GPIO_Label
PA9.GPIO_Label=LED_RED
PA9.Locked=true
PA9.Signal=GPIO_Output
PB14.GPIOParameters=GPIO_Label
PB14.GPIO_Label=UCPD_FLT
PB14.Locked=true
PB14.Signal=GPXTI14
PB15.Locked=true
PB15.Mode=Source_AllSignals
PB15.Signal=UCPD1_CC2
PB3\ (JTDO/TRACESWO).Locked=true
PB3\ (JTDO/TRACESWO).Mode=Trace_Asynchronous_SW
PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
PB5.GPIOParameters=GPIO_Label
PB5.GPIO_Label=UCPD_DBN
PB5.Locked=true
PB5.Signal=GPIO_Output
PB7.GPIOParameters=GPIO_Label
PB7.GPIO_Label=LED_BLUE
PB7.Locked=true
PB7.Signal=GPIO_Output
PC13.GPIOParameters=GPIO_Label
PC13.GPIO_Label=USER_BUTTON
PC13.Locked=true
PC13.Mode=WakeUp1
PC13.Signal=PWR_WKUP2
PC14-OSC32_IN\ (PC14).Locked=true
PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (PC15).Locked=true
PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
PC2.GPIOParameters=GPIO_Label
PC2.GPIO_Label=VBUS_SENSE
PC2.Locked=true
PC2.Signal=ADCx_IN3
PC7.GPIOParameters=GPIO_Label
PC7.GPIO_Label=LED_GREEN
PC7.Locked=true
PC7.Signal=GPIO_Output
PG7.GPIOParameters=GPIO_Label
PG7.GPIO_Label=ST-LINK_VCP_TX
PG7.Locked=true
PG7.Mode=Asynchronous
PG7.Signal=LPUART1_TX
PG8.GPIOParameters=GPIO_Label
PG8.GPIO_Label=ST-LINK_VCP_RX
PG8.Locked=true
PG8.Mode=Asynchronous
PG8.Signal=LPUART1_RX
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32L552ZETxQ
ProjectManager.FirmwarePackage=STM32Cube FW_L5 V1.2.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32L552.ioc
ProjectManager.ProjectName=STM32L552
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,5-MX_RTC_Init-RTC-false-HAL-true,6-MX_UCPD1_Init-UCPD1-false-LL-true,7-MX_USB_PCD_Init-USB-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_SYSCLK
RCC.ADCFreq_Value=110000000
RCC.AHBFreq_Value=110000000
RCC.APB1Freq_Value=110000000
RCC.APB1TimFreq_Value=110000000
RCC.APB2Freq_Value=110000000
RCC.APB2TimFreq_Value=110000000
RCC.CK48CLockSelection=RCC_USBCLKSOURCE_HSI48
RCC.CRSFreq_Value=48000000
RCC.CortexFreq_Value=110000000
RCC.DFSDMAudioFreq_Value=4000000
RCC.DFSDMFreq_Value=110000000
RCC.FCLKCortexFreq_Value=110000000
RCC.FDCANFreq_Value=110000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=110000000
RCC.HSE_VALUE=8000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=110000000
RCC.I2C2Freq_Value=110000000
RCC.I2C3Freq_Value=110000000
RCC.I2C4Freq_Value=110000000
RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CRSFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI2PoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
RCC.LPTIM1Freq_Value=110000000
RCC.LPTIM2Freq_Value=110000000
RCC.LPTIM3Freq_Value=110000000
RCC.LPUART1Freq_Value=110000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=110000000
RCC.MSI_VALUE=4000000
RCC.OCTOSPIMFreq_Value=110000000
RCC.PLLN=55
RCC.PLLPoutputFreq_Value=31428571.42857143
RCC.PLLQoutputFreq_Value=110000000
RCC.PLLRCLKFreq_Value=110000000
RCC.PLLSAI1N=24
RCC.PLLSAI1PoutputFreq_Value=13714285.714285715
RCC.PLLSAI1QoutputFreq_Value=48000000
RCC.PLLSAI1RoutputFreq_Value=48000000
RCC.PLLSAI2PoutputFreq_Value=4571428.571428572
RCC.PWRFreq_Value=110000000
RCC.RNGFreq_Value=48000000
RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
RCC.RTCFreq_Value=32768
RCC.SAI1Freq_Value=13714285.714285715
RCC.SAI2Freq_Value=13714285.714285715
RCC.SDMMCFreq_Value=31428571.42857143
RCC.SYSCLKFreq_VALUE=110000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=110000000
RCC.UART5Freq_Value=110000000
RCC.USART1Freq_Value=110000000
RCC.USART2Freq_Value=110000000
RCC.USART3Freq_Value=110000000
RCC.USBFreq_Value=48000000
RCC.VCOInput2Freq_Value=4000000
RCC.VCOInput3Freq_Value=4000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=220000000
RCC.VCOSAI1OutputFreq_Value=96000000
RCC.VCOSAI2OutputFreq_Value=32000000
SH.ADCx_IN3.0=ADC1_IN3,IN3-Single-Ended
SH.ADCx_IN3.ConfNb=1
SH.GPXTI14.0=GPIO_EXTI14
SH.GPXTI14.ConfNb=1
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_HASH_VS_HASH.Mode=HASH_Activate
VP_HASH_VS_HASH.Signal=HASH_VS_HASH
VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=NUCLEO-L552ZE-Q
boardIOC=true
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

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IDE/STM32Cube/Boards/STM32L562.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_9
ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,NbrOfConversionFlag
ADC1.NbrOfConversionFlag=1
ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
ADC1.Rank-0\#ChannelRegularConversion=1
ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_2CYCLES_5
ADC1.master=1
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,FootprintOK,configTOTAL_HEAP_SIZE
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,35840,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=180000
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
I2C1.IPParameters=Timing
I2C1.Timing=0x40505681
KeepUserPlacement=false
Mcu.Family=STM32L5
Mcu.IP0=ADC1
Mcu.IP1=AES
Mcu.IP10=NVIC
Mcu.IP11=OCTOSPI1
Mcu.IP12=PKA
Mcu.IP13=PWR
Mcu.IP14=RCC
Mcu.IP15=RNG
Mcu.IP16=RTC
Mcu.IP17=SAI1
Mcu.IP18=SDMMC1
Mcu.IP19=SPI1
Mcu.IP2=DEBUG
Mcu.IP20=SYS
Mcu.IP21=TIM4
Mcu.IP22=TIM16
Mcu.IP23=TIM17
Mcu.IP24=UCPD1
Mcu.IP25=USART1
Mcu.IP26=USB
Mcu.IP3=DFSDM1
Mcu.IP4=FMC
Mcu.IP5=FREERTOS
Mcu.IP6=GTZC
Mcu.IP7=HASH
Mcu.IP8=I2C1
Mcu.IP9=LPUART1
Mcu.IPNb=27
Mcu.Name=STM32L562QEIxQ
Mcu.Package=UFBGA132
Mcu.Pin0=PE5
Mcu.Pin1=PE3
Mcu.Pin10=PE2
Mcu.Pin11=PD4
Mcu.Pin12=PD1
Mcu.Pin13=PC12
Mcu.Pin14=PC10
Mcu.Pin15=PA12
Mcu.Pin16=PC14-OSC32_IN (PC14)
Mcu.Pin17=PE6
Mcu.Pin18=PC13
Mcu.Pin19=PB3 (JTDO/TRACESWO)
Mcu.Pin2=PE1
Mcu.Pin20=PD3
Mcu.Pin21=PD0
Mcu.Pin22=PA13 (JTMS/SWDIO)
Mcu.Pin23=PA14 (JTCK/SWCLK)
Mcu.Pin24=PA11
Mcu.Pin25=PC15-OSC32_OUT (PC15)
Mcu.Pin26=PF0
Mcu.Pin27=PF3
Mcu.Pin28=PB7
Mcu.Pin29=PB5
Mcu.Pin3=PB6
Mcu.Pin30=PD7
Mcu.Pin31=PA9
Mcu.Pin32=PA10
Mcu.Pin33=PA8
Mcu.Pin34=PF2
Mcu.Pin35=PF1
Mcu.Pin36=PC9
Mcu.Pin37=PC8
Mcu.Pin38=PH0-OSC_IN (PH0)
Mcu.Pin39=PC2
Mcu.Pin4=PG12
Mcu.Pin40=PC3
Mcu.Pin41=PG6
Mcu.Pin42=PG7
Mcu.Pin43=PG8
Mcu.Pin44=PC1
Mcu.Pin45=PG4
Mcu.Pin46=PG2
Mcu.Pin47=PG3
Mcu.Pin48=PG5
Mcu.Pin49=PC0
Mcu.Pin5=PD5
Mcu.Pin50=PD14
Mcu.Pin51=PD15
Mcu.Pin52=PF14
Mcu.Pin53=PE8
Mcu.Pin54=PE10
Mcu.Pin55=PE12
Mcu.Pin56=PD9
Mcu.Pin57=PA2
Mcu.Pin58=PA7
Mcu.Pin59=PB2
Mcu.Pin6=PD2
Mcu.Pin60=PF11
Mcu.Pin61=PG1
Mcu.Pin62=PE7
Mcu.Pin63=PE14
Mcu.Pin64=PB10
Mcu.Pin65=PB14
Mcu.Pin66=PB15
Mcu.Pin67=PA3
Mcu.Pin68=PA6
Mcu.Pin69=PA4
Mcu.Pin7=PC11
Mcu.Pin70=PB1
Mcu.Pin71=PF12
Mcu.Pin72=PF15
Mcu.Pin73=PE11
Mcu.Pin74=PE15
Mcu.Pin75=PB11
Mcu.Pin76=PB12
Mcu.Pin77=PD8
Mcu.Pin78=PB0
Mcu.Pin79=PE9
Mcu.Pin8=PA15 (JTDI)
Mcu.Pin80=PE13
Mcu.Pin81=PD10
Mcu.Pin82=VP_AES_VS_AES
Mcu.Pin83=VP_DFSDM1_VS_IN0
Mcu.Pin84=VP_DFSDM1_VS_IN2
Mcu.Pin85=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin86=VP_GTZC_VS_GTZC_Enable
Mcu.Pin87=VP_HASH_VS_HASH
Mcu.Pin88=VP_PKA_VS_PKA
Mcu.Pin89=VP_PWR_VS_DBSignals
Mcu.Pin9=PE4
Mcu.Pin90=VP_RNG_VS_RNG
Mcu.Pin91=VP_RTC_VS_RTC_Activate
Mcu.Pin92=VP_SYS_VS_tim1
Mcu.Pin93=VP_SYS_S_VS_Systick
Mcu.Pin94=VP_TIM4_VS_ControllerModeClock
Mcu.Pin95=VP_TIM4_VS_ClockSourceITR
Mcu.Pin96=VP_TIM16_VS_ClockSourceINT
Mcu.Pin97=VP_TIM17_VS_ClockSourceINT
Mcu.Pin98=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.PinsNb=99
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.TrustZone=disable
Mcu.UserConstants=
Mcu.UserName=STM32L562QEIxQ
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_3
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:7\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM1_UP_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_UP_IRQn
NVIC.TimeBaseIP=TIM1
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA10.GPIOParameters=GPIO_Label
PA10.GPIO_Label=USART1_RX [ST-LINK_VCP_TX]
PA10.Locked=true
PA10.Mode=Asynchronous
PA10.Signal=USART1_RX
PA11.Locked=true
PA11.Mode=Device
PA11.Signal=USB_DM
PA12.Locked=true
PA12.Mode=Device
PA12.Signal=USB_DP
PA13\ (JTMS/SWDIO).Locked=true
PA13\ (JTMS/SWDIO).Mode=Trace_Asynchronous_SW
PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
PA14\ (JTCK/SWCLK).Locked=true
PA14\ (JTCK/SWCLK).Mode=Trace_Asynchronous_SW
PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
PA15\ (JTDI).Locked=true
PA15\ (JTDI).Mode=Source_AllSignals
PA15\ (JTDI).Signal=UCPD1_CC1
PA2.Locked=true
PA2.Mode=octods_mode
PA2.Signal=OCTOSPI1_NCS
PA3.Locked=true
PA3.Mode=octods_mode
PA3.Signal=OCTOSPI1_CLK
PA4.GPIOParameters=GPIO_Label
PA4.GPIO_Label=VBUS_SENSE
PA4.Locked=true
PA4.Signal=ADCx_IN9
PA6.Locked=true
PA6.Mode=octods_mode
PA6.Signal=OCTOSPI1_IO3
PA7.Locked=true
PA7.Mode=octods_mode
PA7.Signal=OCTOSPI1_IO2
PA8.GPIOParameters=GPIO_Label
PA8.GPIO_Label=LCD.TE
PA8.Locked=true
PA8.Signal=GPIO_Output
PA9.GPIOParameters=GPIO_Label
PA9.GPIO_Label=USART1_TX [ST-LINK_VCP_RX]
PA9.Locked=true
PA9.Mode=Asynchronous
PA9.Signal=USART1_TX
PB0.Locked=true
PB0.Mode=octods_mode
PB0.Signal=OCTOSPI1_IO1
PB1.Locked=true
PB1.Mode=octods_mode
PB1.Signal=OCTOSPI1_IO0
PB10.Locked=true
PB10.Mode=Asynchronous
PB10.Signal=LPUART1_RX
PB11.Locked=true
PB11.Mode=Asynchronous
PB11.Signal=LPUART1_TX
PB12.Locked=true
PB12.Signal=S_DATAIN1DFSDM1
PB14.GPIOParameters=GPIO_Label
PB14.GPIO_Label=UCPD_FLT
PB14.Locked=true
PB14.Signal=GPIO_Input
PB15.Locked=true
PB15.Mode=Source_AllSignals
PB15.Signal=UCPD1_CC2
PB2.Locked=true
PB2.Mode=octods_mode
PB2.Signal=OCTOSPI1_DQS
PB3\ (JTDO/TRACESWO).Locked=true
PB3\ (JTDO/TRACESWO).Mode=Trace_Asynchronous_SW
PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
PB5.GPIOParameters=GPIO_Label
PB5.GPIO_Label=UCPD_DBn
PB5.Locked=true
PB5.Signal=GPIO_Output
PB6.Locked=true
PB6.Mode=I2C
PB6.Signal=I2C1_SCL
PB7.Locked=true
PB7.Mode=I2C
PB7.Signal=I2C1_SDA
PC0.Locked=true
PC0.Mode=octods_mode
PC0.Signal=OCTOSPI1_IO7
PC1.Locked=true
PC1.Mode=octods_mode
PC1.Signal=OCTOSPI1_IO4
PC10.Locked=true
PC10.Mode=SD_4_bits_Wide_bus
PC10.Signal=SDMMC1_D2
PC11.Locked=true
PC11.Mode=SD_4_bits_Wide_bus
PC11.Signal=SDMMC1_D3
PC12.Locked=true
PC12.Mode=SD_4_bits_Wide_bus
PC12.Signal=SDMMC1_CK
PC13.GPIOParameters=GPIO_Label
PC13.GPIO_Label=USER_BUTTON
PC13.Locked=true
PC13.Signal=GPIO_Input
PC14-OSC32_IN\ (PC14).Locked=true
PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator
PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN
PC15-OSC32_OUT\ (PC15).Locked=true
PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator
PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT
PC2.Locked=true
PC2.Mode=octods_mode
PC2.Signal=OCTOSPI1_IO5
PC3.Locked=true
PC3.Mode=octods_mode
PC3.Signal=OCTOSPI1_IO6
PC8.Locked=true
PC8.Mode=SD_4_bits_Wide_bus
PC8.Signal=SDMMC1_D0
PC9.Locked=true
PC9.Mode=SD_4_bits_Wide_bus
PC9.Signal=SDMMC1_D1
PD0.Locked=true
PD0.Signal=FMC_D2_DA2
PD1.Locked=true
PD1.Signal=FMC_D3_DA3
PD10.Locked=true
PD10.Signal=FMC_D15_DA15
PD14.Locked=true
PD14.Signal=FMC_D0_DA0
PD15.Locked=true
PD15.Signal=FMC_D1_DA1
PD2.Locked=true
PD2.Mode=SD_4_bits_Wide_bus
PD2.Signal=SDMMC1_CMD
PD3.GPIOParameters=GPIO_Label
PD3.GPIO_Label=LED_RED
PD3.Locked=true
PD3.Signal=GPIO_Output
PD4.Locked=true
PD4.Signal=FMC_NOE
PD5.Locked=true
PD5.Signal=FMC_NWE
PD7.Locked=true
PD7.Mode=NorPsramChipSelect1_1
PD7.Signal=FMC_NE1
PD8.Locked=true
PD8.Signal=FMC_D13_DA13
PD9.Locked=true
PD9.Signal=FMC_D14_DA14
PE1.GPIOParameters=GPIO_Label
PE1.GPIO_Label=LCD_BL_PWM
PE1.Locked=true
PE1.Signal=S_TIM17_CH1
PE10.Locked=true
PE10.Signal=FMC_D7_DA7
PE11.Locked=true
PE11.Signal=FMC_D8_DA8
PE12.Locked=true
PE12.Signal=FMC_D9_DA9
PE13.Locked=true
PE13.Signal=FMC_D10_DA10
PE14.Locked=true
PE14.Signal=FMC_D11_DA11
PE15.Locked=true
PE15.Signal=FMC_D12_DA12
PE2.Locked=true
PE2.Mode=SAI_A_MasterWithClock
PE2.Signal=SAI1_MCLK_A
PE3.Locked=true
PE3.Mode=SAI_B_SPDIF
PE3.Signal=SAI1_SD_B
PE4.Locked=true
PE4.Mode=SAI_A_MasterWithClock
PE4.Signal=SAI1_FS_A
PE5.Locked=true
PE5.Mode=SAI_A_MasterWithClock
PE5.Signal=SAI1_SCK_A
PE6.Locked=true
PE6.Mode=SAI_A_MasterWithClock
PE6.Signal=SAI1_SD_A
PE7.Locked=true
PE7.Signal=FMC_D4_DA4
PE8.Locked=true
PE8.Signal=FMC_D5_DA5
PE9.Locked=true
PE9.Signal=FMC_D6_DA6
PF0.Locked=true
PF0.Signal=FMC_A0
PF1.GPIOParameters=GPIO_Label
PF1.GPIO_Label=CTP_INT
PF1.Locked=true
PF1.Signal=GPXTI1
PF11.GPIOParameters=GPIO_Label
PF11.GPIO_Label=STMOD_SEL_12
PF11.Locked=true
PF11.Signal=GPIO_Output
PF12.GPIOParameters=GPIO_Label
PF12.GPIO_Label=STMOD_SEL_34
PF12.Locked=true
PF12.Signal=GPIO_Output
PF14.GPIOParameters=GPIO_Label
PF14.GPIO_Label=LCD_RST
PF14.Locked=true
PF14.Signal=GPIO_Output
PF15.GPIOParameters=GPIO_Label
PF15.GPIO_Label=CTP_RST
PF15.Locked=true
PF15.Signal=GPIO_Output
PF2.GPIOParameters=GPIO_Label
PF2.GPIO_Label=SDIO_DETECT
PF2.Locked=true
PF2.Signal=GPXTI2
PF3.GPIOParameters=GPIO_Label
PF3.GPIO_Label=GYRO_ACC_INT
PF3.Locked=true
PF3.Signal=GPXTI3
PG1.GPIOParameters=GPIO_Label
PG1.GPIO_Label=AUDIO_RESETN
PG1.Locked=true
PG1.Signal=GPIO_Output
PG12.GPIOParameters=GPIO_Label
PG12.GPIO_Label=LED_GREEN
PG12.Locked=true
PG12.Signal=GPIO_Output
PG2.Locked=true
PG2.Mode=Full_Duplex_Master
PG2.Signal=SPI1_SCK
PG3.Locked=true
PG3.Mode=Full_Duplex_Master
PG3.Signal=SPI1_MISO
PG4.Locked=true
PG4.Mode=Full_Duplex_Master
PG4.Signal=SPI1_MOSI
PG5.GPIOParameters=GPIO_Label
PG5.GPIO_Label=BLE_CSN
PG5.Locked=true
PG5.Mode=NSS_Signal_Hard_Input
PG5.Signal=SPI1_NSS
PG6.GPIOParameters=GPIO_Label
PG6.GPIO_Label=BLE_INT
PG6.Locked=true
PG6.Signal=GPXTI6
PG7.Locked=true
PG7.Signal=S_CKOUTDFSDM1
PG8.GPIOParameters=GPIO_Label
PG8.GPIO_Label=BLE_RSTN
PG8.Locked=true
PG8.Signal=GPIO_Output
PH0-OSC_IN\ (PH0).GPIOParameters=GPIO_Label
PH0-OSC_IN\ (PH0).GPIO_Label=LCD_PWR_ON
PH0-OSC_IN\ (PH0).Locked=true
PH0-OSC_IN\ (PH0).Signal=GPIO_Output
PinOutPanel.CurrentBGAView=Top
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32L562QEIxQ
ProjectManager.FirmwarePackage=STM32Cube FW_L5 V1.2.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32L562.ioc
ProjectManager.ProjectName=STM32L562
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_DFSDM1_Init-DFSDM1-false-HAL-true,5-MX_FMC_Init-FMC-false-HAL-true,6-MX_GTZC_Init-GTZC-false-HAL-true,7-MX_I2C1_Init-I2C1-false-HAL-true,8-MX_LPUART1_UART_Init-LPUART1-false-HAL-true,9-MX_USART1_UART_Init-USART1-false-HAL-true,10-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,11-MX_SAI1_Init-SAI1-false-HAL-true,12-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,13-MX_SPI1_Init-SPI1-false-HAL-true,14-MX_TIM4_Init-TIM4-false-HAL-true,15-MX_TIM16_Init-TIM16-false-HAL-true,16-MX_TIM17_Init-TIM17-false-HAL-true,17-MX_UCPD1_Init-UCPD1-false-LL-true,18-MX_USB_PCD_Init-USB-false-HAL-true,19-MX_AES_Init-AES-false-HAL-true,20-MX_HASH_Init-HASH-false-HAL-true,21-MX_PKA_Init-PKA-false-HAL-true,22-MX_RNG_Init-RNG-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
RCC.ADCFreq_Value=96000000
RCC.AHBFreq_Value=110000000
RCC.APB1Freq_Value=110000000
RCC.APB1TimFreq_Value=110000000
RCC.APB2Freq_Value=110000000
RCC.APB2TimFreq_Value=110000000
RCC.CK48CLockSelection=RCC_USBCLKSOURCE_MSI
RCC.CRSFreq_Value=48000000
RCC.CortexFreq_Value=110000000
RCC.DFSDMAudioFreq_Value=48000000
RCC.DFSDMFreq_Value=110000000
RCC.FCLKCortexFreq_Value=110000000
RCC.FDCANFreq_Value=110000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=110000000
RCC.HSE_VALUE=8000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=110000000
RCC.I2C2Freq_Value=110000000
RCC.I2C3Freq_Value=110000000
RCC.I2C4Freq_Value=110000000
RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CRSFreq_Value,CortexFreq_Value,DFSDMAudioFreq_Value,DFSDMFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,MSIClockRange,MSI_VALUE,OCTOSPIMFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1M,PLLSAI1N,PLLSAI1P,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PLLSAI1Source,PLLSAI2PoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value,VCOSAI2OutputFreq_Value
RCC.LPTIM1Freq_Value=110000000
RCC.LPTIM2Freq_Value=110000000
RCC.LPTIM3Freq_Value=110000000
RCC.LPUART1Freq_Value=110000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=110000000
RCC.MSIClockRange=RCC_MSIRANGE_11
RCC.MSI_VALUE=48000000
RCC.OCTOSPIMFreq_Value=110000000
RCC.PLLM=12
RCC.PLLN=55
RCC.PLLPoutputFreq_Value=31428571.42857143
RCC.PLLQoutputFreq_Value=110000000
RCC.PLLRCLKFreq_Value=110000000
RCC.PLLSAI1M=4
RCC.PLLSAI1N=48
RCC.PLLSAI1P=RCC_PLLP_DIV17
RCC.PLLSAI1PoutputFreq_Value=11294117.647058824
RCC.PLLSAI1QoutputFreq_Value=96000000
RCC.PLLSAI1RoutputFreq_Value=96000000
RCC.PLLSAI1Source=RCC_PLLSAI1SOURCE_HSI
RCC.PLLSAI2PoutputFreq_Value=54857142.85714286
RCC.PWRFreq_Value=110000000
RCC.RNGFreq_Value=48000000
RCC.SAI1Freq_Value=11294117.647058824
RCC.SAI2Freq_Value=11294117.647058824
RCC.SDMMCClockSelection=RCC_SDIOCLKSOURCE_CLK48
RCC.SDMMCFreq_Value=48000000
RCC.SYSCLKFreq_VALUE=110000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=110000000
RCC.UART5Freq_Value=110000000
RCC.USART1Freq_Value=110000000
RCC.USART2Freq_Value=110000000
RCC.USART3Freq_Value=110000000
RCC.USBFreq_Value=48000000
RCC.VCOInput2Freq_Value=4000000
RCC.VCOInput3Freq_Value=48000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=220000000
RCC.VCOSAI1OutputFreq_Value=192000000
RCC.VCOSAI2OutputFreq_Value=384000000
SAI1.ErrorAudioFreq-SAI_A_MasterWithClock=-77.02 %
SAI1.IPParameters=Instance-SAI_B_SPDIF,VirtualMode-SAI_B_SPDIF,RealAudioFreq-SAI_B_SPDIF,Instance-SAI_A_MasterWithClock,VirtualMode-SAI_A_MasterWithClock,MckOutput-SAI_A_MasterWithClock,RealAudioFreq-SAI_A_MasterWithClock,ErrorAudioFreq-SAI_A_MasterWithClock
SAI1.Instance-SAI_A_MasterWithClock=SAI$Index_Block_A
SAI1.Instance-SAI_B_SPDIF=SAI$Index_Block_B
SAI1.MckOutput-SAI_A_MasterWithClock=SAI_MCK_OUTPUT_ENABLE
SAI1.RealAudioFreq-SAI_A_MasterWithClock=44.117 KHz
SAI1.RealAudioFreq-SAI_B_SPDIF=214.285 KHz
SAI1.VirtualMode-SAI_A_MasterWithClock=VM_MASTER
SAI1.VirtualMode-SAI_B_SPDIF=VM_SPDIF
SH.ADCx_IN9.0=ADC1_IN9,IN9-Single-Ended
SH.ADCx_IN9.ConfNb=1
SH.FMC_A0.0=FMC_A0,A0_1
SH.FMC_A0.ConfNb=1
SH.FMC_D0_DA0.0=FMC_DA0
SH.FMC_D0_DA0.1=FMC_D0,16b-d1
SH.FMC_D0_DA0.ConfNb=2
SH.FMC_D10_DA10.0=FMC_DA10
SH.FMC_D10_DA10.1=FMC_D10,16b-d1
SH.FMC_D10_DA10.ConfNb=2
SH.FMC_D11_DA11.0=FMC_DA11
SH.FMC_D11_DA11.1=FMC_D11,16b-d1
SH.FMC_D11_DA11.ConfNb=2
SH.FMC_D12_DA12.0=FMC_DA12
SH.FMC_D12_DA12.1=FMC_D12,16b-d1
SH.FMC_D12_DA12.ConfNb=2
SH.FMC_D13_DA13.0=FMC_DA13
SH.FMC_D13_DA13.1=FMC_D13,16b-d1
SH.FMC_D13_DA13.ConfNb=2
SH.FMC_D14_DA14.0=FMC_DA14
SH.FMC_D14_DA14.1=FMC_D14,16b-d1
SH.FMC_D14_DA14.ConfNb=2
SH.FMC_D15_DA15.0=FMC_DA15
SH.FMC_D15_DA15.1=FMC_D15,16b-d1
SH.FMC_D15_DA15.ConfNb=2
SH.FMC_D1_DA1.0=FMC_DA1
SH.FMC_D1_DA1.1=FMC_D1,16b-d1
SH.FMC_D1_DA1.ConfNb=2
SH.FMC_D2_DA2.0=FMC_DA2
SH.FMC_D2_DA2.1=FMC_D2,16b-d1
SH.FMC_D2_DA2.ConfNb=2
SH.FMC_D3_DA3.0=FMC_DA3
SH.FMC_D3_DA3.1=FMC_D3,16b-d1
SH.FMC_D3_DA3.ConfNb=2
SH.FMC_D4_DA4.0=FMC_DA4
SH.FMC_D4_DA4.1=FMC_D4,16b-d1
SH.FMC_D4_DA4.ConfNb=2
SH.FMC_D5_DA5.0=FMC_DA5
SH.FMC_D5_DA5.1=FMC_D5,16b-d1
SH.FMC_D5_DA5.ConfNb=2
SH.FMC_D6_DA6.0=FMC_DA6
SH.FMC_D6_DA6.1=FMC_D6,16b-d1
SH.FMC_D6_DA6.ConfNb=2
SH.FMC_D7_DA7.0=FMC_DA7
SH.FMC_D7_DA7.1=FMC_D7,16b-d1
SH.FMC_D7_DA7.ConfNb=2
SH.FMC_D8_DA8.0=FMC_DA8
SH.FMC_D8_DA8.1=FMC_D8,16b-d1
SH.FMC_D8_DA8.ConfNb=2
SH.FMC_D9_DA9.0=FMC_DA9
SH.FMC_D9_DA9.1=FMC_D9,16b-d1
SH.FMC_D9_DA9.ConfNb=2
SH.FMC_NOE.0=FMC_NOE,Lcd1
SH.FMC_NOE.ConfNb=1
SH.FMC_NWE.0=FMC_NWE,Lcd1
SH.FMC_NWE.ConfNb=1
SH.GPXTI1.0=GPIO_EXTI1
SH.GPXTI1.ConfNb=1
SH.GPXTI2.0=GPIO_EXTI2
SH.GPXTI2.ConfNb=1
SH.GPXTI3.0=GPIO_EXTI3
SH.GPXTI3.ConfNb=1
SH.GPXTI6.0=GPIO_EXTI6
SH.GPXTI6.ConfNb=1
SH.S_CKOUTDFSDM1.0=DFSDM1_CKOUT,CKOUT
SH.S_CKOUTDFSDM1.ConfNb=1
SH.S_DATAIN1DFSDM1.0=DFSDM1_DATIN1,Manchester_input_from_ch1
SH.S_DATAIN1DFSDM1.ConfNb=1
SH.S_TIM17_CH1.0=TIM17_CH1,PWM Generation1 CH1
SH.S_TIM17_CH1.ConfNb=1
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_8
SPI1.CalculateBaudRate=13.75 MBits/s
SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS,BaudRatePrescaler
SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualNSS=VM_NSSHARD
SPI1.VirtualType=VM_MASTER
TIM17.Channel=TIM_CHANNEL_1
TIM17.IPParameters=Channel
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
VP_AES_VS_AES.Mode=AES_Activate
VP_AES_VS_AES.Signal=AES_VS_AES
VP_DFSDM1_VS_IN0.Mode=Parallel_Input_ch0
VP_DFSDM1_VS_IN0.Signal=DFSDM1_VS_IN0
VP_DFSDM1_VS_IN2.Mode=Parallel_Input_ch2
VP_DFSDM1_VS_IN2.Signal=DFSDM1_VS_IN2
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_GTZC_VS_GTZC_Enable.Mode=GTZC_Enable
VP_GTZC_VS_GTZC_Enable.Signal=GTZC_VS_GTZC_Enable
VP_HASH_VS_HASH.Mode=HASH_Activate
VP_HASH_VS_HASH.Signal=HASH_VS_HASH
VP_PKA_VS_PKA.Mode=PKA_Activate
VP_PKA_VS_PKA.Signal=PKA_VS_PKA
VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals
VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_S_VS_Systick.Mode=SysTick
VP_SYS_S_VS_Systick.Signal=SYS_S_VS_Systick
VP_SYS_VS_tim1.Mode=TIM1
VP_SYS_VS_tim1.Signal=SYS_VS_tim1
VP_TIM16_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM16_VS_ClockSourceINT.Signal=TIM16_VS_ClockSourceINT
VP_TIM17_VS_ClockSourceINT.Mode=Enable_Timer
VP_TIM17_VS_ClockSourceINT.Signal=TIM17_VS_ClockSourceINT
VP_TIM4_VS_ClockSourceITR.Mode=TriggerSource_ITR1
VP_TIM4_VS_ClockSourceITR.Signal=TIM4_VS_ClockSourceITR
VP_TIM4_VS_ControllerModeClock.Mode=Clock Mode
VP_TIM4_VS_ControllerModeClock.Signal=TIM4_VS_ControllerModeClock
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=STM32L562E-DK
boardIOC=true
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

256
IDE/STM32Cube/Boards/STM32WB55.ioc Normal file
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#MicroXplorer Configuration settings - do not modify
FREERTOS.FootprintOK=true
FREERTOS.IPParameters=Tasks01,configTOTAL_HEAP_SIZE,configUSE_MALLOC_FAILED_HOOK,configCHECK_FOR_STACK_OVERFLOW,configUSE_DAEMON_TASK_STARTUP_HOOK,FootprintOK
FREERTOS.Tasks01=defaultTask,24,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL;wolfCrypt,8,8960,wolfCryptDemo,As external,NULL,Dynamic,NULL,NULL
FREERTOS.configCHECK_FOR_STACK_OVERFLOW=2
FREERTOS.configTOTAL_HEAP_SIZE=184320
FREERTOS.configUSE_DAEMON_TASK_STARTUP_HOOK=1
FREERTOS.configUSE_MALLOC_FAILED_HOOK=1
File.Version=6
KeepUserPlacement=false
Mcu.Family=STM32WB
Mcu.IP0=AES1
Mcu.IP1=AES2
Mcu.IP10=USB
Mcu.IP2=FREERTOS
Mcu.IP3=NVIC
Mcu.IP4=PKA
Mcu.IP5=RCC
Mcu.IP6=RNG
Mcu.IP7=RTC
Mcu.IP8=SYS
Mcu.IP9=USART1
Mcu.IPNb=11
Mcu.Name=STM32WB55RGVx
Mcu.Package=VFQFPN68
Mcu.Pin0=PC13
Mcu.Pin1=PC14-OSC32_IN
Mcu.Pin10=PA11
Mcu.Pin11=PA12
Mcu.Pin12=PA13
Mcu.Pin13=PA14
Mcu.Pin14=PD0
Mcu.Pin15=PD1
Mcu.Pin16=PB3
Mcu.Pin17=PB5
Mcu.Pin18=PB6
Mcu.Pin19=PB7
Mcu.Pin2=PC15-OSC32_OUT
Mcu.Pin20=VP_AES1_VS_AES
Mcu.Pin21=VP_AES2_VS_AES
Mcu.Pin22=VP_FREERTOS_VS_CMSIS_V2
Mcu.Pin23=VP_PKA_VS_PKA
Mcu.Pin24=VP_RNG_VS_RNG
Mcu.Pin25=VP_RTC_VS_RTC_Activate
Mcu.Pin26=VP_SYS_VS_tim2
Mcu.Pin27=VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
Mcu.Pin3=PA2
Mcu.Pin4=PA3
Mcu.Pin5=PC4
Mcu.Pin6=OSC_OUT
Mcu.Pin7=OSC_IN
Mcu.Pin8=PB0
Mcu.Pin9=PB1
Mcu.PinsNb=28
Mcu.ThirdParty0=wolfSSL.wolfSSL.4.4.1
Mcu.ThirdPartyNb=1
Mcu.UserConstants=
Mcu.UserName=STM32WB55RGVx
MxCube.Version=5.6.1
MxDb.Version=DB.5.0.60
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.ForceEnableDMAVector=true
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false
NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false
NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM2_IRQn
NVIC.TimeBaseIP=TIM2
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
OSC_IN.Locked=true
OSC_IN.Mode=HSE-External-Oscillator
OSC_IN.Signal=RCC_OSC_IN
OSC_OUT.Locked=true
OSC_OUT.Mode=HSE-External-Oscillator
OSC_OUT.Signal=RCC_OSC_OUT
PA11.Locked=true
PA11.Mode=Device
PA11.Signal=USB_DM
PA12.Locked=true
PA12.Mode=Device
PA12.Signal=USB_DP
PA13.GPIOParameters=GPIO_Label
PA13.GPIO_Label=JTMS
PA13.Locked=true
PA13.Mode=Trace_Asynchronous_SW
PA13.Signal=SYS_JTMS-SWDIO
PA14.GPIOParameters=GPIO_Label
PA14.GPIO_Label=JTCK
PA14.Locked=true
PA14.Mode=Trace_Asynchronous_SW
PA14.Signal=SYS_JTCK-SWCLK
PA2.Locked=true
PA2.Signal=LPUART1_TX
PA3.Locked=true
PA3.Signal=LPUART1_RX
PB0.GPIOParameters=GPIO_Label
PB0.GPIO_Label=LD2 [Green Led]
PB0.Locked=true
PB0.Signal=GPIO_Output
PB1.GPIOParameters=GPIO_Label
PB1.GPIO_Label=LD3 [Red Led]
PB1.Locked=true
PB1.Signal=GPIO_Output
PB3.GPIOParameters=GPIO_Label
PB3.GPIO_Label=JTDO
PB3.Locked=true
PB3.Mode=Trace_Asynchronous_SW
PB3.Signal=SYS_JTDO-SWO
PB5.GPIOParameters=GPIO_Label
PB5.GPIO_Label=LD1 [Blue Led]
PB5.Locked=true
PB5.Signal=GPIO_Output
PB6.Locked=true
PB6.Mode=Asynchronous
PB6.Signal=USART1_TX
PB7.Locked=true
PB7.Mode=Asynchronous
PB7.Signal=USART1_RX
PC13.Locked=true
PC13.Mode=SYS_WakeUp1
PC13.Signal=SYS_WKUP2
PC14-OSC32_IN.Locked=true
PC14-OSC32_IN.Mode=LSE-External-Oscillator
PC14-OSC32_IN.Signal=RCC_OSC32_IN
PC15-OSC32_OUT.Locked=true
PC15-OSC32_OUT.Mode=LSE-External-Oscillator
PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
PC4.GPIOParameters=GPIO_Label
PC4.GPIO_Label=B1 [Push Button]
PC4.Locked=true
PC4.Signal=GPIO_Input
PCC.Ble.ConnectionInterval=1000.0
PCC.Ble.DataLength=6
PCC.Ble.Mode=NOT_SELECTED
PCC.Ble.PowerLevel=Min
PD0.GPIOParameters=GPIO_Label
PD0.GPIO_Label=B2 [Push Button]
PD0.Locked=true
PD0.Signal=GPIO_Input
PD1.GPIOParameters=GPIO_Label
PD1.GPIO_Label=B3 [Push Button]
PD1.Locked=true
PD1.Signal=GPIO_Input
PinOutPanel.RotationAngle=0
ProjectManager.AskForMigrate=true
ProjectManager.BackupPrevious=false
ProjectManager.CompilerOptimize=6
ProjectManager.ComputerToolchain=false
ProjectManager.CoupleFile=false
ProjectManager.CustomerFirmwarePackage=
ProjectManager.DefaultFWLocation=true
ProjectManager.DeletePrevious=true
ProjectManager.DeviceId=STM32WB55RGVx
ProjectManager.FirmwarePackage=STM32Cube FW_WB V1.7.0
ProjectManager.FreePins=false
ProjectManager.HalAssertFull=false
ProjectManager.HeapSize=0x200
ProjectManager.KeepUserCode=true
ProjectManager.LastFirmware=true
ProjectManager.LibraryCopy=1
ProjectManager.MainLocation=Core/Src
ProjectManager.NoMain=false
ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=STM32WB55.ioc
ProjectManager.ProjectName=STM32WB55
ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=STM32CubeIDE
ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_USB_PCD_Init-USB-false-HAL-true,5-MX_AES1_Init-AES1-false-HAL-true,6-MX_AES2_Init-AES2-false-HAL-true,7-MX_PKA_Init-PKA-false-HAL-true,8-MX_RNG_Init-RNG-false-HAL-true,9-MX_RTC_Init-RTC-false-HAL-true
RCC.ADCFreq_Value=48000000
RCC.AHB2CLKDivider=RCC_SYSCLK_DIV2
RCC.AHBFreq_Value=64000000
RCC.APB1Freq_Value=64000000
RCC.APB1TimFreq_Value=64000000
RCC.APB2Freq_Value=64000000
RCC.APB2TimFreq_Value=64000000
RCC.APB3Freq_Value=16000000
RCC.Cortex2Freq_Value=32000000
RCC.CortexFreq_Value=64000000
RCC.FCLK2Freq_Value=32000000
RCC.FCLKCortexFreq_Value=64000000
RCC.FamilyName=M
RCC.HCLK2Freq_Value=32000000
RCC.HCLK3Freq_Value=64000000
RCC.HCLKFreq_Value=64000000
RCC.HCLKRFFreq_Value=16000000
RCC.HSE_VALUE=32000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=64000000
RCC.I2C3Freq_Value=64000000
RCC.IPParameters=ADCFreq_Value,AHB2CLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,Cortex2Freq_Value,CortexFreq_Value,FCLK2Freq_Value,FCLKCortexFreq_Value,FamilyName,HCLK2Freq_Value,HCLK3Freq_Value,HCLKFreq_Value,HCLKRFFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C3Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSI_VALUE,MCO1PinFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSAI1N,PLLSAI1PoutputFreq_Value,PLLSAI1QoutputFreq_Value,PLLSAI1RoutputFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SMPS1Freq_Value,SMPSCLockSelectionVirtual,SMPSCLockSelectionVirtualVirtual,SMPSDivider,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAI1OutputFreq_Value
RCC.LPTIM1Freq_Value=64000000
RCC.LPTIM2Freq_Value=64000000
RCC.LPUART1Freq_Value=64000000
RCC.LSCOPinFreq_Value=32000
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=64000000
RCC.PLLN=32
RCC.PLLPoutputFreq_Value=64000000
RCC.PLLQoutputFreq_Value=64000000
RCC.PLLRCLKFreq_Value=64000000
RCC.PLLSAI1N=24
RCC.PLLSAI1PoutputFreq_Value=48000000
RCC.PLLSAI1QoutputFreq_Value=48000000
RCC.PLLSAI1RoutputFreq_Value=48000000
RCC.PWRFreq_Value=64000000
RCC.RNGFreq_Value=32000
RCC.SAI1Freq_Value=48000000
RCC.SMPS1Freq_Value=16000000
RCC.SMPSCLockSelectionVirtual=RCC_SMPSCLKSOURCE_HSI
RCC.SMPSCLockSelectionVirtualVirtual=RCC_SMPSCLKSOURCE_HSI
RCC.SMPSDivider=1
RCC.SYSCLKFreq_VALUE=64000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.USART1Freq_Value=64000000
RCC.USBFreq_Value=48000000
RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=128000000
RCC.VCOSAI1OutputFreq_Value=96000000
USART1.IPParameters=VirtualMode-Asynchronous
USART1.VirtualMode-Asynchronous=VM_ASYNC
VP_AES1_VS_AES.Mode=AES_Activate
VP_AES1_VS_AES.Signal=AES1_VS_AES
VP_AES2_VS_AES.Mode=AES_Activate
VP_AES2_VS_AES.Signal=AES2_VS_AES
VP_FREERTOS_VS_CMSIS_V2.Mode=CMSIS_V2
VP_FREERTOS_VS_CMSIS_V2.Signal=FREERTOS_VS_CMSIS_V2
VP_PKA_VS_PKA.Mode=PKA_Activate
VP_PKA_VS_PKA.Signal=PKA_VS_PKA
VP_RNG_VS_RNG.Mode=RNG_Activate
VP_RNG_VS_RNG.Signal=RNG_VS_RNG
VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
VP_SYS_VS_tim2.Mode=TIM2
VP_SYS_VS_tim2.Signal=SYS_VS_tim2
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Mode=wolfSSLJjwolfSSL
VP_wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1.Signal=wolfSSL.wolfSSL_VS_wolfSSLJjwolfSSL_4.4.1
board=P-NUCLEO-WB55-Nucleo
boardIOC=true
wolfSSL.wolfSSL.4.4.1.IPParameters=wolfSSLCcwolfSSLJjwolfSSLJjCore,wolfSSLCcwolfSSLJjwolfCryptJjCore,wolfSSLCcwolfSSLJjwolfCryptJjTest,WOLF_CONF_MATH,WOLF_CONF_RTOS
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_MATH=4
wolfSSL.wolfSSL.4.4.1.WOLF_CONF_RTOS=2
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfCryptJjTest=true
wolfSSL.wolfSSL.4.4.1.wolfSSLCcwolfSSLJjwolfSSLJjCore=true
wolfSSL.wolfSSL.4.4.1.wolfSSLJjwolfSSL_Checked=true
wolfSSL.wolfSSL.4.4.1_SwParameter=wolfSSLCcwolfSSLJjwolfCryptJjCore\:true;wolfSSLCcwolfSSLJjwolfCryptJjTest\:true;wolfSSLCcwolfSSLJjwolfSSLJjCore\:true;
isbadioc=false

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# wolfSSL STM32 Example for STM32 Cube IDE
This example includes:
* wolfCrypt test
* wolfCrypt benchmark
* wolfSSL TLS client/server test using in-memory transfers
These examples use the CubeMX Hal for STM32. If you'd like to use the older Standard Peripheral library undefine `WOLFSSL_STM32_CUBEMX` in `user_settings.h`.
## Requirements
* STM32CubeIDE: Integrated Development Environment for STM32 [https://www.st.com/en/development-tools/stm32cubeide.html](https://www.st.com/en/development-tools/stm32cubeide.html)
## Setup
1. Using the STM32CubeMX tool, load the `<wolfssl-root>/IDE/STM32Cube/Boards/*.ioc` file for your target.
2. Adjust the HAL options based on your specific micro-controller.
3. Enable the security RNG/HASH/CRYPT if available.
4. Enable the RTC and UART if available.
5. Add wolfSSL via Additional Software and check/configure wolfSSL.
6. Generate source code.
## Configuration
The settings for the wolfSTM32 project are located in `<wolfssl-root>/IDE/STM32Cube/wolfSSL.wolfSSL_conf.h`. The section for hardware platform may need to be adjusted depending on your processor and board:
* To enable STM32F2 support define `WOLFSSL_STM32F2`.
* To enable STM32F4 support define `WOLFSSL_STM32F4`.
* To enable STM32F7 support define `WOLFSSL_STM32F7`.
* To enable STM32L4 support define `WOLFSSL_STM32L4`.
* To enable STM32L5 support define `WOLFSSL_STM32L5`.
* To enable STM32WB support define `WOLFSSL_STM32WB`.
The L5 and WB55 support ECC PKA acceleration, which is enabled with `WOLFSSL_STM32_PKA`.
To disable hardware crypto acceleration you can define:
* `#define NO_STM32_HASH`
* `#define NO_STM32_CRYPTO`
To enable the latest CubeMX HAL support please use: `#define STM32_HAL_V2`
If you are using FreeRTOS make sure your `FreeRTOSConfig.h` has its `configTOTAL_HEAP_SIZE` increased.
The TLS client/server benchmark example requires about 76 KB for allocated tasks (with stack) and peak heap.
## Example Output
```
....MENU
.t. WolfCrypt Test
.b. WolfCrypt Benchmark
.l. WolfSSL TLS Bench
.e. Show Cipher List
Please select one of the above options:
```
## Support
For questions please email [support@wolfssl.com](mailto:support@wolfssl.com)

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# vim:ft=automake
# included from Top Level Makefile.am
# All paths should be given relative to the root
EXTRA_DIST+= IDE/STM32Cube/README.md
EXTRA_DIST+= IDE/STM32Cube/main.c
EXTRA_DIST+= IDE/STM32Cube/wolfssl_example.c
EXTRA_DIST+= IDE/STM32Cube/wolfSSL.wolfSSL_conf.h
EXTRA_DIST+= IDE/STM32Cube/wolfssl_example.h
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32F407.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32F437.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32F777.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32H753.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32L4A6.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32L475.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32L552.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32L562.ioc
EXTRA_DIST+= IDE/STM32Cube/Boards/STM32WB55.ioc

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/* main.c
*
* Copyright (C) 2006-2020 wolfSSL Inc.
*
* This file is part of wolfSSL.
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
/* Example for main.c with STM32Cube/wolfssl_example.c */
#if 0 /* EXAMPLE main.c */
/* Includes ------------------------------------------------------------------*/
#include "wolfssl_example.h"
/* Private variables ---------------------------------------------------------*/
CRYP_HandleTypeDef hcryp;
__ALIGN_BEGIN static const uint32_t pKeyCRYP[6] __ALIGN_END = {
0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000};
HASH_HandleTypeDef hhash;
RNG_HandleTypeDef hrng;
RTC_HandleTypeDef hrtc;
UART_HandleTypeDef huart4;
/* Definitions for defaultTask */
#ifndef SINGLE_THREADED
#ifdef CMSIS_OS2_H_
osThreadId_t defaultTaskHandle;
const osThreadAttr_t wolfCryptDemo_attributes = {
.name = "wolfCryptDemo",
.priority = (osPriority_t) osPriorityNormal,
.stack_size = WOLF_EXAMPLES_STACK
};
#else
osThreadId defaultTaskHandle;
#endif
#endif
/* Private function prototypes -----------------------------------------------*/
void SystemClock_Config(void);
static void MX_GPIO_Init(void);
static void MX_CRYP_Init(void);
static void MX_HASH_Init(void);
static void MX_RNG_Init(void);
static void MX_UART4_Init(void);
static void MX_RTC_Init(void);
/* Retargets the C library printf function to the USART. */
#include <stdio.h>
#ifdef __GNUC__
int __io_putchar(int ch)
#else
int fputc(int ch, FILE *f)
#endif
{
HAL_UART_Transmit(&huart4, (uint8_t *)&ch, 1, 0xFFFF);
return ch;
}
#ifdef __GNUC__
int _write(int file,char *ptr, int len)
{
int DataIdx;
for (DataIdx= 0; DataIdx< len; DataIdx++) {
__io_putchar(*ptr++);
}
return len;
}
#endif
int main(void)
{
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
/* Turn off buffers, so I/O occurs immediately */
setvbuf(stdin, NULL, _IONBF, 0);
setvbuf(stdout, NULL, _IONBF, 0);
setvbuf(stderr, NULL, _IONBF, 0);
/* Configure the system clock */
SystemClock_Config();
/* Initialize all configured peripherals */
MX_GPIO_Init();
MX_CRYP_Init();
MX_HASH_Init();
MX_RNG_Init();
MX_UART4_Init();
MX_RTC_Init();
MX_SPI1_Init();
MX_UART4_Init();
#ifdef SINGLE_THREADED
wolfCryptDemo(NULL);
#else
/* Init scheduler */
osKernelInitialize();
/* Create the thread(s) */
/* definition and creation of defaultTask */
#ifdef CMSIS_OS2_H_
defaultTaskHandle = osThreadNew(wolfCryptDemo, NULL, &wolfCryptDemo_attributes);
#else
osThreadDef(defaultTask, wolfCryptDemo, osPriorityNormal, 0, WOLF_EXAMPLES_STACK);
defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);
#endif
/* Start scheduler */
osKernelStart();
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
while (1) {}
#endif /* SINGLE_THREADED */
}
/** System Clock Configuration
*/
static void SystemClock_Config(void)
{
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 160;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = 7;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Error_Handler();
}
/** Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
Error_Handler();
}
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
Error_Handler();
}
}
/**
* @brief CRYP Initialization Function
* @param None
* @retval None
*/
static void MX_CRYP_Init(void)
{
hcryp.Instance = CRYP;
hcryp.Init.DataType = CRYP_DATATYPE_32B;
hcryp.Init.pKey = (uint32_t *)pKeyCRYP;
hcryp.Init.Algorithm = CRYP_TDES_ECB;
hcryp.Init.DataWidthUnit = CRYP_DATAWIDTHUNIT_WORD;
if (HAL_CRYP_Init(&hcryp) != HAL_OK) {
Error_Handler();
}
}
/**
* @brief HASH Initialization Function
* @param None
* @retval None
*/
static void MX_HASH_Init(void)
{
hhash.Init.DataType = HASH_DATATYPE_32B;
if (HAL_HASH_Init(&hhash) != HAL_OK) {
Error_Handler();
}
}
/**
* @brief RNG Initialization Function
* @param None
* @retval None
*/
static void MX_RNG_Init(void)
{
hrng.Instance = RNG;
if (HAL_RNG_Init(&hrng) != HAL_OK) {
Error_Handler();
}
}
/**
* @brief RTC Initialization Function
* @param None
* @retval None
*/
static void MX_RTC_Init(void)
{
RTC_TimeTypeDef sTime = {0};
RTC_DateTypeDef sDate = {0};
/* Initialize RTC Only */
hrtc.Instance = RTC;
hrtc.Init.HourFormat = RTC_HOURFORMAT_24;
hrtc.Init.AsynchPrediv = 127;
hrtc.Init.SynchPrediv = 255;
hrtc.Init.OutPut = RTC_OUTPUT_DISABLE;
hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
if (HAL_RTC_Init(&hrtc) != HAL_OK) {
Error_Handler();
}
/* Initialize RTC and set the Time and Date */
sTime.Hours = 0x0;
sTime.Minutes = 0x0;
sTime.Seconds = 0x0;
sTime.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
sTime.StoreOperation = RTC_STOREOPERATION_RESET;
if (HAL_RTC_SetTime(&hrtc, &sTime, RTC_FORMAT_BCD) != HAL_OK) {
Error_Handler();
}
sDate.WeekDay = RTC_WEEKDAY_MONDAY;
sDate.Month = RTC_MONTH_JANUARY;
sDate.Date = 0x1;
sDate.Year = 0x0;
if (HAL_RTC_SetDate(&hrtc, &sDate, RTC_FORMAT_BCD) != HAL_OK) {
Error_Handler();
}
}
/**
* @brief UART4 Initialization Function
* @param None
* @retval None
*/
static void MX_UART4_Init(void)
{
huart4.Instance = UART4;
huart4.Init.BaudRate = 115200;
huart4.Init.WordLength = UART_WORDLENGTH_8B;
huart4.Init.StopBits = UART_STOPBITS_1;
huart4.Init.Parity = UART_PARITY_NONE;
huart4.Init.Mode = UART_MODE_TX_RX;
huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart4.Init.OverSampling = UART_OVERSAMPLING_16;
if (HAL_UART_Init(&huart4) != HAL_OK) {
Error_Handler();
}
}
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
}
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM1 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
if (htim->Instance == TIM1) {
HAL_IncTick();
}
}
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
/* User can add his own implementation to report the HAL error return state */
while(1)
{
}
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(uint8_t *file, uint32_t line)
{
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
}
#endif /* USE_FULL_ASSERT */
#if 0
/* Working _sbrk example for .ld based libC malloc/free */
/* Replace this with one in Core/Src/sysmem.c */
/* Symbols defined in the linker script */
extern uint8_t _end;
extern uint8_t _estack;
extern uint32_t _Min_Stack_Size;
void* _sbrk(ptrdiff_t incr)
{
static uint8_t* __sbrk_heap_end = NULL;
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
const uint8_t* max_heap = (uint8_t *)stack_limit;
uint8_t* prev_heap_end;
/* Initialize heap end at first call */
if (__sbrk_heap_end == NULL) {
__sbrk_heap_end = &_end;
}
/* Protect heap from growing into the reserved MSP stack */
if (__sbrk_heap_end + incr > max_heap) {
errno = ENOMEM;
return (void *)-1;
}
prev_heap_end = __sbrk_heap_end;
__sbrk_heap_end += incr;
return (void*)prev_heap_end;
}
#endif
#endif /* EXAMPLE main.c */

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/* wolfSSL.wolfSSL_conf.h
*
* Copyright (C) 2006-2020 wolfSSL Inc.
*
* This file is part of wolfSSL.
*
* wolfSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* wolfSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
/* STM32 Cube Configuration File
* Included automatically when USE_HAL_DRIVER is defined
* (and not WOLFSSL_USER_SETTINGS or HAVE_CONF_H).
*/
#ifndef __WOLFSSL_WOLFSSL_CONF_H__
#define __WOLFSSL_WOLFSSL_CONF_H__
#ifdef __cplusplus
extern "C" {
#endif
/*---------- Debug Support -----------*/
#define WOLF_CONF_DEBUG 0
/*---------- wolfCrypt Only -----------*/
#define WOLF_CONF_WOLFCRYPT_ONLY 0
/*---------- TLS v1.3 -----------*/
#define WOLF_CONF_TLS13 1
/*---------- TLS v1.2 -----------*/
#define WOLF_CONF_TLS12 1
/*---------- DTLS Support -----------*/
#define WOLF_CONF_DTLS 0
/*---------- Math Configuration -----------*/
#define WOLF_CONF_MATH 4
/*---------- RTOS -----------*/
#define WOLF_CONF_RTOS 2
/*---------- RSA Support -----------*/
#define WOLF_CONF_RSA 1
/*---------- ECC Support -----------*/
#define WOLF_CONF_ECC 1
/*---------- DH (Diffie–Hellman) Support -----------*/
#define WOLF_CONF_DH 1
/*---------- AES GCM Support -----------*/
#define WOLF_CONF_AESGCM 1
/*---------- AES CBC Support -----------*/
#define WOLF_CONF_AESCBC 0
/*---------- ChaCha20 / Poly1305 Support -----------*/
#define WOLF_CONF_CHAPOLY 1
/*---------- Ed25519 / Curve25519 Support -----------*/
#define WOLF_CONF_EDCURVE25519 0
/*---------- MD5 Support -----------*/
#define WOLF_CONF_MD5 0
/*---------- SHA1 Support -----------*/
#define WOLF_CONF_SHA1 0
/*---------- SHA2-224 Support -----------*/
#define WOLF_CONF_SHA2_224 0
/*---------- SHA2-256 Support -----------*/
#define WOLF_CONF_SHA2_256 1
/*---------- SHA2-384 Support -----------*/
#define WOLF_CONF_SHA2_384 0
/*---------- SHA2-512 Support -----------*/
#define WOLF_CONF_SHA2_512 0
/*---------- SHA3 Support -----------*/
#define WOLF_CONF_SHA3 0
/*---------- Pre-Shared-Key Support -----------*/
#define WOLF_CONF_PSK 0
/*---------- Pwd Based Key Derivation Support -----------*/
#define WOLF_CONF_PWDBASED 0
/*---------- Keep Peer Cert Support -----------*/
#define WOLF_CONF_KEEP_PEER_CERT 0
/*---------- Base64 Encode Support -----------*/
#define WOLF_CONF_BASE64_ENCODE 0
/*---------- OpenSSL Extra Support -----------*/
#define WOLF_CONF_OPENSSL_EXTRA 0
/*---------- wolfCrypt test/benchmark -----------*/
#define WOLF_CONF_TEST 1
/* ------------------------------------------------------------------------- */
/* Hardware platform */
/* ------------------------------------------------------------------------- */
#define NO_STM32_HASH
#define NO_STM32_CRYPTO
#if defined(STM32WB55xx)
#define WOLFSSL_STM32WB
#define WOLFSSL_STM32_PKA
#undef NO_STM32_CRYPTO
#define HAL_CONSOLE_UART huart1
#elif defined(STM32F407xx)
#define WOLFSSL_STM32F4
#define HAL_CONSOLE_UART huart2
#elif defined(STM32F437xx)
#define WOLFSSL_STM32F4
#undef NO_STM32_HASH
#undef NO_STM32_CRYPTO
#define STM32_HAL_V2
#define HAL_CONSOLE_UART huart4
#elif defined(STM32F777xx)
#define WOLFSSL_STM32F7
#undef NO_STM32_HASH
#undef NO_STM32_CRYPTO
#define STM32_HAL_V2
#define HAL_CONSOLE_UART huart2
#elif defined(STM32H753xx)
#define WOLFSSL_STM32H7
#undef NO_STM32_HASH
#undef NO_STM32_CRYPTO
#define HAL_CONSOLE_UART huart3
#elif defined(STM32L4A6xx)
#define WOLFSSL_STM32L4
#undef NO_STM32_HASH
#undef NO_STM32_CRYPTO
#define HAL_CONSOLE_UART hlpuart1
#elif defined(STM32L475xx)
#define WOLFSSL_STM32L4
#define HAL_CONSOLE_UART huart1
#elif defined(STM32L562xx)
#define WOLFSSL_STM32L5
#define WOLFSSL_STM32_PKA
#define HAL_CONSOLE_UART huart1
#elif defined(STM32L552xx)
#define WOLFSSL_STM32L5
#undef NO_STM32_HASH
#define HAL_CONSOLE_UART hlpuart1
#else
#warning Please define a hardware platform!
#define WOLFSSL_STM32F4 /* default */
#define HAL_CONSOLE_UART huart4
#endif
/* ------------------------------------------------------------------------- */
/* Platform */
/* ------------------------------------------------------------------------- */
#define SIZEOF_LONG_LONG 8
#define WOLFSSL_GENERAL_ALIGNMENT 4
#define WOLFSSL_STM32_CUBEMX
#define WOLFSSL_SMALL_STACK
#define WOLFSSL_USER_IO
#define WOLFSSL_NO_SOCK
#define WOLFSSL_IGNORE_FILE_WARN
/* ------------------------------------------------------------------------- */
/* Operating System */
/* ------------------------------------------------------------------------- */
#if defined(WOLF_CONF_RTOS) && WOLF_CONF_RTOS == 2
#define FREERTOS
#else
#define SINGLE_THREADED
#endif
/* ------------------------------------------------------------------------- */
/* Math Configuration */
/* ------------------------------------------------------------------------- */
/* 1=Fast, 2=Normal, 3=SP C, 4=SP Cortex-M */
#if defined(WOLF_CONF_MATH) && WOLF_CONF_MATH != 2
/* fast (stack) math */
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
/* Optimizations (TFM_ARM, TFM_ASM or none) */
//#define TFM_NO_ASM
//#define TFM_ASM
#endif
#if defined(WOLF_CONF_MATH) && (WOLF_CONF_MATH == 3 || WOLF_CONF_MATH == 4)
/* single precision only */
#define WOLFSSL_SP
#define WOLFSSL_SP_SMALL /* use smaller version of code */
#define WOLFSSL_HAVE_SP_RSA
#define WOLFSSL_HAVE_SP_DH
#define WOLFSSL_HAVE_SP_ECC
#define WOLFSSL_SP_MATH
#define SP_WORD_SIZE 32
//#define WOLFSSL_SP_NO_MALLOC
//#define WOLFSSL_SP_CACHE_RESISTANT
/* single precision Cortex-M only */
#if WOLF_CONF_MATH == 4
#define WOLFSSL_SP_ASM /* required if using the ASM versions */
#define WOLFSSL_SP_ARM_CORTEX_M_ASM
#endif
#endif
/* ------------------------------------------------------------------------- */
/* Enable Features */
/* ------------------------------------------------------------------------- */
/* Required for TLS */
#define HAVE_TLS_EXTENSIONS
#define HAVE_SUPPORTED_CURVES
#define HAVE_ENCRYPT_THEN_MAC
#define HAVE_EXTENDED_MASTER
#if defined(WOLF_CONF_TLS13) && WOLF_CONF_TLS13 == 1
#define WOLFSSL_TLS13
#define HAVE_HKDF
#endif
#if defined(WOLF_CONF_DTLS) && WOLF_CONF_DTLS == 1
#define WOLFSSL_DTLS
#endif
#if defined(WOLF_CONF_PSK) && WOLF_CONF_PSK == 0
#define NO_PSK
#endif
#if defined(WOLF_CONF_PWDBASED) && WOLF_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
#if defined(WOLF_CONF_KEEPPEERCERT) && WOLF_CONF_KEEPPEERCERT == 1
#define KEEP_PEER_CERT
#endif
#if defined(WOLF_CONF_BASE64_ENCODE) && WOLF_CONF_BASE64_ENCODE == 1
#define WOLFSSL_BASE64_ENCODE
#endif
#if defined(WOLF_CONF_OPENSSL_EXTRA) && WOLF_CONF_OPENSSL_EXTRA == 1
#define OPENSSL_EXTRA
#endif
/* TLS Session Cache */
#if 0
#define SMALL_SESSION_CACHE
#else
#define NO_SESSION_CACHE
#endif
/* ------------------------------------------------------------------------- */
/* Crypto */
/* ------------------------------------------------------------------------- */
/* RSA */
#undef NO_RSA
#if defined(WOLF_CONF_RSA) && WOLF_CONF_RSA == 1
#ifdef USE_FAST_MATH
/* Maximum math bits (Max RSA key bits * 2) */
#undef FP_MAX_BITS
#define FP_MAX_BITS 4096
#endif
/* half as much memory but twice as slow */
#undef RSA_LOW_MEM
//#define RSA_LOW_MEM
/* Enables blinding mode, to prevent timing attacks */
#undef WC_RSA_BLINDING
#define WC_RSA_BLINDING
/* RSA PSS Support (required for TLS v1.3) */
#ifdef WOLFSSL_TLS13
#define WC_RSA_PSS
#endif
#else
#define NO_RSA
#endif
/* ECC */
#undef HAVE_ECC
#if defined(WOLF_CONF_ECC) && WOLF_CONF_ECC == 1
#define HAVE_ECC
/* Manually define enabled curves */
#define ECC_USER_CURVES
//#define HAVE_ECC192
//#define HAVE_ECC224
#undef NO_ECC256
//#define HAVE_ECC384
//#define HAVE_ECC521
/* Fixed point cache (speeds repeated operations against same private key) */
#undef FP_ECC
//#define FP_ECC
#ifdef FP_ECC
/* Bits / Entries */
#undef FP_ENTRIES
#define FP_ENTRIES 2
#undef FP_LUT
#define FP_LUT 4
#endif
/* Optional ECC calculation method */
/* Note: doubles heap usage, but slightly faster */
#undef ECC_SHAMIR
#define ECC_SHAMIR
/* Reduces heap usage, but slower */
#define ECC_TIMING_RESISTANT
/* Compressed ECC key support */
//#define HAVE_COMP_KEY
#ifdef USE_FAST_MATH
#ifdef NO_RSA
/* Custom fastmath size if not using RSA */
/* MAX = ROUND32(ECC BITS 256) + SIZE_OF_MP_DIGIT(32) */
#define FP_MAX_BITS (256 + 32)
#else
#define ALT_ECC_SIZE
#endif
/* Enable TFM optimizations for ECC */
//#define TFM_ECC192
//#define TFM_ECC224
#define TFM_ECC256
//#define TFM_ECC384
//#define TFM_ECC521
#endif
#endif
/* DH */
#undef NO_DH
#if defined(WOLF_CONF_DH) && WOLF_CONF_DH == 1
#define HAVE_DH /* freeRTOS settings.h requires this */
#define HAVE_FFDHE_2048
#define HAVE_DH_DEFAULT_PARAMS
#else
#define NO_DH
#endif
/* AES */
#if defined(WOLF_CONF_AESGCM) && WOLF_CONF_AESGCM == 1
#define HAVE_AESGCM
/* GCM Method: GCM_SMALL, GCM_WORD32 or GCM_TABLE */
/* GCM_TABLE is about 4K larger and 3x faster */
#define GCM_SMALL
#define HAVE_AES_DECRYPT
#endif
#if defined(WOLF_CONF_AESCBC) && WOLF_CONF_AESCBC == 1
#define HAVE_AES_CBC
#define HAVE_AES_DECRYPT
#endif
/* Other possible AES modes */
//#define WOLFSSL_AES_COUNTER
//#define HAVE_AESCCM
//#define WOLFSSL_AES_XTS
//#define WOLFSSL_AES_DIRECT
//#define HAVE_AES_ECB
/* ChaCha20 / Poly1305 */
#undef HAVE_CHACHA
#undef HAVE_POLY1305
#if defined(WOLF_CONF_CHAPOLY) && WOLF_CONF_CHAPOLY == 1
#define HAVE_CHACHA
#define HAVE_POLY1305
/* Needed for Poly1305 */
#undef HAVE_ONE_TIME_AUTH
#define HAVE_ONE_TIME_AUTH
#endif
/* Ed25519 / Curve25519 */
#undef HAVE_CURVE25519
#undef HAVE_ED25519
#if defined(WOLF_CONF_EDCURVE25519) && WOLF_CONF_EDCURVE25519 == 1
#define HAVE_CURVE25519
#define HAVE_ED25519
/* Optionally use small math (less flash usage, but much slower) */
#define CURVED25519_SMALL
#endif
/* ------------------------------------------------------------------------- */
/* Hashing */
/* ------------------------------------------------------------------------- */
/* Sha1 */
#undef NO_SHA
#if defined(WOLF_CONF_SHA1) && WOLF_CONF_SHA1 == 1
/* 1k smaller, but 25% slower */
//#define USE_SLOW_SHA
#else
#define NO_SHA
#endif
/* Sha2-256 */
#undef NO_SHA256
#if defined(WOLF_CONF_SHA2_256) && WOLF_CONF_SHA2_256 == 1
/* not unrolled - ~2k smaller and ~25% slower */
//#define USE_SLOW_SHA256
//#define WOLFSSL_SHAKE256
/* Sha2-224 */
#if defined(WOLF_CONF_SHA2_224) && WOLF_CONF_SHA2_224 == 1
#define WOLFSSL_SHA224
#endif
#else
#define NO_SHA256
#endif
/* Sha2-512 */
#undef WOLFSSL_SHA512
#if defined(WOLF_CONF_SHA2_512) && WOLF_CONF_SHA2_512 == 1
/* over twice as small, but 50% slower */
//#define USE_SLOW_SHA512
#define WOLFSSL_SHA512
#define HAVE_SHA512 /* freeRTOS settings.h requires this */
#endif
/* Sha2-384 */
#undef WOLFSSL_SHA384
#if defined(WOLF_CONF_SHA2_384) && WOLF_CONF_SHA2_384 == 1
#define WOLFSSL_SHA384
#endif
/* Sha3 */
#undef WOLFSSL_SHA3
#if defined(WOLF_CONF_SHA3) && WOLF_CONF_SHA3 == 1
#define WOLFSSL_SHA3
#endif
/* MD5 */
#if defined(WOLF_CONF_MD5) && WOLF_CONF_MD5 == 1
/* enabled */
#else
#define NO_MD5
#endif
/* ------------------------------------------------------------------------- */
/* Benchmark / Test */
/* ------------------------------------------------------------------------- */
/* Use reduced benchmark / test sizes */
#define BENCH_EMBEDDED
#define USE_CERT_BUFFERS_2048
#define USE_CERT_BUFFERS_256
/* ------------------------------------------------------------------------- */
/* Debugging */
/* ------------------------------------------------------------------------- */
#if defined(WOLF_CONF_DEBUG) && WOLF_CONF_DEBUG == 1
#define DEBUG_WOLFSSL
/* Use this to measure / print heap usage */
#if 0
#define USE_WOLFSSL_MEMORY
#define WOLFSSL_TRACK_MEMORY
#define WOLFSSL_DEBUG_MEMORY
#define WOLFSSL_DEBUG_MEMORY_PRINT
#endif
#else
//#define NO_WOLFSSL_MEMORY
//#define NO_ERROR_STRINGS
#endif
/* ------------------------------------------------------------------------- */
/* Port */
/* ------------------------------------------------------------------------- */
/* Override Current Time */
/* Allows custom "custom_time()" function to be used for benchmark */
#define WOLFSSL_USER_CURRTIME
/* ------------------------------------------------------------------------- */
/* RNG */
/* ------------------------------------------------------------------------- */
#define NO_OLD_RNGNAME /* conflicts with STM RNG macro */
#define HAVE_HASHDRBG
/* ------------------------------------------------------------------------- */
/* Disable Features */
/* ------------------------------------------------------------------------- */
#if defined(WOLF_CONF_TLS12) && WOLF_CONF_TLS12 == 0
#define WOLFSSL_NO_TLS12
#endif
#if defined(WOLF_CONF_WOLFCRYPT_ONLY) && WOLF_CONF_WOLFCRYPT_ONLY == 1
#define WOLFCRYPT_ONLY
#endif
//#define NO_WOLFSSL_SERVER
//#define NO_WOLFSSL_CLIENT
#if defined(WOLF_CONF_TEST) && WOLF_CONF_TEST == 0
#define NO_CRYPT_TEST
#define NO_CRYPT_BENCHMARK
#endif
#define NO_FILESYSTEM
#define NO_WRITEV
#define NO_MAIN_DRIVER
#define NO_DEV_RANDOM
#define NO_OLD_TLS
#define WOLFSSL_NO_CLIENT_AUTH /* disable client auth for Ed25519/Ed448 */
#define NO_DSA
#define NO_RC4
#define NO_HC128
#define NO_RABBIT
#define NO_MD4
#define NO_DES3
/* In-lining of misc.c functions */
/* If defined, must include wolfcrypt/src/misc.c in build */
/* Slower, but about 1k smaller */
//#define NO_INLINE
/* Base16 / Base64 encoding */
//#define NO_CODING
/* bypass certificate date checking, due to lack of properly configured RTC source */
#ifndef HAL_RTC_MODULE_ENABLED
#define NO_ASN_TIME
#endif
#ifdef __cplusplus
}
#endif
#endif /*__WOLFSSL_WOLFSSL_CONF_H__ */

389
IDE/OPENSTM32/Src/wolfssl_example.c → IDE/STM32Cube/wolfssl_example.c
View File

@ -30,12 +30,17 @@
#include <wolfssl/wolfcrypt/hash.h> /* WC_MAX_DIGEST_SIZE */
#define WOLFSSL_DEBUG_MEMORY
#ifdef WOLFSSL_DEBUG_MEMORY
/* for memory debugging */
#include <task.h>
#ifndef SINGLE_THREADED
#include <cmsis_os.h>
#ifdef WOLFSSL_DEBUG_MEMORY
/* for memory debugging */
#include <task.h>
#endif
#endif
#include <stdio.h>
#include <string.h>
/*****************************************************************************
* Configuration
@ -47,9 +52,18 @@
#define BENCH_RUNTIME_SEC 20
#define BENCH_SHOW_PEER_INFO 1
#define TEST_PACKET_SIZE (2 * 1024) /* TLS packet size */
#ifdef BENCH_EMBEDDED
#define TEST_MAX_SIZE (4 * 1024)
#else
#define TEST_MAX_SIZE (32 * 1024) /* Total bytes to benchmark */
#endif
/* Must be large enough to handle max packet size - TLS header MAX_MSG_EXTRA + MAX DIGEST */
#define MEM_BUFFER_SZ (TEST_PACKET_SIZE + 38 + WC_MAX_DIGEST_SIZE)
/* make sure memory buffer size is large enough */
#if MEM_BUFFER_SZ < 2048
#undef MEM_BUFFER_SZ
#define MEM_BUFFER_SZ 2048
#endif
#define SHOW_VERBOSE 0 /* Default output is tab delimited format */
#ifndef WOLFSSL_CIPHER_LIST_MAX_SIZE
#define WOLFSSL_CIPHER_LIST_MAX_SIZE 2048
@ -58,15 +72,41 @@
/* define this to test only a specific cipher suite(s) (colon separated) */
#define TEST_CIPHER_SUITE "ECDHE-RSA-AES256-GCM-SHA384:ECDHE-RSA-AES128-GCM-SHA256"
#endif
#if 0
/* use non-blocking mode for read/write IO */
#define BENCH_USE_NONBLOCK
#endif
/*****************************************************************************
* Private types/enumerations/variables
****************************************************************************/
#ifdef WOLFSSL_STATIC_MEMORY
#if 1 /* on-chip RAM */
#define RAM_STATIC
#else /* external RAM */
/* requires .ld to be updated with ".extram" section */
#define RAM_STATIC __attribute__ ((section (".extram")))
#endif
#define WOLF_GEN_MEM (20*1024)
#define WOLF_TLS_GEN_MEM (90*1024)
#define WOLF_TLS_IO_POOL_MEM (35*1024)
RAM_STATIC static byte gWolfMem[WOLF_GEN_MEM];
RAM_STATIC static byte gWolfCTXCli[WOLF_TLS_GEN_MEM];
RAM_STATIC static byte gWolfIOCli[WOLF_TLS_IO_POOL_MEM];
RAM_STATIC static byte gWolfCTXSrv[WOLF_TLS_GEN_MEM];
RAM_STATIC static byte gWolfIOSrv[WOLF_TLS_IO_POOL_MEM];
WOLFSSL_HEAP_HINT* HEAP_HINT = NULL;
#endif /* WOLFSSL_STATIC_MEMORY */
/* UART definitions */
extern UART_HandleTypeDef huart4;
extern SPI_HandleTypeDef hspi1;
#ifndef HAL_CONSOLE_UART
#define HAL_CONSOLE_UART huart4
#endif
extern UART_HandleTypeDef HAL_CONSOLE_UART;
/*****************************************************************************
* Public types/enumerations/variables
@ -77,16 +117,20 @@ typedef struct func_args {
int return_code;
} func_args;
const char menu1[] = "\r\n"
"\tt. WolfCrypt Test\r\n"
"\tb. WolfCrypt Benchmark\r\n"
"\tl. WolfSSL TLS Bench\r\n"
"\te. Show Cipher List\r\n";
const char menu1[] = "\n"
"\tt. WolfCrypt Test\n"
"\tb. WolfCrypt Benchmark\n"
"\tl. WolfSSL TLS Bench\n"
"\te. Show Cipher List\n";
static void PrintMemStats(void);
double current_time(void);
static const char* kShutdown = "shutdown";
#if (!defined(NO_WOLFSSL_CLIENT) || !defined(NO_WOLFSSL_SERVER)) && \
!defined(WOLFCRYPT_ONLY)
!defined(WOLFCRYPT_ONLY) && !defined(SINGLE_THREADED)
static const char* kShutdown = "shutdown";
static const char* kTestStr =
"Biodiesel cupidatat marfa, cliche aute put a bird on it incididunt elit\n"
@ -220,10 +264,14 @@ typedef struct {
typedef struct {
int ret;
osThreadDef_t threadDef;
osThreadId threadId;
#ifdef CMSIS_OS2_H_
osSemaphoreId_t mutex;
#else
osThreadDef_t threadDef;
osSemaphoreDef_t mutexDef;
osSemaphoreId mutex;
#endif
byte shutdown:1;
byte done:1;
@ -257,30 +305,14 @@ typedef struct {
} info_t;
extern RTC_HandleTypeDef hrtc;
double current_time(void)
{
RTC_TimeTypeDef time;
RTC_DateTypeDef date;
uint32_t subsec;
/* must get time and date here due to STM32 HW bug */
HAL_RTC_GetTime(&hrtc, &time, FORMAT_BIN);
HAL_RTC_GetDate(&hrtc, &date, FORMAT_BIN);
subsec = (255 - time.SubSeconds) * 1000 / 255;
(void) date;
/* return seconds.milliseconds */
return ((double) time.Hours * 24) + ((double) time.Minutes * 60)
+ (double) time.Seconds + ((double) subsec / 1000);
}
/*****************************************************************************
* Private functions
****************************************************************************/
static double gettime_secs(int reset)
{
return current_time();
}
static void PrintTlsStats(stats_t* wcStat, const char* desc, const char* cipher, int verbose)
{
const char* formatStr;
@ -313,30 +345,6 @@ static void PrintTlsStats(stats_t* wcStat, const char* desc, const char* cipher,
wcStat->connTime * 1000 / wcStat->connCount);
}
static void ShowCiphers(void)
{
int ret;
char* ciphers = (char*)XMALLOC(WOLFSSL_CIPHER_LIST_MAX_SIZE, NULL,
DYNAMIC_TYPE_TMP_BUFFER);
if (ciphers) {
ret = wolfSSL_get_ciphers(ciphers, WOLFSSL_CIPHER_LIST_MAX_SIZE);
if (ret == WOLFSSL_SUCCESS)
printf("%s\n", ciphers);
XFREE(ciphers, NULL, DYNAMIC_TYPE_TMP_BUFFER);
}
}
static void PrintMemStats(void)
{
#ifdef WOLFSSL_DEBUG_MEMORY
printf("\nHeap MinEver %d, Free %d, Stack %lu\n",
xPortGetMinimumEverFreeHeapSize(),
xPortGetFreeHeapSize(),
uxTaskGetStackHighWaterMark(NULL));
#endif
}
#if defined(KEEP_PEER_CERT) || defined(KEEP_OUR_CERT)
static const char* client_showx509_msg[] = {
@ -481,7 +489,11 @@ static void ShowPeer(WOLFSSL* ssl)
/* server send callback */
static int ServerMemSend(info_t* info, char* buf, int sz)
{
#ifdef CMSIS_OS2_H_
osSemaphoreAcquire(info->client.mutex, osWaitForever);
#else
osSemaphoreWait(info->client.mutex, osWaitForever);
#endif
#ifndef BENCH_USE_NONBLOCK
/* check for overflow */
@ -499,7 +511,11 @@ static int ServerMemSend(info_t* info, char* buf, int sz)
info->to_client.write_idx += sz;
info->to_client.write_bytes += sz;
#ifdef CMSIS_OS2_H_
osThreadFlagsSet(info->client.threadId, 1);
#else
osSignalSet(info->client.threadId, 1);
#endif
osSemaphoreRelease(info->client.mutex);
#ifdef BENCH_USE_NONBLOCK
@ -512,14 +528,23 @@ static int ServerMemSend(info_t* info, char* buf, int sz)
/* server recv callback */
static int ServerMemRecv(info_t* info, char* buf, int sz)
{
#ifdef CMSIS_OS2_H_
osSemaphoreAcquire(info->server.mutex, osWaitForever);
#else
osSemaphoreWait(info->server.mutex, osWaitForever);
#endif
#ifndef BENCH_USE_NONBLOCK
while (info->to_server.write_idx - info->to_server.read_idx < sz &&
!info->client.done) {
osSemaphoreRelease(info->server.mutex);
#ifdef CMSIS_OS2_H_
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
osSemaphoreAcquire(info->server.mutex, osWaitForever);
#else
osSignalWait(1, osWaitForever);
osSemaphoreWait(info->server.mutex, osWaitForever);
#endif
}
#else
if (info->to_server.write_idx - info->to_server.read_idx < sz)
@ -548,7 +573,11 @@ static int ServerMemRecv(info_t* info, char* buf, int sz)
/* client send callback */
static int ClientMemSend(info_t* info, char* buf, int sz)
{
#ifdef CMSIS_OS2_H_
osSemaphoreAcquire(info->server.mutex, osWaitForever);
#else
osSemaphoreWait(info->server.mutex, osWaitForever);
#endif
#ifndef BENCH_USE_NONBLOCK
/* check for overflow */
@ -567,7 +596,11 @@ static int ClientMemSend(info_t* info, char* buf, int sz)
info->to_server.write_idx += sz;
info->to_server.write_bytes += sz;
#ifdef CMSIS_OS2_H_
osThreadFlagsSet(info->server.threadId, 1);
#else
osSignalSet(info->server.threadId, 1);
#endif
osSemaphoreRelease(info->server.mutex);
#ifdef BENCH_USE_NONBLOCK
@ -580,14 +613,23 @@ static int ClientMemSend(info_t* info, char* buf, int sz)
/* client recv callback */
static int ClientMemRecv(info_t* info, char* buf, int sz)
{
#ifdef CMSIS_OS2_H_
osSemaphoreAcquire(info->client.mutex, osWaitForever);
#else
osSemaphoreWait(info->client.mutex, osWaitForever);
#endif
#ifndef BENCH_USE_NONBLOCK
while (info->to_client.write_idx - info->to_client.read_idx < sz &&
!info->server.done) {
osSemaphoreRelease(info->client.mutex);
#ifdef CMSIS_OS2_H_
osThreadFlagsWait(1, osFlagsWaitAny, osWaitForever);
osSemaphoreAcquire(info->client.mutex, osWaitForever);
#else
osSignalWait(1, osWaitForever);
osSemaphoreWait(info->client.mutex, osWaitForever);
#endif
}
#else
if (info->to_client.write_idx - info->to_client.read_idx < sz)
@ -645,7 +687,7 @@ static int bench_tls_client(info_t* info)
{
byte *writeBuf = NULL, *readBuf = NULL;
double start, total = 0;
int ret, readBufSz;
int ret = 0, readBufSz;
WOLFSSL_CTX* cli_ctx = NULL;
WOLFSSL* cli_ssl = NULL;
int haveShownPeerInfo = 0;
@ -656,21 +698,43 @@ static int bench_tls_client(info_t* info)
/* set up client */
#ifdef WOLFSSL_TLS13
if (tls13)
if (tls13) {
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&cli_ctx, wolfTLSv1_3_client_method_ex,
gWolfCTXCli, sizeof(gWolfCTXCli), WOLFMEM_GENERAL , 10);
#else
cli_ctx = wolfSSL_CTX_new(wolfTLSv1_3_client_method());
#endif
}
#endif
if (!tls13)
if (!tls13) {
#if !defined(WOLFSSL_TLS13)
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&cli_ctx, wolfSSLv23_client_method_ex,
gWolfCTXCli, sizeof(gWolfCTXCli), WOLFMEM_GENERAL , 10);
#else
cli_ctx = wolfSSL_CTX_new(wolfSSLv23_client_method());
#endif
#elif !defined(WOLFSSL_NO_TLS12)
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&cli_ctx, wolfTLSv1_2_client_method_ex,
gWolfCTXCli, sizeof(gWolfCTXCli), WOLFMEM_GENERAL , 10);
#else
cli_ctx = wolfSSL_CTX_new(wolfTLSv1_2_client_method());
#endif
#endif
}
if (cli_ctx == NULL) {
printf("error creating ctx\n");
if (cli_ctx == NULL || ret != 0) {
printf("error creating ctx: ret %d\n", ret);
ret = MEMORY_E; goto exit;
}
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&cli_ctx, 0, gWolfIOCli, sizeof(gWolfIOCli),
WOLFMEM_IO_POOL, 10 );
#endif
#ifndef NO_CERTS
#ifdef HAVE_ECC
if (XSTRSTR(info->cipher, "ECDSA")) {
@ -733,7 +797,7 @@ static int bench_tls_client(info_t* info)
cli_ssl = wolfSSL_new(cli_ctx);
if (cli_ssl == NULL) {
printf("error creating client object\n");
goto exit;
ret = MEMORY_E; goto exit;
}
wolfSSL_SetIOReadCtx(cli_ssl, info);
@ -846,6 +910,7 @@ static int bench_tls_client(info_t* info)
exit:
if (ret != 0 && ret != WOLFSSL_SUCCESS) {
info->doShutdown = 1;
printf("Client Error: %d (%s)\n", ret,
wolfSSL_ERR_reason_error_string(ret));
}
@ -862,7 +927,11 @@ exit:
return ret;
}
#ifdef CMSIS_OS2_H_
static void client_thread(void* args)
#else
static void client_thread(const void* args)
#endif
{
int ret;
info_t* info = (info_t*)args;
@ -871,8 +940,13 @@ static void client_thread(const void* args)
ret = bench_tls_client(info);
/* signal server */
if (!info->server.done && info->server.threadId != 0)
if (!info->server.done && info->server.threadId != 0) {
#ifdef CMSIS_OS2_H_
osThreadFlagsSet(info->server.threadId, 1);
#else
osSignalSet(info->server.threadId, 1);
#endif
}
info->client.ret = ret;
info->client.done = 1;
osThreadSuspend(NULL);
@ -888,7 +962,7 @@ static int bench_tls_server(info_t* info)
{
byte *readBuf = NULL;
double start;
int ret, len = 0, readBufSz;
int ret = 0, len = 0, readBufSz;
WOLFSSL_CTX* srv_ctx = NULL;
WOLFSSL* srv_ssl = NULL;
int tls13 = XSTRNCMP(info->cipher, "TLS13", 5) == 0;
@ -896,16 +970,43 @@ static int bench_tls_server(info_t* info)
/* set up server */
#ifdef WOLFSSL_TLS13
if (tls13)
if (tls13) {
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&srv_ctx, wolfTLSv1_3_server_method_ex,
gWolfCTXSrv, sizeof(gWolfCTXSrv), WOLFMEM_GENERAL , 10);
#else
srv_ctx = wolfSSL_CTX_new(wolfTLSv1_3_server_method());
#endif
}
#endif
if (!tls13)
if (!tls13) {
#if !defined(WOLFSSL_TLS13)
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&srv_ctx, wolfSSLv23_server_method_ex,
gWolfCTXSrv, sizeof(gWolfCTXSrv), WOLFMEM_GENERAL , 10);
#else
srv_ctx = wolfSSL_CTX_new(wolfSSLv23_server_method());
if (srv_ctx == NULL) {
printf("error creating server ctx\n");
#endif
#elif !defined(WOLFSSL_NO_TLS12)
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&srv_ctx, wolfTLSv1_2_server_method_ex,
gWolfCTXSrv, sizeof(gWolfCTXSrv), WOLFMEM_GENERAL , 10);
#else
srv_ctx = wolfSSL_CTX_new(wolfTLSv1_2_server_method());
#endif
#endif
}
if (srv_ctx == NULL || ret != 0) {
printf("error creating server ctx: ret %d\n", ret);
ret = MEMORY_E; goto exit;
}
#ifdef WOLFSSL_STATIC_MEMORY
ret = wolfSSL_CTX_load_static_memory(&srv_ctx, 0, gWolfIOSrv, sizeof(gWolfIOSrv),
WOLFMEM_IO_POOL, 10 );
#endif
#ifndef NO_CERTS
#ifdef HAVE_ECC
if (XSTRSTR(info->cipher, "ECDSA")) {
@ -1081,6 +1182,7 @@ static int bench_tls_server(info_t* info)
exit:
if (ret != 0 && ret != WOLFSSL_SUCCESS) {
info->doShutdown = 1;
printf("Server Error: %d (%s)\n", ret,
wolfSSL_ERR_reason_error_string(ret));
}
@ -1096,7 +1198,11 @@ exit:
return ret;
}
#ifdef CMSIS_OS2_H_
static void server_thread(void* args)
#else
static void server_thread(const void* args)
#endif
{
int ret;
info_t* info = (info_t*)args;
@ -1105,8 +1211,13 @@ static void server_thread(const void* args)
ret = bench_tls_server(info);
/* signal client */
if (!info->client.done && info->client.threadId != 0)
if (!info->client.done && info->client.threadId != 0) {
#ifdef CMSIS_OS2_H_
osThreadFlagsSet(info->client.threadId, 1);
#else
osSignalSet(info->client.threadId, 1);
#endif
}
info->server.ret = ret;
info->server.done = 1;
osThreadSuspend(NULL);
@ -1118,6 +1229,19 @@ static void server_thread(const void* args)
osThreadTerminate(info->server.threadId);
}
#ifdef CMSIS_OS2_H_
static const osThreadAttr_t server_thread_attributes = {
.name = "server_thread",
.priority = (osPriority_t) osPriorityNormal,
.stack_size = WOLF_EXAMPLES_STACK
};
static const osThreadAttr_t client_thread_attributes = {
.name = "client_thread",
.priority = (osPriority_t) osPriorityNormal,
.stack_size = WOLF_EXAMPLES_STACK
};
#endif
int bench_tls(void* args)
{
int ret = 0;
@ -1170,6 +1294,10 @@ int bench_tls(void* args)
info->showPeerInfo = argShowPeerInfo;
info->showVerbose = argShowVerbose;
#ifdef CMSIS_OS2_H_
info->server.mutex = osSemaphoreNew(1, 0, NULL);
info->client.mutex = osSemaphoreNew(1, 0, NULL);
#else
info->server.mutex = osSemaphoreCreate(&info->server.mutexDef, 1);
info->client.mutex = osSemaphoreCreate(&info->client.mutexDef, 1);
@ -1183,6 +1311,7 @@ int bench_tls(void* args)
info->client.threadDef.pthread = client_thread;
info->client.threadDef.tpriority = osPriorityNormal;
info->client.threadDef.stacksize = WOLF_EXAMPLES_STACK;
#endif
/* parse by : */
while ((cipher != NULL) && (cipher[0] != '\0')) {
@ -1213,13 +1342,21 @@ int bench_tls(void* args)
/* start threads */
if (info->server.threadId == 0) {
#ifdef CMSIS_OS2_H_
info->server.threadId = osThreadNew(server_thread, info, &server_thread_attributes);
#else
info->server.threadId = osThreadCreate(&info->server.threadDef, info);
#endif
}
else {
osThreadResume(info->server.threadId);
}
if (info->client.threadId == 0) {
#ifdef CMSIS_OS2_H_
info->client.threadId = osThreadNew(client_thread, info, &client_thread_attributes);
#else
info->client.threadId = osThreadCreate(&info->client.threadDef, info);
#endif
}
else {
osThreadResume(info->client.threadId);
@ -1277,19 +1414,84 @@ exit:
return ret;
}
#endif /* (!NO_WOLFSSL_CLIENT || !NO_WOLFSSL_SERVER) && !WOLFCRYPT_ONLY */
#endif /* (!NO_WOLFSSL_CLIENT || !NO_WOLFSSL_SERVER) && !WOLFCRYPT_ONLY && !SINGLE_THREADED */
/*****************************************************************************
* Private functions
****************************************************************************/
#ifndef WOLFCRYPT_ONLY
static void ShowCiphers(void)
{
int ret;
char* ciphers = (char*)XMALLOC(WOLFSSL_CIPHER_LIST_MAX_SIZE, NULL,
DYNAMIC_TYPE_TMP_BUFFER);
if (ciphers) {
ret = wolfSSL_get_ciphers(ciphers, WOLFSSL_CIPHER_LIST_MAX_SIZE);
if (ret == WOLFSSL_SUCCESS)
printf("%s\n", ciphers);
XFREE(ciphers, NULL, DYNAMIC_TYPE_TMP_BUFFER);
}
}
#endif
static void PrintMemStats(void)
{
#ifdef WOLFSSL_DEBUG_MEMORY
printf("\nHeap MinEver %d, Free %d, Stack %lu\n",
xPortGetMinimumEverFreeHeapSize(),
xPortGetFreeHeapSize(),
uxTaskGetStackHighWaterMark(NULL));
#endif
}
#if 0
static void* wolfMallocCb(size_t size)
{
void* ptr = malloc(size);
if (ptr == NULL) {
printf("BREAK!\n");
}
return ptr;
}
static void wolfFreeCb(void *ptr)
{
free(ptr);
}
static void* wolfReallocCb(void *ptr, size_t size)
{
return realloc(ptr, size);
}
#endif
/*****************************************************************************
* Public functions
****************************************************************************/
#ifdef HAL_RTC_MODULE_ENABLED
extern RTC_HandleTypeDef hrtc;
double current_time(void)
{
RTC_TimeTypeDef time;
RTC_DateTypeDef date;
uint32_t subsec;
/* must get time and date here due to STM32 HW bug */
HAL_RTC_GetTime(&hrtc, &time, FORMAT_BIN);
HAL_RTC_GetDate(&hrtc, &date, FORMAT_BIN);
subsec = (255 - time.SubSeconds) * 1000 / 255;
(void) date;
/* return seconds.milliseconds */
return ((double) time.Hours * 24) + ((double) time.Minutes * 60)
+ (double) time.Seconds + ((double) subsec / 1000);
}
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef CMSIS_OS2_H_
void wolfCryptDemo(void* argument)
#else
void wolfCryptDemo(const void* argument)
#endif
{
HAL_StatusTypeDef halRet;
uint8_t buffer[1]; /* single char */
uint8_t buffer[2];
func_args args;
#ifdef DEBUG_WOLFSSL
@ -1297,18 +1499,31 @@ void wolfCryptDemo(const void* argument)
#endif
/* initialize wolfSSL */
#ifdef WOLFCRYPT_ONLY
wolfCrypt_Init();
#else
wolfSSL_Init();
#endif
#ifdef WOLFSSL_STATIC_MEMORY
if (wc_LoadStaticMemory(&HEAP_HINT, gWolfMem, sizeof(gWolfMem),
WOLFMEM_GENERAL, 10) != 0) {
printf("unable to load static memory");
}
#endif
//wolfSSL_SetAllocators(wolfMallocCb, wolfFreeCb, wolfReallocCb);
while (1) {
memset(&args, 0, sizeof(args));
args.return_code = NOT_COMPILED_IN; /* default */
printf("\r\n\t\t\t\tMENU\r\n");
printf("\n\t\t\t\tMENU\n");
printf(menu1);
printf("Please select one of the above options:\n");
do {
halRet = HAL_UART_Receive(&huart4, buffer, sizeof(buffer), 100);
halRet = HAL_UART_Receive(&HAL_CONSOLE_UART, buffer, sizeof(buffer), 100);
} while (halRet != HAL_OK || buffer[0] == '\n' || buffer[0] == '\r');
switch (buffer[0]) {
@ -1317,6 +1532,8 @@ void wolfCryptDemo(const void* argument)
#ifndef NO_CRYPT_TEST
args.return_code = 0;
wolfcrypt_test(&args);
#else
args.return_code = NOT_COMPILED_IN;
#endif
printf("Crypt Test: Return code %d\n", args.return_code);
break;
@ -1326,30 +1543,42 @@ void wolfCryptDemo(const void* argument)
#ifndef NO_CRYPT_BENCHMARK
args.return_code = 0;
benchmark_test(&args);
#else
args.return_code = NOT_COMPILED_IN;
#endif
printf("Benchmark Test: Return code %d\n", args.return_code);
break;
case 'l':
printf("Running TLS Benchmarks...\n");
#if (!defined(NO_WOLFSSL_CLIENT) || !defined(NO_WOLFSSL_SERVER)) && !defined(WOLFCRYPT_ONLY)
#if (!defined(NO_WOLFSSL_CLIENT) || !defined(NO_WOLFSSL_SERVER)) && !defined(WOLFCRYPT_ONLY) && !defined(SINGLE_THREADED)
bench_tls(&args);
#else
args.return_code = NOT_COMPILED_IN;
#endif
printf("TLS Benchmarks: Return code %d\n", args.return_code);
break;
case 'e':
#ifndef WOLFCRYPT_ONLY
ShowCiphers();
#else
printf("Not compiled in\n");
#endif
break;
// All other cases go here
default:
printf("\r\nSelection out of range\r\n");
printf("\nSelection out of range\n");
break;
}
PrintMemStats();
}
#ifdef WOLFCRYPT_ONLY
wolfCrypt_Cleanup();
#else
wolfSSL_Cleanup();
#endif
}

17
IDE/OPENSTM32/Inc/wolfssl_example.h → IDE/STM32Cube/wolfssl_example.h
View File

@ -22,10 +22,6 @@
#ifndef WOLFSSL_EXAMPLE_H_
#define WOLFSSL_EXAMPLE_H_
#include <stm32f4xx_hal.h>
#include <stm32f4xx.h>
#include <cmsis_os.h>
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
@ -39,11 +35,18 @@
#include <wolfcrypt/test/test.h>
#include <wolfcrypt/benchmark/benchmark.h>
#ifndef WOLF_EXAMPLES_STACK
#define WOLF_EXAMPLES_STACK (30 * configMINIMAL_STACK_SIZE)
#ifndef SINGLE_THREADED
#include <cmsis_os.h>
#endif
void wolfCryptDemo(void const * argument);
#ifndef WOLF_EXAMPLES_STACK
#define WOLF_EXAMPLES_STACK (30*1024)
#endif
#ifdef CMSIS_OS2_H_
void wolfCryptDemo(void* argument);
#else
void wolfCryptDemo(void const * argument);
#endif
#endif /* WOLFSSL_EXAMPLE_H_ */

1
IDE/VS-AZURE-SPHERE/include.am
View File

@ -16,3 +16,4 @@ EXTRA_DIST+= IDE/VS-AZURE-SPHERE/server/server.h
EXTRA_DIST+= IDE/VS-AZURE-SPHERE/server/server.vcxproj
EXTRA_DIST+= IDE/VS-AZURE-SPHERE/wolfcrypt_test/app_manifest.json
EXTRA_DIST+= IDE/VS-AZURE-SPHERE/wolfcrypt_test/wolfcrypt_test.vcxproj
EXTRA_DIST+= IDE/VS-AZURE-SPHERE/shared/util.h

2
IDE/WICED-STUDIO/user_settings.h
View File

@ -595,7 +595,7 @@ extern unsigned int my_rng_seed_gen(void);
#endif
#if 1
#define FP_MAX_BITS_ECC 512
#define FP_MAX_BITS_ECC (256 + 32)
#endif
/* ------------------------------------------------------------------------- */

2
IDE/WIN/user_settings.h Normal file → Executable file
View File

@ -33,11 +33,9 @@
/* The lib */
#define OPENSSL_EXTRA
#define WOLFSSL_RIPEMD
#define WOLFSSL_SHA512
#define NO_PSK
#define HAVE_EXTENDED_MASTER
#define WOLFSSL_SNIFFER
#define HAVE_TLS_EXTENSIONS
#define HAVE_SECURE_RENEGOTIATION
#define HAVE_AESGCM

2
IDE/WIN10/user_settings.h
View File

@ -54,11 +54,9 @@
/* The lib */
#define OPENSSL_EXTRA
#define WOLFSSL_RIPEMD
#define WOLFSSL_SHA512
#define NO_PSK
#define HAVE_EXTENDED_MASTER
#define WOLFSSL_SNIFFER
#define HAVE_TLS_EXTENSIONS
#define HAVE_SECURE_RENEGOTIATION
#define HAVE_AESGCM

76
IDE/XCODE/Benchmark/wolfBench.xcodeproj/project.pbxproj
View File

@ -8,6 +8,24 @@
/* Begin PBXBuildFile section */
52114C8721B5A7320022ADA1 /* sp_c64.c in Sources */ = {isa = PBXBuildFile; fileRef = 52114C8621B5A7320022ADA1 /* sp_c64.c */; };
A46FE16F2493E8F800A25BE7 /* armv8-chacha.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE14C2493E8F500A25BE7 /* armv8-chacha.c */; };
A46FE1702493E8F800A25BE7 /* sp_int.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE14D2493E8F600A25BE7 /* sp_int.c */; };
A46FE1732493E8F800A25BE7 /* armv8-poly1305.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1502493E8F600A25BE7 /* armv8-poly1305.c */; };
A46FE1742493E8F800A25BE7 /* sp_cortexm.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1512493E8F600A25BE7 /* sp_cortexm.c */; };
A46FE1752493E8F800A25BE7 /* blake2s.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1522493E8F600A25BE7 /* blake2s.c */; };
A46FE1772493E8F800A25BE7 /* wc_pkcs11.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1542493E8F600A25BE7 /* wc_pkcs11.c */; };
A46FE1792493E8F800A25BE7 /* sp_arm64.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1562493E8F600A25BE7 /* sp_arm64.c */; };
A46FE17A2493E8F800A25BE7 /* cryptocb.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1572493E8F600A25BE7 /* cryptocb.c */; };
A46FE1802493E8F800A25BE7 /* ed448.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE15D2493E8F700A25BE7 /* ed448.c */; };
A46FE1812493E8F800A25BE7 /* wc_dsp.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE15E2493E8F700A25BE7 /* wc_dsp.c */; };
A46FE1842493E8F800A25BE7 /* sp_x86_64.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1612493E8F700A25BE7 /* sp_x86_64.c */; };
A46FE1852493E8F800A25BE7 /* sp_armthumb.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1622493E8F700A25BE7 /* sp_armthumb.c */; };
A46FE1882493E8F800A25BE7 /* sp_arm32.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1652493E8F700A25BE7 /* sp_arm32.c */; };
A46FE1892493E8F800A25BE7 /* sp_dsp32.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1662493E8F800A25BE7 /* sp_dsp32.c */; };
A46FE18A2493E8F800A25BE7 /* ge_448.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1672493E8F800A25BE7 /* ge_448.c */; };
A46FE18B2493E8F800A25BE7 /* curve448.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE1682493E8F800A25BE7 /* curve448.c */; };
A46FE18D2493E8F800A25BE7 /* fe_448.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE16A2493E8F800A25BE7 /* fe_448.c */; };
A46FE1912493E8F800A25BE7 /* sp_c32.c in Sources */ = {isa = PBXBuildFile; fileRef = A46FE16E2493E8F800A25BE7 /* sp_c32.c */; };
A47546261FD90492005176B9 /* tls_bench.c in Sources */ = {isa = PBXBuildFile; fileRef = A47546251FD90492005176B9 /* tls_bench.c */; };
A4ADF82F1FCE0BD300A06E90 /* AppDelegate.m in Sources */ = {isa = PBXBuildFile; fileRef = A4ADF82E1FCE0BD300A06E90 /* AppDelegate.m */; };
A4ADF8321FCE0BD300A06E90 /* ViewController.m in Sources */ = {isa = PBXBuildFile; fileRef = A4ADF8311FCE0BD300A06E90 /* ViewController.m */; };
@ -85,6 +103,24 @@
/* Begin PBXFileReference section */
52114C8621B5A7320022ADA1 /* sp_c64.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_c64.c; path = ../../../wolfcrypt/src/sp_c64.c; sourceTree = "<group>"; };
A46FE14C2493E8F500A25BE7 /* armv8-chacha.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "armv8-chacha.c"; path = "../../../wolfcrypt/src/port/arm/armv8-chacha.c"; sourceTree = "<group>"; };
A46FE14D2493E8F600A25BE7 /* sp_int.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_int.c; path = ../../../wolfcrypt/src/sp_int.c; sourceTree = "<group>"; };
A46FE1502493E8F600A25BE7 /* armv8-poly1305.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = "armv8-poly1305.c"; path = "../../../wolfcrypt/src/port/arm/armv8-poly1305.c"; sourceTree = "<group>"; };
A46FE1512493E8F600A25BE7 /* sp_cortexm.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_cortexm.c; path = ../../../wolfcrypt/src/sp_cortexm.c; sourceTree = "<group>"; };
A46FE1522493E8F600A25BE7 /* blake2s.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = blake2s.c; path = ../../../wolfcrypt/src/blake2s.c; sourceTree = "<group>"; };
A46FE1542493E8F600A25BE7 /* wc_pkcs11.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = wc_pkcs11.c; path = ../../../wolfcrypt/src/wc_pkcs11.c; sourceTree = "<group>"; };
A46FE1562493E8F600A25BE7 /* sp_arm64.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_arm64.c; path = ../../../wolfcrypt/src/sp_arm64.c; sourceTree = "<group>"; };
A46FE1572493E8F600A25BE7 /* cryptocb.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = cryptocb.c; path = ../../../wolfcrypt/src/cryptocb.c; sourceTree = "<group>"; };
A46FE15D2493E8F700A25BE7 /* ed448.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = ed448.c; path = ../../../wolfcrypt/src/ed448.c; sourceTree = "<group>"; };
A46FE15E2493E8F700A25BE7 /* wc_dsp.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = wc_dsp.c; path = ../../../wolfcrypt/src/wc_dsp.c; sourceTree = "<group>"; };
A46FE1612493E8F700A25BE7 /* sp_x86_64.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_x86_64.c; path = ../../../wolfcrypt/src/sp_x86_64.c; sourceTree = "<group>"; };
A46FE1622493E8F700A25BE7 /* sp_armthumb.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_armthumb.c; path = ../../../wolfcrypt/src/sp_armthumb.c; sourceTree = "<group>"; };
A46FE1652493E8F700A25BE7 /* sp_arm32.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_arm32.c; path = ../../../wolfcrypt/src/sp_arm32.c; sourceTree = "<group>"; };
A46FE1662493E8F800A25BE7 /* sp_dsp32.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_dsp32.c; path = ../../../wolfcrypt/src/sp_dsp32.c; sourceTree = "<group>"; };
A46FE1672493E8F800A25BE7 /* ge_448.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = ge_448.c; path = ../../../wolfcrypt/src/ge_448.c; sourceTree = "<group>"; };
A46FE1682493E8F800A25BE7 /* curve448.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = curve448.c; path = ../../../wolfcrypt/src/curve448.c; sourceTree = "<group>"; };
A46FE16A2493E8F800A25BE7 /* fe_448.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = fe_448.c; path = ../../../wolfcrypt/src/fe_448.c; sourceTree = "<group>"; };
A46FE16E2493E8F800A25BE7 /* sp_c32.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = sp_c32.c; path = ../../../wolfcrypt/src/sp_c32.c; sourceTree = "<group>"; };
A47546241FD9042D005176B9 /* user_settings.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = user_settings.h; path = ../user_settings.h; sourceTree = "<group>"; };
A47546251FD90492005176B9 /* tls_bench.c */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.c; name = tls_bench.c; path = ../../../examples/benchmark/tls_bench.c; sourceTree = "<group>"; };
A4ADF82A1FCE0BD300A06E90 /* wolfBench.app */ = {isa = PBXFileReference; explicitFileType = wrapper.application; includeInIndex = 0; path = wolfBench.app; sourceTree = BUILT_PRODUCTS_DIR; };
@ -233,13 +269,16 @@
A4ADF8601FCE0BFB00A06E90 /* wolfCrypt */ = {
isa = PBXGroup;
children = (
A4DFEC0F1FD4CB8500A7BB33 /* armv8-aes.c */,
A4DFEC0E1FD4CB8500A7BB33 /* armv8-sha256.c */,
A4ADF8821FCE0C4D00A06E90 /* aes.c */,
A4ADF8921FCE0C4E00A06E90 /* arc4.c */,
A4DFEC0F1FD4CB8500A7BB33 /* armv8-aes.c */,
A46FE14C2493E8F500A25BE7 /* armv8-chacha.c */,
A46FE1502493E8F600A25BE7 /* armv8-poly1305.c */,
A4DFEC0E1FD4CB8500A7BB33 /* armv8-sha256.c */,
A4ADF8A01FCE0C4F00A06E90 /* asm.c */,
A4ADF8C21FCE0C5300A06E90 /* asn.c */,
A4ADF8B11FCE0C5100A06E90 /* blake2b.c */,
A46FE1522493E8F600A25BE7 /* blake2s.c */,
A4ADF8C71FCE0C5400A06E90 /* camellia.c */,
A4ADF8CA1FCE0C5500A06E90 /* chacha.c */,
A4ADF88F1FCE0C4E00A06E90 /* chacha20_poly1305.c */,
@ -247,16 +286,21 @@
A4ADF8CE1FCE0C5500A06E90 /* coding.c */,
A4ADF8871FCE0C4D00A06E90 /* compress.c */,
A4ADF8C11FCE0C5300A06E90 /* cpuid.c */,
A46FE1572493E8F600A25BE7 /* cryptocb.c */,
A46FE1682493E8F800A25BE7 /* curve448.c */,
A4ADF8801FCE0C4D00A06E90 /* curve25519.c */,
A4ADF8A81FCE0C5000A06E90 /* des3.c */,
A4ADF8AB1FCE0C5000A06E90 /* dh.c */,
A4ADF87D1FCE0C4D00A06E90 /* dsa.c */,
A4ADF8841FCE0C4D00A06E90 /* ecc_fp.c */,
A4ADF8CC1FCE0C5500A06E90 /* ecc.c */,
A46FE15D2493E8F700A25BE7 /* ed448.c */,
A4ADF8CB1FCE0C5500A06E90 /* ed25519.c */,
A4ADF8811FCE0C4D00A06E90 /* error.c */,
A46FE16A2493E8F800A25BE7 /* fe_448.c */,
A4ADF89C1FCE0C4F00A06E90 /* fe_low_mem.c */,
A4ADF8BA1FCE0C5300A06E90 /* fe_operations.c */,
A46FE1672493E8F800A25BE7 /* ge_448.c */,
A4ADF8D01FCE0C5500A06E90 /* ge_low_mem.c */,
A4ADF88E1FCE0C4E00A06E90 /* ge_operations.c */,
A4ADF89A1FCE0C4F00A06E90 /* hash.c */,
@ -282,10 +326,20 @@
A4ADF8831FCE0C4D00A06E90 /* sha256.c */,
A4ADF8AE1FCE0C5100A06E90 /* sha512.c */,
A4ADF8B71FCE0C5200A06E90 /* signature.c */,
A46FE1652493E8F700A25BE7 /* sp_arm32.c */,
A46FE1562493E8F600A25BE7 /* sp_arm64.c */,
A46FE1622493E8F700A25BE7 /* sp_armthumb.c */,
A46FE16E2493E8F800A25BE7 /* sp_c32.c */,
52114C8621B5A7320022ADA1 /* sp_c64.c */,
A46FE1512493E8F600A25BE7 /* sp_cortexm.c */,
A46FE1662493E8F800A25BE7 /* sp_dsp32.c */,
A46FE14D2493E8F600A25BE7 /* sp_int.c */,
A46FE1612493E8F700A25BE7 /* sp_x86_64.c */,
A4ADF8BF1FCE0C5300A06E90 /* srp.c */,
A4ADF8881FCE0C4D00A06E90 /* tfm.c */,
A46FE15E2493E8F700A25BE7 /* wc_dsp.c */,
A4ADF8AA1FCE0C5000A06E90 /* wc_encrypt.c */,
A46FE1542493E8F600A25BE7 /* wc_pkcs11.c */,
A4ADF8B61FCE0C5200A06E90 /* wc_port.c */,
A4ADF87B1FCE0C4D00A06E90 /* wolfevent.c */,
A4ADF8B81FCE0C5200A06E90 /* wolfmath.c */,
@ -381,33 +435,46 @@
buildActionMask = 2147483647;
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@ -416,6 +483,7 @@
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@ -425,16 +493,19 @@
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A4ADF8EB1FCE0C5600A06E90 /* chacha20_poly1305.c in Sources */,
A4ADF86B1FCE0C1C00A06E90 /* keys.c in Sources */,
A4ADF8EE1FCE0C5600A06E90 /* arc4.c in Sources */,
A4DFEC111FD4CB8500A7BB33 /* armv8-aes.c in Sources */,
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A4ADF9061FCE0C5600A06E90 /* wc_encrypt.c in Sources */,
A4ADF8DC1FCE0C5600A06E90 /* curve25519.c in Sources */,
A4ADF8D81FCE0C5600A06E90 /* md4.c in Sources */,
@ -449,6 +520,7 @@
A4ADF8F81FCE0C5600A06E90 /* fe_low_mem.c in Sources */,
A4ADF86D1FCE0C1C00A06E90 /* wolfio.c in Sources */,
A4ADF8D71FCE0C5600A06E90 /* wolfevent.c in Sources */,
A46FE1802493E8F800A25BE7 /* ed448.c in Sources */,
A4DFEC0D1FD4CAA300A7BB33 /* benchmark.c in Sources */,
A4ADF91D1FCE0C5600A06E90 /* cpuid.c in Sources */,
);

2
IDE/XCODE/user_settings.h
View File

@ -46,6 +46,7 @@
/* ARMv8 - iPhone 8/8Plus and iPhone X */
#ifdef __ARM_FEATURE_CRYPTO
#define WOLFSSL_ARMASM
#define WOLFSSL_SP_ARM64_ASM
#endif
/* newer algorithms */
@ -75,6 +76,7 @@
/* test certificate buffers */
#define USE_CERT_BUFFERS_2048
#define USE_CERT_BUFFERS_256
#define NO_WRITE_TEMP_FILES
#define WOLFSSL_DTLS

191
IDE/XCODE/wolfssl.xcodeproj/project.pbxproj
View File

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@ -1119,6 +1188,29 @@
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A4DAE3452493F21900CEF51F /* wc_pkcs11.c in Sources */,
A4DAE3302493F21900CEF51F /* ecc_fp.c in Sources */,
A4DAE3362493F21900CEF51F /* wolfevent.c in Sources */,
A4F3187A1BC58B1700FDF2BB /* keys.c in Sources */,
A4F318511BC58B1700FDF2BB /* logging.c in Sources */,
A4F318701BC58B1700FDF2BB /* md2.c in Sources */,
A4DAE34B2493F21900CEF51F /* idea.c in Sources */,
A4F318651BC58B1700FDF2BB /* md4.c in Sources */,
A4F3185E1BC58B1700FDF2BB /* md5.c in Sources */,
A4DAE3562493F29E00CEF51F /* sp_dsp32.c in Sources */,
A4DAE3272493F21900CEF51F /* fe_448.c in Sources */,
A4F3186A1BC58B1700FDF2BB /* memory.c in Sources */,
A4F318641BC58B1700FDF2BB /* ocsp.c in Sources */,
A4DAE3072493F1C700CEF51F /* tls13.c in Sources */,
A4F318531BC58B1700FDF2BB /* poly1305.c in Sources */,
A4F318571BC58B1700FDF2BB /* pwdbased.c in Sources */,
A4F3186E1BC58B1700FDF2BB /* pkcs7.c in Sources */,
520775A32239ABBE00087711 /* sp_c32.c in Sources */,
A4F3185C1BC58B1700FDF2BB /* rabbit.c in Sources */,
A4F318611BC58B1700FDF2BB /* random.c in Sources */,
A4DAE32D2493F21900CEF51F /* cmac.c in Sources */,
A4F318691BC58B1700FDF2BB /* ripemd.c in Sources */,
A4DAE3242493F21900CEF51F /* asm.c in Sources */,
A4F318601BC58B1700FDF2BB /* rsa.c in Sources */,
A4F318521BC58B1700FDF2BB /* sha.c in Sources */,
A4F3186C1BC58B1700FDF2BB /* sha256.c in Sources */,
@ -1673,10 +1853,15 @@
1E8BEB71212F4C340063DCC1 /* sp_int.c in Sources */,
1E8BEB6D212F4AA10063DCC1 /* sp_x86_64.c in Sources */,
A4F3185F1BC58B1700FDF2BB /* ssl.c in Sources */,
A4DAE3482493F21900CEF51F /* blake2s.c in Sources */,
A4DAE32A2493F21900CEF51F /* compress.c in Sources */,
A4F318781BC58B1700FDF2BB /* tfm.c in Sources */,
A4DAE3392493F21900CEF51F /* pkcs12.c in Sources */,
A4F318631BC58B1700FDF2BB /* tls.c in Sources */,
A4F318621BC58B1700FDF2BB /* wc_encrypt.c in Sources */,
A4DAE3542493F29B00CEF51F /* sp_cortexm.c in Sources */,
A4F318561BC58B1700FDF2BB /* wc_port.c in Sources */,
A4DAE3212493F21900CEF51F /* cpuid.c in Sources */,
A4F318771BC58B1700FDF2BB /* wolfio.c in Sources */,
1E8BEB7F212F4DD00063DCC1 /* wolfmath.c in Sources */,
);

0
IDE/XilinxSDK/.cproject → IDE/XilinxSDK/2018_2/.cproject
View File

0
IDE/XilinxSDK/.project → IDE/XilinxSDK/2018_2/.project
View File

0
IDE/XilinxSDK/lscript.ld → IDE/XilinxSDK/2018_2/lscript.ld
View File

378
IDE/XilinxSDK/2019_2/wolfCrypt_example/.cproject Normal file
View File

@ -0,0 +1,378 @@
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<link>
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<link>
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<link>
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<link>
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<link>
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<link>
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<link>
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<link>
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<link>
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<link>
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<link>
<name>src/wolfcrypt/src/port/arm</name>
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<link>
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<locationURI>PARENT-4-PROJECT_LOC/wolfcrypt/src/port/nrf51.c</locationURI>
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<link>
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<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>src/wolfcrypt/src/port/arm/armv8-32-curve25519.S</name>
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<locationURI>PARENT-4-PROJECT_LOC/wolfcrypt/src/port/arm/armv8-32-curve25519.S</locationURI>
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<link>
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<locationURI>PARENT-4-PROJECT_LOC/wolfcrypt/src/port/arm/armv8-32-curve25519.c</locationURI>
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<link>
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<locationURI>PARENT-4-PROJECT_LOC/wolfcrypt/src/port/arm/armv8-chacha.c</locationURI>
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<link>
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<link>
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<locationURI>PARENT-4-PROJECT_LOC/wolfcrypt/src/port/arm/armv8-curve25519.c</locationURI>
</link>
<link>
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<locationURI>PARENT-4-PROJECT_LOC/wolfcrypt/src/port/arm/armv8-poly1305.c</locationURI>
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<link>
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309
IDE/XilinxSDK/2019_2/wolfCrypt_example/src/lscript.ld Normal file
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@ -0,0 +1,309 @@
/* Linker Script for Zynq MP */
/* Stack and Heap increased to 64KB */
_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x10000;
_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x10000;
_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024;
_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048;
_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024;
/* Define Memories in the system */
MEMORY
{
ddr4_ctrl_C0_DDR4_ADDRESS_BLOCK : ORIGIN = 0x500000000, LENGTH = 0x20000000
psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x7FF00000
psu_ddr_1_MEM_0 : ORIGIN = 0x800000000, LENGTH = 0x80000000
psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000
psu_qspi_linear_0_MEM_0 : ORIGIN = 0xC0000000, LENGTH = 0x20000000
}
/* Specify the default entry point to the program */
ENTRY(_vector_table)
/* Define the sections, and where they are mapped in memory */
SECTIONS
{
.text : {
KEEP (*(.vectors))
*(.boot)
*(.text)
*(.text.*)
*(.gnu.linkonce.t.*)
*(.plt)
*(.gnu_warning)
*(.gcc_execpt_table)
*(.glue_7)
*(.glue_7t)
*(.ARM.extab)
*(.gnu.linkonce.armextab.*)
} > psu_ddr_0_MEM_0
.init (ALIGN(64)) : {
KEEP (*(.init))
} > psu_ddr_0_MEM_0
.fini (ALIGN(64)) : {
KEEP (*(.fini))
} > psu_ddr_0_MEM_0
.interp : {
KEEP (*(.interp))
} > psu_ddr_0_MEM_0
.note-ABI-tag : {
KEEP (*(.note-ABI-tag))
} > psu_ddr_0_MEM_0
.rodata : {
. = ALIGN(64);
__rodata_start = .;
*(.rodata)
*(.rodata.*)
*(.gnu.linkonce.r.*)
__rodata_end = .;
} > psu_ddr_0_MEM_0
.rodata1 : {
. = ALIGN(64);
__rodata1_start = .;
*(.rodata1)
*(.rodata1.*)
__rodata1_end = .;
} > psu_ddr_0_MEM_0
.sdata2 : {
. = ALIGN(64);
__sdata2_start = .;
*(.sdata2)
*(.sdata2.*)
*(.gnu.linkonce.s2.*)
__sdata2_end = .;
} > psu_ddr_0_MEM_0
.sbss2 : {
. = ALIGN(64);
__sbss2_start = .;
*(.sbss2)
*(.sbss2.*)
*(.gnu.linkonce.sb2.*)
__sbss2_end = .;
} > psu_ddr_0_MEM_0
.data : {
. = ALIGN(64);
__data_start = .;
*(.data)
*(.data.*)
*(.gnu.linkonce.d.*)
*(.jcr)
*(.got)
*(.got.plt)
__data_end = .;
} > psu_ddr_0_MEM_0
.data1 : {
. = ALIGN(64);
__data1_start = .;
*(.data1)
*(.data1.*)
__data1_end = .;
} > psu_ddr_0_MEM_0
.got : {
*(.got)
} > psu_ddr_0_MEM_0
.got1 : {
*(.got1)
} > psu_ddr_0_MEM_0
.got2 : {
*(.got2)
} > psu_ddr_0_MEM_0
.ctors : {
. = ALIGN(64);
__CTOR_LIST__ = .;
___CTORS_LIST___ = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
__CTOR_END__ = .;
___CTORS_END___ = .;
} > psu_ddr_0_MEM_0
.dtors : {
. = ALIGN(64);
__DTOR_LIST__ = .;
___DTORS_LIST___ = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
__DTOR_END__ = .;
___DTORS_END___ = .;
} > psu_ddr_0_MEM_0
.fixup : {
__fixup_start = .;
*(.fixup)
__fixup_end = .;
} > psu_ddr_0_MEM_0
.eh_frame : {
*(.eh_frame)
} > psu_ddr_0_MEM_0
.eh_framehdr : {
__eh_framehdr_start = .;
*(.eh_framehdr)
__eh_framehdr_end = .;
} > psu_ddr_0_MEM_0
.gcc_except_table : {
*(.gcc_except_table)
} > psu_ddr_0_MEM_0
.mmu_tbl0 (ALIGN(4096)) : {
__mmu_tbl0_start = .;
*(.mmu_tbl0)
__mmu_tbl0_end = .;
} > psu_ddr_0_MEM_0
.mmu_tbl1 (ALIGN(4096)) : {
__mmu_tbl1_start = .;
*(.mmu_tbl1)
__mmu_tbl1_end = .;
} > psu_ddr_0_MEM_0
.mmu_tbl2 (ALIGN(4096)) : {
__mmu_tbl2_start = .;
*(.mmu_tbl2)
__mmu_tbl2_end = .;
} > psu_ddr_0_MEM_0
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx*)
*(.gnu.linkonce.armexidix.*.*)
__exidx_end = .;
} > psu_ddr_0_MEM_0
.preinit_array : {
. = ALIGN(64);
__preinit_array_start = .;
KEEP (*(SORT(.preinit_array.*)))
KEEP (*(.preinit_array))
__preinit_array_end = .;
} > psu_ddr_0_MEM_0
.init_array : {
. = ALIGN(64);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
} > psu_ddr_0_MEM_0
.fini_array : {
. = ALIGN(64);
__fini_array_start = .;
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array))
__fini_array_end = .;
} > psu_ddr_0_MEM_0
.ARM.attributes : {
__ARM.attributes_start = .;
*(.ARM.attributes)
__ARM.attributes_end = .;
} > psu_ddr_0_MEM_0
.sdata : {
. = ALIGN(64);
__sdata_start = .;
*(.sdata)
*(.sdata.*)
*(.gnu.linkonce.s.*)
__sdata_end = .;
} > psu_ddr_0_MEM_0
.sbss (NOLOAD) : {
. = ALIGN(64);
__sbss_start = .;
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.sb.*)
. = ALIGN(64);
__sbss_end = .;
} > psu_ddr_0_MEM_0
.tdata : {
. = ALIGN(64);
__tdata_start = .;
*(.tdata)
*(.tdata.*)
*(.gnu.linkonce.td.*)
__tdata_end = .;
} > psu_ddr_0_MEM_0
.tbss : {
. = ALIGN(64);
__tbss_start = .;
*(.tbss)
*(.tbss.*)
*(.gnu.linkonce.tb.*)
__tbss_end = .;
} > psu_ddr_0_MEM_0
.bss (NOLOAD) : {
. = ALIGN(64);
__bss_start__ = .;
*(.bss)
*(.bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(64);
__bss_end__ = .;
} > psu_ddr_0_MEM_0
_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 );
_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 );
/* Generate Stack and Heap definitions */
.heap (NOLOAD) : {
. = ALIGN(64);
_heap = .;
HeapBase = .;
_heap_start = .;
. += _HEAP_SIZE;
_heap_end = .;
HeapLimit = .;
} > psu_ddr_0_MEM_0
.stack (NOLOAD) : {
. = ALIGN(64);
_el3_stack_end = .;
. += _STACK_SIZE;
__el3_stack = .;
_el2_stack_end = .;
. += _EL2_STACK_SIZE;
. = ALIGN(64);
__el2_stack = .;
_el1_stack_end = .;
. += _EL1_STACK_SIZE;
. = ALIGN(64);
__el1_stack = .;
_el0_stack_end = .;
. += _EL0_STACK_SIZE;
. = ALIGN(64);
__el0_stack = .;
} > psu_ddr_0_MEM_0
_end = .;
}

106
IDE/XilinxSDK/2019_2/wolfCrypt_example_system/.cproject Normal file
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@ -0,0 +1,106 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.1747591511">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.1747591511" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.1747591511" name="Debug" parent="com.xilinx.sdx.system.managedbuilder.debugConfiguration">
<folderInfo id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.1747591511." name="/" resourcePath="">
<toolChain id="com.xilinx.sdx.system.managedbuilder.debug.toolChain.2130101163" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.debug.toolChain">
<targetPlatform id="com.xilinx.sdx.system.managedbuilder.debugConfiguration.1747591511..2039133948" name=""/>
<builder buildPath="${workspace_loc:/wolfCrypt_example_system}/Debug" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.659457512" managedBuildOn="true" name="System Project Builder.Debug" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
<tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.2119034169" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
<cconfiguration id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.315007310">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.315007310" moduleId="org.eclipse.cdt.core.settings" name="Release">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildProperties="" description="" id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.315007310" name="Release" parent="com.xilinx.sdx.system.managedbuilder.releaseConfiguration">
<folderInfo id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.315007310." name="/" resourcePath="">
<toolChain id="com.xilinx.sdx.system.managedbuilder.release.toolChain.1320610434" name="System Toolchain" superClass="com.xilinx.sdx.system.managedbuilder.release.toolChain">
<targetPlatform id="com.xilinx.sdx.system.managedbuilder.releaseConfiguration.315007310..1838809633" name=""/>
<builder buildPath="${workspace_loc:/wolfCrypt_example_system}/Release" enableAutoBuild="true" id="com.xilinx.sdx.system.managedbuilder.systemBuilder.1303178964" managedBuildOn="true" name="System Project Builder.Release" superClass="com.xilinx.sdx.system.managedbuilder.systemBuilder"/>
<tool id="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool.1086546437" name="System Builder" superClass="com.xilinx.sdx.system.managedbuilder.toolchain.cfjoinTool"/>
</toolChain>
</folderInfo>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="wolfCrypt_example_system.com.xilinx.sdx.system.managedbuilder.projectType.320873684" name="Xilinx SDX System Project" projectType="com.xilinx.sdx.system.managedbuilder.projectType"/>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</storageModule>
</cproject>

7
IDE/OPENSTM32/.project → IDE/XilinxSDK/2019_2/wolfCrypt_example_system/.project
View File

@ -1,13 +1,13 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>wolfSTM32_CubeMX</name>
<name>wolfCrypt_example_system</name>
<comment></comment>
<projects>
<project>wolfCrypt_example</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
@ -19,9 +19,10 @@
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdx.system.systemprojectnature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>fr.ac6.mcu.ide.core.MCUProjectNature</nature>
</natures>
</projectDescription>

19
IDE/XilinxSDK/2019_2/wolfCrypt_example_system/wolfCrypt_example_system.sprj Normal file
View File

@ -0,0 +1,19 @@
<?xml version="1.0" encoding="ASCII"?>
<systemproject:SystemProject xmi:version="2.0" xmlns:xmi="http://www.omg.org/XMI" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:sdsproject="http://www.xilinx.com/sdsproject" xmlns:systemproject="http://www.xilinx.com/systemproject" name="wolfCrypt_example_system" platform="${workspace_loc:/standalone_bsp_0}/export/standalone_bsp_0/standalone_bsp_0.xpfm" platformUID="xilinx:zcu102:design_1:0.0(custom)" sysConfig="standalone_bsp_0" runtime="C/C++">
<configuration name="Debug">
<configBuildOptions xsi:type="systemproject:SystemOptions">
<applications name="wolfCrypt_example" domainName="standalone_domain" domainPrettyName="standalone on psu_cortexa53_0" appBuildConfig="Debug"/>
<options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
</configBuildOptions>
<lastBuildOptions xsi:type="systemproject:SystemOptions">
<applications name="wolfCrypt_example" domainName="standalone_domain" domainPrettyName="standalone on psu_cortexa53_0" appBuildConfig="Debug"/>
<options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
</lastBuildOptions>
</configuration>
<configuration name="Release">
<configBuildOptions xsi:type="systemproject:SystemOptions">
<applications name="wolfCrypt_example" domainName="standalone_domain" domainPrettyName="standalone on psu_cortexa53_0" appBuildConfig="Release"/>
<options xsi:type="sdsproject:Option" gensdcard="true" dmclkid="0"/>
</configBuildOptions>
</configuration>
</systemproject:SystemProject>

57
IDE/XilinxSDK/README.md
View File

@ -1,11 +1,64 @@
# Xilinx SDK wolfCrypt Project
# Common Gotcha's
- If compiling all code togther (ie no sperate wolfssl library) than the -fPIC compiler flag should be used. Without using -fPIC in this build setup there could be unexpected failures.
- If building with ARMv8 crypto extensions then the compiler flags "-mstrict-align -mcpu=generic+crypto" must be used.
- Check that enough stack and heap memory is set for the operations if a crash or stall happens.
# Xilinx SDK wolfCrypt Vitis 2018.2 Project
To use this example project:
1. Start a new workspace
2. Create a new BSP called `standalone_bsp_0`.
3. Copy `.cproject` and `.project` into the wolfSSL root.
3. Copy `.cproject` and `.project` from IDE/XilinxSDK/2018_2 into the wolfSSL root.
4. From the Xilinx SDK Import wolfBoot using "Import" -> "Existing Projects into Workspace".
# Detailed Instructions For Example Use With Vitis 2019.2
1. Create a new workspace located in the directory wolfssl/IDE/XilinxSDK/2019_2
2. Create a new BSP, by selecting;
- File->New->Platform Project
- Setting "Project name" to standalone_bsp_0, then click "Next"
- Select the "Create from hardware specification" radius and click "Next"
- "Browse..." to the desired XSA file for the hardare
- (optional) change Processor to R5 now
- click "Finish"
3. (optional) If building for TLS support than expand the standalone_bsp_0 project, double click on platform_spr, Expand the cpu (i.e psu_cortexa53_0), click on Board Support Package, select the "Modify BSP Settings..." box and click on lwip211. Note that the api_mode should be changed from RAW API to SOCKET API.
4. Right click on the standalone_bsp_0 project and click on "Build Project"
5. Import the wolfcrypt example project "File->Import->Eclipse workspace or zip file"
6. Uncheck "Copy projects into workspace"
7. Select the root directory of wolfssl/IDE/XilinxSDK/2019_2, and select wolfCrypt_example and wolfCrypt_example_system. Then click "Finish"
# Steps For Creating Project From Scratch
1. Create a new workspace
2. Create a new BSP, by selecting;
- File->New->Platform Project
- Setting "Project name" to standalone_bsp_0, then click "Next"
- Select the "Create from hardware specification" radius and click "Next"
- "Browse..." to the desired XSA file for the hardare
- (optional) change Processor to R5 now
- click "Finish"
3. (optional) If building for TLS support than expand the standalone_bsp_0 project, double click on platform_spr, Expand the cpu (i.e psu_cortexa53_0), click on Board Support Package, select the "Modify BSP Settings..." box and click on lwip211. Note that the api_mode should be changed from RAW API to SOCKET API.
4. Right click on the standalone_bsp_0 project and click on "Build Project"
5. Create wolfssl project File->New->Application Project
6. Name the project wolfCrypt_example, select "Next"
7. For the platform select standalone_bsp_0 and click next, then next once more on Domain.
8. Select "Empty Application" and click "Finish"
9. Expand the wolfCrypt_example project and right click on the folder "src".
10. Select "Import Sources" and set the "From directory" to be the wolfssl root directory.
11. Select the folders to import as ./src, ./IDE/XilinxSDK, ./wolfcrypt/benchmark, ./wolfcrypt/test, ./wolfcrypt/src
12. (optional) Expand the Advanced tabe and select "Create links in workspace"
13. Click on "Finish"
14. Expand the wolfcrypt/src directory and exlude all .S files from the build
15. Right click on the wolfCrypt_example project and got to Properties. Set the macro WOLFSSL_USER_SETTINGS in C/C++ Build->Settings->ARM v8 gcc compiler->Symbols
16. Set the include path for finding user_settings.h by going to the Properties and setting it in C/C++ Build->Settings->ARM v8 gcc compiler->Directories. This is to the directory wolfssl/IDE/XilinxSDK
17. Set the include path for finding wolfSSL headers. To the root directory wolfssl
18. Add compiler flags "-fPIC -mstrict-align -mcpu=generic+crypto" to the project properties. C/C++ Build->Settings->ARM v8 gcc compiler->Miscellaneous
19. Right click on wolfCrypt_example and "Build Project"
## Platform
Tested on the Zynq UltraScale+ MPSoC (ZUC102).

12
IDE/XilinxSDK/include.am
View File

@ -5,6 +5,12 @@
EXTRA_DIST+= IDE/XilinxSDK/README.md
EXTRA_DIST+= IDE/XilinxSDK/user_settings.h
EXTRA_DIST+= IDE/XilinxSDK/wolfssl_example.c
EXTRA_DIST+= IDE/XilinxSDK/lscript.ld
EXTRA_DIST+= IDE/XilinxSDK/.cproject
EXTRA_DIST+= IDE/XilinxSDK/.project
EXTRA_DIST+= IDE/XilinxSDK/2018_2/lscript.ld
EXTRA_DIST+= IDE/XilinxSDK/2018_2/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2018_2/.project
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example/.project
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example/src/lscript.ld
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example_system/.cproject
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example_system/.project
EXTRA_DIST+= IDE/XilinxSDK/2019_2/wolfCrypt_example_system/wolfCrypt_example_system.sprj

4
IDE/include.am
View File

@ -12,7 +12,7 @@ include IDE/ROWLEY-CROSSWORKS-ARM/include.am
include IDE/TRUESTUDIO/include.am
include IDE/ARDUINO/include.am
include IDE/INTIME-RTOS/include.am
include IDE/OPENSTM32/include.am
include IDE/STM32Cube/include.am
include IDE/VS-ARM/include.am
include IDE/VS-AZURE-SPHERE/include.am
include IDE/GCC-ARM/include.am
@ -24,7 +24,7 @@ include IDE/mynewt/include.am
include IDE/Renesas/e2studio/DK-S7G2/include.am
include IDE/Renesas/cs+/Projects/include.am
include IDE/Renesas/e2studio/Projects/include.am
include IDE/Renesas/e2studio/RA6M3G/include.am
include IDE/Renesas/e2studio/RA6M3/include.am
include IDE/Renesas/e2studio/GR-ROSE/include.am
include IDE/WICED-STUDIO/include.am
include IDE/CRYPTOCELL/include.am

225
README
View File

@ -10,9 +10,9 @@ levels, is up to 20 times smaller than OpenSSL, and offers progressive ciphers
such as ChaCha20, Curve25519, NTRU, and Blake2b. User benchmarking and feedback
reports dramatically better performance when using wolfSSL over OpenSSL.
wolfSSL is powered by the wolfCrypt library. A version of the wolfCrypt
cryptography library has been FIPS 140-2 validated (Certificate #2425). For
additional information, visit the wolfCrypt FIPS FAQ
wolfSSL is powered by the wolfCrypt library. Two versions of the wolfCrypt
cryptography library have been FIPS 140-2 validated (Certificate #2425 and
certificate #3389). For additional information, visit the wolfCrypt FIPS FAQ
(https://www.wolfssl.com/license/fips/) or contact fips@wolfssl.com
*** Why choose wolfSSL? ***
@ -73,126 +73,126 @@ should be used for the enum name.
*** end Notes ***
********* wolfSSL Release 4.3.0 (12/20/2019)
# wolfSSL Release 4.4.0 (04/22/2020)
If you have questions about this release, then feel free to contact us on our info@ address.
If you have questions about this release, feel free to contact us on our
info@ address.
Release 4.3.0 of wolfSSL embedded TLS has bug fixes and new features including:
Release 4.4.0 of wolfSSL embedded TLS has bug fixes and new features including:
***** New Feature Additions
* Add --enable-libwebsockets option for support of libwebsockets build
* Updated support for NGINX 1.15.0 and added support for 1.16.1
* Add wc_scrypt_ex API which can take in iterations rather than cost
* Updates to RSA-PSS salt lengths. Macro WOLFSSL_PSS_SALT_LEN_DISCOVER allows for discovering the salt length. Passing RSA_PSS_SALT_LEN_DISCOVER value into wc_RsaPSS_Verify_ex attempts to discover salt length and can use larger salt lengths
* Additional OpenSSL compatibility API wolfSSL_CertManagerGetCerts and wolfSSL_X509_STORE_GetCerts for retrieving certificates
* Add support for 4096-bit RSA/DH operations to SP (single precision) build
* Update support for Google WebRTC to branch m79
* Adds new FREESCALE_MQX_5_0 macro for MQX 5.0 support
* Adds a CMS/PKCS#7 callback for signing SignedData raw digests enabled with macro HAVE_PKCS7_RSA_RAW_SIGN_CALLBACK and call to function wc_PKCS7_SetRsaSignRawDigestCb
* Add --disable-errorqueue feature to disable adding debug nodes to queue with --enable-opensslextra build
* After defining WOLFSSL_SHUTDOWNONCE macro the function wolfSSL_shutdown will return a specific error code of SSL_SHUTDOWN_ALREADY_DONE_E, to indicate to the application that the shutdown has already occurred
* Add AES-CCM decryption to benchmarking app bundled with wolfSSL
## New Feature Additions
* Hexagon support.
* DSP builds to offload ECC verify operations.
* Certificate Manager callback support.
* New APIs for running updates to ChaCha20/Poly1305 AEAD.
* Support for use with Apache.
* Add support for IBM s390x.
* PKCS8 support for ED25519.
* OpenVPN support.
* Add P384 curve support to SP.
* Add BIO and EVP API.
* Add AES-OFB mode.
* Add AES-CFB mode.
* Add Curve448, X448, and Ed448.
* Add Renesas Synergy S7G2 build and hardware acceleration.
***** Fixes
* Fixes IAR warnings with IAR-EWARM 7.50.2
* Alignment fixes for mmCAU with AES and hashing algorithms
* Fix check for plaintext length when using Encrypt-Then-MAC
* Fix for unit tests with NGINX and debug mode
* Fix for macro names in test cases (WOLFSSL_PUBLIC_MP) and pkcs7.c (HAVE_AESCCM)
* Fix for Apache want read case with BIO retry flag
* Fix for PKCS7 streaming mode that would error rather than verify bundle
* Fix for freeing mutex for X509 and wolfSSL_EVP_PKEY_free, applies to OPENSSL_EXTRA / --enable-opensslextra builds
* Fix for encrypt then MAC when re-handshaking, encrypted handshakes change over to ETM now
* Fix for curve25519 assembly optimizations with GCC + AVX2
* Fix to hang onto certificate for retrieval if using secure renegotiation and session resumption
* Fixes case where the heap hint is created before WOLFSSL_CTX, when calling wc_LoadStaticMemory instead of wolfSSL_CTX_load_static_memory
* Fix for setting correct return value in PKCS12 parse error case
* Reset certificate extension policy count
* Fix for memcpy with TLS I/O buffers when using staticmemory pools and loading memory as WOLFMEM_IO_POOL_FIXED
* Fixes and updates for STM32 port, including additional mutex protection, AES-GCM decrypt auth tag, AES-CTR mode with CubeMX, update to OpenSTM32 project
* Fix for EVP CipherUpdate decrypt and add a test case
* DTLS fixes including; some DTLS sequence number issues in general where the sequence was incremented twice for each record and some offset values in the DTLS window checking
* Fix sp_add to handle carries properly (--enable-sp-math build)
* Additional sanity check on OCSP response decoder
* Fix for vasprintf with Solaris and AIX builds
* Fix for missing variable declaration with --enable-scep --with-libz build
* Fix for certificate date check with async build
* Sanity check on “out” length with Base64_Decode added
* Decode X.509 name - check input length for jurisdiction
* Additional sanity check on variable out index with DecodePolicyOID
* Fix for PKCS#12 PBKDF buffer size for buffer overflow
* TLS supported curve extension check curve name is in range before checking for disabled
* Sanity check for non TLS 1.3 cipher suite with TLS 1.3 connection
* Poly1305 AVX2 assembly optimization fix for carry with large input values
* Fixes for coverity report including null termination of test case strings and initialization of PKCS7 variables
* Fix for API visibility of wc_ed25519_check_key which resolves a wolfcrypt-py install issue
* Sanity check on max ALPN length accepted
* Additional sanity check when parsing CRL’s for copying the structure, fix for bounds checking
* Additional checks on error string length for debug mode and check for null termination
* ProcessPeerCerts allocating memory for exts with OPENSSL_EXTRA properly
* Clear the top bit when generating a serial number
* Sanity check that ASN date characters are valid ASCII characters
* Fix to add deterministic ECDSA and fix corner cases for add point.
* When getting the DH public key, initialize the P, G, and Pub pointers to NULL, then set that we own the DH parameters flag. This allows FreeSSL to correctly clean up the DH key.
## Fixes
***** Improvements/Optimizations
* Added configure error report with using invalid build of --enable-opensslextra and --enable-opensslcoexist together
* Update PKCS11 for determining key type given the private key type
* Update DoVerifyCallback to check verify param hostName and ipasc (--enable-opensslextra builds)
* additional null sanity checks on input arguments with QSH and Cryptocell builds
* Additional checks on RSA key added to the function wc_CheckRsaKey
* Updates for EBSNET support, including fseek, revised macros in settings.h, and realloc support
* MISRA-C updates for SP math code
* Update to allow compiling for pwdbased/PBKDF2 with having NO_ASN defined
* Modify KeyShare and PreSharedKey TLS 1.3 extension linked list advancement to be easier for compilers to handle
* Optimization to parsing certificate extension name strings
* Adjustment to example server -x runtime behavior when encountering an unrecoverable error case
* Remove Blake2b support from HMAC
* Adds new hash wrapper init wc_HashInit_ex and Adds new PBKDF2 API wc_PBKDF2_ex for using heap hints for custom memory pools
* Adding script to cleanup generated test files, scripts/cleanup_testfiles.sh
* Support 20-byte serial numbers and disallow 0
* sp_div improved to handle when a has less digits than d (--enable-sp-math build)
* When decoding a policy OID and turning it into a human readable string use snprintf()
* set the IV length of EVP AES GCM to 96-bits by default
* Allow adding CAs for root CA's over the wire that do not have the extended key usage cert_sign set
* Added logging messages for SendAlert call and update to send alert after verify certificate callback
* updates for synchronous OCTEON support in the Sniffer
* Rework BER to DER functions to not be recursive
* Updates to find CRL by AuthKeyId
* Add a check for subject name hash after matching AKID
* Enhancement to mp_invmod/fp_exptmod/sp_exptmod to handle more inputs
* Remove requirement for macro NO_SKID when CRL use is enabled
* Improvements on XFTELL return code and MAX_WOLFSSL_FILE_SIZE checking
* When checking if value is prime return NO in the case of the value 1
* Improve Cortex-M RSA/DH assembly code performance
* Additional sanity checks on arrays and buffers with OCSP
* Fix for RSA public encrypt / private sign with RSA key sizes over 2048-bit.
* Correct misspellings.
* Secure renegotiation fix.
* Fix memory leak when using ATECC and non-SECP256R1 curves for sign, verify,
or shared secret.
* Fix for K64 MMCAU with `WOLFSSL_SMALL_STACK_CACHE`.
* Fix the RSA verify only build.
* Fix in SP C implementation for small stack.
* Fix using the auth key id extension is set, hash might not be present.
* Fix when flattening certificate structure to include the subject alt names.
* Fixes for building with ECC sign/verify only.
* Fix for ECC and no cache resistance.
* Fix memory leak in DSA.
* Fix build on minGW.
* Fix `PemToDer()` call in `ProcessBuffer()` to set more than ECC.
* Fix for using RSA without SHA-512.
* Add some close tags to the echoserver HTTP example output.
* Miscellaneous fixes and updates for static analysis reports.
* Fixes for time structure support.
* Fixes for VxWorks support.
* Fixes for Async crypto support.
* Fix cache resist compile to work with SP C code.
* Fixes for Curve25519 x64 asm.
* Fix for SP x64 div.
* Fix for DTLS edge case where CCS and Finished come out of order and the
retransmit pool gets flushed.
* Fix for infinite loop in SHA-1 with small inputs. Thanks to Peter W.
* Fix for FIPS Hmac where `wc_HmacInit()` isn't used. `wc_HmacSetKey()` needs
to initialize the Hmac structure. Type is set to NONE, and checked against
NONE, not 0.
* Fixes for SP RSA private operations.
* Fixes for Xilinx SDK and Zynq UltraScale+ MPSoC
* Fix leak when building with HAVE_AESGCM and NO_AES_DECRYPT. Thanks G.G.
* Fixes for building ECC without ASN.
* Fix for async TLSv1.3 issues.
* Fix `wc_KeyPemToDer()` with PKCS1 and empty key.
* Omit `-fomit-frame-pointer` from CFLAGS in configure.ac.
## Improvements/Optimizations
***** This release of wolfSSL includes a fix for 6 security vulnerabilities.
* Qt 5.12 and 5.13 support.
* Added more digest types to Cryptocell RSA sign/verify.
* Some memory usage improvements.
* Speed improvements for mp_rand.
* Improvements to CRL and OCSP support.
* Refactor Poly1305 AEAD/MAC to reduce duplicate code.
* Add blinding to RSA key gen.
* Improvements to blinding.
* Improvement and expansion of OpenSSL Compatibility Layer.
* Improvements to ChaCha20.
* Improvements to X.509 processing.
* Improvements to ECC support.
* Improvement in detecting 64-bit support.
* Refactor to combine duplicate ECC parameter parsing code.
* Improve keyFormat to be set by algId and let later key parsing produce fail.
* Add test cases for 3072-bit and 4096-bit RSA keys.
* Improve signature wrapper and DH test cases.
* Improvements to the configure.ac script.
* Added constant time RSA q modinv p.
* Improve performance of SP Intel 64-bit asm.
* Added a few more functions to the ABI list.
* Improve TLS bidirectional shutdown behavior.
* OpenSSH 8.1 support.
* Improve performance of RSA/DH operations on x64.
* Add support for PKCS7/CMS Enveloped data with fragmented encrypted content.
* Example linker description for FIPS builds to enforce object ordering.
* C# wrapper improvements. Added TLS client example and TLSv1.3 methods.
* Allow setting MTU in DTLS.
* Improve PKCS12 create for outputting encrypted bundles.
* Constant time EC map to affine for private operations.
* Improve performance of RSA public key ops with TFM.
* Smaller table version of AES encrypt/decrypt.
* Support IAR with position independent code (ROPI).
* Improve speed of AArch64 assembly.
* Support AES-CTR on esp32.
* Add a no malloc option for small SP math.
## This release of wolfSSL includes fixes for 2 security vulnerabilities.
A fix for having an additional sanity check when parsing certificate domain names was added. This fix checks that the domain name location index is not past the maximum value before setting it. The reported issue affects users that are parsing certificates and have --enable-opensslextra (macro OPENSSL_EXTRA), or build options that turn this on such as --enable-all, when building wolfSSL. The CVE associated with the fix is CVE-2019-18840.
* For fast math, use a constant time modular inverse when mapping to affine
when operation involves a private key - keygen, calc shared secret, sign.
Thank you to Alejandro Cabrera Aldaya, Cesar Pereida García and
Billy Bob Brumley from the Network and Information Security Group (NISEC)
at Tampere University for the report.
Fix to set a limit on the maximum size of DTLS handshake messages. By default the RFC allows for handshake message sizes of up to 2^24-1 bytes long but in typical field use cases the handshake messages are not this large. Setting a maximum size limit on the handshake message helps avoid a potential DoS attack due to memory being malloc’d. The new default max size is set to handle a certificate chain length of approximately 9, 2048 bit RSA certificates. This only effects builds that have DTLS turned on and have applications that are using DTLS.
* Change constant time and cache resistant ECC mulmod. Ensure points being
operated on change to make constant time. Thank you to Pietro Borrello at
Sapienza University of Rome.
Fix for a potential hang when ECC caching is enabled (off by default) and --enable-fastmath is used. ECC caching is off by default and is turned on in builds that are using --enable-all or --enable-fpecc. This issue does not affect builds that are using the macro WOLFSSL_VALIDATE_ECC_IMPORT which turns on validating all ECC keys that are imported. To fix this potential hang case a sanity check on the input values to the internal invmod function was added.
To fix a potential fault injection attack on a wrapper function for wolfCrypt RSA signature generations an additional sanity check verifying the signature after it’s creation was added. This check is already done automatically in current versions of wolfSSL with TLS connections (internal function call of VerifyRsaSign during TLS state machine). The report only affects users making calls to the wolfCrypt function wc_SignatureGenerateHash and does not affect current TLS use cases. Thanks to Daniel Moghimi (@danielmgmi) from Worcester Polytechnic Institute for the report.
Blinding was added for DSA signing operations. The DSA signing uses the BEEA algorithm during modular inversion of the nonce which can potentially leak the nonce through side channels such as cache and power fluctuations. The fix of adding in blinding makes the DSA signing operation more resistant to side channel attacks. Users who have turned on DSA (disabled by default) and are performing signing operations should update. Note that DSA is not used in any TLS connections. Thanks to Daniel Moghimi (@danielmgmi) from Worcester Polytechnic Institute for the report.
Fix to add additional side channel cache attack resistance to the internal ECC function wc_ecc_mulmod_ex. This function by default is used with ECDSA signing operations. Users should update if performing ECDSA singing operations (server side ECC TLS connections, mutual authentication on client side) or calling wolfCrypt ECC sign functions and have the potential for outside users to perform sophisticated monitoring of the cache.Thanks to Daniel Moghimi (@danielmgmi) from Worcester Polytechnic Institute for the report.
For additional vulnerability information visit the vulnerability page at https://www.wolfssl.com/docs/security-vulnerabilities/
For additional vulnerability information visit the vulnerability page at
https://www.wolfssl.com/docs/security-vulnerabilities/
See INSTALL file for build instructions.
More info can be found on-line at http://wolfssl.com/wolfSSL/Docs.html
More info can be found on-line at https://wolfssl.com/wolfSSL/Docs.html
@ -203,7 +203,9 @@ More info can be found on-line at http://wolfssl.com/wolfSSL/Docs.html
[wolfSSL Wiki](https://github.com/wolfSSL/wolfssl/wiki)
[FIPS FAQ](https://www.wolfssl.com/wolfSSL/fips.html)
[FIPS FAQ](https://wolfssl.com/license/fips)
[wolfSSL Documents](https://wolfssl.com/wolfSSL/Docs.html)
[wolfSSL Manual](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-toc.html)
@ -214,3 +216,6 @@ More info can be found on-line at http://wolfssl.com/wolfSSL/Docs.html
(https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-18-wolfcrypt-api-reference.html)
[TLS 1.3](https://www.wolfssl.com/docs/tls13/)
[wolfSSL Vulnerabilities]
(https://www.wolfssl.com/docs/security-vulnerabilities/)

224
README.md
View File

@ -10,9 +10,9 @@ levels, is up to 20 times smaller than OpenSSL, and offers progressive ciphers
such as ChaCha20, Curve25519, NTRU, and Blake2b. User benchmarking and feedback
reports dramatically better performance when using wolfSSL over OpenSSL.
wolfSSL is powered by the wolfCrypt library. A version of the wolfCrypt
cryptography library has been FIPS 140-2 validated (Certificate #2425). For
additional information, visit the wolfCrypt FIPS FAQ
wolfSSL is powered by the wolfCrypt library. Two versions of the wolfCrypt
cryptography library have been FIPS 140-2 validated (Certificate #2425 and
certificate #3389). For additional information, visit the wolfCrypt FIPS FAQ
(https://www.wolfssl.com/license/fips/) or contact fips@wolfssl.com
*** Why choose wolfSSL? ***
@ -73,125 +73,126 @@ should be used for the enum name.
*** end Notes ***
# wolfSSL Release 4.3.0 (12/20/2019)
# wolfSSL Release 4.4.0 (04/22/2020)
If you have questions about this release, then feel free to contact us on our info@ address.
If you have questions about this release, feel free to contact us on our
info@ address.
Release 4.3.0 of wolfSSL embedded TLS has bug fixes and new features including:
Release 4.4.0 of wolfSSL embedded TLS has bug fixes and new features including:
##### New Feature Additions
* Add --enable-libwebsockets option for support of libwebsockets build
* Updated support for NGINX 1.15.0 and added support for 1.16.1
* Add wc_scrypt_ex API which can take in iterations rather than cost
* Updates to RSA-PSS salt lengths. Macro WOLFSSL_PSS_SALT_LEN_DISCOVER allows for discovering the salt length. Passing RSA_PSS_SALT_LEN_DISCOVER value into wc_RsaPSS_Verify_ex attempts to discover salt length and can use larger salt lengths
* Additional OpenSSL compatibility API wolfSSL_CertManagerGetCerts and wolfSSL_X509_STORE_GetCerts for retrieving certificates
* Add support for 4096-bit RSA/DH operations to SP (single precision) build
* Update support for Google WebRTC to branch m79
* Adds new FREESCALE_MQX_5_0 macro for MQX 5.0 support
* Adds a CMS/PKCS#7 callback for signing SignedData raw digests enabled with macro HAVE_PKCS7_RSA_RAW_SIGN_CALLBACK and call to function wc_PKCS7_SetRsaSignRawDigestCb
* Add --disable-errorqueue feature to disable adding debug nodes to queue with --enable-opensslextra build
* After defining WOLFSSL_SHUTDOWNONCE macro the function wolfSSL_shutdown will return a specific error code of SSL_SHUTDOWN_ALREADY_DONE_E, to indicate to the application that the shutdown has already occurred
* Add AES-CCM decryption to benchmarking app bundled with wolfSSL
## New Feature Additions
* Hexagon support.
* DSP builds to offload ECC verify operations.
* Certificate Manager callback support.
* New APIs for running updates to ChaCha20/Poly1305 AEAD.
* Support for use with Apache.
* Add support for IBM s390x.
* PKCS8 support for ED25519.
* OpenVPN support.
* Add P384 curve support to SP.
* Add BIO and EVP API.
* Add AES-OFB mode.
* Add AES-CFB mode.
* Add Curve448, X448, and Ed448.
* Add Renesas Synergy S7G2 build and hardware acceleration.
##### Fixes
* Fixes IAR warnings with IAR-EWARM 7.50.2
* Alignment fixes for mmCAU with AES and hashing algorithms
* Fix check for plaintext length when using Encrypt-Then-MAC
* Fix for unit tests with NGINX and debug mode
* Fix for macro names in test cases (WOLFSSL_PUBLIC_MP) and pkcs7.c (HAVE_AESCCM)
* Fix for Apache want read case with BIO retry flag
* Fix for PKCS7 streaming mode that would error rather than verify bundle
* Fix for freeing mutex for X509 and wolfSSL_EVP_PKEY_free, applies to OPENSSL_EXTRA / --enable-opensslextra builds
* Fix for encrypt then MAC when re-handshaking, encrypted handshakes change over to ETM now
* Fix for curve25519 assembly optimizations with GCC + AVX2
* Fix to hang onto certificate for retrieval if using secure renegotiation and session resumption
* Fixes case where the heap hint is created before WOLFSSL_CTX, when calling wc_LoadStaticMemory instead of wolfSSL_CTX_load_static_memory
* Fix for setting correct return value in PKCS12 parse error case
* Reset certificate extension policy count
* Fix for memcpy with TLS I/O buffers when using staticmemory pools and loading memory as WOLFMEM_IO_POOL_FIXED
* Fixes and updates for STM32 port, including additional mutex protection, AES-GCM decrypt auth tag, AES-CTR mode with CubeMX, update to OpenSTM32 project
* Fix for EVP CipherUpdate decrypt and add a test case
* DTLS fixes including; some DTLS sequence number issues in general where the sequence was incremented twice for each record and some offset values in the DTLS window checking
* Fix sp_add to handle carries properly (--enable-sp-math build)
* Additional sanity check on OCSP response decoder
* Fix for vasprintf with Solaris and AIX builds
* Fix for missing variable declaration with --enable-scep --with-libz build
* Fix for certificate date check with async build
* Sanity check on “out” length with Base64_Decode added
* Decode X.509 name - check input length for jurisdiction
* Additional sanity check on variable out index with DecodePolicyOID
* Fix for PKCS#12 PBKDF buffer size for buffer overflow
* TLS supported curve extension check curve name is in range before checking for disabled
* Sanity check for non TLS 1.3 cipher suite with TLS 1.3 connection
* Poly1305 AVX2 assembly optimization fix for carry with large input values
* Fixes for coverity report including null termination of test case strings and initialization of PKCS7 variables
* Fix for API visibility of wc_ed25519_check_key which resolves a wolfcrypt-py install issue
* Sanity check on max ALPN length accepted
* Additional sanity check when parsing CRL’s for copying the structure, fix for bounds checking
* Additional checks on error string length for debug mode and check for null termination
* ProcessPeerCerts allocating memory for exts with OPENSSL_EXTRA properly
* Clear the top bit when generating a serial number
* Sanity check that ASN date characters are valid ASCII characters
* Fix to add deterministic ECDSA and fix corner cases for add point.
* When getting the DH public key, initialize the P, G, and Pub pointers to NULL, then set that we own the DH parameters flag. This allows FreeSSL to correctly clean up the DH key.
## Fixes
##### Improvements/Optimizations
* Added configure error report with using invalid build of --enable-opensslextra and --enable-opensslcoexist together
* Update PKCS11 for determining key type given the private key type
* Update DoVerifyCallback to check verify param hostName and ipasc (--enable-opensslextra builds)
* additional null sanity checks on input arguments with QSH and Cryptocell builds
* Additional checks on RSA key added to the function wc_CheckRsaKey
* Updates for EBSNET support, including fseek, revised macros in settings.h, and realloc support
* MISRA-C updates for SP math code
* Update to allow compiling for pwdbased/PBKDF2 with having NO_ASN defined
* Modify KeyShare and PreSharedKey TLS 1.3 extension linked list advancement to be easier for compilers to handle
* Optimization to parsing certificate extension name strings
* Adjustment to example server -x runtime behavior when encountering an unrecoverable error case
* Remove Blake2b support from HMAC
* Adds new hash wrapper init wc_HashInit_ex and Adds new PBKDF2 API wc_PBKDF2_ex for using heap hints for custom memory pools
* Adding script to cleanup generated test files, scripts/cleanup_testfiles.sh
* Support 20-byte serial numbers and disallow 0
* sp_div improved to handle when a has less digits than d (--enable-sp-math build)
* When decoding a policy OID and turning it into a human readable string use snprintf()
* set the IV length of EVP AES GCM to 96-bits by default
* Allow adding CAs for root CA's over the wire that do not have the extended key usage cert_sign set
* Added logging messages for SendAlert call and update to send alert after verify certificate callback
* updates for synchronous OCTEON support in the Sniffer
* Rework BER to DER functions to not be recursive
* Updates to find CRL by AuthKeyId
* Add a check for subject name hash after matching AKID
* Enhancement to mp_invmod/fp_exptmod/sp_exptmod to handle more inputs
* Remove requirement for macro NO_SKID when CRL use is enabled
* Improvements on XFTELL return code and MAX_WOLFSSL_FILE_SIZE checking
* When checking if value is prime return NO in the case of the value 1
* Improve Cortex-M RSA/DH assembly code performance
* Additional sanity checks on arrays and buffers with OCSP
* Fix for RSA public encrypt / private sign with RSA key sizes over 2048-bit.
* Correct misspellings.
* Secure renegotiation fix.
* Fix memory leak when using ATECC and non-SECP256R1 curves for sign, verify,
or shared secret.
* Fix for K64 MMCAU with `WOLFSSL_SMALL_STACK_CACHE`.
* Fix the RSA verify only build.
* Fix in SP C implementation for small stack.
* Fix using the auth key id extension is set, hash might not be present.
* Fix when flattening certificate structure to include the subject alt names.
* Fixes for building with ECC sign/verify only.
* Fix for ECC and no cache resistance.
* Fix memory leak in DSA.
* Fix build on minGW.
* Fix `PemToDer()` call in `ProcessBuffer()` to set more than ECC.
* Fix for using RSA without SHA-512.
* Add some close tags to the echoserver HTTP example output.
* Miscellaneous fixes and updates for static analysis reports.
* Fixes for time structure support.
* Fixes for VxWorks support.
* Fixes for Async crypto support.
* Fix cache resist compile to work with SP C code.
* Fixes for Curve25519 x64 asm.
* Fix for SP x64 div.
* Fix for DTLS edge case where CCS and Finished come out of order and the
retransmit pool gets flushed.
* Fix for infinite loop in SHA-1 with small inputs. Thanks to Peter W.
* Fix for FIPS Hmac where `wc_HmacInit()` isn't used. `wc_HmacSetKey()` needs
to initialize the Hmac structure. Type is set to NONE, and checked against
NONE, not 0.
* Fixes for SP RSA private operations.
* Fixes for Xilinx SDK and Zynq UltraScale+ MPSoC
* Fix leak when building with HAVE_AESGCM and NO_AES_DECRYPT. Thanks G.G.
* Fixes for building ECC without ASN.
* Fix for async TLSv1.3 issues.
* Fix `wc_KeyPemToDer()` with PKCS1 and empty key.
* Omit `-fomit-frame-pointer` from CFLAGS in configure.ac.
## Improvements/Optimizations
##### This release of wolfSSL includes a fix for 6 security vulnerabilities.
* Qt 5.12 and 5.13 support.
* Added more digest types to Cryptocell RSA sign/verify.
* Some memory usage improvements.
* Speed improvements for mp_rand.
* Improvements to CRL and OCSP support.
* Refactor Poly1305 AEAD/MAC to reduce duplicate code.
* Add blinding to RSA key gen.
* Improvements to blinding.
* Improvement and expansion of OpenSSL Compatibility Layer.
* Improvements to ChaCha20.
* Improvements to X.509 processing.
* Improvements to ECC support.
* Improvement in detecting 64-bit support.
* Refactor to combine duplicate ECC parameter parsing code.
* Improve keyFormat to be set by algId and let later key parsing produce fail.
* Add test cases for 3072-bit and 4096-bit RSA keys.
* Improve signature wrapper and DH test cases.
* Improvements to the configure.ac script.
* Added constant time RSA q modinv p.
* Improve performance of SP Intel 64-bit asm.
* Added a few more functions to the ABI list.
* Improve TLS bidirectional shutdown behavior.
* OpenSSH 8.1 support.
* Improve performance of RSA/DH operations on x64.
* Add support for PKCS7/CMS Enveloped data with fragmented encrypted content.
* Example linker description for FIPS builds to enforce object ordering.
* C# wrapper improvements. Added TLS client example and TLSv1.3 methods.
* Allow setting MTU in DTLS.
* Improve PKCS12 create for outputting encrypted bundles.
* Constant time EC map to affine for private operations.
* Improve performance of RSA public key ops with TFM.
* Smaller table version of AES encrypt/decrypt.
* Support IAR with position independent code (ROPI).
* Improve speed of AArch64 assembly.
* Support AES-CTR on esp32.
* Add a no malloc option for small SP math.
## This release of wolfSSL includes fixes for 2 security vulnerabilities.
A fix for having an additional sanity check when parsing certificate domain names was added. This fix checks that the domain name location index is not past the maximum value before setting it. The reported issue affects users that are parsing certificates and have --enable-opensslextra (macro OPENSSL_EXTRA), or build options that turn this on such as --enable-all, when building wolfSSL. The CVE associated with the fix is CVE-2019-18840.
* For fast math, use a constant time modular inverse when mapping to affine
when operation involves a private key - keygen, calc shared secret, sign.
Thank you to Alejandro Cabrera Aldaya, Cesar Pereida García and
Billy Bob Brumley from the Network and Information Security Group (NISEC)
at Tampere University for the report.
Fix to set a limit on the maximum size of DTLS handshake messages. By default the RFC allows for handshake message sizes of up to 2^24-1 bytes long but in typical field use cases the handshake messages are not this large. Setting a maximum size limit on the handshake message helps avoid a potential DoS attack due to memory being malloc’d. The new default max size is set to handle a certificate chain length of approximately 9, 2048 bit RSA certificates. This only effects builds that have DTLS turned on and have applications that are using DTLS.
* Change constant time and cache resistant ECC mulmod. Ensure points being
operated on change to make constant time. Thank you to Pietro Borrello at
Sapienza University of Rome.
Fix for a potential hang when ECC caching is enabled (off by default) and --enable-fastmath is used. ECC caching is off by default and is turned on in builds that are using --enable-all or --enable-fpecc. This issue does not affect builds that are using the macro WOLFSSL_VALIDATE_ECC_IMPORT which turns on validating all ECC keys that are imported. To fix this potential hang case a sanity check on the input values to the internal invmod function was added.
To fix a potential fault injection attack on a wrapper function for wolfCrypt RSA signature generations an additional sanity check verifying the signature after it’s creation was added. This check is already done automatically in current versions of wolfSSL with TLS connections (internal function call of VerifyRsaSign during TLS state machine). The report only affects users making calls to the wolfCrypt function wc_SignatureGenerateHash and does not affect current TLS use cases. Thanks to Daniel Moghimi (@danielmgmi) from Worcester Polytechnic Institute for the report.
Blinding was added for DSA signing operations. The DSA signing uses the BEEA algorithm during modular inversion of the nonce which can potentially leak the nonce through side channels such as cache and power fluctuations. The fix of adding in blinding makes the DSA signing operation more resistant to side channel attacks. Users who have turned on DSA (disabled by default) and are performing signing operations should update. Note that DSA is not used in any TLS connections. Thanks to Daniel Moghimi (@danielmgmi) from Worcester Polytechnic Institute for the report.
Fix to add additional side channel cache attack resistance to the internal ECC function wc_ecc_mulmod_ex. This function by default is used with ECDSA signing operations. Users should update if performing ECDSA singing operations (server side ECC TLS connections, mutual authentication on client side) or calling wolfCrypt ECC sign functions and have the potential for outside users to perform sophisticated monitoring of the cache.Thanks to Daniel Moghimi (@danielmgmi) from Worcester Polytechnic Institute for the report.
For additional vulnerability information visit the vulnerability page at https://www.wolfssl.com/docs/security-vulnerabilities/
For additional vulnerability information visit the vulnerability page at
https://www.wolfssl.com/docs/security-vulnerabilities/
See INSTALL file for build instructions.
More info can be found on-line at http://wolfssl.com/wolfSSL/Docs.html
More info can be found on-line at https://wolfssl.com/wolfSSL/Docs.html
@ -202,7 +203,9 @@ More info can be found on-line at http://wolfssl.com/wolfSSL/Docs.html
[wolfSSL Wiki](https://github.com/wolfSSL/wolfssl/wiki)
[FIPS FAQ](https://www.wolfssl.com/wolfSSL/fips.html)
[FIPS FAQ](https://wolfssl.com/license/fips)
[wolfSSL Documents](https://wolfssl.com/wolfSSL/Docs.html)
[wolfSSL Manual](https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-toc.html)
@ -213,3 +216,6 @@ More info can be found on-line at http://wolfssl.com/wolfSSL/Docs.html
(https://wolfssl.com/wolfSSL/Docs-wolfssl-manual-18-wolfcrypt-api-reference.html)
[TLS 1.3](https://www.wolfssl.com/docs/tls13/)
[wolfSSL Vulnerabilities]
(https://www.wolfssl.com/docs/security-vulnerabilities/)

BIN
certs/1024/ca-cert.der
View File

Binary file not shown.

74
certs/1024/ca-cert.pem
View File

@ -1,16 +1,17 @@
Certificate:
Data:
Version: 3 (0x2)
Serial Number: 15779322327764802375 (0xdafb6a0dfecf9b47)
Serial Number:
51:08:0e:66:59:26:e1:9b:ec:b2:c8:61:15:35:41:9d:4d:e9:8a:ea
Signature Algorithm: sha256WithRSAEncryption
Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting_1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting_1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Apr 13 15:23:10 2018 GMT
Not After : Jan 7 15:23:10 2021 GMT
Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting_1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting_1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
Public-Key: (1024 bit)
RSA Public-Key: (1024 bit)
Modulus:
00:cd:ac:dd:47:ec:be:b7:24:c3:63:1b:54:98:79:
e1:c7:31:16:59:d6:9d:77:9d:8d:e2:8b:ed:04:17:
@ -28,38 +29,41 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:D3:22:8F:28:2C:E0:05:EE:D3:ED:C3:71:3D:C9:B2:36:3A:1D:BF:A8
DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting_1024/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:DA:FB:6A:0D:FE:CF:9B:47
serial:51:08:0E:66:59:26:E1:9B:EC:B2:C8:61:15:35:41:9D:4D:E9:8A:EA
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
1d:48:f6:40:41:04:06:f2:e4:72:2f:ea:ff:c1:67:6b:15:bb:
0a:28:23:28:07:c6:d7:13:2c:be:00:00:ac:1d:f7:f4:92:d3:
2b:af:23:eb:9f:1a:e2:11:3c:2d:97:f2:0f:ac:ae:97:86:0a:
fb:a8:4f:74:1b:de:19:51:db:cd:e2:11:38:c1:a4:9d:56:ab:
47:5c:de:ba:eb:27:df:6d:c8:7e:3a:bd:2e:9b:2a:ad:22:3b:
95:a9:f2:28:03:bc:e5:ec:cc:f2:08:d4:c8:2f:db:ea:fb:2e:
52:16:8c:42:02:a4:59:6d:4c:33:b4:9a:d2:73:4a:1e:9f:d9:
c8:83
bb:85:81:52:e4:7e:d9:40:36:97:7f:e1:db:fe:8e:1f:e5:f4:
d8:05:8e:25:43:6a:f2:6f:5f:d2:5c:b8:f0:a2:71:16:b7:87:
0c:53:d5:50:94:4a:89:ca:d7:a3:f1:db:bc:03:44:34:84:f9:
cb:98:a8:3c:cd:a1:1c:95:19:d0:48:ae:b3:59:70:52:2b:19:
02:05:35:b5:5c:7a:a9:1e:5e:53:74:1d:70:ee:fc:eb:0e:64:
6a:5c:50:7e:87:9e:85:8f:21:c3:39:83:e2:ce:62:88:7b:72:
74:50:09:7b:c6:1d:8f:33:82:ae:3f:6f:11:11:42:dc:c5:bd:
b8:3f
-----BEGIN CERTIFICATE-----
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-----END CERTIFICATE-----

BIN
certs/1024/client-cert.der
View File

Binary file not shown.

76
certs/1024/client-cert.pem
View File

@ -1,16 +1,17 @@
Certificate:
Data:
Version: 3 (0x2)
Serial Number: 13534178914118477827 (0xbbd31003e69d2803)
Serial Number:
0a:60:f5:96:2d:a5:e2:63:56:3e:98:93:65:56:0a:0a:11:23:98:5d
Signature Algorithm: sha256WithRSAEncryption
Issuer: C=US, ST=Montana, L=Bozeman, O=wolfSSL_1024, OU=Programming-1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Issuer: C = US, ST = Montana, L = Bozeman, O = wolfSSL_1024, OU = Programming-1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Apr 13 15:23:09 2018 GMT
Not After : Jan 7 15:23:09 2021 GMT
Subject: C=US, ST=Montana, L=Bozeman, O=wolfSSL_1024, OU=Programming-1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = wolfSSL_1024, OU = Programming-1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
Public-Key: (1024 bit)
RSA Public-Key: (1024 bit)
Modulus:
00:bc:73:0e:a8:49:f3:74:a2:a9:ef:18:a5:da:55:
99:21:f9:c8:ec:b3:6d:48:e5:35:35:75:77:37:ec:
@ -28,39 +29,42 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:81:69:0F:F8:DF:DD:CF:34:29:D5:67:75:71:85:C7:75:10:69:59:EC
DirName:/C=US/ST=Montana/L=Bozeman/O=wolfSSL_1024/OU=Programming-1024/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:BB:D3:10:03:E6:9D:28:03
serial:0A:60:F5:96:2D:A5:E2:63:56:3E:98:93:65:56:0A:0A:11:23:98:5D
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
84:99:d9:e5:37:c4:44:7d:ce:29:b8:b6:80:0e:ea:a3:e2:fa:
a2:2f:5c:d2:4a:85:67:b9:8b:fa:9f:7d:da:6d:85:2a:c2:20:
f3:18:c8:d4:6b:26:b2:7a:68:e7:82:52:87:e7:0c:5b:08:47:
7a:55:a5:0d:fa:72:ce:6b:a1:b2:ae:5a:a1:63:ff:68:db:e5:
49:ef:f1:0e:98:96:09:b5:04:5f:d4:0a:9b:8a:af:d2:31:1f:
95:e5:0f:a8:cd:bb:a1:2d:64:b0:b7:ee:47:a7:58:d9:c7:db:
b0:92:bb:aa:cf:b8:8a:04:5b:0f:9f:3e:e0:d2:42:52:bd:5d:
a7:48
3d:88:55:62:85:d5:b6:f5:cf:c8:1e:c6:6f:40:00:4c:72:2a:
c1:ea:a5:a3:1d:fc:a8:fb:9b:01:56:1e:36:cf:6d:06:bb:2d:
4d:1d:f2:bd:95:e0:21:74:7c:dd:8c:64:f9:6d:8f:96:99:22:
71:4f:c6:e5:c0:5d:ca:f8:1a:b7:23:f7:40:13:7d:92:0d:5a:
80:28:b9:7c:e2:87:68:da:3c:a5:c7:1b:0a:60:32:71:38:da:
f4:fe:56:7e:ff:f4:a3:1f:d9:30:96:48:2a:56:90:0e:7d:86:
97:d2:c7:bf:b6:4b:7a:6d:28:49:42:54:d4:50:5c:13:c8:f1:
24:4f
-----BEGIN CERTIFICATE-----
MIIDxTCCAy6gAwIBAgIJALvTEAPmnSgDMA0GCSqGSIb3DQEBCwUAMIGeMQswCQYD
VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjEVMBMG
A1UECgwMd29sZlNTTF8xMDI0MRkwFwYDVQQLDBBQcm9ncmFtbWluZy0xMDI0MRgw
FgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29s
ZnNzbC5jb20wHhcNMTgwNDEzMTUyMzA5WhcNMjEwMTA3MTUyMzA5WjCBnjELMAkG
A1UEBhMCVVMxEDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xFTAT
BgNVBAoMDHdvbGZTU0xfMTAyNDEZMBcGA1UECwwQUHJvZ3JhbW1pbmctMTAyNDEY
MBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdv
bGZzc2wuY29tMIGfMA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQC8cw6oSfN0oqnv
GKXaVZkh+cjss21I5TU1dXc37NFhkF8+2eTV35TKwanXGdqGyehNxGE2gv6rrX53
JbuNEaW8YjqoOMw5ogRmtPf386raTQIOu16NaUjcd8koDiLpa6Qmukzowf1Kbysf
74qu9pBi5WQe6ys8Z8jcJwD2kWhlqQIDAQABo4IBBzCCAQMwHQYDVR0OBBYEFIFp
D/jf3c80KdVndXGFx3UQaVnsMIHTBgNVHSMEgcswgciAFIFpD/jf3c80KdVndXGF
x3UQaVnsoYGkpIGhMIGeMQswCQYDVQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQ
MA4GA1UEBwwHQm96ZW1hbjEVMBMGA1UECgwMd29sZlNTTF8xMDI0MRkwFwYDVQQL
DBBQcm9ncmFtbWluZy0xMDI0MRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAd
BgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb22CCQC70xAD5p0oAzAMBgNVHRME
BTADAQH/MA0GCSqGSIb3DQEBCwUAA4GBAISZ2eU3xER9zim4toAO6qPi+qIvXNJK
hWe5i/qffdpthSrCIPMYyNRrJrJ6aOeCUofnDFsIR3pVpQ36cs5robKuWqFj/2jb
5Unv8Q6Ylgm1BF/UCpuKr9IxH5XlD6jNu6EtZLC37kenWNnH27CSu6rPuIoEWw+f
PuDSQlK9XadI
MIID+TCCA2KgAwIBAgIUCmD1li2l4mNWPpiTZVYKChEjmF0wDQYJKoZIhvcNAQEL
BQAwgZ4xCzAJBgNVBAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdC
b3plbWFuMRUwEwYDVQQKDAx3b2xmU1NMXzEwMjQxGTAXBgNVBAsMEFByb2dyYW1t
aW5nLTEwMjQxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJ
ARYQaW5mb0B3b2xmc3NsLmNvbTAeFw0yMDA1MDcwNzM5MDRaFw0yMzAyMDEwNzM5
MDRaMIGeMQswCQYDVQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwH
Qm96ZW1hbjEVMBMGA1UECgwMd29sZlNTTF8xMDI0MRkwFwYDVQQLDBBQcm9ncmFt
bWluZy0xMDI0MRgwFgYDVQQDDA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0B
CQEWEGluZm9Ad29sZnNzbC5jb20wgZ8wDQYJKoZIhvcNAQEBBQADgY0AMIGJAoGB
ALxzDqhJ83Siqe8YpdpVmSH5yOyzbUjlNTV1dzfs0WGQXz7Z5NXflMrBqdcZ2obJ
6E3EYTaC/qutfnclu40RpbxiOqg4zDmiBGa09/fzqtpNAg67Xo1pSNx3ySgOIulr
pCa6TOjB/UpvKx/viq72kGLlZB7rKzxnyNwnAPaRaGWpAgMBAAGjggEwMIIBLDAd
BgNVHQ4EFgQUgWkP+N/dzzQp1Wd1cYXHdRBpWewwgd4GA1UdIwSB1jCB04AUgWkP
+N/dzzQp1Wd1cYXHdRBpWeyhgaSkgaEwgZ4xCzAJBgNVBAYTAlVTMRAwDgYDVQQI
DAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMRUwEwYDVQQKDAx3b2xmU1NMXzEw
MjQxGTAXBgNVBAsMEFByb2dyYW1taW5nLTEwMjQxGDAWBgNVBAMMD3d3dy53b2xm
c3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbYIUCmD1li2l
4mNWPpiTZVYKChEjmF0wDAYDVR0TBAUwAwEB/zAcBgNVHREEFTATggtleGFtcGxl
LmNvbYcEfwAAATANBgkqhkiG9w0BAQsFAAOBgQA9iFVihdW29c/IHsZvQABMcirB
6qWjHfyo+5sBVh42z20Guy1NHfK9leAhdHzdjGT5bY+WmSJxT8blwF3K+Bq3I/dA
E32SDVqAKLl84odo2jylxxsKYDJxONr0/lZ+//SjH9kwlkgqVpAOfYaX0se/tkt6
bShJQlTUUFwTyPEkTw==
-----END CERTIFICATE-----

BIN
certs/1024/server-cert.der
View File

Binary file not shown.

129
certs/1024/server-cert.pem
View File

@ -3,14 +3,14 @@ Certificate:
Version: 3 (0x2)
Serial Number: 1 (0x1)
Signature Algorithm: sha256WithRSAEncryption
Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting_1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting_1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Apr 13 15:23:10 2018 GMT
Not After : Jan 7 15:23:10 2021 GMT
Subject: C=US, ST=Montana, L=Bozeman, O=wolfSSL, OU=Support_1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = wolfSSL, OU = Support_1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
Public-Key: (1024 bit)
RSA Public-Key: (1024 bit)
Modulus:
00:aa:3e:a5:9c:d3:17:49:65:43:de:d0:f3:4b:1c:
db:49:0c:fc:7a:65:05:6d:de:6a:c4:e4:73:2c:8a:
@ -28,54 +28,58 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:D3:22:8F:28:2C:E0:05:EE:D3:ED:C3:71:3D:C9:B2:36:3A:1D:BF:A8
DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting_1024/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:DA:FB:6A:0D:FE:CF:9B:47
serial:51:08:0E:66:59:26:E1:9B:EC:B2:C8:61:15:35:41:9D:4D:E9:8A:EA
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
0b:c3:af:43:85:64:61:e7:ab:5a:2a:1b:b2:29:d5:66:68:44:
1a:6d:66:fc:3d:b1:88:ec:a5:41:18:67:62:34:a4:5e:c9:69:
cd:40:c8:56:7e:bf:eb:bc:61:1f:33:34:58:be:57:fd:e6:98:
dd:51:27:7c:b7:2c:bc:c9:39:e5:e5:95:82:e1:3f:d9:b9:97:
30:4e:33:2c:ef:f8:db:b4:ee:35:75:9e:7a:3f:22:8f:a5:71:
d4:01:64:6c:f2:85:f7:72:99:2c:80:0f:a4:31:1d:d4:0b:1e:
a5:0f:e7:53:0a:de:15:0d:b2:d0:6b:f4:d6:2f:e2:0b:a3:8a:
5a:6e
89:cd:fc:5f:7b:99:2c:cd:83:9d:c9:a5:dd:c8:7c:66:1d:05:
9d:a6:fa:01:d7:20:25:6a:a8:22:6b:16:74:21:c4:8f:32:36:
df:e3:08:be:8f:a4:1d:45:fe:1b:80:7f:39:b3:ce:7f:df:d9:
04:2e:83:b7:18:9d:5d:d9:6c:23:fa:cd:0d:0f:98:7b:53:8a:
c1:a7:a4:90:d5:2a:b7:44:29:83:74:ca:b5:b9:41:a5:43:d7:
22:a6:02:6a:a8:28:5c:be:9a:6e:83:38:08:b6:5a:2f:48:5f:
4e:67:bf:da:f3:5f:ef:0e:f6:53:0b:80:43:48:bc:4a:4a:89:
a6:37
-----BEGIN CERTIFICATE-----
MIIDqTCCAxKgAwIBAgIBATANBgkqhkiG9w0BAQsFADCBmTELMAkGA1UEBhMCVVMx
MIID0zCCAzygAwIBAgIBATANBgkqhkiG9w0BAQsFADCBmTELMAkGA1UEBhMCVVMx
EDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNh
d3Rvb3RoMRgwFgYDVQQLDA9Db25zdWx0aW5nXzEwMjQxGDAWBgNVBAMMD3d3dy53
b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAeFw0x
ODA0MTMxNTIzMTBaFw0yMTAxMDcxNTIzMTBaMIGVMQswCQYDVQQGEwJVUzEQMA4G
b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAeFw0y
MDA1MDcwNzM5MDRaFw0yMzAyMDEwNzM5MDRaMIGVMQswCQYDVQQGEwJVUzEQMA4G
A1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjEQMA4GA1UECgwHd29sZlNT
TDEVMBMGA1UECwwMU3VwcG9ydF8xMDI0MRgwFgYDVQQDDA93d3cud29sZnNzbC5j
b20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20wgZ8wDQYJKoZIhvcN
AQEBBQADgY0AMIGJAoGBAKo+pZzTF0llQ97Q80sc20kM/HplBW3easTkcyyKloKP
I6UGcRwGPi+SjQspNEVZ6am8YdckN121xDeNumey7wMn+sG0zWsAZrTWc3AfCDrM
d63p+TTU86AtqedYqcBhhLbsPQqt/VyGc6prR9iLLlhLaRKCJlXmFL9VcIj++XXh
AgMBAAGjggEBMIH+MB0GA1UdDgQWBBTZPDXqdA4jvpz8+imQCcHnhBaffDCBzgYD
VR0jBIHGMIHDgBTTIo8oLOAF7tPtw3E9ybI2Oh2/qKGBn6SBnDCBmTELMAkGA1UE
BhMCVVMxEDAOBgNVBAgMB01vbnRhbmExEDAOBgNVBAcMB0JvemVtYW4xETAPBgNV
BAoMCFNhd3Rvb3RoMRgwFgYDVQQLDA9Db25zdWx0aW5nXzEwMjQxGDAWBgNVBAMM
D3d3dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNv
bYIJANr7ag3+z5tHMAwGA1UdEwQFMAMBAf8wDQYJKoZIhvcNAQELBQADgYEAC8Ov
Q4VkYeerWiobsinVZmhEGm1m/D2xiOylQRhnYjSkXslpzUDIVn6/67xhHzM0WL5X
/eaY3VEnfLcsvMk55eWVguE/2bmXME4zLO/427TuNXWeej8ij6Vx1AFkbPKF93KZ
LIAPpDEd1AsepQ/nUwreFQ2y0Gv01i/iC6OKWm4=
AgMBAAGjggErMIIBJzAdBgNVHQ4EFgQU2Tw16nQOI76c/PopkAnB54QWn3wwgdkG
A1UdIwSB0TCBzoAU0yKPKCzgBe7T7cNxPcmyNjodv6ihgZ+kgZwwgZkxCzAJBgNV
BAYTAlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYD
VQQKDAhTYXd0b290aDEYMBYGA1UECwwPQ29uc3VsdGluZ18xMDI0MRgwFgYDVQQD
DA93d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5j
b22CFFEIDmZZJuGb7LLIYRU1QZ1N6YrqMAwGA1UdEwQFMAMBAf8wHAYDVR0RBBUw
E4ILZXhhbXBsZS5jb22HBH8AAAEwDQYJKoZIhvcNAQELBQADgYEAic38X3uZLM2D
ncml3ch8Zh0Fnab6AdcgJWqoImsWdCHEjzI23+MIvo+kHUX+G4B/ObPOf9/ZBC6D
txidXdlsI/rNDQ+Ye1OKwaekkNUqt0Qpg3TKtblBpUPXIqYCaqgoXL6aboM4CLZa
L0hfTme/2vNf7w72UwuAQ0i8SkqJpjc=
-----END CERTIFICATE-----
Certificate:
Data:
Version: 3 (0x2)
Serial Number: 15779322327764802375 (0xdafb6a0dfecf9b47)
Serial Number:
51:08:0e:66:59:26:e1:9b:ec:b2:c8:61:15:35:41:9d:4d:e9:8a:ea
Signature Algorithm: sha256WithRSAEncryption
Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting_1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting_1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Apr 13 15:23:10 2018 GMT
Not After : Jan 7 15:23:10 2021 GMT
Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting_1024, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting_1024, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
Public-Key: (1024 bit)
RSA Public-Key: (1024 bit)
Modulus:
00:cd:ac:dd:47:ec:be:b7:24:c3:63:1b:54:98:79:
e1:c7:31:16:59:d6:9d:77:9d:8d:e2:8b:ed:04:17:
@ -93,38 +97,41 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:D3:22:8F:28:2C:E0:05:EE:D3:ED:C3:71:3D:C9:B2:36:3A:1D:BF:A8
DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting_1024/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:DA:FB:6A:0D:FE:CF:9B:47
serial:51:08:0E:66:59:26:E1:9B:EC:B2:C8:61:15:35:41:9D:4D:E9:8A:EA
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
1d:48:f6:40:41:04:06:f2:e4:72:2f:ea:ff:c1:67:6b:15:bb:
0a:28:23:28:07:c6:d7:13:2c:be:00:00:ac:1d:f7:f4:92:d3:
2b:af:23:eb:9f:1a:e2:11:3c:2d:97:f2:0f:ac:ae:97:86:0a:
fb:a8:4f:74:1b:de:19:51:db:cd:e2:11:38:c1:a4:9d:56:ab:
47:5c:de:ba:eb:27:df:6d:c8:7e:3a:bd:2e:9b:2a:ad:22:3b:
95:a9:f2:28:03:bc:e5:ec:cc:f2:08:d4:c8:2f:db:ea:fb:2e:
52:16:8c:42:02:a4:59:6d:4c:33:b4:9a:d2:73:4a:1e:9f:d9:
c8:83
bb:85:81:52:e4:7e:d9:40:36:97:7f:e1:db:fe:8e:1f:e5:f4:
d8:05:8e:25:43:6a:f2:6f:5f:d2:5c:b8:f0:a2:71:16:b7:87:
0c:53:d5:50:94:4a:89:ca:d7:a3:f1:db:bc:03:44:34:84:f9:
cb:98:a8:3c:cd:a1:1c:95:19:d0:48:ae:b3:59:70:52:2b:19:
02:05:35:b5:5c:7a:a9:1e:5e:53:74:1d:70:ee:fc:eb:0e:64:
6a:5c:50:7e:87:9e:85:8f:21:c3:39:83:e2:ce:62:88:7b:72:
74:50:09:7b:c6:1d:8f:33:82:ae:3f:6f:11:11:42:dc:c5:bd:
b8:3f
-----BEGIN CERTIFICATE-----
MIIDtTCCAx6gAwIBAgIJANr7ag3+z5tHMA0GCSqGSIb3DQEBCwUAMIGZMQswCQYD
VQQGEwJVUzEQMA4GA1UECAwHTW9udGFuYTEQMA4GA1UEBwwHQm96ZW1hbjERMA8G
A1UECgwIU2F3dG9vdGgxGDAWBgNVBAsMD0NvbnN1bHRpbmdfMTAyNDEYMBYGA1UE
AwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wu
Y29tMB4XDTE4MDQxMzE1MjMxMFoXDTIxMDEwNzE1MjMxMFowgZkxCzAJBgNVBAYT
AlVTMRAwDgYDVQQIDAdNb250YW5hMRAwDgYDVQQHDAdCb3plbWFuMREwDwYDVQQK
DAhTYXd0b290aDEYMBYGA1UECwwPQ29uc3VsdGluZ18xMDI0MRgwFgYDVQQDDA93
d3cud29sZnNzbC5jb20xHzAdBgkqhkiG9w0BCQEWEGluZm9Ad29sZnNzbC5jb20w
gZ8wDQYJKoZIhvcNAQEBBQADgY0AMIGJAoGBAM2s3Ufsvrckw2MbVJh54ccxFlnW
nXedjeKL7QQXssbr5JuRvjFQYpdYtX8p3rNxJAu/lwl/Jtwt7KgusmQreis1GS2i
gMuZ/ZRxGyONVNsuYo2BCC30JHInbPnJjttMdbqbAfg/GPTmf/tXlJLMiMS0AMKq
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EDAOBgNVBAcMB0JvemVtYW4xETAPBgNVBAoMCFNhd3Rvb3RoMRgwFgYDVQQLDA9D
b25zdWx0aW5nXzEwMjQxGDAWBgNVBAMMD3d3dy53b2xmc3NsLmNvbTEfMB0GCSqG
SIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbYIUUQgOZlkm4ZvssshhFTVBnU3piuow
DAYDVR0TBAUwAwEB/zAcBgNVHREEFTATggtleGFtcGxlLmNvbYcEfwAAATANBgkq
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dB1w7vzrDmRqXFB+h56FjyHDOYPizmKIe3J0UAl7xh2PM4KuP28REULcxb24Pw==
-----END CERTIFICATE-----

BIN
certs/3072/client-cert.der
View File

Binary file not shown.

83
certs/3072/client-cert.pem
View File

@ -2,12 +2,12 @@ Certificate:
Data:
Version: 3 (0x2)
Serial Number:
2f:06:07:a8:b6:f4:ee:10:91:43:de:e1:46:99:c4:90:79:e6:f1:d1
16:65:10:ff:e8:9a:35:33:57:0c:4b:37:e1:21:fe:8e:ca:70:54:e8
Signature Algorithm: sha256WithRSAEncryption
Issuer: C = US, ST = Montana, L = Bozeman, O = wolfSSL_3072, OU = Programming-3072, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Jan 22 05:51:48 2020 GMT
Not After : Oct 18 05:51:48 2022 GMT
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = wolfSSL_3072, OU = Programming-3072, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
@ -46,42 +46,42 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:3D:D1:84:C2:AF:B0:20:49:BC:74:87:41:38:AB:BA:D2:D4:0C:A3:A8
DirName:/C=US/ST=Montana/L=Bozeman/O=wolfSSL_3072/OU=Programming-3072/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:2F:06:07:A8:B6:F4:EE:10:91:43:DE:E1:46:99:C4:90:79:E6:F1:D1
serial:16:65:10:FF:E8:9A:35:33:57:0C:4B:37:E1:21:FE:8E:CA:70:54:E8
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
04:f5:e0:e5:75:6b:cf:ee:19:ef:3c:b5:b6:78:ce:b2:c3:f2:
3e:0d:3f:b7:6d:59:7d:b6:7e:6a:91:0f:85:ac:ca:56:30:3c:
3f:5d:30:10:7c:5e:7f:98:b2:9d:95:04:e1:ee:c0:9e:1b:01:
39:cb:02:05:b9:9b:02:88:eb:d0:ad:06:d5:39:2d:24:e6:dc:
4e:ce:8c:36:7d:b6:8e:1d:e8:b7:ef:ff:b4:17:c1:a5:d8:fa:
34:dd:99:3d:30:4b:45:a2:14:6a:88:93:ca:25:e2:5c:d5:ba:
e8:9d:ef:d7:68:76:05:92:48:19:92:11:79:c2:fe:11:49:4d:
d6:d1:8f:32:1c:5f:3b:41:2c:08:b2:72:65:1c:e5:86:02:94:
b3:9d:30:da:59:42:a1:b0:1e:00:92:93:6e:0d:27:cf:df:d8:
cf:2b:cd:cb:8c:ff:b5:6f:83:92:27:00:58:59:a2:0b:91:b0:
39:ca:a8:78:fd:83:56:4f:a1:6e:c3:e0:2b:ae:ef:3c:09:04:
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85:20:66:2c:ac:dd:65:37:36:c2:2f:ba:b8:90:66:6e:9e:58:
a2:4b:d6:a7:30:c8:c9:6c:bd:13:40:a0:ca:59:7c:c5:86:9c:
55:c5:68:c7:0c:7f:94:73:a5:4b:eb:f1:27:96:b5:f9:69:6b:
2b:b6:62:d7:3a:0d:40:65:f0:0d:de:91:77:d4:f6:bb:13:7b:
4a:55:8f:7e:49:65:89:37:46:05:2f:90:14:73:0d:2d:1e:a4:
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1d:16:40:f4:53:5c:80:a3:f6:03:75:9c:d9:54:89:1c:51:78:
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29:29:bd:40:8f:24:03:ae:b4:0c:48:9e:a8:14:1f:59:3d:fc:
2c:7e:a8:e3:8d:f0:78:96:16:b9:87:45:16:44:b8:13:24:b8:
41:bf:b1:1c:cb:da:56:9f:d7:dd:b7:0c:06:4d:5e:90:50:2d:
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48:fd:ed:e3:94:a2:80:61:03:e4:13:ed:9b:87:05:7f:d0:4f:
1b:36:36:bd:c4:4d:19:b7:df:89:a0:d8:89:6b:90:e5:86:7c:
f4:e4:12:cb:e7:86:c9:c7:f8:79:d7:51:4a:09:69:09:6d:a4:
17:5f:46:48:f7:41:31:33:dc:5e:f7:ef:b1:4b:be:04:3a:78:
e3:bf:61:9a:d4:6d:d1:53:ef:3d:64:bc:b8:4b:75:c4:0a:a9:
e6:09:e3:02:fc:86:a8:28:1e:01:7a:57:38:a8:93:dc:ef:92:
e5:a3:15:ec:77:b8:96:43:32:e0:e3:7f:7d:c6:2b:36:3e:63:
31:1f:1f:69:c8:7e:16:83:f8:19:d5:98:5e:ad:d7:e4:b1:a2:
ef:d9:2e:f3:89:34:f1:91:74:f8:6d:b9:d1:cc:e0:b4:b4:31:
67:18:0a:2d:26:51:32:4a:08:32:37:08:2e:76:6f:97:49:b0:
23:a2:0d:af:89:17:72:9d:a7:24:7f:07:07:67:f4:7e:d6:1c:
5b:59:88:15:03:81:b1:7d:0d:c7:ce:1a:95:c8:71:b8:1d:8f:
17:91:c1:21:83:f3
-----BEGIN CERTIFICATE-----
MIIF+DCCBGCgAwIBAgIULwYHqLb07hCRQ97hRpnEkHnm8dEwDQYJKoZIhvcNAQEL
MIIF/jCCBGagAwIBAgIUFmUQ/+iaNTNXDEs34SH+jspwVOgwDQYJKoZIhvcNAQEL
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CQEWEGluZm9Ad29sZnNzbC5jb20wggGiMA0GCSqGSIb3DQEBAQUAA4IBjwAwggGK
@ -93,19 +93,20 @@ dNO2BRHyYgZIKvdmzsGF4dIn6soSpZGXPvyUBllRwOcTtod7X9LAVi9eHQLDESzf
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Nwgudm+XSbAjog2viRdynackfwcHZ/R+1hxbWYgVA4GxfQ3HzhqVyHG4HY8XkcEh
g/M=
-----END CERTIFICATE-----

BIN
certs/4096/client-cert.der
View File

Binary file not shown.

105
certs/4096/client-cert.pem
View File

@ -2,12 +2,12 @@ Certificate:
Data:
Version: 3 (0x2)
Serial Number:
2f:0f:ab:23:bc:a3:14:07:91:06:55:35:01:63:7f:42:bd:fb:f2:43
08:23:7f:d2:d2:23:3e:0f:cc:55:94:25:1f:51:7b:e7:cc:3f:4c:af
Signature Algorithm: sha256WithRSAEncryption
Issuer: C = US, ST = Montana, L = Bozeman, O = wolfSSL_4096, OU = Programming-4096, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Jul 9 03:06:02 2019 GMT
Not After : Apr 4 03:06:02 2022 GMT
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = wolfSSL_4096, OU = Programming-4096, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
@ -55,47 +55,49 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:FA:54:89:67:E5:5F:B7:31:40:EA:FD:E7:F6:A3:C6:5A:56:16:A5:6E
DirName:/C=US/ST=Montana/L=Bozeman/O=wolfSSL_4096/OU=Programming-4096/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:2F:0F:AB:23:BC:A3:14:07:91:06:55:35:01:63:7F:42:BD:FB:F2:43
serial:08:23:7F:D2:D2:23:3E:0F:CC:55:94:25:1F:51:7B:E7:CC:3F:4C:AF
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
57:0d:97:98:78:bf:2a:31:9a:39:41:38:33:46:d5:50:47:e8:
19:62:a8:36:1e:b7:fd:d1:bc:50:5c:3a:eb:96:1a:9b:43:b0:
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2f:fc:ab:4a:13:12:5b:91:0a:a5:12:a2:df:61:a1:d0:a7:5a:
46:1f:b9:16:90:96:f4:86:7f:de:b4:6a:e4:cc:63:06:31:f2:
1c:c2:ba:5a:80:c7:ff:a9:01:ec:0f:26:44:69:4b:c3:a6:90:
25:e4:78:6d:91:3c:22:ac:48:25:1f:92:97:1d:aa:d2:24:60:
bf:3b:e2:35:9d:04:8f:f9:81:36:f5:ef:0e:57:8c:92:bc:0f:
3a:2a:3f:8b:81:1c:55:13:26:e1:1e:85:7f:34:c9:1e:7f:71:
62:17:6d:8d:83:4e:6e:61
-----BEGIN CERTIFICATE-----
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@ -109,22 +111,23 @@ nHc/9YAjfUO01YgKyXXXRBlNd2wLCkmqHC/WWkSmR03lNpZAmSxWJrHykjFZ1yzU
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-----END CERTIFICATE-----

BIN
certs/ca-cert.der
View File

Binary file not shown.

95
certs/ca-cert.pem
View File

@ -1,16 +1,17 @@
Certificate:
Data:
Version: 3 (0x2)
Serial Number: 9727763710660753659 (0x86fff58e10deb8fb)
Serial Number:
3f:32:13:52:92:c6:df:4a:d5:42:05:6c:b0:b2:2e:46:c2:f8:b8:67
Signature Algorithm: sha256WithRSAEncryption
Issuer: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Issuer: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Apr 13 15:23:09 2018 GMT
Not After : Jan 7 15:23:09 2021 GMT
Subject: C=US, ST=Montana, L=Bozeman, O=Sawtooth, OU=Consulting, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Montana, L = Bozeman, O = Sawtooth, OU = Consulting, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: rsaEncryption
Public-Key: (2048 bit)
RSA Public-Key: (2048 bit)
Modulus:
00:bf:0c:ca:2d:14:b2:1e:84:42:5b:cd:38:1f:4a:
f2:4d:75:10:f1:b6:35:9f:df:ca:7d:03:98:d3:ac:
@ -37,50 +38,54 @@ Certificate:
X509v3 Authority Key Identifier:
keyid:27:8E:67:11:74:C3:26:1D:3F:ED:33:63:B3:A4:D8:1D:30:E5:E8:D5
DirName:/C=US/ST=Montana/L=Bozeman/O=Sawtooth/OU=Consulting/CN=www.wolfssl.com/emailAddress=info@wolfssl.com
serial:86:FF:F5:8E:10:DE:B8:FB
serial:3F:32:13:52:92:C6:DF:4A:D5:42:05:6C:B0:B2:2E:46:C2:F8:B8:67
X509v3 Basic Constraints:
CA:TRUE
X509v3 Subject Alternative Name:
DNS:example.com, IP Address:127.0.0.1
Signature Algorithm: sha256WithRSAEncryption
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fa:7e:97:0a:6b:08:ec:a0:9f:3f:90:99:57:39:63:81:76:f7:
ed:ea:01:1d
-----BEGIN CERTIFICATE-----
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eGFtcGxlLmNvbYcEfwAAATANBgkqhkiG9w0BAQsFAAOCAQEAsHuEyR9Bl7gDFA9Z
W28sFUUbxAJv2ZLnGtzM2w5WPVnbcfLxCJoG66vFJZ/fam1ua9CokDnZSG9hf73N
7WCL42wjUreGvCr/kPdtXEdp843unnZiXHuzIuVOzib2Py+3AIwg0nH2MU7hTQO5
8wfdBKemmpywLpkKp/xZl2OlfHfdd2GmhmqyMjMGtLzKrsLHjtyF3KzC5yv7uVBr
1FsPbZOpUdLddV6IrrzKQMcr6V5bp8/i4l0LyWkg00FaerkUF/GF17kXsK3KF2w4
jXONdCUBcME0z2ICSJpW2ESkDecyoLBLxaSblWYA+n6XCmsI7KCfP5CZVzljgXb3
7eoBHQ==
-----END CERTIFICATE-----

BIN
certs/ca-ecc-cert.der
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47
certs/ca-ecc-cert.pem
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@ -1,13 +1,14 @@
Certificate:
Data:
Version: 3 (0x2)
Serial Number: 18234557164704975011 (0xfd0e292166cb48a3)
Serial Number:
43:b5:59:67:bc:60:48:29:8c:82:77:db:b5:42:36:14:e4:85:c0:3a
Signature Algorithm: ecdsa-with-SHA256
Issuer: C=US, ST=Washington, L=Seattle, O=wolfSSL, OU=Development, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Issuer: C = US, ST = Washington, L = Seattle, O = wolfSSL, OU = Development, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Validity
Not Before: Apr 13 15:23:10 2018 GMT
Not After : Jan 7 15:23:10 2021 GMT
Subject: C=US, ST=Washington, L=Seattle, O=wolfSSL, OU=Development, CN=www.wolfssl.com/emailAddress=info@wolfssl.com
Not Before: May 7 07:39:04 2020 GMT
Not After : Feb 1 07:39:04 2023 GMT
Subject: C = US, ST = Washington, L = Seattle, O = wolfSSL, OU = Development, CN = www.wolfssl.com, emailAddress = info@wolfssl.com
Subject Public Key Info:
Public Key Algorithm: id-ecPublicKey
Public-Key: (256 bit)
@ -30,23 +31,23 @@ Certificate:
X509v3 Key Usage: critical
Digital Signature, Certificate Sign, CRL Sign
Signature Algorithm: ecdsa-with-SHA256
30:46:02:21:00:f0:7b:cc:24:73:19:3f:61:68:ed:c8:0a:54:
4a:b8:ac:79:ef:10:32:91:52:2c:3e:bf:50:aa:5f:18:c1:97:
f5:02:21:00:d9:4b:63:67:6f:9b:29:a9:d7:6b:63:9b:98:9f:
32:82:36:da:f0:a9:f7:51:b4:97:aa:fa:fa:dd:ef:ef:4a:ae
30:46:02:21:00:e4:87:41:d1:d5:09:b6:97:1c:7c:1c:40:f6:
b2:a1:df:28:57:00:a3:62:2b:d8:0b:e7:f3:d4:24:56:52:62:
85:02:21:00:cd:0a:3f:60:ca:33:b5:a9:1f:4b:43:2c:60:08:
fd:3e:bd:c4:30:5c:ff:2c:d4:58:ac:77:21:c6:2e:39:d9:11
-----BEGIN CERTIFICATE-----
MIICizCCAjCgAwIBAgIJAP0OKSFmy0ijMAoGCCqGSM49BAMCMIGXMQswCQYDVQQG
EwJVUzETMBEGA1UECAwKV2FzaGluZ3RvbjEQMA4GA1UEBwwHU2VhdHRsZTEQMA4G
A1UECgwHd29sZlNTTDEUMBIGA1UECwwLRGV2ZWxvcG1lbnQxGDAWBgNVBAMMD3d3
dy53b2xmc3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTAe
Fw0xODA0MTMxNTIzMTBaFw0yMTAxMDcxNTIzMTBaMIGXMQswCQYDVQQGEwJVUzET
MBEGA1UECAwKV2FzaGluZ3RvbjEQMA4GA1UEBwwHU2VhdHRsZTEQMA4GA1UECgwH
d29sZlNTTDEUMBIGA1UECwwLRGV2ZWxvcG1lbnQxGDAWBgNVBAMMD3d3dy53b2xm
c3NsLmNvbTEfMB0GCSqGSIb3DQEJARYQaW5mb0B3b2xmc3NsLmNvbTBZMBMGByqG
SM49AgEGCCqGSM49AwEHA0IABALT2W7WAY5FyLmQMeXATOOerSk4mLoQ1ukJKoCp
LhcquYq/M4NG45UL5HdAtTtDRTMPYVN8N0TBy/yAyuhD6qejYzBhMB0GA1UdDgQW
BBRWjprD8ELeGLlFVW75k8/qw/OlITAfBgNVHSMEGDAWgBRWjprD8ELeGLlFVW75
k8/qw/OlITAPBgNVHRMBAf8EBTADAQH/MA4GA1UdDwEB/wQEAwIBhjAKBggqhkjO
PQQDAgNJADBGAiEA8HvMJHMZP2Fo7cgKVEq4rHnvEDKRUiw+v1CqXxjBl/UCIQDZ
S2Nnb5spqddrY5uYnzKCNtrwqfdRtJeq+vrd7+9Krg==
MIICljCCAjugAwIBAgIUQ7VZZ7xgSCmMgnfbtUI2FOSFwDowCgYIKoZIzj0EAwIw
gZcxCzAJBgNVBAYTAlVTMRMwEQYDVQQIDApXYXNoaW5ndG9uMRAwDgYDVQQHDAdT
ZWF0dGxlMRAwDgYDVQQKDAd3b2xmU1NMMRQwEgYDVQQLDAtEZXZlbG9wbWVudDEY
MBYGA1UEAwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdv
bGZzc2wuY29tMB4XDTIwMDUwNzA3MzkwNFoXDTIzMDIwMTA3MzkwNFowgZcxCzAJ
BgNVBAYTAlVTMRMwEQYDVQQIDApXYXNoaW5ndG9uMRAwDgYDVQQHDAdTZWF0dGxl
MRAwDgYDVQQKDAd3b2xmU1NMMRQwEgYDVQQLDAtEZXZlbG9wbWVudDEYMBYGA1UE
AwwPd3d3LndvbGZzc2wuY29tMR8wHQYJKoZIhvcNAQkBFhBpbmZvQHdvbGZzc2wu
Y29tMFkwEwYHKoZIzj0CAQYIKoZIzj0DAQcDQgAEAtPZbtYBjkXIuZAx5cBM456t
KTiYuhDW6QkqgKkuFyq5ir8zg0bjlQvkd0C1O0NFMw9hU3w3RMHL/IDK6EPqp6Nj
MGEwHQYDVR0OBBYEFFaOmsPwQt4YuUVVbvmTz+rD86UhMB8GA1UdIwQYMBaAFFaO
msPwQt4YuUVVbvmTz+rD86UhMA8GA1UdEwEB/wQFMAMBAf8wDgYDVR0PAQH/BAQD
AgGGMAoGCCqGSM49BAMCA0kAMEYCIQDkh0HR1Qm2lxx8HED2sqHfKFcAo2Ir2Avn
89QkVlJihQIhAM0KP2DKM7WpH0tDLGAI/T69xDBc/yzUWKx3IcYuOdkR
-----END CERTIFICATE-----

BIN
certs/ca-ecc384-cert.der
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