From a6b96b17ff5e2641d990dfc10fedbf2aa772ce41 Mon Sep 17 00:00:00 2001 From: David Garske Date: Wed, 15 Jun 2016 14:34:59 -0700 Subject: [PATCH] Fixes to include path for NXP ksdk_port. Fixes for time USER/OVERRIDES so their #ifdef's are checked first. Fix to initialize LTC via new "ksdk_port_init" function. Cleanup of the ksdk_port.c for formatting, macros, statics and line length. Cleanup of the AES code for key size. Cleanup of the wolfCrypt sha.c for readability. Added support for the KSDK bare metal drivers to the IDE Rowley CrossWorks example. Updated the settings.h to allow for overrides in Freescale section. Updated README with info for using LTC. --- .../Kinetis_MemoryMap.xml | 11 - IDE/ROWLEY-CROSSWORKS-ARM/README.md | 8 + IDE/ROWLEY-CROSSWORKS-ARM/arm_startup.c | 179 ++- IDE/ROWLEY-CROSSWORKS-ARM/include.am | 2 +- IDE/ROWLEY-CROSSWORKS-ARM/kinetis_hw.c | 98 +- IDE/ROWLEY-CROSSWORKS-ARM/retarget.c | 11 + IDE/ROWLEY-CROSSWORKS-ARM/user_settings.h | 16 +- IDE/ROWLEY-CROSSWORKS-ARM/wolfssl.hzp | 25 +- IDE/ROWLEY-CROSSWORKS-ARM/wolfssl_ltc.hzp | 626 +++++++++ src/internal.c | 58 +- wolfcrypt/src/aes.c | 293 ++-- wolfcrypt/src/asn.c | 40 +- wolfcrypt/src/curve25519.c | 14 +- wolfcrypt/src/ecc.c | 25 +- wolfcrypt/src/ed25519.c | 2 +- wolfcrypt/src/integer.c | 3 + wolfcrypt/src/port/nxp/ksdk_port.c | 1230 +++++++++-------- wolfcrypt/src/rsa.c | 2 +- wolfcrypt/src/sha.c | 592 ++++---- wolfcrypt/src/tfm.c | 2 +- wolfcrypt/src/wc_port.c | 8 + wolfssl/wolfcrypt/aes.h | 2 + wolfssl/wolfcrypt/port/nxp/ksdk_port.h | 25 +- wolfssl/wolfcrypt/settings.h | 49 +- 24 files changed, 2047 insertions(+), 1274 deletions(-) delete mode 100644 IDE/ROWLEY-CROSSWORKS-ARM/Kinetis_MemoryMap.xml create mode 100644 IDE/ROWLEY-CROSSWORKS-ARM/wolfssl_ltc.hzp diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/Kinetis_MemoryMap.xml b/IDE/ROWLEY-CROSSWORKS-ARM/Kinetis_MemoryMap.xml deleted file mode 100644 index 562fdb70f..000000000 --- a/IDE/ROWLEY-CROSSWORKS-ARM/Kinetis_MemoryMap.xml +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/README.md b/IDE/ROWLEY-CROSSWORKS-ARM/README.md index 9fa89a27b..4a652d7eb 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/README.md +++ b/IDE/ROWLEY-CROSSWORKS-ARM/README.md @@ -34,6 +34,14 @@ To enable Freescale MMCAU: 3. Enable the `FREESCALE_MMCAU` define in `user_settings.h` and make sure its value is `1`. 4. Add the `lib_mmcau.a` file to `Source Files` in the application project. +To enable the NXP LTC: + +1. [Download the NXP KSDK 2.0](https://nxp.flexnetoperations.com/control/frse/download?agree=Accept&element=7353807) +2. Copy the following folders into IDE/ROWLEY-CROSSWORKS-ARM: drivers, mmcau_2.0.0 and CMSIS. +3. Copy the following files into IDE/ROWLEY-CROSSWORKS-ARM: clock_config.c, clock_config.h, fsl_debug_console.c, fsl_debug_console.h, fsl_device_registers.h, system_MK82F25615.c, system_MK82F25615.h, MK82F25615.h and MK82F25615_features.h. +4. Open the wolfssl_ltc.hzp CrossWorks project +5. Build and run + # Project Files * `arm_startup.c`: Handles startup from `reset_handler`. Disabled watchdog, initializes sections, initializes heap, starts harware and starts main. diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/arm_startup.c b/IDE/ROWLEY-CROSSWORKS-ARM/arm_startup.c index 358c0f2d7..28cdce3ea 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/arm_startup.c +++ b/IDE/ROWLEY-CROSSWORKS-ARM/arm_startup.c @@ -84,6 +84,8 @@ void reset_handler(void) // Vector Exception/Interrupt Handlers static void Default_Handler(void) { + /* If we get here then need to implement real IRQ handler */ + while(1); } void HardFault_HandlerC( uint32_t *hardfault_args ) @@ -93,48 +95,48 @@ void HardFault_HandlerC( uint32_t *hardfault_args ) values of the variables, make them global my moving their declaration outside of this function. */ volatile uint32_t stacked_r0; - volatile uint32_t stacked_r1; - volatile uint32_t stacked_r2; - volatile uint32_t stacked_r3; - volatile uint32_t stacked_r12; - volatile uint32_t stacked_lr; + volatile uint32_t stacked_r1; + volatile uint32_t stacked_r2; + volatile uint32_t stacked_r3; + volatile uint32_t stacked_r12; + volatile uint32_t stacked_lr; volatile uint32_t stacked_pc; - volatile uint32_t stacked_psr; - volatile uint32_t _CFSR; - volatile uint32_t _HFSR; - volatile uint32_t _DFSR; - volatile uint32_t _AFSR; - volatile uint32_t _BFAR; - volatile uint32_t _MMAR; + volatile uint32_t stacked_psr; + volatile uint32_t _CFSR; + volatile uint32_t _HFSR; + volatile uint32_t _DFSR; + volatile uint32_t _AFSR; + volatile uint32_t _BFAR; + volatile uint32_t _MMAR; - stacked_r0 = ((uint32_t)hardfault_args[0]); - stacked_r1 = ((uint32_t)hardfault_args[1]); - stacked_r2 = ((uint32_t)hardfault_args[2]); - stacked_r3 = ((uint32_t)hardfault_args[3]); - stacked_r12 = ((uint32_t)hardfault_args[4]); - stacked_lr = ((uint32_t)hardfault_args[5]); - stacked_pc = ((uint32_t)hardfault_args[6]); - stacked_psr = ((uint32_t)hardfault_args[7]); + stacked_r0 = ((uint32_t)hardfault_args[0]); + stacked_r1 = ((uint32_t)hardfault_args[1]); + stacked_r2 = ((uint32_t)hardfault_args[2]); + stacked_r3 = ((uint32_t)hardfault_args[3]); + stacked_r12 = ((uint32_t)hardfault_args[4]); + stacked_lr = ((uint32_t)hardfault_args[5]); + stacked_pc = ((uint32_t)hardfault_args[6]); + stacked_psr = ((uint32_t)hardfault_args[7]); // Configurable Fault Status Register // Consists of MMSR, BFSR and UFSR - _CFSR = (*((volatile uint32_t *)(0xE000ED28))); - - // Hard Fault Status Register - _HFSR = (*((volatile uint32_t *)(0xE000ED2C))); + _CFSR = (*((volatile uint32_t *)(0xE000ED28))); + + // Hard Fault Status Register + _HFSR = (*((volatile uint32_t *)(0xE000ED2C))); - // Debug Fault Status Register - _DFSR = (*((volatile uint32_t *)(0xE000ED30))); + // Debug Fault Status Register + _DFSR = (*((volatile uint32_t *)(0xE000ED30))); - // Auxiliary Fault Status Register - _AFSR = (*((volatile uint32_t *)(0xE000ED3C))); + // Auxiliary Fault Status Register + _AFSR = (*((volatile uint32_t *)(0xE000ED3C))); - // Read the Fault Address Registers. These may not contain valid values. - // Check BFARVALID/MMARVALID to see if they are valid values - // MemManage Fault Address Register - _MMAR = (*((volatile uint32_t *)(0xE000ED34))); - // Bus Fault Address Register - _BFAR = (*((volatile uint32_t *)(0xE000ED38))); + // Read the Fault Address Registers. These may not contain valid values. + // Check BFARVALID/MMARVALID to see if they are valid values + // MemManage Fault Address Register + _MMAR = (*((volatile uint32_t *)(0xE000ED34))); + // Bus Fault Address Register + _BFAR = (*((volatile uint32_t *)(0xE000ED38))); printf ("\n\nHard fault handler (all numbers in hex):\n"); printf ("R0 = %x\n", stacked_r0); @@ -195,5 +197,114 @@ const vector_entry vectors[] __attribute__ ((section(".vectors"),used)) = Default_Handler, // 0x0000_0038 14 - ARM core Pendable request for system service (PendableSrvReq) Default_Handler, // 0x0000_003C 15 - ARM core System tick timer (SysTick) +#ifdef CPU_MK82FN256VLL15 // Add specific driver interrupt handlers below + Default_Handler, /* DMA0_DMA16_IRQn = 0, /**< DMA channel 0,16 transfer complete */ + Default_Handler, /* DMA1_DMA17_IRQn = 1, /**< DMA channel 1,17 transfer complete */ + Default_Handler, /* DMA2_DMA18_IRQn = 2, /**< DMA channel 2,18 transfer complete */ + Default_Handler, /* DMA3_DMA19_IRQn = 3, /**< DMA channel 3,19 transfer complete */ + Default_Handler, /* DMA4_DMA20_IRQn = 4, /**< DMA channel 4,20 transfer complete */ + Default_Handler, /* DMA5_DMA21_IRQn = 5, /**< DMA channel 5,21 transfer complete */ + Default_Handler, /* DMA6_DMA22_IRQn = 6, /**< DMA channel 6,22 transfer complete */ + Default_Handler, /* DMA7_DMA23_IRQn = 7, /**< DMA channel 7,23 transfer complete */ + Default_Handler, /* DMA8_DMA24_IRQn = 8, /**< DMA channel 8,24 transfer complete */ + Default_Handler, /* DMA9_DMA25_IRQn = 9, /**< DMA channel 9,25 transfer complete */ + Default_Handler, /* DMA10_DMA26_IRQn = 10, /**< DMA channel 10,26 transfer complete */ + Default_Handler, /* DMA11_DMA27_IRQn = 11, /**< DMA channel 11,27 transfer complete */ + Default_Handler, /* DMA12_DMA28_IRQn = 12, /**< DMA channel 12,28 transfer complete */ + Default_Handler, /* DMA13_DMA29_IRQn = 13, /**< DMA channel 13,29 transfer complete */ + Default_Handler, /* DMA14_DMA30_IRQn = 14, /**< DMA channel 14,30 transfer complete */ + Default_Handler, /* DMA15_DMA31_IRQn = 15, /**< DMA channel 15,31 transfer complete */ + Default_Handler, /* DMA_Error_IRQn = 16, /**< DMA channel 0 - 31 error */ + Default_Handler, /* MCM_IRQn = 17, /**< MCM normal interrupt */ + Default_Handler, /* FTFA_IRQn = 18, /**< FTFA command complete */ + Default_Handler, /* Read_Collision_IRQn = 19, /**< FTFA read collision */ + Default_Handler, /* LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */ + Default_Handler, /* LLWU_IRQn = 21, /**< Low leakage wakeup unit */ + Default_Handler, /* WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */ + Default_Handler, /* TRNG0_IRQn = 23, /**< True randon number generator */ + Default_Handler, /* I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */ + Default_Handler, /* I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */ + Default_Handler, /* SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */ + Default_Handler, /* SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */ + Default_Handler, /* I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */ + Default_Handler, /* I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */ + Default_Handler, /* LPUART0_IRQn = 30, /**< LPUART0 receive/transmit/error interrupt */ + Default_Handler, /* LPUART1_IRQn = 31, /**< LPUART1 receive/transmit/error interrupt */ + Default_Handler, /* LPUART2_IRQn = 32, /**< LPUART2 receive/transmit/error interrupt */ + Default_Handler, /* LPUART3_IRQn = 33, /**< LPUART3 receive/transmit/error interrupt */ + Default_Handler, /* LPUART4_IRQn = 34, /**< LPUART4 receive/transmit/error interrupt */ + Default_Handler, /* Reserved51_IRQn = 35, /**< Reserved interrupt */ + Default_Handler, /* Reserved52_IRQn = 36, /**< Reserved interrupt */ + Default_Handler, /* EMVSIM0_IRQn = 37, /**< EMVSIM0 common interrupt */ + Default_Handler, /* EMVSIM1_IRQn = 38, /**< EMVSIM1 common interrupt */ + Default_Handler, /* ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */ + Default_Handler, /* CMP0_IRQn = 40, /**< Comparator 0 */ + Default_Handler, /* CMP1_IRQn = 41, /**< Comparator 1 */ + Default_Handler, /* FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */ + Default_Handler, /* FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */ + Default_Handler, /* FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */ + Default_Handler, /* CMT_IRQn = 45, /**< Carrier modulator transmitter */ + Default_Handler, /* RTC_IRQn = 46, /**< Real time clock */ + Default_Handler, /* RTC_Seconds_IRQn = 47, /**< Real time clock seconds */ + Default_Handler, /* PIT0CH0_IRQn = 48, /**< Periodic interrupt timer 0 channel 0 */ + Default_Handler, /* PIT0CH1_IRQn = 49, /**< Periodic interrupt timer 0 channel 1 */ + Default_Handler, /* PIT0CH2_IRQn = 50, /**< Periodic interrupt timer 0 channel 2 */ + Default_Handler, /* PIT0CH3_IRQn = 51, /**< Periodic interrupt timer 0 channel 3 */ + Default_Handler, /* PDB0_IRQn = 52, /**< Programmable delay block */ + Default_Handler, /* USB0_IRQn = 53, /**< USB OTG interrupt */ + Default_Handler, /* USBDCD_IRQn = 54, /**< USB charger detect */ + Default_Handler, /* Reserved71_IRQn = 55, /**< Reserved interrupt */ + Default_Handler, /* DAC0_IRQn = 56, /**< Digital-to-analog converter 0 */ + Default_Handler, /* MCG_IRQn = 57, /**< Multipurpose clock generator */ + Default_Handler, /* LPTMR0_LPTMR1_IRQn = 58, /**< Single interrupt vector for Low Power Timer 0 and 1 */ + Default_Handler, /* PORTA_IRQn = 59, /**< Port A pin detect interrupt */ + Default_Handler, /* PORTB_IRQn = 60, /**< Port B pin detect interrupt */ + Default_Handler, /* PORTC_IRQn = 61, /**< Port C pin detect interrupt */ + Default_Handler, /* PORTD_IRQn = 62, /**< Port D pin detect interrupt */ + Default_Handler, /* PORTE_IRQn = 63, /**< Port E pin detect interrupt */ + Default_Handler, /* SWI_IRQn = 64, /**< Software interrupt */ + Default_Handler, /* SPI2_IRQn = 65, /**< Serial peripheral Interface 2 */ + Default_Handler, /* Reserved82_IRQn = 66, /**< Reserved interrupt */ + Default_Handler, /* Reserved83_IRQn = 67, /**< Reserved interrupt */ + Default_Handler, /* Reserved84_IRQn = 68, /**< Reserved interrupt */ + Default_Handler, /* Reserved85_IRQn = 69, /**< Reserved interrupt */ + Default_Handler, /* FLEXIO0_IRQn = 70, /**< FLEXIO0 */ + Default_Handler, /* FTM3_IRQn = 71, /**< FlexTimer module 3 fault, overflow and channels interrupt */ + Default_Handler, /* Reserved88_IRQn = 72, /**< Reserved interrupt */ + Default_Handler, /* Reserved89_IRQn = 73, /**< Reserved interrupt */ + Default_Handler, /* I2C2_IRQn = 74, /**< Inter-integrated circuit 2 */ + Default_Handler, /* Reserved91_IRQn = 75, /**< Reserved interrupt */ + Default_Handler, /* Reserved92_IRQn = 76, /**< Reserved interrupt */ + Default_Handler, /* Reserved93_IRQn = 77, /**< Reserved interrupt */ + Default_Handler, /* Reserved94_IRQn = 78, /**< Reserved interrupt */ + Default_Handler, /* Reserved95_IRQn = 79, /**< Reserved interrupt */ + Default_Handler, /* Reserved96_IRQn = 80, /**< Reserved interrupt */ + Default_Handler, /* SDHC_IRQn = 81, /**< Secured digital host controller */ + Default_Handler, /* Reserved98_IRQn = 82, /**< Reserved interrupt */ + Default_Handler, /* Reserved99_IRQn = 83, /**< Reserved interrupt */ + Default_Handler, /* Reserved100_IRQn = 84, /**< Reserved interrupt */ + Default_Handler, /* Reserved101_IRQn = 85, /**< Reserved interrupt */ + Default_Handler, /* Reserved102_IRQn = 86, /**< Reserved interrupt */ + Default_Handler, /* TSI0_IRQn = 87, /**< Touch Sensing Input */ + Default_Handler, /* TPM1_IRQn = 88, /**< TPM1 single interrupt vector for all sources */ + Default_Handler, /* TPM2_IRQn = 89, /**< TPM2 single interrupt vector for all sources */ + Default_Handler, /* Reserved106_IRQn = 90, /**< Reserved interrupt */ + Default_Handler, /* I2C3_IRQn = 91, /**< Inter-integrated circuit 3 */ + Default_Handler, /* Reserved108_IRQn = 92, /**< Reserved interrupt */ + Default_Handler, /* Reserved109_IRQn = 93, /**< Reserved interrupt */ + Default_Handler, /* Reserved110_IRQn = 94, /**< Reserved interrupt */ + Default_Handler, /* Reserved111_IRQn = 95, /**< Reserved interrupt */ + Default_Handler, /* Reserved112_IRQn = 96, /**< Reserved interrupt */ + Default_Handler, /* Reserved113_IRQn = 97, /**< Reserved interrupt */ + Default_Handler, /* Reserved114_IRQn = 98, /**< Reserved interrupt */ + Default_Handler, /* Reserved115_IRQn = 99, /**< Reserved interrupt */ + Default_Handler, /* QuadSPI0_IRQn = 100, /**< qspi */ + Default_Handler, /* Reserved117_IRQn = 101, /**< Reserved interrupt */ + Default_Handler, /* Reserved118_IRQn = 102, /**< Reserved interrupt */ + Default_Handler, /* Reserved119_IRQn = 103, /**< Reserved interrupt */ + Default_Handler, /* LTC0_IRQn = 104, /**< LP Trusted Cryptography */ + Default_Handler, /* Reserved121_IRQn = 105, /**< Reserved interrupt */ + Default_Handler, /* Reserved122_IRQn = 106 /**< Reserved interrupt */ +#endif /* CPU_MK82FN256VLL15 */ }; diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/include.am b/IDE/ROWLEY-CROSSWORKS-ARM/include.am index e812cc7e6..c58c76192 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/include.am +++ b/IDE/ROWLEY-CROSSWORKS-ARM/include.am @@ -6,10 +6,10 @@ EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/arm_startup.c EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/benchmark_main.c EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/hw.h EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/kinetis_hw.c -EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/Kinetis_MemoryMap.xml EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/Kinetis_FlashPlacement.xml EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/README.md EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/test_main.c EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/retarget.c EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/user_settings.h EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/wolfssl.hzp +EXTRA_DIST+= IDE/ROWLEY-CROSSWORKS-ARM/wolfssl_ltc.hzp diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/kinetis_hw.c b/IDE/ROWLEY-CROSSWORKS-ARM/kinetis_hw.c index 961e181d8..35b62fd41 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/kinetis_hw.c +++ b/IDE/ROWLEY-CROSSWORKS-ARM/kinetis_hw.c @@ -21,10 +21,10 @@ #include "hw.h" +#include "user_settings.h" #if defined(FREESCALE) && defined(K_SERIES) - /********************************************** * NOTE: Customize for actual hardware **********************************************/ @@ -33,27 +33,53 @@ // $(TargetsDir) location: // On Mac OS/X: Users/USERNAME/Library/Rowley Associates Limited/CrossWorks for ARM/packages/targets/ // On Windows: C:/Users/USERNAME/Application Data/Local/Rowley Associates Limited/CrossWorks for ARM/packages/targets/ -#include // Located in $(TargetsDir)/Kinetis/CMSIS/ + +// Located in $(TargetsDir)/Kinetis/CMSIS/ +#ifdef FREESCALE_KSDK_BM + #include "fsl_common.h" + #include "fsl_debug_console.h" + #include "fsl_rtc.h" + #include "fsl_trng.h" + #include "fsl_lpuart.h" + #include "fsl_port.h" + #include "clock_config.h" +#else + #include // Located in $(TargetsDir)/Kinetis/CMSIS/ +#endif + // System clock -#define SYS_CLK_KHZ 96000ul /* Core system clock in KHz */ -#define SYS_CLK_DRS MCG_C4_DRST_DRS(0x03) /* DRS 0=24MHz, 1=48MHz, 2=72MHz, 3=96MHz */ -#define SYS_CLK_DMX MCG_C4_DMX32_MASK /* 0=Disable DMX32 (lower actual speed), MCG_C4_DMX32_MASK=Enable DMX32 */ -#define SYS_CLK_DIV 1 /* System clock divisor */ -#define BUS_CLK_DIV 2 /* Bus clock divisor */ -#define BUS_CLK_KHZ (SYS_CLK_KHZ/BUS_CLK_DIV) /* Helper to calculate bus speed for UART */ -#define FLASH_CLK_DIV 4 /* Flash clock divisor */ +#ifdef FREESCALE_KSDK_BM + #define SYS_CLK_HZ SystemCoreClock +#else + #define SYS_CLK_HZ 96000000ul /* Core system clock in Hz */ + #define SYS_CLK_DRS MCG_C4_DRST_DRS(0x03) /* DRS 0=24MHz, 1=48MHz, 2=72MHz, 3=96MHz */ + #define SYS_CLK_DMX MCG_C4_DMX32_MASK /* 0=Disable DMX32 (lower actual speed), MCG_C4_DMX32_MASK=Enable DMX32 */ + #define SYS_CLK_DIV 1 /* System clock divisor */ + #define BUS_CLK_DIV 2 /* Bus clock divisor */ + #define BUS_CLK_KHZ (SYS_CLK_HZ/BUS_CLK_DIV) /* Helper to calculate bus speed for UART */ + #define FLASH_CLK_DIV 4 /* Flash clock divisor */ +#endif // UART TX Port, Pin, Mux and Baud -#define UART_PORT UART4 /* UART Port */ -#define UART_TX_PORT PORTE /* UART TX Port */ -#define UART_TX_PIN 24 /* UART TX Pin */ -#define UART_TX_MUX 0x3 /* Kinetis UART pin mux */ -#define UART_BAUD 115200 /* UART Baud Rate */ +#ifdef FREESCALE_KSDK_BM + #define UART_PORT LPUART0 /* UART Port */ + #define UART_TX_PORT PORTA /* UART TX Port */ + #define UART_TX_PIN 2U /* UART TX Pin */ + #define UART_TX_MUX kPORT_MuxAlt2 /* Kinetis UART pin mux */ +#else + #define UART_PORT UART4 /* UART Port */ + #define UART_TX_PORT PORTE /* UART TX Port */ + #define UART_TX_PIN 24U /* UART TX Pin */ + #define UART_TX_MUX 0x3 /* Kinetis UART pin mux */ +#endif +#define UART_BAUD 115200 /* UART Baud Rate */ + /* Note: You will also need to update the UART clock gate in hw_uart_init (SIM_SCGC1_UART5_MASK) */ /* Note: TWR-K60 is UART3, PTC17 */ /* Note: FRDM-K64 is UART4, PTE24 */ /* Note: TWR-K64 is UART5, PTE8 */ +/* Note: FRDM-K82F is LPUART0 A2, LPUART4 PTC15 */ /***********************************************/ @@ -70,6 +96,9 @@ static void delay_nop(uint32_t count) static void hw_mcg_init(void) { +#ifdef FREESCALE_KSDK_BM + BOARD_BootClockHSRUN(); +#else /* Adjust clock dividers (core/system=div/1, bus=div/2, flex bus=div/2, flash=div/4) */ SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(SYS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV2(BUS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV3(BUS_CLK_DIV-1) | SIM_CLKDIV1_OUTDIV4(FLASH_CLK_DIV-1); @@ -77,10 +106,18 @@ static void hw_mcg_init(void) /* Configure FEI internal clock speed */ MCG->C4 = (SYS_CLK_DMX | SYS_CLK_DRS); while((MCG->C4 & (MCG_C4_DRST_DRS_MASK | MCG_C4_DMX32_MASK)) != (SYS_CLK_DMX | SYS_CLK_DRS)); +#endif } static void hw_gpio_init(void) { +#ifdef FREESCALE_KSDK_BM + CLOCK_EnableClock(kCLOCK_PortA); + CLOCK_EnableClock(kCLOCK_PortB); + CLOCK_EnableClock(kCLOCK_PortC); + CLOCK_EnableClock(kCLOCK_PortD); + CLOCK_EnableClock(kCLOCK_PortE); +#else /* Enable clocks to all GPIO ports */ SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK #ifdef SIM_SCGC5_PORTC_MASK @@ -93,6 +130,7 @@ static void hw_gpio_init(void) | SIM_SCGC5_PORTE_MASK #endif ); +#endif } static void hw_uart_init(void) @@ -100,7 +138,13 @@ static void hw_uart_init(void) register uint16_t sbr, brfa; uint8_t temp; +#ifdef FREESCALE_KSDK_BM + PORT_SetPinMux(UART_TX_PORT, UART_TX_PIN, UART_TX_MUX); + CLOCK_SetLpuartClock(1); /* MCGPLLCLK */ + DbgConsole_Init((uint32_t)UART_PORT, UART_BAUD, DEBUG_CONSOLE_DEVICE_TYPE_LPUART, SYS_CLK_HZ); +#else /* Enable UART core clock */ + /* Note: Remember to update me if UART_PORT changes */ SIM->SCGC1 |= SIM_SCGC1_UART4_MASK; /* Configure UART TX pin */ @@ -125,12 +169,13 @@ static void hw_uart_init(void) /* Enable receiver and transmitter */ UART_PORT->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK); +#endif } static void hw_rtc_init(void) { /* Init nop delay */ - mDelayCyclesPerUs = (SYS_CLK_KHZ / 1000 / NOP_FOR_LOOP_INSTRUCTION_COUNT); + mDelayCyclesPerUs = (SYS_CLK_HZ / 1000000 / NOP_FOR_LOOP_INSTRUCTION_COUNT); /* Enable RTC clock and oscillator */ SIM->SCGC6 |= SIM_SCGC6_RTC_MASK; @@ -145,7 +190,7 @@ static void hw_rtc_init(void) } /* Disable RTC Interrupts */ - RTC_IER = 0; + RTC->IER = 0; /* Enable OSC */ if ((RTC->CR & RTC_CR_OSCE_MASK) == 0) { @@ -164,6 +209,14 @@ static void hw_rtc_init(void) static void hw_rand_init(void) { +#ifdef FREESCALE_KSDK_BM + trng_config_t trngConfig; + TRNG_GetDefaultConfig(&trngConfig); + /* Set sample mode of the TRNG ring oscillator to Von Neumann, for better random data.*/ + trngConfig.sampleMode = kTRNG_SampleModeVonNeumann; + /* Initialize TRNG */ + TRNG_Init(TRNG0, &trngConfig); +#else /* Enable RNG clocks */ SIM->SCGC6 |= SIM_SCGC6_RNGA_MASK; SIM->SCGC3 |= SIM_SCGC3_RNGA_MASK; @@ -176,6 +229,7 @@ static void hw_rand_init(void) /* Enable RNG generation to RANDOUT FIFO */ RNG->CR |= RNG_CR_GO_MASK; +#endif } @@ -204,14 +258,24 @@ uint32_t hw_get_time_msec(void) void hw_uart_printchar(int c) { +#ifdef FREESCALE_KSDK_BM + LPUART_WriteBlocking(UART_PORT, (const uint8_t*)&c, 1); /* Send the character */ +#else while(!(UART_PORT->S1 & UART_S1_TDRE_MASK)); /* Wait until space is available in the FIFO */ UART_PORT->D = (uint8_t)c; /* Send the character */ +#endif } uint32_t hw_rand(void) { + uint32_t rng; +#ifdef FREESCALE_KSDK_BM + TRNG_GetRandomData(TRNG0, &rng, sizeof(rng)); +#else while((RNG->SR & RNG_SR_OREG_LVL(0xF)) == 0) {}; /* Wait until FIFO has a value available */ - return RNG->OR; /* Return next value in FIFO output register */ + rng = RNG->OR; /* Return next value in FIFO output register */ +#endif + return rng; } void delay_us(uint32_t microseconds) diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/retarget.c b/IDE/ROWLEY-CROSSWORKS-ARM/retarget.c index 6a4dac38f..958316381 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/retarget.c +++ b/IDE/ROWLEY-CROSSWORKS-ARM/retarget.c @@ -22,6 +22,17 @@ #include "hw.h" #include "user_settings.h" +#include + +void __assert(const char *__expression, const char *__filename, int __line) +{ + printf("Assert: %s, File %s (%d)\n", __expression, __filename, __line); +} + +unsigned int LowResTimer(void) +{ + return hw_get_time_sec(); +} double current_time(int reset) { diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/user_settings.h b/IDE/ROWLEY-CROSSWORKS-ARM/user_settings.h index f8d751ff0..048de56d5 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/user_settings.h +++ b/IDE/ROWLEY-CROSSWORKS-ARM/user_settings.h @@ -140,7 +140,7 @@ extern "C" { /* Ed25519 / Curve25519 */ #undef HAVE_CURVE25519 #undef HAVE_ED25519 -#if 0 +#if 1 #define HAVE_CURVE25519 #define HAVE_ED25519 @@ -196,7 +196,18 @@ extern "C" { /* HW Crypto Acceleration */ /* ------------------------------------------------------------------------- */ // See README.md for instructions -//#define FREESCALE_MMCAU 1 +#if 0 + #define FREESCALE_MMCAU 1 +#endif + +/* NXP LTC Support (See README.md for instructions) */ +#if 0 + #define FSL_HW_CRYPTO_MANUAL_SELECTION + #define FREESCALE_USE_MMCAU + #define FREESCALE_USE_LTC + #define LTC_MAX_ECC_BITS (512) + #define LTC_MAX_INT_BYTES (256) +#endif /* ------------------------------------------------------------------------- */ @@ -243,6 +254,7 @@ extern "C" { /* Override Current Time */ /* Allows custom "custom_time()" function to be used for benchmark */ #define WOLFSSL_USER_CURRTIME +#define USER_TICKS /* ------------------------------------------------------------------------- */ diff --git a/IDE/ROWLEY-CROSSWORKS-ARM/wolfssl.hzp b/IDE/ROWLEY-CROSSWORKS-ARM/wolfssl.hzp index 74a4eeaff..ad5c68af8 100644 --- a/IDE/ROWLEY-CROSSWORKS-ARM/wolfssl.hzp +++ b/IDE/ROWLEY-CROSSWORKS-ARM/wolfssl.hzp @@ -83,6 +83,9 @@ + @@ -140,6 +143,8 @@ arm_target_loader_default_loader="Flash" c_preprocessor_definitions="WOLFSSL_ROWLEY_ARM;WOLFSSL_USER_SETTINGS" c_user_include_directories=".;../;../../;$(TargetsDir);$(TargetsDir)/Kinetis;$(TargetsDir)/Kinetis/CMSIS;$(TargetsDir)/Kinetis/CMSIS/include;$(TargetsDir)/CMSIS_3/CMSIS/include" + debug_register_definition_file="$(TargetsDir)/Kinetis/MK64F12_Peripherals.xml" + linker_memory_map_file="$(TargetsDir)/Kinetis/MK64FN1M0xxx12_MemoryMap.xml" linker_memory_map_macros="FLASHSIZE=0x80000;SRAMSIZE=0x20000" linker_output_format="bin" project_dependencies="libwolfssl" @@ -161,7 +166,6 @@ - @@ -169,16 +173,21 @@ Name="Common" Placement="Flash" Target="MK64FN1M0xxx12" + arm_architecture="v7EM" + arm_core_type="Cortex-M4" + arm_fpu_type="FPv4-SP-D16" arm_linker_fiq_stack_size="0" arm_linker_heap_size="91136" arm_linker_irq_stack_size="0" arm_linker_stack_size="30720" arm_simulator_memory_simulation_filename="$(TargetsDir)/Kinetis/KinetisSimulatorMemory.dll" - arm_simulator_memory_simulation_parameter="MK64FN1M0xxx12;0x100000;0x0;0x0;0x40000" + arm_simulator_memory_simulation_parameter="MK64FN1M0xxx12;0x100000;0x0;0x0;0x40000;4" arm_target_loader_applicable_loaders="Flash" arm_target_loader_default_loader="Flash" c_preprocessor_definitions="WOLFSSL_ROWLEY_ARM;WOLFSSL_USER_SETTINGS" c_user_include_directories=".;../;../../;$(TargetsDir);$(TargetsDir)/Kinetis;$(TargetsDir)/Kinetis/CMSIS;$(TargetsDir)/Kinetis/CMSIS/include;$(TargetsDir)/CMSIS_3/CMSIS/include" + debug_register_definition_file="$(TargetsDir)/Kinetis/MK64F12_Peripherals.xml" + linker_memory_map_file="$(TargetsDir)/Kinetis/MK64FN1M0xxx12_MemoryMap.xml" linker_memory_map_macros="FLASHSIZE=0x80000;SRAMSIZE=0x20000" linker_output_format="bin" project_dependencies="libwolfssl" @@ -200,8 +209,11 @@ - +