diff --git a/.gitignore b/.gitignore
index 3f73f167e..c93a89b30 100644
--- a/.gitignore
+++ b/.gitignore
@@ -81,3 +81,8 @@ cov-int
cyassl.tgz
*.log
*.trs
+IDE\MDK-ARM\Projects/
+IDE\MDK-ARM\STM32F2xx_StdPeriph_Lib/inc
+IDE\MDK-ARM\STM32F2xx_StdPeriph_Lib/src
+IDE\MDK-ARM\LPC43xx\Drivers/
+IDE\MDK-ARM\LPC43xx\LPC43xx/
diff --git a/IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s b/IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s
new file mode 100644
index 000000000..6fdb7ab70
--- /dev/null
+++ b/IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s
@@ -0,0 +1,338 @@
+;/***********************************************************************
+; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
+; *
+; * Project: LPC43xx CMSIS Package
+; *
+; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx
+; * Device Series.
+; *
+; * Copyright(C) 2011, NXP Semiconductor
+; * All rights reserved.
+; *
+; * modified by KEIL
+; ***********************************************************************
+; * Software that is described herein is for illustrative purposes only
+; * which provides customers with programming information regarding the
+; * products. This software is supplied "AS IS" without any warranties.
+; * NXP Semiconductors assumes no responsibility or liability for the
+; * use of the software, conveys no license or title under any patent,
+; * copyright, or mask work right to the product. NXP Semiconductors
+; * reserves the right to make changes in the software without
+; * notification. NXP Semiconductors also make no representation or
+; * warranty that such application will be suitable for the specified
+; * use without further testing or modification.
+; **********************************************************************/
+
+; Stack Configuration
+; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Stack_Size EQU 0x00003000
+
+ AREA STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem SPACE Stack_Size
+__initial_sp
+
+
+; Heap Configuration
+; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+;
+
+Heap_Size EQU 0x0000a000
+
+ AREA HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem SPACE Heap_Size
+__heap_limit
+
+ PRESERVE8
+ THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+
+Sign_Value EQU 0x5A5A5A5A
+
+__Vectors DCD __initial_sp ; 0 Top of Stack
+ DCD Reset_Handler ; 1 Reset Handler
+ DCD NMI_Handler ; 2 NMI Handler
+ DCD HardFault_Handler ; 3 Hard Fault Handler
+ DCD MemManage_Handler ; 4 MPU Fault Handler
+ DCD BusFault_Handler ; 5 Bus Fault Handler
+ DCD UsageFault_Handler ; 6 Usage Fault Handler
+ DCD Sign_Value ; 7 Reserved
+ DCD 0 ; 8 Reserved
+ DCD 0 ; 9 Reserved
+ DCD 0 ; 10 Reserved
+ DCD SVC_Handler ; 11 SVCall Handler
+ DCD DebugMon_Handler ; 12 Debug Monitor Handler
+ DCD 0 ; 13 Reserved
+ DCD PendSV_Handler ; 14 PendSV Handler
+ DCD SysTick_Handler ; 15 SysTick Handler
+
+ ; External Interrupts
+ DCD DAC_IRQHandler ; 16 D/A Converter
+ DCD M0CORE_IRQHandler ; 17 M0 Core
+ DCD DMA_IRQHandler ; 18 General Purpose DMA
+ DCD EZH_IRQHandler ; 19 EZH/EDM
+ DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
+ DCD ETH_IRQHandler ; 21 Ethernet
+ DCD SDIO_IRQHandler ; 22 SD/MMC
+ DCD LCD_IRQHandler ; 23 LCD
+ DCD USB0_IRQHandler ; 24 USB0
+ DCD USB1_IRQHandler ; 25 USB1
+ DCD SCT_IRQHandler ; 26 State Configurable Timer
+ DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
+ DCD TIMER0_IRQHandler ; 28 Timer0
+ DCD TIMER1_IRQHandler ; 29 Timer1
+ DCD TIMER2_IRQHandler ; 30 Timer2
+ DCD TIMER3_IRQHandler ; 31 Timer3
+ DCD MCPWM_IRQHandler ; 32 Motor Control PWM
+ DCD ADC0_IRQHandler ; 33 A/D Converter 0
+ DCD I2C0_IRQHandler ; 34 I2C0
+ DCD I2C1_IRQHandler ; 35 I2C1
+ DCD SPI_IRQHandler ; 36 SPI
+ DCD ADC1_IRQHandler ; 37 A/D Converter 1
+ DCD SSP0_IRQHandler ; 38 SSP0
+ DCD SSP1_IRQHandler ; 39 SSP1
+ DCD UART0_IRQHandler ; 40 UART0
+ DCD UART1_IRQHandler ; 41 UART1
+ DCD UART2_IRQHandler ; 42 UART2
+ DCD UART3_IRQHandler ; 43 UART3
+ DCD I2S0_IRQHandler ; 44 I2S0
+ DCD I2S1_IRQHandler ; 45 I2S1
+ DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
+ DCD SGPIO_IRQHandler ; 47 SGPIO
+ DCD GPIO0_IRQHandler ; 48 GPIO0
+ DCD GPIO1_IRQHandler ; 49 GPIO1
+ DCD GPIO2_IRQHandler ; 50 GPIO2
+ DCD GPIO3_IRQHandler ; 51 GPIO3
+ DCD GPIO4_IRQHandler ; 52 GPIO4
+ DCD GPIO5_IRQHandler ; 53 GPIO5
+ DCD GPIO6_IRQHandler ; 54 GPIO6
+ DCD GPIO7_IRQHandler ; 55 GPIO7
+ DCD GINT0_IRQHandler ; 56 GINT0
+ DCD GINT1_IRQHandler ; 57 GINT1
+ DCD EVRT_IRQHandler ; 58 Event Router
+ DCD CAN1_IRQHandler ; 59 C_CAN1
+ DCD 0 ; 60 Reserved
+ DCD VADC_IRQHandler ; 61 VADC
+ DCD ATIMER_IRQHandler ; 62 ATIMER
+ DCD RTC_IRQHandler ; 63 RTC
+ DCD 0 ; 64 Reserved
+ DCD WDT_IRQHandler ; 65 WDT
+ DCD M0s_IRQHandler ; 66 M0s
+ DCD CAN0_IRQHandler ; 67 C_CAN0
+ DCD QEI_IRQHandler ; 68 QEI
+
+
+;CRP address at offset 0x2FC relative to the BOOT Bank address
+ IF :LNOT::DEF:NO_CRP
+ SPACE (0x2FC - (. - __Vectors))
+; EXPORT CRP_Key
+CRP_Key DCD 0xFFFFFFFF
+; 0xFFFFFFFF => CRP Disabled
+; 0x12345678 => CRP Level 1
+; 0x87654321 => CRP Level 2
+; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
+; 0x4E697370 => NO ISP (ARE YOU SURE?)
+ ENDIF
+
+ AREA |.text|, CODE, READONLY
+
+; Reset Handler
+
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT DAC_IRQHandler [WEAK]
+ EXPORT M0CORE_IRQHandler [WEAK]
+ EXPORT DMA_IRQHandler [WEAK]
+ EXPORT EZH_IRQHandler [WEAK]
+ EXPORT FLASH_EEPROM_IRQHandler [WEAK]
+ EXPORT ETH_IRQHandler [WEAK]
+ EXPORT SDIO_IRQHandler [WEAK]
+ EXPORT LCD_IRQHandler [WEAK]
+ EXPORT USB0_IRQHandler [WEAK]
+ EXPORT USB1_IRQHandler [WEAK]
+ EXPORT SCT_IRQHandler [WEAK]
+ EXPORT RIT_IRQHandler [WEAK]
+ EXPORT TIMER0_IRQHandler [WEAK]
+ EXPORT TIMER1_IRQHandler [WEAK]
+ EXPORT TIMER2_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT MCPWM_IRQHandler [WEAK]
+ EXPORT ADC0_IRQHandler [WEAK]
+ EXPORT I2C0_IRQHandler [WEAK]
+ EXPORT I2C1_IRQHandler [WEAK]
+ EXPORT SPI_IRQHandler [WEAK]
+ EXPORT ADC1_IRQHandler [WEAK]
+ EXPORT SSP0_IRQHandler [WEAK]
+ EXPORT SSP1_IRQHandler [WEAK]
+ EXPORT UART0_IRQHandler [WEAK]
+ EXPORT UART1_IRQHandler [WEAK]
+ EXPORT UART2_IRQHandler [WEAK]
+ EXPORT UART3_IRQHandler [WEAK]
+ EXPORT I2S0_IRQHandler [WEAK]
+ EXPORT I2S1_IRQHandler [WEAK]
+ EXPORT SPIFI_IRQHandler [WEAK]
+ EXPORT SGPIO_IRQHandler [WEAK]
+ EXPORT GPIO0_IRQHandler [WEAK]
+ EXPORT GPIO1_IRQHandler [WEAK]
+ EXPORT GPIO2_IRQHandler [WEAK]
+ EXPORT GPIO3_IRQHandler [WEAK]
+ EXPORT GPIO4_IRQHandler [WEAK]
+ EXPORT GPIO5_IRQHandler [WEAK]
+ EXPORT GPIO6_IRQHandler [WEAK]
+ EXPORT GPIO7_IRQHandler [WEAK]
+ EXPORT GINT0_IRQHandler [WEAK]
+ EXPORT GINT1_IRQHandler [WEAK]
+ EXPORT EVRT_IRQHandler [WEAK]
+ EXPORT CAN1_IRQHandler [WEAK]
+ EXPORT VADC_IRQHandler [WEAK]
+ EXPORT ATIMER_IRQHandler [WEAK]
+ EXPORT RTC_IRQHandler [WEAK]
+ EXPORT WDT_IRQHandler [WEAK]
+ EXPORT M0s_IRQHandler [WEAK]
+ EXPORT CAN0_IRQHandler [WEAK]
+ EXPORT QEI_IRQHandler [WEAK]
+
+DAC_IRQHandler
+M0CORE_IRQHandler
+DMA_IRQHandler
+EZH_IRQHandler
+FLASH_EEPROM_IRQHandler
+ETH_IRQHandler
+SDIO_IRQHandler
+LCD_IRQHandler
+USB0_IRQHandler
+USB1_IRQHandler
+SCT_IRQHandler
+RIT_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+TIMER3_IRQHandler
+MCPWM_IRQHandler
+ADC0_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI_IRQHandler
+ADC1_IRQHandler
+SSP0_IRQHandler
+SSP1_IRQHandler
+UART0_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+UART3_IRQHandler
+I2S0_IRQHandler
+I2S1_IRQHandler
+SPIFI_IRQHandler
+SGPIO_IRQHandler
+GPIO0_IRQHandler
+GPIO1_IRQHandler
+GPIO2_IRQHandler
+GPIO3_IRQHandler
+GPIO4_IRQHandler
+GPIO5_IRQHandler
+GPIO6_IRQHandler
+GPIO7_IRQHandler
+GINT0_IRQHandler
+GINT1_IRQHandler
+EVRT_IRQHandler
+CAN1_IRQHandler
+VADC_IRQHandler
+ATIMER_IRQHandler
+RTC_IRQHandler
+WDT_IRQHandler
+M0s_IRQHandler
+CAN0_IRQHandler
+QEI_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+; User Initial Stack & Heap
+
+ IF :DEF:__MICROLIB
+
+ EXPORT __initial_sp
+ EXPORT __heap_base
+ EXPORT __heap_limit
+
+ ELSE
+
+ IMPORT __use_two_region_memory
+ EXPORT __user_initial_stackheap
+__user_initial_stackheap
+
+ LDR R0, = Heap_Mem
+ LDR R1, =(Stack_Mem + Stack_Size)
+ LDR R2, = (Heap_Mem + Heap_Size)
+ LDR R3, = Stack_Mem
+ BX LR
+
+ ALIGN
+
+ ENDIF
+
+
+ END
diff --git a/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c b/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c
new file mode 100644
index 000000000..4efaf2746
--- /dev/null
+++ b/IDE/MDK-ARM/LPC43xx/time-LCP43xx.c
@@ -0,0 +1,170 @@
+/* time.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+ #include
+#endif
+
+
+/*-----------------------------------------------------------------------------
+ * initialize RTC
+ *----------------------------------------------------------------------------*/
+#include
+#include "lpc43xx_rtc.h"
+#include "lpc43xx_cgu.h"
+
+static void init_RTC()
+{
+ /* Enable GPIO register interface clock */
+ LPC_CCU1->CLK_M4_GPIO_CFG |= 1;
+ while (!(LPC_CCU1->CLK_M4_GPIO_STAT & 1)) ;
+
+ /* RTC Block section ------------------------------------------------------ */
+ /* Init RTC module */
+ RTC_Init(LPC_RTC);
+
+ /* Set ALARM time for second */
+ RTC_SetAlarmTime (LPC_RTC, RTC_TIMETYPE_SECOND, 30);
+
+ /* Set the AMR for 30s match alarm interrupt */
+ RTC_AlarmIntConfig (LPC_RTC, RTC_TIMETYPE_SECOND, ENABLE);
+
+ /* Set the CIIR for minute counter interrupt*/
+ RTC_CntIncrIntConfig (LPC_RTC, RTC_TIMETYPE_MINUTE, ENABLE);
+
+ /* Enable rtc (starts increase the tick counter and second counter register) */
+ RTC_Cmd(LPC_RTC, ENABLE);
+
+}
+
+/*-----------------------------------------------------------------------------
+ * initialize TIM
+ *----------------------------------------------------------------------------*/
+
+#include "lpc43xx_timer.h"
+//#include "lpc43xx_cgu.h"
+//#include "lpc43xx_scu.h"
+//#include "lpc43xx_libcfg.h"
+//#include "debug_frmwrk.h"
+
+static void init_TIM()
+{
+ TIM_TIMERCFG_Type TIM_ConfigStruct;
+ /* Initialize timer 0, prescale count time of 1uS */
+ TIM_ConfigStruct.PrescaleOption = TIM_PRESCALE_TICKVAL;
+ TIM_ConfigStruct.PrescaleValue = 204; /* 204MHz */
+ /* Set configuration for Tim_config and Tim_MatchConfig */
+ TIM_Init(LPC_TIMER2, TIM_TIMER_MODE,&TIM_ConfigStruct);
+ TIM_ResetCounter(LPC_TIMER2);
+ /* To start timer 2 */
+ TIM_Cmd(LPC_TIMER2,ENABLE);
+}
+
+double current_time()
+{
+ return (double)LPC_TIMER2->TC/1000000.0;
+}
+
+
+void init_time(void) {
+ init_RTC() ;
+ init_TIM() ;
+}
+
+#include
+
+struct tm *Cyassl_MDK_gmtime(const time_t *c)
+{
+ static struct tm date ;
+
+ RTC_TIME_Type RTCFullTime;
+ RTC_GetFullTime (LPC_RTC, &RTCFullTime);
+
+ date.tm_year = RTCFullTime.YEAR + 100 ;
+ date.tm_mon = RTCFullTime.MONTH - 1 ;
+ date.tm_mday = RTCFullTime.DOM ;
+ date.tm_hour = RTCFullTime.HOUR ;
+ date.tm_min = RTCFullTime.MIN ;
+ date.tm_sec = RTCFullTime.SEC ;
+
+ #if defined(DEBUG_CYASSL)
+ {
+ extern void CYASSL_MSG(char *msg) ;
+ char msg[100] ;
+ sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n",
+ RTCFullTime.YEAR+2000, RTCFullTime.MONTH, RTCFullTime.DOM,
+ RTCFullTime.HOUR, RTCFullTime.MIN, RTCFullTime.SEC) ;
+ CYASSL_MSG(msg) ;
+ }
+ #endif
+
+ return(&date) ;
+}
+
+typedef struct func_args {
+ int argc;
+ char** argv;
+ int return_code;
+} func_args;
+
+#include
+
+void time_main(void *args)
+{
+ char * datetime ;
+ int year ;
+ RTC_TIME_Type RTCFullTime;
+
+ if( args == NULL || ((func_args *)args)->argc == 1) {
+ RTC_GetFullTime (LPC_RTC, &RTCFullTime);
+ printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
+ RTCFullTime.MONTH, RTCFullTime.DOM, RTCFullTime.YEAR+2000,
+ RTCFullTime.HOUR, RTCFullTime.MIN, RTCFullTime.SEC) ;
+ } else if(((func_args *)args)->argc == 3 &&
+ ((func_args *)args)->argv[1][0] == '-' &&
+ ((func_args *)args)->argv[1][1] == 'd' ) {
+
+ datetime = ((func_args *)args)->argv[2];
+ sscanf(datetime, "%d/%d/%d",
+ (int *)&RTCFullTime.MONTH, (int *)&RTCFullTime.DOM, &year) ;
+ RTCFullTime.YEAR = year - 2000 ;
+ RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MONTH, RTCFullTime.MONTH);
+ RTC_SetTime (LPC_RTC, RTC_TIMETYPE_YEAR, RTCFullTime.YEAR);
+ RTC_SetTime (LPC_RTC, RTC_TIMETYPE_DAYOFMONTH, RTCFullTime.DOM);
+ } else if(((func_args *)args)->argc == 3 &&
+ ((func_args *)args)->argv[1][0] == '-' &&
+ ((func_args *)args)->argv[1][1] == 't' ) {
+ RTC_GetFullTime (LPC_RTC, &RTCFullTime);
+ datetime = ((func_args *)args)->argv[2];
+ sscanf(datetime, "%d:%d:%d",
+ (int *)&RTCFullTime.HOUR,
+ (int *)&RTCFullTime.MIN,
+ (int *)&RTCFullTime.SEC
+ ) ;
+ RTC_SetTime (LPC_RTC, RTC_TIMETYPE_SECOND, RTCFullTime.SEC);
+ RTC_SetTime (LPC_RTC, RTC_TIMETYPE_MINUTE, RTCFullTime.MIN);
+ RTC_SetTime (LPC_RTC, RTC_TIMETYPE_HOUR, RTCFullTime.HOUR);
+ } else printf("Invalid argument\n") ;
+}
+
+
+
+
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h
index 680bdaf38..a88e1bca4 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-BARE-METAL.h
@@ -78,7 +78,7 @@
// STM32 Hardware Crypt
// STM32F2 Hardware RNG
-#define MDK_CONF_STM32F2_RNG 1
+#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h
index a1eb9ea7d..ed2e6d642 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h
@@ -76,7 +76,7 @@
// STM32 Hardware Crypt
// STM32F2 Hardware RNG
-#define MDK_CONF_STM32F2_RNG 1
+#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h
index cd0ff5717..5a424e0df 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h
@@ -99,7 +99,7 @@
//
// STM32 Hardware Crypt
// STM32F2 Hardware RNG
-#define MDK_CONF_STM32F2_RNG 1
+#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c
index 718919b63..f0959de12 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c
@@ -59,7 +59,7 @@ unsigned long inet_addr(const char *cp)
/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/
int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
{
- int ret ;
+ int ret = 0 ;
#if defined(CYASSL_KEIL_TCP_NET)
SOCKADDR_IN addr ;
@@ -86,7 +86,7 @@ int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
{
- int ret ;
+ int ret = 0 ;
#if defined(CYASSL_KEIL_TCP_NET)
while(1) {
@@ -110,7 +110,7 @@ int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
int Cyassl_recv(int sd, void *buf, size_t len, int flags)
{
- int ret ;
+ int ret = 0;
#if defined(CYASSL_KEIL_TCP_NET)
while(1) {
#undef recv /* Go to KEIL TCPnet recv */
@@ -132,7 +132,7 @@ int Cyassl_recv(int sd, void *buf, size_t len, int flags)
int Cyassl_send(int sd, const void *buf, size_t len, int flags)
{
- int ret ;
+ int ret = 0 ;
#if defined(CYASSL_KEIL_TCP_NET)
while(1) {
@@ -170,40 +170,6 @@ int Cyassl_tcp_select(int sd, int timeout)
}
#endif
-struct tm *Cyassl_MDK_gmtime(const time_t *c)
-{
-
- RTC_TimeTypeDef RTC_Time ;
- RTC_DateTypeDef RTC_Date ;
- static struct tm date ;
-
- RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
- RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
-
- date.tm_year = RTC_Date.RTC_Year + 100 ;
- date.tm_mon = RTC_Date.RTC_Month - 1 ;
- date.tm_mday = RTC_Date.RTC_Date ;
- date.tm_hour = RTC_Time.RTC_Hours ;
- date.tm_min = RTC_Time.RTC_Minutes ;
- date.tm_sec = RTC_Time.RTC_Seconds ;
-
- #if defined(DEBUG_CYASSL)
- {
- char msg[100] ;
- sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n",
- RTC_Date.RTC_Year+2000, RTC_Date.RTC_Month, RTC_Date.RTC_Date,
- RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
- CYASSL_MSG(msg) ;
- }
- #endif
-
- return(&date) ;
-}
-
-double current_time()
-{
- return ((double)TIM2->CNT/1000000.0) ;
-}
extern int getkey(void) ;
extern int sendchar(int c) ;
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h
index c565b6e15..052fe2991 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h
@@ -95,13 +95,9 @@ extern int setsockopt(int sockfd, int level, int optname,
extern int select(int nfds, fd_set *readfds, fd_set *writefds,
fd_set *exceptfds, const struct timeval *timeout);
-
-/** KEIL-RL gmtime ****/
-
+/* CyaSSL MDK-ARM time functions */
#include
-#include "stm32f2xx_rtc.h"
-extern struct tm *gmtime(const time_t *timer);
-extern struct tm *Cyassl_MDK_gmtime(const time_t *timer);
+struct tm *Cyassl_MDK_gmtime(const time_t *c) ;
extern double current_time(void) ;
#endif /* CYASSL_KEIL_RL_H */
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c
index f858f71cd..7a39b51f4 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c
@@ -30,10 +30,6 @@
#include
#include "cyassl_MDK_ARM.h"
-#include "stm32f2xx_tim.h"
-#include "stm32f2xx_rcc.h"
-
-
/*-----------------------------------------------------------------------------
* Initialize a Flash Memory Card
*----------------------------------------------------------------------------*/
@@ -87,77 +83,6 @@ __task void tcp_poll (void)
}
#endif
-/*-----------------------------------------------------------------------------
- * initialize RTC
- *----------------------------------------------------------------------------*/
-#include "stm32f2xx_rtc.h"
-#include "stm32f2xx_rcc.h"
-#include "stm32f2xx_pwr.h"
-
-static init_RTC()
-{
- RTC_InitTypeDef RTC_InitStruct ;
-
- RTC_TimeTypeDef RTC_Time ;
- RTC_DateTypeDef RTC_Date ;
-
-
- /* Enable the PWR clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
-
- /* Allow access to RTC */
- PWR_BackupAccessCmd(ENABLE);
-
-/***Configures the External Low Speed oscillator (LSE)****/
-
- RCC_LSEConfig(RCC_LSE_ON);
-
- /* Wait till LSE is ready */
- while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
- {
- }
-
- /* Select the RTC Clock Source */
- RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
-
- /* Enable the RTC Clock */
- RCC_RTCCLKCmd(ENABLE);
-
- /* Wait for RTC APB registers synchronisation */
- RTC_WaitForSynchro();
-
- /* Calendar Configuration with LSI supposed at 32KHz */
- RTC_InitStruct.RTC_AsynchPrediv = 0x7F;
- RTC_InitStruct.RTC_SynchPrediv = 0xFF;
- RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24;
- RTC_Init(&RTC_InitStruct);
-
- RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
- RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
-}
-
-/*-----------------------------------------------------------------------------
- * initialize TIM
- *----------------------------------------------------------------------------*/
-void init_timer()
-{
- TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure ;
-
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) ;
-
- TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
- TIM_TimeBaseStructure.TIM_Prescaler = 60;
- TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseStructure.TIM_Period = 0xffffffff;
- TIM_TimeBaseStructure.TIM_ClockDivision = 0;
- TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
-
- TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
-
- TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure) ;
- TIM_Cmd(TIM2, ENABLE) ;
-}
-
#if defined(HAVE_KEIL_RTX) && defined(CYASSL_MDK_SHELL)
#define SHELL_STACKSIZE 1000
static unsigned char Shell_stack[SHELL_STACKSIZE] ;
@@ -193,11 +118,12 @@ void main_task (void)
shell_main() ;
#endif
#else
-
+
/************************************/
/*** USER APPLICATION HERE ***/
/************************************/
-
+ printf("USER LOGIC STARTED\n") ;
+
#endif
#ifdef HAVE_KEIL_RTX
@@ -217,16 +143,19 @@ void main_task (void)
/*** main entry ***/
+extern void init_time(void) ;
+extern void SystemInit(void);
+
int main() {
- /* stm32_Init (); STM32 setup */
-
+
+ SystemInit();
+ SER_Init() ;
#if !defined(NO_FILESYSTEM)
init_card () ; /* initializing SD card */
#endif
-
- init_RTC() ;
- init_timer() ;
- SER_Init() ;
+
+ init_time() ;
+
#if defined(DEBUG_CYASSL)
printf("Turning ON Debug message\n") ;
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c
index d6268fa80..1a0b6ad73 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c
@@ -384,39 +384,6 @@ static void ipaddr_comm(void *args)
#endif
-static void time_main(void *args)
-{
- char * datetime ;
- RTC_TimeTypeDef RTC_Time ;
- RTC_DateTypeDef RTC_Date ;
- int year ;
- if( args == NULL || ((func_args *)args)->argc == 1) {
- RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
- RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
- printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
- RTC_Date.RTC_Month, RTC_Date.RTC_Date, RTC_Date.RTC_Year+2000,
- RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
- } else if(((func_args *)args)->argc == 3 &&
- ((func_args *)args)->argv[1][0] == '-' &&
- ((func_args *)args)->argv[1][1] == 'd' ) {
- datetime = ((func_args *)args)->argv[2];
- sscanf(datetime, "%d/%d/%d",
- (int *)&RTC_Date.RTC_Month, (int *)&RTC_Date.RTC_Date, &year) ;
- RTC_Date.RTC_Year = year - 2000 ;
- RTC_Date.RTC_WeekDay = 0 ;
- RTC_SetDate(RTC_Format_BIN, &RTC_Date) ;
- } else if(((func_args *)args)->argc == 3 &&
- ((func_args *)args)->argv[1][0] == '-' &&
- ((func_args *)args)->argv[1][1] == 't' ) {
- datetime = ((func_args *)args)->argv[2];
- sscanf(datetime, "%d:%d:%d",
- (int *)&RTC_Time.RTC_Hours,
- (int *)&RTC_Time.RTC_Minutes,
- (int *)&RTC_Time.RTC_Seconds
- ) ;
- RTC_SetTime(RTC_Format_BIN, &RTC_Time) ;
- } else printf("Invalid argument\n") ;
-}
#if defined(HAVE_KEIL_RTX)
diff --git a/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c b/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c
index 72af132d1..024d10373 100644
--- a/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c
+++ b/IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c
@@ -45,9 +45,9 @@ int CyaSSL_get_using_nonblock(CYASSL* ssl)
CYASSL_LEAVE("CyaSSL_get_using_nonblock", ssl->options.usingNonblock);
return ssl->options.usingNonblock;
}
-
-Signer* GetCAByName(void* vp, byte* hash)
-{
- return NULL;
+
+Signer* GetCAByName(void* vp, byte* hash)
+{
+ Signer * ca ;
+ return(ca) ;
}
-
diff --git a/IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini b/IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini
new file mode 100644
index 000000000..5f72e1102
--- /dev/null
+++ b/IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini
@@ -0,0 +1,22 @@
+/******************************************************************************/
+/* Dbg_Flash.ini Initialization File for Debugging from Internal */
+/* Flash for NXP LPC18xx/LPC43xx */
+/******************************************************************************/
+/* This file is part of the uVision/ARM development tools. */
+/* Copyright (c) 2005-2012 Keil Software. All rights reserved. */
+/* This software may only be used under the terms of a valid, current, */
+/* end user licence from KEIL for a compatible version of KEIL software */
+/* development tools. Nothing else gives you the right to use this software. */
+/******************************************************************************/
+
+FUNC void Per_Reset (void) {
+ // Reset peripherals: LCD, USB0, USB1, DMA, SDIO, ETHERNET
+ _WDWORD(0x40053100, 0x005F0000); // Issue reset
+ _sleep_(1);
+}
+
+Per_Reset(); // Reset some peripherals
+
+KILL BUTTON * // Kill all buttons
+DEFINE BUTTON "Reset Peripherals", "Per_Reset()" // Create peripheral reset button
+
diff --git a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c
index 9c121dac5..96b6dada2 100644
--- a/IDE/MDK-ARM/MDK-ARM/config/File_Config.c
+++ b/IDE/MDK-ARM/MDK-ARM/config/File_Config.c
@@ -1,387 +1,401 @@
-/*----------------------------------------------------------------------------
- * RL-ARM - FlashFS
- *----------------------------------------------------------------------------
- * Name: FILE_CONFIG.C
- * Purpose: Configuration of RL FlashFS by user
- * Rev.: V4.50
- *----------------------------------------------------------------------------
- * This code is part of the RealView Run-Time Library.
- * Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
- *---------------------------------------------------------------------------*/
-
-#include
-
-//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
-//
-// File System
-// ==============
-// Define File System global parameters
-
-// Number of open files <4-16>
-// Define number of files that can be
-// opened at the same time.
-// Default: 8
-#define N_FILES 6
-
-// CPU Clock Frequency [Hz]<0-1000000000>
-// Define the CPU Clock frequency used for
-// flash programming and erasing.
-#define CPU_CLK 120000000
-
-//
-// Flash Drive
-// ==============
-// Enable Embedded Flash Drive [F:]
-#define FL0_EN 0
-
-// Base address <0x0-0xFFFFF000:0x1000>
-// Define the target device Base address
-// Default: 0x80000000
-#define FL0_BADR 0x80000000
-
-// Device Size <0x4000-0xFFFFF000:0x4000>
-// Define the size of Flash device in bytes
-// Default: 0x100000 (1MB)
-#define FL0_SIZE 0x0200000
-
-// Content of Erased Memory <0=>0x00 <0xFF=>0xFF
-// Define the initial value for erased Flash data
-// Default: 0xFF
-#define FL0_INITV 0xFF
-
-// Device Description file
-// Specify a file name with a relative path
-// Default: FS_FlashDev.h
-#define FL0_HFILE "FS_FlashDev.h"
-
-// Default Drive [F:]
-// Used when Drive letter not specified
-#define FL0_DEF 1
-
-//
-// SPI Flash Drive
-// ==================
-// Enable SPI Flash Drive [S:]
-#define SF0_EN 0
-
-// Device Size <0x10000-0xFFFFF000:0x8000>
-// Define the size of SPI Flash device in bytes
-// Default: 0x100000 (1MB)
-#define SF0_SIZE 0x0200000
-
-// Content of Erased Memory <0=>0x00 <0xFF=>0xFF
-// Define the initial value for erased Flash data
-// Default: 0xFF
-#define SF0_INITV 0xFF
-
-// Device Description file
-// Specify a file name with a relative path
-// Default: FS_SPI_FlashDev.h
-#define SF0_HFILE "FS_SPI_FlashDev.h"
-
-// Default Drive [S:]
-// Used when Drive letter not specified
-#define SF0_DEF 0
-
-//
-// RAM Drive
-// ============
-// Enable Embedded RAM Drive [R:]
-#define RAM0_EN 0
-
-// Device Size <0x4000-0xFFFFF000:0x4000>
-// Define the size of RAM device in bytes
-// Default: 0x40000
-#define RAM0_SIZE 0x004000
-
-// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
-// Define number of virtual sectors for RAM device
-// Default: 32
-#define RAM0_NSECT 64
-
-// Relocate Device Buffer
-// Locate RAM Device Buffer at a specific address.
-// If not enabled, the linker selects base address.
-#define RAM0_RELOC 1
-
-// Base address <0x0-0xFFFFF000:0x1000>
-// Define the target device Base address.
-// Default: 0x81000000
-#define RAM0_BADR 0x81010000
-
-//
-// Default Drive [R:]
-// Used when Drive letter not specified
-#define RAM0_DEF 0
-
-//
-// Memory Card Drive 0
-// ======================
-// Enable Memory Card Drive [M0:]
-#define MC0_EN 1
-
-// Bus Mode <0=>SD-Native <1=>SPI
-// Define Memory Card bus interface mode.
-// SD-Native mode needs MCI peripheral.
-// SPI mode uses SD Card in SPI mode.
-#define MC0_SPI 0
-
-// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
-// <8=>8 KB <16=>16 KB <32=>32 KB
-// Define System Cache buffer size for file IO.
-// Increase this number for faster r/w access.
-// Default: 4 kB
-#define MC0_CASZ 16
-
-// Relocate Cache Buffer
-// Locate Cache Buffer at a specific address.
-// Some devices like NXP LPC23xx require a Cache buffer
-// for DMA transfer located at specific address.
-#define MC0_RELOC 0
-
-// Base address <0x0000-0xFFFFFE00:0x200>
-// Define the Cache buffer base address.
-// For LPC23xx/24xx devices this is USB RAM
-// starting at 0x7FD00000.
-#define MC0_CADR 0x7FD00000
-
-//
-// FAT Journal
-// Enable FAT Journal in order to guarantee
-// fail-safe FAT file system operation.
-#define MC0_FSJ 0
-
-// Default Drive [M0:]
-// Used when Drive letter not specified
-#define MC0_DEF 1
-
-//
-// Memory Card Drive 1
-// ======================
-// Enable Memory Card Drive [M1:]
-#define MC1_EN 0
-
-// Bus Mode <0=>SD-Native <1=>SPI
-// Define Memory Card bus interface mode.
-// SD-Native mode needs MCI peripheral.
-// SPI mode uses SD Card in SPI mode.
-#define MC1_SPI 1
-
-// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
-// <8=>8 KB <16=>16 KB <32=>32 KB
-// Define System Cache buffer size for file IO.
-// Increase this number for faster r/w access.
-// Default: 4 kB
-#define MC1_CASZ 0
-
-// Relocate Cache Buffer
-// Locate Cache Buffer at a specific address.
-// Some devices like NXP LPC23xx require a Cache buffer
-// for DMA transfer located at specific address.
-#define MC1_RELOC 0
-
-// Base address <0x0000-0xFFFFFE00:0x200>
-// Define the Cache buffer base address.
-// For LPC23xx/24xx devices this is USB RAM
-// starting at 0x7FD00000.
-#define MC1_CADR 0x7FD00000
-
-//
-// FAT Journal
-// Enable FAT Journal in order to guarantee
-// fail-safe FAT file system operation.
-#define MC1_FSJ 0
-
-// Default Drive [M1:]
-// Used when Drive letter not specified
-#define MC1_DEF 0
-
-//
-// USB Flash Drive 0
-// ====================
-// Enable USB Flash Drive [U0:]
-#define USB0_EN 0
-
-// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
-// <8=>8 KB <16=>16 KB <32=>32 KB
-// Define System Cache buffer size for file IO.
-// Increase this number for faster r/w access.
-// Default: 4 kB
-#define USB0_CASZ 8
-
-// FAT Journal
-// Enable FAT Journal in order to guarantee
-// fail-safe FAT file system operation.
-#define USB0_FSJ 0
-
-// Default Drive [U0:]
-// Used when Drive letter not specified
-#define USB0_DEF 1
-
-//
-// USB Flash Drive 1
-// ====================
-// Enable USB Flash Drive [U1:]
-#define USB1_EN 0
-
-// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
-// <8=>8 KB <16=>16 KB <32=>32 KB
-// Define System Cache buffer size for file IO.
-// Increase this number for faster r/w access.
-// Default: 4 kB
-#define USB1_CASZ 8
-
-// FAT Journal
-// Enable FAT Journal in order to guarantee
-// fail-safe FAT file system operation.
-#define USB1_FSJ 0
-
-// Default Drive [U1:]
-// Used when Drive letter not specified
-#define USB1_DEF 1
-
-//
-// NAND Flash Drive 0
-// ===================
-// Enable NAND Flash Drive [N0:]
-#define NAND0_EN 0
-
-// Page size <528=> 512 + 16 bytes
-// <2112=>2048 + 64 bytes
-// <4224=>4096 + 128 bytes
-// <8448=>8192 + 256 bytes
-// Define program Page size in bytes (User + Spare area).
-#define NAND0_PGSZ 2112
-
-// Block Size <8=>8 pages <16=>16 pages <32=>32 pages
-// <64=>64 pages <128=>128 pages <256=>256 pages
-// Define number of pages in a block.
-#define NAND0_PGCNT 64
-
-// Device Size [blocks] <512-32768>
-// Define number of blocks in NAND Flash device.
-#define NAND0_BLCNT 4096
-
-// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
-// <8=>8 pages <16=>16 pages <32=>32 pages
-// Define number of cached Pages.
-// Default: 4 pages
-#define NAND0_CAPG 2
-
-// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
-// <8=>8 blocks <16=>16 blocks <32=>32 blocks
-// <64=>64 blocks <128=>128 blocks <256=>256 blocks
-// Define number of indexed Flash Blocks.
-// Increase this number for better performance.
-// Default: 16 blocks
-#define NAND0_CABL 16
-
-// Software ECC <0=>None <1=>Hamming (SLC)
-// Enable software ECC calculation only,
-// if not supported by hardware.
-#define NAND0_SWECC 1
-
-// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
-// <8=>8 KB <16=>16 KB <32=>32 KB
-// Define System Cache buffer size for file IO.
-// Increase this number for faster r/w access.
-// Default: 4 kB
-#define NAND0_CASZ 4
-
-// Relocate Cache Buffers
-// Use this option to locate Cache buffers
-// at specific address in RAM or SDRAM.
-#define NAND0_RELOC 0
-
-// Base address <0x0000-0xFFFFFE00:0x200>
-// Define base address for Cache Buffers.
-#define NAND0_CADR 0x80000000
-
-//
-// FAT Journal
-// Enable FAT Journal in order to guarantee
-// fail-safe FAT file system operation.
-#define NAND0_FSJ 0
-
-// Default Drive [N0:]
-// Used when Drive letter not specified
-#define NAND0_DEF 0
-
-//
-// NAND Flash Drive 1
-// ===================
-// Enable NAND Flash Drive [N1:]
-#define NAND1_EN 0
-
-// Page size <528=> 512 + 16 bytes
-// <2112=>2048 + 64 bytes
-// <4224=>4096 + 128 bytes
-// <8448=>8192 + 256 bytes
-// Define program Page size in bytes (User + Spare area).
-#define NAND1_PGSZ 2112
-
-// Block Size <8=>8 pages <16=>16 pages <32=>32 pages
-// <64=>64 pages <128=>128 pages <256=>256 pages
-// Define number of pages in a block.
-#define NAND1_PGCNT 32
-
-// Device Size [blocks] <512-32768>
-// Define number of blocks in NAND Flash device.
-#define NAND1_BLCNT 512
-
-// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
-// <8=>8 pages <16=>16 pages <32=>32 pages
-// Define number of cached Pages.
-// Default: 4 pages
-#define NAND1_CAPG 4
-
-// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
-// <8=>8 blocks <16=>16 blocks <32=>32 blocks
-// <64=>64 blocks <128=>128 blocks <256=>256 blocks
-// Define number of indexed Flash Blocks.
-// Increase this number for better performance.
-// Default: 16 blocks
-#define NAND1_CABL 16
-
-// Software ECC <0=>None <1=>Hamming (SLC)
-// Enable software ECC calculation only,
-// if not supported by hardware.
-#define NAND1_SWECC 0
-
-// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
-// <8=>8 KB <16=>16 KB <32=>32 KB
-// Define System Cache buffer size for file IO.
-// Increase this number for faster r/w access.
-// Default: 4 kB
-#define NAND1_CASZ 4
-
-// Relocate Cache Buffers
-// Use this option to locate Cache buffers
-// at specific address in RAM or SDRAM.
-#define NAND1_RELOC 0
-
-// Base address <0x0000-0xFFFFFE00:0x200>
-// Define base address for Cache Buffers.
-#define NAND1_CADR 0x80000000
-
-//
-// FAT Journal
-// Enable FAT Journal in order to guarantee
-// fail-safe FAT file system operation.
-#define NAND1_FSJ 0
-
-// Default Drive [N1:]
-// Used when Drive letter not specified
-#define NAND1_DEF 0
-
-//
-
-//------------- <<< end of configuration section >>> -----------------------
-
-#ifndef __NO_FILE_LIB_C
-#include
-#endif
-
-/*----------------------------------------------------------------------------
- * end of file
- *---------------------------------------------------------------------------*/
+/*----------------------------------------------------------------------------
+ * RL-ARM - FlashFS
+ *----------------------------------------------------------------------------
+ * Name: FILE_CONFIG.C
+ * Purpose: Configuration of RL FlashFS by user
+ * Rev.: V4.70
+ *----------------------------------------------------------------------------
+ * This code is part of the RealView Run-Time Library.
+ * Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved.
+ *---------------------------------------------------------------------------*/
+
+#include
+
+//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
+//
+// File System
+// ==============
+// Define File System global parameters
+
+// Number of open files <4-16>
+// Define number of files that can be
+// opened at the same time.
+// Default: 8
+#define N_FILES 6
+
+// FAT Name Cache Size <0-1000000>
+// Define number of cached FAT file or directory names.
+// 48 bytes of RAM is required for each cached name.
+#define FAT_NAME_CACNT 0
+
+// Relocate FAT Name Cache Buffer
+// Locate Cache Buffer at a specific address.
+#define FAT_NAME_RELOC 0
+
+// Base address <0x0000-0xFFFFFE00:0x200>
+// Define the Cache buffer base address.
+#define FAT_NAME_CADR 0x60000000
+
+//
+// CPU Clock Frequency [Hz]<0-1000000000>
+// Define the CPU Clock frequency used for
+// flash programming and erasing.
+#define CPU_CLK 180000000
+
+//
+// Flash Drive
+// ==============
+// Enable Embedded Flash Drive [F:]
+#define FL0_EN 0
+
+// Base address <0x0-0xFFFFF000:0x1000>
+// Define the target device Base address
+// Default: 0x80000000
+#define FL0_BADR 0x80000000
+
+// Device Size <0x4000-0xFFFFF000:0x4000>
+// Define the size of Flash device in bytes
+// Default: 0x100000 (1MB)
+#define FL0_SIZE 0x0200000
+
+// Content of Erased Memory <0=>0x00 <0xFF=>0xFF
+// Define the initial value for erased Flash data
+// Default: 0xFF
+#define FL0_INITV 0xFF
+
+// Device Description file
+// Specify a file name with a relative path
+// Default: FS_FlashDev.h
+#define FL0_HFILE "FS_FlashDev.h"
+
+// Default Drive [F:]
+// Used when Drive letter not specified
+#define FL0_DEF 1
+
+//
+// SPI Flash Drive
+// ==================
+// Enable SPI Flash Drive [S:]
+#define SF0_EN 0
+
+// Device Size <0x10000-0xFFFFF000:0x8000>
+// Define the size of SPI Flash device in bytes
+// Default: 0x100000 (1MB)
+#define SF0_SIZE 0x0200000
+
+// Content of Erased Memory <0=>0x00 <0xFF=>0xFF
+// Define the initial value for erased Flash data
+// Default: 0xFF
+#define SF0_INITV 0xFF
+
+// Device Description file
+// Specify a file name with a relative path
+// Default: FS_SPI_FlashDev.h
+#define SF0_HFILE "FS_SPI_FlashDev.h"
+
+// Default Drive [S:]
+// Used when Drive letter not specified
+#define SF0_DEF 0
+
+//
+// RAM Drive
+// ============
+// Enable Embedded RAM Drive [R:]
+#define RAM0_EN 0
+
+// Device Size <0x4000-0xFFFFF000:0x4000>
+// Define the size of RAM device in bytes
+// Default: 0x40000
+#define RAM0_SIZE 0x004000
+
+// Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
+// Define number of virtual sectors for RAM device
+// Default: 32
+#define RAM0_NSECT 64
+
+// Relocate Device Buffer
+// Locate RAM Device Buffer at a specific address.
+// If not enabled, the linker selects base address.
+#define RAM0_RELOC 1
+
+// Base address <0x0-0xFFFFF000:0x1000>
+// Define the target device Base address.
+// Default: 0x81000000
+#define RAM0_BADR 0x81010000
+
+//
+// Default Drive [R:]
+// Used when Drive letter not specified
+#define RAM0_DEF 0
+
+//
+// Memory Card Drive 0
+// ======================
+// Enable Memory Card Drive [M0:]
+#define MC0_EN 1
+
+// Bus Mode <0=>SD-Native <1=>SPI
+// Define Memory Card bus interface mode.
+// SD-Native mode needs MCI peripheral.
+// SPI mode uses SD Card in SPI mode.
+#define MC0_SPI 0
+
+// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Define System Cache buffer size for file IO.
+// Increase this number for faster r/w access.
+// Default: 4 kB
+#define MC0_CASZ 4
+
+// Relocate Cache Buffer
+// Locate Cache Buffer at a specific address.
+// Some devices like NXP LPC23xx require a Cache buffer
+// for DMA transfer located at specific address.
+#define MC0_RELOC 0
+
+// Base address <0x0000-0xFFFFFE00:0x200>
+// Define the Cache buffer base address.
+// For LPC23xx/24xx devices this is USB RAM
+// starting at 0x7FD00000.
+#define MC0_CADR 0x7FD00000
+
+//
+// FAT Journal
+// Enable FAT Journal in order to guarantee
+// fail-safe FAT file system operation.
+#define MC0_FSJ 0
+
+// Default Drive [M0:]
+// Used when Drive letter not specified
+#define MC0_DEF 1
+
+//
+// Memory Card Drive 1
+// ======================
+// Enable Memory Card Drive [M1:]
+#define MC1_EN 0
+
+// Bus Mode <0=>SD-Native <1=>SPI
+// Define Memory Card bus interface mode.
+// SD-Native mode needs MCI peripheral.
+// SPI mode uses SD Card in SPI mode.
+#define MC1_SPI 1
+
+// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Define System Cache buffer size for file IO.
+// Increase this number for faster r/w access.
+// Default: 4 kB
+#define MC1_CASZ 0
+
+// Relocate Cache Buffer
+// Locate Cache Buffer at a specific address.
+// Some devices like NXP LPC23xx require a Cache buffer
+// for DMA transfer located at specific address.
+#define MC1_RELOC 0
+
+// Base address <0x0000-0xFFFFFE00:0x200>
+// Define the Cache buffer base address.
+// For LPC23xx/24xx devices this is USB RAM
+// starting at 0x7FD00000.
+#define MC1_CADR 0x7FD00000
+
+//
+// FAT Journal
+// Enable FAT Journal in order to guarantee
+// fail-safe FAT file system operation.
+#define MC1_FSJ 0
+
+// Default Drive [M1:]
+// Used when Drive letter not specified
+#define MC1_DEF 0
+
+//
+// USB Flash Drive 0
+// ====================
+// Enable USB Flash Drive [U0:]
+#define USB0_EN 0
+
+// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Define System Cache buffer size for file IO.
+// Increase this number for faster r/w access.
+// Default: 4 kB
+#define USB0_CASZ 8
+
+// FAT Journal
+// Enable FAT Journal in order to guarantee
+// fail-safe FAT file system operation.
+#define USB0_FSJ 0
+
+// Default Drive [U0:]
+// Used when Drive letter not specified
+#define USB0_DEF 0
+
+//
+// USB Flash Drive 1
+// ====================
+// Enable USB Flash Drive [U1:]
+#define USB1_EN 0
+
+// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Define System Cache buffer size for file IO.
+// Increase this number for faster r/w access.
+// Default: 4 kB
+#define USB1_CASZ 8
+
+// FAT Journal
+// Enable FAT Journal in order to guarantee
+// fail-safe FAT file system operation.
+#define USB1_FSJ 0
+
+// Default Drive [U1:]
+// Used when Drive letter not specified
+#define USB1_DEF 0
+
+//
+// NAND Flash Drive 0
+// ===================
+// Enable NAND Flash Drive [N0:]
+#define NAND0_EN 0
+
+// Page size <528=> 512 + 16 bytes
+// <2112=>2048 + 64 bytes
+// <4224=>4096 + 128 bytes
+// <8448=>8192 + 256 bytes
+// Define program Page size in bytes (User + Spare area).
+#define NAND0_PGSZ 2112
+
+// Block Size <8=>8 pages <16=>16 pages <32=>32 pages
+// <64=>64 pages <128=>128 pages <256=>256 pages
+// Define number of pages in a block.
+#define NAND0_PGCNT 64
+
+// Device Size [blocks] <512-32768>
+// Define number of blocks in NAND Flash device.
+#define NAND0_BLCNT 4096
+
+// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
+// <8=>8 pages <16=>16 pages <32=>32 pages
+// Define number of cached Pages.
+// Default: 4 pages
+#define NAND0_CAPG 2
+
+// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
+// <8=>8 blocks <16=>16 blocks <32=>32 blocks
+// <64=>64 blocks <128=>128 blocks <256=>256 blocks
+// Define number of indexed Flash Blocks.
+// Increase this number for better performance.
+// Default: 16 blocks
+#define NAND0_CABL 16
+
+// Software ECC <0=>None <1=>Hamming (SLC)
+// Enable software ECC calculation only,
+// if not supported by hardware.
+#define NAND0_SWECC 1
+
+// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Define System Cache buffer size for file IO.
+// Increase this number for faster r/w access.
+// Default: 4 kB
+#define NAND0_CASZ 4
+
+// Relocate Cache Buffers
+// Use this option to locate Cache buffers
+// at specific address in RAM or SDRAM.
+#define NAND0_RELOC 0
+
+// Base address <0x0000-0xFFFFFE00:0x200>
+// Define base address for Cache Buffers.
+#define NAND0_CADR 0x80000000
+
+//
+// FAT Journal
+// Enable FAT Journal in order to guarantee
+// fail-safe FAT file system operation.
+#define NAND0_FSJ 0
+
+// Default Drive [N0:]
+// Used when Drive letter not specified
+#define NAND0_DEF 0
+
+//
+// NAND Flash Drive 1
+// ===================
+// Enable NAND Flash Drive [N1:]
+#define NAND1_EN 0
+
+// Page size <528=> 512 + 16 bytes
+// <2112=>2048 + 64 bytes
+// <4224=>4096 + 128 bytes
+// <8448=>8192 + 256 bytes
+// Define program Page size in bytes (User + Spare area).
+#define NAND1_PGSZ 2112
+
+// Block Size <8=>8 pages <16=>16 pages <32=>32 pages
+// <64=>64 pages <128=>128 pages <256=>256 pages
+// Define number of pages in a block.
+#define NAND1_PGCNT 32
+
+// Device Size [blocks] <512-32768>
+// Define number of blocks in NAND Flash device.
+#define NAND1_BLCNT 512
+
+// Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
+// <8=>8 pages <16=>16 pages <32=>32 pages
+// Define number of cached Pages.
+// Default: 4 pages
+#define NAND1_CAPG 4
+
+// Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
+// <8=>8 blocks <16=>16 blocks <32=>32 blocks
+// <64=>64 blocks <128=>128 blocks <256=>256 blocks
+// Define number of indexed Flash Blocks.
+// Increase this number for better performance.
+// Default: 16 blocks
+#define NAND1_CABL 16
+
+// Software ECC <0=>None <1=>Hamming (SLC)
+// Enable software ECC calculation only,
+// if not supported by hardware.
+#define NAND1_SWECC 0
+
+// File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
+// <8=>8 KB <16=>16 KB <32=>32 KB
+// Define System Cache buffer size for file IO.
+// Increase this number for faster r/w access.
+// Default: 4 kB
+#define NAND1_CASZ 4
+
+// Relocate Cache Buffers
+// Use this option to locate Cache buffers
+// at specific address in RAM or SDRAM.
+#define NAND1_RELOC 0
+
+// Base address <0x0000-0xFFFFFE00:0x200>
+// Define base address for Cache Buffers.
+#define NAND1_CADR 0x80000000
+
+//
+// FAT Journal
+// Enable FAT Journal in order to guarantee
+// fail-safe FAT file system operation.
+#define NAND1_FSJ 0
+
+// Default Drive [N1:]
+// Used when Drive letter not specified
+#define NAND1_DEF 0
+
+//
+
+//------------- <<< end of configuration section >>> -----------------------
+
+#ifndef __NO_FILE_LIB_C
+#include
+#endif
+
+/*----------------------------------------------------------------------------
+ * end of file
+ *---------------------------------------------------------------------------*/
diff --git a/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c b/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c
index 2d932a2d1..a03892045 100644
--- a/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c
+++ b/IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c
@@ -39,7 +39,7 @@
// Set the stack size for tasks which is assigned by the system.
// Default: 512
#ifndef OS_STKSIZE
- #define OS_STKSIZE 250
+ #define OS_STKSIZE 499
#endif
// Check for the stack overflow
diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvopt b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvopt
new file mode 100644
index 000000000..eb9077e3e
--- /dev/null
+++ b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvopt
@@ -0,0 +1,1727 @@
+
+
+
+ 1.0
+
+ ### uVision Project, (C) Keil Software
+
+
+ *.c
+ *.s*; *.src; *.a*
+ *.obj
+ *.lib
+ *.txt; *.h; *.inc
+ *.plm
+ *.cpp
+
+
+
+ 0
+ 0
+
+
+
+ MDK-RTX-TCP-FS
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Lst\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 1
+
+ 8
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 9
+
+
+
+
+
+
+
+
+
+ ..\MDK-ARM\config\Dbg_Flash.ini
+ BIN\ULP2CM3.DLL
+
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ ULP2CM3
+ -UP1135060 -O974 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS7 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000
+
+
+
+
+
+ 1
+ 0
+ 0x10005960
+
+
+
+
+ 0
+ Reset Peripherals
+ Per_Reset()
+
+
+
+ 0
+
+
+ 0
+ 0
+ 1
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+ MDK-FS
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Lst\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 0
+
+ 8
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 9
+
+
+
+
+
+
+
+
+
+ ..\MDK-ARM\config\Dbg_Flash.ini
+ BIN\ULP2CM3.DLL
+
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ ULP2CM3
+ -UP1135060 -O974 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS7 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000
+
+
+
+
+
+ 0
+ Reset Peripherals
+ Per_Reset()
+
+
+
+ 0
+
+
+ 0
+ 0
+ 1
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+ MDK-BARE-METAL
+ 0x4
+ ARM-ADS
+
+ 12000000
+
+ 1
+ 1
+ 1
+ 0
+
+
+ 1
+ 65535
+ 0
+ 0
+ 0
+
+
+ 79
+ 66
+ 8
+ .\Lst\
+
+
+ 1
+ 1
+ 1
+ 0
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 0
+
+
+ 1
+ 0
+ 0
+
+ 8
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+ 0
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 1
+ 0
+ 1
+ 0
+ 0
+ 0
+ 9
+
+
+
+
+
+
+
+
+
+ ..\MDK-ARM\config\Dbg_Flash.ini
+ BIN\ULP2CM3.DLL
+
+
+
+ 0
+ DLGTARM
+ (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)
+
+
+ 0
+ ARMDBGFLAGS
+
+
+
+ 0
+ DLGUARM
+
+
+
+ 0
+ ULP2CM3
+ -UP1135060 -O975 -S8 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS7 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000
+
+
+
+
+
+ 0
+ Reset Peripherals
+ Per_Reset()
+
+
+
+ 0
+
+
+ 0
+ 0
+ 1
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 1
+ 0
+ 0
+ 0
+ 0
+
+
+
+
+
+
+
+ CyaSSL Apps
+ 1
+ 0
+ 0
+ 0
+
+ 1
+ 1
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\..\examples\echoclient\echoclient.c
+ echoclient.c
+ 0
+ 0
+
+
+ 1
+ 2
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\..\..\examples\echoserver\echoserver.c
+ echoserver.c
+ 0
+ 0
+
+
+ 1
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+ 1
+ 0
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+ 0
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+ ..\..\..\ctaocrypt\test\test.c
+ test.c
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+
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+ 0
+ 0
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+ benchmark.c
+ 0
+ 0
+
+
+ 1
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+ 1
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+ 0
+ 0
+ 0
+ 0
+ 0
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+ ..\..\..\examples\client\client.c
+ client.c
+ 0
+ 0
+
+
+ 1
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+ 1
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+ 0
+ 0
+ 0
+ 0
+ ..\..\..\examples\server\server.c
+ server.c
+ 0
+ 0
+
+
+ 1
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+ 1
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+ 1
+ 1
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+ ..\MDK-ARM\CyaSSL\shell.c
+ shell.c
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+
+
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+ 1
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+ 149
+ 0
+ ..\MDK-ARM\CyaSSL\main.c
+ main.c
+ 0
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+
+
+ 1
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+ 1
+ 0
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+ 0
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+ 0
+ 0
+ 0
+ ..\MDK-ARM\CyaSSL\cert_data.c
+ cert_data.c
+ 0
+ 0
+
+
+
+
+ LPC43xx
+ 1
+ 0
+ 0
+ 0
+
+ 2
+ 10
+ 1
+ 0
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+ 0
+ ..\LPC43xx\Drivers\source\lpc43xx_rtc.c
+ lpc43xx_rtc.c
+ 0
+ 0
+
+
+ 2
+ 11
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\LPC43xx\Drivers\source\lpc43xx_timer.c
+ lpc43xx_timer.c
+ 0
+ 0
+
+
+ 2
+ 12
+ 1
+ 0
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+ ..\LPC43xx\Drivers\source\lpc43xx_cgu.c
+ lpc43xx_cgu.c
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+
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+ ..\LPC43xx\Drivers\source\lpc43xx_scu.c
+ lpc43xx_scu.c
+ 0
+ 0
+
+
+
+
+ MDK-ARM
+ 1
+ 0
+ 0
+ 0
+
+ 3
+ 14
+ 4
+ 0
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+ 0
+ 0
+ 0
+ 0
+ 0
+ c:\Keil\ARM\RV31\LIB\FS_CM3.lib
+ FS_CM3.lib
+ 0
+ 0
+
+
+ 3
+ 15
+ 4
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+ 0
+ 0
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+ c:\Keil\ARM\RV31\LIB\\RTX_CM3.lib
+ RTX_CM3.lib
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+
+
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+ c:\Keil\ARM\RV31\LIB\TCPD_CM3.lib
+ TCPD_CM3.lib
+ 0
+ 0
+
+
+ 3
+ 17
+ 4
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+ 0
+ 0
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+ 0
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+ c:\Keil\ARM\RV31\LIB\TCP_CM3.lib
+ TCP_CM3.lib
+ 0
+ 0
+
+
+ 3
+ 18
+ 1
+ 0
+ 0
+ 0
+ 0
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+ 56
+ 0
+ C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\Serial.c
+ Serial.c
+ 0
+ 0
+
+
+ 3
+ 19
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ C:\Keil\ARM\RL\TCPnet\Drivers\ETH_LPC43xx.c
+ ETH_LPC43xx.c
+ 0
+ 0
+
+
+ 3
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+ 1
+ 0
+ 0
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+ 0
+ 259
+ 260
+ 0
+ C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\SDIO_LPC43xx.c
+ SDIO_LPC43xx.c
+ 0
+ 0
+
+
+ 3
+ 21
+ 1
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+ 0
+ 0
+ 0
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+ C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\system_LPC43xx.c
+ system_LPC43xx.c
+ 0
+ 0
+
+
+
+
+ CyaSSL Library
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+
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+ 1
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+ ..\..\..\src\crl.c
+ crl.c
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+
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+ ..\..\..\src\ocsp.c
+ ocsp.c
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+ ..\..\..\src\sniffer.c
+ sniffer.c
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diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvproj b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvproj
new file mode 100644
index 000000000..aa30f09ba
--- /dev/null
+++ b/IDE/MDK-ARM/Projects/MDK-ARM-LCP43xx.uvproj
@@ -0,0 +1,3495 @@
+
+
+
+ 1.1
+
+ ### uVision Project, (C) Keil Software
+
+
+
+ MDK-RTX-TCP-FS
+ 0x4
+ ARM-ADS
+
+
+ LPC4357
+ NXP (founded by Philips)
+ IRAM(0x10000000-0x10007FFF) IRAM2(0x20000000-0x2000FFFF) IROM(0x1A000000-0x1A07FFFF) IROM2(0x1B000000-0x1B07FFFF) CLOCK(12000000) CPUTYPE("Cortex-M4") FPU2
+
+ "STARTUP\NXP\LPC43xx\startup_LPC43xx.s" ("NXP LPC43xx Startup Code")
+ UL2CM3(-O975 -S0 -C0 -FO7 -FD10000000 -FC800 -FN2 -FF0LPC18xx43xx_512_BA -FS01A000000 -FL080000 -FF1LPC18xx43xx_512_BB -FS11B000000 -FL180000)
+ 6414
+ LPC43xx.H
+
+
+
+
+
+
+
+
+
+ SFD\NXP\LPC43xx\LPC43xx.SFR
+ 0
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+
+ NXP\LPC43xx\
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+
+
+
+ SARMCM3.DLL
+ -MPU
+ DCM.DLL
+ -pCM4
+ SARMCM3.DLL
+ -MPU
+ TCM.DLL
+ -pCM4
+
+
+
+ 1
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+
+
+
+
+
+
+
+ ..\MDK-ARM\config\Dbg_Flash.ini
+ BIN\ULP2CM3.DLL
+
+
+
+
+ 1
+ 0
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+ 1
+ 4100
+
+ 0
+ BIN\ULP2CM3.DLL
+ "" ()
+
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+
+ HAVE_CONFIG_H CYASSL_LPC43xx __DBG_ITM CORE_M4 __RTX USE_STDPERIPH_DRIVER MDK_CONF_RTX_TCP_FS
+
+ ..\MDK-ARM\CyaSSL;../../..;..\LPC43xx\Drivers\include;..\LPC43xx\LPC43xx\Include
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+
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+
+
+
+
+
+
+
+
+
+
+ CyaSSL Apps
+
+
+ echoclient.c
+ 1
+ ..\..\..\examples\echoclient\echoclient.c
+
+
+ echoserver.c
+ 1
+ ..\..\..\examples\echoserver\echoserver.c
+
+
+ test.c
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+
+ benchmark.c
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+
+
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+
+
+ server.c
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+
+ shell.c
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+
+ cert_data.c
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+ LPC43xx
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+
+ lpc43xx_rtc.c
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+
+
+ lpc43xx_scu.c
+ 1
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+
+
+
+
+ MDK-ARM
+
+
+ FS_CM3.lib
+ 4
+ c:\Keil\ARM\RV31\LIB\FS_CM3.lib
+
+
+ RTX_CM3.lib
+ 4
+ c:\Keil\ARM\RV31\LIB\\RTX_CM3.lib
+
+
+ TCPD_CM3.lib
+ 4
+ c:\Keil\ARM\RV31\LIB\TCPD_CM3.lib
+
+
+ 2
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+
+
+
+
+
+
+
+ TCP_CM3.lib
+ 4
+ c:\Keil\ARM\RV31\LIB\TCP_CM3.lib
+
+
+ Serial.c
+ 1
+ C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\Serial.c
+
+
+ ETH_LPC43xx.c
+ 1
+ C:\Keil\ARM\RL\TCPnet\Drivers\ETH_LPC43xx.c
+
+
+ SDIO_LPC43xx.c
+ 1
+ C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\SDIO_LPC43xx.c
+
+
+ system_LPC43xx.c
+ 1
+ C:\Keil\ARM\Boards\Keil\MCB4300\RL\FlashFS\SD_File\system_LPC43xx.c
+
+
+
+
+ CyaSSL Library
+
+
+ crl.c
+ 1
+ ..\..\..\src\crl.c
+
+
+ internal.c
+ 1
+ ..\..\..\src\internal.c
+
+
+ io.c
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+
+
+ keys.c
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+
+
+ ocsp.c
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+
+ sniffer.c
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+
+ ssl.c
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+
+ tls.c
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+
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+
+
+
+
+
+
+ Crypt/Cipher Library
+
+
+ aes.c
+ 1
+ ..\..\..\ctaocrypt\src\aes.c
+
+
+ arc4.c
+ 1
+ ..\..\..\ctaocrypt\src\arc4.c
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+
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+
+ camellia.c
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+
+ coding.c
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+
+ des3.c
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+
+ dh.c
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+
+ dsa.c
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+
+ ecc.c
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+
+ ecc_fp.c
+ 1
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+
+ error.c
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+
+
+ hc128.c
+ 1
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+
+ hmac.c
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+
+ integer.c
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+
+ logging.c
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+
+ md2.c
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+
+ md4.c
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+
+ memory.c
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+ pwdbased.c
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+
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+ CyaSSL Library
+
+
+ crl.c
+ 1
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+
+
+ internal.c
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+ Crypt/Cipher Library
+
+
+ aes.c
+ 1
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+
+
+ arc4.c
+ 1
+ ..\..\..\ctaocrypt\src\arc4.c
+
+
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+ 1
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+
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+ 1
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+
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+ camellia.c
+ 1
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+
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+ coding.c
+ 1
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+
+
+ des3.c
+ 1
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+
+
+ dh.c
+ 1
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+
+
+ dsa.c
+ 1
+ ..\..\..\ctaocrypt\src\dsa.c
+
+
+ ecc.c
+ 1
+ ..\..\..\ctaocrypt\src\ecc.c
+
+
+ ecc_fp.c
+ 1
+ ..\..\..\ctaocrypt\src\ecc_fp.c
+
+
+ error.c
+ 1
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+
+
+ hc128.c
+ 1
+ ..\..\..\ctaocrypt\src\hc128.c
+
+
+ hmac.c
+ 1
+ ..\..\..\ctaocrypt\src\hmac.c
+
+
+ integer.c
+ 1
+ ..\..\..\ctaocrypt\src\integer.c
+
+
+ logging.c
+ 1
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+
+
+ md2.c
+ 1
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+
+
+ md4.c
+ 1
+ ..\..\..\ctaocrypt\src\md4.c
+
+
+ md5.c
+ 1
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+
+
+ memory.c
+ 1
+ ..\..\..\ctaocrypt\src\memory.c
+
+
+ misc.c
+ 1
+ ..\..\..\ctaocrypt\src\misc.c
+
+
+ pwdbased.c
+ 1
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+
+
+ rabbit.c
+ 1
+ ..\..\..\ctaocrypt\src\rabbit.c
+
+
+ random.c
+ 1
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+
+
+ ripemd.c
+ 1
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+
+
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+ 1
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+
+
+ sha.c
+ 1
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+
+
+ sha256.c
+ 1
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+
+
+ sha512.c
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+
+
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+ config-FS.h
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+
+
+ config-RTX-TCP-FS.h
+ 5
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+
+
+ config-BARE-METAL.h
+ 5
+ ..\MDK-ARM\CyaSSL\config-BARE-METAL.h
+
+
+ startup_LPC43xx.s
+ 2
+ ..\LPC43xx\startup_LPC43xx.s
+
+
+
+
+ CyaSSL-MDK
+
+
+ cyassl_MDK_ARM.c
+ 1
+ ..\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
+
+
+ Retarget.c
+ 1
+ ..\MDK-ARM\CyaSSL\Retarget.c
+
+
+ time-LCP43xx.c
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+ ..\LPC43xx\time-LCP43xx.c
+
+
+
+
+
+
+
+
diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt
index 49b94308c..11abf9df1 100644
--- a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt
+++ b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvopt
@@ -75,7 +75,7 @@
0
1
- 255
+ 0
SARMCM3.DLL
-MPU
@@ -138,7 +138,7 @@
0
ULP2CM3
- -UP1135060 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS0 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000
+ -UP1135060 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS7 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000
@@ -227,11 +227,11 @@
0
- 1
+ 0
0
0
- 255
+ 0
SARMCM3.DLL
-MPU
@@ -294,7 +294,7 @@
0
ULP2CM3
- -UP1135060 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS0 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000
+ -UP1135060 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS7 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000
@@ -383,11 +383,11 @@
0
- 1
+ 0
0
0
- 255
+ 0
SARMCM3.DLL
-MPU
@@ -450,7 +450,7 @@
0
ULP2CM3
- -UP1135060 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS0 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000
+ -UP1135060 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO23 -TC10000000 -TP18 -TDX0 -TDD0 -TDS7 -TDT0 -TDC1F -TIEFFFFFFFF -TIP0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000
@@ -478,7 +478,7 @@
0
0
1
- 1
+ 0
0
0
0
@@ -490,7 +490,7 @@
CyaSSL Apps
- 1
+ 0
0
0
0
@@ -598,8 +598,8 @@
0
0
0
- 387
- 396
+ 0
+ 0
0
..\MDK-ARM\CyaSSL\shell.c
shell.c
@@ -614,8 +614,8 @@
0
0
0
- 209
- 220
+ 143
+ 149
0
..\MDK-ARM\CyaSSL\main.c
main.c
@@ -762,7 +762,7 @@
MDK-ARM
- 1
+ 0
0
0
0
@@ -774,8 +774,8 @@
0
0
0
- 42
- 66
+ 0
+ 0
0
c:\Keil\ARM\Boards\Keil\MCBSTM32F200\RL\FlashFS\SD_File\Serial.c
Serial.c
@@ -898,7 +898,7 @@
CyaSSL Library
- 1
+ 0
0
0
0
@@ -1050,7 +1050,7 @@
Crypt/Cipher Library
- 1
+ 0
0
0
0
@@ -1538,7 +1538,7 @@
Configuration
- 1
+ 0
0
0
0
@@ -1628,7 +1628,7 @@
5
0
0
- 18
+ 0
0
0
0
@@ -1644,7 +1644,7 @@
5
0
0
- 18
+ 0
0
0
0
@@ -1660,7 +1660,7 @@
5
0
0
- 18
+ 0
0
0
0
@@ -1678,7 +1678,7 @@
0
0
0
- 165
+ 163
169
0
..\MDK-ARM\config\startup_stm32f2xx.s
@@ -1698,12 +1698,12 @@
7
73
1
- 1
+ 0
0
0
0
- 200
- 216
+ 172
+ 182
0
..\MDK-ARM\CyaSSL\cyassl_MDK_ARM.c
cyassl_MDK_ARM.c
@@ -1714,18 +1714,34 @@
7
74
1
- 1
+ 0
0
0
0
- 52
- 56
+ 50
+ 57
0
..\MDK-ARM\CyaSSL\Retarget.c
Retarget.c
0
0
+
+ 7
+ 75
+ 1
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ 0
+ ..\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+ time-STM32F2xx.c
+ 0
+ 0
+
diff --git a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj
index 20def53d7..222ef456f 100644
--- a/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj
+++ b/IDE/MDK-ARM/Projects/MDK-ARM-STM32F2xx.uvproj
@@ -44,7 +44,7 @@
1
.\MDK-RTX-TCP-FS\
- MDK-RTX-TCP-FS
+ STM32F2xx-MDK-RTX-TCP-FS
1
0
0
@@ -349,7 +349,7 @@
0
- HAVE_CONFIG_H __DBG_ITM __RTX USE_STDPERIPH_DRIVER MDK_CONF_RTX_TCP_FS
+ HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM __RTX USE_STDPERIPH_DRIVER MDK_CONF_RTX_TCP_FS
..\MDK-ARM\CyaSSL;C:..\STM32F2xx_StdPeriph_Lib\inc;..\..\..\
@@ -930,6 +930,11 @@
1
..\MDK-ARM\CyaSSL\Retarget.c
+
+ time-STM32F2xx.c
+ 1
+ ..\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+
@@ -972,7 +977,7 @@
1
.\MDK-FS\
- MDK-FS
+ STM32F2xx-MDK-FS
1
0
0
@@ -1277,7 +1282,7 @@
0
- HAVE_CONFIG_H __DBG_ITM USE_STDPERIPH_DRIVER MDK_CONF_FS
+ HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM USE_STDPERIPH_DRIVER MDK_CONF_FS
..\MDK-ARM\CyaSSL;..\MDK-ARM\inc;..\STM32F2xx_StdPeriph_Lib\inc;..\POSIX\..\..\..\
@@ -2134,6 +2139,11 @@
1
..\MDK-ARM\CyaSSL\Retarget.c
+
+ time-STM32F2xx.c
+ 1
+ ..\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+
@@ -2176,7 +2186,7 @@
1
.\MDK-BARE-METAL\
- MDK-BARE-METAL
+ STM32F2xx-MDK-BARE-METAL
1
0
0
@@ -2481,7 +2491,7 @@
0
- HAVE_CONFIG_H __DBG_ITM USE_STDPERIPH_DRIVER MDK_CONF_BARE_METAL
+ HAVE_CONFIG_H CYASSL_STM32F2xx __DBG_ITM USE_STDPERIPH_DRIVER MDK_CONF_BARE_METAL
..\MDK-ARM\CyaSSL;..\MDK-ARM\inc;..\STM32F2xx_StdPeriph_Lib\inc;..\POSIX;..\..\..\
@@ -3556,6 +3566,11 @@
1
..\MDK-ARM\CyaSSL\Retarget.c
+
+ time-STM32F2xx.c
+ 1
+ ..\STM32F2xx_StdPeriph_Lib\time-STM32F2xx.c
+
diff --git a/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c b/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c
new file mode 100644
index 000000000..66940453a
--- /dev/null
+++ b/IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c
@@ -0,0 +1,185 @@
+/* main.c
+ *
+ * Copyright (C) 2006-2013 wolfSSL Inc.
+ *
+ * This file is part of CyaSSL.
+ *
+ * CyaSSL is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * CyaSSL is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+ */
+
+#ifdef HAVE_CONFIG_H
+ #include
+#endif
+
+#include "time.h"
+#include "stm32f2xx_tim.h"
+#include "stm32f2xx_rcc.h"
+
+
+/*-----------------------------------------------------------------------------
+ * initialize RTC
+ *----------------------------------------------------------------------------*/
+#include "stm32f2xx_rtc.h"
+#include "stm32f2xx_rcc.h"
+#include "stm32f2xx_pwr.h"
+
+static init_RTC()
+{
+ RTC_InitTypeDef RTC_InitStruct ;
+
+ RTC_TimeTypeDef RTC_Time ;
+ RTC_DateTypeDef RTC_Date ;
+
+
+ /* Enable the PWR clock */
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
+
+ /* Allow access to RTC */
+ PWR_BackupAccessCmd(ENABLE);
+
+/***Configures the External Low Speed oscillator (LSE)****/
+
+ RCC_LSEConfig(RCC_LSE_ON);
+
+ /* Wait till LSE is ready */
+ while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
+ {
+ }
+
+ /* Select the RTC Clock Source */
+ RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
+
+ /* Enable the RTC Clock */
+ RCC_RTCCLKCmd(ENABLE);
+
+ /* Wait for RTC APB registers synchronisation */
+ RTC_WaitForSynchro();
+
+ /* Calendar Configuration with LSI supposed at 32KHz */
+ RTC_InitStruct.RTC_AsynchPrediv = 0x7F;
+ RTC_InitStruct.RTC_SynchPrediv = 0xFF;
+ RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24;
+ RTC_Init(&RTC_InitStruct);
+
+ RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
+ RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
+}
+
+/*-----------------------------------------------------------------------------
+ * initialize TIM
+ *----------------------------------------------------------------------------*/
+static void init_TIM()
+{
+ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure ;
+
+ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) ;
+
+ TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
+ TIM_TimeBaseStructure.TIM_Prescaler = 60;
+ TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
+ TIM_TimeBaseStructure.TIM_Period = 0xffffffff;
+ TIM_TimeBaseStructure.TIM_ClockDivision = 0;
+ TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
+
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
+
+ TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure) ;
+ TIM_Cmd(TIM2, ENABLE) ;
+}
+
+void init_time(void) {
+ init_RTC() ;
+ init_TIM() ;
+}
+
+struct tm *Cyassl_MDK_gmtime(const time_t *c)
+{
+
+ RTC_TimeTypeDef RTC_Time ;
+ RTC_DateTypeDef RTC_Date ;
+ static struct tm date ;
+
+ RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
+ RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
+
+ date.tm_year = RTC_Date.RTC_Year + 100 ;
+ date.tm_mon = RTC_Date.RTC_Month - 1 ;
+ date.tm_mday = RTC_Date.RTC_Date ;
+ date.tm_hour = RTC_Time.RTC_Hours ;
+ date.tm_min = RTC_Time.RTC_Minutes ;
+ date.tm_sec = RTC_Time.RTC_Seconds ;
+
+ #if defined(DEBUG_CYASSL)
+ {
+ char msg[100] ;
+ sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n",
+ RTC_Date.RTC_Year+2000, RTC_Date.RTC_Month, RTC_Date.RTC_Date,
+ RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
+ CYASSL_MSG(msg) ;
+ }
+ #endif
+
+ return(&date) ;
+}
+
+double current_time()
+{
+ return ((double)TIM2->CNT/1000000.0) ;
+}
+
+typedef struct func_args {
+ int argc;
+ char** argv;
+ int return_code;
+} func_args;
+
+
+#include
+
+void time_main(void *args)
+{
+ char * datetime ;
+ RTC_TimeTypeDef RTC_Time ;
+ RTC_DateTypeDef RTC_Date ;
+ int year ;
+ if( args == NULL || ((func_args *)args)->argc == 1) {
+ RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
+ RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
+ printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
+ RTC_Date.RTC_Month, RTC_Date.RTC_Date, RTC_Date.RTC_Year+2000,
+ RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
+ } else if(((func_args *)args)->argc == 3 &&
+ ((func_args *)args)->argv[1][0] == '-' &&
+ ((func_args *)args)->argv[1][1] == 'd' ) {
+ datetime = ((func_args *)args)->argv[2];
+ sscanf(datetime, "%d/%d/%d",
+ (int *)&RTC_Date.RTC_Month, (int *)&RTC_Date.RTC_Date, &year) ;
+ RTC_Date.RTC_Year = year - 2000 ;
+ RTC_Date.RTC_WeekDay = 0 ;
+ RTC_SetDate(RTC_Format_BIN, &RTC_Date) ;
+ } else if(((func_args *)args)->argc == 3 &&
+ ((func_args *)args)->argv[1][0] == '-' &&
+ ((func_args *)args)->argv[1][1] == 't' ) {
+ datetime = ((func_args *)args)->argv[2];
+ sscanf(datetime, "%d:%d:%d",
+ (int *)&RTC_Time.RTC_Hours,
+ (int *)&RTC_Time.RTC_Minutes,
+ (int *)&RTC_Time.RTC_Seconds
+ ) ;
+ RTC_SetTime(RTC_Format_BIN, &RTC_Time) ;
+ } else printf("Invalid argument\n") ;
+}
+
+
diff --git a/ctaocrypt/src/random.c b/ctaocrypt/src/random.c
index f76abf002..fb99c0c58 100644
--- a/ctaocrypt/src/random.c
+++ b/ctaocrypt/src/random.c
@@ -23,8 +23,6 @@
#include
#endif
-#include
-
/* on HPUX 11 you may need to install /dev/random see
http://h20293.www2.hp.com/portal/swdepot/displayProductInfo.do?productNumber=KRNG11I
@@ -39,6 +37,7 @@
#ifdef NO_INLINE
#include
#else
+ #define MISC_DUMM_FUNC misc_dummy_random
#include
#endif
#endif
@@ -60,7 +59,6 @@
#endif
#endif /* USE_WINDOWS_API */
-#if !defined( NO_CYASSL_RANDOM )
#ifdef NO_RC4
@@ -569,10 +567,20 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
return 0;
}
+#elif defined(CYASSL_LPC43xx) || defined(CYASSL_STM32F2xx)
+ #warning "write a real random seed!!!!, just for testing now"
+ int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
+ {
+ int i;
+ for (i = 0; i < sz; i++ )
+ output[i] = i;
+ return 0;
+ }
#elif defined(NO_DEV_RANDOM)
#error "you need to write an os specific GenerateSeed() here"
+
/*
int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
{
@@ -580,6 +588,7 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
}
*/
+
#else /* !USE_WINDOWS_API && !THREADX && !MICRIUM && !NO_DEV_RANDOM */
@@ -622,4 +631,3 @@ int GenerateSeed(OS_Seed* os, byte* output, word32 sz)
#endif /* USE_WINDOWS_API */
-#endif /* NO_CYASSL_RANDOM */
diff --git a/examples/client/client.c b/examples/client/client.c
index 66b89206a..78c63ba1c 100644
--- a/examples/client/client.c
+++ b/examples/client/client.c
@@ -133,6 +133,9 @@ static void Usage(void)
printf("-S Use Host Name Indication\n");
}
+#ifdef CYASSL_MDK_SHELL
+#define exit(code) return(code)
+#endif
#ifdef CYASSL_MDK_SHELL
#define exit(code) return(code)