From 9b7caac3efe05bacaea35423c98e788daa1ce7d0 Mon Sep 17 00:00:00 2001 From: Hideki Miyazaki Date: Sat, 26 Jul 2025 18:35:44 +0900 Subject: [PATCH 1/4] Update RZ examples - Use xSPI0 boot mode - Update FSP from v1.3 to v2.0.0 - Simplify UART - Migrate new User Ctx - Update README - Fix SCE TLS on RA6M4 --- IDE/Renesas/e2studio/RZN2L/README.md | 182 ++++++++++--- .../e2studio/RZN2L/common/user_settings.h | 6 + IDE/Renesas/e2studio/RZN2L/include.am | 2 +- IDE/Renesas/e2studio/RZN2L/test/.cproject | 83 +++++- .../RZN2L/test/script/fsp_ram_execution.ld | 243 ------------------ .../RZN2L/test/src/local_system_init.c | 54 ++++ .../RZN2L/test/src/rzn2l_tst_thread_entry.c | 106 ++++---- .../RZN2L/test/src/serial_io/.gitignore | 2 - .../RZN2L/test/src/serial_io/app_print.c | 83 ++++++ .../test/src/test/wolfssl_rsip_unit_test.c | 41 +-- .../e2studio/RZN2L/test/src/wolfssl_dummy.c | 25 +- wolfcrypt/src/port/Renesas/renesas_common.c | 89 +++++-- .../src/port/Renesas/renesas_fspsm_aes.c | 178 +++++++++++-- .../src/port/Renesas/renesas_fspsm_sha.c | 142 +++++++++- .../src/port/Renesas/renesas_fspsm_util.c | 5 + .../src/port/Renesas/renesas_tsip_util.c | 2 +- wolfcrypt/src/sha.c | 1 + wolfcrypt/src/sha256.c | 3 +- wolfcrypt/src/sha512.c | 6 +- wolfcrypt/test/test.c | 2 +- .../port/Renesas/renesas-fspsm-crypt.h | 6 +- .../port/Renesas/renesas-fspsm-types.h | 17 +- .../port/Renesas/renesas_fspsm_internal.h | 15 +- wolfssl/wolfcrypt/sha.h | 2 +- 24 files changed, 870 insertions(+), 425 deletions(-) delete mode 100644 IDE/Renesas/e2studio/RZN2L/test/script/fsp_ram_execution.ld create mode 100644 IDE/Renesas/e2studio/RZN2L/test/src/local_system_init.c delete mode 100644 IDE/Renesas/e2studio/RZN2L/test/src/serial_io/.gitignore create mode 100644 IDE/Renesas/e2studio/RZN2L/test/src/serial_io/app_print.c diff --git a/IDE/Renesas/e2studio/RZN2L/README.md b/IDE/Renesas/e2studio/RZN2L/README.md index c53605b79..40fc58522 100644 --- a/IDE/Renesas/e2studio/RZN2L/README.md +++ b/IDE/Renesas/e2studio/RZN2L/README.md @@ -21,37 +21,49 @@ The example project summary is listed below and is relevant for every project. ### Project Summary |Item|Name/Version| |:--|:--| +|e2Studio|2025-04.1 (25.4.1)| |Board|RZN2L| |Device|R9A07G084M08GBG| |Toolchain|GCC for Renesas RZ| |Toolchain Version|10.3.1.20210824| -|FSP Version|1.2.0| +|FSP Version|2.0.0| #### Selected software components |Components|Version|Note| |:--|:--|:--| -|Board Support Package Common Files|v1.20|| -|I/O Port|v1.2.0|| -|Arm CMSIS Version 5 - Core (M)|v5.7.0+renesas.1|| -|Board support package for R9A07G084M04GBG|v1.2.0|Note1| -|Board support package for RZN2L|v1.2.0|| -|Board support package for RZN2L - FSP Data|v1.2.0|| -|RSK+RZN2L Board Support Files (RAM execution without flash memory)|v1.2.0|| -|FreeRTOS - Buffer Allocation 2|v1.2.0|| -|FreeRTOS - Memory Management - Heap 4|v1.2.0|| -|FreeRTOS+TCP|v1.2.0|| -|Ethernet PHY |v1.2.0|| -|Ethernet Selector|v1.2.0|| -|Ethernet|v1.2.0|| -|Ethernet Switch|v1.2.0|| -|SCI UART|v1.2.0|| -|r_ether to FreeRTOS+TCP Wrapper|v1.2.0|| -|Renesas Secure IP Driver|v1.3.0+fsp.1.2.0|Need to contact Renesas to get RSIP module| -|RSIP Engine for RZ/N2L|v1.3.0+fsp.1.2.0|Need to contact Renesas to get RSIP module| +|Board Support Package Common Files|v2.0.0|| +|I/O Port|v2.0.0|| +|Arm CMSIS Version 5 - Core (M)|v5.7.0+renesas.1.fsp.2.0.0|| +|Board support package for R9A07G084M04GBG|v2.0.0|Note1| +|Board support package for RZN2L|v2.0.0|| +|Board support package for RZN2L - FSP Data|v2.0.0|| +|RSK+RZN2L Board Support Files (xSPI0 x1 boot mode)|v2.0.0|| +|FreeRTOS - Buffer Allocation 2|v2.0.0|| +|FreeRTOS - Memory Management - Heap 4|v2.0.0|| +|FreeRTOS+TCP|v2.0.0|| +|Ethernet PHY |v2.0.0|| +|Ethernet Selector|v2.0.0|| +|Ethernet|v2.0.0|| +|Ethernet Switch|v2.0.0|| +|SCI UART|v2.0.0|| +|r_ether to FreeRTOS+TCP Wrapper|v2.0.0|| +|Renesas Secure IP Driver|v1.5.0+fsp.1.3.0|| +|RSIP Engine for RZ/N2L|v1.5.0+fsp.1.3.0|| Note1:\ - To use RSIP driver, a device type should be `R9A07G084M04GBG`. However, choosing `R9A07G084M04GBG` won't allow to select `RSK+RZN2L` board. This example uses LED and external flash memory on `RSK + RZN2L` board. Therefore, the example temporary `R9A07G084M04GBG` for the device type. Updating e2studio or fsp could resolve the issue. + To use RSIP driver, a device type should be `R9A07G084M08GBG`. However, choosing `R9A07G084M04GBG` won't allow to select `RSK+RZN2L` board. This example uses LED and external flash memory on `RSK + RZN2L` board. Therefore, the example temporary `R9A07G084M04GBG` for the device type. Updating e2studio or fsp could resolve the issue. + +## Board Settings +This example program uses `xSPI0 boot`. Therefore, the board's switch and jumper settings required to run the sample program from external flash are shown below. For details on each setting, see the Renesas Starter Kit+ for RZN2L User's Manual. + +|Project|SW4-1|SW4-2|SW4-3|SW4-4|SW4-7| +|:--|:--|:--|:--|:--|:--| +|xSPI0 boot mode|ON|ON|ON|ON|OFF| + +|Project|CN8|CN24| +|:--|:--|:--| +|xSPI0 boot mode|Short 2-3|Short2-3| ## Setup Steps and Build wolfSSL Library @@ -63,7 +75,7 @@ Note1:\ + Click File->New->`RZ/N C/C++ FSP Project`. + Enter project name `dummy_application`. -+ Select Board: to `RSK+RZN2L (RAM execution without flash memory)`. ++ Select Board: to `RSK+RZN2L (xSPI0 x1 boot mode)`. + Select Device: to `R9A07G084M04GBG`. Click Next. + Check to `Executable` + Select FreeRTOS from RTOS selection. Click Finish. @@ -93,31 +105,125 @@ Note1:\ + Click `Generate Project Content` on FSP configuration GUI 3.) Prepare UART to logging - -+ Download Sample package from [BACnet Start-Up](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/bacnet-start-rzn2l-rsk) ++ Download Example packages from [RZ/N2L Group Example program](https://www.renesas.com/us/en/document/scd/rzn2l-group-example-program?r=1622651) and unzip the archived file. ++ unzip RZN2L_RSK_sci_uart_Rev200.zip ++ unzip RZN2L_RSK_sci_uart_Rev200/basis/gcc/RZN2L_RSK_sci_uart_Rev200a.zip ++ + Copy the following C source files from the project to src/serial_io folder of `test_RZN2L`\ -um_serial_io_uart.c\ -um_serial_io_task_writer.c\ -um_serial_io_cfg.h\ -um_common_api.h\ -um_common_cfg.h\ -um_serial_io.c\ -um_serial_io.h\ -um_serial_io_api.h\ -um_serial_io_internal.h +sio_char.h\ +siochar.c +4.) Prepare loader project ++ Download Example packages from [RZ/N2L Group Example of separating loader program and application program projects](https://www.renesas.com/en/document/scd/11691006?language=en&r=1622651) and unzip the archived file. ++ Unzip `RZN2L_loader_application\gcc\xspi0bootx1\Loader_application_projects.zip ++ Copy `RZN2L_bsp_xspi0bootx1_loader` and `RZN2L_bsp_xspi0bootx1_app` to `\IDE\Renesas\e2studio\RZN2L` folder ++ Import `RZN2L_bsp_xspi0bootx1_loader` from `e2studio` -+ Open um_serial_io_task_writer.c and re-name printf to uart_printf +## Build `test_RZN2L` +1). Modify `fsp/src/bsp/cmsis/Device/RENESAS/Source/cr/startup_core.c`: +ORIGINAL +``` +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors (void) +{ + __asm volatile ( + " ldr pc,=Reset_Handler \n" +``` +==> -3.) Build `test_RZN2L` project +MODIFIED +``` +BSP_TARGET_ARM BSP_ATTRIBUTE_STACKLESS void __Vectors (void) +{ + __asm volatile ( +#if 0 + " ldr pc,=Reset_Handler \n" +#else + " ldr pc,=local_system_init \n" +#endif +``` +1). Modify `fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c`: -## Run `test_RZN2L` +ORIGINAL +``` +void SystemInit (void) +{ +#if BSP_CFG_EARLY_INIT +... +#if BSP_CFG_C_RUNTIME_INIT -1). Right click the project and Select menu `Debug` -> `Renesas GDB Hardware debugging` + /* Copy the loader data from external Flash to internal RAM. */ + bsp_loader_data_init(); -2). Select J-Link ARM and R9A07G084M04 + /* Clear loader bss section in internal RAM. */ + bsp_loader_bss_init(); +#endif +... +#if !(BSP_CFG_RAM_EXECUTION) -3). Break at Entry point. Change `cpsr` register value from 0xXXXXX1yy to 0xXXXXX1da + /* Copy the application program from external Flash to internal RAM. */ + bsp_copy_to_ram(); + + /* Clear bss section in internal RAM. */ + bsp_application_bss_init(); +#endif +... +} +``` + +==> + +MODIFIED +``` +BSP_TARGET_ARM void mpu_cache_init (void) +{ +... +if BSP_CFG_C_RUNTIME_INIT && !defined(EXTERNAL_LOADER_APP) + + /* Copy the loader data from external Flash to internal RAM. */ + bsp_loader_data_init(); + + /* Clear loader bss section in internal RAM. */ + bsp_loader_bss_init(); +#endif +... +#if !(BSP_CFG_RAM_EXECUTION) && !defined(EXTERNAL_LOADER_APP) + + /* Copy the application program from external Flash to internal RAM. */ + /* bsp_copy_to_ram(); */ + + /* Clear bss section in internal RAM. */ + bsp_application_bss_init(); +#endif +... +} +``` +2). Copy contenst of `fsp_xspi0_boot_app.ld` of `RZN2L_bsp_xspi0bootx1_app\script\` to `test_RZN2L\script\fsp_xspi0_boot.ld` + +3). Right click the project and Select menu `Debug` -> `Renesas GDB Hardware debugging` + +4). Select J-Link ARM and R9A07G084M04 +5). Build `test_RZN2L` + +## Build loader project ++ Modify `src/Flash_section.s`: + +ORIGINAL +``` +.incbin "../../RZN2L_bsp_xspi0bootx1_app/Debug/RZN2L_bsp_xspi0bootx1_app.bin" +``` + +==> + +MODIFIED +``` +.incbin "../../test/Debug/test_RZN2L.bin" +``` ++ Modify `Load Image and Symbol`. Open `Debug Configuration` -> Open `Statup` tab -> Replace `RZN2L_bsp_xspi0bootx1_app.elf` to `test_RZN2L.elf` + +## Run loader and `test_RZN2L` ++ Run the loader project ++ Loader download `test_RZN2L` binary from flash to system ram and execute it. ++ Note: It recommends to re-build the loader project when re-building `test_RZN2L` ## Run TLS 1.3 Client 1.) Enable `WOLFSSL_TLS13` macro in `user_settings.h` diff --git a/IDE/Renesas/e2studio/RZN2L/common/user_settings.h b/IDE/Renesas/e2studio/RZN2L/common/user_settings.h index 345f9b150..8aa255aea 100644 --- a/IDE/Renesas/e2studio/RZN2L/common/user_settings.h +++ b/IDE/Renesas/e2studio/RZN2L/common/user_settings.h @@ -20,6 +20,7 @@ */ /* Operating Environment and Threading */ #if defined(WOLFSSL_RENESAS_RSIP) + #define WOLFSSL_RENESAS_RZFSP_VER 200 /* FSP SM stands for Flexible Software Package Security Module * WOLFSSL_RENESAS_FSPSM enables fundamental code when it uses. * e.g. Open/Close/Random generator @@ -104,7 +105,9 @@ #endif #if defined(WOLFSSL_RENESAS_RSIP_CRYPTONLY) + #define WOLF_CRYPTO_CB_RSA_PAD #define WOLFSSL_KEY_GEN + #define RSA_MIN_SIZE 512 #endif int uart_printf (const char *__restrict format, ...); @@ -112,4 +115,7 @@ int uart_printf (const char *__restrict format, ...); #define printf uart_printf #define TEST_SLEEP() vTaskDelay(50) +#if defined(WOLFSSL_RENESAS_RSIP) #define CUSTOM_RAND_GENERATE_BLOCK wc_fspsm_GenerateRandBlock +#endif + diff --git a/IDE/Renesas/e2studio/RZN2L/include.am b/IDE/Renesas/e2studio/RZN2L/include.am index 88ccadfc7..7e1cc471f 100644 --- a/IDE/Renesas/e2studio/RZN2L/include.am +++ b/IDE/Renesas/e2studio/RZN2L/include.am @@ -10,7 +10,7 @@ EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/wolfssl_dummy.c EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/test/wolf_client.c EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/test/wolf_server.c EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/test/wolfssl_rsip_unit_test.c -EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/serial_io/.gitignore +EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/serial_io/app_print.c EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/wolfCrypt/.gitignore EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/test/src/wolfSSL/.gitignore EXTRA_DIST+= IDE/Renesas/e2studio/RZN2L/common/wolfssl_demo.h diff --git a/IDE/Renesas/e2studio/RZN2L/test/.cproject b/IDE/Renesas/e2studio/RZN2L/test/.cproject index 98caa7842..561cbf7d7 100644 --- a/IDE/Renesas/e2studio/RZN2L/test/.cproject +++ b/IDE/Renesas/e2studio/RZN2L/test/.cproject @@ -43,7 +43,7 @@ @@ -154,7 +184,7 @@