BN APIs from ssl.c have been moved out to ssl_bn.c that is included in
ssl.c.
Added defines for BN_rand() and BN_pseudo_rand() to indicate which bits
are to be set.
'internal' field now always maps to the ;mpi' field that is a MP
integer.
SetIndividualInternal/External renamed to wolfssl_bn_get/set_value.
Fixed BN APIs to work as closely to OpenSSL as possible.
Added tests.
Moved wolfssl_make_rng out to ssl.c as BN APIs are using it now.
SP int and TFM now check trials are in a valid range for
mp_prime_is_prime_ex().
configure.ac: remove implied --disable-examples when --disable-inline;
tests/api.c: always include wolfcrypt/src/misc.c;
wolfcrypt/src/misc.c: use WC_MISC_STATIC to designate staticness of the misc functions;
wolfssl/wolfcrypt/misc.h: define WC_MISC_STATIC to empty or static depending on #ifdef NO_INLINE or not (respectively);
wolfssl/wolfcrypt/types.h: #ifdef NO_INLINE, #define WC_INLINE WC_MAYBE_UNUSED, and move the definitions of WARN_UNUSED_RESULT and WC_MAYBE_UNUSED above the definition of WC_INLINE for clarity;
wolfssl/wolfcrypt/mem_track.h: always declare TrackMalloc() et al static (no functional change, because the state and callback bindings were and remain unconditionally static, but previously #ifdef NO_INLINE the functions were globals, leading to multiple definitions.
Made the following updates based on review feedback
Fixed mixed variable declaration and simplified cases by typedefing
wolfssl_RX64_HW_Hash to wc_Sha, wc_Sha224, & wc_Sha256
Added files to include.am so they are built when using make
Add WOLFSSL_RENESAS_RX64_HASH to settings.h and set WOLFSSL_NO_HASH_RAW
in settings.h based on value of WOLFSSL_RENESAS_RX64_HASH
Add and handle return value for rx64_hw_Open
Fix some minor formatting and comments
Adding support for SHA1, SHA224, and SHA256 hardware acceleration on
Renesas RX64 and RX71 microcontrollers.
This follows the a similar pattern as the Renesas TSIP support.
Speed comparison for hashing 64KB of data on a RX64M
| Hash Speed | SHA1 | SHA256 |
|:----------:|:----:|:------:|
| Hardware | 4ms | 4ms |
| Software | 11ms | 89ms |
Update define for RX64/RX71 SHA hardware support
This will allow for different hardware acceleration modules to be
enabled individually.
Init & Close for the RX64/RX71 SHA subsystem for WolfCrypt
This ensures that the SHA subsystem is ready for use when WolfCrypt
needs access to it.
Shorten the max line length, clean up comments
This wraps code and comments at 80 characters and adds some comments
SP ECC signing code was generating signatures with r of 0.
This is not allowed by the algorithm description.
Retry sig gen when r is 0 like when s is 0.
* Support rwlock
* Fix typo, ENABLE_SESSION_CACHE_ROW_LOCK with TITAN_SESSION_CACHE
* Implement read lock
- Use read lock for the SessionCache
- Don't copy the
* TLS 1.3: Don't push ticket to cache if we don't retrieve from it
* Detect rwlock support with PTHREAD_RWLOCK_INITIALIZER
* Implement explicit rwlocks
- Mutex's still necessary for signals. Implement explicit rwlocks and we can migrate critical mutexs to rwlocks when necessary.
* Remove WOLFSSL_USE_RWLOCK guard around mutex condLock
* condLock not necessary after all
* Use configure.ac to check for pthread_rwlock_destroy support
* Can't include config.h in wc_port.h as that breaks make distcheck
* Check for pthread_rwlock_t to determine if rwlock is available
* Code review
---------
Co-authored-by: Juliusz Sosinowicz <juliusz@wolfssl.com>
* set the client state correctly when wc_ecc_ctx_set_kdf_salt is called
* add test that covers wc_ecc_ctx_set_kdf_salt
* use shared key and smallstack to reduce test stack usage
Add NIDs for RSA-PSS to OpenSSL compat layer.
Have wc_RsaPublicKeyDecode call wc_RsaPublicKeyDecode_ex where logic for
RSA-PSS handling is already done.
