Sean Parkinson 018e937a91 RISC-V ASM unaligned read/writes: alternative assembly ...

Not all RISC-V chips allow unaligned reads and writes with basic
assembly instructions like lw/sw.
Add alternative assembly that is turned on with:
WOLFSSL_RISCV_ASM_NO_UNALIGNED.

2026-05-29 10:11:12 +10:00

..

benchmark

Merge pull request #10448 from SparkiDev/lms_fixes_1

2026-05-12 09:26:42 -07:00

src

RISC-V ASM unaligned read/writes: alternative assembly

2026-05-29 10:11:12 +10:00

test

Rename ML-DSA wc_PqcSignatureType entry

2026-05-20 09:06:54 -07:00