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Daniele Lacamera
a9212acce9
Upstream added an AVX512 arm above the AVX2 one, and the ladder only ever cleared AVX2/BMI2 -- so the AVX512 arm won every row and the arms below it stopped being reached, costing 64 conditions. Three fixes: USE_INTEL_AVX512() is IS_INTEL_AVX512() && IS_INTEL_AVX512_BW(), so the F and BW bits are now cleared separately to give that decision's three operands their own rows; a row clears AVX512_VBMI for the new VBMI arm; and CPUID_INTEL is forced on, because SHA3_USE_AVX2() is gated on IS_CPU_INTEL() and its true side is otherwise unreachable on an AMD host. Rows can now set bits as well as clear them. wc_mldsa.c 292/579 -> 463/579.
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