Files
wolfssl/IDE/XilinxSDK/2022_1/wolfCrypt_example_system/.project
Steffen Jaeckel 0e57e9858f Integrate Xilinx Versal
* add Versal specific glue
   The same structure of an "XSecure client" is used throughout the API's,
   therefor define it once and re-use in all clients.
* integrate Versal AES-GCM engine
* integrate Versal SHA3-384 engine
* add versal support to tests
  - There's no intermediate-hash API for Versal.
* add specific test with large AAD
   Test only with `n*16 byte` wide chunks of AAD, so it gets processed in the
   hardware engine.
* add specific test with misaligned AES-GCM arguments
* integrate Versal RSA engine
* disable failing RSA test-case when Xilinx Crypto is enabled
* introduce define `WOLFSSL_XILINX_CRYPT_VERSAL`
* integrate Versal TRNG engine
* allow using Versal TRNG w/o wolfcrypt DRBG
   Versal TRNG already provides a HRNG mode which does the same as the
   wolfcrypt DRBG implementation.
* add support for user-supplied nonce to Versal TRNG
* add `wc_XsecureErrorToString()` to map PLM error codes to messages.
* integrate Versal EcDSA engine
* update tests to work with Versal EcDSA
   If deterministic K is enabled, the tests failed here since the Versal
   EcDSA engine doesn't support the SECP256R1 curve yet.
* Xilinx crypto engines like aligned memory very much
   Make this a default choice, not via the user configuration.
* add Xilinx-specific `WOLFSSL_MSG()` equivalent
   `WOLFSSL_XIL_MSG()` does the same as `WOLFSSL_MSG()` besides waiting for
   1 second before printing to stdout, since the PLM maybe prints to same and
   outputs would be mixed up.
   This waiting can be disabled by defining `WOLFSSL_XIL_MSG_NO_SLEEP`.
* add option to enable DPA CounterMeasures in AES-GCM crypto engine
* add "command mode" to Xilinx bare-metal example
* update Xilinx default user settings
* add script to execute benchmarks
* add scripts to create graphics
* add Vitis 2022.1 example projects

Signed-off-by: Steffen Jaeckel <jaeckel-floss@eyet-services.de>
2022-09-29 09:39:57 -06:00

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