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320afab227
--enable-sp --enable-sp-asm --disable-fastmath:
cpuid.h - check for WOLFSSL_SP_ASM as well
-enable-curve448 --enable-ed448 --disable-rsa --disable-dh
--enable-tls13 --disable-ecc --enable-certgen --enable-keygen:
api.c - certificate loaded that was RSA but RSA disabled
--enable-sp --enable-sp-asm --enable-sp-math:
cpuid.c - check for WOLFSSL_SP_ASM as well
--disable-shared --disable-ecc --disable-dh --enable-cryptonly
--enable-rsavfy --disable-asn --disable-rng --disable-filesystem:
test.c - rsa_test()
'CC=clang -fsanitize=address' '-enable-distro' '--enable-stacksize':
testsuit.c - echoclient_test_wrapper needs to free ECC FP cache when
it is in a separate thread
128 lines
3.7 KiB
C
128 lines
3.7 KiB
C
/* cpuid.c
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*
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* Copyright (C) 2006-2020 wolfSSL Inc.
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*
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* This file is part of wolfSSL.
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*
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* wolfSSL is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* wolfSSL is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
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*/
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#ifdef HAVE_CONFIG_H
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#include <config.h>
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#endif
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#include <wolfssl/wolfcrypt/settings.h>
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#include <wolfssl/wolfcrypt/cpuid.h>
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#if (defined(WOLFSSL_X86_64_BUILD) || defined(USE_INTEL_SPEEDUP) || \
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defined(WOLFSSL_AESNI) || defined(WOLFSSL_SP_ASM)) && \
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!defined(WOLFSSL_NO_ASM)
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/* Each platform needs to query info type 1 from cpuid to see if aesni is
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* supported. Also, let's setup a macro for proper linkage w/o ABI conflicts
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*/
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#ifndef _MSC_VER
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#define cpuid(reg, leaf, sub)\
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__asm__ __volatile__ ("cpuid":\
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"=a" (reg[0]), "=b" (reg[1]), "=c" (reg[2]), "=d" (reg[3]) :\
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"a" (leaf), "c"(sub));
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#define XASM_LINK(f) asm(f)
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#else
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#include <intrin.h>
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#define cpuid(a,b,c) __cpuidex((int*)a,b,c)
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#define XASM_LINK(f)
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#endif /* _MSC_VER */
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#define EAX 0
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#define EBX 1
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#define ECX 2
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#define EDX 3
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static word32 cpuid_check = 0;
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static word32 cpuid_flags = 0;
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static word32 cpuid_flag(word32 leaf, word32 sub, word32 num, word32 bit)
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{
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int got_intel_cpu = 0;
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int got_amd_cpu = 0;
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unsigned int reg[5];
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reg[4] = '\0';
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cpuid(reg, 0, 0);
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/* check for Intel cpu */
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if (XMEMCMP((char *)&(reg[EBX]), "Genu", 4) == 0 &&
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XMEMCMP((char *)&(reg[EDX]), "ineI", 4) == 0 &&
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XMEMCMP((char *)&(reg[ECX]), "ntel", 4) == 0) {
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got_intel_cpu = 1;
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}
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/* check for AMD cpu */
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if (XMEMCMP((char *)&(reg[EBX]), "Auth", 4) == 0 &&
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XMEMCMP((char *)&(reg[EDX]), "enti", 4) == 0 &&
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XMEMCMP((char *)&(reg[ECX]), "cAMD", 4) == 0) {
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got_amd_cpu = 1;
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}
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if (got_intel_cpu || got_amd_cpu) {
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cpuid(reg, leaf, sub);
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return ((reg[num] >> bit) & 0x1);
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}
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return 0;
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}
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void cpuid_set_flags(void)
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{
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if (!cpuid_check) {
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if (cpuid_flag(1, 0, ECX, 28)) { cpuid_flags |= CPUID_AVX1 ; }
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if (cpuid_flag(7, 0, EBX, 5)) { cpuid_flags |= CPUID_AVX2 ; }
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if (cpuid_flag(7, 0, EBX, 8)) { cpuid_flags |= CPUID_BMI2 ; }
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if (cpuid_flag(1, 0, ECX, 30)) { cpuid_flags |= CPUID_RDRAND; }
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if (cpuid_flag(7, 0, EBX, 18)) { cpuid_flags |= CPUID_RDSEED; }
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if (cpuid_flag(1, 0, ECX, 25)) { cpuid_flags |= CPUID_AESNI ; }
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if (cpuid_flag(7, 0, EBX, 19)) { cpuid_flags |= CPUID_ADX ; }
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if (cpuid_flag(1, 0, ECX, 22)) { cpuid_flags |= CPUID_MOVBE ; }
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cpuid_check = 1;
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}
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}
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word32 cpuid_get_flags(void)
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{
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if (!cpuid_check)
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cpuid_set_flags();
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return cpuid_flags;
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}
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void cpuid_select_flags(word32 flags)
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{
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cpuid_flags = flags;
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}
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void cpuid_set_flag(word32 flag)
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{
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cpuid_flags |= flag;
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}
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void cpuid_clear_flag(word32 flag)
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{
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cpuid_flags &= ~flag;
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}
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#endif
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