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Sean Parkinson ebb49b6e68 RISC-V ChaCha20: assembly implementations 
ChaCha20:
  scalar and vector implementations
  vector implementations doing 6, 4, 2, 1 block at a time.
  scalar implemetations using roriw and pack
  vector implementations using VROR_VI and roriw.

RISC-V SHA-256: avoid using s0 if it can be helped.
2024-08-01 17:51:59 +10:00
..
benchmark
update copyright to 2024
2024-07-19 13:15:05 -06:00
src
RISC-V ChaCha20: assembly implementations
2024-08-01 17:51:59 +10:00
test
RISC-V ChaCha20: assembly implementations
2024-08-01 17:51:59 +10:00