yath/ghidra-xtensa
1
0
Fork 1
mirror of https://github.com/yath/ghidra-xtensa.git synced 2025-07-31 17:34:31 +02:00
Code Issues Packages Projects Releases Wiki Activity

Truncate control flow after ILL

Browse Source 
GCC seems to insert a “DIV0” (in ASCII) after an ILL instruction, so
truncate control flow by looping endlessly.
This commit is contained in:
Sebastian Schmidt
2020-01-04 20:45:16 +01:00
parent 9a837fe2dd
commit f0faee57e4
1 changed files with 2 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
data/languages/xtensaInstructions.sinc
View File

@@ -480,11 +480,13 @@ macro extract_bit(val, bit, result) {
# ILL - Illegal Instruction, pg. 358. # ILL - Illegal Instruction, pg. 358.
:ill is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & at = 0 & op0 = 0 { :ill is op2 = 0 & op1 = 0 & ar = 0 & as = 0 & at = 0 & op0 = 0 {
ill(); ill();
goto inst_start;
} }
# ILL.N - Narrow Illegal Instruction, pg. 359. # ILL.N - Narrow Illegal Instruction, pg. 359.
:ill.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0110 & n_op0 = 0b1101 { :ill.n is n_ar = 0b1111 & n_as = 0 & n_at = 0b0110 & n_op0 = 0b1101 {
ill(); ill();
goto inst_start;
} }
# IPF - Instruction Cache Prefetch, pg. 360. # IPF - Instruction Cache Prefetch, pg. 360.