From fb39ee087a97bfb60d1635227a1a113e30d71539 Mon Sep 17 00:00:00 2001 From: Sebastian Schmidt Date: Sun, 5 Jan 2020 13:02:34 +0100 Subject: [PATCH] Fix Shift Amount Register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The least 5 significant bits is 0x1f, not 0xf. Also, don’t AND the SAR when shifting; it’s already <32. --- data/languages/xtensaInstructions.sinc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/data/languages/xtensaInstructions.sinc b/data/languages/xtensaInstructions.sinc index d3f9f6f..1f49ea7 100644 --- a/data/languages/xtensaInstructions.sinc +++ b/data/languages/xtensaInstructions.sinc @@ -1085,7 +1085,7 @@ macro extract_bit(val, bit, result) { # SLL - Shift Left Logical, pg. 524. :sll ar, as is op2 = 0b1010 & op1 = 0b0001 & ar & as & at = 0 & op0 = 0 { - local sa:1 = 32 - (sar & 0xf); + local sa:1 = 32 - sar; ar = as << sa; } @@ -1156,12 +1156,12 @@ macro extract_bit(val, bit, result) { # SSL - Set Shift Amount for Left Shift, pg. 538. :ssl as is op2 = 0b0100 & op1 = 0 & ar = 0b0001 & as & at = 0 & op0 = 0 { - sar = 32 - (as:1 & 0xf); + sar = 32 - (as:1 & 0x1f); } # SSR - Set Shift Amount for Right Shift, pg. 539. :ssr as is op2 = 0b0100 & op1 = 0 & ar = 0 & as & at = 0 & op0 = 0 { - sar = (as:1 & 0xf); + sar = (as:1 & 0x1f); } # SSX - Store Singe Indexed, pg. 540.