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Clarify UART FIFO size implications

Matthijs Kooijman
2020-11-14 18:46:07 +01:00
parent 815c709c49
commit 456f0ef907
1 changed files with 3 additions and 1 deletions
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ESP8266-NeoMethods.md

@@ -47,7 +47,9 @@ NOTE: Due to the varied board layouts for ESP8266, even though the pin may be ex
These methods use the CPU to manage a small hardware-managed UART buffer to send the data to the NeoPixels. Thus, it requires more CPU overhead than the DMA method, but it does NOT require an extra buffer.
If CPU cycles are an issue in your project, see NeoEsp8266AsyncUart1800KbpsMethod below.
Because the UART FIFO size is limited, data for just a few (typically 10) pixels can be sent completely in the background. If you have more pixels than will fit into the UART FIFO, data sending will block (use the CPU) until only a few pixels are left to send, which can then be completed in the background while the CPU does other things. The exact number of pixels depends on how much bytes each pixel needs. The FIFO buffer is 128 bytes, of which 4 bytes are need for each byte transmitted to the pixel, so for a typical 3-bytes-per-pixel WS2812 you need 12 FIFO bytes per pixel and can drive 10 pixels without blocking).
If CPU cycles or blocking are an issue in your project, see NeoEsp8266AsyncUart1800KbpsMethod below.
Due to using the hardware UART, the associated Serial or Serial1 objects can not be used. If you use UART1, Serial is still available and if you use UART0 then Serial1 is still available.