components/espcoredump/component.mk

COMPONENT_ADD_INCLUDEDIRS := include
COMPONENT_SRCDIRS := src
COMPONENT_PRIV_INCLUDEDIRS := include_core_dump
COMPONENT_ADD_LDFRAGMENTS += linker.lf

ifdef CONFIG_IDF_TARGET_ARCH_XTENSA
	COMPONENT_SRCDIRS += src/port/xtensa
	COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/xtensa
endif

ifdef CONFIG_IDF_TARGET_ARCH_RISCV
	COMPONENT_SRCDIRS += src/port/riscv
	COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/riscv
endif
coredump: improvements refactoring 2019-01-29 15:49:56 +01:00			`COMPONENT_ADD_INCLUDEDIRS := include`
			`COMPONENT_SRCDIRS := src`
			`COMPONENT_PRIV_INCLUDEDIRS := include_core_dump`
Whitespace: Automated whitespace fixes (large commit) 2020-11-10 18:40:01 +11:00			`COMPONENT_ADD_LDFRAGMENTS += linker.lf`
espcoredump: code refactoring and add support for RISC-V implemetation 2020-12-14 11:10:29 +08:00
			`ifdef CONFIG_IDF_TARGET_ARCH_XTENSA`
espcoredump: Fix bugs related to (fake) stacks 2021-03-02 14:17:24 +08:00			`COMPONENT_SRCDIRS += src/port/xtensa`
espcoredump: code refactoring and add support for RISC-V implemetation 2020-12-14 11:10:29 +08:00			`COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/xtensa`
			`endif`

			`ifdef CONFIG_IDF_TARGET_ARCH_RISCV`
espcoredump: Fix bugs related to (fake) stacks 2021-03-02 14:17:24 +08:00			`COMPONENT_SRCDIRS += src/port/riscv`
espcoredump: code refactoring and add support for RISC-V implemetation 2020-12-14 11:10:29 +08:00			`COMPONENT_PRIV_INCLUDEDIRS += include_core_dump/port/riscv`
			`endif`