ci(parlio_rx): enable logic analyzer example test

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1103,10 +1103,22 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
     int
     default 16
 
+config SOC_PARLIO_TX_CLK_SUPPORT_GATING
+    bool
+    default y
+
+config SOC_PARLIO_RX_CLK_SUPPORT_GATING
+    bool
+    default y
+
 config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
     bool
     default y
 
+config SOC_PARLIO_TRANS_BIT_ALIGN
+    bool
+    default y
+
 config SOC_PARLIO_TX_SIZE_BY_DMA
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -420,7 +420,10 @@
 #define SOC_PARLIO_RX_UNITS_PER_GROUP        1U  /*!< number of RX units in each group */
 #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the TX unit */
 #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH    16  /*!< Number of data lines of the RX unit */
+#define SOC_PARLIO_TX_CLK_SUPPORT_GATING     1  /*!< Support gating TX clock */
+#define SOC_PARLIO_RX_CLK_SUPPORT_GATING     1  /*!< Support gating RX clock */
 #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT     1  /*!< Support output RX clock to a GPIO */
+#define SOC_PARLIO_TRANS_BIT_ALIGN           1  /*!< Support bit alignment in transaction */
 #define SOC_PARLIO_TX_SIZE_BY_DMA            1   /*!< Transaction length is controlled by DMA instead of indicated by register */
 
 /*--------------------------- MPI CAPS ---------------------------------------*/

examples/peripherals/.build-test-rules.yml

@@ -262,20 +262,12 @@ examples/peripherals/mcpwm/mcpwm_sync:
 examples/peripherals/parlio:
   disable:
     - if: SOC_PARLIO_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: lack of runner
   depends_components:
     - esp_driver_parlio
 
 examples/peripherals/parlio/parlio_rx:
   disable:
     - if: SOC_PARLIO_SUPPORTED != 1
-  disable_test:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: lack of runner
   depends_components:
     - esp_driver_parlio
 

examples/peripherals/parlio/parlio_rx/logic_analyzer/pytest_logic_analyzer.py

@@ -0,0 +1,22 @@
+# SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import pytest
+from pytest_embedded import Dut
+
+
+@pytest.mark.esp32c6
+@pytest.mark.esp32h2
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'flash_stream',
+    ],
+    indirect=True,
+)
+def test_logic_analyzer_flash_stream(dut: Dut) -> None:
+    dut.expect(r'flash_fat: Probe data partition base addr: \w+ size: \w+')
+    dut.expect(r'flash_fat: flash FATFS mounted')
+    dut.expect(r'esp_probe: Dump data size reached the max dump size')
+    dut.expect(r'example: Probe finished! [0-9]+ \(\w+\) bytes dumped')

examples/peripherals/parlio/parlio_rx/logic_analyzer/sdkconfig.ci.flash_stream

@@ -0,0 +1 @@
+CONFIG_EXAMPLE_FLASH_STREAM=y