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freertos: Xtensa FreeRTOS saves threadptr in solicited stack frame
The Xtensa FreeRTOS port does not save the threadptr register when doing a voluntary yield. This can result in a crash when multiple tasks used the threadptr register and call "taskYIELD()". This commit adds the threadptr register to the solicited stack frame.
This commit is contained in:
Darian Leung
@ -86,16 +86,16 @@ NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
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INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
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A stack frame of this structure is allocated for any interrupt or exception.
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It goes on the current stack. If the RTOS has a system stack for handling
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interrupts, every thread stack must allow space for just one interrupt stack
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It goes on the current stack. If the RTOS has a system stack for handling
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interrupts, every thread stack must allow space for just one interrupt stack
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frame, then nested interrupt stack frames go on the system stack.
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The frame includes basic registers (explicit) and "extra" registers introduced
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The frame includes basic registers (explicit) and "extra" registers introduced
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by user TIE or the use of the MAC16 option in the user's Xtensa config.
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The frame size is minimized by omitting regs not applicable to user's config.
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For Windowed ABI, this stack frame includes the interruptee's base save area,
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another base save area to manage gcc nested functions, and a little temporary
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another base save area to manage gcc nested functions, and a little temporary
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space to help manage the spilling of the register windows.
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-------------------------------------------------------------------------------
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*/
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@ -163,7 +163,7 @@ STRUCT_END(XtExcFrame)
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#else
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#define XT_STK_NEXT2 XT_STK_NEXT1
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#define XT_STK_NEXT2 XT_STK_NEXT1
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#endif
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@ -180,20 +180,28 @@ STRUCT_END(XtExcFrame)
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-------------------------------------------------------------------------------
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SOLICITED STACK FRAME FOR A THREAD
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A stack frame of this structure is allocated whenever a thread enters the
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A stack frame of this structure is allocated whenever a thread enters the
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RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
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It goes on the current thread's stack.
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The solicited frame only includes registers that are required to be preserved
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by the callee according to the compiler's ABI conventions, some space to save
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by the callee according to the compiler's ABI conventions, some space to save
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the return address for returning to the caller, and the caller's PS register.
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Note: Although the xtensa ABI considers the threadptr as "global" across
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functions (meaning it is neither caller or callee saved), it is treated as a
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callee-saved register in a solicited stack frame. This omits the need for the
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OS to include extra logic to save "global" registers on each context switch.
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Only the threadptr register is treated as callee-saved, as all other NCP
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(non-coprocessor extra) registers are caller-saved. See "tie.h" for more
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details.
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For Windowed ABI, this stack frame includes the caller's base save area.
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Note on XT_SOL_EXIT field:
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It is necessary to distinguish a solicited from an interrupt stack frame.
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This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
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always at the same offset (0). It can be written with a code (usually 0)
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always at the same offset (0). It can be written with a code (usually 0)
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to distinguish a solicted frame from an interrupt frame. An RTOS port may
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opt to ignore this field if it has another way of distinguishing frames.
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-------------------------------------------------------------------------------
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@ -204,7 +212,11 @@ STRUCT_BEGIN
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STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
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STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
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STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
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STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
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#if XCHAL_HAVE_THREADPTR
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STRUCT_FIELD (long, 4, XT_SOL_THREADPTR, threadptr)
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#else
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STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) /* Dummy register for 16-byte alignment */
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#endif
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STRUCT_FIELD (long, 4, XT_SOL_A12, a12) /* should be on 16-byte alignment */
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STRUCT_FIELD (long, 4, XT_SOL_A13, a13)
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STRUCT_FIELD (long, 4, XT_SOL_A14, a14)
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@ -213,7 +225,11 @@ STRUCT_FIELD (long, 4, XT_SOL_A15, a15)
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STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
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STRUCT_FIELD (long, 4, XT_SOL_PC, pc)
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STRUCT_FIELD (long, 4, XT_SOL_PS, ps)
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STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
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#if XCHAL_HAVE_THREADPTR
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STRUCT_FIELD (long, 4, XT_SOL_THREADPTR, threadptr)
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#else
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STRUCT_FIELD (long, 4, XT_SOL_NEXT, next) /* Dummy register for 16-byte alignment */
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#endif
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STRUCT_FIELD (long, 4, XT_SOL_A0, a0) /* should be on 16-byte alignment */
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STRUCT_FIELD (long, 4, XT_SOL_A1, a1)
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STRUCT_FIELD (long, 4, XT_SOL_A2, a2)
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@ -238,7 +254,7 @@ STRUCT_END(XtSolFrame)
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and the context switch of that co-processor is then peformed by the handler.
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Ownership represents which thread's state is currently in the co-processor.
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Co-processors may not be used by interrupt or exception handlers. If an
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Co-processors may not be used by interrupt or exception handlers. If an
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co-processor instruction is executed by an interrupt or exception handler,
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the co-processor exception handler will trigger a kernel panic and freeze.
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This restriction is introduced to reduce the overhead of saving and restoring
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@ -249,7 +265,7 @@ STRUCT_END(XtSolFrame)
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such as in the thread control block or above the thread stack area. It need
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not be in the interrupt stack frame since interrupts don't use co-processors.
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Along with the save area for each co-processor, two bitmasks with flags per
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Along with the save area for each co-processor, two bitmasks with flags per
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co-processor (laid out as in the CPENABLE reg) help manage context-switching
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co-processors as efficiently as possible:
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@ -265,10 +281,10 @@ STRUCT_END(XtSolFrame)
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XT_CPSTORED
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A bitmask with the same layout as CPENABLE, a bit per co-processor.
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Indicates whether the state of each co-processor is saved in the state
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Indicates whether the state of each co-processor is saved in the state
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save area. When a thread enters the kernel, only the state of co-procs
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still enabled in CPENABLE is saved. When the co-processor exception
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handler assigns ownership of a co-processor to a thread, it restores
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still enabled in CPENABLE is saved. When the co-processor exception
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handler assigns ownership of a co-processor to a thread, it restores
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the saved state only if this bit is set, and clears this bit.
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XT_CP_CS_ST
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@ -349,7 +365,7 @@ STRUCT_END(XtSolFrame)
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For framed functions the frame is created and the return address saved at
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base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
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For frameless functions, there is no frame and return address remains in a0.
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Note: Because CPP macros expand to a single line, macros requiring multi-line
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Note: Because CPP macros expand to a single line, macros requiring multi-line
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expansions are implemented as assembler macros.
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-------------------------------------------------------------------------------
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*/
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@ -362,7 +378,7 @@ STRUCT_END(XtSolFrame)
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addi sp, sp, -\size
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s32i a0, sp, 0
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.endm
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#define ENTRY0
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#define ENTRY0
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#define RET(sz) ret1 sz
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.macro ret1 size=0x10
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l32i a0, sp, 0
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@ -56,10 +56,10 @@ port_switch_flag:
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*******************************************************************************
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* _frxt_setup_switch
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* void _frxt_setup_switch(void);
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*
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*
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* Sets an internal flag indicating that a task switch is required on return
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* from interrupt handling.
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*
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*
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*******************************************************************************
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*/
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.global _frxt_setup_switch
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@ -152,7 +152,7 @@ _frxt_int_enter:
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#if XCHAL_CP_NUM > 0
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movi a3, 0 /* whilst ISRs pending keep CPENABLE exception active */
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wsr a3, CPENABLE
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rsync
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rsync
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#endif
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#endif
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@ -192,10 +192,10 @@ _frxt_int_exit:
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s32i a2, a3, 0 /* save nesting count */
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bnez a2, .Lnesting /* !=0 after decr so still nested */
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#ifdef CONFIG_FREERTOS_FPU_IN_ISR
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#ifdef CONFIG_FREERTOS_FPU_IN_ISR
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#if XCHAL_CP_NUM > 0
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l32i a3, sp, 0 /* Grab last CPENABLE before leave ISR */
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addi sp, sp, 4
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addi sp, sp, 4
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wsr a3, CPENABLE
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rsync /* ensure CPENABLE was modified */
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#endif
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@ -444,6 +444,10 @@ _frxt_dispatch:
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.L_frxt_dispatch_sol:
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/* Solicited stack frame. Restore minimal context and return from vPortYield(). */
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#if XCHAL_HAVE_THREADPTR
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l32i a2, sp, XT_SOL_THREADPTR
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wur.threadptr a2
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#endif
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l32i a3, sp, XT_SOL_PS
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#ifdef __XTENSA_CALL0_ABI__
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l32i a12, sp, XT_SOL_A12
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@ -531,6 +535,10 @@ vPortYield:
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rsr a2, PS
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s32i a0, sp, XT_SOL_PC
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s32i a2, sp, XT_SOL_PS
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#if XCHAL_HAVE_THREADPTR
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rur.threadptr a2
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s32i a2, sp, XT_SOL_THREADPTR
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#endif
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#ifdef __XTENSA_CALL0_ABI__
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s32i a12, sp, XT_SOL_A12 /* save callee-saved registers */
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s32i a13, sp, XT_SOL_A13
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