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hal(ecp32c2): Adds spi_flash_encrypted_ll

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This commit is contained in:
KonstantinKondrashov
2022-05-24 16:24:11 +08:00
committed by BOT
parent dd4642b6ba
commit 0b22839925
3 changed files with 33 additions and 11 deletions
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32
components/hal/esp32c2/include/hal/spi_flash_encrypted_ll.h
View File

@@ -35,7 +35,9 @@ typedef enum
*/
static inline void spi_flash_encrypt_ll_enable(void)
{
abort();
REG_SET_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
}
/*
@@ -43,7 +45,8 @@ static inline void spi_flash_encrypt_ll_enable(void)
*/
static inline void spi_flash_encrypt_ll_disable(void)
{
abort();
REG_CLR_BIT(SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
}
/**
@@ -55,7 +58,9 @@ static inline void spi_flash_encrypt_ll_disable(void)
*/
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
abort();
// Our hardware only support flash encryption
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_WRITE(AES_XTS_DESTINATION_REG, type);
}
/**
@@ -65,7 +70,8 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
*/
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
abort();
// Desired block should not be larger than the block size.
REG_WRITE(AES_XTS_SIZE_REG, size >> 5);
}
/**
@@ -78,7 +84,8 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
*/
static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
{
abort();
uint32_t plaintext_offs = (address % 64);
memcpy((void *)(AES_XTS_PLAIN_BASE + plaintext_offs), buffer, size);
}
/**
@@ -88,7 +95,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
abort();
REG_WRITE(AES_XTS_PHYSICAL_ADDR_REG, flash_addr);
}
/**
@@ -96,7 +103,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
abort();
REG_WRITE(AES_XTS_TRIGGER_REG, 1);
}
/**
@@ -104,7 +111,8 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
abort();
while(REG_READ(AES_XTS_STATE_REG) == 0x1) {
}
}
/**
@@ -112,7 +120,9 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/
static inline void spi_flash_encrypt_ll_done(void)
{
abort();
REG_WRITE(AES_XTS_RELEASE_REG, 1);
while(REG_READ(AES_XTS_STATE_REG) != 0x3) {
}
}
/**
@@ -120,7 +130,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
abort();
REG_WRITE(AES_XTS_DESTROY_REG, 1);
}
/**
@@ -131,7 +141,7 @@ static inline void spi_flash_encrypt_ll_destroy(void)
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
abort();
return ((address % length) == 0) ? true : false;
}
#ifdef __cplusplus

11
components/soc/esp32c2/include/soc/hwcrypto_reg.h
View File

@@ -27,4 +27,15 @@
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
/* AES-XTS registers */
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_XTS_BASE) + 0x00)
#define AES_XTS_SIZE_REG ((DR_REG_AES_XTS_BASE) + 0x40)
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_XTS_BASE) + 0x44)
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_XTS_BASE) + 0x48)
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_XTS_BASE) + 0x4C)
#define AES_XTS_RELEASE_REG ((DR_REG_AES_XTS_BASE) + 0x50)
#define AES_XTS_DESTROY_REG ((DR_REG_AES_XTS_BASE) + 0x54)
#define AES_XTS_STATE_REG ((DR_REG_AES_XTS_BASE) + 0x58)
#endif

1
components/soc/esp32c2/include/soc/reg_base.h
View File

@@ -41,3 +41,4 @@
#define DR_REG_BLE_SEC_BASE 0x6004C000
#define DR_REG_COEX_BIT_BASE 0x6004C400
#define DR_REG_I2C_MST_BASE 0x6004E800
#define DR_REG_AES_XTS_BASE 0x600CC000