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Merge branch 'bugfix/power-down-rtc-periph-for-ulp-touch-fsm' into 'master'

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ulp: Keep RTC_CNTL_COCPU_SHUT_RESET_EN set for ULP RISC-V

Closes IDFGH-6186

See merge request espressif/esp-idf!17680
This commit is contained in:
Sudeep Mohanty
2022-05-09 15:31:50 +08:00
parent f7f6a929f2 f709faea7c
commit 0eafe4d326
2 changed files with 8 additions and 8 deletions
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12
components/ulp/ulp_riscv/ulp_riscv.c
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@@ -55,10 +55,8 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
#endif //CONFIG_IDF_TARGET_ESP32S3 #endif //CONFIG_IDF_TARGET_ESP32S3
#if CONFIG_IDF_TARGET_ESP32S2 #if CONFIG_IDF_TARGET_ESP32S2
/* Reset COCPU when power on. */ /* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN); SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
esp_rom_delay_us(20);
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* The coprocessor cpu trap signal doesnt have a stable reset value, /* The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/ force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
@@ -77,12 +75,14 @@ esp_err_t ulp_riscv_config_and_run(ulp_riscv_cfg_t* cfg)
ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source); ret = ulp_riscv_config_wakeup_source(cfg->wakeup_source);
#elif CONFIG_IDF_TARGET_ESP32S3 #elif CONFIG_IDF_TARGET_ESP32S3
/* Reset COCPU when power on. */ /* The coprocessor cpu trap signal doesnt have a stable reset value,
force ULP-RISC-V clock on to stop RTC_COCPU_TRAP_TRIG_EN from waking the CPU*/
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
esp_rom_delay_us(20); esp_rom_delay_us(20);
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO); CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_CLK_FO);
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* Set RTC_CNTL_COCPU_SHUT_RESET_EN to make sure COCPU is reset after halt. */
SET_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_SHUT_RESET_EN);
/* Disable ULP timer */ /* Disable ULP timer */
CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ULP_CP_TIMER_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);

2
components/ulp/ulp_riscv/ulp_riscv_utils.c
View File

@@ -13,7 +13,7 @@
void ulp_riscv_rescue_from_monitor(void) void ulp_riscv_rescue_from_monitor(void)
{ {
/* Rescue RISCV from monitor state. */ /* Rescue RISCV from monitor state. */
CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE | RTC_CNTL_COCPU_SHUT_RESET_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_COCPU_CTRL_REG, RTC_CNTL_COCPU_DONE);
} }
void ulp_riscv_wakeup_main_processor(void) void ulp_riscv_wakeup_main_processor(void)