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Merge branch 'docs/uhci_doc_compiling' into 'master'
docs(uhci): Fix uhci compiling on non-supported target See merge request espressif/esp-idf!41677
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@@ -115,7 +115,9 @@ BITSCRAMBLER_DOCS = ['api-reference/peripherals/bitscrambler.rst']
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CLK_TREE_DOCS = ['api-reference/peripherals/clk_tree.rst']
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UART_DOCS = ['api-reference/peripherals/uart.rst', 'api-reference/peripherals/uhci.rst']
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UART_DOCS = ['api-reference/peripherals/uart.rst']
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UHCI_DOCS = ['api-reference/peripherals/uhci.rst']
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SDMMC_DOCS = ['api-reference/peripherals/sdmmc_host.rst']
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@@ -340,6 +342,7 @@ conditional_include_dict = {
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'SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE': MM_SYNC_DOCS,
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'SOC_CLK_TREE_SUPPORTED': CLK_TREE_DOCS,
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'SOC_UART_SUPPORTED': UART_DOCS,
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'SOC_UHCI_SUPPORTED': UHCI_DOCS,
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'SOC_SDMMC_HOST_SUPPORTED': SDMMC_DOCS,
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'SOC_SDIO_SLAVE_SUPPORTED': SDIO_SLAVE_DOCS,
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'SOC_MCPWM_SUPPORTED': MCPWM_DOCS,
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@@ -18,13 +18,13 @@ Each UART controller is independently configurable with parameters such as baud
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Additionally, the {IDF_TARGET_NAME} chip has one low-power (LP) UART controller. It is the cut-down version of regular UART. Usually, the LP UART controller only support basic UART functionality with a much smaller RAM size, and does not support IrDA or RS485 protocols. For a full list of difference between UART and LP UART, please refer to the **{IDF_TARGET_NAME} Technical Reference Manual** > **UART Controller (UART)** > **Features** [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]).
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.. toctree::
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.. only:: SOC_UHCI_SUPPORTED
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.. toctree::
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:hidden:
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uhci
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.. only:: SOC_UHCI_SUPPORTED
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The {IDF_TARGET_NAME} chip also supports using DMA with UART. For details, see to :doc:`uhci`.
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Functional Overview
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@@ -239,7 +239,7 @@ The UART controller supports a number of communication modes. A mode can be sele
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Use Interrupts
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^^^^^^^^^^^^^^^^
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There are many interrupts that can be generated depending on specific UART states or detected errors. The full list of available interrupts is provided in *{IDF_TARGET_NAME} Technical Reference Manual* > *UART Controller (UART)* > *UART Interrupts* and *UHCI Interrupts* [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]. You can enable or disable specific interrupts by calling :cpp:func:`uart_enable_intr_mask` or :cpp:func:`uart_disable_intr_mask` respectively.
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There are many interrupts that can be generated depending on specific UART states or detected errors. The full list of available interrupts is provided in *{IDF_TARGET_NAME} Technical Reference Manual* > *UART Controller (UART)* > *UART Interrupts* [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]. You can enable or disable specific interrupts by calling :cpp:func:`uart_enable_intr_mask` or :cpp:func:`uart_disable_intr_mask` respectively.
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The UART driver provides a convenient way to handle specific interrupts by wrapping them into corresponding events. Events defined in :cpp:type:`uart_event_type_t` can be reported to a user application using the FreeRTOS queue functionality.
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@@ -18,13 +18,13 @@
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此外,{IDF_TARGET_NAME} 芯片还有一个满足低功耗需求的 LP UART 控制器。LP UART 是原 UART 的功能剪裁版本。它只支持基础 UART 功能,不支持 IrDA 或 RS485 协议,并且只有一块较小的 RAM 存储空间。想要全面了解的 UART 及 LP UART 功能区别,请参考 **{IDF_TARGET_NAME} 技术参考手册** > UART 控制器 (UART) > 主要特性 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__]。
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.. toctree::
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.. only:: SOC_UHCI_SUPPORTED
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.. toctree::
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:hidden:
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uhci
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.. only:: SOC_UHCI_SUPPORTED
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{IDF_TARGET_NAME} 芯片也支持 UART DMA 模式, 请参考 :doc:`uhci` 以获得更多信息.
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功能概述
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@@ -239,7 +239,7 @@ UART 控制器支持多种通信模式,使用函数 :cpp:func:`uart_set_mode`
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使用中断
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^^^^^^^^^^^^^^^^^
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根据特定的 UART 状态或检测到的错误,可以生成许多不同的中断。**{IDF_TARGET_NAME} 技术参考手册** > UART 控制器 (UART) > UART 中断 和 UHCI 中断 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__] 中提供了可用中断的完整列表。调用 :cpp:func:`uart_enable_intr_mask` 或 :cpp:func:`uart_disable_intr_mask` 能够分别启用或禁用特定中断。
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根据特定的 UART 状态或检测到的错误,可以生成许多不同的中断。**{IDF_TARGET_NAME} 技术参考手册** > UART 控制器 (UART) > UART 中断 [`PDF <{IDF_TARGET_TRM_EN_URL}#uart>`__] 中提供了可用中断的完整列表。调用 :cpp:func:`uart_enable_intr_mask` 或 :cpp:func:`uart_disable_intr_mask` 能够分别启用或禁用特定中断。
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UART 驱动提供了一种便利的方法来处理特定的中断,即将中断包装成相应的事件。这些事件定义在 :cpp:type:`uart_event_type_t` 中,FreeRTOS 队列功能可将这些事件报告给用户应用程序。
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