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Merge branch 'refactor/abstract_flash_rom_code' into 'master'

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spi_flash: refactor `spi_flash.h` to decline duplicated code and Infinite growth header

Closes IDF-2703

See merge request espressif/esp-idf!15372
This commit is contained in:
Simon
2021-12-30 07:29:57 +00:00
parent e234abf1bb d397464fc4
commit 15380099e3
82 changed files with 1292 additions and 1496 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
components/app_update/test/test_switch_ota.c
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@@ -12,11 +12,7 @@
#include "string.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
@@ -25,7 +21,7 @@
#include "unity.h"
#include "bootloader_common.h"
#include "../include_bootloader/bootloader_flash_priv.h"
#include "../bootloader_flash/include/bootloader_flash_priv.h"
#include "esp_log.h"
#include "esp_ota_ops.h"

1
components/bootloader/subproject/main/ld/esp32/bootloader.ld
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@@ -63,6 +63,7 @@ SECTIONS
*libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
*libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
*libefuse.a:*.*(.literal .text .literal.* .text.*)
*libesp_rom.a:*.*(.literal .text .literal.* .text.*)
*(.fini.literal)
*(.fini)
*(.gnu.version)

11
components/bootloader_support/CMakeLists.txt
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@@ -2,7 +2,7 @@ set(srcs
"src/bootloader_common.c"
"src/bootloader_common_loader.c"
"src/bootloader_clock_init.c"
"src/bootloader_flash.c"
"bootloader_flash/src/bootloader_flash.c"
"src/bootloader_mem.c"
"src/bootloader_random.c"
"src/bootloader_random_${IDF_TARGET}.c"
@@ -11,13 +11,14 @@ set(srcs
"src/flash_encrypt.c"
"src/secure_boot.c"
"src/flash_partitions.c"
"src/flash_qio_mode.c"
"src/bootloader_flash_config_${IDF_TARGET}.c"
"bootloader_flash/src/flash_qio_mode.c"
"bootloader_flash/src/bootloader_flash_config_${IDF_TARGET}.c"
"src/bootloader_efuse_${IDF_TARGET}.c"
)
if(BOOTLOADER_BUILD)
set(include_dirs "include" "include_bootloader")
set(include_dirs "include" "bootloader_flash/include"
"include_bootloader")
set(priv_requires micro-ecc spi_flash efuse)
list(APPEND srcs
"src/bootloader_init.c"
@@ -33,7 +34,7 @@ if(BOOTLOADER_BUILD)
else()
list(APPEND srcs
"src/idf/bootloader_sha.c")
set(include_dirs "include")
set(include_dirs "include" "bootloader_flash/include")
set(priv_include_dirs "include_bootloader")
# heap is required for `heap_memory_layout.h` header
set(priv_requires spi_flash mbedtls efuse app_update heap)

0
components/bootloader_support/include/bootloader_flash.h → components/bootloader_support/bootloader_flash/include/bootloader_flash.h
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0
components/bootloader_support/include/bootloader_flash_config.h → components/bootloader_support/bootloader_flash/include/bootloader_flash_config.h
View File

0
components/bootloader_support/include/bootloader_flash_override.h → components/bootloader_support/bootloader_flash/include/bootloader_flash_override.h
View File

8
components/bootloader_support/include_bootloader/bootloader_flash_priv.h → components/bootloader_support/bootloader_flash/include/bootloader_flash_priv.h
View File

@@ -14,6 +14,10 @@
#include "sdkconfig.h"
#include "bootloader_flash.h"
#ifdef __cplusplus
extern "C" {
#endif
#define FLASH_SECTOR_SIZE 0x1000
#define FLASH_BLOCK_SIZE 0x10000
#define MMAP_ALIGNED_MASK 0x0000FFFF
@@ -171,4 +175,8 @@ uint32_t bootloader_flash_read_sfdp(uint32_t sfdp_addr, unsigned int miso_byte_n
*/
void bootloader_enable_wp(void);
#ifdef __cplusplus
}
#endif
#endif

2
components/bootloader_support/include_bootloader/flash_qio_mode.h → components/bootloader_support/bootloader_flash/include/flash_qio_mode.h
View File

@@ -5,6 +5,8 @@
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif

25
components/bootloader_support/src/bootloader_flash.c → components/bootloader_support/bootloader_flash/src/bootloader_flash.c
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@@ -23,19 +23,7 @@
# define SPIFLASH SPIMEM1
#endif
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
#define ENCRYPTION_IS_VIRTUAL 1
@@ -127,29 +115,24 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
#else //BOOTLOADER_BUILD
/* Bootloader version, uses ROM functions only */
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/cache.h"
#include "soc/cache_memory.h"
#endif
#include "esp_rom_spiflash.h"
static const char *TAG = "bootloader_flash";
#if CONFIG_IDF_TARGET_ESP32
@@ -526,10 +509,6 @@ esp_err_t IRAM_ATTR __attribute__((weak)) bootloader_flash_unlock(void)
return err;
}
/* dummy_len_plus values defined in ROM for SPI flash configuration */
#ifndef g_rom_spiflash_dummy_len_plus // ESP32-C3 uses a macro to access ROM data here
extern uint8_t g_rom_spiflash_dummy_len_plus[];
#endif
IRAM_ATTR static uint32_t bootloader_flash_execute_command_common(
uint8_t command,
uint32_t addr_len, uint32_t address,

1
components/bootloader_support/src/bootloader_flash_config_esp32.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
View File

@@ -134,7 +134,6 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr)
}
}
extern uint8_t g_rom_spiflash_dummy_len_plus[];
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_80M:
g_rom_spiflash_dummy_len_plus[0] = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;

0
components/bootloader_support/src/bootloader_flash_config_esp32c3.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
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0
components/bootloader_support/src/bootloader_flash_config_esp32h2.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c
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0
components/bootloader_support/src/bootloader_flash_config_esp32s2.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
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0
components/bootloader_support/src/bootloader_flash_config_esp32s3.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
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0
components/bootloader_support/src/bootloader_flash_config_esp8684.c → components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp8684.c
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14
components/bootloader_support/src/flash_qio_mode.c → components/bootloader_support/bootloader_flash/src/flash_qio_mode.c
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@@ -12,20 +12,8 @@
#include "esp_log.h"
#include "esp_err.h"
#include "esp_rom_efuse.h"
#include "esp_rom_spiflash.h"
#include "flash_qio_mode.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
#include "soc/efuse_periph.h"
#include "soc/io_mux_reg.h"

14
components/bootloader_support/src/bootloader_common.c
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@@ -9,19 +9,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_rom_sys.h"

7
components/bootloader_support/src/bootloader_common_loader.c
View File

@@ -8,12 +8,7 @@
#include "sdkconfig.h"
#include "esp_err.h"
#include "esp_log.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/ets_sys.h"
#endif
#include "esp_rom_spiflash.h"
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_flash_partitions.h"

7
components/bootloader_support/src/bootloader_utility.c
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@@ -17,17 +17,14 @@
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/secure_boot.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/secure_boot.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
@@ -35,7 +32,6 @@
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/crc.h"
#include "esp32c3/rom/uart.h"
#include "esp32c3/rom/gpio.h"
@@ -46,7 +42,6 @@
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/crc.h"
#include "esp32h2/rom/uart.h"
#include "esp32h2/rom/gpio.h"
@@ -57,7 +52,6 @@
#include "esp8684/rom/cache.h"
#include "esp8684/rom/efuse.h"
#include "esp8684/rom/ets_sys.h"
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/crc.h"
#include "esp8684/rom/rtc.h"
#include "esp8684/rom/uart.h"
@@ -68,6 +62,7 @@
#else // CONFIG_IDF_TARGET_*
#error "Unsupported IDF_TARGET"
#endif
#include "esp_rom_spiflash.h"
#include "soc/soc.h"
#include "esp_cpu.h"

2
components/bootloader_support/src/esp32/bootloader_esp32.c
View File

@@ -32,7 +32,7 @@
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp32/rom/spi_flash.h"
#include "esp_rom_spiflash.h"
#include "esp_efuse.h"
static const char *TAG = "boot.esp32";

3
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@@ -13,6 +13,7 @@
#include "esp_rom_efuse.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "soc/efuse_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
@@ -24,10 +25,8 @@
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/spi_flash.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "bootloader_clock.h"

3
components/bootloader_support/src/esp32h2/bootloader_esp32h2.c
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@@ -13,6 +13,7 @@
#include "esp_rom_efuse.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "soc/efuse_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
@@ -24,10 +25,8 @@
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp32h2/rom/efuse.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/spi_flash.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
#include "bootloader_clock.h"

2
components/bootloader_support/src/esp32s2/bootloader_esp32s2.c
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@@ -22,8 +22,8 @@
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp_attr.h"
#include "esp_log.h"

2
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
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@@ -23,7 +23,7 @@
#include "esp_rom_gpio.h"
#include "esp_rom_efuse.h"
#include "esp_rom_sys.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp_rom_spiflash.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/rom/rtc.h"

5
components/bootloader_support/src/esp8684/bootloader_esp8684.c
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@@ -13,6 +13,7 @@
#include "esp_rom_efuse.h"
#include "esp_rom_uart.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "soc/efuse_reg.h"
#include "soc/gpio_sig_map.h"
#include "soc/io_mux_reg.h"
@@ -24,10 +25,8 @@
#include "soc/io_mux_reg.h"
#include "soc/system_reg.h"
#include "esp8684/rom/efuse.h"
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/cache.h"
#include "esp8684/rom/ets_sys.h"
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/rtc.h"
#include "bootloader_common.h"
#include "bootloader_init.h"
@@ -203,7 +202,7 @@ static esp_err_t bootloader_init_spi_flash(void)
#endif
bootloader_spi_flash_resume();
esp_rom_spiflash_unlock();
bootloader_flash_unlock();
#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
bootloader_enable_qio_mode();

14
components/bootloader_support/src/flash_partitions.c
View File

@@ -7,19 +7,7 @@
#include "esp_flash_partitions.h"
#include "esp_log.h"
#include "esp_rom_md5.h"
#if CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#else
#include "esp32/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
static const char *TAG = "flash_parts";

2
components/efuse/src/esp_efuse_utility.c
View File

@@ -404,7 +404,7 @@ void esp_efuse_init_virtual_mode_in_ram(void)
#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
#include "../include_bootloader/bootloader_flash_priv.h"
#include "../bootloader_flash/include/bootloader_flash_priv.h"
static uint32_t esp_efuse_flash_offset = 0;
static uint32_t esp_efuse_flash_size = 0;

4
components/esp_rom/CMakeLists.txt
View File

@@ -16,6 +16,7 @@ else()
list(APPEND sources "patches/esp_rom_crc.c"
"patches/esp_rom_sys.c"
"patches/esp_rom_uart.c"
"patches/esp_rom_spiflash.c"
"patches/esp_rom_tjpgd.c")
list(APPEND private_required_comp soc hal)
endif()
@@ -26,7 +27,8 @@ endif()
idf_component_register(SRCS ${sources}
INCLUDE_DIRS ${include_dirs}
PRIV_REQUIRES ${private_required_comp})
PRIV_REQUIRES ${private_required_comp}
LDFRAGMENTS linker.lf)
if(target STREQUAL "esp32h2")
if(CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1)

78
components/esp_rom/README.md Normal file
View File

@@ -0,0 +1,78 @@
# `esp_rom` Component
## Function Description
`esp_rom` component contains each chip's ROM functions, which are used in the ROM bootloader, 2nd bootloader, esp_tool flash stub and some driver code (e.g. GPIO matrix). ROM functions as not treated as public APIs, attentions are required when you use ROM functions:
1. ROM functions are **not** thread-safe in RTOS, extra locks are needed to be around the ROM functions.
2. Names/signatures/behaviors of ROM function may be different between chips.
3. ROM functions are not guaranteed to exist across all chips.
When using ROM functions in esp-idf, the including convention is `<target>/rom/<header_file>.h`. This can prevent you from using a nonexistent ROM function for a specific `<target>`. Thus ROM functions are recommended for use in a target-specific source file. For example, `bootloader_esp32.c` can include `esp32/rom/<header_file>.h` without any violations. However, this is not the case when it comes to a common source file that also wants to use some of the ROM functions. The include list would be quite extensive:
```c
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/uart.h"
...
```
So, we added a wrapper for those commonly used ROM functions. They're declared in `esp_rom/include/esp_rom_xxx.h`. Unlike the original ROM functions, these extracted ones are expected to exist across all chips. If some of them are missed in the new chips, we will implement them again in `esp_rom/patches`. These ROM APIs are always prefixed with the name `esp_rom` (e.g. `esp_rom_printf`), so that it's obvious to know whether a function is linked to ROM.
Most of the time, the ROM wrapper APIs are just alias to the original ROM functions by linker script `esp_rom/<target>/ld/<target>.rom.api.ld`. For example, `esp_rom_printf` is alias to `ets_printf` in the following way:
```
PROVIDE ( esp_rom_printf = ets_printf );
```
If some original ROM functions have changed the behavior or have bugs, we should override them in the wrapper layer. A common example is the `esp_rom_install_uart_printf()`, on ESP32 and ESP32S2, it's just alias to `ets_install_uart_printf`, but on other chips, it's re-implemented in the `esp_rom/patches/esp_rom_uart.c`. To some extent, the ROM wrapper layer works like an anti-corrosion layer between esp-rom project and esp-idf project.
As ROM functions are unique to each target, features are as well. For example, ESP32 has the `tjpgd` library built into the ROM, but ESP32S2 hasn't. We have a header file `esp_rom/<target>/esp_rom_caps.h` declaring the features that are supported by each target. Based on the macros defined there, we can decide whether a function should be patched or whether a feature should be re-implemented.
## Directory Structure
```
.
├── CMakeLists.txt
├── <target/chip_name>
│   ├── esp_rom_caps.h
│   └── ld
│   ├── <target>.rom.api.ld
│   ├── <target>.rom.ld
│   ├── <target>.rom.libgcc.ld
│   ├── <target>.rom.newlib.ld
│   ├── <target>.rom.newlib-nano.ld
│   ├── <target>.rom.version.ld
│   └── ... // other ROM linker scripts, added when bring up new chip
├── include
│   ├── <target/chip_name>
│   │   └── rom
│   │   ├── cache.h
│   │   ├── efuse.h
│   │   ├── esp_flash.h
│   │   ├── ets_sys.h
│   │   ├── gpio.h
│   │   ├── uart.h
│   │   └── ... // other original ROM header files, added when bring up new chip
│   ├── esp_rom_gpio.h
│   ├── esp_rom_md5.h
│   ├── esp_rom_sys.h
│   ├── esp_rom_uart.h
│   └── ... // other ROM wrapper api files
├── Kconfig.projbuild
├── linker.lf
├── patches
│   ├── esp_rom_sys.c
│   ├── esp_rom_uart.c
│   └── ... // other patched source files
├── README.md
└── test
├── CMakeLists.txt
├── test_miniz.c
└── ... // other ROM function unit tests
```

3
components/esp_rom/esp32/ld/esp32.rom.api.ld
View File

@@ -43,3 +43,6 @@ PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_spiflash_set_bp = esp_rom_spiflash_lock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

1
components/esp_rom/esp32/ld/esp32.rom.ld
View File

@@ -1365,6 +1365,7 @@ PROVIDE ( esp_rom_spiflash_select_qio_pins = 0x40061ddc );
PROVIDE ( esp_rom_spiflash_attach = 0x40062a6c );
PROVIDE ( esp_rom_spiflash_config_clk = 0x40062bc8 );
PROVIDE ( g_rom_spiflash_chip = 0x3ffae270 );
PROVIDE ( SPI_write_enable = 0x40062320 );
PROVIDE ( hci_le_rd_rem_used_feats_cmd_handler = 0x400417b4 );
PROVIDE ( llcp_length_req_handler = 0x40043808 );
PROVIDE ( llcp_unknown_rsp_handler = 0x40043ba8 );

3
components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld
View File

@@ -40,3 +40,6 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

3
components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld
View File

@@ -43,3 +43,6 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

3
components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld
View File

@@ -43,3 +43,6 @@ PROVIDE ( esp_rom_md5_final = MD5Final );
PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

3
components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld
View File

@@ -37,3 +37,6 @@ PROVIDE ( esp_rom_printf = ets_printf );
PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld
View File

@@ -45,3 +45,5 @@ PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

2
components/esp_rom/esp8684/ld/esp8684.rom.api.ld
View File

@@ -39,3 +39,5 @@ PROVIDE ( esp_rom_delay_us = ets_delay_us );
PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
PROVIDE( esp_rom_spiflash_attach = spi_flash_attach );
PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable);

216
components/esp_rom/include/esp32/rom/spi_flash.h
View File

@@ -1,26 +1,16 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "sdkconfig.h"
#include "esp_rom_spiflash.h"
#ifdef CONFIG_LEGACY_INCLUDE_COMMON_HEADERS
#include "soc/spi_reg.h"
@@ -30,14 +20,6 @@
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
/*************************************************************
* Note
*************************************************************
@@ -113,48 +95,12 @@ extern "C" {
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2)
//Extra dummy for flash read
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M 0
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1
#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
@@ -164,60 +110,6 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
@@ -225,7 +117,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -316,19 +208,19 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
* @param None.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Unlock SPI write protect.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
@@ -340,7 +232,7 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* @brief SPI flash set BP0 to BP2.(Only valid when WRSR+2Bytes)
* Please do not call this function in SDK.
*
* @param None.
@@ -551,19 +443,81 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
/**
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
extern esp_rom_spiflash_chip_t g_rom_flashchip;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @}
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

298
components/esp_rom/include/esp32c3/rom/spi_flash.h
View File

@@ -1,37 +1,20 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
@@ -75,40 +58,27 @@ extern "C" {
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
} spiflash_legacy_funcs_t;
typedef struct {
uint8_t data_length;
@@ -119,60 +89,6 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
@@ -180,7 +96,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -215,7 +131,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
@@ -271,19 +187,19 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
* @param None.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Unlock SPI write protect.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
@@ -294,18 +210,6 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
@@ -327,7 +231,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
@@ -468,18 +372,6 @@ void esp_rom_spiflash_write_encrypted_disable(void);
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/* TODO: figure out how to map these to their new names */
typedef enum {
SPI_ENCRYPT_DESTINATION_FLASH,
} SpiEncryptDest;
typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len);
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
@@ -511,47 +403,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *sp
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
typedef void (* spi_flash_func_t)(void);
typedef SpiFlashOpResult (* spi_flash_op_t)(void);
typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t);
typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef SpiFlashOpResult (* spi_flash_wren_t)(void*);
typedef struct {
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
} spiflash_legacy_funcs_t;
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
/** @brief Global ROM spiflash data, as used by legacy
SPI flash functions
*/
typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} spiflash_legacy_data_t;
extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
/* Defines to make the C3 ROM legacvy data access compatible with previous chips */
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
/**
* @brief Clear WEL bit unconditionally.
*
@@ -560,11 +411,82 @@ extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/**
* @}
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

304
components/esp_rom/include/esp32h2/rom/spi_flash.h
View File

@@ -1,37 +1,20 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
@@ -75,40 +58,33 @@ extern "C" {
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
typedef struct {
uint8_t data_length;
@@ -119,60 +95,6 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
@@ -180,7 +102,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -215,7 +137,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
@@ -271,19 +193,19 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
* @param None.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Unlock SPI write protect.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
@@ -294,18 +216,6 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
@@ -327,7 +237,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
@@ -468,18 +378,6 @@ void esp_rom_spiflash_write_encrypted_disable(void);
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/* TODO: figure out how to map these to their new names */
typedef enum {
SPI_ENCRYPT_DESTINATION_FLASH,
} SpiEncryptDest;
typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len);
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
@@ -511,47 +409,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *sp
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
typedef void (* spi_flash_func_t)(void);
typedef SpiFlashOpResult (* spi_flash_op_t)(void);
typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t);
typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef SpiFlashOpResult (* spi_flash_wren_t)(void*);
typedef struct {
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
} spiflash_legacy_funcs_t;
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
/** @brief Global ROM spiflash data, as used by legacy
SPI flash functions
*/
typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} spiflash_legacy_data_t;
extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
/* Defines to make the H2 ROM legacvy data access compatible with previous chips */
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
/**
* @brief Clear WEL bit unconditionally.
*
@@ -560,11 +417,82 @@ extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/**
* @}
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

244
components/esp_rom/include/esp32s2/rom/spi_flash.h
View File

@@ -1,19 +1,10 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#ifndef CONFIG_IDF_TARGET_ESP32S2
#error This file should only be included for ESP32-S2 target
@@ -21,22 +12,14 @@
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "soc/spi_mem_reg.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
/*************************************************************
* Note
*************************************************************
@@ -111,46 +94,6 @@ extern "C" {
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE,
ESP_ROM_SPIFLASH_OPI_STR_MODE,
ESP_ROM_SPIFLASH_OPI_DTR_MODE,
ESP_ROM_SPIFLASH_OOUT_MODE,
ESP_ROM_SPIFLASH_OIO_STR_MODE,
ESP_ROM_SPIFLASH_OIO_DTR_MODE,
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
@@ -160,60 +103,6 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
@@ -221,7 +110,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -256,7 +145,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
@@ -312,19 +201,19 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
* @param None.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Unlock SPI write protect.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
@@ -335,18 +224,6 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
@@ -509,19 +386,6 @@ void esp_rom_spiflash_write_encrypted_disable(void);
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/* TODO: figure out how to map these to their new names */
typedef enum {
SPI_ENCRYPT_DESTINATION_FLASH,
SPI_ENCRYPT_DESTINATION_PSRAM,
} SpiEncryptDest;
typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void* data, uint32_t len);
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
@@ -560,19 +424,81 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions
/**
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
extern esp_rom_spiflash_chip_t g_rom_flashchip;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @}
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

265
components/esp_rom/include/esp32s3/rom/spi_flash.h
View File

@@ -1,34 +1,19 @@
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
/*************************************************************
* Note
*************************************************************
@@ -103,54 +88,6 @@ extern "C" {
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE,
ESP_ROM_SPIFLASH_OPI_STR_MODE,
ESP_ROM_SPIFLASH_OPI_DTR_MODE,
ESP_ROM_SPIFLASH_OOUT_MODE,
ESP_ROM_SPIFLASH_OIO_STR_MODE,
ESP_ROM_SPIFLASH_OIO_DTR_MODE,
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
typedef void (*spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (*spi_flash_op_t)(void);
@@ -180,60 +117,14 @@ typedef struct {
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
typedef struct {
uint8_t data_length;
uint8_t read_cmd0;
uint8_t read_cmd1;
uint8_t write_cmd;
uint16_t data_mask;
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
@@ -242,7 +133,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -277,7 +168,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
@@ -333,19 +224,19 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
* @param None.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Unlock SPI write protect.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
@@ -356,18 +247,6 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
@@ -389,7 +268,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
@@ -530,19 +409,6 @@ void esp_rom_spiflash_write_encrypted_disable(void);
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/* TODO: figure out how to map these to their new names */
typedef enum {
SPI_ENCRYPT_DESTINATION_FLASH,
SPI_ENCRYPT_DESTINATION_PSRAM,
} SpiEncryptDest;
typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len);
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
@@ -580,16 +446,83 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} spiflash_legacy_data_t;
extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
/**
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
#ifdef __cplusplus
}

290
components/esp_rom/include/esp8684/rom/spi_flash.h
View File

@@ -4,26 +4,17 @@
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
#pragma once
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
#define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1)
@@ -67,40 +58,33 @@ extern "C" {
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16
#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf
//SPI status register
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define FLASH_ID_GD25LQ32C 0xC86016
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE
} esp_rom_spiflash_read_mode_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
typedef void (* spi_flash_func_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
spi_flash_erase_area_t erase_area;
} spiflash_legacy_funcs_t;
typedef struct {
uint8_t data_length;
@@ -111,60 +95,6 @@ typedef struct {
uint16_t data;
} esp_rom_spiflash_common_cmd_t;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
@@ -172,7 +102,7 @@ void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
@@ -207,7 +137,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
@@ -263,19 +193,19 @@ esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
* @param None.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
* @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
/**
* @brief Unlock SPI write protect.
* @brief Clear all SR bits except QE bit.
* Please do not call this function in SDK.
*
* @param None.
@@ -286,18 +216,6 @@ uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
*/
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
@@ -319,7 +237,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
@@ -460,18 +378,6 @@ void esp_rom_spiflash_write_encrypted_disable(void);
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/* TODO: figure out how to map these to their new names */
typedef enum {
SPI_ENCRYPT_DESTINATION_FLASH,
} SpiEncryptDest;
typedef esp_rom_spiflash_result_t SpiFlashOpResult;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len);
SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len);
void SPI_Write_Encrypt_Enable(void);
void SPI_Write_Encrypt_Disable(void);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
@@ -503,51 +409,6 @@ esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *sp
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
typedef void (* spi_flash_func_t)(void);
typedef SpiFlashOpResult (* spi_flash_op_t)(void);
typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t);
typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
typedef SpiFlashOpResult (* spi_flash_wren_t)(void*);
typedef struct {
uint8_t pp_addr_bit_len;
uint8_t se_addr_bit_len;
uint8_t be_addr_bit_len;
uint8_t rd_addr_bit_len;
uint32_t read_sub_len;
uint32_t write_sub_len;
spi_flash_op_t unlock;
spi_flash_erase_t erase_sector;
spi_flash_erase_t erase_block;
spi_flash_rd_t read;
spi_flash_wr_t write;
spi_flash_ewr_t encrypt_write;
spi_flash_func_t check_sus;
spi_flash_wren_t wren;
spi_flash_op_t wait_idle;
} spiflash_legacy_funcs_t;
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
/** @brief Global ROM spiflash data, as used by legacy
SPI flash functions
*/
typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} spiflash_legacy_data_t;
extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
/* Defines to make the C3 ROM legacvy data access compatible with previous chips */
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
/**
* @brief Clear WEL bit unconditionally.
*
@@ -556,11 +417,82 @@ extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/**
* @}
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SPI_FLASH_H_ */

373
components/esp_rom/include/esp_rom_spiflash.h Normal file
View File

@@ -0,0 +1,373 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
#include <stdint.h>
#include <stdbool.h>
#include "esp_rom_spiflash_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ESP_ROM_SPIFLASH_QIO_MODE = 0,
ESP_ROM_SPIFLASH_QOUT_MODE,
ESP_ROM_SPIFLASH_DIO_MODE,
ESP_ROM_SPIFLASH_DOUT_MODE,
ESP_ROM_SPIFLASH_FASTRD_MODE,
ESP_ROM_SPIFLASH_SLOWRD_MODE,
ESP_ROM_SPIFLASH_OPI_STR_MODE,
ESP_ROM_SPIFLASH_OPI_DTR_MODE,
ESP_ROM_SPIFLASH_OOUT_MODE,
ESP_ROM_SPIFLASH_OIO_STR_MODE,
ESP_ROM_SPIFLASH_OIO_DTR_MODE,
ESP_ROM_SPIFLASH_QPI_MODE,
} esp_rom_spiflash_read_mode_t;
typedef struct {
uint32_t device_id;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
uint32_t sector_size;
uint32_t page_size;
uint32_t status_mask;
} esp_rom_spiflash_chip_t;
typedef enum {
ESP_ROM_SPIFLASH_RESULT_OK,
ESP_ROM_SPIFLASH_RESULT_ERR,
ESP_ROM_SPIFLASH_RESULT_TIMEOUT
} esp_rom_spiflash_result_t;
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: always keeping false.
*
* @return None
*/
void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
/**
* @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
/**
* @brief Write status to Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t status_value : Value to .
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
/**
* @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* Please do not call this function in SDK.
*
* @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
/**
* @brief Config SPI Flash clock divisor.
* Please do not call this function in SDK.
*
* @param uint8_t freqdiv: clock divisor.
*
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : config error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
*
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
*
* @param uint32_t chip_size : The Flash size.
*
* @param uint32_t block_size : The Flash block size.
*
* @param uint32_t sector_size : The Flash sector size.
*
* @param uint32_t page_size : The Flash page size.
*
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
* Please do not call this function in SDK.
*
* @param None
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
/**
* @brief Erase a 64KB block of flash
* Uses SPI flash command D8H.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
/**
* @brief Erase a sector of flash.
* Uses SPI flash command 20H.
* Please do not call this function in SDK.
*
* @param uint32_t sector_num : Which sector to erase.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
/**
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
* @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
* ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
/**
* @brief SPI1 go out of encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void esp_rom_spiflash_write_encrypted_disable(void);
/**
* @brief Write data to flash with transparent encryption.
* @note Sectors to be written should already be erased.
*
* @note Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 byte aligned.
*
* @param uint32_t *data : The pointer to data to write. Note, this pointer must
* be 32 bit aligned and the content of the data will be
* modified by the encryption function.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
* ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
* ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
/** @brief Wait until SPI flash write operation is complete
*
* @note Please do not call this function in SDK.
*
* Reads the Write In Progress bit of the SPI flash status register,
* repeats until this bit is zero (indicating write complete).
*
* @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
* ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
*/
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
/** @brief Enable Quad I/O pin functions
*
* @note Please do not call this function in SDK.
*
* Sets the HD & WP pin functions for Quad I/O modes, based on the
* efuse SPI pin configuration.
*
* @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
*
* @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
* - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
* - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
* - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
* to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
* Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
*/
void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
/**
* @brief Clear WEL bit unconditionally.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
/**
* @brief Set WREN bit.
*
* @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
*
* @return always ESP_ROM_SPIFLASH_RESULT_OK
*/
esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
/* Flash data defined in ROM*/
#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2
extern esp_rom_spiflash_chip_t g_rom_flashchip;
extern uint8_t g_rom_spiflash_dummy_len_plus[];
#else
typedef struct {
esp_rom_spiflash_chip_t chip;
uint8_t dummy_len_plus[3];
uint8_t sig_matrix;
} esp_rom_spiflash_legacy_data_t;
extern esp_rom_spiflash_legacy_data_t *rom_spiflash_legacy_data;
#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
#endif
#ifdef __cplusplus
}
#endif

31
components/esp_rom/include/esp_rom_spiflash_defs.h Normal file
View File

@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**********************************************************
* Public definations for ROM
*********************************************************/
#ifdef __cplusplus
extern "C" {
#endif
#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0
#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
#define ESP_ROM_SPIFLASH_BP0 BIT2
#define ESP_ROM_SPIFLASH_BP1 BIT3
#define ESP_ROM_SPIFLASH_BP2 BIT4
#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
#define ESP_ROM_SPIFLASH_QE BIT9
#define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2)
#define FLASH_ID_GD25LQ32C 0xC86016
#ifdef __cplusplus
}
#endif

4
components/esp_rom/linker.lf Normal file
View File

@@ -0,0 +1,4 @@
[mapping:esp_rom]
archive: libesp_rom.a
entries:
esp_rom_spiflash (noflash)

127
components/spi_flash/esp32/spi_flash_rom_patch.c → components/esp_rom/patches/esp_rom_spiflash.c
View File

@@ -1,25 +1,23 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include "esp32/rom/spi_flash.h"
#include "soc/spi_periph.h"
#include "spi_flash_defs.h"
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#endif
#define SPI_IDX 1
#define OTH_IDX 0
#if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
#if CONFIG_IDF_TARGET_ESP32
extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
@@ -31,18 +29,11 @@ static inline bool is_issi_chip(const esp_rom_spiflash_chip_t* chip)
esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi)
{
uint32_t status;
#if CONFIG_IDF_TARGET_ESP32
//wait for spi control ready
while ((REG_READ(SPI_EXT2_REG(1)) & SPI_ST)) {
}
while ((REG_READ(SPI_EXT2_REG(0)) & SPI_ST)) {
}
#elif CONFIG_IDF_TARGET_ESP32S2
while ((REG_READ(SPI_MEM_FSM_REG(1)) & SPI_MEM_ST)) {
}
while ((REG_READ(SPI_MEM_FSM_REG(0)) & SPI_MEM_ST)) {
}
#endif
//wait for flash status ready
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_status(spi, &status)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
@@ -50,10 +41,9 @@ esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *sp
return ESP_ROM_SPIFLASH_RESULT_OK;
}
/* Modified version of esp_rom_spiflash_clear_bp() that replaces version in ROM.
/* Modified version of esp_rom_spiflash_unlock() that replaces version in ROM.
This works around a bug where esp_rom_spiflash_unlock sometimes reads the wrong
This works around a bug where esp_rom_spiflash_clear_bp sometimes reads the wrong
high status byte (RDSR2 result) and then copies it back to the
flash status, which can cause the CMP bit or Status Register
Protect bit to become set.
@@ -63,7 +53,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *sp
about interrupts, CPU coordination, flash mapping. However some of
the functions in esp_spi_flash.c call it.
*/
__attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void)
__attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void)
{
uint32_t status;
uint32_t new_status;
@@ -78,7 +68,7 @@ __attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_unlock(vo
}
/* Clear all bits in the mask.
(This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.)
(This is different from ROM esp_rom_spiflash_clear_bp, which keeps all bits as-is.)
*/
new_status = status & (~ESP_ROM_SPIFLASH_BP_MASK_ISSI);
// Skip if nothing needs to be cleared. Otherwise will waste time waiting for the flash to clear nothing.
@@ -91,7 +81,7 @@ __attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_unlock(vo
}
/* Clear all bits except QE, if it is set.
(This is different from ROM esp_rom_spiflash_unlock, which keeps all bits as-is.)
(This is different from ROM esp_rom_spiflash_clear_bp, which keeps all bits as-is.)
*/
new_status = status & ESP_ROM_SPIFLASH_QE;
SET_PERI_REG_MASK(SPI_CTRL_REG(SPI_IDX), SPI_WRSR_2B);
@@ -110,11 +100,7 @@ __attribute__((__unused__)) esp_rom_spiflash_result_t esp_rom_spiflash_unlock(vo
}
return ret;
}
#if CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
extern uint8_t g_rom_spiflash_dummy_len_plus[];
esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void) __attribute__((alias("esp_rom_spiflash_clear_bp")));
static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_chip_t *spi);
@@ -125,7 +111,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip_internal(esp_rom_sp
// Chip erase.
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
// check erase is finished.
esp_rom_spiflash_wait_idle(spi);
@@ -146,7 +133,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector_internal(esp_rom_
// sector erase 4Kbytes erase is sector erase.
WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
esp_rom_spiflash_wait_idle(spi);
@@ -161,7 +149,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_erase_block_internal(esp_rom_s
// sector erase 4Kbytes erase is sector erase.
WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff);
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
esp_rom_spiflash_wait_idle(spi);
@@ -215,7 +204,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_program_page_internal(esp_rom_
temp_bl = 0;
}
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP);
while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 );
while ( READ_PERI_REG(PERIPHS_SPI_FLASH_CMD ) != 0 ) {
}
esp_rom_spiflash_wait_idle(spi);
}
@@ -231,7 +221,8 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *
while (ESP_ROM_SPIFLASH_BUSY_FLAG == (status_value & ESP_ROM_SPIFLASH_BUSY_FLAG)) {
WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, 0); // clear regisrter
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_RDSR);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
status_value = READ_PERI_REG(PERIPHS_SPI_FLASH_STATUS) & (spi->status_mask);
}
@@ -261,7 +252,8 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t
// update status value by status_value
WRITE_PERI_REG(PERIPHS_SPI_FLASH_STATUS, status_value); // write status regisrter
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WRSR);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
esp_rom_spiflash_wait_idle(spi);
return ESP_ROM_SPIFLASH_RESULT_OK;
@@ -292,7 +284,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chi
REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0) {
}
for (i = 0; i < (ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM >> 2); i++) {
*addr_dest++ = READ_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4);
@@ -304,7 +297,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_read_data(esp_rom_spiflash_chi
WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, temp_addr << 8);
REG_WRITE(SPI_MISO_DLEN_REG(1), ((ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM << 3) - 1) << SPI_USR_MISO_DBITLEN_S);
REG_WRITE(PERIPHS_SPI_FLASH_CMD, SPI_USR);
while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0);
while (REG_READ(PERIPHS_SPI_FLASH_CMD) != 0) {
};
remain_word_num = (0 == (temp_length & 0x3)) ? (temp_length >> 2) : (temp_length >> 2) + 1;
for (i = 0; i < remain_word_num; i++) {
@@ -325,7 +319,8 @@ static esp_rom_spiflash_result_t esp_rom_spiflash_enable_write(esp_rom_spiflash_
//enable write
WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_WREN); // enable write operation
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
// make sure the flash is ready for writing
while (ESP_ROM_SPIFLASH_WRENABLE_FLAG != (flash_status & ESP_ROM_SPIFLASH_WRENABLE_FLAG)) {
@@ -375,7 +370,7 @@ static void spi_cache_mode_switch(uint32_t modebit)
}
}
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void)
esp_rom_spiflash_result_t esp_rom_spiflash_set_bp(void)
{
uint32_t status;
@@ -396,7 +391,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_lock(void)
return ESP_ROM_SPIFLASH_RESULT_OK;
}
esp_rom_spiflash_result_t esp_rom_spiflash_lock(void) __attribute__((alias("esp_rom_spiflash_set_bp")));
esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode)
{
@@ -480,30 +475,31 @@ esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num)
return ESP_ROM_SPIFLASH_RESULT_OK;
}
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t *src_addr, int32_t len)
esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len)
{
uint32_t page_size;
uint32_t pgm_len, pgm_num;
uint8_t i;
uint32_t pgm_len;
uint32_t pgm_num;
uint32_t i;
// flash write is always 1 line currently
REG_CLR_BIT(PERIPHS_SPI_FLASH_USRREG, SPI_USR_DUMMY);
REG_SET_FIELD(PERIPHS_SPI_FLASH_USRREG1, SPI_USR_ADDR_BITLEN, ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN);
//check program size
if ( (target + len) > (g_rom_spiflash_chip.chip_size)) {
if ( (dest_addr + len) > (g_rom_spiflash_chip.chip_size)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
page_size = g_rom_spiflash_chip.page_size;
pgm_len = page_size - (target % page_size);
pgm_len = page_size - (dest_addr % page_size);
if (len < pgm_len) {
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
target, (uint32_t *)src_addr, len)) {
dest_addr, (uint32_t *)src, len)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
} else {
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
target, (uint32_t *)src_addr, pgm_len)) {
dest_addr, (uint32_t *)src, pgm_len)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
@@ -511,7 +507,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t
pgm_num = (len - pgm_len) / page_size;
for (i = 0; i < pgm_num; i++) {
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), page_size)) {
dest_addr + pgm_len, (uint32_t *)src + (pgm_len >> 2), page_size)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
pgm_len += page_size;
@@ -519,7 +515,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t target, const uint32_t
//remain parts to program
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_program_page_internal(&g_rom_spiflash_chip,
target + pgm_len, (uint32_t *)src_addr + (pgm_len >> 2), len - pgm_len)) {
dest_addr + pgm_len, (uint32_t *)src + (pgm_len >> 2), len - pgm_len)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
}
@@ -552,7 +548,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr,
return ret;
}
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_addr, int32_t len)
esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len)
{
// QIO or SIO, non-QIO regard as SIO
uint32_t modebit;
@@ -607,7 +603,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t target, uint32_t *dest_
REG_WRITE(PERIPHS_SPI_FLASH_USRREG2, (0x7 << SPI_USR_COMMAND_BITLEN_S) | 0x03);
}
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, target, dest_addr, len)) {
if ( ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_read_data(&g_rom_spiflash_chip, src_addr, dest, len)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
return ESP_ROM_SPIFLASH_RESULT_OK;
@@ -637,7 +633,7 @@ esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint3
}
//Unlock flash to enable erase
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_unlock(/*&g_rom_spiflash_chip*/)) {
if (ESP_ROM_SPIFLASH_RESULT_OK != esp_rom_spiflash_clear_bp(/*&g_rom_spiflash_chip*/)) {
return ESP_ROM_SPIFLASH_RESULT_ERR;
}
@@ -686,8 +682,21 @@ esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint3
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
{
REG_WRITE(SPI_CMD_REG(SPI_IDX), SPI_FLASH_WRDI);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
return ESP_ROM_SPIFLASH_RESULT_OK;
}
#endif
#elif CONFIG_IDF_TARGET_ESP32S2
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
{
REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WRDI);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) {
}
return ESP_ROM_SPIFLASH_RESULT_OK;
}
#endif // IDF_TARGET
#endif // CONFIG_SPI_FLASH_ROM_DRIVER_PATCH

14
components/esp_system/port/cpu_start.c
View File

@@ -85,19 +85,7 @@
#include "bootloader_mem.h"
#if CONFIG_APP_BUILD_TYPE_ELF_RAM
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
#endif // CONFIG_APP_BUILD_TYPE_ELF_RAM
// Set efuse ROM_LOG_MODE on first boot

1
components/fatfs/test_fatfs_host/Makefile.files
View File

@@ -35,6 +35,7 @@ INCLUDE_DIRS := \
esp32/include \
esp_common/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
spi_flash/include \

2
components/spi_flash/CMakeLists.txt
View File

@@ -1,6 +1,5 @@
idf_build_get_property(target IDF_TARGET)
if(BOOTLOADER_BUILD)
set(srcs "${target}/spi_flash_rom_patch.c")
set(cache_srcs "")
set(priv_requires bootloader_support soc)
else()
@@ -12,7 +11,6 @@ else()
)
set(srcs
"partition.c"
"${target}/spi_flash_rom_patch.c"
)
if(CONFIG_ESPTOOLPY_OCT_FLASH)

7
components/spi_flash/cache_utils.c
View File

@@ -14,34 +14,29 @@
#include <freertos/semphr.h>
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include <esp32/rom/spi_flash.h>
#include <esp32/rom/cache.h>
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/cache.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#endif
#include "esp_rom_spiflash.h"
#include <soc/soc.h>
#include "sdkconfig.h"
#ifndef CONFIG_FREERTOS_UNICORE

20
components/spi_flash/esp32/flash_ops_esp32.c
View File

@@ -1,20 +1,12 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "esp_spi_flash.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/cache.h"
#include "esp_rom_spiflash.h"
static inline void IRAM_ATTR spi_flash_guard_start(void)
{

20
components/spi_flash/esp32c3/flash_ops_esp32c3.c
View File

@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <sys/param.h>
@@ -18,12 +10,12 @@
#include "esp_spi_flash.h"
#include "soc/system_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp32c3/rom/spi_flash.h"
#include "esp32c3/rom/cache.h"
#include "hal/spi_flash_hal.h"
#include "esp_flash.h"
#include "esp_log.h"
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
static const char *TAG = "spiflash_c3";

26
components/spi_flash/esp32c3/spi_flash_rom_patch.c
View File

@@ -1,26 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include "esp32c3/rom/spi_flash.h"
#include "soc/spi_periph.h"
#include "spi_flash_defs.h"
#define SPI_IDX 1
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
{
REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WRDI);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
return ESP_ROM_SPIFLASH_RESULT_OK;
}

20
components/spi_flash/esp32h2/flash_ops_esp32h2.c
View File

@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <sys/param.h>
@@ -18,12 +10,12 @@
#include "esp_spi_flash.h"
#include "soc/system_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp32h2/rom/spi_flash.h"
#include "esp32h2/rom/cache.h"
#include "hal/spi_flash_hal.h"
#include "esp_flash.h"
#include "esp_log.h"
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
static const char *TAG = "spiflash_h2";

26
components/spi_flash/esp32h2/spi_flash_rom_patch.c
View File

@@ -1,26 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include "esp32h2/rom/spi_flash.h"
#include "soc/spi_periph.h"
#include "spi_flash_defs.h"
#define SPI_IDX 1
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
{
REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WRDI);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
return ESP_ROM_SPIFLASH_RESULT_OK;
}

22
components/spi_flash/esp32s2/flash_ops_esp32s2.c
View File

@@ -1,16 +1,8 @@
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <sys/param.h>
@@ -18,12 +10,12 @@
#include "esp_spi_flash.h"
#include "soc/system_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/cache.h"
#include "bootloader_flash.h"
#include "hal/spi_flash_hal.h"
#include "esp_flash.h"
#include "esp_log.h"
#include "esp_rom_spiflash.h"
static const char *TAG = "spiflash_s2";
@@ -71,7 +63,7 @@ esp_rom_spiflash_result_t IRAM_ATTR spi_flash_write_encrypted_chip(size_t dest_a
ops->start();
}
flash_rom_init();
rc = SPI_Encrypt_Write(dest_addr, src, size);
rc = esp_rom_spiflash_write_encrypted(dest_addr, (uint32_t*)src, size);
if (ops && ops->end) {
ops->end();
}

28
components/spi_flash/esp32s2/spi_flash_rom_patch.c
View File

@@ -1,28 +0,0 @@
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "sdkconfig.h"
#include "esp32s2/rom/spi_flash.h"
#include "soc/spi_periph.h"
#include "spi_flash_defs.h"
#define SPI_IDX 1
extern esp_rom_spiflash_chip_t g_rom_spiflash_chip;
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
{
REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WRDI);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
return ESP_ROM_SPIFLASH_RESULT_OK;
}

20
components/spi_flash/esp32s3/flash_ops_esp32s3.c
View File

@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <sys/param.h>
@@ -18,12 +10,12 @@
#include "esp_spi_flash.h"
#include "soc/system_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/cache.h"
#include "bootloader_flash.h"
#include "hal/spi_flash_hal.h"
#include "esp_flash.h"
#include "esp_log.h"
#include "esp_rom_spiflash.h"
static const char *TAG = "spiflash_s3";

5
components/spi_flash/esp32s3/spi_flash_oct_flash_init.c
View File

@@ -30,7 +30,6 @@
const static char *TAG = "Octal Flash";
// default value is rom_default_spiflash_legacy_flash_func
extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
extern int SPI_write_enable(void *spi);
static uint32_t s_chip_id;
@@ -78,7 +77,7 @@ static void s_set_flash_dtr_str_opi_mode(int spi_num, uint8_t val)
int dummy = 0;
int data_bit_len = 8;
SPI_write_enable(&g_rom_flashchip);
esp_rom_spiflash_write_enable(&g_rom_flashchip);
//SPI command, WRCR2
esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_FASTRD_MODE,
SPI_FLASH_SPI_CMD_WRCR2, cmd_len,
@@ -129,7 +128,7 @@ static void s_set_flash_ouput_driver_strength(int spi_num, uint8_t strength)
//Write
//SPI command, WRSR/WRCR
data_bit_len = 16;
SPI_write_enable(&g_rom_flashchip);
esp_rom_spiflash_write_enable(&g_rom_flashchip);
esp_rom_opiflash_exec_cmd(spi_num, ESP_ROM_SPIFLASH_FASTRD_MODE,
SPI_FLASH_SPI_CMD_WRSRCR, cmd_len,
addr, addr_bit_len,

6
components/spi_flash/esp32s3/spi_flash_rom_patch.c
View File

@@ -1,6 +0,0 @@
/*
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// We keep this file here only for future use

4
components/spi_flash/esp8684/flash_ops_esp8684.c
View File

@@ -10,14 +10,14 @@
#include "esp_spi_flash.h"
#include "soc/system_reg.h"
#include "soc/soc_memory_layout.h"
#include "esp8684/rom/spi_flash.h"
#include "esp8684/rom/cache.h"
#include "hal/spi_flash_hal.h"
#include "esp_flash.h"
#include "esp_log.h"
#include "esp_attr.h"
#include "esp_rom_spiflash.h"
static const char *TAG = "spiflash_c3";
static const char *TAG = "spiflash_8684";
#define SPICACHE SPIMEM0
#define SPIFLASH SPIMEM1

18
components/spi_flash/esp8684/spi_flash_rom_patch.c
View File

@@ -1,18 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include "esp8684/rom/spi_flash.h"
#include "soc/spi_periph.h"
#include "spi_flash_defs.h"
#define SPI_IDX 1
esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void)
{
REG_WRITE(SPI_MEM_CMD_REG(SPI_IDX), SPI_MEM_FLASH_WRDI);
while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0);
return ESP_ROM_SPIFLASH_RESULT_OK;
}

14
components/spi_flash/esp_flash_api.c
View File

@@ -16,22 +16,10 @@
#include "esp_flash_internal.h"
#include "spi_flash_defs.h"
#include "esp_rom_caps.h"
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp_crypto_lock.h" // for locking flash encryption peripheral
#endif //CONFIG_IDF_TARGET_ESP32S2
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
static const char TAG[] = "spi_flash";

16
components/spi_flash/esp_flash_spi_init.c
View File

@@ -20,21 +20,7 @@
#include "esp_flash_internal.h"
#include "esp_rom_gpio.h"
#include "esp_private/spi_flash_os.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/efuse.h"
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/efuse.h"
#include "esp8684/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
__attribute__((unused)) static const char TAG[] = "spi_flash";

7
components/spi_flash/flash_mmap.c
View File

@@ -19,26 +19,24 @@
#include "esp_attr.h"
#include "esp_spi_flash.h"
#include "esp_flash_encrypt.h"
#include "esp_rom_spiflash.h"
#include "esp_log.h"
#include "cache_utils.h"
#if CONFIG_IDF_TARGET_ESP32
#include "soc/dport_reg.h"
#include "esp32/rom/cache.h"
#include "esp32/rom/spi_flash.h"
#include "esp32/spiram.h"
#include "soc/mmu.h"
// TODO: IDF-3821
#define INVALID_PHY_PAGE 0xffff
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/spiram.h"
#include "soc/extmem_reg.h"
#include "soc/cache_memory.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/spiram.h"
#include "soc/extmem_reg.h"
@@ -46,17 +44,14 @@
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/spi_flash.h"
#include "soc/cache_memory.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/spi_flash.h"
#include "soc/cache_memory.h"
#include "soc/mmu.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/cache.h"
#include "esp8684/rom/spi_flash.h"
#include "soc/cache_memory.h"
#include "soc/mmu.h"
#endif

6
components/spi_flash/flash_ops.c
View File

@@ -27,23 +27,19 @@
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/cache.h"
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "soc/spi_mem_reg.h"
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#include "esp32s3/rom/cache.h"
#include "esp32s3/opi_flash_private.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/cache.h"
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/cache.h"
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/cache.h"
#include "esp8684/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
#include "esp_flash_partitions.h"
#include "cache_utils.h"
#include "esp_flash.h"

10
components/spi_flash/include/esp_private/spi_flash_os.h
View File

@@ -22,16 +22,8 @@
#include <stdint.h>
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_rom_spiflash.h"
#include "esp_err.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#endif
#include "esp_flash.h"
#include "hal/spi_flash_hal.h"

1
components/spi_flash/linker.lf
View File

@@ -1,7 +1,6 @@
[mapping:spi_flash]
archive: libspi_flash.a
entries:
spi_flash_rom_patch (noflash)
spi_flash_chip_generic (noflash)
spi_flash_chip_issi (noflash)
spi_flash_chip_mxic (noflash)

1
components/spi_flash/sim/Makefile.files
View File

@@ -37,6 +37,7 @@ INCLUDE_DIRS := \
esp32/include \
esp_timer/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
hal/esp32/include \

20
components/spi_flash/sim/SpiFlash.h
View File

@@ -1,16 +1,8 @@
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _SpiFlash_H_
#define _SpiFlash_H_
@@ -18,7 +10,7 @@
#include <stdbool.h>
#include "esp_err.h"
#include "esp32/rom/spi_flash.h"
#include "esp_rom_spiflash.h"
/**
* @brief This class is used to emulate flash devices.

2
components/spi_flash/sim/flash_mock.cpp
View File

@@ -7,7 +7,7 @@
#include "esp_partition.h"
#include "esp_err.h"
#include "esp32/rom/spi_flash.h"
#include "esp_rom_spiflash.h"
SpiFlash spiflash = SpiFlash();

2
components/spi_flash/sim/flash_mock_util.c
View File

@@ -2,7 +2,7 @@
#include "esp_partition.h"
#include "esp_err.h"
#include "esp32/rom/spi_flash.h"
#include "esp_rom_spiflash.h"
bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length)
{

1
components/spi_flash/sim/stubs/Makefile.files
View File

@@ -31,6 +31,7 @@ INCLUDE_DIRS := \
esp32/include \
esp_timer/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
spi_flash/include \

20
components/spi_flash/test/test_large_flash_writes.c
View File

@@ -1,16 +1,8 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Test for spi_flash_write() with large buffers (in RAM or on flash)
@@ -25,7 +17,7 @@
#include <test_utils.h>
#include <esp_spi_flash.h>
#include <esp_log.h>
#include <esp32/rom/spi_flash.h>
#include "esp_rom_spiflash.h"
#include "../cache_utils.h"
#include "soc/timer_periph.h"

11
components/spi_flash/test/test_read_write.c
View File

@@ -18,17 +18,10 @@
#include "../cache_utils.h"
#include "soc/timer_periph.h"
#include "esp_heap_caps.h"
#include "esp_rom_spiflash.h"
#if CONFIG_IDF_TARGET_ESP32
// Used for rom_fix function
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP8684)

12
components/spi_flash/test/test_spi_flash.c
View File

@@ -13,20 +13,12 @@
#include "ccomp_timer.h"
#include "esp_log.h"
#include "esp_rom_sys.h"
#include "esp_rom_spiflash.h"
#include "esp_timer.h"
#include "bootloader_flash.h" //for bootloader_flash_xmc_startup
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP8684)
@@ -425,7 +417,7 @@ TEST_CASE("rom unlock will not erase QE bit", "[spi_flash]")
if (((legacy_chip->device_id >> 16) & 0xff) != 0x9D) {
TEST_IGNORE_MESSAGE("This test is only for ISSI chips. Ignore.");
}
esp_rom_spiflash_unlock();
bootloader_flash_unlock();
esp_rom_spiflash_read_status(legacy_chip, &status);
printf("status: %08x\n", status);

14
components/spiffs/esp_spiffs.c
View File

@@ -21,19 +21,7 @@
#include <sys/lock.h>
#include "esp_vfs.h"
#include "esp_err.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP8684
#include "esp8684/rom/spi_flash.h"
#endif
#include "esp_rom_spiflash.h"
#include "spiffs_api.h"

1
components/spiffs/test_spiffs_host/Makefile.files
View File

@@ -35,6 +35,7 @@ INCLUDE_DIRS := \
soc/include \
esp32/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
spi_flash/include \
hal/include \

1
components/wear_levelling/test_wl_host/Makefile.files
View File

@@ -35,6 +35,7 @@ INCLUDE_DIRS := \
soc/include \
esp32/include \
bootloader_support/include \
bootloader_support/bootloader_flash/include \
app_update/include \
hal/include \
spi_flash/include \

9
docs/en/migration-guides/peripherals.rst
View File

@@ -7,3 +7,12 @@ Peripheral Clock Gating
As usual, peripheral clock gating is still handled by driver itself, users don't need to take care of the peripheral module clock gating.
However, for advanced users who implement their own drivers based on ``hal`` and ``soc`` components, the previous clock gating include path has been changed from ``driver/periph_ctrl.h`` to ``esp_private/periph_ctrl.h``.
SPI Flash Interface
-------------------
Version before v5.0, spi flash functions in rom can be included by ``esp32**/rom/spi_flash.h``. However, your code written for different chips may be filled with ROM headers of different versions. At the meantime not all the APIs can be used on all chips.
Therefore, the common APIs are extracted to ``esp_rom_spiflash.h``. Although it's not a breaking change, it is strongly recommended to only use the functions with prefix ``esp_rom_spiflash`` included by ``esp_rom_spiflash.h`` for better cross-compatibility.
To make the API clearer, we renamed the function ``esp_rom_spiflash_lock`` to ``esp_rom_spiflash_set_bp``. We renamed ``esp_rom_spiflash_unlock`` to ``esp_rom_spiflash_clear_bp``.

16
tools/ci/check_copyright_ignore.txt
View File

@@ -623,7 +623,6 @@ components/esp_rom/include/esp32/rom/miniz.h
components/esp_rom/include/esp32/rom/rsa_pss.h
components/esp_rom/include/esp32/rom/rtc.h
components/esp_rom/include/esp32/rom/sha.h
components/esp_rom/include/esp32/rom/spi_flash.h
components/esp_rom/include/esp32/rom/tbconsole.h
components/esp_rom/include/esp32/rom/tjpgd.h
components/esp_rom/include/esp32/rom/uart.h
@@ -646,7 +645,6 @@ components/esp_rom/include/esp32c3/rom/rom_layout.h
components/esp_rom/include/esp32c3/rom/rsa_pss.h
components/esp_rom/include/esp32c3/rom/rtc.h
components/esp_rom/include/esp32c3/rom/sha.h
components/esp_rom/include/esp32c3/rom/spi_flash.h
components/esp_rom/include/esp32c3/rom/tjpgd.h
components/esp_rom/include/esp32c3/rom/uart.h
components/esp_rom/include/esp32h2/rom/aes.h
@@ -668,7 +666,6 @@ components/esp_rom/include/esp32h2/rom/rom_layout.h
components/esp_rom/include/esp32h2/rom/rsa_pss.h
components/esp_rom/include/esp32h2/rom/rtc.h
components/esp_rom/include/esp32h2/rom/sha.h
components/esp_rom/include/esp32h2/rom/spi_flash.h
components/esp_rom/include/esp32h2/rom/tjpgd.h
components/esp_rom/include/esp32h2/rom/uart.h
components/esp_rom/include/esp32s2/rom/aes.h
@@ -688,7 +685,6 @@ components/esp_rom/include/esp32s2/rom/opi_flash.h
components/esp_rom/include/esp32s2/rom/rsa_pss.h
components/esp_rom/include/esp32s2/rom/rtc.h
components/esp_rom/include/esp32s2/rom/sha.h
components/esp_rom/include/esp32s2/rom/spi_flash.h
components/esp_rom/include/esp32s2/rom/uart.h
components/esp_rom/include/esp32s2/rom/usb/cdc_acm.h
components/esp_rom/include/esp32s2/rom/usb/chip_usb_dw_wrapper.h
@@ -718,7 +714,6 @@ components/esp_rom/include/esp32s3/rom/opi_flash.h
components/esp_rom/include/esp32s3/rom/rom_layout.h
components/esp_rom/include/esp32s3/rom/rsa_pss.h
components/esp_rom/include/esp32s3/rom/sha.h
components/esp_rom/include/esp32s3/rom/spi_flash.h
components/esp_rom/include/esp32s3/rom/tjpgd.h
components/esp_rom/include/esp32s3/rom/uart.h
components/esp_rom/include/esp32s3/rom/usb/cdc_acm.h
@@ -2047,15 +2042,6 @@ components/soc/include/soc/usb_periph.h
components/soc/lldesc.c
components/soc/soc_include_legacy_warn.c
components/spi_flash/cache_utils.h
components/spi_flash/esp32/flash_ops_esp32.c
components/spi_flash/esp32/spi_flash_rom_patch.c
components/spi_flash/esp32c3/flash_ops_esp32c3.c
components/spi_flash/esp32c3/spi_flash_rom_patch.c
components/spi_flash/esp32h2/flash_ops_esp32h2.c
components/spi_flash/esp32h2/spi_flash_rom_patch.c
components/spi_flash/esp32s2/flash_ops_esp32s2.c
components/spi_flash/esp32s2/spi_flash_rom_patch.c
components/spi_flash/esp32s3/flash_ops_esp32s3.c
components/spi_flash/include/esp_flash.h
components/spi_flash/include/esp_flash_internal.h
components/spi_flash/include/esp_flash_spi_init.h
@@ -2073,7 +2059,6 @@ components/spi_flash/include/spi_flash_chip_mxic.h
components/spi_flash/include/spi_flash_chip_winbond.h
components/spi_flash/memspi_host_driver.c
components/spi_flash/sim/SpiFlash.cpp
components/spi_flash/sim/SpiFlash.h
components/spi_flash/sim/flash_mock.cpp
components/spi_flash/sim/flash_mock_util.c
components/spi_flash/sim/sdkconfig/sdkconfig.h
@@ -2086,7 +2071,6 @@ components/spi_flash/spi_flash_chip_mxic_opi.c
components/spi_flash/spi_flash_chip_winbond.c
components/spi_flash/test/test_esp_flash.c
components/spi_flash/test/test_flash_encryption.c
components/spi_flash/test/test_large_flash_writes.c
components/spi_flash/test/test_mmap.c
components/spi_flash/test/test_out_of_bounds_write.c
components/spi_flash/test/test_partition_ext.c