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https://github.com/espressif/esp-idf.git
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test(i3c): Add simple test for i2c mode in i3c peripheral
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# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
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components/esp_driver_i3c/test_apps/i3c_test_apps:
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disable:
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- if: SOC_I3C_MASTER_SUPPORTED != 1
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depends_components:
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- esp_driver_i3c
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# This is the project CMakeLists.txt file for the test subproject
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cmake_minimum_required(VERSION 3.16)
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# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
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set(COMPONENTS main)
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set(EXTRA_COMPONENT_DIRS
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"$ENV{IDF_PATH}/tools/unit-test-app/components"
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)
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include($ENV{IDF_PATH}/tools/cmake/project.cmake)
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project(i3c_master_test)
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if(CONFIG_COMPILER_DUMP_RTL_FILES)
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add_custom_target(check_test_app_sections ALL
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COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
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--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i3c/,${CMAKE_BINARY_DIR}/esp-idf/hal/
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--elf-file ${CMAKE_BINARY_DIR}/i3c_master_test.elf
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find-refs
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--from-sections=.iram0.text
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--to-sections=.flash.text,.flash.rodata
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--exit-code
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DEPENDS ${elf}
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)
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endif()
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message(STATUS "Checking i3c registers are not read-write by half-word")
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include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
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check_register_rw_half_word(SOC_MODULES "i3c_mst" "i3c_mst_mem" "hp_sys_clkrst" "lpperi" "lp_clkrst"
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HAL_MODULES "i3c_master")
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| Supported Targets | ESP32-P4 |
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| ----------------- | -------- |
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set(srcs "test_app_main.c"
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"test_i3c_master_common.c"
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)
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idf_component_register(SRCS ${srcs}
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PRIV_REQUIRES unity test_utils esp_driver_i3c
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WHOLE_ARCHIVE)
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "unity.h"
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#include "unity_test_runner.h"
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#include "unity_test_utils_memory.h"
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#include "esp_heap_caps.h"
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#include "sdkconfig.h"
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#define LEAKS (700)
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void setUp(void)
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{
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unity_utils_record_free_mem();
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}
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void tearDown(void)
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{
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unity_utils_evaluate_leaks_direct(LEAKS);
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}
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void app_main(void)
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{
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unity_run_menu();
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}
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Unlicense OR CC0-1.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include "unity.h"
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#include "esp_err.h"
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#include "driver/i3c_master.h"
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#include "driver/i3c_master_i2c.h"
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#include "esp_system.h"
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#include "freertos/FreeRTOS.h"
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#include "esp_log.h"
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#include "test_utils.h"
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static const char TAG[] = "test-i3c";
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TEST_CASE("I3C bus install-uninstall test", "[i3c]")
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{
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i3c_master_bus_config_t i3c_bus_config = {
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.scl_io_num = 5,
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.sda_io_num = 6,
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.flags.enable_internal_opendrain = true,
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.flags.enable_internal_pullup = true,
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.flags.use_dma = true,
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.flags.enable_async_trans = true,
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.max_transfer_size = 1024,
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.trans_queue_depth = 30,
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};
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i3c_master_bus_handle_t bus_handle;
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// Install master bus 0
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ESP_LOGI(TAG, "Initialize bus0");
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TEST_ESP_OK(i3c_new_master_bus(&i3c_bus_config, &bus_handle));
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// Install master bus 0 again
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ESP_LOGI(TAG, "Initialize bus0 again");
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TEST_ESP_ERR(ESP_ERR_NOT_FOUND, i3c_new_master_bus(&i3c_bus_config, &bus_handle));
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ESP_LOGI(TAG, "Delete bus0");
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TEST_ESP_OK(i3c_del_master_bus(bus_handle));
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}
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TEST_CASE("I3C driver memory leaking check", "[i3c]")
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{
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i3c_master_bus_config_t i3c_bus_config = {
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.scl_io_num = 5,
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.sda_io_num = 6,
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.flags.enable_internal_opendrain = true,
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.flags.enable_internal_pullup = true,
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.flags.use_dma = true,
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.flags.enable_async_trans = true,
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.max_transfer_size = 1024,
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.trans_queue_depth = 30,
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};
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i3c_master_bus_handle_t bus_handle;
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int size = esp_get_free_heap_size();
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for (uint32_t i = 0; i <= 5; i++) {
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TEST_ESP_OK(i3c_new_master_bus(&i3c_bus_config, &bus_handle));
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vTaskDelay(10 / portTICK_PERIOD_MS);
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TEST_ESP_OK(i3c_del_master_bus(bus_handle));
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}
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TEST_ASSERT_INT_WITHIN(300, size, esp_get_free_heap_size());
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}
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TEST_CASE("I3C device add & remove check", "[i3c]")
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{
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i3c_master_bus_config_t i2c_mst_config_1 = {
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.clock_source = I3C_MASTER_CLK_SRC_DEFAULT,
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.scl_io_num = 5,
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.sda_io_num = 6,
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.flags.enable_internal_opendrain = true,
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.flags.enable_internal_pullup = true,
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.flags.use_dma = true,
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.flags.enable_async_trans = true,
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.max_transfer_size = 1024,
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.trans_queue_depth = 30,
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};
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i3c_master_bus_handle_t bus_handle;
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TEST_ESP_OK(i3c_new_master_bus(&i2c_mst_config_1, &bus_handle));
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i3c_device_i2c_config_t dev_cfg_1 = {
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.scl_speed_hz = 100 * 1000,
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.device_address = 0x10,
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};
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i3c_master_i2c_device_handle_t dev_1;
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i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_1, &dev_1);
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i3c_device_i2c_config_t dev_cfg_2 = {
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.scl_speed_hz = 100 * 1000,
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.device_address = 0x20,
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};
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i3c_master_i2c_device_handle_t dev_2;
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i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_2, &dev_2);
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i3c_device_i2c_config_t dev_cfg_3 = {
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.scl_speed_hz = 100 * 1000,
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.device_address = 0x30,
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};
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i3c_master_i2c_device_handle_t dev_3;
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i3c_master_bus_add_i2c_device(bus_handle, &dev_cfg_3, &dev_3);
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i3c_master_bus_rm_i2c_device(dev_1);
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i3c_master_bus_rm_i2c_device(dev_2);
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, i3c_del_master_bus(bus_handle));
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i3c_master_bus_rm_i2c_device(dev_3);
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TEST_ESP_OK(i3c_del_master_bus(bus_handle));
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}
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# SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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# SPDX-License-Identifier: CC0-1.0
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import pytest
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from pytest_embedded import Dut
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from pytest_embedded_idf.utils import idf_parametrize
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from pytest_embedded_idf.utils import soc_filtered_targets
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@pytest.mark.generic
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@pytest.mark.parametrize(
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'config',
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[
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'release',
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'cache_safe',
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],
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indirect=True,
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)
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@idf_parametrize('target', soc_filtered_targets('SOC_I3C_MASTER_SUPPORTED == 1'), indirect=['target'])
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def test_i3c(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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CONFIG_PM_ENABLE=y
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CONFIG_COMPILER_DUMP_RTL_FILES=y
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CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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CONFIG_COMPILER_OPTIMIZATION_NONE=y
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CONFIG_ESP_MAIN_TASK_STACK_SIZE=8192
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CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
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CONFIG_I3C_MASTER_ISR_CACHE_SAFE=y
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CONFIG_PM_ENABLE=y
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CONFIG_FREERTOS_USE_TICKLESS_IDLE=y
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CONFIG_COMPILER_OPTIMIZATION_SIZE=y
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CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
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CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
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CONFIG_FREERTOS_HZ=1000
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CONFIG_ESP_TASK_WDT_INIT=n
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