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Merge branch 'fix/i2s_iram_safe_issue_while_use_psram_v5.4' into 'release/v5.4'
fix(i2s): fixed failure when dma is iram_safe but i2s not (v5.4) See merge request espressif/esp-idf!38003
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@ -3,6 +3,7 @@ menu "ESP-Driver:I2S Configurations"
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config I2S_ISR_IRAM_SAFE
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bool "I2S ISR IRAM-Safe"
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default n
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select GDMA_ISR_IRAM_SAFE if SOC_GDMA_SUPPORTED
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help
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Ensure the I2S interrupt is IRAM-Safe by allowing the interrupt handler to be
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executable when the cache is disabled (e.g. SPI Flash write).
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@ -493,6 +493,7 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu
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handle->dma.desc = (lldesc_t **)heap_caps_calloc(num, sizeof(lldesc_t *), I2S_MEM_ALLOC_CAPS);
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ESP_GOTO_ON_FALSE(handle->dma.desc, ESP_ERR_NO_MEM, err, TAG, "create I2S DMA descriptor array failed");
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handle->dma.bufs = (uint8_t **)heap_caps_calloc(num, sizeof(uint8_t *), I2S_MEM_ALLOC_CAPS);
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ESP_GOTO_ON_FALSE(handle->dma.bufs, ESP_ERR_NO_MEM, err, TAG, "create I2S DMA buffer array failed");
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for (int i = 0; i < num; i++) {
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/* Allocate DMA descriptor */
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handle->dma.desc[i] = (lldesc_t *) i2s_dma_calloc(handle, 1, sizeof(lldesc_t));
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@ -40,7 +40,7 @@ extern "C" {
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// If ISR handler is allowed to run whilst cache is disabled,
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// Make sure all the code and related variables used by the handler are in the SRAM
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#if CONFIG_I2S_ISR_IRAM_SAFE
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#if CONFIG_I2S_ISR_IRAM_SAFE || CONFIG_GDMA_ISR_IRAM_SAFE
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#define I2S_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED | ESP_INTR_FLAG_SHARED)
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#define I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
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#else
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