Merge branch 'feature/support_esp8684_gpio' into 'master'

ESP8684: Support ESP8684 gpio Closes IDF-4019 and IDF-3841 See merge request espressif/esp-idf!15667
2025-08-05 05:34:32 +02:00 · 2021-12-30 09:16:23 +00:00
parent 15380099e3 e0bc3a923c
commit 2906fbfb9e
23 changed files with 270 additions and 245 deletions
--- a/components/driver/test/test_gpio.c
+++ b/components/driver/test/test_gpio.c
@@ -58,7 +58,7 @@
 #define TEST_GPIO_EXT_OUT_IO            2  // default output GPIO
 #define TEST_GPIO_EXT_IN_IO             3  // default input GPIO
 #define TEST_GPIO_OUTPUT_PIN            1
-#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_21
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_MAX
 #define TEST_GPIO_USB_DM_IO             18  // USB D- GPIO
 #define TEST_GPIO_USB_DP_IO             19  // USB D+ GPIO
 #define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  10
@@ -67,7 +67,7 @@
 #define TEST_GPIO_EXT_OUT_IO            2  // default output GPIO
 #define TEST_GPIO_EXT_IN_IO             3  // default input GPIO
 #define TEST_GPIO_OUTPUT_PIN            1
-#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_21
+#define TEST_GPIO_OUTPUT_MAX            GPIO_NUM_MAX
 #define TEST_GPIO_INPUT_LEVEL_HIGH_PIN  10
 #define TEST_GPIO_INPUT_LEVEL_LOW_PIN   1
 #endif
@@ -75,7 +75,7 @@
 // If there is any input-only pin, enable input-only pin part of some tests.
 #define SOC_HAS_INPUT_ONLY_PIN (CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2)

-// define public test io on all boards(esp32, esp32s2, esp32s3, esp32c3)
+// define public test io on all boards
 #define TEST_IO_9 GPIO_NUM_9
 #define TEST_IO_10 GPIO_NUM_10

@@ -95,12 +95,13 @@ static bool wake_up_result = false;  // use this to judge the wake up event happ
 static gpio_config_t init_io(gpio_num_t num)
 {
    TEST_ASSERT(num < TEST_GPIO_OUTPUT_MAX);
-    gpio_config_t io_conf;
-    io_conf.intr_type = GPIO_INTR_DISABLE;
-    io_conf.mode = GPIO_MODE_OUTPUT;
-    io_conf.pin_bit_mask = (1ULL << num);
-    io_conf.pull_down_en = 0;
-    io_conf.pull_up_en = 0;
+    gpio_config_t io_conf = {
+        .intr_type = GPIO_INTR_DISABLE,
+        .mode = GPIO_MODE_OUTPUT,
+        .pin_bit_mask = (1ULL << num),
+        .pull_down_en = 0,
+        .pull_up_en = 0,
+    };
    return io_conf;
 }

@@ -800,11 +801,11 @@ static void gpio_isr_handler(void *arg)
 */
 TEST_CASE("GPIO ISR service test", "[gpio][ignore]")
 {
-    static gpio_isr_param_t io9_param = {
+    gpio_isr_param_t io9_param = {
        .gpio_num =  TEST_IO_9,
        .isr_cnt = 0,
    };
-    static gpio_isr_param_t io10_param = {
+    gpio_isr_param_t io10_param = {
        .gpio_num =  TEST_IO_10,
        .isr_cnt = 0,
    };
--- a/components/hal/esp32c3/include/hal/gpio_ll.h
+++ b/components/hal/esp32c3/include/hal/gpio_ll.h
@@ -18,24 +18,15 @@
 #include "soc/gpio_periph.h"
 #include "soc/gpio_struct.h"
 #include "soc/rtc_cntl_reg.h"
+#include "soc/usb_serial_jtag_reg.h"
 #include "hal/gpio_types.h"
+#include "hal/assert.h"
 #include "stdlib.h"

 #ifdef __cplusplus
 extern "C" {
 #endif

-/*
- * The following defines are used to disable USB JTAG when pins 18 and pins 19
- * are set to be used as GPIO.
- * See gpio_pad_select_gpio() below.
- *
- * TODO: Delete these definitions once the USB device registers definition is
- * merged.
- */
-#define USB_DEVICE_CONF0_REG        (0x60043018)
-#define USB_DEVICE_USB_PAD_ENABLE   (BIT(14))
-
 // Get GPIO hardware instance with giving gpio num
 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)

@@ -140,7 +131,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
  */
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
-    // Not supported on C3
+    // Less than 32 GPIOs on ESP32-C3. Do nothing.
 }

 /**
@@ -152,11 +143,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 */
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
-    if (core_id == 0) {
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
    GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
-    } else {
-        // GPIO.pin[gpio_num].int_ena = GPIO_APP_CPU_INTR_ENA;     //enable pro cpu intr
-    }
 }

 /**
@@ -392,8 +380,9 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
 */
 static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
 {
+    // Disable USB Serial JTAG if pins 18 or pins 19 needs to select an IOMUX function
    if (pin_name == IO_MUX_GPIO18_REG || pin_name == IO_MUX_GPIO19_REG) {
-        CLEAR_PERI_REG_MASK(USB_DEVICE_CONF0_REG, USB_DEVICE_USB_PAD_ENABLE);
+        CLEAR_PERI_REG_MASK(USB_SERIAL_JTAG_CONF0_REG, USB_SERIAL_JTAG_USB_PAD_ENABLE);
    }
    PIN_FUNC_SELECT(pin_name, func);
 }
@@ -548,9 +537,8 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n
 */
 static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    if (gpio_num > GPIO_NUM_5) {
-        abort(); // gpio lager than 5 doesn't support.
-    }
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
    REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE);
    REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER);
    SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
@@ -568,9 +556,8 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gp
 */
 static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    if (gpio_num > GPIO_NUM_5) {
-        abort(); // gpio lager than 5 doesn't support.
-    }
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
    CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
    CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
 }
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@@ -20,6 +20,7 @@
 #include "soc/rtc_io_reg.h"
 #include "soc/gpio_struct.h"
 #include "hal/gpio_types.h"
+#include "hal/assert.h"

 #ifdef __cplusplus
 extern "C" {
@@ -142,9 +143,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 */
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
-    if (core_id == 0) {
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
    GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
-    }
 }

 /**
--- a/components/hal/esp8684/include/hal/gpio_ll.h
+++ b/components/hal/esp8684/include/hal/gpio_ll.h
@@ -18,6 +18,7 @@
 #include "soc/gpio_periph.h"
 #include "soc/rtc_cntl_reg.h"
 #include "hal/gpio_types.h"
+#include "hal/assert.h"
 #include "stdlib.h"

 #ifdef __cplusplus
@@ -37,7 +38,7 @@ extern "C" {
  */
 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
 }

 /**
@@ -48,7 +49,7 @@ static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
 }

 /**
@@ -59,7 +60,7 @@ static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
 }

 /**
@@ -70,7 +71,7 @@ static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
 }

 /**
@@ -82,7 +83,7 @@ static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 */
 static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    abort();// IDF-4019
+    hw->pin[gpio_num].int_type = intr_type;
 }

 /**
@@ -94,7 +95,7 @@ static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gp
  */
 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
-    abort();// IDF-4019
+    *status = hw->pcpu_int.procpu_int;
 }

 /**
@@ -106,7 +107,7 @@ static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uin
  */
 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
 {
-    abort();// IDF-4019
+    *status = 0; // Less than 32 GPIOs in ESP8684
 }

 /**
@@ -117,7 +118,7 @@ static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id
  */
 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
 {
-    abort();// IDF-4019
+    hw->status_w1tc.status_w1tc = mask;
 }

 /**
@@ -128,7 +129,7 @@ static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
  */
 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 {
-    abort();// IDF-4019
+    // Less than 32 GPIOs in ESP8684. Do nothing.
 }

 /**
@@ -140,7 +141,8 @@ static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
 */
 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    HAL_ASSERT(core_id == 0 && "target SoC only has a single core");
+    GPIO.pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA;     //enable pro cpu intr
 }

 /**
@@ -151,7 +153,7 @@ static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id,
 */
 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    hw->pin[gpio_num].int_ena = 0;                             //disable GPIO intr
 }

 /**
@@ -162,7 +164,7 @@ static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -173,7 +175,7 @@ static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -184,7 +186,10 @@ static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    hw->enable_w1tc.enable_w1tc = (0x1 << gpio_num);
+    // Ensure no other output signal is routed via GPIO matrix to this pin
+    REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
+              SIG_GPIO_OUT_IDX);
 }

 /**
@@ -195,7 +200,7 @@ static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    hw->enable_w1ts.enable_w1ts = (0x1 << gpio_num);
 }

 /**
@@ -206,7 +211,7 @@ static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    hw->pin[gpio_num].pad_driver = 0;
 }

 /**
@@ -217,7 +222,7 @@ static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    hw->pin[gpio_num].pad_driver = 1;
 }

 /**
@@ -229,7 +234,11 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 */
 static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
 {
-    abort();// IDF-4019
+    if (level) {
+        hw->out_w1ts.out_w1ts = (1 << gpio_num);
+    } else {
+        hw->out_w1tc.out_w1tc = (1 << gpio_num);
+    }
 }

 /**
@@ -246,7 +255,7 @@ static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32
 */
 static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    return (hw->in.in_data_next >> gpio_num) & 0x1;
 }

 /**
@@ -258,7 +267,8 @@ static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
 */
 static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    abort();// IDF-4019
+    hw->pin[gpio_num].int_type = intr_type;
+    hw->pin[gpio_num].wakeup_enable = 0x1;
 }

 /**
@@ -269,7 +279,7 @@ static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gp
 */
 static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    hw->pin[gpio_num].wakeup_enable = 0;
 }

 /**
@@ -281,7 +291,7 @@ static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
 {
-    abort();// IDF-4019
+    SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
 }

 /**
@@ -293,7 +303,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    abort();// IDF-4019
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
 }

 /**
@@ -303,7 +313,8 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
 {
-    abort();// IDF-4019
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
 }

 /**
@@ -313,7 +324,7 @@ static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
  */
 static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
 {
-    abort();// IDF-4019
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
 }

 /**
@@ -324,7 +335,11 @@ static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
  */
 static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    if (gpio_num <= GPIO_NUM_5) {
+        REG_SET_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num));
+    } else {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
+    }
 }

 /**
@@ -335,7 +350,11 @@ static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    if (gpio_num <= GPIO_NUM_5) {
+        REG_CLR_BIT(RTC_CNTL_PAD_HOLD_REG, BIT(gpio_num));
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
+    }
 }

 /**
@@ -347,7 +366,8 @@ static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
 {
-    abort();// IDF-4019
+    hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
+    PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
 }

 /**
@@ -358,7 +378,7 @@ static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t sign
 */
 static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
 {
-    abort();// IDF-4019
+    PIN_FUNC_SELECT(pin_name, func);
 }

 /**
@@ -372,17 +392,24 @@ static inline void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
  */
 static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
 {
-    abort();// IDF-4019
+    hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
+    hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
+    gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
 }

 static inline void gpio_ll_force_hold_all(gpio_dev_t *hw)
 {
-    abort();// IDF-4019
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
 }

 static inline void gpio_ll_force_unhold_all(void)
 {
-    // abort();// IDF-4019
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_HOLD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_HOLD_M);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CLR_DG_PAD_AUTOHOLD);
 }

 /**
@@ -393,7 +420,7 @@ static inline void gpio_ll_force_unhold_all(void)
  */
 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -404,7 +431,7 @@ static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -415,7 +442,7 @@ static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -426,7 +453,7 @@ static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -437,7 +464,7 @@ static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
  */
 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -448,7 +475,7 @@ static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num
  */
 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -459,7 +486,7 @@ static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_nu
  */
 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -470,7 +497,7 @@ static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_n
  */
 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -481,7 +508,7 @@ static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_nu
  */
 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -492,7 +519,7 @@ static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
 }

 /**
@@ -504,7 +531,15 @@ static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_n
 */
 static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
 {
-    abort();// IDF-4019
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
+    REG_SET_BIT(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN_CLK_GATE);
+    REG_SET_BIT(RTC_CNTL_EXT_WAKEUP_CONF_REG, RTC_CNTL_GPIO_WAKEUP_FILTER);
+    SET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
+    uint32_t reg = REG_READ(RTC_CNTL_GPIO_WAKEUP_REG);
+    reg &= (~(RTC_CNTL_GPIO_PIN0_INT_TYPE_V << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3)));
+    reg |= (intr_type << (RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3));
+    REG_WRITE(RTC_CNTL_GPIO_WAKEUP_REG, reg);
 }

 /**
@@ -515,7 +550,10 @@ static inline void gpio_ll_deepsleep_wakeup_enable(gpio_dev_t *hw, gpio_num_t gp
 */
 static inline void gpio_ll_deepsleep_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
 {
-    abort();// IDF-4019
+    HAL_ASSERT(gpio_num <= GPIO_NUM_5 && "gpio larger than 5 does not support deep sleep wake-up function");
+
+    CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, 1 << (RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE_S - gpio_num));
+    CLEAR_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_PIN0_INT_TYPE_S - gpio_num * 3);
 }

 #ifdef __cplusplus
--- a/components/hal/include/hal/gpio_types.h
+++ b/components/hal/include/hal/gpio_types.h
@@ -294,7 +294,6 @@ typedef enum {
    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
-    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
    GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
@@ -366,23 +365,6 @@ typedef enum {
    GPIO_NUM_18 = 18,   /*!< GPIO18, input and output */
    GPIO_NUM_19 = 19,   /*!< GPIO19, input and output */
    GPIO_NUM_20 = 20,   /*!< GPIO20, input and output */
-    GPIO_NUM_21 = 21,   /*!< GPIO21, input and output */
-    GPIO_NUM_22 = 22,   /*!< GPIO22, input and output */
-    GPIO_NUM_26 = 26,   /*!< GPIO26, input and output */
-    GPIO_NUM_27 = 27,   /*!< GPIO27, input and output */
-    GPIO_NUM_28 = 28,   /*!< GPIO28, input and output */
-    GPIO_NUM_29 = 29,   /*!< GPIO29, input and output */
-    GPIO_NUM_30 = 30,   /*!< GPIO30, input and output */
-    GPIO_NUM_31 = 31,   /*!< GPIO31, input and output */
-    GPIO_NUM_32 = 32,   /*!< GPIO32, input and output */
-    GPIO_NUM_33 = 33,   /*!< GPIO33, input and output */
-    GPIO_NUM_34 = 34,   /*!< GPIO34, input and output */
-    GPIO_NUM_35 = 35,   /*!< GPIO35, input and output */
-    GPIO_NUM_36 = 36,   /*!< GPIO36, input and output */
-    GPIO_NUM_37 = 37,   /*!< GPIO37, input and output */
-    GPIO_NUM_38 = 38,   /*!< GPIO38, input and output */
-    GPIO_NUM_39 = 39,   /*!< GPIO39, input and output */
-    GPIO_NUM_40 = 40,   /*!< GPIO40, input and output */
    GPIO_NUM_MAX,
 /** @endcond */
 } gpio_num_t;
--- a/components/soc/esp32c3/include/soc/io_mux_reg.h
+++ b/components/soc/esp32c3/include/soc/io_mux_reg.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_IO_MUX_REG_H_
 #define _SOC_IO_MUX_REG_H_

@@ -138,9 +130,9 @@
 #define SD_DATA2_GPIO_NUM 9
 #define SD_DATA3_GPIO_NUM 10

-#define MAX_RTC_GPIO_NUM 0
-#define MAX_PAD_GPIO_NUM 22
-#define MAX_GPIO_NUM    22
+#define MAX_RTC_GPIO_NUM 5
+#define MAX_PAD_GPIO_NUM 21
+#define MAX_GPIO_NUM    25

 #define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
 #define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
--- a/components/soc/esp32s2/gpio_periph.c
+++ b/components/soc/esp32s2/gpio_periph.c
@@ -1,16 +1,8 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include "soc/gpio_periph.h"

@@ -62,7 +54,6 @@ const uint32_t GPIO_PIN_MUX_REG[SOC_GPIO_PIN_COUNT] = {
    IO_MUX_GPIO44_REG,
    IO_MUX_GPIO45_REG,
    IO_MUX_GPIO46_REG,
-    0,
 };

 const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
@@ -113,5 +104,4 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
    BIT(23),
    BIT(24),
    BIT(25),
-    BIT(26),
 };
--- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
@@ -217,7 +217,7 @@ config SOC_GPIO_PORT

 config SOC_GPIO_PIN_COUNT
    int
-    default 48
+    default 47

 config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
    bool
@@ -229,7 +229,7 @@ config SOC_GPIO_SUPPORT_FORCE_HOLD

 config SOC_GPIO_VALID_GPIO_MASK
    hex
-    default 0xFFFFFFFFFFFF
+    default 0x7FFFFFFFFFFF

 config SOC_GPIO_SUPPORT_SLP_SWITCH
    bool
--- a/components/soc/esp32s2/include/soc/io_mux_reg.h
+++ b/components/soc/esp32s2/include/soc/io_mux_reg.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_IO_MUX_REG_H_
 #define _SOC_IO_MUX_REG_H_

@@ -138,7 +130,6 @@
 #define IO_MUX_GPIO46_REG	PERIPHS_IO_MUX_GPIO46_U


-#define FUNC_GPIO_GPIO                              1
 #define PIN_FUNC_GPIO								1

 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
--- a/components/soc/esp32s2/include/soc/soc_caps.h
+++ b/components/soc/esp32s2/include/soc/soc_caps.h
@@ -116,18 +116,18 @@
 /*-------------------------- GPIO CAPS ---------------------------------------*/
 // ESP32-S2 has 1 GPIO peripheral
 #define SOC_GPIO_PORT           (1U)
-#define SOC_GPIO_PIN_COUNT      (48)
+#define SOC_GPIO_PIN_COUNT      (47)

-// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
+// On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register.
 // On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1)
 // Force hold is a new function of ESP32-S2
 #define SOC_GPIO_SUPPORT_FORCE_HOLD      (1)

-// 0~47 except from 22~25, 47 are valid
-#define SOC_GPIO_VALID_GPIO_MASK             (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47))
-// GPIO 46, 47 are input only
-#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK     (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47))
+// 0~46 except from 22~25 are valid
+#define SOC_GPIO_VALID_GPIO_MASK             (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25))
+// GPIO 46 is input only
+#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK     (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46))

 // Support to configure slept status
 #define SOC_GPIO_SUPPORT_SLP_SWITCH  (1)
--- a/components/soc/esp32s2/rtc_io_periph.c
+++ b/components/soc/esp32s2/rtc_io_periph.c
@@ -1,16 +1,8 @@
-// Copyright 2018-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include "soc/rtc_io_periph.h"

@@ -62,7 +54,6 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
    -1,//GPIO44
    -1,//GPIO45
    -1,//GPIO46
-    -1,//GPIO47
 };

 //Reg,Mux,Fun,IE,Up,Down,Rtc_number
--- a/components/soc/esp32s3/include/soc/io_mux_reg.h
+++ b/components/soc/esp32s3/include/soc/io_mux_reg.h
@@ -1,16 +1,8 @@
-// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once

 #include "soc.h"
@@ -138,7 +130,6 @@
 #define IO_MUX_GPIO47_REG       PERIPHS_IO_MUX_SPICLK_P_U
 #define IO_MUX_GPIO48_REG       PERIPHS_IO_MUX_SPICLK_N_U

-#define FUNC_GPIO_GPIO                              1
 #define PIN_FUNC_GPIO                               1

 #define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
--- a/components/soc/esp8684/gpio_periph.c
+++ b/components/soc/esp8684/gpio_periph.c
@@ -37,19 +37,19 @@ const uint32_t GPIO_HOLD_MASK[SOC_GPIO_PIN_COUNT] = {
    BIT(3),          //GPIO3
    BIT(4),          //GPIO4
    BIT(5),          //GPIO5
-    BIT(5),     //GPIO6
-    BIT(6),     //GPIO7
-    BIT(3),     //GPIO8
-    BIT(4),     //GPIO9
-    BIT(0),     //GPIO10
-    BIT(15),    //GPIO11
-    BIT(10),    //GPIO12
-    BIT(12),    //GPIO13
-    BIT(8),     //GPIO14
-    BIT(7),     //GPIO15
-    BIT(9),     //GPIO16
-    BIT(11),    //GPIO17
-    BIT(1),     //GPIO18
-    BIT(2),     //GPIO19
-    BIT(13),    //GPIO20
+    BIT(6),          //GPIO6
+    BIT(7),          //GPIO7
+    BIT(8),          //GPIO8
+    BIT(9),          //GPIO9
+    BIT(10),         //GPIO10
+    BIT(11),         //GPIO11
+    BIT(12),         //GPIO12
+    BIT(13),         //GPIO13
+    BIT(14),         //GPIO14
+    BIT(15),         //GPIO15
+    BIT(16),         //GPIO16
+    BIT(17),         //GPIO17
+    BIT(18),         //GPIO18
+    BIT(19),         //GPIO19
+    BIT(20),         //GPIO20
 };
--- a/components/soc/esp8684/include/soc/io_mux_reg.h
+++ b/components/soc/esp8684/include/soc/io_mux_reg.h
@@ -109,7 +109,6 @@
 #define IO_MUX_GPIO19_REG              PERIPHS_IO_MUX_U0RXD_U
 #define IO_MUX_GPIO20_REG              PERIPHS_IO_MUX_U0TXD_U

-#define FUNC_GPIO_GPIO                              1
 #define PIN_FUNC_GPIO								1

 #define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
--- a/components/soc/esp8684/include/soc/soc_caps.h
+++ b/components/soc/esp8684/include/soc/soc_caps.h
@@ -100,8 +100,7 @@
 // GPIO0~5 on ESP8684 can support chip deep sleep wakeup
 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP   (1)

-// GPIO19 on ESP8684 is invalid.
-#define SOC_GPIO_VALID_GPIO_MASK        (((1U<<SOC_GPIO_PIN_COUNT) - 1) & (~(BIT19)))
+#define SOC_GPIO_VALID_GPIO_MASK        ((1U<<SOC_GPIO_PIN_COUNT) - 1)
 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK        (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5)

--- a/examples/peripherals/gpio/generic_gpio/README.md
+++ b/examples/peripherals/gpio/generic_gpio/README.md
@@ -7,16 +7,23 @@ This test code shows how to configure GPIO and how to use it with interruption.
 ## GPIO functions:

 | GPIO                         | Direction | Configuration                                          |
-| -------- | --------- | ------------------------------------------------------ |
-| GPIO18   | output    |                                                        |
-| GPIO19   | output    |                                                        |
-| GPIO4    | input     | pulled up, interrupt from rising edge and falling edge |
-| GPIO5    | input     | pulled up, interrupt from rising edge                  |
+| ---------------------------- | --------- | ------------------------------------------------------ |
+| CONFIG_GPIO_OUTPUT_0         | output    |                                                        |
+| CONFIG_GPIO_OUTPUT_1         | output    |                                                        |
+| CONFIG_GPIO_INPUT_0          | input     | pulled up, interrupt from rising edge and falling edge |
+| CONFIG_GPIO_INPUT_1          | input     | pulled up, interrupt from rising edge                  |

 ## Test:
- 1. Connect GPIO18 with GPIO4
- 2. Connect GPIO19 with GPIO5
- 3. Generate pulses on GPIO18/19, that triggers interrupt on GPIO4/5
+ 1. Connect CONFIG_GPIO_OUTPUT_0 with CONFIG_GPIO_INPUT_0
+ 2. Connect CONFIG_GPIO_OUTPUT_1 with CONFIG_GPIO_INPUT_1
+ 3. Generate pulses on CONFIG_GPIO_OUTPUT_0/1, that triggers interrupt on CONFIG_GPIO_INPUT_0/1
+
+ **Note:** The following pin assignments are used by default, you can change them by `idf.py menuconfig` > `Example Configuration`.
+
+|                 | CONFIG_GPIO_OUTPUT_0 | CONFIG_GPIO_OUTPUT_1 | CONFIG_GPIO_INPUT_0 | CONFIG_GPIO_INPUT_1 |
+| --------------- | -------------------- | -------------------- | ------------------- | ------------------- |
+| ESP8684/ESP32H2 | 8                    | 9                    | 4                   | 5                   |
+| All other chips | 18                   | 19                   | 4                   | 5                   |

 ## How to use example

@@ -24,7 +31,7 @@ Before project configuration and build, be sure to set the correct chip target u

 ### Hardware Required

-* A development board with ESP32/ESP32-S2/ESP32-C3 SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
+* A development board with with any Espressif SoC (e.g., ESP32-DevKitC, ESP-WROVER-KIT, etc.)
 * A USB cable for Power supply and programming
 * Some jumper wires to connect GPIOs.

@@ -38,11 +45,7 @@ Run `idf.py -p PORT flash monitor` to build, flash and monitor the project.

 (To exit the serial monitor, type ``Ctrl-]``.)

-See the Getting Started Guide for all the steps to configure and use the ESP-IDF to build projects.
-
-* [ESP-IDF Getting Started Guide on ESP32](https://docs.espressif.com/projects/esp-idf/en/latest/esp32/get-started/index.html)
-* [ESP-IDF Getting Started Guide on ESP32-S2](https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/get-started/index.html)
-* [ESP-IDF Getting Started Guide on ESP32-C3](https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/get-started/index.html)
+See the [Getting Started Guide](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/index.html) for full steps to configure and use ESP-IDF to build projects.

 ## Example Output

@@ -56,14 +59,28 @@ I (347) gpio: GPIO[5]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldow
 Minimum free heap size: 289892 bytes
 cnt: 0
 cnt: 1
+GPIO[4] intr, val: 1
+GPIO[5] intr, val: 1
 cnt: 2
+GPIO[4] intr, val: 0
 cnt: 3
+GPIO[4] intr, val: 1
+GPIO[5] intr, val: 1
 cnt: 4
+GPIO[4] intr, val: 0
 cnt: 5
+GPIO[4] intr, val: 1
+GPIO[5] intr, val: 1
 cnt: 6
+GPIO[4] intr, val: 0
 cnt: 7
+GPIO[4] intr, val: 1
+GPIO[5] intr, val: 1
 cnt: 8
+GPIO[4] intr, val: 0
 cnt: 9
+GPIO[4] intr, val: 1
+GPIO[5] intr, val: 1
 cnt: 10
 ...
 ```
--- a/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild
+++ b/examples/peripherals/gpio/generic_gpio/main/Kconfig.projbuild
@@ -0,0 +1,29 @@
+menu "Example Configuration"
+
+    config GPIO_OUTPUT_0
+        int "GPIO output pin 0"
+        default 18 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+        default 8 if IDF_TARGET_ESP8684 || IDF_TARGET_ESP32H2
+        help
+            GPIO pin number to be used as GPIO_OUTPUT_IO_0.
+
+    config GPIO_OUTPUT_1
+        int "GPIO output pin 1"
+        default 19 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+        default 9 if IDF_TARGET_ESP8684 || IDF_TARGET_ESP32H2
+        help
+            GPIO pin number to be used as GPIO_OUTPUT_IO_1.
+
+    config GPIO_INPUT_0
+        int "GPIO input pin 0"
+        default 4
+        help
+            GPIO pin number to be used as GPIO_INPUT_IO_0.
+
+    config GPIO_INPUT_1
+        int "GPIO input pin 1"
+        default 5
+        help
+            GPIO pin number to be used as GPIO_INPUT_IO_1.
+
+endmenu
--- a/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
+++ b/examples/peripherals/gpio/generic_gpio/main/gpio_example_main.c
@@ -19,23 +19,26 @@
 * This test code shows how to configure gpio and how to use gpio interrupt.
 *
 * GPIO status:
- * GPIO18: output
- * GPIO19: output
+ * GPIO18: output (ESP8684/ESP32H2 uses GPIO8 as the second output pin)
+ * GPIO19: output (ESP8684/ESP32H2 uses GPIO9 as the second output pin)
 * GPIO4:  input, pulled up, interrupt from rising edge and falling edge
 * GPIO5:  input, pulled up, interrupt from rising edge.
 *
+ * Note. These are the default GPIO pins to be used in the example. You can
+ * change IO pins in menuconfig.
+ *
 * Test:
- * Connect GPIO18 with GPIO4
- * Connect GPIO19 with GPIO5
- * Generate pulses on GPIO18/19, that triggers interrupt on GPIO4/5
+ * Connect GPIO18(8) with GPIO4
+ * Connect GPIO19(9) with GPIO5
+ * Generate pulses on GPIO18(8)/19(9), that triggers interrupt on GPIO4/5
 *
 */

-#define GPIO_OUTPUT_IO_0    18
-#define GPIO_OUTPUT_IO_1    19
+#define GPIO_OUTPUT_IO_0    CONFIG_GPIO_OUTPUT_0
+#define GPIO_OUTPUT_IO_1    CONFIG_GPIO_OUTPUT_1
 #define GPIO_OUTPUT_PIN_SEL  ((1ULL<<GPIO_OUTPUT_IO_0) | (1ULL<<GPIO_OUTPUT_IO_1))
-#define GPIO_INPUT_IO_0     4
-#define GPIO_INPUT_IO_1     5
+#define GPIO_INPUT_IO_0     CONFIG_GPIO_INPUT_0
+#define GPIO_INPUT_IO_1     CONFIG_GPIO_INPUT_1
 #define GPIO_INPUT_PIN_SEL  ((1ULL<<GPIO_INPUT_IO_0) | (1ULL<<GPIO_INPUT_IO_1))
 #define ESP_INTR_FLAG_DEFAULT 0

--- a/examples/system/deep_sleep/main/Kconfig.projbuild
+++ b/examples/system/deep_sleep/main/Kconfig.projbuild
@@ -22,7 +22,7 @@ menu "Example Configuration"
    config EXAMPLE_EXT1_WAKEUP
        bool "Enable wakeup from GPIO"
        default y
-        depends on !IDF_TARGET_ESP32C3
+        depends on !SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
        help
            This option enables wake up from deep sleep from GPIO2 and GPIO4. They should be connected to LOW to avoid
            floating pins. When triggering a wake up, connect one or both of the pins to HIGH. Note that floating
@@ -31,13 +31,13 @@ menu "Example Configuration"
    config EXAMPLE_GPIO_WAKEUP
        bool "Enable wakeup from GPIO"
        default y
-        depends on IDF_TARGET_ESP32C3
+        depends on SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
        help
-            This option enables wake up from GPIO, only GPIO0~5 can be used to wake up. Be aware that if you use low level
-            to trigger wakeup, we strongly recommand you to connect external pull-up resistance.
+            This option enables wake up from GPIO, only GPIO0~5 can be used to wake up. Be aware that if you use low
+            level to trigger wakeup, we strongly recommand you to connect external pull-up resistance.

    menu "GPIO wakeup configuration"
-        visible if IDF_TARGET_ESP32C3
+        visible if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP

        config EXAMPLE_GPIO_WAKEUP_PIN
            int "Enable wakeup from GPIO"
--- a/examples/system/deep_sleep/main/deep_sleep_example_main.c
+++ b/examples/system/deep_sleep/main/deep_sleep_example_main.c
@@ -31,7 +31,7 @@
 #include "driver/touch_pad.h"
 #endif

-#ifdef CONFIG_IDF_TARGET_ESP32C3
+#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
 #define DEFAULT_WAKEUP_PIN      CONFIG_EXAMPLE_GPIO_WAKEUP_PIN
 #ifdef CONFIG_EXAMPLE_GPIO_WAKEUP_HIGH_LEVEL
 #define DEFAULT_WAKEUP_LEVEL    ESP_GPIO_WAKEUP_GPIO_HIGH
--- a/tools/ci/check_copyright_ignore.txt
+++ b/tools/ci/check_copyright_ignore.txt
@@ -1693,7 +1693,6 @@ components/soc/esp32c3/include/soc/i2s_reg.h
 components/soc/esp32c3/include/soc/i2s_struct.h
 components/soc/esp32c3/include/soc/interrupt_core0_reg.h
 components/soc/esp32c3/include/soc/interrupt_reg.h
-components/soc/esp32c3/include/soc/io_mux_reg.h
 components/soc/esp32c3/include/soc/ledc_reg.h
 components/soc/esp32c3/include/soc/mmu.h
 components/soc/esp32c3/include/soc/nrx_reg.h
@@ -1759,7 +1758,6 @@ components/soc/esp32h2/include/soc/gpio_sd_struct.h
 components/soc/esp32h2/include/soc/gpio_struct.h
 components/soc/esp32h2/include/soc/hwcrypto_reg.h
 components/soc/esp32h2/include/soc/interrupt_reg.h
-components/soc/esp32h2/include/soc/io_mux_reg.h
 components/soc/esp32h2/include/soc/ledc_reg.h
 components/soc/esp32h2/include/soc/mmu.h
 components/soc/esp32h2/include/soc/nrx_reg.h
@@ -1793,7 +1791,6 @@ components/soc/esp32h2/uart_periph.c
 components/soc/esp32s2/adc_periph.c
 components/soc/esp32s2/dac_periph.c
 components/soc/esp32s2/dedic_gpio_periph.c
-components/soc/esp32s2/gpio_periph.c
 components/soc/esp32s2/i2c_periph.c
 components/soc/esp32s2/i2s_periph.c
 components/soc/esp32s2/include/soc/adc_channel.h
@@ -1829,7 +1826,6 @@ components/soc/esp32s2/include/soc/i2c_struct.h
 components/soc/esp32s2/include/soc/i2s_reg.h
 components/soc/esp32s2/include/soc/i2s_struct.h
 components/soc/esp32s2/include/soc/interrupt_reg.h
-components/soc/esp32s2/include/soc/io_mux_reg.h
 components/soc/esp32s2/include/soc/ledc_reg.h
 components/soc/esp32s2/include/soc/ledc_struct.h
 components/soc/esp32s2/include/soc/memprot_defs.h
@@ -1886,7 +1882,6 @@ components/soc/esp32s2/interrupts.c
 components/soc/esp32s2/ledc_periph.c
 components/soc/esp32s2/pcnt_periph.c
 components/soc/esp32s2/rmt_periph.c
-components/soc/esp32s2/rtc_io_periph.c
 components/soc/esp32s2/sigmadelta_periph.c
 components/soc/esp32s2/spi_periph.c
 components/soc/esp32s2/touch_sensor_periph.c
@@ -1934,7 +1929,6 @@ components/soc/esp32s3/include/soc/interrupt_core1_reg.h
 components/soc/esp32s3/include/soc/interrupt_core1_struct.h
 components/soc/esp32s3/include/soc/interrupt_reg.h
 components/soc/esp32s3/include/soc/interrupt_struct.h
-components/soc/esp32s3/include/soc/io_mux_reg.h
 components/soc/esp32s3/include/soc/ledc_reg.h
 components/soc/esp32s3/include/soc/ledc_struct.h
 components/soc/esp32s3/include/soc/mmu.h
--- a/tools/unit-test-app/partition_table_unit_test_app_2m.csv
+++ b/tools/unit-test-app/partition_table_unit_test_app_2m.csv
@@ -0,0 +1,17 @@
+# Special partition table for unit test app
+#
+# Name,     Type, SubType, Offset,   Size, Flags
+# Note: if you have increased the bootloader size, make sure to update the offsets to avoid overlap
+nvs,        data, nvs,      0xb000,  0x5000
+otadata,    data, ota,      0x10000,  0x2000
+phy_init,   data, phy,      0x12000,  0x1000
+factory,    0,    0,        0x20000, 0x160000
+# these OTA partitions are used for tests, but can't fit real OTA apps in them
+# (done this way to reduce total flash usage.)
+ota_0,      0,    ota_0,    ,        64K
+ota_1,      0,    ota_1,    ,        64K
+# flash_test partition used for SPI flash tests, WL FAT tests, and SPIFFS tests
+flash_test, data, fat,      ,        320K
+nvs_key,    data, nvs_keys, ,        0x1000, encrypted
+
+# Note: occupied 1.85MB in the 2MB flash
--- a/tools/unit-test-app/sdkconfig.defaults.esp8684
+++ b/tools/unit-test-app/sdkconfig.defaults.esp8684
@@ -0,0 +1,4 @@
+CONFIG_ESP_SYSTEM_MEMPROT_FEATURE=n
+CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
+CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partition_table_unit_test_app_2m.csv"
+CONFIG_PARTITION_TABLE_FILENAME="partition_table_unit_test_app_2m.csv"