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Merge branch 'feat/p4_eco5_gdma' into 'master'

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feat(gdma): update gdma struct on p4 eco5

Closes IDF-13729

See merge request espressif/esp-idf!41569
This commit is contained in:
Chen Ji Chang
2025-09-02 11:12:37 +08:00
parent 5e4f67cc68 444346d3b3
commit 290e3d655d
7 changed files with 547 additions and 6077 deletions
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135
components/hal/esp32p4/include/hal/ahb_dma_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -69,6 +69,31 @@ static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev)
dev->intr_mem_end_addr.val = 0x4FFC0000;
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
/**
* @brief Enable the weighted arbitration for AHB-DMA
*
* @param dev DMA register base address
* @param enable True to enable, false to disable
*/
static inline void ahb_dma_ll_enable_weighted_arb(ahb_dma_dev_t *dev, bool enable)
{
dev->weight_en.weight_en = enable;
}
/**
* @brief Set the weighted arbitration timeout for AHB-DMA
*
* @param dev DMA register base address
* @param timeout AHB bus clock cycle
*/
static inline void ahb_dma_ll_set_weighted_arb_timeout(ahb_dma_dev_t *dev, uint32_t timeout)
{
HAL_ASSERT(timeout != 0 && timeout <= 65535);
dev->arb_timeout.arb_timeout_num = timeout;
}
#endif
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word
@@ -136,6 +161,34 @@ static inline void ahb_dma_ll_rx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin
dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
}
#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
/**
* @brief Set RX channel burst size
*/
static inline void ahb_dma_ll_rx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz)
{
uint8_t burst_mode = 0;
switch (sz) {
case 4:
burst_mode = 0; // single
break;
case 16:
burst_mode = 1; // incr4
break;
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
}
dev->channel[channel].in.in_conf0.in_data_burst_mode_sel_chn = burst_mode;
}
#endif
/**
* @brief Reset DMA RX channel FSM and FIFO pointer
*/
@@ -297,6 +350,32 @@ static inline void ahb_dma_ll_rx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
dev->channel[channel].in.in_conf0.in_etm_en_chn = enable;
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
/**
* @brief Enable the weighted arbitration optimize for DMA RX channel
*
* @param dev DMA register base address
* @param channel Channel ID
* @param enable True to enable, false to disable
*/
static inline void ahb_dma_ll_rx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->in_crc_arb[channel].arb_weight_opt.rx_arb_weight_opt_dis_chn = !enable;
}
/**
* @brief Set the weight for DMA RX channel
*
* @param dev DMA register base address
* @param channel Channel ID
* @param weight Weight value
*/
static inline void ahb_dma_ll_rx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->in_crc_arb[channel].ch_arb_weight.rx_arb_weight_value_chn = weight;
}
#endif
///////////////////////////////////// TX /////////////////////////////////////////
/**
* @brief Get DMA TX channel interrupt status word
@@ -364,6 +443,34 @@ static inline void ahb_dma_ll_tx_enable_descriptor_burst(ahb_dma_dev_t *dev, uin
dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
}
#if GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE
/**
* @brief Set TX channel burst size
*/
static inline void ahb_dma_ll_tx_set_burst_size(ahb_dma_dev_t *dev, uint32_t channel, uint32_t sz)
{
uint8_t burst_mode = 0;
switch (sz) {
case 4:
burst_mode = 0; // single
break;
case 16:
burst_mode = 1; // incr4
break;
case 32:
burst_mode = 2; // incr8
break;
case 64:
burst_mode = 3; // incr16
break;
default:
HAL_ASSERT(false);
break;
}
dev->channel[channel].out.out_conf0.out_data_burst_mode_sel_chn = burst_mode;
}
#endif
/**
* @brief Set TX channel EOF mode
*/
@@ -523,6 +630,32 @@ static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
/**
* @brief Enable the weighted arbitration optimize for DMA TX channel
*
* @param dev DMA register base address
* @param channel Channel ID
* @param enable True to enable, false to disable
*/
static inline void ahb_dma_ll_tx_enable_weighted_arb_opt(ahb_dma_dev_t *dev, uint32_t channel, bool enable)
{
dev->out_crc_arb[channel].arb_weight_opt.tx_arb_weight_opt_dis_chn = !enable;
}
/**
* @brief Set the weight for DMA TX channel
*
* @param dev DMA register base address
* @param channel Channel ID
* @param weight Weight value
*/
static inline void ahb_dma_ll_tx_set_weight(ahb_dma_dev_t *dev, uint32_t channel, uint32_t weight)
{
dev->out_crc_arb[channel].ch_arb_weight.tx_arb_weight_value_chn = weight;
}
#endif
///////////////////////////////////// CRC-TX /////////////////////////////////////////
/**

5
components/hal/esp32p4/include/hal/gdma_ll.h
View File

@@ -14,6 +14,7 @@
#include <stdbool.h>
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/soc_etm_source.h"
#include "hal/config.h"
#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
@@ -49,6 +50,10 @@
#define GDMA_LL_AXI_DESC_ALIGNMENT 8
#define GDMA_LL_MAX_BURST_SIZE_PSRAM 128 // PSRAM controller doesn't support burst access with size > 128 bytes
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define GDMA_LL_AHB_BURST_SIZE_ADJUSTABLE 1 // AHB GDMA supports adjustable burst size
#endif
#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \
(uint32_t[2][GDMA_ETM_EVENT_MAX]){ \
{ \

5
components/hal/platform_port/include/hal/config.h
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@@ -49,6 +49,11 @@ extern "C" {
*/
#define HAL_CONFIG_ECDSA_GEN_SIG_CM CONFIG_HAL_ECDSA_GEN_SIG_CM
/**
* @brief The minimum supported chip revision.
*/
#define HAL_CONFIG_CHIP_SUPPORT_MIN_REV CONFIG_ESP_REV_MIN_FULL
#ifdef __cplusplus
}
#endif

3866
components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_eco5_struct.h
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File diff suppressed because it is too large Load Diff

436
components/soc/esp32p4/register/hw_ver3/soc/ahb_dma_struct.h
View File

@@ -55,7 +55,11 @@ typedef union {
* underflow.
*/
uint32_t infifo_udf_chn_int_raw: 1;
uint32_t reserved_7: 25;
/** in_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt status of AHB_DMA_IN_RESP_ERR_CHN_INT
*/
uint32_t in_ahbinf_resp_err_chn_int_raw:1;
uint32_t reserved_8: 24;
};
uint32_t val;
} ahb_dma_in_int_raw_chn_reg_t;
@@ -93,7 +97,11 @@ typedef union {
* The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t infifo_udf_chn_int_st: 1;
uint32_t reserved_7: 25;
/** in_ahbinf_resp_err_chn_int_st : RO; bitpos: [7]; default: 0;
* The masked interrupt status of AHB_DMA_IN_RESP_ERR_CHN_INT
*/
uint32_t in_ahbinf_resp_err_chn_int_st: 1;
uint32_t reserved_8: 24;
};
uint32_t val;
} ahb_dma_in_int_st_chn_reg_t;
@@ -131,7 +139,11 @@ typedef union {
* The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t infifo_udf_chn_int_ena: 1;
uint32_t reserved_7: 25;
/** in_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [7]; default: 0;
* Write 1 to enable AHB_DMA_IN_RESP_ERR_CHN_INT
*/
uint32_t in_ahbinf_resp_err_chn_int_ena: 1;
uint32_t reserved_8: 24;
};
uint32_t val;
} ahb_dma_in_int_ena_chn_reg_t;
@@ -169,7 +181,11 @@ typedef union {
* Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t infifo_udf_chn_int_clr: 1;
uint32_t reserved_7: 25;
/** in_ahbinf_resp_err_chn_int_clr : WT; bitpos: [7]; default: 0;
* Write 1 to clear AHB_DMA_IN_RESP_ERR_CHN_INT
*/
uint32_t in_ahbinf_resp_err_chn_int_clr: 1;
uint32_t reserved_8: 24;
};
uint32_t val;
} ahb_dma_in_int_clr_chn_reg_t;
@@ -211,7 +227,11 @@ typedef union {
* underflow.
*/
uint32_t outfifo_udf_chn_int_raw: 1;
uint32_t reserved_6: 26;
/** out_ahbinf_resp_err_chn_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt status of AHB_DMA_OUT_RESP_ERR_CHN_INT
*/
uint32_t out_ahbinf_resp_err_chn_int_raw:1;
uint32_t reserved_7:25;
};
uint32_t val;
} ahb_dma_out_int_raw_chn_reg_t;
@@ -245,7 +265,11 @@ typedef union {
* The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t outfifo_udf_chn_int_st: 1;
uint32_t reserved_6: 26;
/** out_ahbinf_resp_err_chn_int_st : RO; bitpos: [6]; default: 0;
* The masked interrupt status of AHB_DMA_OUT_RESP_ERR_CHN_INT
*/
uint32_t out_ahbinf_resp_err_chn_int_st:1;
uint32_t reserved_7:25;
};
uint32_t val;
} ahb_dma_out_int_st_chn_reg_t;
@@ -279,7 +303,11 @@ typedef union {
* The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t outfifo_udf_chn_int_ena: 1;
uint32_t reserved_6: 26;
/** out_ahbinf_resp_err_chn_int_ena : R/W; bitpos: [6]; default: 0;
* Write 1 to enable AHB_DMA_OUT_RESP_ERR_CHN_INT
*/
uint32_t out_ahbinf_resp_err_chn_int_ena: 1;
uint32_t reserved_7: 25;
};
uint32_t val;
} ahb_dma_out_int_ena_chn_reg_t;
@@ -313,7 +341,11 @@ typedef union {
* Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
*/
uint32_t outfifo_udf_chn_int_clr: 1;
uint32_t reserved_6: 26;
/** out_ahbinf_resp_err_chn_int_clr : WT; bitpos: [6]; default: 0;
* Write 1 to clear AHB_DMA_OUT_RESP_ERR_CHN_INT
*/
uint32_t out_ahbinf_resp_err_chn_int_clr: 1;
uint32_t reserved_7: 25;
};
uint32_t val;
} ahb_dma_out_int_clr_chn_reg_t;
@@ -396,7 +428,15 @@ typedef union {
* task.
*/
uint32_t in_etm_en_chn: 1;
uint32_t reserved_6: 26;
/** in_data_burst_mode_sel_chn : R/W; bitpos: [7:6]; default: 1;
* Configures max burst size for Rx channeln.
* 2'b00: single
* 2'b01: incr4
* 2'b10: incr8
* 2'b11: incr16
*/
uint32_t in_data_burst_mode_sel_chn: 2;
uint32_t reserved_8: 24;
};
uint32_t val;
} ahb_dma_in_conf0_chn_reg_t;
@@ -564,13 +604,21 @@ typedef union {
* task.
*/
uint32_t out_etm_en_chn: 1;
uint32_t reserved_7: 25;
/** out_data_burst_mode_sel_chn : R/W; bitpos: [9:8]; default: 1;
* Configures max burst size for TX channeln.
* 2'b00: single
* 2'b01: incr4
* 2'b10: incr8
* 2'b11: incr16
*/
uint32_t out_data_burst_mode_sel_chn:2;
uint32_t reserved_10:22;
};
uint32_t val;
} ahb_dma_out_conf0_chn_reg_t;
/** Type of out_crc_init_data_chn register
* This register is used to config ch0 crc initial data(max 32 bit)
* This register is used to config chn crc initial data(max 32 bit)
*/
typedef union {
struct {
@@ -583,7 +631,7 @@ typedef union {
} ahb_dma_out_crc_init_data_chn_reg_t;
/** Type of tx_crc_width_chn register
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
* This register is used to config tx chn crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -603,7 +651,7 @@ typedef union {
} ahb_dma_tx_crc_width_chn_reg_t;
/** Type of out_crc_clear_chn register
* This register is used to clear ch0 crc result
* This register is used to clear chn crc result
*/
typedef union {
struct {
@@ -617,7 +665,7 @@ typedef union {
} ahb_dma_out_crc_clear_chn_reg_t;
/** Type of out_crc_final_result_chn register
* This register is used to store ch0 crc result
* This register is used to store chn crc result
*/
typedef union {
struct {
@@ -630,7 +678,7 @@ typedef union {
} ahb_dma_out_crc_final_result_chn_reg_t;
/** Type of tx_crc_en_wr_data_chn register
* This resister is used to config ch0 crc en for every bit
* This resister is used to config chn crc en for every bit
*/
typedef union {
struct {
@@ -643,7 +691,7 @@ typedef union {
} ahb_dma_tx_crc_en_wr_data_chn_reg_t;
/** Type of tx_crc_en_addr_chn register
* This register is used to config ch0 crc en addr
* This register is used to config chn crc en addr
*/
typedef union {
struct {
@@ -688,13 +736,13 @@ typedef union {
typedef union {
struct {
/** tx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
* reserved
* Configures the weight(i.e the number of tokens) of TX channeln
*/
uint32_t tx_ch_arb_weigh_chn: 4;
uint32_t tx_arb_weight_value_chn: 4;
uint32_t reserved_4: 28;
};
uint32_t val;
} ahb_dma_tx_ch_arb_weigh_chn_reg_t;
} ahb_dma_tx_ch_arb_weight_chn_reg_t;
/** Type of tx_arb_weigh_opt_dir_chn register
* This register is used to config off or on weigh optimization
@@ -704,14 +752,14 @@ typedef union {
/** tx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t tx_arb_weigh_opt_dir_chn: 1;
uint32_t tx_arb_weight_opt_dis_chn: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t;
} ahb_dma_tx_arb_weight_opt_dis_chn_reg_t;
/** Type of in_crc_init_data_chn register
* This register is used to config ch0 crc initial data(max 32 bit)
* This register is used to config chn crc initial data(max 32 bit)
*/
typedef union {
struct {
@@ -724,7 +772,7 @@ typedef union {
} ahb_dma_in_crc_init_data_chn_reg_t;
/** Type of rx_crc_width_chn register
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
* This register is used to config rx chn crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -744,7 +792,7 @@ typedef union {
} ahb_dma_rx_crc_width_chn_reg_t;
/** Type of in_crc_clear_chn register
* This register is used to clear ch0 crc result
* This register is used to clear chn crc result
*/
typedef union {
struct {
@@ -758,7 +806,7 @@ typedef union {
} ahb_dma_in_crc_clear_chn_reg_t;
/** Type of in_crc_final_result_chn register
* This register is used to store ch0 crc result
* This register is used to store chn crc result
*/
typedef union {
struct {
@@ -771,7 +819,7 @@ typedef union {
} ahb_dma_in_crc_final_result_chn_reg_t;
/** Type of rx_crc_en_wr_data_chn register
* This resister is used to config ch0 crc en for every bit
* This resister is used to config chn crc en for every bit
*/
typedef union {
struct {
@@ -784,7 +832,7 @@ typedef union {
} ahb_dma_rx_crc_en_wr_data_chn_reg_t;
/** Type of rx_crc_en_addr_chn register
* This register is used to config ch0 crc en addr
* This register is used to config chn crc en addr
*/
typedef union {
struct {
@@ -828,14 +876,14 @@ typedef union {
*/
typedef union {
struct {
/** rx_ch_arb_weigh_chn : R/W; bitpos: [3:0]; default: 0;
* reserved
/** rx_ch_arb_weight_chn : R/W; bitpos: [3:0]; default: 0;
* Configures the weight(i.e the number of tokens) of RX channeln
*/
uint32_t rx_ch_arb_weigh_chn: 4;
uint32_t rx_arb_weight_value_chn: 4;
uint32_t reserved_4: 28;
};
uint32_t val;
} ahb_dma_rx_ch_arb_weigh_chn_reg_t;
} ahb_dma_rx_ch_arb_weight_chn_reg_t;
/** Type of rx_arb_weigh_opt_dir_chn register
* This register is used to config off or on weigh optimization
@@ -845,11 +893,11 @@ typedef union {
/** rx_arb_weigh_opt_dir_chn : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t rx_arb_weigh_opt_dir_chn: 1;
uint32_t rx_arb_weight_opt_dis_chn: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t;
} ahb_dma_rx_arb_weight_opt_dis_chn_reg_t;
/** Type of in_link_addr_chn register
* Link descriptor configure of Rx channel 0
@@ -907,69 +955,13 @@ typedef union {
uint32_t val;
} ahb_dma_intr_mem_end_addr_reg_t;
/** Type of arb_timeout_tx register
* This retister is used to config arbiter time slice for tx dir
*/
typedef union {
struct {
/** arb_timeout_tx : R/W; bitpos: [15:0]; default: 0;
* This register is used to config arbiter time out value
*/
uint32_t arb_timeout_tx: 16;
uint32_t reserved_16: 16;
};
uint32_t val;
} ahb_dma_arb_timeout_tx_reg_t;
/** Type of arb_timeout_rx register
* This retister is used to config arbiter time slice for rx dir
*/
typedef union {
struct {
/** arb_timeout_rx : R/W; bitpos: [15:0]; default: 0;
* This register is used to config arbiter time out value
*/
uint32_t arb_timeout_rx: 16;
uint32_t reserved_16: 16;
};
uint32_t val;
} ahb_dma_arb_timeout_rx_reg_t;
/** Type of weight_en_tx register
* This register is used to config arbiter weigh function to on or off for tx dir
*/
typedef union {
struct {
/** weight_en_tx : R/W; bitpos: [0]; default: 0;
* This register is used to config arbiter weight function off/on
*/
uint32_t weight_en_tx: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} ahb_dma_weight_en_tx_reg_t;
/** Type of weight_en_rx register
* This register is used to config arbiter weigh function to on or off for rx dir
*/
typedef union {
struct {
/** weight_en_rx : R/W; bitpos: [0]; default: 0;
* This register is used to config arbiter weight function off/on
*/
uint32_t weight_en_rx: 1;
uint32_t reserved_1: 31;
};
uint32_t val;
} ahb_dma_weight_en_rx_reg_t;
/** Group: Version Registers */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36712768;
/** date : R/W; bitpos: [31:0]; default: 2425376;
* register version.
*/
uint32_t date: 32;
@@ -991,11 +983,12 @@ typedef union {
* L1 Rx FIFO empty signal for Rx channel 0.
*/
uint32_t infifo_empty_chn: 1;
/** infifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
uint32_t reserved_2: 6;
/** infifo_cnt_chn : RO; bitpos: [14:8]; default: 0;
* The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
*/
uint32_t infifo_cnt_chn: 6;
uint32_t reserved_8: 15;
uint32_t infifo_cnt_chn: 7;
uint32_t reserved_15: 8;
/** in_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
* reserved
*/
@@ -1044,7 +1037,7 @@ typedef union {
} ahb_dma_in_state_chn_reg_t;
/** Type of in_suc_eof_des_addr_chn register
* Inlink descriptor address when EOF occurs of Rx channel 0
* Inlink descriptor address when EOF occurs of Rx channel n
*/
typedef union {
struct {
@@ -1058,7 +1051,7 @@ typedef union {
} ahb_dma_in_suc_eof_des_addr_chn_reg_t;
/** Type of in_err_eof_des_addr_chn register
* Inlink descriptor address when errors occur of Rx channel 0
* Inlink descriptor address when errors occur of Rx channel n
*/
typedef union {
struct {
@@ -1072,7 +1065,7 @@ typedef union {
} ahb_dma_in_err_eof_des_addr_chn_reg_t;
/** Type of in_dscr_chn register
* Current inlink descriptor address of Rx channel 0
* Current inlink descriptor address of Rx channel n
*/
typedef union {
struct {
@@ -1085,12 +1078,13 @@ typedef union {
} ahb_dma_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register
* The last inlink descriptor address of Rx channel 0
* The last inlink descriptor address of Rx channel n
*/
typedef union {
struct {
/** inlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
* The address of the last inlink descriptor x-1.
* Represents the address of the current receive descriptor x that has already been
* fetched.
*/
uint32_t inlink_dscr_bf0_chn: 32;
};
@@ -1098,12 +1092,13 @@ typedef union {
} ahb_dma_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register
* The second-to-last inlink descriptor address of Rx channel 0
* The second-to-last inlink descriptor address of Rx channel n
*/
typedef union {
struct {
/** inlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
* The address of the second-to-last inlink descriptor x-2.
* Represents the address of the previous receive descriptor x-1 that has already been
* fetched.
*/
uint32_t inlink_dscr_bf1_chn: 32;
};
@@ -1111,7 +1106,7 @@ typedef union {
} ahb_dma_in_dscr_bf1_chn_reg_t;
/** Type of outfifo_status_chn register
* Transmit FIFO status of Tx channel 0
* Transmit FIFO status of Tx channel n
*/
typedef union {
struct {
@@ -1123,11 +1118,12 @@ typedef union {
* L1 Tx FIFO empty signal for Tx channel 0.
*/
uint32_t outfifo_empty_chn: 1;
/** outfifo_cnt_chn : RO; bitpos: [7:2]; default: 0;
uint32_t reserved_2:6;
/** outfifo_cnt_chn : RO; bitpos: [14:8]; default: 0;
* The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
*/
uint32_t outfifo_cnt_chn: 6;
uint32_t reserved_8: 15;
uint32_t outfifo_cnt_chn: 7;
uint32_t reserved_15: 8;
/** out_remain_under_1b_chn : RO; bitpos: [23]; default: 1;
* reserved
*/
@@ -1150,12 +1146,13 @@ typedef union {
} ahb_dma_outfifo_status_chn_reg_t;
/** Type of out_state_chn register
* Transmit status of Tx channel 0
* Transmit status of Tx channel n
*/
typedef union {
struct {
/** outlink_dscr_addr_chn : RO; bitpos: [17:0]; default: 0;
* This register stores the current outlink descriptor's address.
* Represents the lower 18 bits of the address of the next transmit descriptor to be
* processed.
*/
uint32_t outlink_dscr_addr_chn: 18;
/** out_dscr_state_chn : RO; bitpos: [19:18]; default: 0;
@@ -1172,7 +1169,7 @@ typedef union {
} ahb_dma_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register
* Outlink descriptor address when EOF occurs of Tx channel 0
* Outlink descriptor address when EOF occurs of Tx channel n
*/
typedef union {
struct {
@@ -1186,7 +1183,7 @@ typedef union {
} ahb_dma_out_eof_des_addr_chn_reg_t;
/** Type of out_eof_bfr_des_addr_chn register
* The last outlink descriptor address when EOF occurs of Tx channel 0
* The last outlink descriptor address when EOF occurs of Tx channel n
*/
typedef union {
struct {
@@ -1200,12 +1197,13 @@ typedef union {
} ahb_dma_out_eof_bfr_des_addr_chn_reg_t;
/** Type of out_dscr_chn register
* Current inlink descriptor address of Tx channel 0
* Current inlink descriptor address of Tx channel n
*/
typedef union {
struct {
/** outlink_dscr_chn : RO; bitpos: [31:0]; default: 0;
* The address of the current outlink descriptor y.
* Represents the address of the next transmit descriptor y+1 pointed by the current
* transmit descriptor that has already been fetched.
*/
uint32_t outlink_dscr_chn: 32;
};
@@ -1213,12 +1211,13 @@ typedef union {
} ahb_dma_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register
* The last inlink descriptor address of Tx channel 0
* The last inlink descriptor address of Tx channel n
*/
typedef union {
struct {
/** outlink_dscr_bf0_chn : RO; bitpos: [31:0]; default: 0;
* The address of the last outlink descriptor y-1.
* Represents the address of the current transmit descriptor y that has already been
* fetched.
*/
uint32_t outlink_dscr_bf0_chn: 32;
};
@@ -1226,12 +1225,13 @@ typedef union {
} ahb_dma_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register
* The second-to-last inlink descriptor address of Tx channel 0
* The second-to-last inlink descriptor address of Tx channel n
*/
typedef union {
struct {
/** outlink_dscr_bf1_chn : RO; bitpos: [31:0]; default: 0;
* The address of the second-to-last inlink descriptor x-2.
* Represents the address of the previous transmit descriptor y-1 that has already
* been fetched.
*/
uint32_t outlink_dscr_bf1_chn: 32;
};
@@ -1240,7 +1240,7 @@ typedef union {
/** Group: Priority Registers */
/** Type of in_pri_chn register
* Priority register of Rx channel 0
* Priority register of Rx channel n
*/
typedef union {
struct {
@@ -1274,9 +1274,19 @@ typedef union {
typedef union {
struct {
/** peri_in_sel_chn : R/W; bitpos: [5:0]; default: 63;
* This register is used to select peripheral for Rx channel 0. I3C. 1: Dummy. 2:
* UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
* RMT,11~15: Dummy
* Configures the peripheral connected to RX channel n.
* 0: I3C
* 1: Dummy
* 2: UHCI0
* 3: I2S0
* 4: I2S1
* 5: I2S2
* 6: Dummy
* 7: Dummy
* 8: ADC_DAC
* 9: Dummy
* 10: RMT
* 11~15: Dummy
*/
uint32_t peri_in_sel_chn: 6;
uint32_t reserved_6: 26;
@@ -1285,14 +1295,24 @@ typedef union {
} ahb_dma_in_peri_sel_chn_reg_t;
/** Type of out_peri_sel_chn register
* Peripheral selection of Tx channel 0
* Peripheral selection of Tx channel n
*/
typedef union {
struct {
/** peri_out_sel_chn : R/W; bitpos: [5:0]; default: 63;
* This register is used to select peripheral for Tx channel 0. I3C. 1: Dummy. 2:
* UHCI0. 3: I2S0. 4: I2S1. 5: I2S2. 6: Dummy. 7: Dummy. 8: ADC_DAC. 9: Dummy. 10:
* RMT,11~15: Dummy
* Configures the peripheral connected to TX channel n.
* 0: I3C
* 1: Dummy
* 2: UHCI0
* 3: I2S0
* 4: I2S1
* 5: I2S2
* 6: Dummy
* 7: Dummy
* 8: ADC_DAC
* 9: Dummy
* 10: RMT
* 11~15: Dummy
*/
uint32_t peri_out_sel_chn: 6;
uint32_t reserved_6: 26;
@@ -1300,6 +1320,151 @@ typedef union {
uint32_t val;
} ahb_dma_out_peri_sel_chn_reg_t;
/** Type of arb_timeout register
* TX arbitration timeout configuration register
*/
typedef union {
struct {
/** arb_timeout_num : R/W; bitpos: [15:0]; default: 0;
* Configures the time slot. Measurement unit: AHB bus clock cycle.
*/
uint32_t arb_timeout_num:16;
uint32_t reserved_16:16;
};
uint32_t val;
} ahb_dma_arb_timeout_reg_t;
/** Type of weight_en register
* TX weight arbitration enable register
*/
typedef union {
struct {
/** weight_en : R/W; bitpos: [0]; default: 0;
* Configures whether to enable weight arbitration.
* 0: Disable
* 1: Enable
*/
uint32_t weight_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ahb_dma_weight_en_reg_t;
/** Type of module_clk_en register
* Module clock force on register
*/
typedef union {
struct {
/** ahb_apb_sync_clk_en : R/W; bitpos: [2:0]; default: 7;
* Configures whether to force on ahb_apb_sync 2~0 module clock. For bit n:
* 0 : Not force on ahb_apb_sync n clock
* 1 : Force on ahb_apb_sync n clock
*/
uint32_t ahb_apb_sync_clk_en:3;
/** out_dscr_clk_en : R/W; bitpos: [5:3]; default: 7;
* Configures whether to force on out_dscr 2~0 module clock. For bit n:
* 0 : Not force on out_dscr n clock
* 1 : Force on out_dscr n clock
*/
uint32_t out_dscr_clk_en:3;
/** out_ctrl_clk_en : R/W; bitpos: [8:6]; default: 7;
* Configures whether to force on out_ctrl 2~0 module clock. For bit n:
* 0 : Not force on out_ctrl n clock
* 1 : Force on out_ctrl n clock
*/
uint32_t out_ctrl_clk_en:3;
/** in_dscr_clk_en : R/W; bitpos: [11:9]; default: 7;
* Configures whether to force on in_dscr 2~0 module clock. For bit n:
* 0 : Not force on in_dscr n clock
* 1 : Force on in_dscr n clock
*/
uint32_t in_dscr_clk_en:3;
/** in_ctrl_clk_en : R/W; bitpos: [14:12]; default: 7;
* Configures whether to force on in_ctrl 2~0 module clock. For bit n:
* 0 : Not force on in_ctrl n clock
* 1 : Force on in_ctrl n clock
*/
uint32_t in_ctrl_clk_en:3;
uint32_t reserved_15:12;
/** cmd_arb_clk_en : R/W; bitpos: [27]; default: 0;
* Configures whether to force on cmd_arb module clock.
* 0 : Not force on cmd_arb clock
* 1 : Force on cmd_arb clock
*/
uint32_t cmd_arb_clk_en:1;
/** ahbinf_clk_en : R/W; bitpos: [28]; default: 0;
* Configures whether to force on ahbinf module clock.
* 0 : Not force on ahbinf clock
* 1 : Force on ahbinf clock
*/
uint32_t ahbinf_clk_en:1;
uint32_t reserved_29:3;
};
uint32_t val;
} ahb_dma_module_clk_en_reg_t;
/** Type of ahbinf_resp_err_status0 register
* AHB response error status 0 register
*/
typedef union {
struct {
/** ahbinf_resp_err_addr : RO; bitpos: [31:0]; default: 0;
* Represents the address of the AHB response error.
*/
uint32_t ahbinf_resp_err_addr:32;
};
uint32_t val;
} ahb_dma_ahbinf_resp_err_status0_reg_t;
/** Type of ahbinf_resp_err_status1 register
* AHB response error status 1 register
*/
typedef union {
struct {
/** ahbinf_resp_err_wr : RO; bitpos: [0]; default: 0;
* Represents the AHB response error is write request.
*/
uint32_t ahbinf_resp_err_wr:1;
/** ahbinf_resp_err_id : RO; bitpos: [4:1]; default: 15;
* Represents the AHB response error request id.
*/
uint32_t ahbinf_resp_err_id:4;
/** ahbinf_resp_err_ch_id : RO; bitpos: [7:5]; default: 0;
* Represents the AHB response error request channel id.bit[2]=1:TX channel.
* bit[2]=0:RX channel.
*/
uint32_t ahbinf_resp_err_ch_id:3;
uint32_t reserved_8:24;
};
uint32_t val;
} ahb_dma_ahbinf_resp_err_status1_reg_t;
/** Type of in_done_des_addr_ch0 register
* RX_done Inlink descriptor address of RX channel 0
*/
typedef union {
struct {
/** in_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
* Represents the address of the inlink descriptor when this descriptor is completed .
*/
uint32_t in_done_des_addr_ch0:32;
};
uint32_t val;
} ahb_dma_in_done_des_addr_chn_reg_t;
/** Type of out_done_des_addr_ch0 register
* TX done outlink descriptor address of TX channel 0
*/
typedef union {
struct {
/** out_done_des_addr_ch0 : RO; bitpos: [31:0]; default: 0;
* Represents the address of the outlink descriptor when this descriptor is completed.
*/
uint32_t out_done_des_addr_ch0:32;
};
uint32_t val;
} ahb_dma_out_done_des_addr_chn_reg_t;
typedef struct {
volatile ahb_dma_in_int_raw_chn_reg_t raw;
volatile ahb_dma_in_int_st_chn_reg_t st;
@@ -1355,8 +1520,8 @@ typedef struct {
ahb_dma_rx_crc_en_addr_chn_reg_t crc_en_addr;
ahb_dma_rx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
ahb_dma_rx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
ahb_dma_rx_ch_arb_weight_chn_reg_t ch_arb_weight;
ahb_dma_rx_arb_weight_opt_dis_chn_reg_t arb_weight_opt;
} ahb_dma_in_crc_arb_chn_reg_t;
typedef struct {
@@ -1368,8 +1533,8 @@ typedef struct {
ahb_dma_tx_crc_en_addr_chn_reg_t crc_en_addr;
ahb_dma_tx_crc_data_en_wr_data_chn_reg_t crc_data_en_wr_data;
ahb_dma_tx_crc_data_en_addr_chn_reg_t crc_data_en_addr;
ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
ahb_dma_tx_ch_arb_weight_chn_reg_t ch_arb_weight;
ahb_dma_tx_arb_weight_opt_dis_chn_reg_t arb_weight_opt;
} ahb_dma_out_crc_arb_chn_reg_t;
typedef struct {
@@ -1379,6 +1544,11 @@ typedef struct {
uint32_t reserved_out[11];
} ahb_dma_chn_reg_t;
typedef struct {
volatile ahb_dma_in_done_des_addr_chn_reg_t in;
volatile ahb_dma_out_done_des_addr_chn_reg_t out;
} ahb_dma_done_des_addr_chn_reg_t;
typedef struct {
volatile ahb_dma_in_int_chn_reg_t in_intr[3];
volatile ahb_dma_out_int_chn_reg_t out_intr[3];
@@ -1394,16 +1564,20 @@ typedef struct {
volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[3];
volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
volatile ahb_dma_arb_timeout_rx_reg_t arb_timeout_rx;
volatile ahb_dma_weight_en_tx_reg_t weight_en_tx;
volatile ahb_dma_weight_en_rx_reg_t weight_en_rx;
uint32_t reserved_3cc[4];
volatile ahb_dma_arb_timeout_reg_t arb_timeout;
uint32_t reserved_3e0[8];
volatile ahb_dma_weight_en_reg_t weight_en;
volatile ahb_dma_module_clk_en_reg_t module_clk_en;
volatile ahb_dma_ahbinf_resp_err_status0_reg_t ahbinf_resp_err_status0;
volatile ahb_dma_ahbinf_resp_err_status1_reg_t ahbinf_resp_err_status1;
volatile ahb_dma_done_des_addr_chn_reg_t done_des_addr_chn[3];
} ahb_dma_dev_t;
extern ahb_dma_dev_t AHB_DMA;
#ifndef __cplusplus
_Static_assert(sizeof(ahb_dma_dev_t) == 0x3DC, "Invalid size of ahb_dma_dev_t structure");
_Static_assert(sizeof(ahb_dma_dev_t) == 0x428, "Invalid size of ahb_dma_dev_t structure");
#endif
#ifdef __cplusplus

2021
components/soc/esp32p4/register/hw_ver3/soc/axi_dma_eco5_struct.h
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File diff suppressed because it is too large Load Diff

156
components/soc/esp32p4/register/hw_ver3/soc/axi_dma_struct.h
View File

@@ -10,9 +10,9 @@
extern "C" {
#endif
/** Group: in */
/** Group: Interrupt Registers */
/** Type of in_int_raw_chn register
* Raw status interrupt of channel 0
* Raw status interrupt of channel n
*/
typedef union {
struct {
@@ -81,7 +81,7 @@ typedef union {
} axi_dma_in_int_raw_chn_reg_t;
/** Type of in_int_st_chn register
* Masked interrupt of channel 0
* Masked interrupt of channel n
*/
typedef union {
struct {
@@ -135,7 +135,7 @@ typedef union {
} axi_dma_in_int_st_chn_reg_t;
/** Type of in_int_ena_chn register
* Interrupt enable bits of channel 0
* Interrupt enable bits of channel n
*/
typedef union {
struct {
@@ -189,7 +189,7 @@ typedef union {
} axi_dma_in_int_ena_chn_reg_t;
/** Type of in_int_clr_chn register
* Interrupt clear bits of channel 0
* Interrupt clear bits of channel n
*/
typedef union {
struct {
@@ -243,7 +243,7 @@ typedef union {
} axi_dma_in_int_clr_chn_reg_t;
/** Type of in_conf0_chn register
* Configure 0 register of Rx channel 0
* Configure 0 register of Rx channel n
*/
typedef union {
struct {
@@ -288,7 +288,7 @@ typedef union {
} axi_dma_in_conf0_chn_reg_t;
/** Type of in_conf1_chn register
* Configure 1 register of Rx channel 0
* Configure 1 register of Rx channel n
*/
typedef union {
struct {
@@ -303,7 +303,7 @@ typedef union {
} axi_dma_in_conf1_chn_reg_t;
/** Type of infifo_status_chn register
* Receive FIFO status of Rx channel 0
* Receive FIFO status of Rx channel n
*/
typedef union {
struct {
@@ -401,7 +401,7 @@ typedef union {
} axi_dma_infifo_status_chn_reg_t;
/** Type of in_pop_chn register
* Pop control register of Rx channel 0
* Pop control register of Rx channel n
*/
typedef union {
struct {
@@ -419,7 +419,7 @@ typedef union {
} axi_dma_in_pop_chn_reg_t;
/** Type of in_link1_chn register
* Link descriptor configure and control register of Rx channel 0
* Link descriptor configure and control register of Rx channel n
*/
typedef union {
struct {
@@ -451,7 +451,7 @@ typedef union {
} axi_dma_in_link1_chn_reg_t;
/** Type of in_link2_chn register
* Link descriptor configure and control register of Rx channel 0
* Link descriptor configure and control register of Rx channel n
*/
typedef union {
struct {
@@ -465,7 +465,7 @@ typedef union {
} axi_dma_in_link2_chn_reg_t;
/** Type of in_state_chn register
* Receive status of Rx channel 0
* Receive status of Rx channel n
*/
typedef union {
struct {
@@ -487,7 +487,7 @@ typedef union {
} axi_dma_in_state_chn_reg_t;
/** Type of in_suc_eof_des_addr_chn register
* Inlink descriptor address when EOF occurs of Rx channel 0
* Inlink descriptor address when EOF occurs of Rx channel n
*/
typedef union {
struct {
@@ -501,7 +501,7 @@ typedef union {
} axi_dma_in_suc_eof_des_addr_chn_reg_t;
/** Type of in_err_eof_des_addr_chn register
* Inlink descriptor address when errors occur of Rx channel 0
* Inlink descriptor address when errors occur of Rx channel n
*/
typedef union {
struct {
@@ -515,7 +515,7 @@ typedef union {
} axi_dma_in_err_eof_des_addr_chn_reg_t;
/** Type of in_dscr_chn register
* Current inlink descriptor address of Rx channel 0
* Current inlink descriptor address of Rx channel n
*/
typedef union {
struct {
@@ -528,7 +528,7 @@ typedef union {
} axi_dma_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register
* The last inlink descriptor address of Rx channel 0
* The last inlink descriptor address of Rx channel n
*/
typedef union {
struct {
@@ -541,7 +541,7 @@ typedef union {
} axi_dma_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register
* The second-to-last inlink descriptor address of Rx channel 0
* The second-to-last inlink descriptor address of Rx channel n
*/
typedef union {
struct {
@@ -554,7 +554,7 @@ typedef union {
} axi_dma_in_dscr_bf1_chn_reg_t;
/** Type of in_pri_chn register
* Priority register of Rx channel 0
* Priority register of Rx channel n
*/
typedef union {
struct {
@@ -576,7 +576,7 @@ typedef union {
} axi_dma_in_pri_chn_reg_t;
/** Type of in_peri_sel_chn register
* Peripheral selection of Rx channel 0
* Peripheral selection of Rx channel n
*/
typedef union {
struct {
@@ -591,7 +591,7 @@ typedef union {
} axi_dma_in_peri_sel_chn_reg_t;
/** Type of in_crc_init_data_chn register
* This register is used to config ch0 crc initial data(max 32 bit)
* This register is used to config chn crc initial data(max 32 bit)
*/
typedef union {
struct {
@@ -604,7 +604,7 @@ typedef union {
} axi_dma_in_crc_init_data_chn_reg_t;
/** Type of rx_crc_width_chn register
* This register is used to config rx ch0 crc result width,2'b00 mean crc_width
* This register is used to config rx chn crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -624,7 +624,7 @@ typedef union {
} axi_dma_rx_crc_width_chn_reg_t;
/** Type of in_crc_clear_chn register
* This register is used to clear ch0 crc result
* This register is used to clear chn crc result
*/
typedef union {
struct {
@@ -638,7 +638,7 @@ typedef union {
} axi_dma_in_crc_clear_chn_reg_t;
/** Type of in_crc_final_result_chn register
* This register is used to store ch0 crc result
* This register is used to store chn crc result
*/
typedef union {
struct {
@@ -651,7 +651,7 @@ typedef union {
} axi_dma_in_crc_final_result_chn_reg_t;
/** Type of rx_crc_en_wr_data_chn register
* This resister is used to config ch0 crc en for every bit
* This resister is used to config chn crc en for every bit
*/
typedef union {
struct {
@@ -664,7 +664,7 @@ typedef union {
} axi_dma_rx_crc_en_wr_data_chn_reg_t;
/** Type of rx_crc_en_addr_chn register
* This register is used to config ch0 crc en addr
* This register is used to config chn crc en addr
*/
typedef union {
struct {
@@ -705,7 +705,7 @@ typedef union {
/** Group: out */
/** Type of out_int_raw_chn register
* Raw status interrupt of channel0
* Raw status interrupt of channeln
*/
typedef union {
struct {
@@ -761,13 +761,18 @@ typedef union {
* underflow.
*/
uint32_t outfifo_l3_udf_chn_int_raw: 1;
uint32_t reserved_10: 22;
/** out_link_switch_chn_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when the dma switch to new link for Tx
* channel0.
*/
uint32_t out_link_switch_chn_int_raw: 1;
uint32_t reserved_11: 21;
};
uint32_t val;
} axi_dma_out_int_raw_chn_reg_t;
/** Type of out_int_st_chn register
* Masked interrupt of channel0
* Masked interrupt of channeln
*/
typedef union {
struct {
@@ -811,13 +816,17 @@ typedef union {
* The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
*/
uint32_t outfifo_l3_udf_chn_int_st: 1;
uint32_t reserved_10: 22;
/** out_link_switch_chn_int_st : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the OUT_LINK_SWITCH_CH_INT interrupt.
*/
uint32_t out_link_switch_chn_int_st: 1;
uint32_t reserved_11: 21;
};
uint32_t val;
} axi_dma_out_int_st_chn_reg_t;
/** Type of out_int_ena_chn register
* Interrupt enable bits of channel0
* Interrupt enable bits of channeln
*/
typedef union {
struct {
@@ -861,13 +870,17 @@ typedef union {
* The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.
*/
uint32_t outfifo_l3_udf_chn_int_ena: 1;
uint32_t reserved_10: 22;
/** out_link_switch_chn_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the OUT_LINK_SWITCH_CH_INT interrupt.
*/
uint32_t out_link_switch_chn_int_ena: 1;
uint32_t reserved_11: 21;
};
uint32_t val;
} axi_dma_out_int_ena_chn_reg_t;
/** Type of out_int_clr_chn register
* Interrupt clear bits of channel0
* Interrupt clear bits of channeln
*/
typedef union {
struct {
@@ -911,13 +924,17 @@ typedef union {
* Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.
*/
uint32_t outfifo_l3_udf_chn_int_clr: 1;
uint32_t reserved_10: 22;
/** out_link_switch_chn_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear the OUT_LINK_SWITCH_CH_INT interrupt.
*/
uint32_t out_link_switch_chn_int_clr: 1;
uint32_t reserved_11: 21;
};
uint32_t val;
} axi_dma_out_int_clr_chn_reg_t;
/** Type of out_conf0_chn register
* Configure 0 register of Tx channelN
* Configure 0 register of Tx channeln
*/
typedef union {
struct {
@@ -967,7 +984,7 @@ typedef union {
} axi_dma_out_conf0_chn_reg_t;
/** Type of out_conf1_chn register
* Configure 1 register of Tx channel0
* Configure 1 register of Tx channeln
*/
typedef union {
struct {
@@ -982,7 +999,7 @@ typedef union {
} axi_dma_out_conf1_chn_reg_t;
/** Type of outfifo_status_chn register
* Transmit FIFO status of Tx channel0
* Transmit FIFO status of Tx channeln
*/
typedef union {
struct {
@@ -1077,7 +1094,7 @@ typedef union {
} axi_dma_outfifo_status_chn_reg_t;
/** Type of out_push_chn register
* Push control register of Tx channel0
* Push control register of Tx channeln
*/
typedef union {
struct {
@@ -1095,7 +1112,7 @@ typedef union {
} axi_dma_out_push_chn_reg_t;
/** Type of out_link1_chn register
* Link descriptor configure and control register of Tx channel0
* Link descriptor configure and control register of Tx channeln
*/
typedef union {
struct {
@@ -1122,7 +1139,7 @@ typedef union {
} axi_dma_out_link1_chn_reg_t;
/** Type of out_link2_chn register
* Link descriptor configure and control register of Tx channel0
* Link descriptor configure and control register of Tx channeln
*/
typedef union {
struct {
@@ -1136,7 +1153,7 @@ typedef union {
} axi_dma_out_link2_chn_reg_t;
/** Type of out_state_chn register
* Transmit status of Tx channel0
* Transmit status of Tx channeln
*/
typedef union {
struct {
@@ -1158,7 +1175,7 @@ typedef union {
} axi_dma_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register
* Outlink descriptor address when EOF occurs of Tx channel0
* Outlink descriptor address when EOF occurs of Tx channeln
*/
typedef union {
struct {
@@ -1172,7 +1189,7 @@ typedef union {
} axi_dma_out_eof_des_addr_chn_reg_t;
/** Type of out_eof_bfr_des_addr_chn register
* The last outlink descriptor address when EOF occurs of Tx channel0
* The last outlink descriptor address when EOF occurs of Tx channeln
*/
typedef union {
struct {
@@ -1186,7 +1203,7 @@ typedef union {
} axi_dma_out_eof_bfr_des_addr_chn_reg_t;
/** Type of out_dscr_chn register
* Current outlink descriptor address of Tx channel0
* Current outlink descriptor address of Tx channeln
*/
typedef union {
struct {
@@ -1199,7 +1216,7 @@ typedef union {
} axi_dma_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register
* The last outlink descriptor address of Tx channel0
* The last outlink descriptor address of Tx channeln
*/
typedef union {
struct {
@@ -1212,7 +1229,7 @@ typedef union {
} axi_dma_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register
* The second-to-last outlink descriptor address of Tx channel0
* The second-to-last outlink descriptor address of Tx channeln
*/
typedef union {
struct {
@@ -1225,7 +1242,7 @@ typedef union {
} axi_dma_out_dscr_bf1_chn_reg_t;
/** Type of out_pri_chn register
* Priority register of Tx channel0.
* Priority register of Tx channeln.
*/
typedef union {
struct {
@@ -1247,7 +1264,7 @@ typedef union {
} axi_dma_out_pri_chn_reg_t;
/** Type of out_peri_sel_chn register
* Peripheral selection of Tx channel0
* Peripheral selection of Tx channeln
*/
typedef union {
struct {
@@ -1262,7 +1279,7 @@ typedef union {
} axi_dma_out_peri_sel_chn_reg_t;
/** Type of out_crc_init_data_chn register
* This register is used to config ch0 crc initial data(max 32 bit)
* This register is used to config chn crc initial data(max 32 bit)
*/
typedef union {
struct {
@@ -1275,7 +1292,7 @@ typedef union {
} axi_dma_out_crc_init_data_chn_reg_t;
/** Type of tx_crc_width_chn register
* This register is used to config tx ch0 crc result width,2'b00 mean crc_width
* This register is used to config tx chn crc result width,2'b00 mean crc_width
* <=8bit,2'b01 8<crc_width<=16 ,2'b10 mean 16<crc_width <=24,2'b11 mean
* 24<crc_width<=32
*/
@@ -1295,7 +1312,7 @@ typedef union {
} axi_dma_tx_crc_width_chn_reg_t;
/** Type of out_crc_clear_chn register
* This register is used to clear ch0 crc result
* This register is used to clear chn crc result
*/
typedef union {
struct {
@@ -1309,7 +1326,7 @@ typedef union {
} axi_dma_out_crc_clear_chn_reg_t;
/** Type of out_crc_final_result_chn register
* This register is used to store ch0 crc result
* This register is used to store chn crc result
*/
typedef union {
struct {
@@ -1322,7 +1339,7 @@ typedef union {
} axi_dma_out_crc_final_result_chn_reg_t;
/** Type of tx_crc_en_wr_data_chn register
* This resister is used to config ch0 crc en for every bit
* This resister is used to config chn crc en for every bit
*/
typedef union {
struct {
@@ -1335,7 +1352,7 @@ typedef union {
} axi_dma_tx_crc_en_wr_data_chn_reg_t;
/** Type of tx_crc_en_addr_chn register
* This register is used to config ch0 crc en addr
* This register is used to config chn crc en addr
*/
typedef union {
struct {
@@ -1503,7 +1520,7 @@ typedef union {
} axi_dma_extr_mem_end_addr_reg_t;
/** Type of in_reset_avail_chn register
* The rx channel 0 reset valid_flag register.
* The rx channel n reset valid_flag register.
*/
typedef union {
struct {
@@ -1517,7 +1534,7 @@ typedef union {
} axi_dma_in_reset_avail_chn_reg_t;
/** Type of out_reset_avail_chn register
* The tx channel 0 reset valid_flag register.
* The tx channel n reset valid_flag register.
*/
typedef union {
struct {
@@ -1633,7 +1650,7 @@ typedef union {
} axi_dma_rresp_cnt_reg_t;
/** Type of infifo_status1_chn register
* Receive FIFO status of Rx channel 0
* Receive FIFO status of Rx channel n
*/
typedef union {
struct {
@@ -1651,7 +1668,7 @@ typedef union {
} axi_dma_infifo_status1_chn_reg_t;
/** Type of outfifo_status1_chn register
* Receive FIFO status of Tx channel 0
* Receive FIFO status of Tx channel n
*/
typedef union {
struct {
@@ -1668,6 +1685,28 @@ typedef union {
uint32_t val;
} axi_dma_outfifo_status1_chn_reg_t;
/** Type of link_switch_state register
* Version control register
*/
typedef union {
struct {
/** link_switch_state_ch0 : R/W; bitpos: [0]; default: 0;
* The register that confirm ch dscr switch success
*/
uint32_t link_switch_state_ch0: 1;
/** link_switch_state_ch1 : R/W; bitpos: [1]; default: 0;
* The register that confirm ch dscr switch success
*/
uint32_t link_switch_state_ch1: 1;
/** link_switch_state_ch2 : R/W; bitpos: [2]; default: 0;
* The register that confirm ch dscr switch success
*/
uint32_t link_switch_state_ch2: 1;
uint32_t reserved_3: 29;
};
uint32_t val;
} axi_dma_link_switch_state_reg_t;
/** Group: Version Registers */
/** Type of date register
* Version control register
@@ -1786,12 +1825,13 @@ typedef struct {
volatile axi_dma_infifo_status1_chn_reg_t infifo_status1_chn[3];
volatile axi_dma_outfifo_status1_chn_reg_t outfifo_status1_chn[3];
volatile axi_dma_date_reg_t date;
volatile axi_dma_link_switch_state_reg_t link_switch_state;
} axi_dma_dev_t;
extern axi_dma_dev_t AXI_DMA;
#ifndef __cplusplus
_Static_assert(sizeof(axi_dma_dev_t) == 0x2dc, "Invalid size of axi_dma_dev_t structure");
_Static_assert(sizeof(axi_dma_dev_t) == 0x2e0, "Invalid size of axi_dma_dev_t structure");
#endif
#ifdef __cplusplus