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Merge branch 'feat/support_esp32h4_dfs' into 'master'

Browse Source 
Support dfs and light & deep sleep  in esp32h4 beta5

Closes PM-446

See merge request espressif/esp-idf!40595
This commit is contained in:
He Binglin
2025-08-19 10:50:48 +08:00
parent 5276a56911 8f8a97787d
commit 316d744845
18 changed files with 181 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
components/esp_hw_support/CMakeLists.txt
View File

@@ -185,13 +185,6 @@ if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/include/soc/${target}")
)
endif()
if(CONFIG_IDF_TARGET_ESP32H4)
list(REMOVE_ITEM srcs
"sleep_modes.c"
"sleep_gpio.c" # TODO: [ESP32H4] IDF-12279, IDF-12281
)
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include_dirs}
PRIV_INCLUDE_DIRS port/include include/esp_private

2
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
View File

@@ -41,7 +41,7 @@ extern "C" {
#define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 1
#define PMU_LP_DBIAS_SLEEP_0V7_DEFAULT 6
#define PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US 0
#define PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US 480
// The current value of this depends on the restoration time overhead of the longest chain in regdma
#define PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US 390

8
components/esp_hw_support/port/esp32h21/Kconfig.rtc
View File

@@ -1,10 +1,10 @@
choice RTC_CLK_SRC
prompt "RTC clock source"
default RTC_CLK_SRC_INT_RC_D4
default RTC_CLK_SRC_INT_RC
help
Choose which clock is used as RTC clock source.
config RTC_CLK_SRC_INT_RC_D4
config RTC_CLK_SRC_INT_RC
bool "Internal 600 kHz RC oscillator, divide by 4"
config RTC_CLK_SRC_EXT_CRYS
bool "External 32 kHz crystal"
@@ -17,9 +17,9 @@ endchoice
config RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
default 1024 if RTC_CLK_SRC_INT_RC_D4
default 1024 if RTC_CLK_SRC_INT_RC
range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
range 0 32766 if RTC_CLK_SRC_INT_RC_D4
range 0 32766 if RTC_CLK_SRC_INT_RC
help
When the startup code initializes RTC_SLOW_CLK, it can perform
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL

8
components/esp_hw_support/port/esp32h4/Kconfig.rtc
View File

@@ -1,10 +1,10 @@
choice RTC_CLK_SRC
prompt "RTC clock source"
default RTC_CLK_SRC_INT_RC_D4
default RTC_CLK_SRC_INT_RC
help
Choose which clock is used as RTC clock source.
config RTC_CLK_SRC_INT_RC_D4
config RTC_CLK_SRC_INT_RC
bool "Internal 600kHz RC oscillator, divide by 4"
config RTC_CLK_SRC_EXT_CRYS
bool "External 32kHz crystal"
@@ -17,9 +17,9 @@ endchoice
config RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
default 1024 if RTC_CLK_SRC_INT_RC_D4
default 1024 if RTC_CLK_SRC_INT_RC
range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
range 0 32766 if RTC_CLK_SRC_INT_RC_D4
range 0 32766 if RTC_CLK_SRC_INT_RC
help
When the startup code initializes RTC_SLOW_CLK, it can perform
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL

17
components/esp_hw_support/port/esp32h4/pmu_init.c
View File

@@ -56,6 +56,7 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys
pmu_ll_hp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
pmu_ll_hp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, mode, power->xtal.xpd_xtal);
pmu_ll_hp_set_xtalx2_xpd (ctx->hal->dev, mode, power->xtal.xpd_xtalx2);
/* Default configuration of hp-system clock in active, modem and sleep modes */
pmu_ll_hp_set_icg_func (ctx->hal->dev, mode, clock->icg_func);
@@ -114,6 +115,9 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys
pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true);
pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP);
/* set dcdc ccm mode software enable */
pmu_ll_set_dcdc_ccm_sw_en(ctx->hal->dev, true);
}
void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_system_param_t *param)
@@ -126,7 +130,7 @@ void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_sys
pmu_ll_lp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
pmu_ll_lp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, power->xtal.xpd_xtal);
pmu_ll_lp_set_xtalx2_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, power->xtal.xpd_xtalx2);
/* Default configuration of lp-system analog sub-system in active and
* sleep modes */
if (mode == PMU_MODE_LP_SLEEP) {
@@ -169,6 +173,7 @@ static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
}
/* Isolate all memory banks while sleeping, avoid memory leakage current */
pmu_ll_hp_set_memory_no_isolate (ctx->hal->dev, 0);
pmu_ll_hp_set_memory_power_up (ctx->hal->dev, 0);
pmu_ll_lp_set_power_force_power_up (ctx->hal->dev, false);
pmu_ll_lp_set_power_force_no_reset (ctx->hal->dev, false);
@@ -230,20 +235,16 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
void pmu_init(void)
{
/* No peripheral reg i2c power up required on the target */
pmu_hp_system_init_default(PMU_instance());
pmu_lp_system_init_default(PMU_instance());
pmu_power_domain_force_default(PMU_instance());
// default ccm mode
REG_SET_FIELD(PMU_DCM_CTRL_REG, PMU_DCDC_CCM_SW_EN, 1);
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCDC_CCM_ENB, 0);
#if !CONFIG_IDF_ENV_FPGA
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_DREG0, 24);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_PCUR_LIMIT0, 4);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_PCUR_LIMIT0, 1);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_DREG0, 24);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_PCUR_LIMIT0, 2);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_XPD_TRX, 0);
#endif

50
components/esp_hw_support/port/esp32h4/pmu_param.c
View File

@@ -66,17 +66,17 @@ static __attribute__((unused)) const char *TAG = "pmu_param";
.xpd_bbpll = 1 \
}, \
.xtal = { \
.xpd_xtalx2 = 1, \
.xpd_xtalx2 = 0, \
.xpd_xtal = 1 \
} \
}
#define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.vdd_flash_mode = 1, \
.vdd_flash_mode = 3, \
.mem_dslp = 0, \
.mem_pd_en = 0, \
.wifi_pd_en = 1, \
.wifi_pd_en = 0, \
.peri_pd_en = 0, \
.cpu_pd_en = 0, \
.aon_pd_en = 0, \
@@ -208,12 +208,12 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
.bias = { \
.dcdc_ccm_enb = 1, \
.dcdc_ccm_enb = 0, \
.dcdc_clear_rdy = 0, \
.dig_reg_dpcur_bias = 3, \
.dig_reg_dsfmos = 6, \
.dcm_vset = 23, \
.dcm_mode = 0, \
.dcm_mode = 3, \
.dcm_vset = 24, \
.xpd_trx = 1, \
.xpd_bias = 1, \
.discnnt_dig_rtc = 0, \
@@ -234,7 +234,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dbias = HP_CALI_DBIAS_DEFAULT \
}, \
.regulator1 = { \
.drv_b = 0x0 \
.drv_b = 2 \
} \
}
@@ -244,8 +244,8 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dcdc_clear_rdy = 0, \
.dig_reg_dpcur_bias = 1, \
.dig_reg_dsfmos = 4, \
.dcm_vset = 23, \
.dcm_mode = 0, \
.dcm_mode = 3, \
.dcm_vset = 24, \
.xpd_trx = 1, \
.xpd_bias = 0, \
.discnnt_dig_rtc = 0, \
@@ -262,23 +262,23 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dbias = HP_CALI_DBIAS_DEFAULT \
}, \
.regulator1 = { \
.drv_b = 0x0 \
.drv_b = 2 \
} \
}
#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
.bias = { \
.dcdc_ccm_enb = 0, \
.dcdc_ccm_enb = 1, \
.dcdc_clear_rdy = 0, \
.dig_reg_dpcur_bias = 1, \
.dig_reg_dsfmos = 4, \
.dcm_vset = 23, \
.dcm_mode = 0, \
.dcm_mode = 3, \
.dcm_vset = 24, \
.xpd_trx = 0, \
.xpd_bias = 0, \
.discnnt_dig_rtc = 0, \
.pd_cur = 0, \
.bias_sleep = 0 \
.pd_cur = 1, \
.bias_sleep = 1 \
}, \
.regulator0 = { \
.power_det_bypass = 0, \
@@ -287,10 +287,10 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.xpd = 1, \
.slp_mem_dbias = 0, \
.slp_logic_dbias = 0, \
.dbias = 1 \
.dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 0x0 \
.drv_b = 7 \
} \
}
@@ -384,10 +384,10 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.vdd_io_mode = 0, \
.vdd_io_mode = 3, \
.bod_source_sel = 0, \
.vddbat_mode = 0, \
.mem_dslp = 1, \
.mem_dslp = 0, \
.peri_pd_en = 0, \
}, \
.clk_power = { \
@@ -421,18 +421,18 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
.dbias = LP_CALI_DBIAS_DEFAULT \
}, \
.regulator1 = { \
.drv_b = 0x0 \
.drv_b = 2 \
} \
}
#define PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
.bias = { \
.dcdc_ccm_enb = 0, \
.dcdc_ccm_enb = 1, \
.dcdc_clear_rdy = 0, \
.dig_reg_dpcur_bias = 1, \
.dig_reg_dsfmos = 4, \
.dcm_vset = 23, \
.dcm_mode = 0, \
.dcm_mode = 3, \
.dcm_vset = 0, \
.xpd_bias = 0, \
.discnnt_dig_rtc = 0, \
.pd_cur = 1, \
@@ -442,10 +442,10 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
.slp_xpd = 0, \
.xpd = 1, \
.slp_dbias = 0, \
.dbias = 12 \
.dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 0x0 \
.drv_b = 7 \
} \
}

8
components/esp_hw_support/port/esp32h4/pmu_sleep.c
View File

@@ -68,6 +68,8 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \
+ lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us + mc->lp.power_up_wait_time_us;
mc->hp.regdma_s2a_work_time_us = (sleep_flags & PMU_SLEEP_PD_TOP) ? PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US : PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US;
/* HP core hardware wait time, microsecond */
const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
const int hp_control_wait_time_us = mc->hp.isolate_wait_time_us + mc->hp.reset_wait_time_us;
@@ -138,6 +140,9 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
if (dslp) {
power_default.hp_sys.memory.mem0_mask = 0;
power_default.hp_sys.memory.mem1_mask = 0;
power_default.hp_sys.memory.mem2_mask = 0;
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
config->analog = analog_default;
@@ -178,6 +183,8 @@ static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_confi
pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val);
pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val);
pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal);
pmu_ll_hp_set_memory_power_on_mask(ctx->hal->dev, power->hp_sys.memory.mem0_mask, power->hp_sys.memory.mem1_mask, power->hp_sys.memory.mem2_mask);
}
static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
@@ -188,6 +195,7 @@ static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_c
static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
{
assert(ctx->hal);
// Core power supply (include DCDC, HP LDO, LP LDO) configuration
pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur);
pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep);
pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);

33
components/esp_hw_support/port/esp32h4/private_include/pmu_param.h
View File

@@ -40,6 +40,10 @@ extern "C" {
#define PMU_HP_DBIAS_LIGHTSLEEP_0V6_DEFAULT 1
#define PMU_LP_DBIAS_LIGHTSLEEP_0V7_DEFAULT 12
#define PMU_REGDMA_S2A_WORK_TIME_PD_TOP_US 0
// The current value of this depends on the restoration time overhead of the longest chain in regdma
#define PMU_REGDMA_S2A_WORK_TIME_PU_TOP_US 390
// FOR DEEPSLEEP
#define PMU_DBG_HP_DEEPSLEEP 0
#define PMU_HP_XPD_DEEPSLEEP 0
@@ -134,6 +138,15 @@ typedef union {
uint32_t xpd_xtalx2 : 1;
uint32_t xpd_xtal : 1;
};
struct {
uint32_t mem2_pd_mask: 5;
uint32_t mem1_pd_mask: 5;
uint32_t mem0_pd_mask: 5;
uint32_t reserved5 : 2;
uint32_t mem2_mask : 5;
uint32_t mem1_mask : 5;
uint32_t mem0_mask : 5;
};
uint32_t val;
} pmu_hp_power_t;
@@ -277,6 +290,7 @@ typedef struct {
pmu_hp_power_t dig_power;
pmu_hp_power_t clk_power;
pmu_hp_power_t xtal;
pmu_hp_power_t memory;
} hp_sys;
struct {
pmu_lp_power_t dig_power;
@@ -288,7 +302,7 @@ typedef struct {
#define PMU_SLEEP_POWER_CONFIG_DEFAULT(pd_flags) { \
.hp_sys = { \
.dig_power = { \
.vdd_flash_mode = 0, \
.vdd_flash_mode = ((pd_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 3, \
.wifi_pd_en = ((pd_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0, \
.cpu_pd_en = ((pd_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0, \
.aon_pd_en = ((pd_flags) & PMU_SLEEP_PD_HP_AON) ? 1 : 0, \
@@ -306,6 +320,11 @@ typedef struct {
.xtal = { \
.xpd_xtalx2 = 0, \
.xpd_xtal = ((pd_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
}, \
.memory = { \
.mem0_mask = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.mem1_mask = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
.mem2_mask = ((pd_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0 \
} \
}, \
.lp_sys[PMU_MODE_LP_ACTIVE] = { \
@@ -325,11 +344,11 @@ typedef struct {
}, \
.lp_sys[PMU_MODE_LP_SLEEP] = { \
.dig_power = { \
.vdd_io_mode = 0, \
.vdd_io_mode = 3, \
.bod_source_sel = 0, \
.vddbat_mode = 0, \
.peri_pd_en = ((pd_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0,\
.mem_dslp = 1 \
.mem_dslp = 0 \
}, \
.clk_power = { \
.xpd_lppll = 0, \
@@ -508,8 +527,8 @@ typedef struct pmu_sleep_machine_constant {
.lp = { \
.min_slp_time_us = 450, \
.wakeup_wait_cycle = 4, \
.analog_wait_time_us = 154, \
.xtal_wait_stable_time_us = 250, \
.analog_wait_time_us = 400, \
.xtal_wait_stable_time_us = 2000, \
.clk_switch_cycle = 1, \
.clk_power_on_wait_cycle = 1, \
.isolate_wait_time_us = 1, \
@@ -521,7 +540,7 @@ typedef struct pmu_sleep_machine_constant {
.min_slp_time_us = 450, \
.clock_domain_sync_time_us = 150, \
.system_dfs_up_work_time_us = 124, \
.analog_wait_time_us = 154, \
.analog_wait_time_us = 800, \
.isolate_wait_time_us = 1, \
.reset_wait_time_us = 1, \
.power_supply_wait_time_us = 2, \
@@ -532,7 +551,7 @@ typedef struct pmu_sleep_machine_constant {
.regdma_a2s_work_time_us = 382, \
.regdma_rf_on_work_time_us = 70, \
.regdma_rf_off_work_time_us = 23, \
.xtal_wait_stable_time_us = 250, \
.xtal_wait_stable_time_us = 2000, \
.pll_wait_stable_time_us = 1 \
} \
}

4
components/esp_hw_support/test_apps/wakeup_tests/README.md
View File

@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |

52
components/hal/esp32h4/include/hal/pmu_ll.h
View File

@@ -99,6 +99,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode,
hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_xtalx2_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtalx2)
{
hw->hp_sys[mode].xtal.xpd_xtalx2 = xpd_xtalx2;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
{
hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
@@ -339,6 +344,12 @@ FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode,
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
}
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtalx2_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtalx2)
{
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
hw->lp_sys[mode].xtal.xpd_xtalx2 = xpd_xtalx2;
}
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
{
hw->lp_sys[mode].dig_power.val = flag;
@@ -560,6 +571,20 @@ FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu
hw->power.mem_cntl.force_hp_mem_pu = fpu;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_on_mask(pmu_dev_t *hw, uint32_t mem0_mask, uint32_t mem1_mask, uint32_t mem2_mask)
{
hw->power.mem_mask.mem0_mask = mem0_mask;
hw->power.mem_mask.mem1_mask = mem1_mask;
hw->power.mem_mask.mem2_mask = mem2_mask;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_off_mask(pmu_dev_t *hw, uint32_t mem0_pd_mask, uint32_t mem1_pd_mask, uint32_t mem2_pd_mask)
{
hw->power.mem_mask.mem0_pd_mask = mem0_pd_mask;
hw->power.mem_mask.mem1_pd_mask = mem1_pd_mask;
hw->power.mem_mask.mem2_pd_mask = mem2_pd_mask;
}
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
{
hw->wakeup.cntl0.sleep_req = 1;
@@ -786,11 +811,38 @@ FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *
return hw->power.wait_timer0.hp_powerup_timer;
}
FORCE_INLINE_ATTR void pmu_ll_hp_vddspi_ldo_set_sw_adjust(bool sw_enable, uint32_t vdd_flash_mode)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.flash_ldo[vdd_flash_mode], sw_en_xpd, sw_enable);
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.flash_ldo[vdd_flash_mode], sw_en_power_adjust, sw_enable);
}
FORCE_INLINE_ATTR void pmu_ll_hp_vddspi_ldo_set_sw_adjust_value(uint32_t value, uint32_t vdd_flash_mode)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.flash_ldo[vdd_flash_mode], power_adjust, value);
}
FORCE_INLINE_ATTR void pmu_ll_hp_vddio_ldo_set_sw_adjust(bool sw_enable)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.io_ldo, sw_en_xpd, sw_enable);
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.io_ldo, sw_en_power_adjust, sw_enable);
}
FORCE_INLINE_ATTR void pmu_ll_hp_vddio_ldo_set_sw_adjust_value(uint32_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(PMU.power.io_ldo, power_adjust, value);
}
FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
{
return hw->clk_state0.sysclk_slp_sel_state;
}
FORCE_INLINE_ATTR void pmu_ll_set_dcdc_ccm_sw_en(pmu_dev_t *hw, bool en)
{
hw->dcm_ctrl.dcdc_ccm_sw_en = en;
}
#ifdef __cplusplus
}
#endif

18
components/hal/esp32h4/include/hal/uart_ll.h
View File

@@ -779,15 +779,15 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
// case UART_WK_MODE_FIFO_THRESH: // TODO: [ESP32H4] PM-457
// hw->sleep_conf2.wk_mode_sel = 1;
// break;
// case UART_WK_MODE_START_BIT:
// hw->sleep_conf2.wk_mode_sel = 2;
// break;
// case UART_WK_MODE_CHAR_SEQ:
// hw->sleep_conf2.wk_mode_sel = 3;
// break;
default:
abort();
break;

56
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
View File

@@ -67,10 +67,6 @@ config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_PMU_SUPPORTED
bool
default y
@@ -103,6 +99,22 @@ config SOC_SPIRAM_SUPPORTED
bool
default y
config SOC_LIGHT_SLEEP_SUPPORTED
bool
default y
config SOC_DEEP_SLEEP_SUPPORTED
bool
default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_PM_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_32M
bool
default y
@@ -791,30 +803,10 @@ config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_UART_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN
int
default 5
config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE
bool
default y
config SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE
bool
default y
config SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE
bool
default y
config SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE
bool
default y
config SOC_SPIRAM_XIP_SUPPORTED
bool
default y
@@ -839,22 +831,10 @@ config SOC_PHY_DIG_REGS_MEM_SIZE
int
default 21
config SOC_PM_SUPPORT_BT_WAKEUP
bool
default y
config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
bool
default y
config SOC_PM_SUPPORT_TOUCH_WAKEUP
bool
default y
config SOC_PM_SUPPORT_MODEM_PD
bool
default y
config SOC_PM_SUPPORT_XTAL32K_PD
bool
default y
@@ -879,10 +859,6 @@ config SOC_PM_SUPPORT_MAC_BB_PD
bool
default y
config SOC_PM_SUPPORT_RTC_PERIPH_PD
bool
default y
config SOC_PM_PAU_LINK_NUM
int
default 4

24
components/soc/esp32h4/include/soc/soc_caps.h
View File

@@ -70,7 +70,6 @@
// #define SOC_ECC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12264
#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12261
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12262
#define SOC_MODEM_CLOCK_SUPPORTED 1
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32H4] IDF-12295
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256
@@ -87,7 +86,10 @@
#define SOC_WDT_SUPPORTED 1
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32H4] IDF-12388
#define SOC_SPIRAM_SUPPORTED 1
#define SOC_LIGHT_SLEEP_SUPPORTED 1
#define SOC_DEEP_SLEEP_SUPPORTED 1
#define SOC_MODEM_CLOCK_SUPPORTED 1
#define SOC_PM_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_32M 1
#define SOC_XTAL_CLOCK_PATH_DEPENDS_ON_TOP_DOMAIN 1
@@ -499,13 +501,13 @@
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
// #define SOC_UART_SUPPORT_SLEEP_RETENTION (1) /*!< Support back up registers before sleep */
#define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
// #define SOC_UART_WAKEUP_CHARS_SEQ_MAX_LEN 5
#define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1)
// #define SOC_UART_WAKEUP_SUPPORT_FIFO_THRESH_MODE (1) // TODO: [ESP32H4] PM-457
// #define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1)
// #define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1)
/*-------------------------- SPIRAM CAPS -------------------------------------*/
#define SOC_SPIRAM_XIP_SUPPORTED 1
@@ -523,12 +525,12 @@
// TODO: IDF-12286 (inherit from verify code, need check)
/*-------------------------- Power Management CAPS ----------------------------*/
#define SOC_PM_SUPPORT_BT_WAKEUP (1)
// #define SOC_PM_SUPPORT_BT_WAKEUP (1)
// #define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
// #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
#define SOC_PM_SUPPORT_TOUCH_WAKEUP (1)
// #define SOC_PM_SUPPORT_CPU_PD (1)
#define SOC_PM_SUPPORT_MODEM_PD (1)
// #define SOC_PM_SUPPORT_MODEM_PD (1)
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
#define SOC_PM_SUPPORT_RC32K_PD (1)
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
@@ -536,7 +538,7 @@
// #define SOC_PM_SUPPORT_TOP_PD (1)
#define SOC_PM_SUPPORT_HP_AON_PD (1)
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
// #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) // TODO： [ESP32H4] PM-484
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
// /* macro redefine for pass esp_wifi headers md5sum check */

4
examples/system/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
# System Examples

4
examples/system/deep_sleep/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
# Deep Sleep Example

2
examples/system/deep_sleep/sdkconfig.ci.basic
View File

@@ -2,8 +2,6 @@
CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
CONFIG_EXAMPLE_EXT1_WAKEUP=n
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_RESERVE_MEM=512
CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y

2
examples/system/deep_sleep/sdkconfig.defaults
View File

@@ -1,5 +1,3 @@
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_RESERVE_MEM=512
CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y

4
examples/system/light_sleep/README.md
View File

@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
# Light Sleep Example