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change(esp_hw_support): change clock kconfig name in eso32h4beta5

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This commit is contained in:
hebinglin
2025-08-18 12:55:42 +08:00
parent 9f4a568163
commit 8f8a97787d
4 changed files with 8 additions and 12 deletions
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8
components/esp_hw_support/port/esp32h21/Kconfig.rtc
View File

@@ -1,10 +1,10 @@
choice RTC_CLK_SRC
prompt "RTC clock source"
default RTC_CLK_SRC_INT_RC_D4
default RTC_CLK_SRC_INT_RC
help
Choose which clock is used as RTC clock source.
config RTC_CLK_SRC_INT_RC_D4
config RTC_CLK_SRC_INT_RC
bool "Internal 600 kHz RC oscillator, divide by 4"
config RTC_CLK_SRC_EXT_CRYS
bool "External 32 kHz crystal"
@@ -17,9 +17,9 @@ endchoice
config RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
default 1024 if RTC_CLK_SRC_INT_RC_D4
default 1024 if RTC_CLK_SRC_INT_RC
range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
range 0 32766 if RTC_CLK_SRC_INT_RC_D4
range 0 32766 if RTC_CLK_SRC_INT_RC
help
When the startup code initializes RTC_SLOW_CLK, it can perform
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL

8
components/esp_hw_support/port/esp32h4/Kconfig.rtc
View File

@@ -1,10 +1,10 @@
choice RTC_CLK_SRC
prompt "RTC clock source"
default RTC_CLK_SRC_INT_RC_D4
default RTC_CLK_SRC_INT_RC
help
Choose which clock is used as RTC clock source.
config RTC_CLK_SRC_INT_RC_D4
config RTC_CLK_SRC_INT_RC
bool "Internal 600kHz RC oscillator, divide by 4"
config RTC_CLK_SRC_EXT_CRYS
bool "External 32kHz crystal"
@@ -17,9 +17,9 @@ endchoice
config RTC_CLK_CAL_CYCLES
int "Number of cycles for RTC_SLOW_CLK calibration"
default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
default 1024 if RTC_CLK_SRC_INT_RC_D4
default 1024 if RTC_CLK_SRC_INT_RC
range 0 8190 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC
range 0 32766 if RTC_CLK_SRC_INT_RC_D4
range 0 32766 if RTC_CLK_SRC_INT_RC
help
When the startup code initializes RTC_SLOW_CLK, it can perform
calibration by comparing the RTC_SLOW_CLK frequency with main XTAL

2
examples/system/deep_sleep/sdkconfig.ci.basic
View File

@@ -2,8 +2,6 @@
CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
CONFIG_EXAMPLE_EXT1_WAKEUP=n
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_RESERVE_MEM=512
CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y

2
examples/system/deep_sleep/sdkconfig.defaults
View File

@@ -1,5 +1,3 @@
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_80=y
CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=80
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_RESERVE_MEM=512
CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y