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Merge branch 'feature/support_ut_esp32s2beta' into 'feature/esp32s2beta'

Browse Source 
ci: support build and run UT for esp32s2beta

See merge request espressif/esp-idf!5702
This commit is contained in:
Angus Gratton
2019-09-09 08:34:16 +08:00
parent 2ca954ae0f f9aaaa6c3a
commit 35147119f1
184 changed files with 3029 additions and 4693 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
.gitlab-ci.yml
View File

@@ -26,7 +26,8 @@ variables:
# If the "recursive" strategy is used we have a problem with using relative URLs for sub-submodules.
GIT_SUBMODULE_STRATEGY: normal
UNIT_TEST_BUILD_SYSTEM: make
UNIT_TEST_BUILD_SYSTEM: cmake
EXAMPLE_TEST_BUILD_SYSTEM: cmake
# IDF environment
IDF_PATH: "$CI_PROJECT_DIR"

8
components/app_update/test/CMakeLists.txt
View File

@@ -1,3 +1,5 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils app_update bootloader_support nvs_flash)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils app_update bootloader_support nvs_flash)
endif()

2
components/app_update/test/test_ota_ops.c
View File

@@ -58,7 +58,7 @@ TEST_CASE("esp_ota_get_next_update_partition logic", "[ota]")
TEST_ASSERT_NOT_NULL(ota_1);
TEST_ASSERT_NULL(ota_2); /* this partition shouldn't exist in test partition table */
TEST_ASSERT_EQUAL_PTR(factory, running); /* this may not be true if/when we get OTA tests that do OTA updates */
TEST_ASSERT_EQUAL_PTR(factory, running); /* this may not be true if/when we get OTA tests that do OTA updates */
/* (The test steps verify subtypes before verifying pointer equality, because the failure messages are more readable
this way.)

6
components/app_update/test/test_switch_ota.c
View File

@@ -7,9 +7,13 @@
#include "string.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/spi_flash.h"
#include "esp32/rom/rtc.h"
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/spi_flash.h"
#include "esp32s2beta/rom/rtc.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

4
components/bootloader_support/CMakeLists.txt
View File

@@ -1,4 +1,4 @@
set(srcs
set(srcs
"src/bootloader_clock.c"
"src/bootloader_common.c"
"src/bootloader_flash.c"
@@ -10,7 +10,7 @@ set(srcs
"src/bootloader_flash_config_${IDF_TARGET}.c"
)
if(CONFIG_IDF_TARGET_ESP32)
if(IDF_TARGET STREQUAL "esp32")
# Not supported on ESP32S2Beta yet
list(APPEND srcs "src/flash_encrypt.c")
endif()

3
components/bootloader_support/test/test_verify_image.c
View File

@@ -5,7 +5,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "string.h"
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
@@ -34,7 +33,7 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support]")
TEST_ASSERT_EQUAL(data.image_len, bootloader_length);
}
TEST_CASE("Verify unit test app image", "[bootloader_support]")
TEST_CASE_ESP32("Verify unit test app image", "[bootloader_support]")
{
esp_image_metadata_t data = { 0 };
const esp_partition_t *running = esp_ota_get_running_partition();

1
components/bt/Kconfig
View File

@@ -2,6 +2,7 @@ menu Bluetooth
config BT_ENABLED
bool "Bluetooth"
depends on IDF_TARGET_ESP32
help
Select this option to enable Bluetooth and show the submenu with Bluetooth configuration choices.

4
components/cxx/test/test_cxx.cpp
View File

@@ -276,14 +276,14 @@ TEST_CASE("c++ exceptions emergency pool", "[cxx] [ignore]")
#else // !CONFIG_COMPILER_CXX_EXCEPTIONS
TEST_CASE("std::out_of_range exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]")
TEST_CASE_ESP32("std::out_of_range exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]")
{
std::vector<int> v(10);
v.at(20) = 42;
TEST_FAIL_MESSAGE("Unreachable because we are aborted on the line above");
}
TEST_CASE("std::bad_alloc exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]")
TEST_CASE_ESP32("std::bad_alloc exception when -fno-exceptions", "[cxx][reset=abort,SW_CPU_RESET]")
{
std::string s = std::string(2000000000, 'a');
(void)s;

4
components/driver/CMakeLists.txt
View File

@@ -20,7 +20,7 @@ set(srcs
set(includes "include")
if(CONFIG_IDF_TARGET_ESP32)
if(IDF_TARGET STREQUAL "esp32")
# SDMMC and MCPWM are in ESP32 only.
list(APPEND srcs "mcpwm.c"
"sdio_slave.c"
@@ -28,7 +28,7 @@ if(CONFIG_IDF_TARGET_ESP32)
"sdmmc_transaction.c")
endif()
if(CONFIG_IDF_TARGET_ESP32S2BETA)
if(IDF_TARGET STREQUAL "esp32s2beta")
list(APPEND srcs "esp32s2beta/rtc_tempsensor.c"
"esp32s2beta/rtc_touchpad.c")
# currently only S2 beta has its own target-specific includes

5
components/driver/include/driver/mcpwm.h
View File

@@ -20,6 +20,11 @@
#include "driver/gpio.h"
#include "driver/periph_ctrl.h"
#include "esp_intr_alloc.h"
#include "soc/soc_caps.h"
#ifndef SOC_MCPWM_SUPPORTED
#error MCPWM is not supported in this chip target
#endif
#ifdef __cplusplus
extern "C" {

6
components/driver/include/driver/sdmmc_host.h
View File

@@ -20,6 +20,12 @@
#include "sdmmc_types.h"
#include "driver/gpio.h"
#include "soc/soc_caps.h"
#ifndef SOC_SDMMC_HOST_SUPPORTED
#error SDMMC host is not supported in this chip target
#endif
#ifdef __cplusplus
extern "C" {
#endif

1
components/driver/include/driver/sdspi_host.h
View File

@@ -20,7 +20,6 @@
#include "sdmmc_types.h"
#include "driver/gpio.h"
#include "driver/spi_master.h"
#include "driver/sdmmc_host.h"
#ifdef __cplusplus
extern "C" {

2
components/driver/sdspi_transaction.c
View File

@@ -18,7 +18,7 @@
#include "sys/lock.h"
#include "driver/sdmmc_types.h"
#include "driver/sdmmc_defs.h"
#include "driver/sdmmc_host.h"
#include "driver/sdmmc_types.h"
#include "sdspi_private.h"
#include "sdspi_crc.h"

12
components/driver/test/CMakeLists.txt
View File

@@ -1,3 +1,9 @@
idf_component_register(SRC_DIRS "." "param_test"
INCLUDE_DIRS "include" "param_test/include"
REQUIRES unity test_utils driver nvs_flash)
set(srcdirs . param_test)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS include param_test/include
REQUIRES unity test_utils driver nvs_flash
)

1
components/driver/test/component.mk
View File

@@ -2,6 +2,7 @@
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_SRCDIRS += param_test
COMPONENT_PRIV_INCLUDEDIRS += param_test/include

0
components/driver/test/test_adc2.c → components/driver/test/esp32/test_adc2.c
View File

9
components/driver/test/test_gpio.c → components/driver/test/esp32/test_gpio.c
View File

@@ -4,7 +4,7 @@
*/
#include <stdio.h>
#include <string.h>
#include "esp32/rom/uart.h"
#include "esp_system.h"
#include "esp_sleep.h"
#include "unity.h"
@@ -12,6 +12,13 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/queue.h"
#include "sdkconfig.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/uart.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/uart.h"
#endif
#define WAKE_UP_IGNORE 1 // gpio_wakeup function development is not completed yet, set it deprecated.
#define GPIO_OUTPUT_IO 18 // default output GPIO

356
components/driver/test/esp32/test_i2c.c Normal file
View File

@@ -0,0 +1,356 @@
/**
* test environment UT_T2_I2C:
* please prepare two ESP32-WROVER-KIT board.
* Then connect GPIO18 and GPIO18, GPIO19 and GPIO19 between these two boards.
*/
#include <stdio.h>
#include <string.h>
#include "unity.h"
#include "test_utils.h"
#include "unity_config.h"
#include "driver/i2c.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/gpio_periph.h"
#include "soc/i2c_periph.h"
#include "esp_system.h"
#include "driver/pcnt.h"
#define DATA_LENGTH 512 /*!<Data buffer length for test buffer*/
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
#define DELAY_TIME_BETWEEN_ITEMS_MS 1234 /*!< delay time between different test items */
#define I2C_SLAVE_SCL_IO 19 /*!<gpio number for i2c slave clock */
#define I2C_SLAVE_SDA_IO 18 /*!<gpio number for i2c slave data */
#define I2C_SLAVE_NUM I2C_NUM_0 /*!<I2C port number for slave dev */
#define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */
#define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */
#define I2C_MASTER_SCL_IO 19 /*!< gpio number for I2C master clock */
#define I2C_MASTER_SDA_IO 18 /*!< gpio number for I2C master data */
#define I2C_MASTER_NUM I2C_NUM_1 /*!< I2C port number for master dev */
#define I2C_MASTER_TX_BUF_DISABLE 0 /*!< I2C master do not need buffer */
#define I2C_MASTER_RX_BUF_DISABLE 0 /*!< I2C master do not need buffer */
#define I2C_MASTER_FREQ_HZ 100000 /*!< I2C master clock frequency */
#define ESP_SLAVE_ADDR 0x28 /*!< ESP32 slave address, you can set any 7bit value */
#define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
#define READ_BIT I2C_MASTER_READ /*!< I2C master read */
#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */
#define ACK_VAL 0x0 /*!< I2C ack value */
#define NACK_VAL 0x1 /*!< I2C nack value */
#define PULSE_IO 19
#define PCNT_INPUT_IO 4
#define PCNT_CTRL_FLOATING_IO 5
#define HIGHEST_LIMIT 10000
#define LOWEST_LIMIT -10000
static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, size_t size)
{
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
TEST_ESP_OK(i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | WRITE_BIT, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_write(cmd, data_wr, size, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_stop(cmd));
esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
return ret;
}
static i2c_config_t i2c_master_init(void)
{
i2c_config_t conf_master = {
.mode = I2C_MODE_MASTER,
.sda_pullup_en = GPIO_PULLUP_ENABLE,
.scl_pullup_en = GPIO_PULLUP_ENABLE,
.master.clk_speed = I2C_MASTER_FREQ_HZ,
.sda_io_num = I2C_MASTER_SDA_IO,
.scl_io_num = I2C_MASTER_SCL_IO,
};
return conf_master;
}
// print the reading buffer
static void disp_buf(uint8_t *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
printf("%02x ", buf[i]);
if (( i + 1 ) % 16 == 0) {
printf("\n");
}
}
printf("\n");
}
static i2c_config_t i2c_slave_init(void)
{
i2c_config_t conf_slave = {
.mode = I2C_MODE_SLAVE,
.sda_io_num = I2C_SLAVE_SDA_IO,
.scl_io_num = I2C_SLAVE_SCL_IO,
.sda_pullup_en = GPIO_PULLUP_ENABLE,
.scl_pullup_en = GPIO_PULLUP_ENABLE,
.slave.addr_10bit_en = 0,
.slave.slave_addr = ESP_SLAVE_ADDR,
};
return conf_slave;
}
static void i2c_master_write_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int i;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
unity_send_signal("master write");
for (i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, DATA_LENGTH / 2);
disp_buf(data_wr, i + 1);
free(data_wr);
unity_wait_for_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_MASTER_NUM));
}
static void i2c_slave_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
int size_rd = 0;
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int i = 0; i < size_rd; i++) {
TEST_ASSERT(data_rd[i] == i);
}
free(data_rd);
unity_send_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_SLAVE_NUM));
}
TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_test, i2c_slave_read_test);
static void master_read_slave_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH-1, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH-1, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("%d\n", data_rd[i]);
TEST_ASSERT(data_rd[i]==i);
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void slave_write_buffer_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read");
unity_wait_for_signal("ready to delete");
free(data_wr);
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test);
static void i2c_master_write_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read and write");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
disp_buf(data_rd, RW_TEST_LENGTH);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i/2);
}
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = i % 3;
}
vTaskDelay(100 / portTICK_RATE_MS);
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
free(data_wr);
free(data_rd);
unity_send_signal("slave read");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_read_write_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i/2;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read and write");
unity_wait_for_signal("slave read");
size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_RATE_MS);
printf("slave read data is:\n");
disp_buf(data_rd, size_rd);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i % 3);
}
free(data_wr);
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test);
static void i2c_master_repeat_write(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int times = 3;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
for (int j = 0; j < times; j++) {
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = j + i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
disp_buf(data_wr, RW_TEST_LENGTH);
}
free(data_wr);
unity_send_signal("master write");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_repeat_read(void)
{
int size_rd = 0;
int times = 3;
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH * 3);
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
int len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int j = 0; j < times; j++) {
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("data: %d, %d\n", data_rd[j * RW_TEST_LENGTH + i], (i % 129 + j));
TEST_ASSERT(data_rd[j * RW_TEST_LENGTH + i] == (i % 129 + j));
}
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read);

0
components/driver/test/test_i2s.c → components/driver/test/esp32/test_i2s.c
View File

1
components/driver/test/test_ledc.c → components/driver/test/esp32/test_ledc.c
View File

@@ -13,7 +13,6 @@
#include <stdlib.h>
#include <malloc.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

1
components/driver/test/test_pcnt.c → components/driver/test/esp32/test_pcnt.c
View File

@@ -22,7 +22,6 @@
#include "esp_log.h"
#include "soc/gpio_periph.h"
#include "unity.h"
#include "esp32/rom/ets_sys.h"
#define PULSE_IO 18
#define PCNT_INPUT_IO 4

1
components/driver/test/test_pwm.c → components/driver/test/esp32/test_pwm.c
View File

@@ -25,7 +25,6 @@
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/rtc.h"
#include "esp32/rom/ets_sys.h"
#define GPIO_PWMA_OUT 4
#define GPIO_PWMB_OUT 13

0
components/driver/test/test_rmt.c → components/driver/test/esp32/test_rmt.c
View File

281
components/driver/test/esp32/test_rs485.c Normal file
View File

@@ -0,0 +1,281 @@
/* This file is from test_uart.c, but mainly about RS485 */
#include <string.h>
#include <sys/param.h>
#include "unity.h"
#include "test_utils.h" // unity_send_signal
#include "driver/uart.h" // for the uart driver access
#include "esp_log.h"
#include "esp_system.h" // for uint32_t esp_random()
#define UART_TAG "Uart"
#define UART_NUM1 (UART_NUM_1)
#define BUF_SIZE (100)
#define UART1_RX_PIN (22)
#define UART1_TX_PIN (23)
#define UART_BAUD_11520 (11520)
#define UART_BAUD_115200 (115200)
#define TOLERANCE (0.02) //baud rate error tolerance 2%.
#define UART_TOLERANCE_CHECK(val, uper_limit, lower_limit) ( (val) <= (uper_limit) && (val) >= (lower_limit) )
// RTS for RS485 Half-Duplex Mode manages DE/~RE
#define UART1_RTS_PIN (18)
// Number of packets to be send during test
#define PACKETS_NUMBER (10)
// Wait timeout for uart driver
#define PACKET_READ_TICS (1000 / portTICK_RATE_MS)
// The table for fast CRC16 calculation
static const uint8_t crc_hi[] = {
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0,
0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1,
0x81, 0x40, 0x01,
0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01,
0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80,
0x41, 0x01, 0xC0,
0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
0x80, 0x41, 0x01,
0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00,
0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0,
0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1,
0x81, 0x40, 0x01,
0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01,
0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0,
0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
0x80, 0x41, 0x01,
0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01,
0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40
};
static const uint8_t crc_low[] = {
0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
0x05, 0xC5, 0xC4,
0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB,
0x0B, 0xC9, 0x09,
0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE,
0xDF, 0x1F, 0xDD,
0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2,
0x12, 0x13, 0xD3,
0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
0x36, 0xF6, 0xF7,
0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E,
0xFE, 0xFA, 0x3A,
0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B,
0x2A, 0xEA, 0xEE,
0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27,
0xE7, 0xE6, 0x26,
0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
0x63, 0xA3, 0xA2,
0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD,
0x6D, 0xAF, 0x6F,
0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8,
0xB9, 0x79, 0xBB,
0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4,
0x74, 0x75, 0xB5,
0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
0x50, 0x90, 0x91,
0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94,
0x54, 0x9C, 0x5C,
0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59,
0x58, 0x98, 0x88,
0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D,
0x4D, 0x4C, 0x8C,
0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
0x41, 0x81, 0x80,
0x40
};
// Calculate buffer checksum using tables
// The checksum CRC16 algorithm is specific
// for Modbus standard and uses polynomial value = 0xA001
static uint16_t get_buffer_crc16( uint8_t * frame_ptr, uint16_t length )
{
TEST_ASSERT( frame_ptr != NULL);
uint8_t crc_hi_byte = 0xFF;
uint8_t crc_low_byte = 0xFF;
int index;
while ( length-- )
{
index = crc_low_byte ^ *(frame_ptr++);
crc_low_byte = crc_hi_byte ^ crc_hi[index];
crc_hi_byte = crc_low[index];
}
return ((crc_hi_byte << 8) | crc_low_byte);
}
// Fill the buffer with random numbers and apply CRC16 at the end
static uint16_t buffer_fill_random(uint8_t *buffer, size_t length)
{
TEST_ASSERT( buffer != NULL);
// Packet is too short
if (length < 4) {
return 0;
}
for (int i = 0; i < length; i += 4) {
uint32_t random = esp_random();
memcpy(buffer + i, &random, MIN(length - i, 4));
}
// Get checksum of the buffer
uint16_t crc = get_buffer_crc16((uint8_t*)buffer, (length - 2));
// Apply checksum bytes into packet
buffer[length - 2] = (uint8_t)(crc & 0xFF); // Set Low byte CRC
buffer[length - 1] = (uint8_t)(crc >> 8); // Set High byte CRC
return crc;
}
static void rs485_init(void)
{
uart_config_t uart_config = {
.baud_rate = UART_BAUD_115200,
.data_bits = UART_DATA_8_BITS,
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
.rx_flow_ctrl_thresh = 122,
};
printf("RS485 port initialization...\r\n");
// Configure UART1 parameters
uart_param_config(UART_NUM1, &uart_config);
// Set UART1 pins(TX: IO4, RX: I05, RTS: IO18, CTS: IO19)
uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, UART1_RTS_PIN, UART_PIN_NO_CHANGE);
// Install UART driver (we don't need an event queue here)
uart_driver_install(UART_NUM1, BUF_SIZE * 2, 0, 0, NULL, 0);
// Setup rs485 half duplex mode
//uart_set_rs485_hd_mode(uart_num, true);
uart_set_mode(UART_NUM1, UART_MODE_RS485_HALF_DUPLEX);
}
static esp_err_t print_packet_data(const char *str, uint8_t *buffer, uint16_t buffer_size)
{
TEST_ASSERT( buffer != NULL);
TEST_ASSERT( str != NULL);
// Calculate the checksum of the buffer
uint16_t crc16_calc = get_buffer_crc16(buffer, (buffer_size - 2));
uint16_t crc16_in = ((uint16_t)(buffer[buffer_size - 1]) << 8) | buffer[buffer_size - 2];
const char* state_str = (crc16_in != crc16_calc) ? "incorrect " : "correct ";
// Print an array of data
printf("%s%s RS485 packet = [ ", str, state_str);
for (int i = 0; i < buffer_size; i++) {
printf("0x%.2X ", (uint8_t)buffer[i]);
}
printf(" ]\r\n");
printf("crc_in = 0x%.4X\r\n", (uint16_t)crc16_in);
printf("crc_calc = 0x%.4X\r\n", (uint16_t)crc16_calc);
esp_err_t result = (crc16_in != crc16_calc) ? ESP_ERR_INVALID_CRC : ESP_OK;
return result;
}
// Slave test case for multi device
static void rs485_slave(void)
{
rs485_init();
uint8_t* slave_data = (uint8_t*) malloc(BUF_SIZE);
uint16_t err_count = 0, good_count = 0;
printf("Start recieve loop.\r\n");
unity_send_signal("Slave_ready");
unity_wait_for_signal("Master_started");
for(int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) {
//Read slave_data from UART
int len = uart_read_bytes(UART_NUM1, slave_data, BUF_SIZE, (PACKET_READ_TICS * 2));
//Write slave_data back to UART
if (len > 2) {
esp_err_t status = print_packet_data("Received ", slave_data, len);
// If received packet is correct then send it back
if (status == ESP_OK) {
uart_write_bytes(UART_NUM1, (char*)slave_data, len);
good_count++;
} else {
printf("Incorrect packet received.\r\n");
err_count++;
}
} else {
printf("Incorrect data packet[%d] received.\r\n", pack_count);
err_count++;
}
}
printf("Test completed. Received packets = %d, errors = %d\r\n", good_count, err_count);
// Wait for packet to be sent
uart_wait_tx_done(UART_NUM1, PACKET_READ_TICS);
free(slave_data);
uart_driver_delete(UART_NUM1);
TEST_ASSERT(err_count < 2);
}
// Master test of multi device test case.
// It forms packet with random data, apply generated CRC16 and sends to slave.
// If response recieved correctly from slave means RS485 channel works.
static void rs485_master(void)
{
uint16_t err_count = 0, good_count = 0;
rs485_init();
uint8_t* master_buffer = (uint8_t*) malloc(BUF_SIZE);
uint8_t* slave_buffer = (uint8_t*) malloc(BUF_SIZE);
// The master test case should be synchronized with slave
unity_wait_for_signal("Slave_ready");
unity_send_signal("Master_started");
printf("Start recieve loop.\r\n");
for(int i = 0; i < PACKETS_NUMBER; i++) {
// Form random buffer with CRC16
buffer_fill_random(master_buffer, BUF_SIZE);
// Print created packet for debugging
esp_err_t status = print_packet_data("Send ", master_buffer, BUF_SIZE);
TEST_ASSERT(status == ESP_OK);
uart_write_bytes(UART_NUM1, (char*)master_buffer, BUF_SIZE);
// Read translated packet from slave
int len = uart_read_bytes(UART_NUM1, slave_buffer, BUF_SIZE, (PACKET_READ_TICS * 2));
// Check if the received packet is too short
if (len > 2) {
// Print received packet and check checksum
esp_err_t status = print_packet_data("Received ", slave_buffer, len);
if (status == ESP_OK) {
good_count++;
printf("Received: %d\r\n", good_count);
} else {
err_count++;
printf("Errors: %d\r\n", err_count);
}
}
else {
printf("Incorrect answer from slave.\r\n");
err_count++;
}
}
// Free the buffer and delete driver at the end
free(master_buffer);
uart_driver_delete(UART_NUM1);
TEST_ASSERT(err_count <= 1);
printf("Test completed. Received packets = %d, errors = %d\r\n", (uint16_t)good_count, (uint16_t)err_count);
}
/*
* This multi devices test case verifies RS485 mode of the uart driver and checks
* correctness of RS485 interface channel communication. It requires
* RS485 bus driver hardware to be connected to boards.
*/
TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave);

47
components/driver/test/test_spi_master.c → components/driver/test/esp32/test_spi_master.c
View File

@@ -7,7 +7,6 @@
#include <stdlib.h>
#include <malloc.h>
#include <string.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@@ -54,10 +53,12 @@ static void check_spi_pre_n_for(int clk, int pre, int n)
t.tx_buffer=sendbuf;
ret=spi_device_transmit(handle, &t);
printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, SPI2.clock.clkdiv_pre+1, SPI2.clock.clkcnt_n+1);
spi_dev_t* hw = spi_periph_signal[TEST_SPI_HOST].hw;
TEST_ASSERT(SPI2.clock.clkcnt_n+1==n);
TEST_ASSERT(SPI2.clock.clkdiv_pre+1==pre);
printf("Checking clk rate %dHz. expect pre %d n %d, got pre %d n %d\n", clk, pre, n, hw->clock.clkdiv_pre+1, hw->clock.clkcnt_n+1);
TEST_ASSERT(hw->clock.clkcnt_n+1==n);
TEST_ASSERT(hw->clock.clkdiv_pre+1==pre);
ret=spi_bus_remove_device(handle);
TEST_ASSERT(ret==ESP_OK);
@@ -330,7 +331,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 6 iomux output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -339,7 +340,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 4 iomux output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -349,7 +350,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 6 output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -359,7 +360,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test 4 output pins...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -368,14 +369,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD;
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -383,14 +384,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o );
@@ -398,7 +399,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "check native flag for 6 output pins...");
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
@@ -406,61 +407,61 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
ESP_LOGI(TAG, "check native flag for 4 output pins...");
flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS;
//swap MOSI and MISO
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MISO, .miso_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin...");
flags_expected = SPICOMMON_BUSFLAG_DUAL;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = 34, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check sclk flag...");
flags_expected = SPICOMMON_BUSFLAG_SCLK;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = -1, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check mosi flag...");
flags_expected = SPICOMMON_BUSFLAG_MOSI;
cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check miso flag...");
flags_expected = SPICOMMON_BUSFLAG_MISO;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = -1, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
ESP_LOGI(TAG, "check quad flag...");
flags_expected = SPICOMMON_BUSFLAG_QUAD;
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = -1, .quadwp_io_num = HSPI_IOMUX_PIN_NUM_WP,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));
cfg = (spi_bus_config_t){.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI, .miso_io_num = HSPI_IOMUX_PIN_NUM_MISO, .sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK, .quadhd_io_num = HSPI_IOMUX_PIN_NUM_HD, .quadwp_io_num = -1,
cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1,
.max_transfer_sz = 8, .flags = flags_expected};
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o));
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o));

0
components/driver/test/test_spi_param.c → components/driver/test/esp32/test_spi_param.c
View File

0
components/driver/test/test_spi_sio.c → components/driver/test/esp32/test_spi_sio.c
View File

8
components/driver/test/test_spi_slave.c → components/driver/test/esp32/test_spi_slave.c
View File

@@ -88,10 +88,10 @@ TEST_CASE("test slave send unaligned","[spi]")
slave_init();
//do internal connection
int_connect( PIN_NUM_MOSI, HSPID_OUT_IDX, VSPIQ_IN_IDX );
int_connect( PIN_NUM_MISO, VSPIQ_OUT_IDX, HSPID_IN_IDX );
int_connect( PIN_NUM_CS, HSPICS0_OUT_IDX, VSPICS0_IN_IDX );
int_connect( PIN_NUM_CLK, HSPICLK_OUT_IDX, VSPICLK_IN_IDX );
int_connect( PIN_NUM_MOSI, spi_periph_signal[TEST_SPI_HOST].spid_out, spi_periph_signal[TEST_SLAVE_HOST].spiq_in );
int_connect( PIN_NUM_MISO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out, spi_periph_signal[TEST_SPI_HOST].spid_in );
int_connect( PIN_NUM_CS, spi_periph_signal[TEST_SPI_HOST].spics_out[0], spi_periph_signal[TEST_SLAVE_HOST].spics_in );
int_connect( PIN_NUM_CLK, spi_periph_signal[TEST_SPI_HOST].spiclk_out, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in );
for ( int i = 0; i < 4; i ++ ) {
//slave send

39
components/driver/test/include/test/test_common_spi.h
View File

@@ -13,9 +13,43 @@
// All the tests using the header should use this definition as much as possible,
// so that the working host can be changed easily in the future.
#if CONFIG_IDF_TARGET_ESP32
#define TEST_SPI_HOST HSPI_HOST
#define TEST_SLAVE_HOST VSPI_HOST
#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO VSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI VSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK VSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP
#define SLAVE_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#define TEST_SPI_HOST FSPI_HOST
#define TEST_SLAVE_HOST HSPI_HOST
#define PIN_NUM_MISO FSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI FSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK FSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS FSPI_IOMUX_PIN_NUM_CS
#define PIN_NUM_WP FSPI_IOMUX_PIN_NUM_WP
#define PIN_NUM_HD FSPI_IOMUX_PIN_NUM_HD
#define SLAVE_PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define SLAVE_PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define SLAVE_PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define SLAVE_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
#define SLAVE_PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP
#define SLAVE_PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD
#endif
#define FUNC_SPI 1
#define FUNC_GPIO 2
@@ -52,11 +86,6 @@
0,\
}
#define PIN_NUM_MISO HSPI_IOMUX_PIN_NUM_MISO
#define PIN_NUM_MOSI HSPI_IOMUX_PIN_NUM_MOSI
#define PIN_NUM_CLK HSPI_IOMUX_PIN_NUM_CLK
#define PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS
//default bus config for tests
#define SPI_BUS_TEST_DEFAULT_CONFIG() {\
.miso_io_num=PIN_NUM_MISO, \

267
components/driver/test/test_i2c.c
View File

@@ -62,19 +62,6 @@ static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, si
return ret;
}
// print the reading buffer
static void disp_buf(uint8_t *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
printf("%02x ", buf[i]);
if (( i + 1 ) % 16 == 0) {
printf("\n");
}
}
printf("\n");
}
static i2c_config_t i2c_master_init(void)
{
i2c_config_t conf_master = {
@@ -252,260 +239,6 @@ TEST_CASE("I2C driver memory leaking check", "[i2c]")
TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size());
}
static void i2c_master_write_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int i;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
unity_send_signal("master write");
for (i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, DATA_LENGTH / 2);
disp_buf(data_wr, i + 1);
free(data_wr);
unity_wait_for_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_MASTER_NUM));
}
static void i2c_slave_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
int size_rd = 0;
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int i = 0; i < size_rd; i++) {
TEST_ASSERT(data_rd[i] == i);
}
free(data_rd);
unity_send_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_SLAVE_NUM));
}
TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_test, i2c_slave_read_test);
static void master_read_slave_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH-1, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH-1, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("%d\n", data_rd[i]);
TEST_ASSERT(data_rd[i]==i);
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void slave_write_buffer_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read");
unity_wait_for_signal("ready to delete");
free(data_wr);
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test);
static void i2c_master_write_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read and write");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
disp_buf(data_rd, RW_TEST_LENGTH);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i/2);
}
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = i % 3;
}
vTaskDelay(100 / portTICK_RATE_MS);
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
free(data_wr);
free(data_rd);
unity_send_signal("slave read");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_read_write_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i/2;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read and write");
unity_wait_for_signal("slave read");
size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_RATE_MS);
printf("slave read data is:\n");
disp_buf(data_rd, size_rd);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i % 3);
}
free(data_wr);
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test);
static void i2c_master_repeat_write(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int times = 3;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
for (int j = 0; j < times; j++) {
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = j + i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
disp_buf(data_wr, RW_TEST_LENGTH);
}
free(data_wr);
unity_send_signal("master write");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_repeat_read(void)
{
int size_rd = 0;
int times = 3;
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH * 3);
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
int len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int j = 0; j < times; j++) {
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("data: %d, %d\n", data_rd[j * RW_TEST_LENGTH + i], (i % 129 + j));
TEST_ASSERT(data_rd[j * RW_TEST_LENGTH + i] == (i % 129 + j));
}
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read);
static volatile bool exit_flag;
static bool test_read_func;

7
components/driver/test/test_sdmmc_sdspi_init.cpp
View File

@@ -1,4 +1,9 @@
#include "soc/soc_caps.h"
#if SOC_SDMMC_HOST_SUPPORTED
#include "driver/sdmmc_host.h"
#endif
#include "driver/sdspi_host.h"
@@ -9,10 +14,12 @@ static void test_initializers() __attribute__((unused));
static void test_initializers()
{
#if SOC_SDMMC_HOST_SUPPORTED
sdmmc_host_t sdmmc_host = SDMMC_HOST_DEFAULT();
(void) sdmmc_host;
sdmmc_slot_config_t sdmmc_slot = SDMMC_SLOT_CONFIG_DEFAULT();
(void) sdmmc_slot;
#endif
sdmmc_host_t sdspi_host = SDSPI_HOST_DEFAULT();
(void) sdspi_host;
sdspi_slot_config_t sdspi_slot = SDSPI_SLOT_CONFIG_DEFAULT();

251
components/driver/test/test_uart.c
View File

@@ -26,83 +26,6 @@
// Wait timeout for uart driver
#define PACKET_READ_TICS (1000 / portTICK_RATE_MS)
// The table for fast CRC16 calculation
static const uint8_t crc_hi[] = {
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0,
0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1,
0x81, 0x40, 0x01,
0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01,
0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80,
0x41, 0x01, 0xC0,
0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
0x80, 0x41, 0x01,
0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00,
0xC1, 0x81, 0x40,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0,
0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1,
0x81, 0x40, 0x01,
0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01,
0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81,
0x40, 0x01, 0xC0,
0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0,
0x80, 0x41, 0x01,
0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01,
0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
0x00, 0xC1, 0x81,
0x40
};
static const uint8_t crc_low[] = {
0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
0x05, 0xC5, 0xC4,
0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB,
0x0B, 0xC9, 0x09,
0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE,
0xDF, 0x1F, 0xDD,
0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2,
0x12, 0x13, 0xD3,
0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
0x36, 0xF6, 0xF7,
0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E,
0xFE, 0xFA, 0x3A,
0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B,
0x2A, 0xEA, 0xEE,
0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27,
0xE7, 0xE6, 0x26,
0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
0x63, 0xA3, 0xA2,
0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD,
0x6D, 0xAF, 0x6F,
0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8,
0xB9, 0x79, 0xBB,
0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4,
0x74, 0x75, 0xB5,
0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
0x50, 0x90, 0x91,
0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94,
0x54, 0x9C, 0x5C,
0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59,
0x58, 0x98, 0x88,
0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D,
0x4D, 0x4C, 0x8C,
0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
0x41, 0x81, 0x80,
0x40
};
static void uart_config(uint32_t baud_rate, bool use_ref_tick)
{
uart_config_t uart_config = {
@@ -203,177 +126,3 @@ TEST_CASE("test uart tx data with break", "[uart]")
free(psend);
uart_driver_delete(UART_NUM1);
}
// Calculate buffer checksum using tables
// The checksum CRC16 algorithm is specific
// for Modbus standard and uses polynomial value = 0xA001
static uint16_t get_buffer_crc16( uint8_t * frame_ptr, uint16_t length )
{
TEST_ASSERT( frame_ptr != NULL);
uint8_t crc_hi_byte = 0xFF;
uint8_t crc_low_byte = 0xFF;
int index;
while ( length-- )
{
index = crc_low_byte ^ *(frame_ptr++);
crc_low_byte = crc_hi_byte ^ crc_hi[index];
crc_hi_byte = crc_low[index];
}
return ((crc_hi_byte << 8) | crc_low_byte);
}
// Fill the buffer with random numbers and apply CRC16 at the end
static uint16_t buffer_fill_random(uint8_t *buffer, size_t length)
{
TEST_ASSERT( buffer != NULL);
// Packet is too short
if (length < 4) {
return 0;
}
for (int i = 0; i < length; i += 4) {
uint32_t random = esp_random();
memcpy(buffer + i, &random, MIN(length - i, 4));
}
// Get checksum of the buffer
uint16_t crc = get_buffer_crc16((uint8_t*)buffer, (length - 2));
// Apply checksum bytes into packet
buffer[length - 2] = (uint8_t)(crc & 0xFF); // Set Low byte CRC
buffer[length - 1] = (uint8_t)(crc >> 8); // Set High byte CRC
return crc;
}
static void rs485_init(void)
{
uart_config_t uart_config = {
.baud_rate = UART_BAUD_115200,
.data_bits = UART_DATA_8_BITS,
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
.rx_flow_ctrl_thresh = 122,
};
printf("RS485 port initialization...\r\n");
// Configure UART1 parameters
uart_param_config(UART_NUM1, &uart_config);
// Set UART1 pins(TX: IO4, RX: I05, RTS: IO18, CTS: IO19)
uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, UART1_RTS_PIN, UART_PIN_NO_CHANGE);
// Install UART driver (we don't need an event queue here)
uart_driver_install(UART_NUM1, BUF_SIZE * 2, 0, 0, NULL, 0);
// Setup rs485 half duplex mode
//uart_set_rs485_hd_mode(uart_num, true);
uart_set_mode(UART_NUM1, UART_MODE_RS485_HALF_DUPLEX);
}
static esp_err_t print_packet_data(const char *str, uint8_t *buffer, uint16_t buffer_size)
{
TEST_ASSERT( buffer != NULL);
TEST_ASSERT( str != NULL);
// Calculate the checksum of the buffer
uint16_t crc16_calc = get_buffer_crc16(buffer, (buffer_size - 2));
uint16_t crc16_in = ((uint16_t)(buffer[buffer_size - 1]) << 8) | buffer[buffer_size - 2];
const char* state_str = (crc16_in != crc16_calc) ? "incorrect " : "correct ";
// Print an array of data
printf("%s%s RS485 packet = [ ", str, state_str);
for (int i = 0; i < buffer_size; i++) {
printf("0x%.2X ", (uint8_t)buffer[i]);
}
printf(" ]\r\n");
printf("crc_in = 0x%.4X\r\n", (uint16_t)crc16_in);
printf("crc_calc = 0x%.4X\r\n", (uint16_t)crc16_calc);
esp_err_t result = (crc16_in != crc16_calc) ? ESP_ERR_INVALID_CRC : ESP_OK;
return result;
}
// Slave test case for multi device
static void rs485_slave(void)
{
rs485_init();
uint8_t* slave_data = (uint8_t*) malloc(BUF_SIZE);
uint16_t err_count = 0, good_count = 0;
printf("Start recieve loop.\r\n");
unity_send_signal("Slave_ready");
unity_wait_for_signal("Master_started");
for(int pack_count = 0; pack_count < PACKETS_NUMBER; pack_count++) {
//Read slave_data from UART
int len = uart_read_bytes(UART_NUM1, slave_data, BUF_SIZE, (PACKET_READ_TICS * 2));
//Write slave_data back to UART
if (len > 2) {
esp_err_t status = print_packet_data("Received ", slave_data, len);
// If received packet is correct then send it back
if (status == ESP_OK) {
uart_write_bytes(UART_NUM1, (char*)slave_data, len);
good_count++;
} else {
printf("Incorrect packet received.\r\n");
err_count++;
}
} else {
printf("Incorrect data packet[%d] received.\r\n", pack_count);
err_count++;
}
}
printf("Test completed. Received packets = %d, errors = %d\r\n", good_count, err_count);
// Wait for packet to be sent
uart_wait_tx_done(UART_NUM1, PACKET_READ_TICS);
free(slave_data);
uart_driver_delete(UART_NUM1);
TEST_ASSERT(err_count < 2);
}
// Master test of multi device test case.
// It forms packet with random data, apply generated CRC16 and sends to slave.
// If response recieved correctly from slave means RS485 channel works.
static void rs485_master(void)
{
uint16_t err_count = 0, good_count = 0;
rs485_init();
uint8_t* master_buffer = (uint8_t*) malloc(BUF_SIZE);
uint8_t* slave_buffer = (uint8_t*) malloc(BUF_SIZE);
// The master test case should be synchronized with slave
unity_wait_for_signal("Slave_ready");
unity_send_signal("Master_started");
printf("Start recieve loop.\r\n");
for(int i = 0; i < PACKETS_NUMBER; i++) {
// Form random buffer with CRC16
buffer_fill_random(master_buffer, BUF_SIZE);
// Print created packet for debugging
esp_err_t status = print_packet_data("Send ", master_buffer, BUF_SIZE);
TEST_ASSERT(status == ESP_OK);
uart_write_bytes(UART_NUM1, (char*)master_buffer, BUF_SIZE);
// Read translated packet from slave
int len = uart_read_bytes(UART_NUM1, slave_buffer, BUF_SIZE, (PACKET_READ_TICS * 2));
// Check if the received packet is too short
if (len > 2) {
// Print received packet and check checksum
esp_err_t status = print_packet_data("Received ", slave_buffer, len);
if (status == ESP_OK) {
good_count++;
printf("Received: %d\r\n", good_count);
} else {
err_count++;
printf("Errors: %d\r\n", err_count);
}
}
else {
printf("Incorrect answer from slave.\r\n");
err_count++;
}
}
// Free the buffer and delete driver at the end
free(master_buffer);
uart_driver_delete(UART_NUM1);
TEST_ASSERT(err_count <= 1);
printf("Test completed. Received packets = %d, errors = %d\r\n", (uint16_t)good_count, (uint16_t)err_count);
}
/*
* This multi devices test case verifies RS485 mode of the uart driver and checks
* correctness of RS485 interface channel communication. It requires
* RS485 bus driver hardware to be connected to boards.
*/
TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave);

4
components/driver/uart.c
View File

@@ -948,9 +948,9 @@ static void uart_rx_intr_handler_default(void *param)
//We have to read out all data in RX FIFO to clear the interrupt signal
for(buf_idx = 0; buf_idx < rx_fifo_len; buf_idx++) {
#if CONFIG_IDF_TARGET_ESP32
p_uart->rx_data_buf[buf_idx++] = uart_reg->fifo.rw_byte;
p_uart->rx_data_buf[buf_idx] = uart_reg->fifo.rw_byte;
#elif CONFIG_IDF_TARGET_ESP32S2BETA
p_uart->rx_data_buf[buf_idx++] = READ_PERI_REG(UART_FIFO_AHB_REG(uart_num));
p_uart->rx_data_buf[buf_idx] = READ_PERI_REG(UART_FIFO_AHB_REG(uart_num));
#endif
}
uint8_t pat_chr = uart_reg->at_cmd_char.data;

9
components/efuse/test/CMakeLists.txt
View File

@@ -1,3 +1,6 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "include"
REQUIRES unity test_utils efuse bootloader_support)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS . include
REQUIRES unity test_utils efuse bootloader_support
)
endif()

25
components/esp32/test/CMakeLists.txt
View File

@@ -1,16 +1,19 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}"
REQUIRES unity test_utils nvs_flash ulp esp_common)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
REQUIRES unity test_utils nvs_flash ulp esp_common
)
add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
WORKING_DIRECTORY ${COMPONENT_DIR}
DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg")
add_custom_command(OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
COMMAND xxd -i "logo.jpg" "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h"
WORKING_DIRECTORY ${COMPONENT_DIR}
DEPENDS "${CMAKE_CURRENT_LIST_DIR}/logo.jpg")
add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h")
add_custom_target(esp32_test_logo DEPENDS "${CMAKE_CURRENT_BINARY_DIR}/test_tjpgd_logo.h")
add_dependencies(${COMPONENT_LIB} esp32_test_logo)
add_dependencies(${COMPONENT_LIB} esp32_test_logo)
idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND)
idf_build_set_property(COMPILE_DEFINITIONS "-DESP_TIMER_DYNAMIC_OVERFLOW_VAL" APPEND)
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")
endif()
target_link_libraries(${COMPONENT_LIB} INTERFACE "-u ld_include_test_dport_xt_highint5")

1
components/esp32/test/test_aes_sha_rsa.c
View File

@@ -2,7 +2,6 @@
#include <stdlib.h>
#include <string.h>
#include "esp_types.h"
#include "esp32/clk.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

5
components/esp32/test/test_intr_alloc.c
View File

@@ -4,8 +4,11 @@
#include <esp_types.h>
#include <stdio.h>
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/ets_sys.h"
#elif CONFIG_IDF_TARGET_ESP32S2BETA
#include "esp32s2beta/rom/ets_sys.h"
#endif
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"

25
components/esp32/test/test_sleep.c
View File

@@ -18,6 +18,7 @@
#include "test_utils.h"
#include "sdkconfig.h"
#define ESP_EXT0_WAKEUP_LEVEL_LOW 0
#define ESP_EXT0_WAKEUP_LEVEL_HIGH 1
@@ -330,7 +331,7 @@ TEST_CASE("wake up using ext1 when RTC_PERIPH is on (13 low)", "[deepsleep][igno
static float get_time_ms(void)
{
gettimeofday(&tv_stop, NULL);
float dt = (tv_stop.tv_sec - tv_start.tv_sec) * 1e3f +
(tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f;
return fabs(dt);
@@ -343,20 +344,20 @@ static uint32_t get_cause(void)
return wakeup_cause;
}
// This test case verifies deactivation of trigger for wake up sources
// This test case verifies deactivation of trigger for wake up sources
TEST_CASE("disable source trigger behavior", "[deepsleep]")
{
float dt = 0;
printf("Setup timer and ext0 to wake up immediately from GPIO_13 \n");
// Setup ext0 configuration to wake up almost immediately
// The wakeup time is proportional to input capacitance * pullup resistance
ESP_ERROR_CHECK(rtc_gpio_init(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pullup_en(GPIO_NUM_13));
ESP_ERROR_CHECK(gpio_pulldown_dis(GPIO_NUM_13));
ESP_ERROR_CHECK(esp_sleep_enable_ext0_wakeup(GPIO_NUM_13, ESP_EXT0_WAKEUP_LEVEL_HIGH));
// Setup timer to wakeup with timeout
esp_sleep_enable_timer_wakeup(2000000);
@@ -367,22 +368,22 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
dt = get_time_ms();
printf("Ext0 sleep time = %d \n", (int) dt);
// Check wakeup from Ext0 using time measurement because wakeup cause is
// Check wakeup from Ext0 using time measurement because wakeup cause is
// not available in light sleep mode
TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt);
TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0);
// Disable Ext0 source. Timer source should be triggered
ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0));
printf("Disable ext0 trigger and leave timer active.\n");
gettimeofday(&tv_start, NULL);
esp_light_sleep_start();
dt = get_time_ms();
printf("Timer sleep time = %d \n", (int) dt);
TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt);
// Additionally check wakeup cause
@@ -407,8 +408,8 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
TEST_ASSERT_INT32_WITHIN(100, 100, (int) dt);
TEST_ASSERT((get_cause() & RTC_EXT0_TRIG_EN) != 0);
// Check error message when source is already disabled
// Check error message when source is already disabled
esp_err_t err_code = esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_TIMER);
TEST_ASSERT(err_code == ESP_ERR_INVALID_STATE);
}
@@ -429,7 +430,7 @@ static void trigger_deepsleep(void)
// Save start time. Deep sleep.
gettimeofday(&start, NULL);
esp_sleep_enable_timer_wakeup(1000);
// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
// In function esp_deep_sleep_start() uses function esp_sync_counters_rtc_and_frc()
// to prevent a negative time after wake up.
esp_deep_sleep_start();
}

6
components/esp32s2beta/Kconfig
View File

@@ -149,10 +149,7 @@ menu "ESP32S2-specific"
choice SPIRAM_TYPE
prompt "Type of SPI RAM chip in use"
default SPIRAM_TYPE_AUTO
config SPIRAM_TYPE_AUTO
bool "Auto-detect"
default SPIRAM_TYPE_ESPPSRAM32
config SPIRAM_TYPE_ESPPSRAM32
bool "ESP-PSRAM32 or IS25WP032"
@@ -163,7 +160,6 @@ menu "ESP32S2-specific"
config SPIRAM_SIZE
int
default -1 if SPIRAM_TYPE_AUTO
default 4194304 if SPIRAM_TYPE_ESPPSRAM32
default 8388608 if SPIRAM_TYPE_ESPPSRAM64
default 0

7
components/esp32s2beta/ld/esp32s2beta.ld
View File

@@ -85,11 +85,10 @@ MEMORY
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM,
len = 0x1000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
len = 0x2000 - CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM
/* RTC fast memory (same block as above), viewed from data bus
* TODO: check whether rtc_data_seg address is correct - IDF-760 */
rtc_data_seg(RW) : org = 0x3ff9e000, len = 0
/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000
}
_static_data_end = _bss_end;

8
components/esp_eth/test/CMakeLists.txt
View File

@@ -1,3 +1,5 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
PRIV_REQUIRES "unity" "test_utils" "esp_eth")
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS .
INCLUDE_DIRS .
PRIV_REQUIRES unity test_utils esp_eth)
endif()

11
components/esp_event/test/CMakeLists.txt
View File

@@ -1,3 +1,8 @@
idf_component_register(SRC_DIRS "."
PRIV_INCLUDE_DIRS "../private_include" "."
REQUIRES unity test_utils esp_event driver)
set(srcdirs .)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
PRIV_INCLUDE_DIRS . ../private_include
PRIV_REQUIRES unity test_utils esp_event driver)

2
components/esp_event/test/component.mk
View File

@@ -1,5 +1,7 @@
#
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_PRIV_INCLUDEDIRS := ../private_include .
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

1220
components/esp_event/test/esp32/test_event.c Normal file
View File

File diff suppressed because it is too large Load Diff

79
components/esp_event/test/test_event.c
View File

@@ -278,44 +278,6 @@ static void test_teardown(void)
#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds
#define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer
#if CONFIG_ESP_EVENT_POST_FROM_ISR
static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data)
{
SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg;
// Event data is just the address value (maybe have been truncated due to casting).
int *data = (int*) event_data;
TEST_ASSERT_EQUAL(*data, (int) (*sem));
xSemaphoreGive(*sem);
}
#endif
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "test_event_on_timer_alarm not ported to esp32s2beta"
#else
#if CONFIG_ESP_EVENT_POST_FROM_ISR
void IRAM_ATTR test_event_on_timer_alarm(void* para)
{
/* Retrieve the interrupt status and the counter value
from the timer that reported the interrupt */
uint64_t timer_counter_value =
timer_group_get_counter_value_in_isr(TIMER_GROUP_0, TIMER_0);
timer_group_intr_clr_in_isr(TIMER_GROUP_0, TIMER_0);
timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE);
timer_group_set_alarm_value_in_isr(TIMER_GROUP_0, TIMER_0, timer_counter_value);
int data = (int) para;
// Posting events with data more than 4 bytes should fail.
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, 5, NULL));
// This should succeedd, as data is int-sized. The handler for the event checks that the passed event data
// is correct.
BaseType_t task_unblocked;
TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, sizeof(data), &task_unblocked));
if (task_unblocked == pdTRUE) {
portYIELD_FROM_ISR();
}
}
#endif //CONFIG_ESP_EVENT_POST_FROM_ISR
#endif //CONFIG_IDF_TARGET_ESP32S2BETA
TEST_CASE("can create and delete event loops", "[event]")
{
@@ -876,7 +838,7 @@ TEST_CASE("performance test - dedicated task", "[event]")
performance_test(true);
}
TEST_CASE("performance test - no dedicated task", "[event]")
TEST_CASE_ESP32("performance test - no dedicated task", "[event]")
{
performance_test(false);
}
@@ -1188,45 +1150,6 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]")
TEST_TEARDOWN();
}
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "can post events from interrupt handler not ported to esp32s2beta"
#else
TEST_CASE("can post events from interrupt handler", "[event]")
{
SemaphoreHandle_t sem = xSemaphoreCreateBinary();
/* Select and initialize basic parameters of the timer */
timer_config_t config;
config.divider = TIMER_DIVIDER;
config.counter_dir = TIMER_COUNT_UP;
config.counter_en = TIMER_PAUSE;
config.alarm_en = TIMER_ALARM_EN;
config.intr_type = TIMER_INTR_LEVEL;
config.auto_reload = false;
timer_init(TIMER_GROUP_0, TIMER_0, &config);
/* Timer's counter will initially start from value below.
Also, if auto_reload is set, this value will be automatically reload on alarm */
timer_set_counter_value(TIMER_GROUP_0, TIMER_0, 0x00000000ULL);
/* Configure the alarm value and the interrupt on alarm. */
timer_set_alarm_value(TIMER_GROUP_0, TIMER_0, TIMER_INTERVAL0_SEC * TIMER_SCALE);
timer_enable_intr(TIMER_GROUP_0, TIMER_0);
timer_isr_register(TIMER_GROUP_0, TIMER_0, test_event_on_timer_alarm,
(void *) sem, ESP_INTR_FLAG_IRAM, NULL);
timer_start(TIMER_GROUP_0, TIMER_0);
TEST_SETUP();
TEST_ASSERT_EQUAL(ESP_OK, esp_event_handler_register(s_test_base1, TEST_EVENT_BASE1_EV1,
test_handler_post_from_isr, &sem));
xSemaphoreTake(sem, portMAX_DELAY);
TEST_TEARDOWN();
}
#endif // CONFIG_IDF_TARGET_ESP32S2BETA
#endif // CONFIG_ESP_EVENT_POST_FROM_ISR
#ifdef CONFIG_ESP_EVENT_LOOP_PROFILING

2
components/esp_rom/esp32s2beta/ld/esp32s2beta.rom.spiflash.ld
View File

@@ -26,3 +26,5 @@ PROVIDE ( esp_rom_spiflash_erase_sector = SPIEraseSector );
PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock );
PROVIDE ( esp_rom_spiflash_wait_idle = SPI_Wait_Idle );
PROVIDE ( esp_rom_spiflash_config_readmode = SPIReadModeCnfig );
PROVIDE ( esp_rom_spiflash_erase_block = SPIEraseBlock );
PROVIDE ( esp_rom_spiflash_write_encrypted = SPI_Encrypt_Write );

2
components/esp_wifi/lib_esp32

Submodule components/esp_wifi/lib_esp32 updated: 75c9095783...7d93cbf05b

2
components/esp_wifi/lib_esp32s2beta

Submodule components/esp_wifi/lib_esp32s2beta updated: ef025b8fd5...adea187bc0

12
components/esp_wifi/test/CMakeLists.txt
View File

@@ -1,6 +1,12 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "${CMAKE_CURRENT_BINARY_DIR}"
REQUIRES unity test_utils nvs_flash ulp esp_common)
set(srcdirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
REQUIRES unity test_utils nvs_flash ulp esp_common
)
idf_component_get_property(esp_wifi_dir esp_wifi COMPONENT_DIR)

1
components/esp_wifi/test/component.mk
View File

@@ -5,6 +5,7 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_SRCDIRS := .
COMPONENT_SRCDIRS += esp32
# Calculate MD5 value of header file esp_wifi_os_adapter.h
WIFI_OS_ADAPTER_MD5_VAL=\"$(shell md5sum $(IDF_PATH)/components/esp_wifi/include/esp_private/wifi_os_adapter.h | cut -c 1-7)\"

21
components/esp_wifi/test/test_phy_rtc.c → components/esp_wifi/test/esp32/test_phy_rtc.c
View File

@@ -11,18 +11,23 @@
#include <freertos/FreeRTOS.h>
#include <freertos/task.h>
#include <freertos/semphr.h>
#include "soc/soc_caps.h"
//Function just extern, need not test
#ifdef SOC_BT_SUPPORTED
extern void bt_bb_init_cmplx(void);
#endif
extern void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu(void);
extern void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu(void);
//Functions in librtc.a called by WIFI or Blutooth directly in ISR
#ifdef SOC_BT_SUPPORTED
extern void bt_bb_init_cmplx_reg(void);
extern void bt_track_pll_cap(void);
#endif
extern void force_wifi_mode(int);
extern void unforce_wifi_mode(void);
extern void bt_track_pll_cap(void);
static const char* TAG = "test_phy_rtc";
@@ -39,7 +44,9 @@ static void test_phy_rtc_init(void)
}
TEST_ESP_OK(ret);
#ifdef SOC_BT_SUPPORTED
esp_phy_load_cal_and_init(PHY_BT_MODULE);
#endif
esp_phy_load_cal_and_init(PHY_WIFI_MODULE);
//must run here, not blocking in above code
@@ -51,11 +58,6 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
{
test_phy_rtc_init();
ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()...");
spi_flash_disable_interrupts_caches_and_other_cpu();
bt_bb_init_cmplx_reg();
spi_flash_enable_interrupts_caches_and_other_cpu();
for (int i = 0; i < 2; i++) {
ESP_LOGI(TAG, "Test force_wifi_mode(%d)...", i);
spi_flash_disable_interrupts_caches_and_other_cpu();
@@ -68,10 +70,17 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
spi_flash_enable_interrupts_caches_and_other_cpu();
}
#ifdef SOC_BT_SUPPORTED
ESP_LOGI(TAG, "Test bt_bb_init_cmplx_reg()...");
spi_flash_disable_interrupts_caches_and_other_cpu();
bt_bb_init_cmplx_reg();
spi_flash_enable_interrupts_caches_and_other_cpu();
ESP_LOGI(TAG, "Test bt_track_pll_cap()...");
spi_flash_disable_interrupts_caches_and_other_cpu();
bt_track_pll_cap();
spi_flash_enable_interrupts_caches_and_other_cpu();
#endif
TEST_ASSERT( xSemaphoreGive(semphr_done) );

233
components/esp_wifi/test/esp32/test_wifi.c Normal file
View File

@@ -0,0 +1,233 @@
/*
Tests for the Wi-Fi
*/
#include "string.h"
#include "esp_system.h"
#include "unity.h"
#include "esp_system.h"
#include "esp_event_loop.h"
#include "esp_wifi.h"
#include "esp_wifi_types.h"
#include "esp_log.h"
#include "nvs_flash.h"
#include "test_utils.h"
#include "freertos/task.h"
#include "freertos/event_groups.h"
static const char* TAG = "test_wifi";
#define DEFAULT_SSID "TEST_SSID"
#define DEFAULT_PWD "TEST_PASS"
#define GOT_IP_EVENT 0x00000001
#define DISCONNECT_EVENT 0x00000002
#define EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT 0x00000001
static uint32_t wifi_event_handler_flag;
static EventGroupHandle_t wifi_events;
static esp_err_t event_handler(void *ctx, system_event_t *event)
{
printf("ev_handle_called.\n");
switch(event->event_id) {
case SYSTEM_EVENT_STA_START:
ESP_LOGI(TAG, "SYSTEM_EVENT_STA_START");
//do not actually connect in test case
//;
break;
case SYSTEM_EVENT_STA_GOT_IP:
ESP_LOGI(TAG, "SYSTEM_EVENT_STA_GOT_IP");
ESP_LOGI(TAG, "got ip:%s\n",
ip4addr_ntoa(&event->event_info.got_ip.ip_info.ip));
if (wifi_events) {
xEventGroupSetBits(wifi_events, GOT_IP_EVENT);
}
break;
case SYSTEM_EVENT_STA_DISCONNECTED:
ESP_LOGI(TAG, "SYSTEM_EVENT_STA_DISCONNECTED");
if (! (EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT & wifi_event_handler_flag) ) {
TEST_ESP_OK(esp_wifi_connect());
}
if (wifi_events) {
xEventGroupSetBits(wifi_events, DISCONNECT_EVENT);
}
break;
default:
break;
}
return ESP_OK;
}
static void start_wifi_as_softap(void)
{
wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
cfg.nvs_enable = false;
wifi_config_t w_config = {
.ap.ssid = DEFAULT_SSID,
.ap.password = DEFAULT_PWD,
.ap.ssid_len = 0,
.ap.channel = 1,
.ap.authmode = WIFI_AUTH_WPA2_PSK,
.ap.ssid_hidden = false,
.ap.max_connection = 4,
.ap.beacon_interval = 100,
};
TEST_ESP_OK(esp_event_loop_init(event_handler, NULL));
// can't deinit event loop, need to reset leak check
unity_reset_leak_checks();
if (wifi_events == NULL) {
wifi_events = xEventGroupCreate();
}
TEST_ESP_OK(esp_wifi_init(&cfg));
TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_AP));
TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_AP, &w_config));
TEST_ESP_OK(esp_wifi_start());
}
static void start_wifi_as_sta(void)
{
wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
cfg.nvs_enable = false;
// do not auto connect
wifi_event_handler_flag |= EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT;
TEST_ESP_OK(esp_event_loop_init(event_handler, NULL));
// can't deinit event loop, need to reset leak check
unity_reset_leak_checks();
if (wifi_events == NULL) {
wifi_events = xEventGroupCreate();
} else {
xEventGroupClearBits(wifi_events, 0x00ffffff);
}
TEST_ESP_OK(esp_wifi_init(&cfg));
TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA));
TEST_ESP_OK(esp_wifi_start());
}
static void stop_wifi(void)
{
printf("stop wifi\n");
TEST_ESP_OK(esp_wifi_stop());
TEST_ESP_OK(esp_wifi_deinit());
if (wifi_events) {
vEventGroupDelete(wifi_events);
wifi_events = NULL;
}
vTaskDelay(1000/portTICK_PERIOD_MS);
}
static void receive_ds2ds_packet(void)
{
test_case_uses_tcpip();
start_wifi_as_softap();
unity_wait_for_signal("sender ready");
unity_send_signal("receiver ready");
// wait for sender to send packets
vTaskDelay(1000/portTICK_PERIOD_MS);
stop_wifi();
}
static const char ds2ds_pdu[] = {
0x48, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x60, 0x94, 0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x1C, 0x26, 0xB9,
0x0D, 0x02, 0x7D, 0x13, 0x00, 0x00, 0x01, 0xE8, 0x65, 0xD4, 0xCB, 0x74,
0x1C, 0x00, 0x00, 0x26, 0xB9, 0x00, 0x00, 0x00, 0x00
};
static void send_ds2ds_packet(void)
{
test_case_uses_tcpip();
start_wifi_as_softap();
unity_send_signal("sender ready");
unity_wait_for_signal("receiver ready");
// send packet 20 times to make sure receiver will get this packet
for (uint16_t i = 0; i < 20; i++) {
esp_wifi_80211_tx(ESP_IF_WIFI_AP, ds2ds_pdu, sizeof(ds2ds_pdu), true);
vTaskDelay(50 / portTICK_PERIOD_MS);
}
stop_wifi();
}
TEST_CASE_MULTIPLE_DEVICES("receive ds2ds packet without exception", "[wifi][test_env=UT_T2_1]", receive_ds2ds_packet, send_ds2ds_packet);
static void wifi_connect_by_bssid(uint8_t *bssid)
{
EventBits_t bits;
wifi_config_t w_config = {
.sta.ssid = DEFAULT_SSID,
.sta.password = DEFAULT_PWD,
.sta.bssid_set = true,
};
memcpy(w_config.sta.bssid, bssid, 6);
TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &w_config));
TEST_ESP_OK(esp_wifi_connect());
bits = xEventGroupWaitBits(wifi_events, GOT_IP_EVENT, 1, 0, 5000/portTICK_RATE_MS);
TEST_ASSERT(bits == GOT_IP_EVENT);
}
static void test_wifi_connection_sta(void)
{
char mac_str[19];
uint8_t mac[6];
EventBits_t bits;
test_case_uses_tcpip();
start_wifi_as_sta();
unity_wait_for_signal_param("SoftAP mac", mac_str, 19);
TEST_ASSERT_TRUE(unity_util_convert_mac_from_string(mac_str, mac));
wifi_connect_by_bssid(mac);
unity_send_signal("STA connected");
bits = xEventGroupWaitBits(wifi_events, DISCONNECT_EVENT, 1, 0, 60000 / portTICK_RATE_MS);
// disconnect event not triggered
printf("wait finish\n");
TEST_ASSERT(bits == 0);
stop_wifi();
}
static void test_wifi_connection_softap(void)
{
char mac_str[19] = {0};
uint8_t mac[6];
test_case_uses_tcpip();
start_wifi_as_softap();
TEST_ESP_OK(esp_wifi_get_mac(ESP_IF_WIFI_AP, mac));
sprintf(mac_str, MACSTR, MAC2STR(mac));
unity_send_signal_param("SoftAP mac", mac_str);
unity_wait_for_signal("STA connected");
vTaskDelay(60000 / portTICK_PERIOD_MS);
stop_wifi();
}
TEST_CASE_MULTIPLE_DEVICES("test wifi retain connection for 60s", "[wifi][test_env=UT_T2_1][timeout=90]", test_wifi_connection_sta, test_wifi_connection_softap);

179
components/esp_wifi/test/test_wifi.c
View File

@@ -110,7 +110,7 @@ TEST_CASE("wifi stop and deinit","[wifi]")
.password = DEFAULT_PWD
},
};
//init nvs
ESP_LOGI(TAG, EMPH_STR("nvs_flash_init"));
esp_err_t r = nvs_flash_init();
@@ -118,7 +118,7 @@ TEST_CASE("wifi stop and deinit","[wifi]")
ESP_LOGI(TAG, EMPH_STR("no free pages or nvs version mismatch, erase.."));
TEST_ESP_OK(nvs_flash_erase());
r = nvs_flash_init();
}
}
TEST_ESP_OK(r);
//init tcpip
ESP_LOGI(TAG, EMPH_STR("tcpip_adapter_init"));
@@ -126,7 +126,7 @@ TEST_CASE("wifi stop and deinit","[wifi]")
//init event loop
ESP_LOGI(TAG, EMPH_STR("esp_event_loop_init"));
TEST_ESP_OK(esp_event_loop_init(event_handler, NULL));
ESP_LOGI(TAG, "test wifi init & deinit...");
test_wifi_init_deinit(&cfg, &wifi_config);
ESP_LOGI(TAG, "wifi init & deinit seem to be OK.");
@@ -140,175 +140,4 @@ TEST_CASE("wifi stop and deinit","[wifi]")
ESP_LOGI(TAG, "test passed...");
TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of tcpip_adapter and event_loop.");
}
static void start_wifi_as_softap(void)
{
wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
cfg.nvs_enable = false;
wifi_config_t w_config = {
.ap.ssid = DEFAULT_SSID,
.ap.password = DEFAULT_PWD,
.ap.ssid_len = 0,
.ap.channel = 1,
.ap.authmode = WIFI_AUTH_WPA2_PSK,
.ap.ssid_hidden = false,
.ap.max_connection = 4,
.ap.beacon_interval = 100,
};
TEST_ESP_OK(esp_event_loop_init(event_handler, NULL));
// can't deinit event loop, need to reset leak check
unity_reset_leak_checks();
if (wifi_events == NULL) {
wifi_events = xEventGroupCreate();
}
TEST_ESP_OK(esp_wifi_init(&cfg));
TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_AP));
TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_AP, &w_config));
TEST_ESP_OK(esp_wifi_start());
}
static void start_wifi_as_sta(void)
{
wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
cfg.nvs_enable = false;
// do not auto connect
wifi_event_handler_flag |= EVENT_HANDLER_FLAG_DO_NOT_AUTO_RECONNECT;
TEST_ESP_OK(esp_event_loop_init(event_handler, NULL));
// can't deinit event loop, need to reset leak check
unity_reset_leak_checks();
if (wifi_events == NULL) {
wifi_events = xEventGroupCreate();
} else {
xEventGroupClearBits(wifi_events, 0x00ffffff);
}
TEST_ESP_OK(esp_wifi_init(&cfg));
TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA));
TEST_ESP_OK(esp_wifi_start());
}
static void stop_wifi(void)
{
printf("stop wifi\n");
TEST_ESP_OK(esp_wifi_stop());
TEST_ESP_OK(esp_wifi_deinit());
if (wifi_events) {
vEventGroupDelete(wifi_events);
wifi_events = NULL;
}
vTaskDelay(1000/portTICK_PERIOD_MS);
}
static void receive_ds2ds_packet(void)
{
test_case_uses_tcpip();
start_wifi_as_softap();
unity_wait_for_signal("sender ready");
unity_send_signal("receiver ready");
// wait for sender to send packets
vTaskDelay(1000/portTICK_PERIOD_MS);
stop_wifi();
}
static const char ds2ds_pdu[] = {
0x48, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x19, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x60, 0x94, 0xE8, 0x65, 0xD4, 0xCB, 0x74, 0x1C, 0x26, 0xB9,
0x0D, 0x02, 0x7D, 0x13, 0x00, 0x00, 0x01, 0xE8, 0x65, 0xD4, 0xCB, 0x74,
0x1C, 0x00, 0x00, 0x26, 0xB9, 0x00, 0x00, 0x00, 0x00
};
static void send_ds2ds_packet(void)
{
test_case_uses_tcpip();
start_wifi_as_softap();
unity_send_signal("sender ready");
unity_wait_for_signal("receiver ready");
// send packet 20 times to make sure receiver will get this packet
for (uint16_t i = 0; i < 20; i++) {
esp_wifi_80211_tx(ESP_IF_WIFI_AP, ds2ds_pdu, sizeof(ds2ds_pdu), true);
vTaskDelay(50 / portTICK_PERIOD_MS);
}
stop_wifi();
}
TEST_CASE_MULTIPLE_DEVICES("receive ds2ds packet without exception", "[wifi][test_env=UT_T2_1]", receive_ds2ds_packet, send_ds2ds_packet);
static void wifi_connect_by_bssid(uint8_t *bssid)
{
EventBits_t bits;
wifi_config_t w_config = {
.sta.ssid = DEFAULT_SSID,
.sta.password = DEFAULT_PWD,
.sta.bssid_set = true,
};
memcpy(w_config.sta.bssid, bssid, 6);
TEST_ESP_OK(esp_wifi_set_config(WIFI_IF_STA, &w_config));
TEST_ESP_OK(esp_wifi_connect());
bits = xEventGroupWaitBits(wifi_events, GOT_IP_EVENT, 1, 0, 5000/portTICK_RATE_MS);
TEST_ASSERT(bits == GOT_IP_EVENT);
}
static void test_wifi_connection_sta(void)
{
char mac_str[19];
uint8_t mac[6];
EventBits_t bits;
test_case_uses_tcpip();
start_wifi_as_sta();
unity_wait_for_signal_param("SoftAP mac", mac_str, 19);
TEST_ASSERT_TRUE(unity_util_convert_mac_from_string(mac_str, mac));
wifi_connect_by_bssid(mac);
unity_send_signal("STA connected");
bits = xEventGroupWaitBits(wifi_events, DISCONNECT_EVENT, 1, 0, 60000 / portTICK_RATE_MS);
// disconnect event not triggered
printf("wait finish\n");
TEST_ASSERT(bits == 0);
stop_wifi();
}
static void test_wifi_connection_softap(void)
{
char mac_str[19] = {0};
uint8_t mac[6];
test_case_uses_tcpip();
start_wifi_as_softap();
TEST_ESP_OK(esp_wifi_get_mac(ESP_IF_WIFI_AP, mac));
sprintf(mac_str, MACSTR, MAC2STR(mac));
unity_send_signal_param("SoftAP mac", mac_str);
unity_wait_for_signal("STA connected");
vTaskDelay(60000 / portTICK_PERIOD_MS);
stop_wifi();
}
TEST_CASE_MULTIPLE_DEVICES("test wifi retain connection for 60s", "[wifi][test_env=UT_T2_1][timeout=90]", test_wifi_connection_sta, test_wifi_connection_softap);
}

30
components/fatfs/CMakeLists.txt
View File

@@ -1,12 +1,18 @@
idf_component_register(SRCS "diskio/diskio.c"
"diskio/diskio_rawflash.c"
"diskio/diskio_sdmmc.c"
"diskio/diskio_wl.c"
"src/ff.c"
"port/freertos/ffsystem.c"
"src/ffunicode.c"
"vfs/vfs_fat.c"
"vfs/vfs_fat_sdmmc.c"
"vfs/vfs_fat_spiflash.c"
INCLUDE_DIRS diskio vfs src
REQUIRES wear_levelling sdmmc)
set(srcs "diskio/diskio.c"
"diskio/diskio_rawflash.c"
"diskio/diskio_sdmmc.c"
"diskio/diskio_wl.c"
"src/ff.c"
"port/freertos/ffsystem.c"
"src/ffunicode.c"
"vfs/vfs_fat.c"
"vfs/vfs_fat_spiflash.c")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcs "vfs/vfs_fat_sdmmc.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS diskio vfs src
REQUIRES wear_levelling sdmmc
)

14
components/fatfs/test/CMakeLists.txt
View File

@@ -1,4 +1,10 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils vfs fatfs
EMBED_TXTFILES fatfs.img)
set(srcdirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS .
REQUIRES unity test_utils vfs fatfs
EMBED_TXTFILES fatfs.img
)

1
components/fatfs/test/component.mk
View File

@@ -1,2 +1,3 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_EMBED_TXTFILES := fatfs.img
COMPONENT_SRCDIRS += esp32

2
components/fatfs/test/test_fatfs_sdmmc.c → components/fatfs/test/esp32/test_fatfs_sdmmc.c
View File

@@ -29,7 +29,7 @@
#include "driver/sdmmc_defs.h"
#include "sdmmc_cmd.h"
#include "ff.h"
#include "test_fatfs_common.h"
#include "../test_fatfs_common.h"
static void test_setup(void)

1
components/fatfs/vfs/esp_vfs_fat.h
View File

@@ -17,7 +17,6 @@
#include "esp_err.h"
#include "driver/gpio.h"
#include "driver/sdmmc_types.h"
#include "driver/sdmmc_host.h"
#include "driver/sdspi_host.h"
#include "ff.h"
#include "wear_levelling.h"

18
components/freertos/include/freertos/portmacro.h
View File

@@ -353,13 +353,29 @@ static inline unsigned portENTER_CRITICAL_NESTED(void) {
* ESP32 (portMUX assertions would fail).
*/
static inline void uxPortCompareSet(volatile uint32_t *addr, uint32_t compare, uint32_t *set) {
#ifndef CONFIG_FREERTOS_UNICORE
#if XCHAL_HAVE_S32C1I
__asm__ __volatile__ (
"WSR %2,SCOMPARE1 \n"
"S32C1I %0, %1, 0 \n"
:"=r"(*set)
:"r"(addr), "r"(compare), "0"(*set)
);
#else
// No S32C1I, so do this by disabling and re-enabling interrupts (slower)
uint32_t intlevel, old_value;
__asm__ __volatile__ ("rsil %0, " XTSTR(XCHAL_EXCM_LEVEL) "\n"
: "=r"(intlevel));
old_value = *addr;
if (old_value == compare) {
*addr = *set;
}
__asm__ __volatile__ ("memw \n"
"wsr %0, ps\n"
:: "r"(intlevel));
*set = old_value;
#endif
}

6
components/freertos/portmux_impl.h
View File

@@ -91,16 +91,21 @@
static inline bool __attribute__((always_inline)) vPortCPUAcquireMutexIntsDisabled(PORTMUX_AQUIRE_MUX_FN_ARGS) {
#if !defined(CONFIG_FREERTOS_UNICORE)
#if defined(CONFIG_SPIRAM)
if (esp_ptr_external_ram(mux)) {
return vPortCPUAcquireMutexIntsDisabledExtram(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux));
}
#endif
return vPortCPUAcquireMutexIntsDisabledInternal(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux));
#else
return true;
#endif
}
static inline void vPortCPUReleaseMutexIntsDisabled(PORTMUX_RELEASE_MUX_FN_ARGS) {
#if !defined(CONFIG_FREERTOS_UNICORE)
#if defined(CONFIG_SPIRAM)
if (esp_ptr_external_ram(mux)) {
vPortCPUReleaseMutexIntsDisabledExtram(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux));
@@ -108,5 +113,6 @@ static inline void vPortCPUReleaseMutexIntsDisabled(PORTMUX_RELEASE_MUX_FN_ARGS)
}
#endif
vPortCPUReleaseMutexIntsDisabledInternal(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux));
#endif
}

14
components/freertos/test/CMakeLists.txt
View File

@@ -1,3 +1,11 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity test_utils)
set(srcdirs .)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs esp32)
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS .
REQUIRES unity test_utils
)

1
components/freertos/test/component.mk
View File

@@ -2,4 +2,5 @@
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

6
components/freertos/test/test_freertos_task_delay_until.c → components/freertos/test/esp32/test_freertos_task_delay_until.c
View File

@@ -27,10 +27,6 @@
static SemaphoreHandle_t task_delete_semphr;
#if CONFIG_IDF_TARGET_ESP32S2BETA
#warning "Test not ported to esp32s2beta"
#else
static void delaying_task(void* arg)
{
uint64_t ref_prev, ref_current;
@@ -76,5 +72,3 @@ TEST_CASE("Test vTaskDelayUntil", "[freertos]")
vSemaphoreDelete(task_delete_semphr);
ref_clock_deinit();
}
#endif // CONFIG_IDF_TARGET_ESP32S2BETA

2
components/heap/test/test_leak.c
View File

@@ -57,4 +57,4 @@ static void test_fn3(void)
check_calloc(7000);
}
TEST_CASE_MULTIPLE_STAGES("Check for leaks in MULTIPLE_STAGES mode (manual reset)", "[heap][leaks][reset=SW_CPU_RESET, SW_CPU_RESET]", test_fn2, test_fn2, test_fn3);
TEST_CASE_MULTIPLE_STAGES_ESP32("Check for leaks in MULTIPLE_STAGES mode (manual reset)", "[heap][leaks][reset=SW_CPU_RESET, SW_CPU_RESET]", test_fn2, test_fn2, test_fn3);

1
components/heap/test/test_malloc.c
View File

@@ -4,7 +4,6 @@
#include <esp_types.h>
#include <stdio.h>
#include "esp32/rom/ets_sys.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"

2
components/heap/test/test_malloc_caps.c
View File

@@ -11,7 +11,7 @@
#include <stdlib.h>
#include <sys/param.h>
TEST_CASE("Capabilities allocator test", "[heap]")
TEST_CASE_ESP32("Capabilities allocator test", "[heap]")
{
char *m1, *m2[10];
int x;

2
components/heap/test/test_realloc.c
View File

@@ -22,7 +22,7 @@ TEST_CASE("realloc shrink buffer in place", "[heap]")
#endif
TEST_CASE("realloc move data to a new heap type", "[heap]")
TEST_CASE_ESP32("realloc move data to a new heap type", "[heap]")
{
const char *test = "I am some test content to put in the heap";
char buf[64];

2
components/libsodium/test/test_sodium.c
View File

@@ -39,7 +39,7 @@ TEST_CASE("box tests", "[libsodium]")
extern int ed25519_convert_xmain(void);
TEST_CASE("ed25519_convert tests", "[libsodium][timeout=60]")
TEST_CASE_ESP32("ed25519_convert tests", "[libsodium][timeout=60]")
{
printf("Running ed25519_convert\n");
TEST_ASSERT_EQUAL(0, ed25519_convert_xmain() );

3
components/lwip/weekend_test/net_suite_test.py
View File

@@ -9,6 +9,7 @@ from shutil import copyfile
try:
import IDF
from IDF.IDFDUT import ESP32DUT
except ImportError:
# this is a test case write with tiny-test-fw.
# to run test cases outside tiny-test-fw,
@@ -83,7 +84,7 @@ def lwip_test_suite(env, extra_data):
3. Execute ttcn3 test suite
4. Collect result from ttcn3
"""
dut1 = env.get_dut("net_suite", "examples/system/network_tests")
dut1 = env.get_dut("net_suite", "examples/system/network_tests", dut_class=ESP32DUT)
# check and log bin size
binary_file = os.path.join(dut1.app.binary_path, "net_suite.bin")
bin_size = os.path.getsize(binary_file)

4
components/mbedtls/CMakeLists.txt
View File

@@ -41,5 +41,7 @@ foreach(target ${mbedtls_targets})
target_compile_definitions(${target} PUBLIC -DMBEDTLS_CONFIG_FILE="mbedtls/esp_config.h")
endforeach()
set_property(TARGET mbedcrypto APPEND PROPERTY LINK_INTERFACE_LIBRARIES mbedtls)
# Link mbedtls libraries to component library
target_link_libraries(${COMPONENT_LIB} INTERFACE ${mbedtls_targets})
target_link_libraries(${COMPONENT_LIB} INTERFACE ${mbedtls_targets})

2
components/mbedtls/port/esp32s2beta/esp_bignum.c
View File

@@ -61,7 +61,7 @@ static IRAM_ATTR void rsa_complete_isr(void *arg)
}
}
static void rsa_isr_initialise()
static void rsa_isr_initialise(void)
{
if (op_complete_sem == NULL) {
op_complete_sem = xSemaphoreCreateBinary();

4
components/mbedtls/test/test_ecp.c
View File

@@ -21,7 +21,7 @@
error hex value (mbedTLS uses -N for error codes) */
#define TEST_ASSERT_MBEDTLS_OK(X) TEST_ASSERT_EQUAL_HEX32(0, -(X))
TEST_CASE("mbedtls ECDH Generate Key", "[mbedtls]")
TEST_CASE_ESP32("mbedtls ECDH Generate Key", "[mbedtls]")
{
mbedtls_ecdh_context ctx;
mbedtls_entropy_context entropy;
@@ -48,7 +48,7 @@ TEST_CASE("mbedtls ECP self-tests", "[mbedtls]")
TEST_ASSERT_EQUAL(0, mbedtls_ecp_self_test(1));
}
TEST_CASE("mbedtls ECP mul w/ koblitz", "[mbedtls]")
TEST_CASE_ESP32("mbedtls ECP mul w/ koblitz", "[mbedtls]")
{
/* Test case code via https://github.com/espressif/esp-idf/issues/1556 */
mbedtls_entropy_context ctxEntropy;

4
components/mbedtls/test/test_mbedtls_mpi.c
View File

@@ -143,7 +143,7 @@ static bool test_bignum_modexp(const char *z_str, const char *x_str, const char
if (ret_error != mbedtls_mpi_exp_mod(&Z, &X, &Y, &M, NULL)) {
fail = true;
}
if (ret_error == MBEDTLS_OK) {
mbedtls_mpi_write_string(&Z, 16, z_buf, sizeof(z_buf)-1, &z_buf_len);
if (memcmp(z_str, z_buf, strlen(z_str)) != 0) {
@@ -165,7 +165,7 @@ static bool test_bignum_modexp(const char *z_str, const char *x_str, const char
return fail;
}
TEST_CASE("test MPI modexp", "[bignum]")
TEST_CASE_ESP32("test MPI modexp", "[bignum]")
{
bool test_error = false;
printf("Z = (X ^ Y) mod M \n");

14
components/mbedtls/test/test_mbedtls_sha.c
View File

@@ -15,7 +15,7 @@
#include "sdkconfig.h"
#include "test_apb_dport_access.h"
TEST_CASE("mbedtls SHA self-tests", "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA self-tests", "[mbedtls]")
{
start_apb_access_loop();
TEST_ASSERT_FALSE_MESSAGE(mbedtls_sha1_self_test(1), "SHA1 self-tests should pass.");
@@ -121,7 +121,7 @@ static void tskRunSHA256Test(void *pvParameters)
#define SHA_TASK_STACK_SIZE (10*1024)
TEST_CASE("mbedtls SHA multithreading", "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA multithreading", "[mbedtls]")
{
done_sem = xSemaphoreCreateCounting(4, 0);
xTaskCreate(tskRunSHA1Test, "SHA1Task1", SHA_TASK_STACK_SIZE, NULL, 3, NULL);
@@ -164,7 +164,7 @@ void tskRunSHASelftests(void *param)
vTaskDelete(NULL);
}
TEST_CASE("mbedtls SHA self-tests multithreaded", "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA self-tests multithreaded", "[mbedtls]")
{
done_sem = xSemaphoreCreateCounting(2, 0);
xTaskCreate(tskRunSHASelftests, "SHASelftests1", SHA_TASK_STACK_SIZE, NULL, 3, NULL);
@@ -180,7 +180,7 @@ TEST_CASE("mbedtls SHA self-tests multithreaded", "[mbedtls]")
vSemaphoreDelete(done_sem);
}
TEST_CASE("mbedtls SHA512 clone", "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA512 clone", "[mbedtls]")
{
mbedtls_sha512_context ctx;
mbedtls_sha512_context clone;
@@ -205,7 +205,7 @@ TEST_CASE("mbedtls SHA512 clone", "[mbedtls]")
TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha512_thousand_bs, sha512, 64, "SHA512 cloned calculation");
}
TEST_CASE("mbedtls SHA384 clone", "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA384 clone", "[mbedtls]")
{
mbedtls_sha512_context ctx;
mbedtls_sha512_context clone;
@@ -231,7 +231,7 @@ TEST_CASE("mbedtls SHA384 clone", "[mbedtls]")
}
TEST_CASE("mbedtls SHA256 clone", "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA256 clone", "[mbedtls]")
{
mbedtls_sha256_context ctx;
mbedtls_sha256_context clone;
@@ -276,7 +276,7 @@ static void tskFinaliseSha(void *v_param)
vTaskDelete(NULL);
}
TEST_CASE("mbedtls SHA session passed between tasks" , "[mbedtls]")
TEST_CASE_ESP32("mbedtls SHA session passed between tasks" , "[mbedtls]")
{
finalise_sha_param_t param = { 0 };

3
components/mqtt/weekend_test/mqtt_publish_test.py
View File

@@ -13,6 +13,7 @@ import random
try:
import IDF
from IDF.IDFDUT import ESP32DUT
except ImportError:
# this is a test case write with tiny-test-fw.
# to run test cases outside tiny-test-fw,
@@ -138,7 +139,7 @@ def test_weekend_mqtt_publish(env, extra_data):
3. Test evaluates python client received correct qos0 message
4. Test ESP32 client received correct qos0 message
"""
dut1 = env.get_dut("mqtt_publish", "examples/protocols/mqtt/publish_test")
dut1 = env.get_dut("mqtt_publish", "examples/protocols/mqtt/publish_test", dut_class=ESP32DUT)
# check and log bin size
binary_file = os.path.join(dut1.app.binary_path, "mqtt_publish.bin")
bin_size = os.path.getsize(binary_file)

84
components/newlib/test/test_time.c
View File

@@ -9,7 +9,6 @@
#include "freertos/semphr.h"
#include "sdkconfig.h"
#include "soc/rtc.h"
#include "esp32/clk.h"
#include "esp_system.h"
#include "test_utils.h"
@@ -223,16 +222,26 @@ static void get_time_task(void *pvParameters)
static void start_measure(int64_t* sys_time, int64_t* real_time)
{
struct timeval tv_time;
*real_time = esp_timer_get_time();
gettimeofday(&tv_time, NULL);
int64_t t1, t2;
do {
t1 = esp_timer_get_time();
gettimeofday(&tv_time, NULL);
t2 = esp_timer_get_time();
} while (t2 - t1 > 40);
*real_time = t2;
*sys_time = (int64_t)tv_time.tv_sec * 1000000L + tv_time.tv_usec;
}
static void end_measure(int64_t* sys_time, int64_t* real_time)
{
struct timeval tv_time;
gettimeofday(&tv_time, NULL);
*real_time = esp_timer_get_time();
int64_t t1, t2;
do {
t1 = esp_timer_get_time();
gettimeofday(&tv_time, NULL);
t2 = esp_timer_get_time();
} while (t2 - t1 > 40);
*real_time = t2;
*sys_time = (int64_t)tv_time.tv_sec * 1000000L + tv_time.tv_usec;
}
@@ -253,51 +262,55 @@ static int64_t calc_correction(const char* tag, int64_t* sys_time, int64_t* real
static void measure_time_task(void *pvParameters)
{
struct timeval tv_time;
int64_t real_time_us[2];
int64_t sys_time_us[2];
int64_t delay_us = 2 * 1000000; // 2 sec
xSemaphoreHandle *sema = (xSemaphoreHandle *) pvParameters;
int64_t main_real_time_us[2];
int64_t main_sys_time_us[2];
struct timeval tv_time = {.tv_sec = 1550000000, .tv_usec = 0};
TEST_ASSERT_EQUAL(0, settimeofday(&tv_time, NULL));
struct timeval delta = {.tv_sec = 2000, .tv_usec = 900000};
adjtime(&delta, NULL);
gettimeofday(&tv_time, NULL);
start_measure(&sys_time_us[0], &real_time_us[0]);
// although exit flag is set in another task, checking (exit_flag == false) is safe
while (exit_flag == false) {
ets_delay_us(delay_us);
start_measure(&main_sys_time_us[0], &main_real_time_us[0]);
end_measure(&sys_time_us[1], &real_time_us[1]);
result_adjtime_correction_us[1] += calc_correction("measure", sys_time_us, real_time_us);
{
int64_t real_time_us[2];
int64_t sys_time_us[2];
int64_t delay_us = 2 * 1000000; // 2 sec
start_measure(&sys_time_us[0], &real_time_us[0]);
// although exit flag is set in another task, checking (exit_flag == false) is safe
while (exit_flag == false) {
ets_delay_us(delay_us);
sys_time_us[0] = sys_time_us[1];
real_time_us[0] = real_time_us[1];
end_measure(&sys_time_us[1], &real_time_us[1]);
result_adjtime_correction_us[1] += calc_correction("measure", sys_time_us, real_time_us);
sys_time_us[0] = sys_time_us[1];
real_time_us[0] = real_time_us[1];
}
}
end_measure(&main_sys_time_us[1], &main_real_time_us[1]);
result_adjtime_correction_us[0] = calc_correction("main", main_sys_time_us, main_real_time_us);
int64_t delta_us = result_adjtime_correction_us[0] - result_adjtime_correction_us[1];
printf("\nresult of adjtime correction: %lli us, %lli us. delta = %lli us\n", result_adjtime_correction_us[0], result_adjtime_correction_us[1], delta_us);
TEST_ASSERT_INT_WITHIN(100, 0, delta_us);
xSemaphoreGive(*sema);
vTaskDelete(NULL);
}
TEST_CASE("test time adjustment happens linearly", "[newlib][timeout=35]")
{
int64_t real_time_us[2];
int64_t sys_time_us[2];
exit_flag = false;
struct timeval tv_time = {.tv_sec = 1550000000, .tv_usec = 0};
TEST_ASSERT_EQUAL(0, settimeofday(&tv_time, NULL));
struct timeval delta = {.tv_sec = 2000, .tv_usec = 900000};
adjtime(&delta, NULL);
gettimeofday(&tv_time, NULL);
xSemaphoreHandle exit_sema[2];
for (int i = 0; i < 2; ++i) {
exit_sema[i] = xSemaphoreCreateBinary();
result_adjtime_correction_us[i] = 0;
}
start_measure(&sys_time_us[0], &real_time_us[0]);
xTaskCreatePinnedToCore(get_time_task, "get_time_task", 2048, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, NULL, 0);
xTaskCreatePinnedToCore(measure_time_task, "measure_time_task", 2048, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, NULL, 1);
xTaskCreatePinnedToCore(get_time_task, "get_time_task", 4096, &exit_sema[0], UNITY_FREERTOS_PRIORITY - 1, NULL, 0);
xTaskCreatePinnedToCore(measure_time_task, "measure_time_task", 4096, &exit_sema[1], UNITY_FREERTOS_PRIORITY - 1, NULL, 1);
printf("start waiting for 30 seconds\n");
vTaskDelay(30000 / portTICK_PERIOD_MS);
@@ -311,13 +324,6 @@ TEST_CASE("test time adjustment happens linearly", "[newlib][timeout=35]")
}
}
end_measure(&sys_time_us[1], &real_time_us[1]);
result_adjtime_correction_us[0] = calc_correction("main", sys_time_us, real_time_us);
int64_t delta_us = result_adjtime_correction_us[0] - result_adjtime_correction_us[1];
printf("\nresult of adjtime correction: %lli us, %lli us. delta = %lli us\n", result_adjtime_correction_us[0], result_adjtime_correction_us[1], delta_us);
TEST_ASSERT_INT_WITHIN(100, 0, delta_us);
for (int i = 0; i < 2; ++i) {
vSemaphoreDelete(exit_sema[i]);
}
@@ -424,7 +430,7 @@ void test_posix_timers_clock (void)
#endif // defined( WITH_FRC ) || defined( WITH_RTC )
}
TEST_CASE("test posix_timers clock_... functions", "[newlib]")
TEST_CASE_ESP32("test posix_timers clock_... functions", "[newlib]")
{
test_posix_timers_clock();
}

12
components/protocomm/test/test_protocomm.c
View File

@@ -1098,7 +1098,7 @@ static esp_err_t test_security0 (void)
return ESP_OK;
}
TEST_CASE("leak test", "[PROTOCOMM]")
TEST_CASE_ESP32("leak test", "[PROTOCOMM]")
{
#ifdef CONFIG_HEAP_TRACING
heap_trace_init_standalone(trace_record, NUM_RECORDS);
@@ -1144,17 +1144,17 @@ TEST_CASE("security 0 basic test", "[PROTOCOMM]")
TEST_ASSERT(test_security0() == ESP_OK);
}
TEST_CASE("security 1 basic test", "[PROTOCOMM]")
TEST_CASE_ESP32("security 1 basic test", "[PROTOCOMM]")
{
TEST_ASSERT(test_security1() == ESP_OK);
}
TEST_CASE("security 1 no encryption test", "[PROTOCOMM]")
TEST_CASE_ESP32("security 1 no encryption test", "[PROTOCOMM]")
{
TEST_ASSERT(test_security1_no_encryption() == ESP_OK);
}
TEST_CASE("security 1 session overflow test", "[PROTOCOMM]")
TEST_CASE_ESP32("security 1 session overflow test", "[PROTOCOMM]")
{
TEST_ASSERT(test_security1_session_overflow() == ESP_OK);
}
@@ -1164,12 +1164,12 @@ TEST_CASE("security 1 wrong pop test", "[PROTOCOMM]")
TEST_ASSERT(test_security1_wrong_pop() == ESP_OK);
}
TEST_CASE("security 1 insecure client test", "[PROTOCOMM]")
TEST_CASE_ESP32("security 1 insecure client test", "[PROTOCOMM]")
{
TEST_ASSERT(test_security1_insecure_client() == ESP_OK);
}
TEST_CASE("security 1 weak session test", "[PROTOCOMM]")
TEST_CASE_ESP32("security 1 weak session test", "[PROTOCOMM]")
{
TEST_ASSERT(test_security1_weak_session() == ESP_OK);
}

8
components/sdmmc/test/CMakeLists.txt
View File

@@ -1,3 +1,5 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity sdmmc)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity sdmmc)
endif()

2
components/sdmmc/test/test_sdio.c
View File

@@ -40,7 +40,6 @@
/* TODO: add SDIO slave header files, remove these definitions */
#define DR_REG_SLC_BASE 0x3ff58000
#define DR_REG_SLC_MASK 0xfffffc00
#define SLCCONF1 (DR_REG_SLC_BASE + 0x60)
@@ -52,7 +51,6 @@
#define SLC_SLC0_TXLINK_RESTART (BIT(30))
#define SLC_SLC0_TXLINK_START (BIT(29))
#define DR_REG_SLCHOST_BASE 0x3ff55000
#define DR_REG_SLCHOST_MASK 0xfffffc00
#define SLCHOST_STATE_W0 (DR_REG_SLCHOST_BASE + 0x64)
#define SLCHOST_CONF_W0 (DR_REG_SLCHOST_BASE + 0x6C)

2
components/soc/CMakeLists.txt
View File

@@ -20,7 +20,7 @@ list(APPEND srcs
)
# TODO: SPI Flash HAL for ESP32S2Beta also
if(CONFIG_IDF_TARGET_ESP32)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcs "src/hal/spi_flash_hal.c"
"src/hal/spi_flash_hal_iram.c"
)

2
components/soc/esp32/include/hal/spi_ll.h
View File

@@ -36,6 +36,8 @@
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
#define SPI_LL_GET_HW(ID) ((ID)==0? &SPI1:((ID)==1? &SPI2 : &SPI3))
/**
* The data structure holding calculated clock configuration. Since the
* calculation needs long time, it should be calculated during initialization and

8
components/soc/esp32/include/soc/soc_caps.h Normal file
View File

@@ -0,0 +1,8 @@
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.
#define SOC_MCPWM_SUPPORTED 1
#define SOC_SDMMC_HOST_SUPPORTED 1
#define SOC_BT_SUPPORTED 1

11
components/soc/esp32/soc_memory_layout.c
View File

@@ -68,6 +68,13 @@ const soc_memory_type_desc_t soc_memory_types[] = {
const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
#if CONFIG_SPIRAM_SIZE == -1
// Assume we need to reserve 4MB in the auto-detection case
#define RESERVE_SPIRAM_SIZE (4*1024*1024)
#else
#define RESERVE_SPIRAM_SIZE CONFIG_SPIRAM_SIZE
#endif
/*
Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
@@ -76,7 +83,7 @@ from low to high start address.
*/
const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, CONFIG_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
{ SOC_EXTRAM_DATA_LOW, RESERVE_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
#endif
{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
@@ -167,7 +174,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
#endif
#ifdef CONFIG_SPIRAM
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + RESERVE_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
#endif
#endif /* BOOTLOADER_BUILD */

2
components/soc/esp32s2beta/include/hal/spi_ll.h
View File

@@ -36,6 +36,8 @@
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : ((ID)==2? &GPSPI3: &GPSPI4)))
/**
* The data structure holding calculated clock configuration. Since the
* calculation needs long time, it should be calculated during initialization and

3028
components/soc/esp32s2beta/include/soc/mcpwm_reg.h
View File

File diff suppressed because it is too large Load Diff

462
components/soc/esp32s2beta/include/soc/mcpwm_struct.h
View File

@@ -1,462 +0,0 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_MCPWM_STRUCT_H__
#define _SOC_MCPWM_STRUCT_H__
#ifdef __cplusplus
extern "C" {
#endif
typedef volatile struct {
union {
struct {
uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
uint32_t reserved8: 24;
};
uint32_t val;
}clk_cfg;
struct {
union {
struct {
uint32_t prescale: 8; /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
uint32_t period: 16; /*period shadow reg of PWM timer0*/
uint32_t upmethod: 2; /*Update method for active reg of PWM timer0 period 0: immediate 1: TEZ 2: sync 3: TEZ | sync. TEZ here and below means timer equal zero event*/
uint32_t reserved26: 6;
};
uint32_t val;
}period;
union {
struct {
uint32_t start: 3; /*PWM timer0 start and stop control. 0: stop @ TEZ 1: stop @ TEP 2: free run 3: start and stop @ next TEZ 4: start and stop @ next TEP. TEP here and below means timer equal period event*/
uint32_t mode: 2; /*PWM timer0 working mode 0: freeze 1: increase mod 2: decrease mod 3: up-down mod*/
uint32_t reserved5: 27;
};
uint32_t val;
}mode;
union {
struct {
uint32_t in_en: 1; /*when set timer reload with phase on sync input event is enabled*/
uint32_t sync_sw: 1; /*write the negate value will trigger a software sync*/
uint32_t out_sel: 2; /*PWM timer0 synco selection 0: synci 1: TEZ 2: TEP else 0*/
uint32_t timer_phase: 17; /*phase for timer reload on sync event*/
uint32_t reserved21: 11;
};
uint32_t val;
}sync;
union {
struct {
uint32_t value: 16; /*current PWM timer0 counter value*/
uint32_t direction: 1; /*current PWM timer0 counter direction 0: increment 1: decrement*/
uint32_t reserved17: 15;
};
uint32_t val;
}status;
}timer[3];
union {
struct {
uint32_t t0_in_sel: 3; /*select sync input for PWM timer0 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t t1_in_sel: 3; /*select sync input for PWM timer1 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t t2_in_sel: 3; /*select sync input for PWM timer2 1: PWM timer0 synco 2: PWM timer1 synco 3: PWM timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix else: none*/
uint32_t ext_in0_inv: 1; /*invert SYNC0 from GPIO matrix*/
uint32_t ext_in1_inv: 1; /*invert SYNC1 from GPIO matrix*/
uint32_t ext_in2_inv: 1; /*invert SYNC2 from GPIO matrix*/
uint32_t reserved12: 20;
};
uint32_t val;
}timer_synci_cfg;
union {
struct {
uint32_t operator0_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator0 0: timer0 1: timer1 2: timer2*/
uint32_t operator1_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator1 0: timer0 1: timer1 2: timer2*/
uint32_t operator2_sel: 2; /*Select which PWM timer's is the timing reference for PWM operator2 0: timer0 1: timer1 2: timer2*/
uint32_t reserved6: 26;
};
uint32_t val;
}timer_sel;
struct {
union {
struct {
uint32_t a_upmethod: 4; /*Update method for PWM compare0 A's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
uint32_t b_upmethod: 4; /*Update method for PWM compare0 B's active reg. 0: immediate bit0: TEZ bit1: TEP bit2: sync bit3: freeze*/
uint32_t a_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared A's active reg has been updated with shadow reg latest value*/
uint32_t b_shdw_full: 1; /*Set and reset by hardware. If set PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared B's active reg has been updated with shadow reg latest value*/
uint32_t reserved10: 22;
};
uint32_t val;
}cmpr_cfg;
union {
struct {
uint32_t cmpr_val: 16; /*PWM compare0 A's shadow reg*/
uint32_t reserved16:16;
};
uint32_t val;
}cmpr_value[2];
union {
struct {
uint32_t upmethod: 4; /*Update method for PWM generate0's active reg of configuration. 0: immediate bit0: TEZ bit1: TEP bit2: sync. bit3: freeze*/
uint32_t t0_sel: 3; /*Source selection for PWM generate0 event_t0 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
uint32_t t1_sel: 3; /*Source selection for PWM generate0 event_t1 take effect immediately 0: fault_event0 1: fault_event1 2: fault_event2 3: sync_taken 4: none*/
uint32_t reserved10: 22;
};
uint32_t val;
}gen_cfg0;
union {
struct {
uint32_t cntu_force_upmethod: 6; /*Update method for continuous software force of PWM generate0. 0: immediate bit0: TEZ bit1: TEP bit2: TEA bit3: TEB bit4: sync bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
uint32_t a_cntuforce_mode: 2; /*Continuous software force mode for PWM0A. 0: disabled 1: low 2: high 3: disabled*/
uint32_t b_cntuforce_mode: 2; /*Continuous software force mode for PWM0B. 0: disabled 1: low 2: high 3: disabled*/
uint32_t a_nciforce: 1; /*non-continuous immediate software force trigger for PWM0A a toggle will trigger a force event*/
uint32_t a_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0A 0: disabled 1: low 2: high 3: disabled*/
uint32_t b_nciforce: 1; /*non-continuous immediate software force trigger for PWM0B a toggle will trigger a force event*/
uint32_t b_nciforce_mode: 2; /*non-continuous immediate software force mode for PWM0B 0: disabled 1: low 2: high 3: disabled*/
uint32_t reserved16: 16;
};
uint32_t val;
}gen_force;
union {
struct {
uint32_t utez: 2; /*Action on PWM0A triggered by event TEZ when timer increasing*/
uint32_t utep: 2; /*Action on PWM0A triggered by event TEP when timer increasing*/
uint32_t utea: 2; /*Action on PWM0A triggered by event TEA when timer increasing*/
uint32_t uteb: 2; /*Action on PWM0A triggered by event TEB when timer increasing*/
uint32_t ut0: 2; /*Action on PWM0A triggered by event_t0 when timer increasing*/
uint32_t ut1: 2; /*Action on PWM0A triggered by event_t1 when timer increasing*/
uint32_t dtez: 2; /*Action on PWM0A triggered by event TEZ when timer decreasing*/
uint32_t dtep: 2; /*Action on PWM0A triggered by event TEP when timer decreasing*/
uint32_t dtea: 2; /*Action on PWM0A triggered by event TEA when timer decreasing*/
uint32_t dteb: 2; /*Action on PWM0A triggered by event TEB when timer decreasing*/
uint32_t dt0: 2; /*Action on PWM0A triggered by event_t0 when timer decreasing*/
uint32_t dt1: 2; /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change 1: low 2: high 3: toggle*/
uint32_t reserved24: 8;
};
uint32_t val;
}generator[2];
union {
struct {
uint32_t fed_upmethod: 4; /*Update method for FED (falling edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t red_upmethod: 4; /*Update method for RED (rising edge delay) active reg. 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
uint32_t deb_mode: 1; /*S8 in documentation dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
uint32_t a_outswap: 1; /*S6 in documentation*/
uint32_t b_outswap: 1; /*S7 in documentation*/
uint32_t red_insel: 1; /*S4 in documentation*/
uint32_t fed_insel: 1; /*S5 in documentation*/
uint32_t red_outinvert: 1; /*S2 in documentation*/
uint32_t fed_outinvert: 1; /*S3 in documentation*/
uint32_t a_outbypass: 1; /*S1 in documentation*/
uint32_t b_outbypass: 1; /*S0 in documentation*/
uint32_t clk_sel: 1; /*Dead band0 clock selection. 0: PWM_clk 1: PT_clk*/
uint32_t reserved18: 14;
};
uint32_t val;
}db_cfg;
union {
struct {
uint32_t fed: 16; /*Shadow reg for FED*/
uint32_t reserved16:16;
};
uint32_t val;
}db_fed_cfg;
union {
struct {
uint32_t red: 16; /*Shadow reg for RED*/
uint32_t reserved16:16;
};
uint32_t val;
}db_red_cfg;
union {
struct {
uint32_t en: 1; /*When set carrier0 function is enabled. When reset carrier0 is bypassed*/
uint32_t prescale: 4; /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
uint32_t duty: 3; /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
uint32_t oshtwth: 4; /*width of the fist pulse in number of periods of the carrier*/
uint32_t out_invert: 1; /*when set invert the output of PWM0A and PWM0B for this submodule*/
uint32_t in_invert: 1; /*when set invert the input of PWM0A and PWM0B for this submodule*/
uint32_t reserved14: 18;
};
uint32_t val;
}carrier_cfg;
union {
struct {
uint32_t sw_cbc: 1; /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f2_cbc: 1; /*event_f2 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f1_cbc: 1; /*event_f1 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t f0_cbc: 1; /*event_f0 will trigger cycle-by-cycle trip event. 0: disable 1: enable*/
uint32_t sw_ost: 1; /*one-shot tripping software force event will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f2_ost: 1; /*event_f2 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f1_ost: 1; /*event_f1 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t f0_ost: 1; /*event_f0 will trigger one-shot trip event. 0: disable 1: enable*/
uint32_t a_cbc_d: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_cbc_u: 2; /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_d: 2; /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t a_ost_u: 2; /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_d: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_cbc_u: 2; /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_d: 2; /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t b_ost_u: 2; /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing 1: force lo 2: force hi 3: toggle*/
uint32_t reserved24: 8;
};
uint32_t val;
}tz_cfg0;
union {
struct {
uint32_t clr_ost: 1; /*a toggle will clear on going one-shot tripping*/
uint32_t cbcpulse: 2; /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ bit1:TEP*/
uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping software force event*/
uint32_t force_ost: 1; /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
uint32_t reserved5: 27;
};
uint32_t val;
}tz_cfg1;
union {
struct {
uint32_t cbc_on: 1; /*Set and reset by hardware. If set an cycle-by-cycle trip event is on going*/
uint32_t ost_on: 1; /*Set and reset by hardware. If set an one-shot trip event is on going*/
uint32_t reserved2: 30;
};
uint32_t val;
}tz_status;
}channel[3];
union {
struct {
uint32_t f0_en: 1; /*When set event_f0 generation is enabled*/
uint32_t f1_en: 1; /*When set event_f1 generation is enabled*/
uint32_t f2_en: 1; /*When set event_f2 generation is enabled*/
uint32_t f0_pole: 1; /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f1_pole: 1; /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t f2_pole: 1; /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low 1: level high*/
uint32_t event_f0: 1; /*Set and reset by hardware. If set event_f0 is on going*/
uint32_t event_f1: 1; /*Set and reset by hardware. If set event_f1 is on going*/
uint32_t event_f2: 1; /*Set and reset by hardware. If set event_f2 is on going*/
uint32_t reserved9: 23;
};
uint32_t val;
}fault_detect;
union {
struct {
uint32_t timer_en: 1; /*When set capture timer incrementing under APB_clk is enabled.*/
uint32_t synci_en: 1; /*When set capture timer sync is enabled.*/
uint32_t synci_sel: 3; /*capture module sync input selection. 0: none 1: timer0 synco 2: timer1 synco 3: timer2 synco 4: SYNC0 from GPIO matrix 5: SYNC1 from GPIO matrix 6: SYNC2 from GPIO matrix*/
uint32_t sync_sw: 1; /*Write 1 will force a capture timer sync capture timer is loaded with value in phase register.*/
uint32_t reserved6: 26;
};
uint32_t val;
}cap_timer_cfg;
uint32_t cap_timer_phase; /*Phase value for capture timer sync operation.*/
union {
struct {
uint32_t en: 1; /*When set capture on channel 0 is enabled*/
uint32_t mode: 2; /*Edge of capture on channel 0 after prescale. bit0: negedge cap en bit1: posedge cap en*/
uint32_t prescale: 8; /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
uint32_t in_invert: 1; /*when set CAP0 form GPIO matrix is inverted before prescale*/
uint32_t sw: 1; /*Write 1 will trigger a software forced capture on channel 0*/
uint32_t reserved13: 19;
};
uint32_t val;
}cap_cfg_ch[3];
uint32_t cap_val_ch[3]; /*Value of last capture on channel 0*/
union {
struct {
uint32_t cap0_edge: 1; /*Edge of last capture trigger on channel 0 0: posedge 1: negedge*/
uint32_t cap1_edge: 1; /*Edge of last capture trigger on channel 1 0: posedge 1: negedge*/
uint32_t cap2_edge: 1; /*Edge of last capture trigger on channel 2 0: posedge 1: negedge*/
uint32_t reserved3: 29;
};
uint32_t val;
}cap_status;
union {
struct {
uint32_t global_up_en: 1; /*The global enable of update of all active registers in MCPWM module*/
uint32_t global_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
uint32_t op0_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 0 are enabled*/
uint32_t op0_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
uint32_t op1_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 1 are enabled*/
uint32_t op1_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
uint32_t op2_up_en: 1; /*When set and PWM_GLOBAL_UP_EN is set update of active registers in PWM operator 2 are enabled*/
uint32_t op2_force_up: 1; /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
uint32_t reserved8: 24;
};
uint32_t val;
}update_cfg;
union {
struct {
uint32_t timer0_stop_int_ena: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_ena: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_ena: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_ena: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_ena: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_ena: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_ena: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_ena: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_ena: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_ena: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_ena: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_ena: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_ena: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_ena: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_ena: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_ena: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_ena: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_ena: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_ena: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_ena: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_ena: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_ena: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_ena: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_ena: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_ena: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_ena: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_ena: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_ena: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_ena;
union {
struct {
uint32_t timer0_stop_int_raw: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_raw: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_raw: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_raw: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_raw: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_raw: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_raw: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_raw: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_raw: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_raw: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_raw: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_raw: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_raw: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_raw: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_raw: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_raw: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_raw: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_raw: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_raw: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_raw: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_raw: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_raw: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_raw: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_raw: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_raw: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_raw: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_raw: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_raw: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_raw;
union {
struct {
uint32_t timer0_stop_int_st: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_st: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_st: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_st: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_st: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_st: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_st: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_st: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_st: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_st: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_st: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_st: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_st: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_st: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_st: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_st: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_st: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_st: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_st: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_st: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_st: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_st: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_st: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_st: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_st: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_st: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_st: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_st: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_st;
union {
struct {
uint32_t timer0_stop_int_clr: 1; /*Interrupt when timer 0 stops*/
uint32_t timer1_stop_int_clr: 1; /*Interrupt when timer 1 stops*/
uint32_t timer2_stop_int_clr: 1; /*Interrupt when timer 2 stops*/
uint32_t timer0_tez_int_clr: 1; /*A PWM timer 0 TEZ event will trigger this interrupt*/
uint32_t timer1_tez_int_clr: 1; /*A PWM timer 1 TEZ event will trigger this interrupt*/
uint32_t timer2_tez_int_clr: 1; /*A PWM timer 2 TEZ event will trigger this interrupt*/
uint32_t timer0_tep_int_clr: 1; /*A PWM timer 0 TEP event will trigger this interrupt*/
uint32_t timer1_tep_int_clr: 1; /*A PWM timer 1 TEP event will trigger this interrupt*/
uint32_t timer2_tep_int_clr: 1; /*A PWM timer 2 TEP event will trigger this interrupt*/
uint32_t fault0_int_clr: 1; /*Interrupt when event_f0 starts*/
uint32_t fault1_int_clr: 1; /*Interrupt when event_f1 starts*/
uint32_t fault2_int_clr: 1; /*Interrupt when event_f2 starts*/
uint32_t fault0_clr_int_clr: 1; /*Interrupt when event_f0 ends*/
uint32_t fault1_clr_int_clr: 1; /*Interrupt when event_f1 ends*/
uint32_t fault2_clr_int_clr: 1; /*Interrupt when event_f2 ends*/
uint32_t cmpr0_tea_int_clr: 1; /*A PWM operator 0 TEA event will trigger this interrupt*/
uint32_t cmpr1_tea_int_clr: 1; /*A PWM operator 1 TEA event will trigger this interrupt*/
uint32_t cmpr2_tea_int_clr: 1; /*A PWM operator 2 TEA event will trigger this interrupt*/
uint32_t cmpr0_teb_int_clr: 1; /*A PWM operator 0 TEB event will trigger this interrupt*/
uint32_t cmpr1_teb_int_clr: 1; /*A PWM operator 1 TEB event will trigger this interrupt*/
uint32_t cmpr2_teb_int_clr: 1; /*A PWM operator 2 TEB event will trigger this interrupt*/
uint32_t tz0_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_cbc_int_clr: 1; /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
uint32_t tz0_ost_int_clr: 1; /*An one-shot trip event on PWM0 will trigger this interrupt*/
uint32_t tz1_ost_int_clr: 1; /*An one-shot trip event on PWM1 will trigger this interrupt*/
uint32_t tz2_ost_int_clr: 1; /*An one-shot trip event on PWM2 will trigger this interrupt*/
uint32_t cap0_int_clr: 1; /*A capture on channel 0 will trigger this interrupt*/
uint32_t cap1_int_clr: 1; /*A capture on channel 1 will trigger this interrupt*/
uint32_t cap2_int_clr: 1; /*A capture on channel 2 will trigger this interrupt*/
uint32_t reserved30: 2;
};
uint32_t val;
}int_clr;
union {
struct {
uint32_t clk_en: 1; /*Force clock on for this reg file*/
uint32_t reserved1: 31;
};
uint32_t val;
}reg_clk;
union {
struct {
uint32_t date: 28; /*Version of this reg file*/
uint32_t reserved28: 4;
};
uint32_t val;
}version;
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1;
#ifdef __cplusplus
}
#endif
#endif /* _SOC_MCPWM_STRUCT_H__ */

4
components/soc/esp32s2beta/include/soc/soc_caps.h Normal file
View File

@@ -0,0 +1,4 @@
// The long term plan is to have a single soc_caps.h for each peripheral.
// During the refactoring and multichip support development process, we
// seperate these information into periph_caps.h for each peripheral and
// include them here.

7
components/soc/include/soc/soc_memory_layout.h
View File

@@ -163,9 +163,12 @@ inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
intptr_t ip = (intptr_t) p;
bool r;
r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
#if CONFIG_SPIRAM && CONFIG_SPIRAM_SIZE
// ToDo: Use SOC_EXTRAM_DATA_HIGH if CONFIG_SPIRAM_SIZE is -1 (ie max possible SPIRAM size)
#if CONFIG_SPIRAM
#if CONFIG_SPIRAM_SIZE != -1 // Fixed size, can be more accurate
r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
#else
r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_HIGH));
#endif
#endif
return r;
}

4
components/spi_flash/CMakeLists.txt
View File

@@ -4,7 +4,7 @@ if(BOOTLOADER_BUILD)
# but on other platforms no source files are needed for bootloader
set(srcs)
else()
set(srcs
set(srcs
"cache_utils.c"
"flash_mmap.c"
"flash_ops.c"
@@ -27,7 +27,7 @@ else()
set(priv_requires bootloader_support app_update soc)
endif()
if(CONFIG_IDF_TARGET_ESP32)
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcs "spi_flash_rom_patch.c")
endif()

6
components/spi_flash/test/CMakeLists.txt
View File

@@ -1,3 +1,7 @@
idf_component_register(SRC_DIRS "."
set(src_dirs ".")
if(IDF_TARGET STREQUAL "esp32")
list(APPEND src_dirs "esp32")
endif()
idf_component_register(SRC_DIRS ${src_dirs}
INCLUDE_DIRS "."
REQUIRES unity test_utils spi_flash bootloader_support app_update)

1
components/spi_flash/test/component.mk
View File

@@ -2,4 +2,5 @@
#Component Makefile
#
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

0
components/spi_flash/test/test_esp_flash.c → components/spi_flash/test/esp32/test_esp_flash.c
View File

0
components/spi_flash/test/test_partition_ext.c → components/spi_flash/test/esp32/test_partition_ext.c
View File

10
components/spi_flash/test/test_mmap.c
View File

@@ -75,7 +75,7 @@ static void setup_mmap_tests(void)
}
}
TEST_CASE("Can mmap into data address space", "[spi_flash]")
TEST_CASE_ESP32("Can mmap into data address space", "[spi_flash]")
{
setup_mmap_tests();
@@ -135,7 +135,7 @@ TEST_CASE("Can mmap into data address space", "[spi_flash]")
TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA));
}
TEST_CASE("Can mmap into instruction address space", "[mmap]")
TEST_CASE_ESP32("Can mmap into instruction address space", "[mmap]")
{
setup_mmap_tests();
@@ -183,7 +183,7 @@ TEST_CASE("Can mmap into instruction address space", "[mmap]")
}
TEST_CASE("Can mmap unordered pages into contiguous memory", "[spi_flash]")
TEST_CASE_ESP32("Can mmap unordered pages into contiguous memory", "[spi_flash]")
{
int nopages;
int *pages;
@@ -324,7 +324,7 @@ TEST_CASE("flash_mmap can mmap after get enough free MMU pages", "[spi_flash]")
TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA));
}
TEST_CASE("phys2cache/cache2phys basic checks", "[spi_flash]")
TEST_CASE_ESP32("phys2cache/cache2phys basic checks", "[spi_flash]")
{
uint8_t buf[64];
@@ -401,7 +401,7 @@ TEST_CASE("munmap followed by mmap flushes cache", "[spi_flash]")
TEST_ASSERT_NOT_EQUAL(0, memcmp(buf, data, sizeof(buf)));
}
TEST_CASE("no stale data read post mmap and write partition", "[spi_flash]")
TEST_CASE_ESP32("no stale data read post mmap and write partition", "[spi_flash]")
{
const char buf[] = "Test buffer data for partition";
char read_data[sizeof(buf)];

2
components/spi_flash/test/test_read_write.c
View File

@@ -167,7 +167,7 @@ static void IRAM_ATTR test_write(int dst_off, int src_off, int len)
TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
}
TEST_CASE("Test spi_flash_write", "[spi_flash][esp_flash]")
TEST_CASE_ESP32("Test spi_flash_write", "[spi_flash][esp_flash]")
{
setup_tests();
#if CONFIG_SPI_FLASH_MINIMAL_TEST

16
components/ulp/test/CMakeLists.txt
View File

@@ -1,8 +1,10 @@
idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "."
REQUIRES unity ulp soc esp_common)
if(IDF_TARGET STREQUAL "esp32")
idf_component_register(SRC_DIRS esp32
INCLUDE_DIRS .
REQUIRES unity ulp soc esp_common)
set(ulp_app_name ulp_test_app)
set(ulp_s_sources "ulp/test_jumps.S")
set(ulp_exp_dep_srcs "test_ulp_as.c")
ulp_embed_binary(${ulp_app_name} ${ulp_s_sources} ${ulp_exp_dep_srcs})
set(ulp_app_name ulp_test_app)
set(ulp_s_sources "ulp/test_jumps_esp32.S")
set(ulp_exp_dep_srcs "esp32/test_ulp_as.c")
ulp_embed_binary(${ulp_app_name} ${ulp_s_sources} ${ulp_exp_dep_srcs})
endif()

8
components/ulp/test/component.mk
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@@ -1,11 +1,13 @@
ULP_APP_NAME = ulp_test_app
COMPONENT_SRCDIRS += esp32
ULP_S_SOURCES = $(addprefix $(COMPONENT_PATH)/ulp/, \
test_jumps.S \
test_jumps_esp32.S \
)
ULP_EXP_DEP_OBJECTS := test_ulp_as.o
ULP_EXP_DEP_OBJECTS := esp32/test_ulp_as.o
include $(IDF_PATH)/components/ulp/component_ulp_common.mk
COMPONENT_ADD_LDFLAGS += -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

0
components/ulp/test/test_ulp.c → components/ulp/test/esp32/test_ulp.c
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0
components/ulp/test/test_ulp_as.c → components/ulp/test/esp32/test_ulp_as.c
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0
components/ulp/test/ulp/test_jumps.S → components/ulp/test/ulp/test_jumps_esp32.S
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