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Merge branch 'feat/h4_introduce_step2_2' into 'master'

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feat(esp32h4): add soc register header files (stage 3/8, part 2/3)

See merge request espressif/esp-idf!37030
This commit is contained in:
Chen Ji Chang
2025-02-19 16:27:31 +08:00
parent 7e93f4b5ed d68fcf1d7b
commit 36335e38b6
50 changed files with 56340 additions and 0 deletions
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326
components/soc/esp32h4/include/soc/gpio_sig_map.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define TIMER_IN_IDX 0 // TODO: [ESP32H4] IDF-12499 need check
#define LEDC_LS_SIG_OUT0_IDX 0
#define LEDC_LS_SIG_OUT1_IDX 1
#define LEDC_LS_SIG_OUT2_IDX 2
#define LEDC_LS_SIG_OUT3_IDX 3
#define LEDC_LS_SIG_OUT4_IDX 4
#define LEDC_LS_SIG_OUT5_IDX 5
#define LEDC_LS_SIG_OUT6_IDX 6
#define LEDC_LS_SIG_OUT7_IDX 7
#define U0RXD_IN_IDX 8
#define U0TXD_OUT_IDX 8
#define U0CTS_IN_IDX 9
#define U0RTS_OUT_IDX 9
#define U0DSR_IN_IDX 10
#define U0DTR_OUT_IDX 10
#define U1RXD_IN_IDX 11
#define U1TXD_OUT_IDX 11
#define U1CTS_IN_IDX 12
#define U1RTS_OUT_IDX 12
#define U1DSR_IN_IDX 13
#define U1DTR_OUT_IDX 13
#define I2S_MCLK_IN_IDX 14
#define I2S_MCLK_OUT_IDX 14
#define I2SO_BCK_IN_IDX 15
#define I2SO_BCK_OUT_IDX 15
#define I2SO_WS_IN_IDX 16
#define I2SO_WS_OUT_IDX 16
#define I2SI_SD_IN_IDX 17
#define I2SO_SD_OUT_IDX 17
#define I2SI_BCK_IN_IDX 18
#define I2SI_BCK_OUT_IDX 18
#define I2SI_WS_IN_IDX 19
#define I2SI_WS_OUT_IDX 19
#define I2SO_SD1_OUT_IDX 20
#define CPU0_TESTBUS0_IDX 21
#define CPU0_TESTBUS1_IDX 22
#define CPU0_TESTBUS2_IDX 23
#define CPU0_TESTBUS3_IDX 24
#define CPU0_TESTBUS4_IDX 25
#define CPU0_TESTBUS5_IDX 26
#define CPU0_TESTBUS6_IDX 27
#define CPU0_TESTBUS7_IDX 28
#define CPU0_GPIO_IN0_IDX 29
#define CPU0_GPIO_OUT0_IDX 29
#define CPU0_GPIO_IN1_IDX 30
#define CPU0_GPIO_OUT1_IDX 30
#define CPU0_GPIO_IN2_IDX 31
#define CPU0_GPIO_OUT2_IDX 31
#define CPU0_GPIO_IN3_IDX 32
#define CPU0_GPIO_OUT3_IDX 32
#define CPU0_GPIO_IN4_IDX 33
#define CPU0_GPIO_OUT4_IDX 33
#define CPU0_GPIO_IN5_IDX 34
#define CPU0_GPIO_OUT5_IDX 34
#define CPU0_GPIO_IN6_IDX 35
#define CPU0_GPIO_OUT6_IDX 35
#define CPU0_GPIO_IN7_IDX 36
#define CPU0_GPIO_OUT7_IDX 36
#define USB_JTAG_TDO_IDX 37
#define USB_JTAG_TRST_IDX 37
#define USB_JTAG_SRST_IDX 38
#define USB_JTAG_TCK_IDX 39
#define USB_JTAG_TMS_IDX 40
#define USB_JTAG_TDI_IDX 41
#define CPU_USB_JTAG_TDO_IDX 42
#define USB_OTG_IDDIG_IN_IDX 43
#define USB_SRP_DISCHRGVBUS_OUT_IDX 43
#define USB_OTG_AVALID_IN_IDX 44
#define USB_OTG_IDPULLUP_OUT_IDX 44
#define USB_SRP_BVALID_IN_IDX 45
#define USB_OTG_DPPULLDOWN_OUT_IDX 45
#define USB_OTG_VBUSVALID_IN_IDX 46
#define USB_OTG_DMPULLDOWN_OUT_IDX 46
#define USB_SRP_SESSEND_IN_IDX 47
#define USB_OTG_DRVVBUS_OUT_IDX 47
#define USB_SRP_CHRGVBUS_OUT_IDX 48
#define I2CEXT0_SCL_IN_IDX 49
#define I2CEXT0_SCL_OUT_IDX 49
#define I2CEXT0_SDA_IN_IDX 50
#define I2CEXT0_SDA_OUT_IDX 50
#define PARL_RX_DATA0_IDX 51
#define PARL_TX_DATA0_IDX 51
#define PARL_RX_DATA1_IDX 52
#define PARL_TX_DATA1_IDX 52
#define PARL_RX_DATA2_IDX 53
#define PARL_TX_DATA2_IDX 53
#define PARL_RX_DATA3_IDX 54
#define PARL_TX_DATA3_IDX 54
#define PARL_RX_DATA4_IDX 55
#define PARL_TX_DATA4_IDX 55
#define PARL_RX_DATA5_IDX 56
#define PARL_TX_DATA5_IDX 56
#define PARL_RX_DATA6_IDX 57
#define PARL_TX_DATA6_IDX 57
#define PARL_RX_DATA7_IDX 58
#define PARL_TX_DATA7_IDX 58
#define FSPICLK_IN_IDX 59
#define FSPICLK_OUT_IDX 59
#define FSPIQ_IN_IDX 60
#define FSPIQ_OUT_IDX 60
#define FSPID_IN_IDX 61
#define FSPID_OUT_IDX 61
#define FSPIHD_IN_IDX 62
#define FSPIHD_OUT_IDX 62
#define FSPIWP_IN_IDX 63
#define FSPIWP_OUT_IDX 63
#define FSPICS0_IN_IDX 64
#define FSPICS0_OUT_IDX 64
#define PARL_RX_CLK_IN_IDX 65
#define PARL_RX_CLK_OUT_IDX 65
#define PARL_TX_CLK_IN_IDX 66
#define PARL_TX_CLK_OUT_IDX 66
#define RMT_SIG_IN0_IDX 67
#define RMT_SIG_OUT0_IDX 67
#define RMT_SIG_IN1_IDX 68
#define RMT_SIG_OUT1_IDX 68
#define TWAI0_RX_IDX 69
#define TWAI0_TX_IDX 69
#define PARL_TX_CS_IDX 70
#define EXTERN_PRIORITY_I_IDX 75
#define EXTERN_PRIORITY_O_IDX 75
#define EXTERN_ACTIVE_I_IDX 76
#define EXTERN_ACTIVE_O_IDX 76
#define PCNT_RST_IN0_IDX 77
#define GPIO_SD0_OUT_IDX 77
#define PCNT_RST_IN1_IDX 78
#define GPIO_SD1_OUT_IDX 78
#define PCNT_RST_IN2_IDX 79
#define GPIO_SD2_OUT_IDX 79
#define PCNT_RST_IN3_IDX 80
#define GPIO_SD3_OUT_IDX 80
#define PWM0_SYNC0_IN_IDX 81
#define PWM0_OUT0A_IDX 81
#define PWM0_SYNC1_IN_IDX 82
#define PWM0_OUT0B_IDX 82
#define PWM0_SYNC2_IN_IDX 83
#define PWM0_OUT1A_IDX 83
#define PWM0_F0_IN_IDX 84
#define PWM0_OUT1B_IDX 84
#define PWM0_F1_IN_IDX 85
#define PWM0_OUT2A_IDX 85
#define PWM0_F2_IN_IDX 86
#define PWM0_OUT2B_IDX 86
#define PWM0_CAP0_IN_IDX 87
#define PWM0_CAP1_IN_IDX 88
#define PWM0_CAP2_IN_IDX 89
#define GPIO_EVENT_MATRIX_IN0_IDX 90
#define GPIO_TASK_MATRIX_OUT0_IDX 90
#define GPIO_EVENT_MATRIX_IN1_IDX 91
#define GPIO_TASK_MATRIX_OUT1_IDX 91
#define GPIO_EVENT_MATRIX_IN2_IDX 92
#define GPIO_TASK_MATRIX_OUT2_IDX 92
#define GPIO_EVENT_MATRIX_IN3_IDX 93
#define GPIO_TASK_MATRIX_OUT3_IDX 93
#define CLK_OUT_OUT1_IDX 94
#define CLK_OUT_OUT2_IDX 95
#define CLK_OUT_OUT3_IDX 96
#define SIG_IN_FUNC_97_IDX 97
#define SIG_IN_FUNC97_IDX 97
#define SIG_IN_FUNC_98_IDX 98
#define SIG_IN_FUNC98_IDX 98
#define SIG_IN_FUNC_99_IDX 99
#define SIG_IN_FUNC99_IDX 99
#define SIG_IN_FUNC_100_IDX 100
#define SIG_IN_FUNC100_IDX 100
#define PCNT_SIG_CH0_IN0_IDX 102
#define FSPICS1_OUT_IDX 102
#define PCNT_SIG_CH1_IN0_IDX 103
#define FSPICS2_OUT_IDX 103
#define PCNT_CTRL_CH0_IN0_IDX 104
#define FSPICS3_OUT_IDX 104
#define PCNT_CTRL_CH1_IN0_IDX 105
#define FSPICS4_OUT_IDX 105
#define PCNT_SIG_CH0_IN1_IDX 106
#define FSPICS5_OUT_IDX 106
#define PCNT_SIG_CH1_IN1_IDX 107
#define MODEM_DIAG0_IDX 107
#define PCNT_CTRL_CH0_IN1_IDX 108
#define MODEM_DIAG1_IDX 108
#define PCNT_CTRL_CH1_IN1_IDX 109
#define MODEM_DIAG2_IDX 109
#define PCNT_SIG_CH0_IN2_IDX 110
#define MODEM_DIAG3_IDX 110
#define PCNT_SIG_CH1_IN2_IDX 111
#define MODEM_DIAG4_IDX 111
#define PCNT_CTRL_CH0_IN2_IDX 112
#define MODEM_DIAG5_IDX 112
#define PCNT_CTRL_CH1_IN2_IDX 113
#define MODEM_DIAG6_IDX 113
#define PCNT_SIG_CH0_IN3_IDX 114
#define MODEM_DIAG7_IDX 114
#define PCNT_SIG_CH1_IN3_IDX 115
#define MODEM_DIAG8_IDX 115
#define PCNT_CTRL_CH0_IN3_IDX 116
#define MODEM_DIAG9_IDX 116
#define PCNT_CTRL_CH1_IN3_IDX 117
#define MODEM_DIAG10_IDX 117
#define MODEM_DIAG11_IDX 118
#define MODEM_DIAG12_IDX 119
#define MODEM_DIAG13_IDX 120
#define MODEM_DIAG14_IDX 121
#define MODEM_DIAG15_IDX 122
#define MODEM_DIAG16_IDX 123
#define MODEM_DIAG17_IDX 124
#define MODEM_DIAG18_IDX 125
#define MODEM_DIAG19_IDX 126
#define MODEM_DIAG20_IDX 127
#define MODEM_DIAG21_IDX 128
#define MODEM_DIAG22_IDX 129
#define MODEM_DIAG23_IDX 130
#define MODEM_DIAG24_IDX 131
#define MODEM_DIAG25_IDX 132
#define MODEM_DIAG26_IDX 133
#define MODEM_DIAG27_IDX 134
#define MODEM_DIAG28_IDX 135
#define MODEM_DIAG29_IDX 136
#define MODEM_DIAG30_IDX 137
#define MODEM_DIAG31_IDX 138
#define ANT_SEL0_IDX 139
#define ANT_SEL1_IDX 140
#define ANT_SEL2_IDX 141
#define ANT_SEL3_IDX 142
#define ANT_SEL4_IDX 143
#define ANT_SEL5_IDX 144
#define ANT_SEL6_IDX 145
#define ANT_SEL7_IDX 146
#define ANT_SEL8_IDX 147
#define ANT_SEL9_IDX 148
#define ANT_SEL10_IDX 149
#define ANT_SEL11_IDX 150
#define ANT_SEL12_IDX 151
#define ANT_SEL13_IDX 152
#define ANT_SEL14_IDX 153
#define ANT_SEL15_IDX 154
#define PWM1_SYNC0_IN_IDX 155
#define PWM1_OUT0A_IDX 155
#define PWM1_SYNC1_IN_IDX 156
#define PWM1_OUT0B_IDX 156
#define PWM1_SYNC2_IN_IDX 157
#define PWM1_OUT1A_IDX 157
#define PWM1_F0_IN_IDX 158
#define PWM1_OUT1B_IDX 158
#define PWM1_F1_IN_IDX 159
#define PWM1_OUT2A_IDX 159
#define PWM1_F2_IN_IDX 160
#define PWM1_OUT2B_IDX 160
#define PWM1_CAP0_IN_IDX 161
#define PWM1_CAP1_IN_IDX 162
#define PWM1_CAP2_IN_IDX 163
#define I2CEXT1_SCL_IN_IDX 164
#define I2CEXT1_SCL_OUT_IDX 164
#define I2CEXT1_SDA_IN_IDX 165
#define I2CEXT1_SDA_OUT_IDX 165
#define FSPI3CLK_IN_IDX 166
#define FSPI3CLK_OUT_IDX 166
#define FSPI3Q_IN_IDX 167
#define FSPI3Q_OUT_IDX 167
#define FSPI3D_IN_IDX 168
#define FSPI3D_OUT_IDX 168
#define FSPI3HD_IN_IDX 169
#define FSPI3HD_OUT_IDX 169
#define FSPI3WP_IN_IDX 170
#define FSPI3WP_OUT_IDX 170
#define FSPI3CS0_IN_IDX 171
#define FSPI3CS0_OUT_IDX 171
#define FSPI3CS1_OUT_IDX 172
#define FSPI3CS2_OUT_IDX 173
#define CPU1_TESTBUS0_IDX 174
#define CPU1_TESTBUS1_IDX 175
#define CPU1_TESTBUS2_IDX 176
#define CPU1_TESTBUS3_IDX 177
#define CPU1_TESTBUS4_IDX 178
#define CPU1_TESTBUS5_IDX 179
#define CPU1_TESTBUS6_IDX 180
#define CPU1_TESTBUS7_IDX 181
#define CPU1_GPIO_IN0_IDX 182
#define CPU1_GPIO_OUT0_IDX 182
#define CPU1_GPIO_IN1_IDX 183
#define CPU1_GPIO_OUT1_IDX 183
#define CPU1_GPIO_IN2_IDX 184
#define CPU1_GPIO_OUT2_IDX 184
#define CPU1_GPIO_IN3_IDX 185
#define CPU1_GPIO_OUT3_IDX 185
#define CPU1_GPIO_IN4_IDX 186
#define CPU1_GPIO_OUT4_IDX 186
#define CPU1_GPIO_IN5_IDX 187
#define CPU1_GPIO_OUT5_IDX 187
#define CPU1_GPIO_IN6_IDX 188
#define CPU1_GPIO_OUT6_IDX 188
#define CPU1_GPIO_IN7_IDX 189
#define CPU1_GPIO_OUT7_IDX 189
#define DIAG_MODE0_OUT_MUX0_IDX 190
#define DIAG_MODE0_OUT_MUX1_IDX 191
#define DIAG_MODE0_OUT_MUX2_IDX 192
#define DIAG_MODE0_OUT_MUX3_IDX 193
#define DIAG_MODE0_OUT_MUX4_IDX 194
#define DIAG_MODE0_OUT_MUX5_IDX 195
#define DIAG_MODE0_OUT_MUX6_IDX 196
#define DIAG_MODE0_OUT_MUX7_IDX 197
#define PROBE_TOUCH_OUT_IDX 198
#define PROBE_TOP_OUT0_IDX 199
#define PROBE_TOP_OUT1_IDX 200
#define PROBE_TOP_OUT2_IDX 201
#define PROBE_TOP_OUT3_IDX 202
#define PROBE_TOP_OUT4_IDX 203
#define PROBE_TOP_OUT5_IDX 204
#define PROBE_TOP_OUT6_IDX 205
#define PROBE_TOP_OUT7_IDX 206
#define PROBE_TOP_OUT8_IDX 207
#define PROBE_TOP_OUT9_IDX 208
#define PROBE_TOP_OUT10_IDX 209
#define PROBE_TOP_OUT11_IDX 210
#define PROBE_TOP_OUT12_IDX 211
#define PROBE_TOP_OUT13_IDX 212
#define PROBE_TOP_OUT14_IDX 213
#define PROBE_TOP_OUT15_IDX 214
// version date 2403250
#define SIG_GPIO_OUT_IDX 256

116
components/soc/esp32h4/include/soc/interrupts.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_PWR_INTR_SOURCE,
ETS_WIFI_BB_INTR_SOURCE,
ETS_BT_MAC_INTR_SOURCE,
ETS_BT_BB_INTR_SOURCE,
ETS_BT_BB_NMI_SOURCE,
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MST_INTR_SOURCE,
ETS_ZB_MAC_INTR_SOURCE,
ETS_MODEM_APB_TIMEOUT_INTR_SOURCE,
ETS_BT_MAC_INT1_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE,
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_RTC_BLE_TIMER_INTR_SOURCE,
ETS_LP_WDT_INTR_SOURCE,
ETS_TOUCH_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
ETS_BUS_MONITOR_INTR_SOURCE,
ETS_CORE0_TRACE_INTR_SOURCE,
ETS_CORE1_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTERRUPT_PRO_SOURCE,
ETS_GPIO_INTERRUPT_2_SOURCE,
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_HP_APM_M0_INTR_SOURCE,
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_CPU_APM_M0_INTR_SOURCE,
ETS_CPU_APM_M1_INTR_SOURCE,
ETS_CPU_APM_M2_INTR_SOURCE,
ETS_CPU_APM_M3_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S_INTR_SOURCE,
ETS_UHCI0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_LEDC_INTR_SOURCE,
ETS_TWAI0_INTR_SOURCE,
ETS_TWAI0_TIMER_INTR_SOURCE,
ETS_USB_SERIAL_JTAG_INTR_SOURCE,
ETS_RMT_INTR_SOURCE,
ETS_I2C_EXT0_INTR_SOURCE,
ETS_I2C_EXT1_INTR_SOURCE,
ETS_TG0_T0_INTR_SOURCE,
ETS_TG0_WDT_INTR_SOURCE,
ETS_TG1_T0_INTR_SOURCE,
ETS_TG1_WDT_INTR_SOURCE,
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
ETS_APB_ADC_INTR_SOURCE,
ETS_PWM0_INTR_SOURCE,
ETS_PWM1_INTR_SOURCE,
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,
ETS_USB_OTG11_INTR_SOURCE,
ETS_ASRC_CHNL0_INTR_SOURCE,
ETS_ASRC_CHNL1_INTR_SOURCE,
ETS_ZERO_DET_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE,
ETS_DMA_IN_CH1_INTR_SOURCE,
ETS_DMA_IN_CH2_INTR_SOURCE,
ETS_DMA_IN_CH3_INTR_SOURCE,
ETS_DMA_IN_CH4_INTR_SOURCE,
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH2_INTR_SOURCE,
ETS_DMA_OUT_CH3_INTR_SOURCE,
ETS_DMA_OUT_CH4_INTR_SOURCE,
ETS_GPSPI2_INTR_SOURCE,
ETS_GPSPI3_INTR_SOURCE,
ETS_AES_INTR_SOURCE,
ETS_SHA_INTR_SOURCE,
ETS_ECC_INTR_SOURCE,
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
#ifdef __cplusplus
}
#endif

67
components/soc/esp32h4/include/soc/pmu_icg_mapping.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define PMU_ICG_APB_ENA_SEC 0
#define PMU_ICG_APB_ENA_GDMA 1
#define PMU_ICG_APB_ENA_SPI2 2
#define PMU_ICG_APB_ENA_INTMTX 3
#define PMU_ICG_APB_ENA_I2S 4
#define PMU_ICG_APB_ENA_MSPI 5
#define PMU_ICG_APB_ENA_UART0 6
#define PMU_ICG_APB_ENA_UART1 7
#define PMU_ICG_APB_ENA_UHCI 8
#define PMU_ICG_APB_ENA_SARADC 9
#define PMU_ICG_APB_ENA_TG0 11
#define PMU_ICG_APB_ENA_TG1 12
#define PMU_ICG_APB_ENA_I2C 13
#define PMU_ICG_APB_ENA_LEDC 14
#define PMU_ICG_APB_ENA_RMT 15
#define PMU_ICG_APB_ENA_SYSTIMER 16
#define PMU_ICG_APB_ENA_USB_DEVICE 17
#define PMU_ICG_APB_ENA_TWAI0 18
#define PMU_ICG_APB_ENA_TWAI1 19
#define PMU_ICG_APB_ENA_PCNT 20
#define PMU_ICG_APB_ENA_PWM 21
#define PMU_ICG_APB_ENA_SOC_ETM 22
#define PMU_ICG_APB_ENA_PARL 23
#define PMU_ICG_APB_ENA_REGDMA 24
#define PMU_ICG_APB_ENA_MEM_MONITOR 25
#define PMU_ICG_APB_ENA_IOMUX 26
#define PMU_ICG_APB_ENA_PVT_MONITOR 27
#define PMU_ICG_FUNC_ENA_GDMA 0
#define PMU_ICG_FUNC_ENA_SPI2 1
#define PMU_ICG_FUNC_ENA_I2S_RX 2
#define PMU_ICG_FUNC_ENA_UART0 3
#define PMU_ICG_FUNC_ENA_UART1 4
#define PMU_ICG_FUNC_ENA_UHCI 5
#define PMU_ICG_FUNC_ENA_USB_DEVICE 6
#define PMU_ICG_FUNC_ENA_I2S_TX 7
#define PMU_ICG_FUNC_ENA_REGDMA 8
#define PMU_ICG_FUNC_ENA_RETENTION 9
#define PMU_ICG_FUNC_ENA_MEM_MONITOR 10
#define PMU_ICG_FUNC_ENA_SDIO_SLAVE 11
#define PMU_ICG_FUNC_ENA_TSENS 12
#define PMU_ICG_FUNC_ENA_TG1 13
#define PMU_ICG_FUNC_ENA_TG0 14
#define PMU_ICG_FUNC_ENA_HPBUS 15
#define PMU_ICG_FUNC_ENA_SOC_ETM 16
#define PMU_ICG_FUNC_ENA_HPCORE 17
#define PMU_ICG_FUNC_ENA_SYSTIMER 18
#define PMU_ICG_FUNC_ENA_SEC 19
#define PMU_ICG_FUNC_ENA_SARADC 20
#define PMU_ICG_FUNC_ENA_RMT 21
#define PMU_ICG_FUNC_ENA_PWM 22
#define PMU_ICG_FUNC_ENA_PVT_MONITOR 23
#define PMU_ICG_FUNC_ENA_PARL_TX 24
#define PMU_ICG_FUNC_ENA_PARL_RX 25
#define PMU_ICG_FUNC_ENA_MSPI 26
#define PMU_ICG_FUNC_ENA_LEDC 27
#define PMU_ICG_FUNC_ENA_IOMUX 28
#define PMU_ICG_FUNC_ENA_I2C 29
#define PMU_ICG_FUNC_ENA_TWAI1 30
#define PMU_ICG_FUNC_ENA_TWAI0 31

79
components/soc/esp32h4/include/soc/reg_base.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define DR_REG_TRACE0_BASE 0x60000000
#define DR_REG_TRACE1_BASE 0x60001000
#define DR_REG_ASSIST_DEBUG_BASE 0x60002000
#define DR_REG_INTPRI_BASE 0x60005000
#define DR_REG_CACHE_BASE 0x60008000
#define DR_REG_GPSPI2_BASE 0x60010000
#define DR_REG_GPSPI3_BASE 0x60011000
#define DR_REG_UART0_BASE 0x60012000
#define DR_REG_UART1_BASE 0x60013000
#define DR_REG_UHCI0_BASE 0x60014000
#define DR_REG_I2C0_BASE 0x60015000
#define DR_REG_I2C1_BASE 0x60016000
#define DR_REG_I2S0_BASE 0x60017000
#define DR_REG_PARL_IO_BASE 0x60018000
#define DR_REG_MCPWM0_BASE 0x60019000
#define DR_REG_MCPWM1_BASE 0x6001A000
#define DR_REG_LEDC_BASE 0x6001B000
#define DR_REG_TWAIFD_BASE 0x6001C000
#define DR_REG_USB_SERIAL_JTAG_BASE 0x6001D000
#define DR_REG_RMT_BASE 0x6001E000
#define DR_REG_AHB_DMA_BASE 0x6001F000
#define DR_REG_PAU_BASE 0x60020000
#define DR_REG_SOC_ETM_BASE 0x60021000
#define DR_REG_APB_SARADC_BASE 0x60022000
#define DR_REG_SYSTIMER_BASE 0x60023000
#define DR_REG_MEM_MONITOR_BASE 0x60025000
#define DR_REG_PVT_BASE 0x60026000
#define DR_REG_PCNT_BASE 0x60027000
#define DR_REG_SAMPLE_RATE_CONVERTER_BASE 0x60028000
#define DR_REG_ZERO_DET_BASE 0x60029000
#define DR_REG_USB_OTG_FS_CORE0_BASE 0x60040000
#define DR_REG_USB_OTG_FS_CORE1_BASE 0x6007F000
#define DR_REG_USB_OTG_FS_PHY_BASE 0x60080000
#define DR_REG_TIMERG0_BASE 0x60090000
#define DR_REG_TIMERG1_BASE 0x60091000
#define DR_REG_IO_MUX_BASE 0x60092000
#define DR_REG_GPIO_BASE 0x60093000
#define DR_REG_GPIO_EXT_BASE 0x60093E00
#define DR_REG_PCR_BASE 0x60094000
#define DR_REG_SPIMEM0_BASE 0x60098000
#define DR_REG_SPIMEM1_BASE 0x60099000
#define DR_REG_INTMTX0_BASE 0x6009A000
#define DR_REG_INTMTX1_BASE 0x6009B000
#define DR_REG_HP_SYSTEM_BASE 0x6009C000
#define DR_REG_HP_APM_BASE 0x6009D000
#define DR_REG_CPU_APM_REG_BASE 0x6009E000
#define DR_REG_TEE_BASE 0x6009F000
#define DR_REG_KEYMNG_BASE 0x600A5000
#define DR_REG_AES_BASE 0x600A6000
#define DR_REG_SHA_BASE 0x600A7000
#define DR_REG_ECC_BASE 0x600A8000
#define DR_REG_HMAC_BASE 0x600A9000
#define DR_REG_ECDSA_BASE 0x600AA000
#define DR_REG_HUK_BASE 0x600B1000
#define DR_REG_LP_TEE_BASE 0x600B1400
#define DR_REG_EFUSE_BASE 0x600B1800
#define DR_REG_OTP_DEBUG_BASE 0x600B1C00
#define DR_REG_TRNG_BASE 0x600B2000
#define DR_REG_PMU_BASE 0x600B2400
#define DR_REG_LP_AON_BASE 0x600B2800
#define DR_REG_LP_ANA_PERI_BASE 0x600B2C00
#define DR_REG_LP_CLKRST_BASE 0x600B3000
#define DR_REG_LPPERI_BASE 0x600B3400
#define DR_REG_LP_IO_MUX_BASE 0x600B3800
#define DR_REG_LP_GPIO_BASE 0x600B3C00
#define DR_REG_LP_TIMER_BASE 0x600B5000
#define DR_REG_LP_WDT_BASE 0x600B5400
#define DR_REG_TOUCH_SENS_BASE 0x600B5800
#define DR_REG_TOUCH_AON_BASE 0x600B5C00
#define DR_REG_I2C_ANA_MST_BASE 0x600AF800 // TODO: [ESP32H4] IDF-12315 inherit from verify code, need check

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components/soc/esp32h4/include/soc/soc_etm_source.h Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define GPIO_EVT_CH0_RISE_EDGE 1
#define GPIO_EVT_CH1_RISE_EDGE 2
#define GPIO_EVT_CH2_RISE_EDGE 3
#define GPIO_EVT_CH3_RISE_EDGE 4
#define GPIO_EVT_CH4_RISE_EDGE 5
#define GPIO_EVT_CH5_RISE_EDGE 6
#define GPIO_EVT_CH6_RISE_EDGE 7
#define GPIO_EVT_CH7_RISE_EDGE 8
#define GPIO_EVT_CH0_FALL_EDGE 9
#define GPIO_EVT_CH1_FALL_EDGE 10
#define GPIO_EVT_CH2_FALL_EDGE 11
#define GPIO_EVT_CH3_FALL_EDGE 12
#define GPIO_EVT_CH4_FALL_EDGE 13
#define GPIO_EVT_CH5_FALL_EDGE 14
#define GPIO_EVT_CH6_FALL_EDGE 15
#define GPIO_EVT_CH7_FALL_EDGE 16
#define GPIO_EVT_CH0_ANY_EDGE 17
#define GPIO_EVT_CH1_ANY_EDGE 18
#define GPIO_EVT_CH2_ANY_EDGE 19
#define GPIO_EVT_CH3_ANY_EDGE 20
#define GPIO_EVT_CH4_ANY_EDGE 21
#define GPIO_EVT_CH5_ANY_EDGE 22
#define GPIO_EVT_CH6_ANY_EDGE 23
#define GPIO_EVT_CH7_ANY_EDGE 24
#define GPIO_EVT_ZERO_DET_POS0 25
#define GPIO_EVT_ZERO_DET_NEG0 26
#define LEDC_EVT_DUTY_CHNG_END_CH0 27
#define LEDC_EVT_DUTY_CHNG_END_CH1 28
#define LEDC_EVT_DUTY_CHNG_END_CH2 29
#define LEDC_EVT_DUTY_CHNG_END_CH3 30
#define LEDC_EVT_DUTY_CHNG_END_CH4 31
#define LEDC_EVT_DUTY_CHNG_END_CH5 32
#define LEDC_EVT_DUTY_CHNG_END_CH6 33
#define LEDC_EVT_DUTY_CHNG_END_CH7 34
#define LEDC_EVT_OVF_CNT_PLS_CH0 35
#define LEDC_EVT_OVF_CNT_PLS_CH1 36
#define LEDC_EVT_OVF_CNT_PLS_CH2 37
#define LEDC_EVT_OVF_CNT_PLS_CH3 38
#define LEDC_EVT_OVF_CNT_PLS_CH4 39
#define LEDC_EVT_OVF_CNT_PLS_CH5 40
#define LEDC_EVT_OVF_CNT_PLS_CH6 41
#define LEDC_EVT_OVF_CNT_PLS_CH7 42
#define LEDC_EVT_TIME_OVF_TIMER0 43
#define LEDC_EVT_TIME_OVF_TIMER1 44
#define LEDC_EVT_TIME_OVF_TIMER2 45
#define LEDC_EVT_TIME_OVF_TIMER3 46
#define LEDC_EVT_TIMER0_CMP 47
#define LEDC_EVT_TIMER1_CMP 48
#define LEDC_EVT_TIMER2_CMP 49
#define LEDC_EVT_TIMER3_CMP 50
#define TG0_EVT_CNT_CMP_TIMER0 51
#define TG1_EVT_CNT_CMP_TIMER0 52
#define SYSTIMER_EVT_CNT_CMP0 53
#define SYSTIMER_EVT_CNT_CMP1 54
#define SYSTIMER_EVT_CNT_CMP2 55
#define MCPWM0_EVT_TIMER0_STOP 56
#define MCPWM0_EVT_TIMER1_STOP 57
#define MCPWM0_EVT_TIMER2_STOP 58
#define MCPWM0_EVT_TIMER0_TEZ 59
#define MCPWM0_EVT_TIMER1_TEZ 60
#define MCPWM0_EVT_TIMER2_TEZ 61
#define MCPWM0_EVT_TIMER0_TEP 62
#define MCPWM0_EVT_TIMER1_TEP 63
#define MCPWM0_EVT_TIMER2_TEP 64
#define MCPWM0_EVT_OP0_TEA 65
#define MCPWM0_EVT_OP1_TEA 66
#define MCPWM0_EVT_OP2_TEA 67
#define MCPWM0_EVT_OP0_TEB 68
#define MCPWM0_EVT_OP1_TEB 69
#define MCPWM0_EVT_OP2_TEB 70
#define MCPWM0_EVT_F0 71
#define MCPWM0_EVT_F1 72
#define MCPWM0_EVT_F2 73
#define MCPWM0_EVT_F0_CLR 74
#define MCPWM0_EVT_F1_CLR 75
#define MCPWM0_EVT_F2_CLR 76
#define MCPWM0_EVT_TZ0_CBC 77
#define MCPWM0_EVT_TZ1_CBC 78
#define MCPWM0_EVT_TZ2_CBC 79
#define MCPWM0_EVT_TZ0_OST 80
#define MCPWM0_EVT_TZ1_OST 81
#define MCPWM0_EVT_TZ2_OST 82
#define MCPWM0_EVT_CAP0 83
#define MCPWM0_EVT_CAP1 84
#define MCPWM0_EVT_CAP2 85
#define MCPWM0_EVT_OP0_TEE1 86
#define MCPWM0_EVT_OP1_TEE1 87
#define MCPWM0_EVT_OP2_TEE1 88
#define MCPWM0_EVT_OP0_TEE2 89
#define MCPWM0_EVT_OP1_TEE2 90
#define MCPWM0_EVT_OP2_TEE2 91
#define MCPWM1_EVT_TIMER0_STOP 92
#define MCPWM1_EVT_TIMER1_STOP 93
#define MCPWM1_EVT_TIMER2_STOP 94
#define MCPWM1_EVT_TIMER0_TEZ 95
#define MCPWM1_EVT_TIMER1_TEZ 96
#define MCPWM1_EVT_TIMER2_TEZ 97
#define MCPWM1_EVT_TIMER0_TEP 98
#define MCPWM1_EVT_TIMER1_TEP 99
#define MCPWM1_EVT_TIMER2_TEP 100
#define MCPWM1_EVT_OP0_TEA 101
#define MCPWM1_EVT_OP1_TEA 102
#define MCPWM1_EVT_OP2_TEA 103
#define MCPWM1_EVT_OP0_TEB 104
#define MCPWM1_EVT_OP1_TEB 105
#define MCPWM1_EVT_OP2_TEB 106
#define MCPWM1_EVT_F0 107
#define MCPWM1_EVT_F1 108
#define MCPWM1_EVT_F2 109
#define MCPWM1_EVT_F0_CLR 110
#define MCPWM1_EVT_F1_CLR 111
#define MCPWM1_EVT_F2_CLR 112
#define MCPWM1_EVT_TZ0_CBC 113
#define MCPWM1_EVT_TZ1_CBC 114
#define MCPWM1_EVT_TZ2_CBC 115
#define MCPWM1_EVT_TZ0_OST 116
#define MCPWM1_EVT_TZ1_OST 117
#define MCPWM1_EVT_TZ2_OST 118
#define MCPWM1_EVT_CAP0 119
#define MCPWM1_EVT_CAP1 120
#define MCPWM1_EVT_CAP2 121
#define MCPWM1_EVT_OP0_TEE1 122
#define MCPWM1_EVT_OP1_TEE1 123
#define MCPWM1_EVT_OP2_TEE1 124
#define MCPWM1_EVT_OP0_TEE2 125
#define MCPWM1_EVT_OP1_TEE2 126
#define MCPWM1_EVT_OP2_TEE2 127
#define ADC_EVT_CONV_CMPLT0 128
#define ADC_EVT_EQ_ABOVE_THRESH0 129
#define ADC_EVT_EQ_ABOVE_THRESH1 130
#define ADC_EVT_EQ_BELOW_THRESH0 131
#define ADC_EVT_EQ_BELOW_THRESH1 132
#define ADC_EVT_RESULT_DONE0 133
#define ADC_EVT_STOPPED0 134
#define ADC_EVT_STARTED0 135
#define REGDMA_EVT_DONE0 136
#define REGDMA_EVT_DONE1 137
#define REGDMA_EVT_DONE2 138
#define REGDMA_EVT_DONE3 139
#define REGDMA_EVT_ERR0 140
#define REGDMA_EVT_ERR1 141
#define REGDMA_EVT_ERR2 142
#define REGDMA_EVT_ERR3 143
#define TMPSNSR_EVT_OVER_LIMIT 144
#define I2S0_EVT_RX_DONE 145
#define I2S0_EVT_TX_DONE 146
#define I2S0_EVT_X_WORDS_RECEIVED 147
#define I2S0_EVT_X_WORDS_SENT 148
#define ULP_EVT_ERR_INTR 149
#define ULP_EVT_HALT 150
#define ULP_EVT_START_INTR 151
#define RTC_EVT_TICK 152
#define RTC_EVT_OVF 153
#define RTC_EVT_CMP 154
#define GDMA_EVT_IN_DONE_CH0 155
#define GDMA_EVT_IN_DONE_CH1 156
#define GDMA_EVT_IN_DONE_CH2 157
#define GDMA_EVT_IN_DONE_CH3 158
#define GDMA_EVT_IN_DONE_CH4 159
#define GDMA_EVT_IN_SUC_EOF_CH0 160
#define GDMA_EVT_IN_SUC_EOF_CH1 161
#define GDMA_EVT_IN_SUC_EOF_CH2 162
#define GDMA_EVT_IN_SUC_EOF_CH3 163
#define GDMA_EVT_IN_SUC_EOF_CH4 164
#define GDMA_EVT_IN_FIFO_EMPTY_CH0 165
#define GDMA_EVT_IN_FIFO_EMPTY_CH1 166
#define GDMA_EVT_IN_FIFO_EMPTY_CH2 167
#define GDMA_EVT_IN_FIFO_EMPTY_CH3 168
#define GDMA_EVT_IN_FIFO_EMPTY_CH4 169
#define GDMA_EVT_IN_FIFO_FULL_CH0 170
#define GDMA_EVT_IN_FIFO_FULL_CH1 171
#define GDMA_EVT_IN_FIFO_FULL_CH2 172
#define GDMA_EVT_IN_FIFO_FULL_CH3 173
#define GDMA_EVT_IN_FIFO_FULL_CH4 174
#define GDMA_EVT_OUT_DONE_CH0 175
#define GDMA_EVT_OUT_DONE_CH1 176
#define GDMA_EVT_OUT_DONE_CH2 177
#define GDMA_EVT_OUT_DONE_CH3 178
#define GDMA_EVT_OUT_DONE_CH4 179
#define GDMA_EVT_OUT_EOF_CH0 180
#define GDMA_EVT_OUT_EOF_CH1 181
#define GDMA_EVT_OUT_EOF_CH2 182
#define GDMA_EVT_OUT_EOF_CH3 183
#define GDMA_EVT_OUT_EOF_CH4 184
#define GDMA_EVT_OUT_TOTAL_EOF_CH0 185
#define GDMA_EVT_OUT_TOTAL_EOF_CH1 186
#define GDMA_EVT_OUT_TOTAL_EOF_CH2 187
#define GDMA_EVT_OUT_TOTAL_EOF_CH3 188
#define GDMA_EVT_OUT_TOTAL_EOF_CH4 189
#define GDMA_EVT_OUT_FIFO_EMPTY_CH0 190
#define GDMA_EVT_OUT_FIFO_EMPTY_CH1 191
#define GDMA_EVT_OUT_FIFO_EMPTY_CH2 192
#define GDMA_EVT_OUT_FIFO_EMPTY_CH3 193
#define GDMA_EVT_OUT_FIFO_EMPTY_CH4 194
#define GDMA_EVT_OUT_FIFO_FULL_CH0 195
#define GDMA_EVT_OUT_FIFO_FULL_CH1 196
#define GDMA_EVT_OUT_FIFO_FULL_CH2 197
#define GDMA_EVT_OUT_FIFO_FULL_CH3 198
#define GDMA_EVT_OUT_FIFO_FULL_CH4 199
#define PMU_EVT_SLEEP_WEEKUP 200
#define MODEM_EVT_G0 201
#define MODEM_EVT_G1 202
#define MODEM_EVT_G2 203
#define MODEM_EVT_G3 204
#define ZERO_DET_EVT_CHANNEL_1_POS 205
#define ZERO_DET_EVT_CHANNEL_2_POS 206
#define ZERO_DET_EVT_CHANNEL_3_POS 207
#define ZERO_DET_EVT_CHANNEL_1_NEG 208
#define ZERO_DET_EVT_CHANNEL_2_NEG 209
#define ZERO_DET_EVT_CHANNEL_3_NEG 210
#define GPIO_TASK_CH0_SET 1
#define GPIO_TASK_CH1_SET 2
#define GPIO_TASK_CH2_SET 3
#define GPIO_TASK_CH3_SET 4
#define GPIO_TASK_CH4_SET 5
#define GPIO_TASK_CH5_SET 6
#define GPIO_TASK_CH6_SET 7
#define GPIO_TASK_CH7_SET 8
#define GPIO_TASK_CH0_CLEAR 9
#define GPIO_TASK_CH1_CLEAR 10
#define GPIO_TASK_CH2_CLEAR 11
#define GPIO_TASK_CH3_CLEAR 12
#define GPIO_TASK_CH4_CLEAR 13
#define GPIO_TASK_CH5_CLEAR 14
#define GPIO_TASK_CH6_CLEAR 15
#define GPIO_TASK_CH7_CLEAR 16
#define GPIO_TASK_CH0_TOGGLE 17
#define GPIO_TASK_CH1_TOGGLE 18
#define GPIO_TASK_CH2_TOGGLE 19
#define GPIO_TASK_CH3_TOGGLE 20
#define GPIO_TASK_CH4_TOGGLE 21
#define GPIO_TASK_CH5_TOGGLE 22
#define GPIO_TASK_CH6_TOGGLE 23
#define GPIO_TASK_CH7_TOGGLE 24
#define LEDC_TASK_TIMER0_RES_UPDATE 25
#define LEDC_TASK_TIMER1_RES_UPDATE 26
#define LEDC_TASK_TIMER2_RES_UPDATE 27
#define LEDC_TASK_TIMER3_RES_UPDATE 28
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH0 29
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH1 30
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH2 31
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH3 32
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH4 33
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH5 34
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH6 35
#define LEDC_TASK_DUTY_SCALE_UPDATE_CH7 36
#define LEDC_TASK_TIMER0_CAP 37
#define LEDC_TASK_TIMER1_CAP 38
#define LEDC_TASK_TIMER2_CAP 39
#define LEDC_TASK_TIMER3_CAP 40
#define LEDC_TASK_SIG_OUT_DIS_CH0 41
#define LEDC_TASK_SIG_OUT_DIS_CH1 42
#define LEDC_TASK_SIG_OUT_DIS_CH2 43
#define LEDC_TASK_SIG_OUT_DIS_CH3 44
#define LEDC_TASK_SIG_OUT_DIS_CH4 45
#define LEDC_TASK_SIG_OUT_DIS_CH5 46
#define LEDC_TASK_SIG_OUT_DIS_CH6 47
#define LEDC_TASK_SIG_OUT_DIS_CH7 48
#define LEDC_TASK_OVF_CNT_RST_CH0 49
#define LEDC_TASK_OVF_CNT_RST_CH1 50
#define LEDC_TASK_OVF_CNT_RST_CH2 51
#define LEDC_TASK_OVF_CNT_RST_CH3 52
#define LEDC_TASK_OVF_CNT_RST_CH4 53
#define LEDC_TASK_OVF_CNT_RST_CH5 54
#define LEDC_TASK_OVF_CNT_RST_CH6 55
#define LEDC_TASK_OVF_CNT_RST_CH7 56
#define LEDC_TASK_TIMER0_RST 57
#define LEDC_TASK_TIMER1_RST 58
#define LEDC_TASK_TIMER2_RST 59
#define LEDC_TASK_TIMER3_RST 60
#define LEDC_TASK_TIMER0_RESUME 61
#define LEDC_TASK_TIMER1_RESUME 62
#define LEDC_TASK_TIMER2_RESUME 63
#define LEDC_TASK_TIMER3_RESUME 64
#define LEDC_TASK_TIMER0_PAUSE 65
#define LEDC_TASK_TIMER1_PAUSE 66
#define LEDC_TASK_TIMER2_PAUSE 67
#define LEDC_TASK_TIMER3_PAUSE 68
#define LEDC_TASK_FADE_RESTART_CH0 69
#define LEDC_TASK_FADE_RESTART_CH1 70
#define LEDC_TASK_FADE_RESTART_CH2 71
#define LEDC_TASK_FADE_RESTART_CH3 72
#define LEDC_TASK_FADE_RESTART_CH4 73
#define LEDC_TASK_FADE_RESTART_CH5 74
#define LEDC_TASK_FADE_RESTART_CH6 75
#define LEDC_TASK_FADE_RESTART_CH7 76
#define LEDC_TASK_FADE_PAUSE_CH0 77
#define LEDC_TASK_FADE_PAUSE_CH1 78
#define LEDC_TASK_FADE_PAUSE_CH2 79
#define LEDC_TASK_FADE_PAUSE_CH3 80
#define LEDC_TASK_FADE_PAUSE_CH4 81
#define LEDC_TASK_FADE_PAUSE_CH5 82
#define LEDC_TASK_FADE_PAUSE_CH6 83
#define LEDC_TASK_FADE_PAUSE_CH7 84
#define LEDC_TASK_FADE_RESUME_CH0 85
#define LEDC_TASK_FADE_RESUME_CH1 86
#define LEDC_TASK_FADE_RESUME_CH2 87
#define LEDC_TASK_FADE_RESUME_CH3 88
#define LEDC_TASK_FADE_RESUME_CH4 89
#define LEDC_TASK_FADE_RESUME_CH5 90
#define LEDC_TASK_FADE_RESUME_CH6 91
#define LEDC_TASK_FADE_RESUME_CH7 92
#define TG0_TASK_CNT_START_TIMER0 93
#define TG0_TASK_ALARM_START_TIMER0 94
#define TG0_TASK_CNT_STOP_TIMER0 95
#define TG0_TASK_CNT_RELOAD_TIMER0 96
#define TG0_TASK_CNT_CAP_TIMER0 97
#define TG1_TASK_CNT_START_TIMER0 98
#define TG1_TASK_ALARM_START_TIMER0 99
#define TG1_TASK_CNT_STOP_TIMER0 100
#define TG1_TASK_CNT_RELOAD_TIMER0 101
#define TG1_TASK_CNT_CAP_TIMER0 102
#define MCPWM0_TASK_CMPR0_A_UP 103
#define MCPWM0_TASK_CMPR1_A_UP 104
#define MCPWM0_TASK_CMPR2_A_UP 105
#define MCPWM0_TASK_CMPR0_B_UP 106
#define MCPWM0_TASK_CMPR1_B_UP 107
#define MCPWM0_TASK_CMPR2_B_UP 108
#define MCPWM0_TASK_GEN_STOP 109
#define MCPWM0_TASK_TIMER0_SYN 110
#define MCPWM0_TASK_TIMER1_SYN 111
#define MCPWM0_TASK_TIMER2_SYN 112
#define MCPWM0_TASK_TIMER0_PERIOD_UP 113
#define MCPWM0_TASK_TIMER1_PERIOD_UP 114
#define MCPWM0_TASK_TIMER2_PERIOD_UP 115
#define MCPWM0_TASK_TZ0_OST 116
#define MCPWM0_TASK_TZ1_OST 117
#define MCPWM0_TASK_TZ2_OST 118
#define MCPWM0_TASK_CLR0_OST 119
#define MCPWM0_TASK_CLR1_OST 120
#define MCPWM0_TASK_CLR2_OST 121
#define MCPWM0_TASK_CAP0 122
#define MCPWM0_TASK_CAP1 123
#define MCPWM0_TASK_CAP2 124
#define MCPWM1_TASK_CMPR0_A_UP 125
#define MCPWM1_TASK_CMPR1_A_UP 126
#define MCPWM1_TASK_CMPR2_A_UP 127
#define MCPWM1_TASK_CMPR0_B_UP 128
#define MCPWM1_TASK_CMPR1_B_UP 129
#define MCPWM1_TASK_CMPR2_B_UP 130
#define MCPWM1_TASK_GEN_STOP 131
#define MCPWM1_TASK_TIMER0_SYN 132
#define MCPWM1_TASK_TIMER1_SYN 133
#define MCPWM1_TASK_TIMER2_SYN 134
#define MCPWM1_TASK_TIMER0_PERIOD_UP 135
#define MCPWM1_TASK_TIMER1_PERIOD_UP 136
#define MCPWM1_TASK_TIMER2_PERIOD_UP 137
#define MCPWM1_TASK_TZ0_OST 138
#define MCPWM1_TASK_TZ1_OST 139
#define MCPWM1_TASK_TZ2_OST 140
#define MCPWM1_TASK_CLR0_OST 141
#define MCPWM1_TASK_CLR1_OST 142
#define MCPWM1_TASK_CLR2_OST 143
#define MCPWM1_TASK_CAP0 144
#define MCPWM1_TASK_CAP1 145
#define MCPWM1_TASK_CAP2 146
#define ADC_TASK_SAMPLE0 147
#define ADC_TASK_SAMPLE1 148
#define ADC_TASK_START0 149
#define ADC_TASK_STOP0 150
#define REGDMA_TASK_START0 151
#define REGDMA_TASK_START1 152
#define REGDMA_TASK_START2 153
#define REGDMA_TASK_START3 154
#define TMPSNSR_TASK_START_SAMPLE 155
#define TMPSNSR_TASK_STOP_SAMPLE 156
#define I2S0_TASK_START_RX 157
#define I2S0_TASK_START_TX 158
#define I2S0_TASK_STOP_RX 159
#define I2S0_TASK_STOP_TX 160
#define I2S0_TASK_SYNC_CHECK 161
#define ULP_TASK_WAKEUP_CPU 162
#define ULP_TASK_INT_CPU 163
#define RTC_TASK_START 164
#define RTC_TASK_STOP 165
#define RTC_TASK_CLR 166
#define RTC_TASK_TRIGGERFLW 167
#define GDMA_TASK_IN_START_CH0 168
#define GDMA_TASK_IN_START_CH1 169
#define GDMA_TASK_IN_START_CH2 170
#define GDMA_TASK_IN_START_CH3 171
#define GDMA_TASK_IN_START_CH4 172
#define GDMA_TASK_OUT_START_CH0 173
#define GDMA_TASK_OUT_START_CH1 174
#define GDMA_TASK_OUT_START_CH2 175
#define GDMA_TASK_OUT_START_CH3 176
#define GDMA_TASK_OUT_START_CH4 177
#define PMU_TASK_SLEEP_REQ 178
#define MODEM_TASK_G0 179
#define MODEM_TASK_G1 180
#define MODEM_TASK_G2 181
#define MODEM_TASK_G3 182
#define ZERO_DET_TASK_START 183

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components/soc/esp32h4/interrupts.c
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
const char *const esp_isr_names[] = {
[0] = "WIFI_MAC",
[1] = "WIFI_MAC_NMI",
[2] = "WIFI_PWR",
[3] = "WIFI_BB",
[4] = "BT_MAC",
[5] = "BT_BB",
[6] = "BT_BB_NMI",
[7] = "LP_TIMER",
[8] = "COEX",
[9] = "BLE_TIMER",
[10] = "BLE_SEC",
[11] = "I2C_MST",
[12] = "ZB_MAC",
[13] = "MODEM_APB_TIMEOUT",
[14] = "BT_MAC_INT1",
[15] = "PMU",
[16] = "EFUSE",
[17] = "LP_RTC_TIMER",
[18] = "LP_RTC_BLE_TIMER",
[19] = "LP_WDT",
[20] = "TOUCH",
[21] = "HUK",
[22] = "CPU_FROM_CPU_0",
[23] = "CPU_FROM_CPU_1",
[24] = "CPU_FROM_CPU_2",
[25] = "CPU_FROM_CPU_3",
[26] = "BUS_MONITOR",
[27] = "CORE0_TRACE",
[28] = "CORE1_TRACE",
[29] = "CACHE",
[30] = "CPU_PERI_TIMEOUT",
[31] = "GPIO_INTERRUPT_PRO",
[32] = "GPIO_INTERRUPT_2",
[33] = "PAU",
[34] = "HP_PERI_TIMEOUT",
[35] = "HP_APM_M0",
[36] = "HP_APM_M1",
[37] = "HP_APM_M2",
[38] = "HP_APM_M3",
[39] = "HP_APM_M4",
[40] = "CPU_APM_M0",
[41] = "CPU_APM_M1",
[42] = "CPU_APM_M2",
[43] = "CPU_APM_M3",
[44] = "MSPI",
[45] = "I2S",
[46] = "UHCI0",
[47] = "UART0",
[48] = "UART1",
[49] = "LEDC",
[50] = "TWAI0",
[51] = "TWAI0_TIMER",
[52] = "USB_SERIAL_JTAG",
[53] = "RMT",
[54] = "I2C_EXT0",
[55] = "I2C_EXT1",
[56] = "TG0_T0",
[57] = "TG0_WDT",
[58] = "TG1_T0",
[59] = "TG1_WDT",
[60] = "SYSTIMER_TARGET0",
[61] = "SYSTIMER_TARGET1",
[62] = "SYSTIMER_TARGET2",
[63] = "APB_ADC",
[64] = "PWM0",
[65] = "PWM1",
[66] = "PCNT",
[67] = "PARL_IO_TX",
[68] = "PARL_IO_RX",
[69] = "USB_OTG11",
[70] = "ASRC_CHNL0",
[71] = "ASRC_CHNL1",
[72] = "ZERO_DET",
[73] = "DMA_IN_CH0",
[74] = "DMA_IN_CH1",
[75] = "DMA_IN_CH2",
[76] = "DMA_IN_CH3",
[77] = "DMA_IN_CH4",
[78] = "DMA_OUT_CH0",
[79] = "DMA_OUT_CH1",
[80] = "DMA_OUT_CH2",
[81] = "DMA_OUT_CH3",
[82] = "DMA_OUT_CH4",
[83] = "GPSPI2",
[84] = "GPSPI3",
[85] = "AES",
[86] = "SHA",
[87] = "ECC",
[88] = "ECDSA",
[89] = "KM",
};

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components/soc/esp32h4/ld/esp32h4.peripherals.ld Normal file
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
PROVIDE ( TRACE0 = 0x60000000 );
PROVIDE ( TRACE1 = 0x60001000 );
PROVIDE ( ASSIST_DEBUG = 0x60002000 );
PROVIDE ( INTPRI = 0x60005000 );
PROVIDE ( CACHE = 0x60008000 );
PROVIDE ( GPSPI2 = 0x60010000 );
PROVIDE ( GPSPI3 = 0x60011000 );
PROVIDE ( UART0 = 0x60012000 );
PROVIDE ( UART1 = 0x60013000 );
PROVIDE ( UHCI0 = 0x60014000 );
PROVIDE ( I2C0 = 0x60015000 );
PROVIDE ( I2C1 = 0x60016000 );
PROVIDE ( I2S0 = 0x60017000 );
PROVIDE ( PARL_IO = 0x60018000 );
PROVIDE ( MCPWM0 = 0x60019000 );
PROVIDE ( MCPWM1 = 0x6001A000 );
PROVIDE ( LEDC = 0x6001B000 );
PROVIDE ( TWAI0 = 0x6001C000 );
PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 );
PROVIDE ( RMT = 0x6001E000 );
PROVIDE ( GDMA = 0x6001F000 );
PROVIDE ( PAU = 0x60020000 );
PROVIDE ( SOC_ETM = 0x60021000 );
PROVIDE ( ADC = 0x60022000 );
PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( PSRAM_ACS_MONITOR = 0x60024000 ); /* TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */
PROVIDE ( MEM_MONITOR = 0x60025000 );
PROVIDE ( PVT = 0x60026000 );
PROVIDE ( PCNT = 0x60027000 );
PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 );
PROVIDE ( ZERO_DET = 0x60029000 );
PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 );
PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 );
PROVIDE ( USB_OTG_FS_PHY = 0x60080000 );
PROVIDE ( TIMERG0 = 0x60090000 );
PROVIDE ( TIMERG1 = 0x60091000 );
PROVIDE ( IO_MUX = 0x60092000 );
PROVIDE ( GPIO = 0x60093000 );
PROVIDE ( GPIO_EXT = 0x60093E00 );
PROVIDE ( PCR = 0x60094000 );
PROVIDE ( SPIMEM0 = 0x60098000 );
PROVIDE ( SPIMEM1 = 0x60099000 );
PROVIDE ( INTMTX0 = 0x6009A000 );
PROVIDE ( INTMTX1 = 0x6009B000 );
PROVIDE ( HP_SYSTEM = 0x6009C000 );
PROVIDE ( HP_APM = 0x6009D000 );
PROVIDE ( CPU_APM_REG = 0x6009E000 );
PROVIDE ( TEE = 0x6009F000 );
PROVIDE ( KEYMNG = 0x600A5000 );
PROVIDE ( AES = 0x600A6000 );
PROVIDE ( SHA = 0x600A7000 );
PROVIDE ( ECC = 0x600A8000 );
PROVIDE ( HMAC = 0x600A9000 );
PROVIDE ( ECDSA = 0x600AA000 );
PROVIDE ( HUK = 0x600B1000 );
PROVIDE ( LP_TEE = 0x600B1400 );
PROVIDE ( EFUSE = 0x600B1800 );
PROVIDE ( OTP_DEBUG = 0x600B1C00 );
PROVIDE ( TRNG = 0x600B2000 );
PROVIDE ( PMU = 0x600B2400 );
PROVIDE ( LP_AON = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_CLKRST = 0x600B3000 );
PROVIDE ( LPPERI = 0x600B3400 );
PROVIDE ( LP_IO_MUX = 0x600B3800 );
PROVIDE ( LP_GPIO = 0x600B3C00 );
PROVIDE ( LP_TIMER = 0x600B5000 );
PROVIDE ( LP_WDT = 0x600B5400 );
PROVIDE ( TOUCH_SENS = 0x600B5800 );
PROVIDE ( TOUCH_AON = 0x600B5C00 );
PROVIDE ( LP_UART = 0x600B1400 ); /* TODO: IDF-12445 [ESP32H4] inherit from verify code, need remove */

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components/soc/esp32h4/register/soc/aes_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** AES_KEY_0_REG register
* AES key data register 0
*/
#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_1_REG register
* AES key data register 1
*/
#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_2_REG register
* AES key data register 2
*/
#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_3_REG register
* AES key data register 3
*/
#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_4_REG register
* AES key data register 4
*/
#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_5_REG register
* AES key data register 5
*/
#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_6_REG register
* AES key data register 6
*/
#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_KEY_7_REG register
* AES key data register 7
*/
#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
#define AES_KEY_0 0xFFFFFFFFU
#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
#define AES_KEY_0_V 0xFFFFFFFFU
#define AES_KEY_0_S 0
/** AES_TEXT_IN_0_REG register
* Source text data register 0
*/
#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_1_REG register
* Source text data register 1
*/
#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_2_REG register
* Source text data register 2
*/
#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_IN_3_REG register
* Source text data register 3
*/
#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
#define AES_TEXT_IN_0 0xFFFFFFFFU
#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
#define AES_TEXT_IN_0_V 0xFFFFFFFFU
#define AES_TEXT_IN_0_S 0
/** AES_TEXT_OUT_0_REG register
* Result text data register 0
*/
#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_1_REG register
* Result text data register 1
*/
#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_2_REG register
* Result text data register 2
*/
#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_TEXT_OUT_3_REG register
* Result text data register 3
*/
#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
#define AES_TEXT_OUT_0 0xFFFFFFFFU
#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
#define AES_TEXT_OUT_0_S 0
/** AES_MODE_REG register
* Defines key length and encryption / decryption
*/
#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
#define AES_MODE 0x00000007U
#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
#define AES_MODE_V 0x00000007U
#define AES_MODE_S 0
/** AES_TRIGGER_REG register
* Operation start controlling register
*/
#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
#define AES_TRIGGER (BIT(0))
#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
#define AES_TRIGGER_V 0x00000001U
#define AES_TRIGGER_S 0
/** AES_STATE_REG register
* Operation status register
*/
#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
/** AES_STATE : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
#define AES_STATE 0x00000003U
#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
#define AES_STATE_V 0x00000003U
#define AES_STATE_S 0
/** AES_IV_MEM register
* The memory that stores initialization vector
*/
#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
#define AES_IV_MEM_SIZE_BYTES 16
/** AES_H_MEM register
* The memory that stores GCM hash subkey
*/
#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
#define AES_H_MEM_SIZE_BYTES 16
/** AES_J0_MEM register
* The memory that stores J0
*/
#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
#define AES_J0_MEM_SIZE_BYTES 16
/** AES_T0_MEM register
* The memory that stores T0
*/
#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
#define AES_T0_MEM_SIZE_BYTES 16
/** AES_DMA_ENABLE_REG register
* Selects the working mode of the AES accelerator
*/
#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
#define AES_DMA_ENABLE (BIT(0))
#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
#define AES_DMA_ENABLE_V 0x00000001U
#define AES_DMA_ENABLE_S 0
/** AES_BLOCK_MODE_REG register
* Defines the block cipher mode
*/
#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
#define AES_BLOCK_MODE 0x00000007U
#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
#define AES_BLOCK_MODE_V 0x00000007U
#define AES_BLOCK_MODE_S 0
/** AES_BLOCK_NUM_REG register
* Block number configuration register
*/
#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
#define AES_BLOCK_NUM 0xFFFFFFFFU
#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
#define AES_BLOCK_NUM_V 0xFFFFFFFFU
#define AES_BLOCK_NUM_S 0
/** AES_INC_SEL_REG register
* Standard incrementing function register
*/
#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
#define AES_INC_SEL (BIT(0))
#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
#define AES_INC_SEL_V 0x00000001U
#define AES_INC_SEL_S 0
/** AES_INT_CLEAR_REG register
* DMA-AES interrupt clear register
*/
#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
#define AES_INT_CLEAR (BIT(0))
#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
#define AES_INT_CLEAR_V 0x00000001U
#define AES_INT_CLEAR_S 0
/** AES_INT_ENA_REG register
* DMA-AES interrupt enable register
*/
#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
#define AES_INT_ENA (BIT(0))
#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
#define AES_INT_ENA_V 0x00000001U
#define AES_INT_ENA_S 0
/** AES_DATE_REG register
* AES version control register
*/
#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
* This bits stores the version information of AES.
*/
#define AES_DATE 0x0FFFFFFFU
#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
#define AES_DATE_V 0x0FFFFFFFU
#define AES_DATE_S 0
/** AES_DMA_EXIT_REG register
* Operation exit controlling register
*/
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
#define AES_DMA_EXIT (BIT(0))
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
#define AES_DMA_EXIT_V 0x00000001U
#define AES_DMA_EXIT_S 0
/** AES_RX_RESET_REG register
* AES-DMA reset rx-fifo register
*/
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
#define AES_RX_RESET (BIT(0))
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
#define AES_RX_RESET_V 0x00000001U
#define AES_RX_RESET_S 0
/** AES_TX_RESET_REG register
* AES-DMA reset tx-fifo register
*/
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
#define AES_TX_RESET (BIT(0))
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
#define AES_TX_RESET_V 0x00000001U
#define AES_TX_RESET_S 0
/** AES_PSEUDO_REG register
* AES PSEUDO function configure register
*/
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
#define AES_PSEUDO_EN (BIT(0))
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
#define AES_PSEUDO_EN_V 0x00000001U
#define AES_PSEUDO_EN_S 0
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
#define AES_PSEUDO_BASE 0x0000000FU
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
#define AES_PSEUDO_BASE_V 0x0000000FU
#define AES_PSEUDO_BASE_S 1
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
#define AES_PSEUDO_INC 0x00000003U
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
#define AES_PSEUDO_INC_V 0x00000003U
#define AES_PSEUDO_INC_S 5
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
#define AES_PSEUDO_RNG_CNT 0x00000007U
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
#define AES_PSEUDO_RNG_CNT_S 7
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Key Registers */
/** Type of key_n register
* AES key data register n
*/
typedef union {
struct {
/** key_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores key_0 that is a part of key material.
*/
uint32_t key_0:32;
};
uint32_t val;
} aes_key_n_reg_t;
/** Group: TEXT_IN Registers */
/** Type of text_in_n register
* Source text data register n
*/
typedef union {
struct {
/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_in_0 that is a part of source text material.
*/
uint32_t text_in_0:32;
};
uint32_t val;
} aes_text_in_n_reg_t;
/** Group: TEXT_OUT Registers */
/** Type of text_out_n register
* Result text data register n
*/
typedef union {
struct {
/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
* This bits stores text_out_0 that is a part of result text material.
*/
uint32_t text_out_0:32;
};
uint32_t val;
} aes_text_out_n_reg_t;
/** Group: Control / Configuration Registers */
/** Type of mode register
* Defines key length and encryption / decryption
*/
typedef union {
struct {
/** mode : R/W; bitpos: [2:0]; default: 0;
* Configures the key length and encryption / decryption of the AES accelerator.
* 0: AES-128 encryption
* 1: AES-192 encryption
* 2: AES-256 encryption
* 3: Reserved
* 4: AES-128 decryption
* 5: AES-192 decryption
* 6: AES-256 decryption
* 7: Reserved
*/
uint32_t mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_mode_reg_t;
/** Type of trigger register
* Operation start controlling register
*/
typedef union {
struct {
/** trigger : WT; bitpos: [0]; default: 0;
* Configures whether or not to start AES operation.
* 0: No effect
* 1: Start
*/
uint32_t trigger:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_trigger_reg_t;
/** Type of dma_enable register
* Selects the working mode of the AES accelerator
*/
typedef union {
struct {
/** dma_enable : R/W; bitpos: [0]; default: 0;
* Configures the working mode of the AES accelerator.
* 0: Typical AES
* 1: DMA-AES
*/
uint32_t dma_enable:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_enable_reg_t;
/** Type of block_mode register
* Defines the block cipher mode
*/
typedef union {
struct {
/** block_mode : R/W; bitpos: [2:0]; default: 0;
* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
* working mode.
* 0: ECB (Electronic Code Block)
* 1: CBC (Cipher Block Chaining)
* 2: OFB (Output FeedBack)
* 3: CTR (Counter)
* 4: CFB8 (8-bit Cipher FeedBack)
* 5: CFB128 (128-bit Cipher FeedBack)
* 6: GCM
* 7: Reserved
*/
uint32_t block_mode:3;
uint32_t reserved_3:29;
};
uint32_t val;
} aes_block_mode_reg_t;
/** Type of block_num register
* Block number configuration register
*/
typedef union {
struct {
/** block_num : R/W; bitpos: [31:0]; default: 0;
* Represents the Block Number of plaintext or ciphertext when the AES accelerator
* operates under the DMA-AES working mode. For details, see Section . "
*/
uint32_t block_num:32;
};
uint32_t val;
} aes_block_num_reg_t;
/** Type of inc_sel register
* Standard incrementing function register
*/
typedef union {
struct {
/** inc_sel : R/W; bitpos: [0]; default: 0;
* Configures the Standard Incrementing Function for CTR block operation.
* 0: INC_32
* 1: INC_128
*/
uint32_t inc_sel:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_inc_sel_reg_t;
/** Type of dma_exit register
* Operation exit controlling register
*/
typedef union {
struct {
/** dma_exit : WT; bitpos: [0]; default: 0;
* Configures whether or not to exit AES operation.
* 0: No effect
* 1: Exit
* Only valid for DMA-AES operation.
*/
uint32_t dma_exit:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_dma_exit_reg_t;
/** Type of rx_reset register
* AES-DMA reset rx-fifo register
*/
typedef union {
struct {
/** rx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset rx_fifo under dma_aes working mode.
*/
uint32_t rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_rx_reset_reg_t;
/** Type of tx_reset register
* AES-DMA reset tx-fifo register
*/
typedef union {
struct {
/** tx_reset : WT; bitpos: [0]; default: 0;
* Set this bit to reset tx_fifo under dma_aes working mode.
*/
uint32_t tx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_tx_reset_reg_t;
/** Group: Configuration register */
/** Type of pseudo register
* AES PSEUDO function configure register
*/
typedef union {
struct {
/** pseudo_en : R/W; bitpos: [0]; default: 0;
* This bit decides whether the pseudo round function is enable or not.
*/
uint32_t pseudo_en:1;
/** pseudo_base : R/W; bitpos: [4:1]; default: 2;
* Those bits decides the basic number of pseudo round number.
*/
uint32_t pseudo_base:4;
/** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
* Those bits decides the increment number of pseudo round number
*/
uint32_t pseudo_inc:2;
/** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
* Those bits decides the update frequency of the pseudo-key.
*/
uint32_t pseudo_rng_cnt:3;
uint32_t reserved_10:22;
};
uint32_t val;
} aes_pseudo_reg_t;
/** Group: Status Register */
/** Type of state register
* Operation status register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* Represents the working status of the AES accelerator.
* In Typical AES working mode:
* 0: IDLE
* 1: WORK
* 2: No effect
* 3: No effect
* In DMA-AES working mode:
* 0: IDLE
* 1: WORK
* 2: DONE
* 3: No effect
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} aes_state_reg_t;
/** Group: memory type */
/** Group: Interrupt Registers */
/** Type of int_clear register
* DMA-AES interrupt clear register
*/
typedef union {
struct {
/** int_clear : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear AES interrupt.
* 0: No effect
* 1: Clear
*/
uint32_t int_clear:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_clear_reg_t;
/** Type of int_ena register
* DMA-AES interrupt enable register
*/
typedef union {
struct {
/** int_ena : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable AES interrupt.
* 0: Disable
* 1: Enable
*/
uint32_t int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} aes_int_ena_reg_t;
/** Group: Version control register */
/** Type of date register
* AES version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 36774000;
* This bits stores the version information of AES.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} aes_date_reg_t;
typedef struct {
volatile aes_key_n_reg_t key_n[8];
volatile aes_text_in_n_reg_t text_in_n[4];
volatile aes_text_out_n_reg_t text_out_n[4];
volatile aes_mode_reg_t mode;
uint32_t reserved_044;
volatile aes_trigger_reg_t trigger;
volatile aes_state_reg_t state;
volatile uint32_t iv[4];
volatile uint32_t h[4];
volatile uint32_t j0[4];
volatile uint32_t t0[4];
volatile aes_dma_enable_reg_t dma_enable;
volatile aes_block_mode_reg_t block_mode;
volatile aes_block_num_reg_t block_num;
volatile aes_inc_sel_reg_t inc_sel;
uint32_t reserved_0a0[3];
volatile aes_int_clear_reg_t int_clear;
volatile aes_int_ena_reg_t int_ena;
volatile aes_date_reg_t date;
volatile aes_dma_exit_reg_t dma_exit;
uint32_t reserved_0bc;
volatile aes_rx_reset_reg_t rx_reset;
volatile aes_tx_reset_reg_t tx_reset;
uint32_t reserved_0c8[2];
volatile aes_pseudo_reg_t pseudo;
} aes_dev_t;
extern aes_dev_t AES;
#ifndef __cplusplus
_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECC_MULT_INT_RAW_REG register
* ECC raw interrupt status register
*/
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_BASE + 0xc)
/** ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (ECC_MULT_CALC_DONE_INT_RAW_V << ECC_MULT_CALC_DONE_INT_RAW_S)
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
/** ECC_MULT_INT_ST_REG register
* ECC masked interrupt status register
*/
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_BASE + 0x10)
/** ECC_MULT_CALC_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (ECC_MULT_CALC_DONE_INT_ST_V << ECC_MULT_CALC_DONE_INT_ST_S)
#define ECC_MULT_CALC_DONE_INT_ST_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ST_S 0
/** ECC_MULT_INT_ENA_REG register
* ECC interrupt enable register
*/
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_BASE + 0x14)
/** ECC_MULT_CALC_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (ECC_MULT_CALC_DONE_INT_ENA_V << ECC_MULT_CALC_DONE_INT_ENA_S)
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
/** ECC_MULT_INT_CLR_REG register
* ECC interrupt clear register
*/
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_BASE + 0x18)
/** ECC_MULT_CALC_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (ECC_MULT_CALC_DONE_INT_CLR_V << ECC_MULT_CALC_DONE_INT_CLR_S)
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x00000001U
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
/** ECC_MULT_CONF_REG register
* ECC configuration register
*/
#define ECC_MULT_CONF_REG (DR_REG_ECC_BASE + 0x1c)
/** ECC_MULT_START : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (ECC_MULT_START_V << ECC_MULT_START_S)
#define ECC_MULT_START_V 0x00000001U
#define ECC_MULT_START_S 0
/** ECC_MULT_RESET : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (ECC_MULT_RESET_V << ECC_MULT_RESET_S)
#define ECC_MULT_RESET_V 0x00000001U
#define ECC_MULT_RESET_S 1
/** ECC_MULT_KEY_LENGTH : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: SM2.
*/
#define ECC_MULT_KEY_LENGTH 0x00000003U
#define ECC_MULT_KEY_LENGTH_M (ECC_MULT_KEY_LENGTH_V << ECC_MULT_KEY_LENGTH_S)
#define ECC_MULT_KEY_LENGTH_V 0x00000003U
#define ECC_MULT_KEY_LENGTH_S 2
/** ECC_MULT_MOD_BASE : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
#define ECC_MULT_MOD_BASE (BIT(4))
#define ECC_MULT_MOD_BASE_M (ECC_MULT_MOD_BASE_V << ECC_MULT_MOD_BASE_S)
#define ECC_MULT_MOD_BASE_V 0x00000001U
#define ECC_MULT_MOD_BASE_S 4
/** ECC_MULT_WORK_MODE : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
#define ECC_MULT_WORK_MODE 0x0000000FU
#define ECC_MULT_WORK_MODE_M (ECC_MULT_WORK_MODE_V << ECC_MULT_WORK_MODE_S)
#define ECC_MULT_WORK_MODE_V 0x0000000FU
#define ECC_MULT_WORK_MODE_S 5
/** ECC_MULT_SECURITY_MODE : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
#define ECC_MULT_SECURITY_MODE (BIT(9))
#define ECC_MULT_SECURITY_MODE_M (ECC_MULT_SECURITY_MODE_V << ECC_MULT_SECURITY_MODE_S)
#define ECC_MULT_SECURITY_MODE_V 0x00000001U
#define ECC_MULT_SECURITY_MODE_S 9
/** ECC_MULT_VERIFICATION_RESULT : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(29))
#define ECC_MULT_VERIFICATION_RESULT_M (ECC_MULT_VERIFICATION_RESULT_V << ECC_MULT_VERIFICATION_RESULT_S)
#define ECC_MULT_VERIFICATION_RESULT_V 0x00000001U
#define ECC_MULT_VERIFICATION_RESULT_S 29
/** ECC_MULT_CLK_EN : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_CLK_EN (BIT(30))
#define ECC_MULT_CLK_EN_M (ECC_MULT_CLK_EN_V << ECC_MULT_CLK_EN_S)
#define ECC_MULT_CLK_EN_V 0x00000001U
#define ECC_MULT_CLK_EN_S 30
/** ECC_MULT_MEM_CLOCK_GATE_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON (BIT(31))
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_M (ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V << ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S)
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_V 0x00000001U
#define ECC_MULT_MEM_CLOCK_GATE_FORCE_ON_S 31
/** ECC_MULT_DATE_REG register
* Version control register
*/
#define ECC_MULT_DATE_REG (DR_REG_ECC_BASE + 0xfc)
/** ECC_MULT_DATE : R/W; bitpos: [27:0]; default: 37781792;
* ECC mult version control register
*/
#define ECC_MULT_DATE 0x0FFFFFFFU
#define ECC_MULT_DATE_M (ECC_MULT_DATE_V << ECC_MULT_DATE_S)
#define ECC_MULT_DATE_V 0x0FFFFFFFU
#define ECC_MULT_DATE_S 0
/** ECC_MULT_K_MEM register
* The memory that stores k.
*/
#define ECC_MULT_K_MEM (DR_REG_ECC_BASE + 0x100)
#define ECC_MULT_K_MEM_SIZE_BYTES 48
/** ECC_MULT_PX_MEM register
* The memory that stores Px.
*/
#define ECC_MULT_PX_MEM (DR_REG_ECC_BASE + 0x130)
#define ECC_MULT_PX_MEM_SIZE_BYTES 48
/** ECC_MULT_PY_MEM register
* The memory that stores Py.
*/
#define ECC_MULT_PY_MEM (DR_REG_ECC_BASE + 0x160)
#define ECC_MULT_PY_MEM_SIZE_BYTES 48
/** ECC_MULT_QX_MEM register
* The memory that stores Qx.
*/
#define ECC_MULT_QX_MEM (DR_REG_ECC_BASE + 0x190)
#define ECC_MULT_QX_MEM_SIZE_BYTES 48
/** ECC_MULT_QY_MEM register
* The memory that stores Qy.
*/
#define ECC_MULT_QY_MEM (DR_REG_ECC_BASE + 0x1c0)
#define ECC_MULT_QY_MEM_SIZE_BYTES 48
/** ECC_MULT_QZ_MEM register
* The memory that stores Qz.
*/
#define ECC_MULT_QZ_MEM (DR_REG_ECC_BASE + 0x1f0)
#define ECC_MULT_QZ_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Interrupt registers */
/** Type of mult_int_raw register
* ECC raw interrupt status register
*/
typedef union {
struct {
/** mult_calc_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_raw:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_raw_reg_t;
/** Type of mult_int_st register
* ECC masked interrupt status register
*/
typedef union {
struct {
/** mult_calc_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status of the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_st_reg_t;
/** Type of mult_int_ena register
* ECC interrupt enable register
*/
typedef union {
struct {
/** mult_calc_done_int_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_ena_reg_t;
/** Type of mult_int_clr register
* ECC interrupt clear register
*/
typedef union {
struct {
/** mult_calc_done_int_clr : WT; bitpos: [0]; default: 0;
* Write 1 to clear the ECC_CALC_DONE_INT interrupt.
*/
uint32_t mult_calc_done_int_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecc_mult_int_clr_reg_t;
/** Group: RX Control and configuration registers */
/** Type of mult_conf register
* ECC configuration register
*/
typedef union {
struct {
/** mult_start : R/W/SC; bitpos: [0]; default: 0;
* Configures whether to start calculation of ECC Accelerator. This bit will be
* self-cleared after the calculation is done.
* 0: No effect
* 1: Start calculation of ECC Accelerator
*/
uint32_t mult_start:1;
/** mult_reset : WT; bitpos: [1]; default: 0;
* Configures whether to reset ECC Accelerator.
* 0: No effect
* 1: Reset
*/
uint32_t mult_reset:1;
/** mult_key_length : R/W; bitpos: [3:2]; default: 0;
* Configures the key length mode bit of ECC Accelerator.
* 0: P-192
* 1: P-256
* 2: P-384
* 3: SM2.
*/
uint32_t mult_key_length:2;
/** mult_mod_base : R/W; bitpos: [4]; default: 0;
* Configures the mod base of mod operation, only valid in work_mode 8-11.
* 0: n(order of curve)
* 1: p(mod base of curve)
*/
uint32_t mult_mod_base:1;
/** mult_work_mode : R/W; bitpos: [8:5]; default: 0;
* Configures the work mode of ECC Accelerator.
* 0: Point Multi mode
* 1: Reserved
* 2: Point Verif mode
* 3: Point Verif + Multi mode
* 4: Jacobian Point Multi mode
* 5: Reserved
* 6: Jacobian Point Verif mode
* 7: Point Verif + Jacobian Point Multi mode
* 8: Mod Add mode
* 9. Mod Sub mode
* 10: Mod Multi mode
* 11: Mod Div mode
*/
uint32_t mult_work_mode:4;
/** mult_security_mode : R/W; bitpos: [9]; default: 0;
* Configures the security mode of ECC Accelerator.
* 0: no secure function enabled.
* 1: enable constant-time calculation in all point multiplication modes.
*/
uint32_t mult_security_mode:1;
uint32_t reserved_10:19;
/** mult_verification_result : RO/SS; bitpos: [29]; default: 0;
* Represents the verification result of ECC Accelerator, valid only when calculation
* is done.
*/
uint32_t mult_verification_result:1;
/** mult_clk_en : R/W; bitpos: [30]; default: 0;
* Configures whether to force on register clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mult_clk_en:1;
/** mult_mem_clock_gate_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether to force on ECC memory clock gate.
* 0: No effect
* 1: Force on
*/
uint32_t mult_mem_clock_gate_force_on:1;
};
uint32_t val;
} ecc_mult_conf_reg_t;
/** Group: Version register */
/** Type of mult_date register
* Version control register
*/
typedef union {
struct {
/** mult_date : R/W; bitpos: [27:0]; default: 37781792;
* ECC mult version control register
*/
uint32_t mult_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecc_mult_date_reg_t;
typedef struct {
uint32_t reserved_000[3];
volatile ecc_mult_int_raw_reg_t mult_int_raw;
volatile ecc_mult_int_st_reg_t mult_int_st;
volatile ecc_mult_int_ena_reg_t mult_int_ena;
volatile ecc_mult_int_clr_reg_t mult_int_clr;
volatile ecc_mult_conf_reg_t mult_conf;
uint32_t reserved_020[55];
volatile ecc_mult_date_reg_t mult_date;
volatile uint32_t mult_k[12];
volatile uint32_t mult_px[12];
volatile uint32_t mult_py[12];
volatile uint32_t mult_qx[12];
volatile uint32_t mult_qy[12];
volatile uint32_t mult_qz[12];
} ecc_dev_t;
extern ecc_dev_t ECC;
#ifndef __cplusplus
_Static_assert(sizeof(ecc_dev_t) == 0x220, "Invalid size of ecc_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** ECDSA_CONF_REG register
* ECDSA configure register
*/
#define ECDSA_CONF_REG (DR_REG_ECDSA_BASE + 0x4)
/** ECDSA_WORK_MODE : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
#define ECDSA_WORK_MODE 0x00000003U
#define ECDSA_WORK_MODE_M (ECDSA_WORK_MODE_V << ECDSA_WORK_MODE_S)
#define ECDSA_WORK_MODE_V 0x00000003U
#define ECDSA_WORK_MODE_S 0
/** ECDSA_ECC_CURVE : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2.
*/
#define ECDSA_ECC_CURVE 0x00000003U
#define ECDSA_ECC_CURVE_M (ECDSA_ECC_CURVE_V << ECDSA_ECC_CURVE_S)
#define ECDSA_ECC_CURVE_V 0x00000003U
#define ECDSA_ECC_CURVE_S 2
/** ECDSA_SOFTWARE_SET_K : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
#define ECDSA_SOFTWARE_SET_K (BIT(4))
#define ECDSA_SOFTWARE_SET_K_M (ECDSA_SOFTWARE_SET_K_V << ECDSA_SOFTWARE_SET_K_S)
#define ECDSA_SOFTWARE_SET_K_V 0x00000001U
#define ECDSA_SOFTWARE_SET_K_S 4
/** ECDSA_SOFTWARE_SET_Z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
#define ECDSA_SOFTWARE_SET_Z (BIT(5))
#define ECDSA_SOFTWARE_SET_Z_M (ECDSA_SOFTWARE_SET_Z_V << ECDSA_SOFTWARE_SET_Z_S)
#define ECDSA_SOFTWARE_SET_Z_V 0x00000001U
#define ECDSA_SOFTWARE_SET_Z_S 5
/** ECDSA_DETERMINISTIC_K : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
#define ECDSA_DETERMINISTIC_K (BIT(6))
#define ECDSA_DETERMINISTIC_K_M (ECDSA_DETERMINISTIC_K_V << ECDSA_DETERMINISTIC_K_S)
#define ECDSA_DETERMINISTIC_K_V 0x00000001U
#define ECDSA_DETERMINISTIC_K_S 6
/** ECDSA_CLK_REG register
* ECDSA clock gate register
*/
#define ECDSA_CLK_REG (DR_REG_ECDSA_BASE + 0x8)
/** ECDSA_CLK_GATE_FORCE_ON : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
#define ECDSA_CLK_GATE_FORCE_ON (BIT(0))
#define ECDSA_CLK_GATE_FORCE_ON_M (ECDSA_CLK_GATE_FORCE_ON_V << ECDSA_CLK_GATE_FORCE_ON_S)
#define ECDSA_CLK_GATE_FORCE_ON_V 0x00000001U
#define ECDSA_CLK_GATE_FORCE_ON_S 0
/** ECDSA_INT_RAW_REG register
* ECDSA interrupt raw register, valid in level.
*/
#define ECDSA_INT_RAW_REG (DR_REG_ECDSA_BASE + 0xc)
/** ECDSA_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_RAW (BIT(0))
#define ECDSA_PREP_DONE_INT_RAW_M (ECDSA_PREP_DONE_INT_RAW_V << ECDSA_PREP_DONE_INT_RAW_S)
#define ECDSA_PREP_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PREP_DONE_INT_RAW_S 0
/** ECDSA_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_RAW (BIT(1))
#define ECDSA_PROC_DONE_INT_RAW_M (ECDSA_PROC_DONE_INT_RAW_V << ECDSA_PROC_DONE_INT_RAW_S)
#define ECDSA_PROC_DONE_INT_RAW_V 0x00000001U
#define ECDSA_PROC_DONE_INT_RAW_S 1
/** ECDSA_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_RAW (BIT(2))
#define ECDSA_POST_DONE_INT_RAW_M (ECDSA_POST_DONE_INT_RAW_V << ECDSA_POST_DONE_INT_RAW_S)
#define ECDSA_POST_DONE_INT_RAW_V 0x00000001U
#define ECDSA_POST_DONE_INT_RAW_S 2
/** ECDSA_SHA_RELEASE_INT_RAW : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_RAW (BIT(3))
#define ECDSA_SHA_RELEASE_INT_RAW_M (ECDSA_SHA_RELEASE_INT_RAW_V << ECDSA_SHA_RELEASE_INT_RAW_S)
#define ECDSA_SHA_RELEASE_INT_RAW_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_RAW_S 3
/** ECDSA_INT_ST_REG register
* ECDSA interrupt status register.
*/
#define ECDSA_INT_ST_REG (DR_REG_ECDSA_BASE + 0x10)
/** ECDSA_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ST (BIT(0))
#define ECDSA_PREP_DONE_INT_ST_M (ECDSA_PREP_DONE_INT_ST_V << ECDSA_PREP_DONE_INT_ST_S)
#define ECDSA_PREP_DONE_INT_ST_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ST_S 0
/** ECDSA_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ST (BIT(1))
#define ECDSA_PROC_DONE_INT_ST_M (ECDSA_PROC_DONE_INT_ST_V << ECDSA_PROC_DONE_INT_ST_S)
#define ECDSA_PROC_DONE_INT_ST_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ST_S 1
/** ECDSA_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ST (BIT(2))
#define ECDSA_POST_DONE_INT_ST_M (ECDSA_POST_DONE_INT_ST_V << ECDSA_POST_DONE_INT_ST_S)
#define ECDSA_POST_DONE_INT_ST_V 0x00000001U
#define ECDSA_POST_DONE_INT_ST_S 2
/** ECDSA_SHA_RELEASE_INT_ST : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ST (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ST_M (ECDSA_SHA_RELEASE_INT_ST_V << ECDSA_SHA_RELEASE_INT_ST_S)
#define ECDSA_SHA_RELEASE_INT_ST_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ST_S 3
/** ECDSA_INT_ENA_REG register
* ECDSA interrupt enable register.
*/
#define ECDSA_INT_ENA_REG (DR_REG_ECDSA_BASE + 0x14)
/** ECDSA_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_ENA (BIT(0))
#define ECDSA_PREP_DONE_INT_ENA_M (ECDSA_PREP_DONE_INT_ENA_V << ECDSA_PREP_DONE_INT_ENA_S)
#define ECDSA_PREP_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PREP_DONE_INT_ENA_S 0
/** ECDSA_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_ENA (BIT(1))
#define ECDSA_PROC_DONE_INT_ENA_M (ECDSA_PROC_DONE_INT_ENA_V << ECDSA_PROC_DONE_INT_ENA_S)
#define ECDSA_PROC_DONE_INT_ENA_V 0x00000001U
#define ECDSA_PROC_DONE_INT_ENA_S 1
/** ECDSA_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_ENA (BIT(2))
#define ECDSA_POST_DONE_INT_ENA_M (ECDSA_POST_DONE_INT_ENA_V << ECDSA_POST_DONE_INT_ENA_S)
#define ECDSA_POST_DONE_INT_ENA_V 0x00000001U
#define ECDSA_POST_DONE_INT_ENA_S 2
/** ECDSA_SHA_RELEASE_INT_ENA : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_ENA (BIT(3))
#define ECDSA_SHA_RELEASE_INT_ENA_M (ECDSA_SHA_RELEASE_INT_ENA_V << ECDSA_SHA_RELEASE_INT_ENA_S)
#define ECDSA_SHA_RELEASE_INT_ENA_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_ENA_S 3
/** ECDSA_INT_CLR_REG register
* ECDSA interrupt clear register.
*/
#define ECDSA_INT_CLR_REG (DR_REG_ECDSA_BASE + 0x18)
/** ECDSA_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
#define ECDSA_PREP_DONE_INT_CLR (BIT(0))
#define ECDSA_PREP_DONE_INT_CLR_M (ECDSA_PREP_DONE_INT_CLR_V << ECDSA_PREP_DONE_INT_CLR_S)
#define ECDSA_PREP_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PREP_DONE_INT_CLR_S 0
/** ECDSA_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
#define ECDSA_PROC_DONE_INT_CLR (BIT(1))
#define ECDSA_PROC_DONE_INT_CLR_M (ECDSA_PROC_DONE_INT_CLR_V << ECDSA_PROC_DONE_INT_CLR_S)
#define ECDSA_PROC_DONE_INT_CLR_V 0x00000001U
#define ECDSA_PROC_DONE_INT_CLR_S 1
/** ECDSA_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
#define ECDSA_POST_DONE_INT_CLR (BIT(2))
#define ECDSA_POST_DONE_INT_CLR_M (ECDSA_POST_DONE_INT_CLR_V << ECDSA_POST_DONE_INT_CLR_S)
#define ECDSA_POST_DONE_INT_CLR_V 0x00000001U
#define ECDSA_POST_DONE_INT_CLR_S 2
/** ECDSA_SHA_RELEASE_INT_CLR : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
#define ECDSA_SHA_RELEASE_INT_CLR (BIT(3))
#define ECDSA_SHA_RELEASE_INT_CLR_M (ECDSA_SHA_RELEASE_INT_CLR_V << ECDSA_SHA_RELEASE_INT_CLR_S)
#define ECDSA_SHA_RELEASE_INT_CLR_V 0x00000001U
#define ECDSA_SHA_RELEASE_INT_CLR_S 3
/** ECDSA_START_REG register
* ECDSA start register
*/
#define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
/** ECDSA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
#define ECDSA_START (BIT(0))
#define ECDSA_START_M (ECDSA_START_V << ECDSA_START_S)
#define ECDSA_START_V 0x00000001U
#define ECDSA_START_S 0
/** ECDSA_LOAD_DONE : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_LOAD_DONE (BIT(1))
#define ECDSA_LOAD_DONE_M (ECDSA_LOAD_DONE_V << ECDSA_LOAD_DONE_S)
#define ECDSA_LOAD_DONE_V 0x00000001U
#define ECDSA_LOAD_DONE_S 1
/** ECDSA_GET_DONE : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
#define ECDSA_GET_DONE (BIT(2))
#define ECDSA_GET_DONE_M (ECDSA_GET_DONE_V << ECDSA_GET_DONE_S)
#define ECDSA_GET_DONE_V 0x00000001U
#define ECDSA_GET_DONE_S 2
/** ECDSA_STATE_REG register
* ECDSA status register
*/
#define ECDSA_STATE_REG (DR_REG_ECDSA_BASE + 0x20)
/** ECDSA_BUSY : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
#define ECDSA_BUSY 0x00000003U
#define ECDSA_BUSY_M (ECDSA_BUSY_V << ECDSA_BUSY_S)
#define ECDSA_BUSY_V 0x00000003U
#define ECDSA_BUSY_S 0
/** ECDSA_RESULT_REG register
* ECDSA result register
*/
#define ECDSA_RESULT_REG (DR_REG_ECDSA_BASE + 0x24)
/** ECDSA_OPERATION_RESULT : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
#define ECDSA_OPERATION_RESULT (BIT(0))
#define ECDSA_OPERATION_RESULT_M (ECDSA_OPERATION_RESULT_V << ECDSA_OPERATION_RESULT_S)
#define ECDSA_OPERATION_RESULT_V 0x00000001U
#define ECDSA_OPERATION_RESULT_S 0
/** ECDSA_DATE_REG register
* Version control register
*/
#define ECDSA_DATE_REG (DR_REG_ECDSA_BASE + 0xfc)
/** ECDSA_DATE : R/W; bitpos: [27:0]; default: 37785984;
* ECDSA version control register
*/
#define ECDSA_DATE 0x0FFFFFFFU
#define ECDSA_DATE_M (ECDSA_DATE_V << ECDSA_DATE_S)
#define ECDSA_DATE_V 0x0FFFFFFFU
#define ECDSA_DATE_S 0
/** ECDSA_SHA_MODE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_MODE_REG (DR_REG_ECDSA_BASE + 0x200)
/** ECDSA_SHA_MODE : R/W; bitpos: [3:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
* invalid.
*/
#define ECDSA_SHA_MODE 0x0000000FU
#define ECDSA_SHA_MODE_M (ECDSA_SHA_MODE_V << ECDSA_SHA_MODE_S)
#define ECDSA_SHA_MODE_V 0x0000000FU
#define ECDSA_SHA_MODE_S 0
/** ECDSA_SHA_START_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
/** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_START (BIT(0))
#define ECDSA_SHA_START_M (ECDSA_SHA_START_V << ECDSA_SHA_START_S)
#define ECDSA_SHA_START_V 0x00000001U
#define ECDSA_SHA_START_S 0
/** ECDSA_SHA_CONTINUE_REG register
* ECDSA control SHA register
*/
#define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
/** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
#define ECDSA_SHA_CONTINUE (BIT(0))
#define ECDSA_SHA_CONTINUE_M (ECDSA_SHA_CONTINUE_V << ECDSA_SHA_CONTINUE_S)
#define ECDSA_SHA_CONTINUE_V 0x00000001U
#define ECDSA_SHA_CONTINUE_S 0
/** ECDSA_SHA_BUSY_REG register
* ECDSA status register
*/
#define ECDSA_SHA_BUSY_REG (DR_REG_ECDSA_BASE + 0x218)
/** ECDSA_SHA_BUSY : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
#define ECDSA_SHA_BUSY (BIT(0))
#define ECDSA_SHA_BUSY_M (ECDSA_SHA_BUSY_V << ECDSA_SHA_BUSY_S)
#define ECDSA_SHA_BUSY_V 0x00000001U
#define ECDSA_SHA_BUSY_S 0
/** ECDSA_MESSAGE_MEM register
* The memory that stores message.
*/
#define ECDSA_MESSAGE_MEM (DR_REG_ECDSA_BASE + 0x280)
#define ECDSA_MESSAGE_MEM_SIZE_BYTES 64
/** ECDSA_R_MEM register
* The memory that stores r.
*/
#define ECDSA_R_MEM (DR_REG_ECDSA_BASE + 0x3e0)
#define ECDSA_R_MEM_SIZE_BYTES 48
/** ECDSA_S_MEM register
* The memory that stores s.
*/
#define ECDSA_S_MEM (DR_REG_ECDSA_BASE + 0x410)
#define ECDSA_S_MEM_SIZE_BYTES 48
/** ECDSA_Z_MEM register
* The memory that stores software written z.
*/
#define ECDSA_Z_MEM (DR_REG_ECDSA_BASE + 0x440)
#define ECDSA_Z_MEM_SIZE_BYTES 48
/** ECDSA_QAX_MEM register
* The memory that stores x coordinates of QA or software written k.
*/
#define ECDSA_QAX_MEM (DR_REG_ECDSA_BASE + 0x470)
#define ECDSA_QAX_MEM_SIZE_BYTES 48
/** ECDSA_QAY_MEM register
* The memory that stores y coordinates of QA.
*/
#define ECDSA_QAY_MEM (DR_REG_ECDSA_BASE + 0x4a0)
#define ECDSA_QAY_MEM_SIZE_BYTES 48
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Data Memory */
/** Group: Configuration registers */
/** Type of conf register
* ECDSA configure register
*/
typedef union {
struct {
/** work_mode : R/W; bitpos: [1:0]; default: 0;
* The work mode bits of ECDSA Accelerator. 0: Signature Verify Mode. 1: Signature
* Generate Mode. 2: Export Public Key Mode. 3: invalid.
*/
uint32_t work_mode:2;
/** ecc_curve : R/W; bitpos: [3:2]; default: 0;
* The ecc curve select bit of ECDSA Accelerator. 0: P-192. 1: P-256. 2: P-384 3: SM2.
*/
uint32_t ecc_curve:2;
/** software_set_k : R/W; bitpos: [4]; default: 0;
* The source of k select bit. 0: k is automatically generated by hardware. 1: k is
* written by software.
*/
uint32_t software_set_k:1;
/** software_set_z : R/W; bitpos: [5]; default: 0;
* The source of z select bit. 0: z is generated from SHA result. 1: z is written by
* software.
*/
uint32_t software_set_z:1;
/** deterministic_k : R/W; bitpos: [6]; default: 0;
* The source of hardware generated k. 0: k is generated by TRNG. 1: k is generated by
* deterministic derivation algorithm.
*/
uint32_t deterministic_k:1;
uint32_t reserved_7:25;
};
uint32_t val;
} ecdsa_conf_reg_t;
/** Type of start register
* ECDSA start register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
* after configuration.
*/
uint32_t start:1;
/** load_done : WT; bitpos: [1]; default: 0;
* Write 1 to input load done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t load_done:1;
/** get_done : WT; bitpos: [2]; default: 0;
* Write 1 to input get done signal of ECDSA Accelerator. This bit will be
* self-cleared after configuration.
*/
uint32_t get_done:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ecdsa_start_reg_t;
/** Group: Clock and reset registers */
/** Type of clk register
* ECDSA clock gate register
*/
typedef union {
struct {
/** clk_gate_force_on : R/W; bitpos: [0]; default: 0;
* Write 1 to force on register clock gate.
*/
uint32_t clk_gate_force_on:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* ECDSA interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
/** sha_release_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_raw_reg_t;
/** Type of int_st register
* ECDSA interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
/** sha_release_int_st : RO; bitpos: [3]; default: 0;
* The masked interrupt status bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_st_reg_t;
/** Type of int_ena register
* ECDSA interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
/** sha_release_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_ena_reg_t;
/** Type of int_clr register
* ECDSA interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the ecdsa_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the ecdsa_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the ecdsa_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
/** sha_release_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the ecdsa_sha_release_int interrupt
*/
uint32_t sha_release_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_int_clr_reg_t;
/** Group: Status registers */
/** Type of state register
* ECDSA status register
*/
typedef union {
struct {
/** busy : RO; bitpos: [1:0]; default: 0;
* The status bits of ECDSA Accelerator. ECDSA is at 0: IDLE, 1: LOAD, 2: GET, 3: BUSY
* state.
*/
uint32_t busy:2;
uint32_t reserved_2:30;
};
uint32_t val;
} ecdsa_state_reg_t;
/** Group: Result registers */
/** Type of result register
* ECDSA result register
*/
typedef union {
struct {
/** operation_result : RO/SS; bitpos: [0]; default: 0;
* The operation result bit of ECDSA Accelerator, only valid when ECDSA calculation is
* done.
*/
uint32_t operation_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_result_reg_t;
/** Group: SHA register */
/** Type of sha_mode register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_mode : R/W; bitpos: [3:0]; default: 0;
* The work mode bits of SHA Calculator in ECDSA Accelerator. 0: SHA1. 1: SHA-224. 2:
* SHA-256. 3: SHA-384 4: SHA-512. 5: SHA-512224. 6: SHA-512256. 14:SM3. Others:
* invalid.
*/
uint32_t sha_mode:4;
uint32_t reserved_4:28;
};
uint32_t val;
} ecdsa_sha_mode_reg_t;
/** Type of sha_start register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_start : WT; bitpos: [0]; default: 0;
* Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_start_reg_t;
/** Type of sha_continue register
* ECDSA control SHA register
*/
typedef union {
struct {
/** sha_continue : WT; bitpos: [0]; default: 0;
* Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
* bit will be self-cleared after configuration.
*/
uint32_t sha_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_continue_reg_t;
/** Type of sha_busy register
* ECDSA status register
*/
typedef union {
struct {
/** sha_busy : RO; bitpos: [0]; default: 0;
* The busy status bit of SHA Calculator in ECDSA Accelerator. 1:SHA is in
* calculation. 0: SHA is idle.
*/
uint32_t sha_busy:1;
uint32_t reserved_1:31;
};
uint32_t val;
} ecdsa_sha_busy_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37785984;
* ECDSA version control register
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} ecdsa_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile ecdsa_conf_reg_t conf;
volatile ecdsa_clk_reg_t clk;
volatile ecdsa_int_raw_reg_t int_raw;
volatile ecdsa_int_st_reg_t int_st;
volatile ecdsa_int_ena_reg_t int_ena;
volatile ecdsa_int_clr_reg_t int_clr;
volatile ecdsa_start_reg_t start;
volatile ecdsa_state_reg_t state;
volatile ecdsa_result_reg_t result;
uint32_t reserved_028[53];
volatile ecdsa_date_reg_t date;
uint32_t reserved_100[64];
volatile ecdsa_sha_mode_reg_t sha_mode;
uint32_t reserved_204[3];
volatile ecdsa_sha_start_reg_t sha_start;
volatile ecdsa_sha_continue_reg_t sha_continue;
volatile ecdsa_sha_busy_reg_t sha_busy;
uint32_t reserved_21c[25];
volatile uint32_t message[16];
uint32_t reserved_2c0[72];
volatile uint32_t r[12];
volatile uint32_t s[12];
volatile uint32_t z[12];
volatile uint32_t qax[12];
volatile uint32_t qay[12];
} ecdsa_dev_t;
extern ecdsa_dev_t ECDSA;
#ifndef __cplusplus
_Static_assert(sizeof(ecdsa_dev_t) == 0x4d0, "Invalid size of ecdsa_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/hmac_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HMAC_SET_START_REG register
* HMAC start control register
*/
#define HMAC_SET_START_REG (DR_REG_HMAC_BASE + 0x40)
/** HMAC_SET_START : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
*
* 0: Disable HMAC
*
* 1: Enable HMAC
*/
#define HMAC_SET_START (BIT(0))
#define HMAC_SET_START_M (HMAC_SET_START_V << HMAC_SET_START_S)
#define HMAC_SET_START_V 0x00000001U
#define HMAC_SET_START_S 0
/** HMAC_SET_PARA_PURPOSE_REG register
* HMAC parameter configuration register
*/
#define HMAC_SET_PARA_PURPOSE_REG (DR_REG_HMAC_BASE + 0x44)
/** HMAC_PURPOSE_SET : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table . "
*/
#define HMAC_PURPOSE_SET 0x0000000FU
#define HMAC_PURPOSE_SET_M (HMAC_PURPOSE_SET_V << HMAC_PURPOSE_SET_S)
#define HMAC_PURPOSE_SET_V 0x0000000FU
#define HMAC_PURPOSE_SET_S 0
/** HMAC_SET_PARA_KEY_REG register
* HMAC parameters configuration register
*/
#define HMAC_SET_PARA_KEY_REG (DR_REG_HMAC_BASE + 0x48)
/** HMAC_KEY_SET : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
#define HMAC_KEY_SET 0x00000007U
#define HMAC_KEY_SET_M (HMAC_KEY_SET_V << HMAC_KEY_SET_S)
#define HMAC_KEY_SET_V 0x00000007U
#define HMAC_KEY_SET_S 0
/** HMAC_SET_PARA_FINISH_REG register
* HMAC configuration completion register
*/
#define HMAC_SET_PARA_FINISH_REG (DR_REG_HMAC_BASE + 0x4c)
/** HMAC_SET_PARA_END : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
*
* 0: No effect
*
* 1: Finish configuration
*/
#define HMAC_SET_PARA_END (BIT(0))
#define HMAC_SET_PARA_END_M (HMAC_SET_PARA_END_V << HMAC_SET_PARA_END_S)
#define HMAC_SET_PARA_END_V 0x00000001U
#define HMAC_SET_PARA_END_S 0
/** HMAC_SET_MESSAGE_ONE_REG register
* HMAC message control register
*/
#define HMAC_SET_MESSAGE_ONE_REG (DR_REG_HMAC_BASE + 0x50)
/** HMAC_SET_TEXT_ONE : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
#define HMAC_SET_TEXT_ONE (BIT(0))
#define HMAC_SET_TEXT_ONE_M (HMAC_SET_TEXT_ONE_V << HMAC_SET_TEXT_ONE_S)
#define HMAC_SET_TEXT_ONE_V 0x00000001U
#define HMAC_SET_TEXT_ONE_S 0
/** HMAC_SET_MESSAGE_ING_REG register
* HMAC message continue register
*/
#define HMAC_SET_MESSAGE_ING_REG (DR_REG_HMAC_BASE + 0x54)
/** HMAC_SET_TEXT_ING : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
*
* 0: No unprocessed message block
*
* 1: There are still some message blocks to be processed.
*/
#define HMAC_SET_TEXT_ING (BIT(0))
#define HMAC_SET_TEXT_ING_M (HMAC_SET_TEXT_ING_V << HMAC_SET_TEXT_ING_S)
#define HMAC_SET_TEXT_ING_V 0x00000001U
#define HMAC_SET_TEXT_ING_S 0
/** HMAC_SET_MESSAGE_END_REG register
* HMAC message end register
*/
#define HMAC_SET_MESSAGE_END_REG (DR_REG_HMAC_BASE + 0x58)
/** HMAC_SET_TEXT_END : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
*
* 0: No effect
*
* 1: Start hardware padding
*/
#define HMAC_SET_TEXT_END (BIT(0))
#define HMAC_SET_TEXT_END_M (HMAC_SET_TEXT_END_V << HMAC_SET_TEXT_END_S)
#define HMAC_SET_TEXT_END_V 0x00000001U
#define HMAC_SET_TEXT_END_S 0
/** HMAC_SET_RESULT_FINISH_REG register
* HMAC result reading finish register
*/
#define HMAC_SET_RESULT_FINISH_REG (DR_REG_HMAC_BASE + 0x5c)
/** HMAC_SET_RESULT_END : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
*
* 0: Not exit
*
* 1: Exit upstream mode and clear calculation results.
*/
#define HMAC_SET_RESULT_END (BIT(0))
#define HMAC_SET_RESULT_END_M (HMAC_SET_RESULT_END_V << HMAC_SET_RESULT_END_S)
#define HMAC_SET_RESULT_END_V 0x00000001U
#define HMAC_SET_RESULT_END_S 0
/** HMAC_SET_INVALIDATE_JTAG_REG register
* Invalidate JTAG result register
*/
#define HMAC_SET_INVALIDATE_JTAG_REG (DR_REG_HMAC_BASE + 0x60)
/** HMAC_SET_INVALIDATE_JTAG : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_JTAG (BIT(0))
#define HMAC_SET_INVALIDATE_JTAG_M (HMAC_SET_INVALIDATE_JTAG_V << HMAC_SET_INVALIDATE_JTAG_S)
#define HMAC_SET_INVALIDATE_JTAG_V 0x00000001U
#define HMAC_SET_INVALIDATE_JTAG_S 0
/** HMAC_SET_INVALIDATE_DS_REG register
* Invalidate digital signature result register
*/
#define HMAC_SET_INVALIDATE_DS_REG (DR_REG_HMAC_BASE + 0x64)
/** HMAC_SET_INVALIDATE_DS : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
#define HMAC_SET_INVALIDATE_DS (BIT(0))
#define HMAC_SET_INVALIDATE_DS_M (HMAC_SET_INVALIDATE_DS_V << HMAC_SET_INVALIDATE_DS_S)
#define HMAC_SET_INVALIDATE_DS_V 0x00000001U
#define HMAC_SET_INVALIDATE_DS_S 0
/** HMAC_QUERY_ERROR_REG register
* Stores matching results between keys generated by users and corresponding purposes
*/
#define HMAC_QUERY_ERROR_REG (DR_REG_HMAC_BASE + 0x68)
/** HMAC_QUREY_CHECK : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
*
* 0: Match
*
* 1: Error
*/
#define HMAC_QUREY_CHECK (BIT(0))
#define HMAC_QUREY_CHECK_M (HMAC_QUREY_CHECK_V << HMAC_QUREY_CHECK_S)
#define HMAC_QUREY_CHECK_V 0x00000001U
#define HMAC_QUREY_CHECK_S 0
/** HMAC_QUERY_BUSY_REG register
* Busy state of HMAC module
*/
#define HMAC_QUERY_BUSY_REG (DR_REG_HMAC_BASE + 0x6c)
/** HMAC_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
*
* 0: Idle
*
* 1: HMAC is still working on the calculation
*/
#define HMAC_BUSY_STATE (BIT(0))
#define HMAC_BUSY_STATE_M (HMAC_BUSY_STATE_V << HMAC_BUSY_STATE_S)
#define HMAC_BUSY_STATE_V 0x00000001U
#define HMAC_BUSY_STATE_S 0
/** HMAC_WR_MESSAGE_MEM register
* Message block memory.
*/
#define HMAC_WR_MESSAGE_MEM (DR_REG_HMAC_BASE + 0x80)
#define HMAC_WR_MESSAGE_MEM_SIZE_BYTES 64
/** HMAC_RD_RESULT_MEM register
* Result from upstream.
*/
#define HMAC_RD_RESULT_MEM (DR_REG_HMAC_BASE + 0xc0)
#define HMAC_RD_RESULT_MEM_SIZE_BYTES 32
/** HMAC_SET_MESSAGE_PAD_REG register
* Software padding register
*/
#define HMAC_SET_MESSAGE_PAD_REG (DR_REG_HMAC_BASE + 0xf0)
/** HMAC_SET_TEXT_PAD : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
*
* 0: Not applied by software
*
* 1: Applied by software
*/
#define HMAC_SET_TEXT_PAD (BIT(0))
#define HMAC_SET_TEXT_PAD_M (HMAC_SET_TEXT_PAD_V << HMAC_SET_TEXT_PAD_S)
#define HMAC_SET_TEXT_PAD_V 0x00000001U
#define HMAC_SET_TEXT_PAD_S 0
/** HMAC_ONE_BLOCK_REG register
* One block message register
*/
#define HMAC_ONE_BLOCK_REG (DR_REG_HMAC_BASE + 0xf4)
/** HMAC_SET_ONE_BLOCK : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
#define HMAC_SET_ONE_BLOCK (BIT(0))
#define HMAC_SET_ONE_BLOCK_M (HMAC_SET_ONE_BLOCK_V << HMAC_SET_ONE_BLOCK_S)
#define HMAC_SET_ONE_BLOCK_V 0x00000001U
#define HMAC_SET_ONE_BLOCK_S 0
/** HMAC_SOFT_JTAG_CTRL_REG register
* Jtag register 0.
*/
#define HMAC_SOFT_JTAG_CTRL_REG (DR_REG_HMAC_BASE + 0xf8)
/** HMAC_SOFT_JTAG_CTRL : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
*
* 0: Disable
*
* 1: Enable
*
*/
#define HMAC_SOFT_JTAG_CTRL (BIT(0))
#define HMAC_SOFT_JTAG_CTRL_M (HMAC_SOFT_JTAG_CTRL_V << HMAC_SOFT_JTAG_CTRL_S)
#define HMAC_SOFT_JTAG_CTRL_V 0x00000001U
#define HMAC_SOFT_JTAG_CTRL_S 0
/** HMAC_WR_JTAG_REG register
* Re-enable JTAG register 1
*/
#define HMAC_WR_JTAG_REG (DR_REG_HMAC_BASE + 0xfc)
/** HMAC_WR_JTAG : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
#define HMAC_WR_JTAG 0xFFFFFFFFU
#define HMAC_WR_JTAG_M (HMAC_WR_JTAG_V << HMAC_WR_JTAG_S)
#define HMAC_WR_JTAG_V 0xFFFFFFFFU
#define HMAC_WR_JTAG_S 0
/** HMAC_DATE_REG register
* Version control register
*/
#define HMAC_DATE_REG (DR_REG_HMAC_BASE + 0x1fc)
/** HMAC_DATE : R/W; bitpos: [29:0]; default: 539166977;
* Hmac date information/ hmac version information.
*/
#define HMAC_DATE 0x3FFFFFFFU
#define HMAC_DATE_M (HMAC_DATE_V << HMAC_DATE_S)
#define HMAC_DATE_V 0x3FFFFFFFU
#define HMAC_DATE_S 0
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Status Registers */
/** Type of set_start register
* HMAC start control register
*/
typedef union {
struct {
/** set_start : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable HMAC.
*
* 0: Disable HMAC
*
* 1: Enable HMAC
*/
uint32_t set_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_start_reg_t;
/** Type of set_para_finish register
* HMAC configuration completion register
*/
typedef union {
struct {
/** set_para_end : WS; bitpos: [0]; default: 0;
* Configures whether to finish HMAC configuration.
*
* 0: No effect
*
* 1: Finish configuration
*/
uint32_t set_para_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_para_finish_reg_t;
/** Type of set_message_one register
* HMAC message control register
*/
typedef union {
struct {
/** set_text_one : WS; bitpos: [0]; default: 0;
* Calls SHA to calculate one message block.
*/
uint32_t set_text_one:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_one_reg_t;
/** Type of set_message_ing register
* HMAC message continue register
*/
typedef union {
struct {
/** set_text_ing : WS; bitpos: [0]; default: 0;
* Configures whether or not there are unprocessed message blocks.
*
* 0: No unprocessed message block
*
* 1: There are still some message blocks to be processed.
*/
uint32_t set_text_ing:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_ing_reg_t;
/** Type of set_message_end register
* HMAC message end register
*/
typedef union {
struct {
/** set_text_end : WS; bitpos: [0]; default: 0;
* Configures whether to start hardware padding.
*
* 0: No effect
*
* 1: Start hardware padding
*/
uint32_t set_text_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_end_reg_t;
/** Type of set_result_finish register
* HMAC result reading finish register
*/
typedef union {
struct {
/** set_result_end : WS; bitpos: [0]; default: 0;
* Configures whether to exit upstream mode and clear calculation results.
*
* 0: Not exit
*
* 1: Exit upstream mode and clear calculation results.
*/
uint32_t set_result_end:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_result_finish_reg_t;
/** Type of set_invalidate_jtag register
* Invalidate JTAG result register
*/
typedef union {
struct {
/** set_invalidate_jtag : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results when re-enabling JTAG in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
uint32_t set_invalidate_jtag:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_jtag_reg_t;
/** Type of set_invalidate_ds register
* Invalidate digital signature result register
*/
typedef union {
struct {
/** set_invalidate_ds : WS; bitpos: [0]; default: 0;
* Configures whether or not to clear calculation results of the DS module in
* downstream mode.
*
* 0: Not clear
*
* 1: Clear calculation results
*/
uint32_t set_invalidate_ds:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_invalidate_ds_reg_t;
/** Type of query_error register
* Stores matching results between keys generated by users and corresponding purposes
*/
typedef union {
struct {
/** qurey_check : RO; bitpos: [0]; default: 0;
* Represents whether or not an HMAC key matches the purpose.
*
* 0: Match
*
* 1: Error
*/
uint32_t qurey_check:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_error_reg_t;
/** Type of query_busy register
* Busy state of HMAC module
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Represents whether or not HMAC is in a busy state. Before configuring HMAC, please
* make sure HMAC is in an IDLE state.
*
* 0: Idle
*
* 1: HMAC is still working on the calculation
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_query_busy_reg_t;
/** Type of set_message_pad register
* Software padding register
*/
typedef union {
struct {
/** set_text_pad : WO; bitpos: [0]; default: 0;
* Configures whether or not the padding is applied by software.
*
* 0: Not applied by software
*
* 1: Applied by software
*/
uint32_t set_text_pad:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_set_message_pad_reg_t;
/** Type of one_block register
* One block message register
*/
typedef union {
struct {
/** set_one_block : WS; bitpos: [0]; default: 0;
* Write 1 to indicate there is only one block which already contains padding bits and
* there is no need for padding.
*/
uint32_t set_one_block:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_one_block_reg_t;
/** Group: Configuration Registers */
/** Type of set_para_purpose register
* HMAC parameter configuration register
*/
typedef union {
struct {
/** purpose_set : WO; bitpos: [3:0]; default: 0;
* Configures the HMAC purpose, refer to the Table . "
*/
uint32_t purpose_set:4;
uint32_t reserved_4:28;
};
uint32_t val;
} hmac_set_para_purpose_reg_t;
/** Type of set_para_key register
* HMAC parameters configuration register
*/
typedef union {
struct {
/** key_set : WO; bitpos: [2:0]; default: 0;
* Configures HMAC key. There are six keys with index 0~5. Write the index of the
* selected key to this field.
*/
uint32_t key_set:3;
uint32_t reserved_3:29;
};
uint32_t val;
} hmac_set_para_key_reg_t;
/** Type of wr_jtag register
* Re-enable JTAG register 1
*/
typedef union {
struct {
/** wr_jtag : WO; bitpos: [31:0]; default: 0;
* Writes the comparing input used for re-enabling JTAG.
*/
uint32_t wr_jtag:32;
};
uint32_t val;
} hmac_wr_jtag_reg_t;
/** Group: Memory Type */
/** Group: Configuration Register */
/** Type of soft_jtag_ctrl register
* Jtag register 0.
*/
typedef union {
struct {
/** soft_jtag_ctrl : WS; bitpos: [0]; default: 0;
* Configures whether or not to enable JTAG authentication mode.
*
* 0: Disable
*
* 1: Enable
*
*/
uint32_t soft_jtag_ctrl:1;
uint32_t reserved_1:31;
};
uint32_t val;
} hmac_soft_jtag_ctrl_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539166977;
* Hmac date information/ hmac version information.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} hmac_date_reg_t;
typedef struct {
uint32_t reserved_000[16];
volatile hmac_set_start_reg_t set_start;
volatile hmac_set_para_purpose_reg_t set_para_purpose;
volatile hmac_set_para_key_reg_t set_para_key;
volatile hmac_set_para_finish_reg_t set_para_finish;
volatile hmac_set_message_one_reg_t set_message_one;
volatile hmac_set_message_ing_reg_t set_message_ing;
volatile hmac_set_message_end_reg_t set_message_end;
volatile hmac_set_result_finish_reg_t set_result_finish;
volatile hmac_set_invalidate_jtag_reg_t set_invalidate_jtag;
volatile hmac_set_invalidate_ds_reg_t set_invalidate_ds;
volatile hmac_query_error_reg_t query_error;
volatile hmac_query_busy_reg_t query_busy;
uint32_t reserved_070[4];
volatile uint32_t wr_message[16];
volatile uint32_t rd_result[8];
uint32_t reserved_0e0[4];
volatile hmac_set_message_pad_reg_t set_message_pad;
volatile hmac_one_block_reg_t one_block;
volatile hmac_soft_jtag_ctrl_reg_t soft_jtag_ctrl;
volatile hmac_wr_jtag_reg_t wr_jtag;
uint32_t reserved_100[63];
volatile hmac_date_reg_t date;
} hmac_dev_t;
extern hmac_dev_t HMAC;
#ifndef __cplusplus
_Static_assert(sizeof(hmac_dev_t) == 0x200, "Invalid size of hmac_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/huk_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** HUK_CLK_REG register
* HUK Generator clock gate control register
*/
#define HUK_CLK_REG (DR_REG_HUK_BASE + 0x4)
/** HUK_CLK_EN : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define HUK_CLK_EN (BIT(0))
#define HUK_CLK_EN_M (HUK_CLK_EN_V << HUK_CLK_EN_S)
#define HUK_CLK_EN_V 0x00000001U
#define HUK_CLK_EN_S 0
/** HUK_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define HUK_MEM_CG_FORCE_ON (BIT(1))
#define HUK_MEM_CG_FORCE_ON_M (HUK_MEM_CG_FORCE_ON_V << HUK_MEM_CG_FORCE_ON_S)
#define HUK_MEM_CG_FORCE_ON_V 0x00000001U
#define HUK_MEM_CG_FORCE_ON_S 1
/** HUK_INT_RAW_REG register
* HUK Generator interrupt raw register, valid in level.
*/
#define HUK_INT_RAW_REG (DR_REG_HUK_BASE + 0x8)
/** HUK_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_RAW (BIT(0))
#define HUK_PREP_DONE_INT_RAW_M (HUK_PREP_DONE_INT_RAW_V << HUK_PREP_DONE_INT_RAW_S)
#define HUK_PREP_DONE_INT_RAW_V 0x00000001U
#define HUK_PREP_DONE_INT_RAW_S 0
/** HUK_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_RAW (BIT(1))
#define HUK_PROC_DONE_INT_RAW_M (HUK_PROC_DONE_INT_RAW_V << HUK_PROC_DONE_INT_RAW_S)
#define HUK_PROC_DONE_INT_RAW_V 0x00000001U
#define HUK_PROC_DONE_INT_RAW_S 1
/** HUK_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_RAW (BIT(2))
#define HUK_POST_DONE_INT_RAW_M (HUK_POST_DONE_INT_RAW_V << HUK_POST_DONE_INT_RAW_S)
#define HUK_POST_DONE_INT_RAW_V 0x00000001U
#define HUK_POST_DONE_INT_RAW_S 2
/** HUK_INT_ST_REG register
* HUK Generator interrupt status register.
*/
#define HUK_INT_ST_REG (DR_REG_HUK_BASE + 0xc)
/** HUK_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ST (BIT(0))
#define HUK_PREP_DONE_INT_ST_M (HUK_PREP_DONE_INT_ST_V << HUK_PREP_DONE_INT_ST_S)
#define HUK_PREP_DONE_INT_ST_V 0x00000001U
#define HUK_PREP_DONE_INT_ST_S 0
/** HUK_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ST (BIT(1))
#define HUK_PROC_DONE_INT_ST_M (HUK_PROC_DONE_INT_ST_V << HUK_PROC_DONE_INT_ST_S)
#define HUK_PROC_DONE_INT_ST_V 0x00000001U
#define HUK_PROC_DONE_INT_ST_S 1
/** HUK_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ST (BIT(2))
#define HUK_POST_DONE_INT_ST_M (HUK_POST_DONE_INT_ST_V << HUK_POST_DONE_INT_ST_S)
#define HUK_POST_DONE_INT_ST_V 0x00000001U
#define HUK_POST_DONE_INT_ST_S 2
/** HUK_INT_ENA_REG register
* HUK Generator interrupt enable register.
*/
#define HUK_INT_ENA_REG (DR_REG_HUK_BASE + 0x10)
/** HUK_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_ENA (BIT(0))
#define HUK_PREP_DONE_INT_ENA_M (HUK_PREP_DONE_INT_ENA_V << HUK_PREP_DONE_INT_ENA_S)
#define HUK_PREP_DONE_INT_ENA_V 0x00000001U
#define HUK_PREP_DONE_INT_ENA_S 0
/** HUK_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_ENA (BIT(1))
#define HUK_PROC_DONE_INT_ENA_M (HUK_PROC_DONE_INT_ENA_V << HUK_PROC_DONE_INT_ENA_S)
#define HUK_PROC_DONE_INT_ENA_V 0x00000001U
#define HUK_PROC_DONE_INT_ENA_S 1
/** HUK_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_ENA (BIT(2))
#define HUK_POST_DONE_INT_ENA_M (HUK_POST_DONE_INT_ENA_V << HUK_POST_DONE_INT_ENA_S)
#define HUK_POST_DONE_INT_ENA_V 0x00000001U
#define HUK_POST_DONE_INT_ENA_S 2
/** HUK_INT_CLR_REG register
* HUK Generator interrupt clear register.
*/
#define HUK_INT_CLR_REG (DR_REG_HUK_BASE + 0x14)
/** HUK_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
#define HUK_PREP_DONE_INT_CLR (BIT(0))
#define HUK_PREP_DONE_INT_CLR_M (HUK_PREP_DONE_INT_CLR_V << HUK_PREP_DONE_INT_CLR_S)
#define HUK_PREP_DONE_INT_CLR_V 0x00000001U
#define HUK_PREP_DONE_INT_CLR_S 0
/** HUK_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
#define HUK_PROC_DONE_INT_CLR (BIT(1))
#define HUK_PROC_DONE_INT_CLR_M (HUK_PROC_DONE_INT_CLR_V << HUK_PROC_DONE_INT_CLR_S)
#define HUK_PROC_DONE_INT_CLR_V 0x00000001U
#define HUK_PROC_DONE_INT_CLR_S 1
/** HUK_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
#define HUK_POST_DONE_INT_CLR (BIT(2))
#define HUK_POST_DONE_INT_CLR_M (HUK_POST_DONE_INT_CLR_V << HUK_POST_DONE_INT_CLR_S)
#define HUK_POST_DONE_INT_CLR_V 0x00000001U
#define HUK_POST_DONE_INT_CLR_S 2
/** HUK_CONF_REG register
* HUK Generator configuration register
*/
#define HUK_CONF_REG (DR_REG_HUK_BASE + 0x20)
/** HUK_MODE : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
#define HUK_MODE (BIT(0))
#define HUK_MODE_M (HUK_MODE_V << HUK_MODE_S)
#define HUK_MODE_V 0x00000001U
#define HUK_MODE_S 0
/** HUK_START_REG register
* HUK Generator control register
*/
#define HUK_START_REG (DR_REG_HUK_BASE + 0x24)
/** HUK_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
#define HUK_START (BIT(0))
#define HUK_START_M (HUK_START_V << HUK_START_S)
#define HUK_START_V 0x00000001U
#define HUK_START_S 0
/** HUK_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
#define HUK_CONTINUE (BIT(1))
#define HUK_CONTINUE_M (HUK_CONTINUE_V << HUK_CONTINUE_S)
#define HUK_CONTINUE_V 0x00000001U
#define HUK_CONTINUE_S 1
/** HUK_STATE_REG register
* HUK Generator state register
*/
#define HUK_STATE_REG (DR_REG_HUK_BASE + 0x28)
/** HUK_STATE : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define HUK_STATE 0x00000003U
#define HUK_STATE_M (HUK_STATE_V << HUK_STATE_S)
#define HUK_STATE_V 0x00000003U
#define HUK_STATE_S 0
/** HUK_STATUS_REG register
* HUK Generator HUK status register
*/
#define HUK_STATUS_REG (DR_REG_HUK_BASE + 0x34)
/** HUK_STATUS : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
#define HUK_STATUS 0x00000003U
#define HUK_STATUS_M (HUK_STATUS_V << HUK_STATUS_S)
#define HUK_STATUS_V 0x00000003U
#define HUK_STATUS_S 0
/** HUK_RISK_LEVEL : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
#define HUK_RISK_LEVEL 0x00000007U
#define HUK_RISK_LEVEL_M (HUK_RISK_LEVEL_V << HUK_RISK_LEVEL_S)
#define HUK_RISK_LEVEL_V 0x00000007U
#define HUK_RISK_LEVEL_S 2
/** HUK_UPDATE_REQ : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
#define HUK_UPDATE_REQ (BIT(5))
#define HUK_UPDATE_REQ_M (HUK_UPDATE_REQ_V << HUK_UPDATE_REQ_S)
#define HUK_UPDATE_REQ_V 0x00000001U
#define HUK_UPDATE_REQ_S 5
/** HUK_DATE_REG register
* Version control register
*/
#define HUK_DATE_REG (DR_REG_HUK_BASE + 0xfc)
/** HUK_DATE : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
#define HUK_DATE 0x0FFFFFFFU
#define HUK_DATE_M (HUK_DATE_V << HUK_DATE_S)
#define HUK_DATE_V 0x0FFFFFFFU
#define HUK_DATE_S 0
/** HUK_INFO_MEM register
* The memory that stores HUK info.
*/
#define HUK_INFO_MEM (DR_REG_HUK_BASE + 0x100)
#define HUK_INFO_MEM_SIZE_BYTES 384
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* HUK Generator clock gate control register
*/
typedef union {
struct {
/** clk_en : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t clk_en:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* HUK Generator interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_raw_reg_t;
/** Type of int_st register
* HUK Generator interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_st_reg_t;
/** Type of int_ena register
* HUK Generator interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the huk_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_ena_reg_t;
/** Type of int_clr register
* HUK Generator interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the huk_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the huk_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the huk_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} huk_int_clr_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* HUK Generator configuration register
*/
typedef union {
struct {
/** mode : R/W; bitpos: [0]; default: 0;
* Set this field to choose the huk process. 1: process huk generate mode. 0: process
* huk recovery mode.
*/
uint32_t mode:1;
uint32_t reserved_1:31;
};
uint32_t val;
} huk_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* HUK Generator control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue HUK Generator operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start HUK Generator at IDLE state.
*/
uint32_t continue:1;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_start_reg_t;
/** Group: State registers */
/** Type of state register
* HUK Generator state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of HUK Generator. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} huk_state_reg_t;
/** Group: Result registers */
/** Type of status register
* HUK Generator HUK status register
*/
typedef union {
struct {
/** status : RO; bitpos: [1:0]; default: 0;
* The HUK generation status. 0: HUK is not generated. 1: HUK is generated and valid.
* 2: HUK is generated but invalid. 3: reserved.
*/
uint32_t status:2;
/** risk_level : RO; bitpos: [4:2]; default: 0;
* The risk level of HUK. 0-6: the higher the risk level is, the more error bits there
* are in the PUF SRAM. 7: Error Level, HUK is invalid.
*/
uint32_t risk_level:3;
/** update_req : RO; bitpos: [5]; default: 0;
* The update request of HUK info. 0: User can update HUK info according to the risk
* level. 1: The HUK info is expired, and user need to update it.
*/
uint32_t update_req:1;
uint32_t reserved_6:26;
};
uint32_t val;
} huk_status_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37765232;
* HUK Generator version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} huk_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile huk_clk_reg_t clk;
volatile huk_int_raw_reg_t int_raw;
volatile huk_int_st_reg_t int_st;
volatile huk_int_ena_reg_t int_ena;
volatile huk_int_clr_reg_t int_clr;
uint32_t reserved_018[2];
volatile huk_conf_reg_t conf;
volatile huk_start_reg_t start;
volatile huk_state_reg_t state;
uint32_t reserved_02c[2];
volatile huk_status_reg_t status;
uint32_t reserved_038[49];
volatile huk_date_reg_t date;
volatile uint32_t info[96];
} huk_dev_t;
extern huk_dev_t HUK;
#ifndef __cplusplus
_Static_assert(sizeof(huk_dev_t) == 0x280, "Invalid size of huk_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
/* Output enable in sleep mode */
#define SLP_OE (BIT(0))
#define SLP_OE_M (BIT(0))
#define SLP_OE_V 1
#define SLP_OE_S 0
/* Pin used for wakeup from sleep */
#define SLP_SEL (BIT(1))
#define SLP_SEL_M (BIT(1))
#define SLP_SEL_V 1
#define SLP_SEL_S 1
/* Pulldown enable in sleep mode */
#define SLP_PD (BIT(2))
#define SLP_PD_M (BIT(2))
#define SLP_PD_V 1
#define SLP_PD_S 2
/* Pullup enable in sleep mode */
#define SLP_PU (BIT(3))
#define SLP_PU_M (BIT(3))
#define SLP_PU_V 1
#define SLP_PU_S 3
/* Input enable in sleep mode */
#define SLP_IE (BIT(4))
#define SLP_IE_M (BIT(4))
#define SLP_IE_V 1
#define SLP_IE_S 4
/* Drive strength in sleep mode */
#define SLP_DRV 0x3
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
#define SLP_DRV_V 0x3
#define SLP_DRV_S 5
/* Pulldown enable */
#define FUN_PD (BIT(7))
#define FUN_PD_M (BIT(7))
#define FUN_PD_V 1
#define FUN_PD_S 7
/* Pullup enable */
#define FUN_PU (BIT(8))
#define FUN_PU_M (BIT(8))
#define FUN_PU_V 1
#define FUN_PU_S 8
/* Input enable */
#define FUN_IE (BIT(9))
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
#define FUN_IE_V 1
#define FUN_IE_S 9
/* Drive strength */
#define FUN_DRV 0x3
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
#define FUN_DRV_V 0x3
#define FUN_DRV_S 10
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
#define MCU_SEL 0x7
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
#define MCU_SEL_V 0x7
#define MCU_SEL_S 12
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
#define FILTER_EN (BIT(15))
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
#define FILTER_EN_V 1
#define FILTER_EN_S 15
/* Configures whether or not to enable the hysteresis function of the pin when IO_MUX_GPIO$n_HYS_SEL is set to 1. */
#define HYS_EN (BIT(16))
#define HYS_EN_M (HYS_EN_V << HYS_EN_S)
#define HYS_EN_V 1
#define HYS_EN_S 16
/* Configures to choose the signal for enabling the hysteresis function for GPIO$n. */
#define HYS_SEL (BIT(17))
#define HYS_SEL_M (HYS_SEL_V << HYS_SEL_S)
#define HYS_SEL_V 1
#define HYS_SEL_S 17
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_U_PAD_GPIO0
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_U_PAD_GPIO1
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_U_PAD_GPIO2
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_U_PAD_GPIO3
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_P
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_U_PAD_XTAL_32K_N
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_U_PAD_SPICS1
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_U_PAD_SPICS0
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_U_PAD_SPIQ
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_U_PAD_SPIWP
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_U_PAD_GPIO13
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_U_PAD_GPIO14
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_U_PAD_GPIO15
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U_PAD_GPIO16
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U_PAD_GPIO17
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_U_PAD_GPIO18
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_GPIO19
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_GPIO20
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_GPIO21
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_U0RXD
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_U0TXD
#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_U_PAD_GPIO25
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_U_PAD_GPIO26
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_U_PAD_GPIO27
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_U_PAD_MTMS
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_U_PAD_MTDI
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_U_PAD_MTCK
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_U_PAD_MTDO
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_U_PAD_GPIO32
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_U_PAD_GPIO33
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_U_PAD_GPIO34
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_U_PAD_GPIO35
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_U_PAD_GPIO36
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_U_PAD_GPIO37
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_U_PAD_GPIO38
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_U_PAD_GPIO39
#define FUNC_GPIO_GPIO 1
#define PIN_FUNC_GPIO 1
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define EXT_OSC_SLOW_GPIO_NUM 0
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 39
#define MAX_GPIO_NUM 43
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define GPIO_NUM_IN_FORCE_0 0x60
#define GPIO_NUM_IN_FORCE_1 0x40
#define GPIO_NUM_IN_INVALID 0x50
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
#define PAD_POWER_SEL_S 15
#define PAD_POWER_SWITCH_DELAY 0x7
#define PAD_POWER_SWITCH_DELAY_V 0x7
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
#define PAD_POWER_SWITCH_DELAY_S 12
#define CLK_OUT3 0x0000000F
#define CLK_OUT3_V 0xF
#define CLK_OUT3_S 8
#define CLK_OUT3_M ((0xF)<<(8))
#define CLK_OUT2 0x0000000F
#define CLK_OUT2_V 0xF
#define CLK_OUT2_S 8
#define CLK_OUT2_M ((0xF)<<(8))
#define CLK_OUT1 0x0000000F
#define CLK_OUT1_V 0xF
#define CLK_OUT1_S 8
#define CLK_OUT1_M ((0xF)<<(8))
// definitions above are inherited from previous version of code, should double check
// definitions below are generated from pin_txt.csv
#define PERIPHS_IO_MUX_U_PAD_GPIO0 (REG_IO_MUX_BASE + 0x0)
#define FUNC_GPIO0_GPIO0 1
#define FUNC_GPIO0_GPIO0_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO1 (REG_IO_MUX_BASE + 0x4)
#define FUNC_GPIO1_GPIO1 1
#define FUNC_GPIO1_GPIO1_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO2 (REG_IO_MUX_BASE + 0x8)
#define FUNC_GPIO2_GPIO2 1
#define FUNC_GPIO2_GPIO2_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO3 (REG_IO_MUX_BASE + 0xC)
#define FUNC_GPIO3_GPIO3 1
#define FUNC_GPIO3_GPIO3_0 0
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_N (REG_IO_MUX_BASE + 0x10)
#define FUNC_XTAL_32K_N_GPIO4 1
#define FUNC_XTAL_32K_N_GPIO4_0 0
#define PERIPHS_IO_MUX_U_PAD_XTAL_32K_P (REG_IO_MUX_BASE + 0x14)
#define FUNC_XTAL_32K_P_GPIO5 1
#define FUNC_XTAL_32K_P_GPIO5_0 0
#define PERIPHS_IO_MUX_U_PAD_SPICS1 (REG_IO_MUX_BASE + 0x18)
#define FUNC_SPICS1_GPIO6 1
#define FUNC_SPICS1_SPICS1 0
#define PERIPHS_IO_MUX_U_PAD_SPICS0 (REG_IO_MUX_BASE + 0x1C)
#define FUNC_SPICS0_GPIO7 1
#define FUNC_SPICS0_SPICS0 0
#define PERIPHS_IO_MUX_U_PAD_SPIQ (REG_IO_MUX_BASE + 0x20)
#define FUNC_SPIQ_GPIO8 1
#define FUNC_SPIQ_SPIQ 0
#define PERIPHS_IO_MUX_U_PAD_SPIWP (REG_IO_MUX_BASE + 0x24)
#define FUNC_SPIWP_GPIO9 1
#define FUNC_SPIWP_SPIWP 0
#define PERIPHS_IO_MUX_U_PAD_SPIHD (REG_IO_MUX_BASE + 0x28)
#define FUNC_SPIHD_GPIO10 1
#define FUNC_SPIHD_SPIHD 0
#define PERIPHS_IO_MUX_U_PAD_SPICLK (REG_IO_MUX_BASE + 0x2C)
#define FUNC_SPICLK_GPIO11 1
#define FUNC_SPICLK_SPICLK 0
#define PERIPHS_IO_MUX_U_PAD_SPID (REG_IO_MUX_BASE + 0x30)
#define FUNC_SPID_GPIO12 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_U_PAD_GPIO13 (REG_IO_MUX_BASE + 0x34)
#define FUNC_GPIO13_GPIO13 1
#define FUNC_GPIO13_GPIO13_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO14 (REG_IO_MUX_BASE + 0x38)
#define FUNC_GPIO14_GPIO14 1
#define FUNC_GPIO14_GPIO14_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO15 (REG_IO_MUX_BASE + 0x3C)
#define FUNC_GPIO15_FSPIQ 2
#define FUNC_GPIO15_GPIO15 1
#define FUNC_GPIO15_GPIO15_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO16 (REG_IO_MUX_BASE + 0x40)
#define FUNC_GPIO16_FSPICLK 2
#define FUNC_GPIO16_GPIO16 1
#define FUNC_GPIO16_GPIO16_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO17 (REG_IO_MUX_BASE + 0x44)
#define FUNC_GPIO17_FSPID 2
#define FUNC_GPIO17_GPIO17 1
#define FUNC_GPIO17_GPIO17_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO18 (REG_IO_MUX_BASE + 0x48)
#define FUNC_GPIO18_FSPIWP 2
#define FUNC_GPIO18_GPIO18 1
#define FUNC_GPIO18_GPIO18_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO19 (REG_IO_MUX_BASE + 0x4C)
#define FUNC_GPIO19_FSPIHD 2
#define FUNC_GPIO19_GPIO19 1
#define FUNC_GPIO19_GPIO19_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO20 (REG_IO_MUX_BASE + 0x50)
#define FUNC_GPIO20_FSPICS0 2
#define FUNC_GPIO20_GPIO20 1
#define FUNC_GPIO20_GPIO20_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO21 (REG_IO_MUX_BASE + 0x54)
#define FUNC_GPIO21_GPIO21 1
#define FUNC_GPIO21_GPIO21_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U_PAD_U0RXD (REG_IO_MUX_BASE + 0x5C)
#define FUNC_U0RXD_GPIO23 1
#define FUNC_U0RXD_U0RXD 0
#define PERIPHS_IO_MUX_U_PAD_U0TXD (REG_IO_MUX_BASE + 0x60)
#define FUNC_U0TXD_GPIO24 1
#define FUNC_U0TXD_U0TXD 0
#define PERIPHS_IO_MUX_U_PAD_GPIO25 (REG_IO_MUX_BASE + 0x64)
#define FUNC_GPIO25_GPIO25 1
#define FUNC_GPIO25_GPIO25_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO26 (REG_IO_MUX_BASE + 0x68)
#define FUNC_GPIO26_GPIO26 1
#define FUNC_GPIO26_GPIO26_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO27 (REG_IO_MUX_BASE + 0x6C)
#define FUNC_GPIO27_GPIO27 1
#define FUNC_GPIO27_GPIO27_0 0
#define PERIPHS_IO_MUX_U_PAD_MTMS (REG_IO_MUX_BASE + 0x70)
#define FUNC_MTMS_GPIO28 1
#define FUNC_MTMS_MTMS 0
#define PERIPHS_IO_MUX_U_PAD_MTDI (REG_IO_MUX_BASE + 0x74)
#define FUNC_MTDI_GPIO29 1
#define FUNC_MTDI_MTDI 0
#define PERIPHS_IO_MUX_U_PAD_MTCK (REG_IO_MUX_BASE + 0x78)
#define FUNC_MTCK_GPIO30 1
#define FUNC_MTCK_MTCK 0
#define PERIPHS_IO_MUX_U_PAD_MTDO (REG_IO_MUX_BASE + 0x7C)
#define FUNC_MTDO_GPIO31 1
#define FUNC_MTDO_MTDO 0
#define PERIPHS_IO_MUX_U_PAD_GPIO32 (REG_IO_MUX_BASE + 0x80)
#define FUNC_GPIO32_FSPICLK 2
#define FUNC_GPIO32_GPIO32 1
#define FUNC_GPIO32_GPIO32_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO33 (REG_IO_MUX_BASE + 0x84)
#define FUNC_GPIO33_FSPID 2
#define FUNC_GPIO33_GPIO33 1
#define FUNC_GPIO33_GPIO33_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO34 (REG_IO_MUX_BASE + 0x88)
#define FUNC_GPIO34_GPIO34 1
#define FUNC_GPIO34_GPIO34_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO35 (REG_IO_MUX_BASE + 0x8C)
#define FUNC_GPIO35_GPIO35 1
#define FUNC_GPIO35_GPIO35_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO36 (REG_IO_MUX_BASE + 0x90)
#define FUNC_GPIO36_FSPIQ 2
#define FUNC_GPIO36_GPIO36 1
#define FUNC_GPIO36_GPIO36_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO37 (REG_IO_MUX_BASE + 0x94)
#define FUNC_GPIO37_FSPIWP 2
#define FUNC_GPIO37_GPIO37 1
#define FUNC_GPIO37_GPIO37_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO38 (REG_IO_MUX_BASE + 0x98)
#define FUNC_GPIO38_FSPIHD 2
#define FUNC_GPIO38_GPIO38 1
#define FUNC_GPIO38_GPIO38_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO39 (REG_IO_MUX_BASE + 0x9C)
#define FUNC_GPIO39_FSPICS0 2
#define FUNC_GPIO39_GPIO39 1
#define FUNC_GPIO39_GPIO39_0 0
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0x1FC)
/* IO_MUX_REG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2412160 ; */
/*description: Version control register.*/
#define IO_MUX_REG_DATE 0x0FFFFFFF
#define IO_MUX_REG_DATE_M ((IO_MUX_REG_DATE_V)<<(IO_MUX_REG_DATE_S))
#define IO_MUX_REG_DATE_V 0xFFFFFFF
#define IO_MUX_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

395
components/soc/esp32h4/register/soc/keymng_reg.h Normal file
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@@ -0,0 +1,395 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** KEYMNG_CLK_REG register
* Key Manager clock gate control register
*/
#define KEYMNG_CLK_REG (DR_REG_KEYMNG_BASE + 0x4)
/** KEYMNG_REG_CG_FORCE_ON : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
#define KEYMNG_REG_CG_FORCE_ON (BIT(0))
#define KEYMNG_REG_CG_FORCE_ON_M (KEYMNG_REG_CG_FORCE_ON_V << KEYMNG_REG_CG_FORCE_ON_S)
#define KEYMNG_REG_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_REG_CG_FORCE_ON_S 0
/** KEYMNG_MEM_CG_FORCE_ON : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
#define KEYMNG_MEM_CG_FORCE_ON (BIT(1))
#define KEYMNG_MEM_CG_FORCE_ON_M (KEYMNG_MEM_CG_FORCE_ON_V << KEYMNG_MEM_CG_FORCE_ON_S)
#define KEYMNG_MEM_CG_FORCE_ON_V 0x00000001U
#define KEYMNG_MEM_CG_FORCE_ON_S 1
/** KEYMNG_INT_RAW_REG register
* Key Manager interrupt raw register, valid in level.
*/
#define KEYMNG_INT_RAW_REG (DR_REG_KEYMNG_BASE + 0x8)
/** KEYMNG_PREP_DONE_INT_RAW : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_RAW (BIT(0))
#define KEYMNG_PREP_DONE_INT_RAW_M (KEYMNG_PREP_DONE_INT_RAW_V << KEYMNG_PREP_DONE_INT_RAW_S)
#define KEYMNG_PREP_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_RAW_S 0
/** KEYMNG_PROC_DONE_INT_RAW : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_RAW (BIT(1))
#define KEYMNG_PROC_DONE_INT_RAW_M (KEYMNG_PROC_DONE_INT_RAW_V << KEYMNG_PROC_DONE_INT_RAW_S)
#define KEYMNG_PROC_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_RAW_S 1
/** KEYMNG_POST_DONE_INT_RAW : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_RAW (BIT(2))
#define KEYMNG_POST_DONE_INT_RAW_M (KEYMNG_POST_DONE_INT_RAW_V << KEYMNG_POST_DONE_INT_RAW_S)
#define KEYMNG_POST_DONE_INT_RAW_V 0x00000001U
#define KEYMNG_POST_DONE_INT_RAW_S 2
/** KEYMNG_INT_ST_REG register
* Key Manager interrupt status register.
*/
#define KEYMNG_INT_ST_REG (DR_REG_KEYMNG_BASE + 0xc)
/** KEYMNG_PREP_DONE_INT_ST : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ST (BIT(0))
#define KEYMNG_PREP_DONE_INT_ST_M (KEYMNG_PREP_DONE_INT_ST_V << KEYMNG_PREP_DONE_INT_ST_S)
#define KEYMNG_PREP_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ST_S 0
/** KEYMNG_PROC_DONE_INT_ST : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ST (BIT(1))
#define KEYMNG_PROC_DONE_INT_ST_M (KEYMNG_PROC_DONE_INT_ST_V << KEYMNG_PROC_DONE_INT_ST_S)
#define KEYMNG_PROC_DONE_INT_ST_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ST_S 1
/** KEYMNG_POST_DONE_INT_ST : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ST (BIT(2))
#define KEYMNG_POST_DONE_INT_ST_M (KEYMNG_POST_DONE_INT_ST_V << KEYMNG_POST_DONE_INT_ST_S)
#define KEYMNG_POST_DONE_INT_ST_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ST_S 2
/** KEYMNG_INT_ENA_REG register
* Key Manager interrupt enable register.
*/
#define KEYMNG_INT_ENA_REG (DR_REG_KEYMNG_BASE + 0x10)
/** KEYMNG_PREP_DONE_INT_ENA : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_ENA (BIT(0))
#define KEYMNG_PREP_DONE_INT_ENA_M (KEYMNG_PREP_DONE_INT_ENA_V << KEYMNG_PREP_DONE_INT_ENA_S)
#define KEYMNG_PREP_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_ENA_S 0
/** KEYMNG_PROC_DONE_INT_ENA : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_ENA (BIT(1))
#define KEYMNG_PROC_DONE_INT_ENA_M (KEYMNG_PROC_DONE_INT_ENA_V << KEYMNG_PROC_DONE_INT_ENA_S)
#define KEYMNG_PROC_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_ENA_S 1
/** KEYMNG_POST_DONE_INT_ENA : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_ENA (BIT(2))
#define KEYMNG_POST_DONE_INT_ENA_M (KEYMNG_POST_DONE_INT_ENA_V << KEYMNG_POST_DONE_INT_ENA_S)
#define KEYMNG_POST_DONE_INT_ENA_V 0x00000001U
#define KEYMNG_POST_DONE_INT_ENA_S 2
/** KEYMNG_INT_CLR_REG register
* Key Manager interrupt clear register.
*/
#define KEYMNG_INT_CLR_REG (DR_REG_KEYMNG_BASE + 0x14)
/** KEYMNG_PREP_DONE_INT_CLR : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
#define KEYMNG_PREP_DONE_INT_CLR (BIT(0))
#define KEYMNG_PREP_DONE_INT_CLR_M (KEYMNG_PREP_DONE_INT_CLR_V << KEYMNG_PREP_DONE_INT_CLR_S)
#define KEYMNG_PREP_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PREP_DONE_INT_CLR_S 0
/** KEYMNG_PROC_DONE_INT_CLR : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
#define KEYMNG_PROC_DONE_INT_CLR (BIT(1))
#define KEYMNG_PROC_DONE_INT_CLR_M (KEYMNG_PROC_DONE_INT_CLR_V << KEYMNG_PROC_DONE_INT_CLR_S)
#define KEYMNG_PROC_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_PROC_DONE_INT_CLR_S 1
/** KEYMNG_POST_DONE_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
#define KEYMNG_POST_DONE_INT_CLR (BIT(2))
#define KEYMNG_POST_DONE_INT_CLR_M (KEYMNG_POST_DONE_INT_CLR_V << KEYMNG_POST_DONE_INT_CLR_S)
#define KEYMNG_POST_DONE_INT_CLR_V 0x00000001U
#define KEYMNG_POST_DONE_INT_CLR_S 2
/** KEYMNG_STATIC_REG register
* Key Manager static configuration register
*/
#define KEYMNG_STATIC_REG (DR_REG_KEYMNG_BASE + 0x18)
/** KEYMNG_USE_EFUSE_KEY : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
#define KEYMNG_USE_EFUSE_KEY 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_M (KEYMNG_USE_EFUSE_KEY_V << KEYMNG_USE_EFUSE_KEY_S)
#define KEYMNG_USE_EFUSE_KEY_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_S 0
/** KEYMNG_RND_SWITCH_CYCLE : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
#define KEYMNG_RND_SWITCH_CYCLE 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_M (KEYMNG_RND_SWITCH_CYCLE_V << KEYMNG_RND_SWITCH_CYCLE_S)
#define KEYMNG_RND_SWITCH_CYCLE_V 0x0000001FU
#define KEYMNG_RND_SWITCH_CYCLE_S 5
/** KEYMNG_USE_SW_INIT_KEY : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY (BIT(10))
#define KEYMNG_USE_SW_INIT_KEY_M (KEYMNG_USE_SW_INIT_KEY_V << KEYMNG_USE_SW_INIT_KEY_S)
#define KEYMNG_USE_SW_INIT_KEY_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_S 10
/** KEYMNG_FLASH_KEY_LEN : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_FLASH_KEY_LEN (BIT(11))
#define KEYMNG_FLASH_KEY_LEN_M (KEYMNG_FLASH_KEY_LEN_V << KEYMNG_FLASH_KEY_LEN_S)
#define KEYMNG_FLASH_KEY_LEN_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_S 11
/** KEYMNG_PSRAM_KEY_LEN : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
#define KEYMNG_PSRAM_KEY_LEN (BIT(12))
#define KEYMNG_PSRAM_KEY_LEN_M (KEYMNG_PSRAM_KEY_LEN_V << KEYMNG_PSRAM_KEY_LEN_S)
#define KEYMNG_PSRAM_KEY_LEN_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_S 12
/** KEYMNG_LOCK_REG register
* Key Manager static configuration locker register
*/
#define KEYMNG_LOCK_REG (DR_REG_KEYMNG_BASE + 0x1c)
/** KEYMNG_USE_EFUSE_KEY_LOCK : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
#define KEYMNG_USE_EFUSE_KEY_LOCK 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_M (KEYMNG_USE_EFUSE_KEY_LOCK_V << KEYMNG_USE_EFUSE_KEY_LOCK_S)
#define KEYMNG_USE_EFUSE_KEY_LOCK_V 0x0000001FU
#define KEYMNG_USE_EFUSE_KEY_LOCK_S 0
/** KEYMNG_RND_SWITCH_CYCLE_LOCK : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
#define KEYMNG_RND_SWITCH_CYCLE_LOCK (BIT(5))
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_M (KEYMNG_RND_SWITCH_CYCLE_LOCK_V << KEYMNG_RND_SWITCH_CYCLE_LOCK_S)
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_V 0x00000001U
#define KEYMNG_RND_SWITCH_CYCLE_LOCK_S 5
/** KEYMNG_USE_SW_INIT_KEY_LOCK : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
#define KEYMNG_USE_SW_INIT_KEY_LOCK (BIT(6))
#define KEYMNG_USE_SW_INIT_KEY_LOCK_M (KEYMNG_USE_SW_INIT_KEY_LOCK_V << KEYMNG_USE_SW_INIT_KEY_LOCK_S)
#define KEYMNG_USE_SW_INIT_KEY_LOCK_V 0x00000001U
#define KEYMNG_USE_SW_INIT_KEY_LOCK_S 6
/** KEYMNG_FLASH_KEY_LEN_LOCK : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
#define KEYMNG_FLASH_KEY_LEN_LOCK (BIT(7))
#define KEYMNG_FLASH_KEY_LEN_LOCK_M (KEYMNG_FLASH_KEY_LEN_LOCK_V << KEYMNG_FLASH_KEY_LEN_LOCK_S)
#define KEYMNG_FLASH_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_FLASH_KEY_LEN_LOCK_S 7
/** KEYMNG_PSRAM_KEY_LEN_LOCK : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
#define KEYMNG_PSRAM_KEY_LEN_LOCK (BIT(8))
#define KEYMNG_PSRAM_KEY_LEN_LOCK_M (KEYMNG_PSRAM_KEY_LEN_LOCK_V << KEYMNG_PSRAM_KEY_LEN_LOCK_S)
#define KEYMNG_PSRAM_KEY_LEN_LOCK_V 0x00000001U
#define KEYMNG_PSRAM_KEY_LEN_LOCK_S 8
/** KEYMNG_CONF_REG register
* Key Manager configuration register
*/
#define KEYMNG_CONF_REG (DR_REG_KEYMNG_BASE + 0x20)
/** KEYMNG_KGEN_MODE : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
#define KEYMNG_KGEN_MODE 0x00000007U
#define KEYMNG_KGEN_MODE_M (KEYMNG_KGEN_MODE_V << KEYMNG_KGEN_MODE_S)
#define KEYMNG_KGEN_MODE_V 0x00000007U
#define KEYMNG_KGEN_MODE_S 0
/** KEYMNG_KEY_PURPOSE : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
* ecdsa_key_384_h. Others: reserved.
*/
#define KEYMNG_KEY_PURPOSE 0x0000000FU
#define KEYMNG_KEY_PURPOSE_M (KEYMNG_KEY_PURPOSE_V << KEYMNG_KEY_PURPOSE_S)
#define KEYMNG_KEY_PURPOSE_V 0x0000000FU
#define KEYMNG_KEY_PURPOSE_S 3
/** KEYMNG_START_REG register
* Key Manager control register
*/
#define KEYMNG_START_REG (DR_REG_KEYMNG_BASE + 0x24)
/** KEYMNG_START : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
#define KEYMNG_START (BIT(0))
#define KEYMNG_START_M (KEYMNG_START_V << KEYMNG_START_S)
#define KEYMNG_START_V 0x00000001U
#define KEYMNG_START_S 0
/** KEYMNG_CONTINUE : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
#define KEYMNG_CONTINUE (BIT(1))
#define KEYMNG_CONTINUE_M (KEYMNG_CONTINUE_V << KEYMNG_CONTINUE_S)
#define KEYMNG_CONTINUE_V 0x00000001U
#define KEYMNG_CONTINUE_S 1
/** KEYMNG_STATE_REG register
* Key Manager state register
*/
#define KEYMNG_STATE_REG (DR_REG_KEYMNG_BASE + 0x28)
/** KEYMNG_STATE : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
#define KEYMNG_STATE 0x00000003U
#define KEYMNG_STATE_M (KEYMNG_STATE_V << KEYMNG_STATE_S)
#define KEYMNG_STATE_V 0x00000003U
#define KEYMNG_STATE_S 0
/** KEYMNG_RESULT_REG register
* Key Manager operation result register
*/
#define KEYMNG_RESULT_REG (DR_REG_KEYMNG_BASE + 0x2c)
/** KEYMNG_PROC_RESULT : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
#define KEYMNG_PROC_RESULT (BIT(0))
#define KEYMNG_PROC_RESULT_M (KEYMNG_PROC_RESULT_V << KEYMNG_PROC_RESULT_S)
#define KEYMNG_PROC_RESULT_V 0x00000001U
#define KEYMNG_PROC_RESULT_S 0
/** KEYMNG_KEY_VLD_REG register
* Key Manager key status register
*/
#define KEYMNG_KEY_VLD_REG (DR_REG_KEYMNG_BASE + 0x30)
/** KEYMNG_KEY_ECDSA_192_VLD : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_192_VLD (BIT(0))
#define KEYMNG_KEY_ECDSA_192_VLD_M (KEYMNG_KEY_ECDSA_192_VLD_V << KEYMNG_KEY_ECDSA_192_VLD_S)
#define KEYMNG_KEY_ECDSA_192_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_192_VLD_S 0
/** KEYMNG_KEY_ECDSA_256_VLD : RO; bitpos: [1]; default: 0;
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_256_VLD (BIT(1))
#define KEYMNG_KEY_ECDSA_256_VLD_M (KEYMNG_KEY_ECDSA_256_VLD_V << KEYMNG_KEY_ECDSA_256_VLD_S)
#define KEYMNG_KEY_ECDSA_256_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_256_VLD_S 1
/** KEYMNG_KEY_FLASH_VLD : RO; bitpos: [2]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_FLASH_VLD (BIT(2))
#define KEYMNG_KEY_FLASH_VLD_M (KEYMNG_KEY_FLASH_VLD_V << KEYMNG_KEY_FLASH_VLD_S)
#define KEYMNG_KEY_FLASH_VLD_V 0x00000001U
#define KEYMNG_KEY_FLASH_VLD_S 2
/** KEYMNG_KEY_HMAC_VLD : RO; bitpos: [3]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_HMAC_VLD (BIT(3))
#define KEYMNG_KEY_HMAC_VLD_M (KEYMNG_KEY_HMAC_VLD_V << KEYMNG_KEY_HMAC_VLD_S)
#define KEYMNG_KEY_HMAC_VLD_V 0x00000001U
#define KEYMNG_KEY_HMAC_VLD_S 3
/** KEYMNG_KEY_DS_VLD : RO; bitpos: [4]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_DS_VLD (BIT(4))
#define KEYMNG_KEY_DS_VLD_M (KEYMNG_KEY_DS_VLD_V << KEYMNG_KEY_DS_VLD_S)
#define KEYMNG_KEY_DS_VLD_V 0x00000001U
#define KEYMNG_KEY_DS_VLD_S 4
/** KEYMNG_KEY_PSRAM_VLD : RO; bitpos: [5]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
#define KEYMNG_KEY_PSRAM_VLD (BIT(5))
#define KEYMNG_KEY_PSRAM_VLD_M (KEYMNG_KEY_PSRAM_VLD_V << KEYMNG_KEY_PSRAM_VLD_S)
#define KEYMNG_KEY_PSRAM_VLD_V 0x00000001U
#define KEYMNG_KEY_PSRAM_VLD_S 5
/** KEYMNG_KEY_ECDSA_384_VLD : RO; bitpos: [6]; default: 0;
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
#define KEYMNG_KEY_ECDSA_384_VLD (BIT(6))
#define KEYMNG_KEY_ECDSA_384_VLD_M (KEYMNG_KEY_ECDSA_384_VLD_V << KEYMNG_KEY_ECDSA_384_VLD_S)
#define KEYMNG_KEY_ECDSA_384_VLD_V 0x00000001U
#define KEYMNG_KEY_ECDSA_384_VLD_S 6
/** KEYMNG_HUK_VLD_REG register
* Key Manager HUK status register
*/
#define KEYMNG_HUK_VLD_REG (DR_REG_KEYMNG_BASE + 0x34)
/** KEYMNG_HUK_VALID : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
#define KEYMNG_HUK_VALID (BIT(0))
#define KEYMNG_HUK_VALID_M (KEYMNG_HUK_VALID_V << KEYMNG_HUK_VALID_S)
#define KEYMNG_HUK_VALID_V 0x00000001U
#define KEYMNG_HUK_VALID_S 0
/** KEYMNG_DATE_REG register
* Version control register
*/
#define KEYMNG_DATE_REG (DR_REG_KEYMNG_BASE + 0xfc)
/** KEYMNG_DATE : R/W; bitpos: [27:0]; default: 37781824;
* Key Manager version control register.
*/
#define KEYMNG_DATE 0x0FFFFFFFU
#define KEYMNG_DATE_M (KEYMNG_DATE_V << KEYMNG_DATE_S)
#define KEYMNG_DATE_V 0x0FFFFFFFU
#define KEYMNG_DATE_S 0
/** KEYMNG_ASSIST_INFO_MEM register
* The memory that stores assist key info.
*/
#define KEYMNG_ASSIST_INFO_MEM (DR_REG_KEYMNG_BASE + 0x100)
#define KEYMNG_ASSIST_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_PUBLIC_INFO_MEM register
* The memory that stores public key info.
*/
#define KEYMNG_PUBLIC_INFO_MEM (DR_REG_KEYMNG_BASE + 0x140)
#define KEYMNG_PUBLIC_INFO_MEM_SIZE_BYTES 64
/** KEYMNG_SW_INIT_KEY_MEM register
* The memory that stores software written init key.
*/
#define KEYMNG_SW_INIT_KEY_MEM (DR_REG_KEYMNG_BASE + 0x180)
#define KEYMNG_SW_INIT_KEY_MEM_SIZE_BYTES 32
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/keymng_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Memory data */
/** Group: Clock gate register */
/** Type of clk register
* Key Manager clock gate control register
*/
typedef union {
struct {
/** reg_cg_force_on : R/W; bitpos: [0]; default: 1;
* Write 1 to force on register clock gate.
*/
uint32_t reg_cg_force_on:1;
/** mem_cg_force_on : R/W; bitpos: [1]; default: 0;
* Write 1 to force on memory clock gate.
*/
uint32_t mem_cg_force_on:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_clk_reg_t;
/** Group: Interrupt registers */
/** Type of int_raw register
* Key Manager interrupt raw register, valid in level.
*/
typedef union {
struct {
/** prep_done_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_raw:1;
/** proc_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_raw:1;
/** post_done_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_raw:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_raw_reg_t;
/** Type of int_st register
* Key Manager interrupt status register.
*/
typedef union {
struct {
/** prep_done_int_st : RO; bitpos: [0]; default: 0;
* The masked interrupt status bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_st:1;
/** proc_done_int_st : RO; bitpos: [1]; default: 0;
* The masked interrupt status bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_st:1;
/** post_done_int_st : RO; bitpos: [2]; default: 0;
* The masked interrupt status bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_st_reg_t;
/** Type of int_ena register
* Key Manager interrupt enable register.
*/
typedef union {
struct {
/** prep_done_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the km_prep_done_int interrupt
*/
uint32_t prep_done_int_ena:1;
/** proc_done_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the km_proc_done_int interrupt
*/
uint32_t proc_done_int_ena:1;
/** post_done_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the km_post_done_int interrupt
*/
uint32_t post_done_int_ena:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_ena_reg_t;
/** Type of int_clr register
* Key Manager interrupt clear register.
*/
typedef union {
struct {
/** prep_done_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the km_prep_done_int interrupt
*/
uint32_t prep_done_int_clr:1;
/** proc_done_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the km_proc_done_int interrupt
*/
uint32_t proc_done_int_clr:1;
/** post_done_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the km_post_done_int interrupt
*/
uint32_t post_done_int_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} keymng_int_clr_reg_t;
/** Group: Static configuration registers */
/** Type of static register
* Key Manager static configuration register
*/
typedef union {
struct {
/** use_efuse_key : R/W; bitpos: [4:0]; default: 0;
* Set each bit to choose efuse key instead of key manager deployed key. Each bit
* stands for a key type:bit 4 for psram_key; bit 3 for ds_key; bit 2 for hmac_key;
* bit 1 for flash_key; bit 0 for ecdsa_key
*/
uint32_t use_efuse_key:5;
/** rnd_switch_cycle : R/W; bitpos: [9:5]; default: 15;
* The core clock cycle number to sample one rng input data. Please set it bigger than
* the clock cycle ratio: T_rng/T_km
*/
uint32_t rnd_switch_cycle:5;
/** use_sw_init_key : R/W; bitpos: [10]; default: 0;
* Set this bit to use software written init key instead of efuse_init_key.
*/
uint32_t use_sw_init_key:1;
/** flash_key_len : R/W; bitpos: [11]; default: 0;
* Set this bit to choose flash crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
uint32_t flash_key_len:1;
/** psram_key_len : R/W; bitpos: [12]; default: 0;
* Set this bit to choose psram crypt using xts-aes-256 or xts-aes-128. 1: use
* xts-aes-256. 0: use xts-aes-128.
*/
uint32_t psram_key_len:1;
uint32_t reserved_13:19;
};
uint32_t val;
} keymng_static_reg_t;
/** Type of lock register
* Key Manager static configuration locker register
*/
typedef union {
struct {
/** use_efuse_key_lock : R/W1; bitpos: [4:0]; default: 0;
* Write 1 to lock reg_use_efuse_key. Each bit locks the corresponding bit of
* reg_use_efuse_key.
*/
uint32_t use_efuse_key_lock:5;
/** rnd_switch_cycle_lock : R/W1; bitpos: [5]; default: 0;
* Write 1 to lock reg_rnd_switch_cycle.
*/
uint32_t rnd_switch_cycle_lock:1;
/** use_sw_init_key_lock : R/W1; bitpos: [6]; default: 0;
* Write 1 to lock reg_use_sw_init_key.
*/
uint32_t use_sw_init_key_lock:1;
/** flash_key_len_lock : R/W1; bitpos: [7]; default: 0;
* Write 1 to lock reg_flash_key_len.
*/
uint32_t flash_key_len_lock:1;
/** psram_key_len_lock : R/W1; bitpos: [8]; default: 0;
* Write 1 to lock reg_psram_key_len.
*/
uint32_t psram_key_len_lock:1;
uint32_t reserved_9:23;
};
uint32_t val;
} keymng_lock_reg_t;
/** Group: Configuration registers */
/** Type of conf register
* Key Manager configuration register
*/
typedef union {
struct {
/** kgen_mode : R/W; bitpos: [2:0]; default: 0;
* Set this field to choose the key generator deployment mode. 0: random mode. 1: AES
* mode. 2: ECDH0 mode. 3: ECDH1 mode. 4: recover mode. 5: export mode. 6-7: reserved.
*/
uint32_t kgen_mode:3;
/** key_purpose : R/W; bitpos: [6:3]; default: 0;
* Set this field to choose the key purpose. 1: ecdsa_key_192. 2: ecdsa_key_256. 3:
* flash_256_1_key. 4: flash_256_2_key. 5: flash_128_key. 6: hmac_key. 7: ds_key. 8:
* psram_256_1_key. 9: psram_256_2_key. 10: psram_128_key. 11: ecdsa_key_384_l. 12:
* ecdsa_key_384_h. Others: reserved.
*/
uint32_t key_purpose:4;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_conf_reg_t;
/** Group: Control registers */
/** Type of start register
* Key Manager control register
*/
typedef union {
struct {
/** start : WT; bitpos: [0]; default: 0;
* Write 1 to continue Key Manager operation at LOAD/GAIN state.
*/
uint32_t start:1;
/** continue : WT; bitpos: [1]; default: 0;
* Write 1 to start Key Manager at IDLE state.
*/
uint32_t continue:1;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_start_reg_t;
/** Group: State registers */
/** Type of state register
* Key Manager state register
*/
typedef union {
struct {
/** state : RO; bitpos: [1:0]; default: 0;
* The state of Key Manager. 0: IDLE. 1: LOAD. 2: GAIN. 3: BUSY.
*/
uint32_t state:2;
uint32_t reserved_2:30;
};
uint32_t val;
} keymng_state_reg_t;
/** Group: Result registers */
/** Type of result register
* Key Manager operation result register
*/
typedef union {
struct {
/** proc_result : RO/SS; bitpos: [0]; default: 0;
* The procedure result bit of Key Manager, only valid when Key Manager procedure is
* done. 1: Key Manager procedure succeeded. 0: Key Manager procedure failed.
*/
uint32_t proc_result:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_result_reg_t;
/** Type of key_vld register
* Key Manager key status register
*/
typedef union {
struct {
/** key_ecdsa_192_vld : RO; bitpos: [0]; default: 0;
* The status bit for key_ecdsa_192. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ecdsa_192_vld:1;
/** key_ecdsa_256_vld : RO; bitpos: [1]; default: 0;
* The status bit for key_ecdsa_256. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ecdsa_256_vld:1;
/** key_flash_vld : RO; bitpos: [2]; default: 0;
* The status bit for key_flash. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_flash_vld:1;
/** key_hmac_vld : RO; bitpos: [3]; default: 0;
* The status bit for key_hmac. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_hmac_vld:1;
/** key_ds_vld : RO; bitpos: [4]; default: 0;
* The status bit for key_ds. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ds_vld:1;
/** key_psram_vld : RO; bitpos: [5]; default: 0;
* The status bit for key_psram. 1: The key has been deployed correctly. 0: The key
* has not been deployed yet.
*/
uint32_t key_psram_vld:1;
/** key_ecdsa_384_vld : RO; bitpos: [6]; default: 0;
* The status bit for key_ecdsa_384. 1: The key has been deployed correctly. 0: The
* key has not been deployed yet.
*/
uint32_t key_ecdsa_384_vld:1;
uint32_t reserved_7:25;
};
uint32_t val;
} keymng_key_vld_reg_t;
/** Type of huk_vld register
* Key Manager HUK status register
*/
typedef union {
struct {
/** huk_valid : RO; bitpos: [0]; default: 0;
* The HUK status. 0: HUK is not valid. 1: HUK is valid.
*/
uint32_t huk_valid:1;
uint32_t reserved_1:31;
};
uint32_t val;
} keymng_huk_vld_reg_t;
/** Group: Version register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 37781824;
* Key Manager version control register.
*/
uint32_t date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} keymng_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile keymng_clk_reg_t clk;
volatile keymng_int_raw_reg_t int_raw;
volatile keymng_int_st_reg_t int_st;
volatile keymng_int_ena_reg_t int_ena;
volatile keymng_int_clr_reg_t int_clr;
volatile keymng_static_reg_t static;
volatile keymng_lock_reg_t lock;
volatile keymng_conf_reg_t conf;
volatile keymng_start_reg_t start;
volatile keymng_state_reg_t state;
volatile keymng_result_reg_t result;
volatile keymng_key_vld_reg_t key_vld;
volatile keymng_huk_vld_reg_t huk_vld;
uint32_t reserved_038[49];
volatile keymng_date_reg_t date;
volatile uint32_t assist_info[16];
volatile uint32_t public_info[16];
volatile uint32_t sw_init_key[8];
} keymng_dev_t;
extern keymng_dev_t KEYMNG;
#ifndef __cplusplus
_Static_assert(sizeof(keymng_dev_t) == 0x1a0, "Invalid size of keymng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

469
components/soc/esp32h4/register/soc/lp_analog_peri_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_ANA_BOD_MODE0_CNTL_REG register
* need_des
*/
#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
/** LP_ANA_BOD_MODE1_CNTL_REG register
* need_des
*/
#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
/** LP_ANA_VDD_SOURCE_CNTL_REG register
* need_des
*/
#define LP_ANA_VDD_SOURCE_CNTL_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_ANA_DETMODE_SEL : R/W; bitpos: [7:0]; default: 255;
* need_des
*/
#define LP_ANA_DETMODE_SEL 0x000000FFU
#define LP_ANA_DETMODE_SEL_M (LP_ANA_DETMODE_SEL_V << LP_ANA_DETMODE_SEL_S)
#define LP_ANA_DETMODE_SEL_V 0x000000FFU
#define LP_ANA_DETMODE_SEL_S 0
/** LP_ANA_VGOOD_EVENT_RECORD : RO; bitpos: [15:8]; default: 0;
* need_des
*/
#define LP_ANA_VGOOD_EVENT_RECORD 0x000000FFU
#define LP_ANA_VGOOD_EVENT_RECORD_M (LP_ANA_VGOOD_EVENT_RECORD_V << LP_ANA_VGOOD_EVENT_RECORD_S)
#define LP_ANA_VGOOD_EVENT_RECORD_V 0x000000FFU
#define LP_ANA_VGOOD_EVENT_RECORD_S 8
/** LP_ANA_VBAT_EVENT_RECORD_CLR : WT; bitpos: [23:16]; default: 0;
* need_des
*/
#define LP_ANA_VBAT_EVENT_RECORD_CLR 0x000000FFU
#define LP_ANA_VBAT_EVENT_RECORD_CLR_M (LP_ANA_VBAT_EVENT_RECORD_CLR_V << LP_ANA_VBAT_EVENT_RECORD_CLR_S)
#define LP_ANA_VBAT_EVENT_RECORD_CLR_V 0x000000FFU
#define LP_ANA_VBAT_EVENT_RECORD_CLR_S 16
/** LP_ANA_BOD_SOURCE_ENA : R/W; bitpos: [31:24]; default: 4;
* need_des
*/
#define LP_ANA_BOD_SOURCE_ENA 0x000000FFU
#define LP_ANA_BOD_SOURCE_ENA_M (LP_ANA_BOD_SOURCE_ENA_V << LP_ANA_BOD_SOURCE_ENA_S)
#define LP_ANA_BOD_SOURCE_ENA_V 0x000000FFU
#define LP_ANA_BOD_SOURCE_ENA_S 24
/** LP_ANA_VDDBAT_BOD_CNTL_REG register
* need_des
*/
#define LP_ANA_VDDBAT_BOD_CNTL_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG (BIT(0))
#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S)
#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_V 0x00000001U
#define LP_ANA_VDDBAT_UNDERVOLTAGE_FLAG_S 0
/** LP_ANA_VDDBAT_CHARGER : R/W; bitpos: [10]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGER (BIT(10))
#define LP_ANA_VDDBAT_CHARGER_M (LP_ANA_VDDBAT_CHARGER_V << LP_ANA_VDDBAT_CHARGER_S)
#define LP_ANA_VDDBAT_CHARGER_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGER_S 10
/** LP_ANA_VDDBAT_CNT_CLR : R/W; bitpos: [11]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CNT_CLR (BIT(11))
#define LP_ANA_VDDBAT_CNT_CLR_M (LP_ANA_VDDBAT_CNT_CLR_V << LP_ANA_VDDBAT_CNT_CLR_S)
#define LP_ANA_VDDBAT_CNT_CLR_V 0x00000001U
#define LP_ANA_VDDBAT_CNT_CLR_S 11
/** LP_ANA_VDDBAT_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET 0x000003FFU
#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S)
#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANA_VDDBAT_UPVOLTAGE_TARGET_S 12
/** LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
* need_des
*/
#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET 0x000003FFU
#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S)
#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANA_VDDBAT_UNDERVOLTAGE_TARGET_S 22
/** LP_ANA_VDDBAT_CHARGE_CNTL_REG register
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_CNTL_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG : RO; bitpos: [0]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG (BIT(0))
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S)
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_FLAG_S 0
/** LP_ANA_VDDBAT_CHARGE_CHARGER : R/W; bitpos: [10]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_CHARGER (BIT(10))
#define LP_ANA_VDDBAT_CHARGE_CHARGER_M (LP_ANA_VDDBAT_CHARGE_CHARGER_V << LP_ANA_VDDBAT_CHARGE_CHARGER_S)
#define LP_ANA_VDDBAT_CHARGE_CHARGER_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_CHARGER_S 10
/** LP_ANA_VDDBAT_CHARGE_CNT_CLR : R/W; bitpos: [11]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_CNT_CLR (BIT(11))
#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_M (LP_ANA_VDDBAT_CHARGE_CNT_CLR_V << LP_ANA_VDDBAT_CHARGE_CNT_CLR_S)
#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_CNT_CLR_S 11
/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET : R/W; bitpos: [21:12]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET 0x000003FFU
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S)
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_TARGET_S 12
/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET : R/W; bitpos: [31:22]; default: 1023;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET 0x000003FFU
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S)
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22
/** LP_ANA_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
/** LP_ANA_PG_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANA_PG_GLITCH_CNTL_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_ANA_POWER_GLITCH_RESET_ENA : R/W; bitpos: [31:26]; default: 0;
* need_des
*/
#define LP_ANA_POWER_GLITCH_RESET_ENA 0x0000003FU
#define LP_ANA_POWER_GLITCH_RESET_ENA_M (LP_ANA_POWER_GLITCH_RESET_ENA_V << LP_ANA_POWER_GLITCH_RESET_ENA_S)
#define LP_ANA_POWER_GLITCH_RESET_ENA_V 0x0000003FU
#define LP_ANA_POWER_GLITCH_RESET_ENA_S 26
/** LP_ANA_FIB_ENABLE_REG register
* need_des
*/
#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:24]; default: 255;
* need_des
*/
#define LP_ANA_ANA_FIB_ENA 0x000000FFU
#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
#define LP_ANA_ANA_FIB_ENA_V 0x000000FFU
#define LP_ANA_ANA_FIB_ENA_S 24
#define LP_ANALOG_PERI_LP_ANA_FIB_GLITCH_RST BIT(0)
#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
#define LP_ANALOG_PERI_LP_ANA_FIB_SUPER_WDT_RST BIT(2)
/** LP_ANA_INT_RAW_REG register
* need_des
*/
#define LP_ANA_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW (BIT(27))
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S)
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_RAW_S 27
/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW (BIT(28))
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S)
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_RAW_S 28
/** LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW (BIT(29))
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S)
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_V 0x00000001U
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_RAW_S 29
/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW (BIT(30))
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S)
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_V 0x00000001U
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_RAW_S 30
/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_RAW_S 31
/** LP_ANA_INT_ST_REG register
* need_des
*/
#define LP_ANA_INT_ST_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST : RO; bitpos: [27]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST (BIT(27))
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S)
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ST_S 27
/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST : RO; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST (BIT(28))
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S)
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ST_S 28
/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ST : RO; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST (BIT(29))
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S)
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_V 0x00000001U
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ST_S 29
/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST : RO; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST (BIT(30))
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S)
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_V 0x00000001U
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ST_S 30
/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ST_S 31
/** LP_ANA_INT_ENA_REG register
* need_des
*/
#define LP_ANA_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA (BIT(27))
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S)
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_ENA_S 27
/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA (BIT(28))
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S)
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_ENA_S 28
/** LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA (BIT(29))
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S)
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_V 0x00000001U
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_ENA_S 29
/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA : R/W; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA (BIT(30))
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S)
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_V 0x00000001U
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_ENA_S 30
/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_ENA_S 31
/** LP_ANA_INT_CLR_REG register
* need_des
*/
#define LP_ANA_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR : WT; bitpos: [27]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR (BIT(27))
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S)
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UPVOLTAGE_INT_CLR_S 27
/** LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR : WT; bitpos: [28]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR (BIT(28))
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S)
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_V 0x00000001U
#define LP_ANA_VDDBAT_CHARGE_UNDERVOLTAGE_INT_CLR_S 28
/** LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR : WT; bitpos: [29]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR (BIT(29))
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S)
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_V 0x00000001U
#define LP_ANA_VDDBAT_UPVOLTAGE_INT_CLR_S 29
/** LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR : WT; bitpos: [30]; default: 0;
* need_des
*/
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR (BIT(30))
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_M (LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V << LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S)
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_V 0x00000001U
#define LP_ANA_VDDBAT_UNDERVOLTAGE_INT_CLR_S 30
/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_INT_CLR_S 31
/** LP_ANA_LP_INT_RAW_REG register
* need_des
*/
#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_AON_BASE + 0x30)
/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
/** LP_ANA_LP_INT_ST_REG register
* need_des
*/
#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
/** LP_ANA_LP_INT_ENA_REG register
* need_des
*/
#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
/** LP_ANA_LP_INT_CLR_REG register
* need_des
*/
#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
/** LP_ANA_DATE_REG register
* need_des
*/
#define LP_ANA_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 37818752;
* need_des
*/
#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU
#define LP_ANA_LP_ANA_DATE_S 0
/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANA_CLK_EN (BIT(31))
#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
#define LP_ANA_CLK_EN_V 0x00000001U
#define LP_ANA_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

420
components/soc/esp32h4/register/soc/lp_analog_peri_struct.h Normal file
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@@ -0,0 +1,420 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of ana_bod_mode0_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:6;
/** ana_bod_mode0_close_flash_ena : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_close_flash_ena:1;
/** ana_bod_mode0_pd_rf_ena : R/W; bitpos: [7]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_pd_rf_ena:1;
/** ana_bod_mode0_intr_wait : R/W; bitpos: [17:8]; default: 1;
* need_des
*/
uint32_t ana_bod_mode0_intr_wait:10;
/** ana_bod_mode0_reset_wait : R/W; bitpos: [27:18]; default: 1023;
* need_des
*/
uint32_t ana_bod_mode0_reset_wait:10;
/** ana_bod_mode0_cnt_clr : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_cnt_clr:1;
/** ana_bod_mode0_intr_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_intr_ena:1;
/** ana_bod_mode0_reset_sel : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_reset_sel:1;
/** ana_bod_mode0_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode0_cntl_reg_t;
/** Type of ana_bod_mode1_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ana_bod_mode1_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode1_reset_ena:1;
};
uint32_t val;
} lp_ana_bod_mode1_cntl_reg_t;
/** Type of ana_vdd_source_cntl register
* need_des
*/
typedef union {
struct {
/** ana_detmode_sel : R/W; bitpos: [7:0]; default: 255;
* need_des
*/
uint32_t ana_detmode_sel:8;
/** ana_vgood_event_record : RO; bitpos: [15:8]; default: 0;
* need_des
*/
uint32_t ana_vgood_event_record:8;
/** ana_vbat_event_record_clr : WT; bitpos: [23:16]; default: 0;
* need_des
*/
uint32_t ana_vbat_event_record_clr:8;
/** ana_bod_source_ena : R/W; bitpos: [31:24]; default: 4;
* need_des
*/
uint32_t ana_bod_source_ena:8;
};
uint32_t val;
} lp_ana_vdd_source_cntl_reg_t;
/** Type of ana_vddbat_bod_cntl register
* need_des
*/
typedef union {
struct {
/** ana_vddbat_undervoltage_flag : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t ana_vddbat_undervoltage_flag:1;
uint32_t reserved_1:9;
/** ana_vddbat_charger : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charger:1;
/** ana_vddbat_cnt_clr : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t ana_vddbat_cnt_clr:1;
/** ana_vddbat_upvoltage_target : R/W; bitpos: [21:12]; default: 0;
* need_des
*/
uint32_t ana_vddbat_upvoltage_target:10;
/** ana_vddbat_undervoltage_target : R/W; bitpos: [31:22]; default: 1023;
* need_des
*/
uint32_t ana_vddbat_undervoltage_target:10;
};
uint32_t val;
} lp_ana_vddbat_bod_cntl_reg_t;
/** Type of ana_vddbat_charge_cntl register
* need_des
*/
typedef union {
struct {
/** ana_vddbat_charge_undervoltage_flag : RO; bitpos: [0]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_undervoltage_flag:1;
uint32_t reserved_1:9;
/** ana_vddbat_charge_charger : R/W; bitpos: [10]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_charger:1;
/** ana_vddbat_charge_cnt_clr : R/W; bitpos: [11]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_cnt_clr:1;
/** ana_vddbat_charge_upvoltage_target : R/W; bitpos: [21:12]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_upvoltage_target:10;
/** ana_vddbat_charge_undervoltage_target : R/W; bitpos: [31:22]; default: 1023;
* need_des
*/
uint32_t ana_vddbat_charge_undervoltage_target:10;
};
uint32_t val;
} lp_ana_vddbat_charge_cntl_reg_t;
/** Type of ana_ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ana_ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_ana_ck_glitch_cntl_reg_t;
/** Type of ana_pg_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** ana_power_glitch_reset_ena : R/W; bitpos: [31:26]; default: 0;
* need_des
*/
uint32_t ana_power_glitch_reset_ena:6;
};
uint32_t val;
} lp_ana_pg_glitch_cntl_reg_t;
/** Type of ana_fib_enable register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** ana_ana_fib_ena : R/W; bitpos: [31:24]; default: 255;
* need_des
*/
uint32_t ana_ana_fib_ena:8;
};
uint32_t val;
} lp_ana_fib_enable_reg_t;
/** Type of ana_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** ana_vddbat_charge_upvoltage_int_raw : R/WTC/SS; bitpos: [27]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_upvoltage_int_raw:1;
/** ana_vddbat_charge_undervoltage_int_raw : R/WTC/SS; bitpos: [28]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_undervoltage_int_raw:1;
/** ana_vddbat_upvoltage_int_raw : R/WTC/SS; bitpos: [29]; default: 0;
* need_des
*/
uint32_t ana_vddbat_upvoltage_int_raw:1;
/** ana_vddbat_undervoltage_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* need_des
*/
uint32_t ana_vddbat_undervoltage_int_raw:1;
/** ana_bod_mode0_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_int_raw:1;
};
uint32_t val;
} lp_ana_int_raw_reg_t;
/** Type of ana_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** ana_vddbat_charge_upvoltage_int_st : RO; bitpos: [27]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_upvoltage_int_st:1;
/** ana_vddbat_charge_undervoltage_int_st : RO; bitpos: [28]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_undervoltage_int_st:1;
/** ana_vddbat_upvoltage_int_st : RO; bitpos: [29]; default: 0;
* need_des
*/
uint32_t ana_vddbat_upvoltage_int_st:1;
/** ana_vddbat_undervoltage_int_st : RO; bitpos: [30]; default: 0;
* need_des
*/
uint32_t ana_vddbat_undervoltage_int_st:1;
/** ana_bod_mode0_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_int_st:1;
};
uint32_t val;
} lp_ana_int_st_reg_t;
/** Type of ana_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** ana_vddbat_charge_upvoltage_int_ena : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_upvoltage_int_ena:1;
/** ana_vddbat_charge_undervoltage_int_ena : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_undervoltage_int_ena:1;
/** ana_vddbat_upvoltage_int_ena : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t ana_vddbat_upvoltage_int_ena:1;
/** ana_vddbat_undervoltage_int_ena : R/W; bitpos: [30]; default: 0;
* need_des
*/
uint32_t ana_vddbat_undervoltage_int_ena:1;
/** ana_bod_mode0_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_int_ena:1;
};
uint32_t val;
} lp_ana_int_ena_reg_t;
/** Type of ana_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** ana_vddbat_charge_upvoltage_int_clr : WT; bitpos: [27]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_upvoltage_int_clr:1;
/** ana_vddbat_charge_undervoltage_int_clr : WT; bitpos: [28]; default: 0;
* need_des
*/
uint32_t ana_vddbat_charge_undervoltage_int_clr:1;
/** ana_vddbat_upvoltage_int_clr : WT; bitpos: [29]; default: 0;
* need_des
*/
uint32_t ana_vddbat_upvoltage_int_clr:1;
/** ana_vddbat_undervoltage_int_clr : WT; bitpos: [30]; default: 0;
* need_des
*/
uint32_t ana_vddbat_undervoltage_int_clr:1;
/** ana_bod_mode0_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_int_clr:1;
};
uint32_t val;
} lp_ana_int_clr_reg_t;
/** Type of ana_lp_int_raw register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ana_bod_mode0_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_lp_int_raw:1;
};
uint32_t val;
} lp_ana_lp_int_raw_reg_t;
/** Type of ana_lp_int_st register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ana_bod_mode0_lp_int_st : RO; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_lp_int_st:1;
};
uint32_t val;
} lp_ana_lp_int_st_reg_t;
/** Type of ana_lp_int_ena register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ana_bod_mode0_lp_int_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_lp_int_ena:1;
};
uint32_t val;
} lp_ana_lp_int_ena_reg_t;
/** Type of ana_lp_int_clr register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ana_bod_mode0_lp_int_clr : WT; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_bod_mode0_lp_int_clr:1;
};
uint32_t val;
} lp_ana_lp_int_clr_reg_t;
/** Type of ana_date register
* need_des
*/
typedef union {
struct {
/** ana_lp_ana_date : R/W; bitpos: [30:0]; default: 37818752;
* need_des
*/
uint32_t ana_lp_ana_date:31;
/** ana_clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ana_clk_en:1;
};
uint32_t val;
} lp_ana_date_reg_t;
typedef struct {
volatile lp_ana_bod_mode0_cntl_reg_t ana_bod_mode0_cntl;
volatile lp_ana_bod_mode1_cntl_reg_t ana_bod_mode1_cntl;
volatile lp_ana_vdd_source_cntl_reg_t ana_vdd_source_cntl;
volatile lp_ana_vddbat_bod_cntl_reg_t ana_vddbat_bod_cntl;
volatile lp_ana_vddbat_charge_cntl_reg_t ana_vddbat_charge_cntl;
volatile lp_ana_ck_glitch_cntl_reg_t ana_ck_glitch_cntl;
volatile lp_ana_pg_glitch_cntl_reg_t ana_pg_glitch_cntl;
volatile lp_ana_fib_enable_reg_t ana_fib_enable;
volatile lp_ana_int_raw_reg_t ana_int_raw;
volatile lp_ana_int_st_reg_t ana_int_st;
volatile lp_ana_int_ena_reg_t ana_int_ena;
volatile lp_ana_int_clr_reg_t ana_int_clr;
volatile lp_ana_lp_int_raw_reg_t ana_lp_int_raw;
volatile lp_ana_lp_int_st_reg_t ana_lp_int_st;
volatile lp_ana_lp_int_ena_reg_t ana_lp_int_ena;
volatile lp_ana_lp_int_clr_reg_t ana_lp_int_clr;
uint32_t reserved_040[239];
volatile lp_ana_date_reg_t ana_date;
} lp_ana_dev_t;
extern lp_ana_dev_t LP_ANA_PERI;
#ifndef __cplusplus
_Static_assert(sizeof(lp_ana_dev_t) == 0x400, "Invalid size of lp_ana_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_aon_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_AON_STORE0_REG register
* store the software massege0 in always-on field
*/
#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0)
/** LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0;
* store the software massege0 in always-on field
*/
#define LP_AON_LP_AON_STORE0 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S)
#define LP_AON_LP_AON_STORE0_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE0_S 0
/** LP_AON_STORE1_REG register
* store the software massege1 in always-on field
*/
#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4)
/** LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0;
* store the software massege1 in always-on field
*/
#define LP_AON_LP_AON_STORE1 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S)
#define LP_AON_LP_AON_STORE1_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE1_S 0
/** LP_AON_STORE2_REG register
* store the software massege2 in always-on field
*/
#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8)
/** LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0;
* store the software massege2 in always-on field
*/
#define LP_AON_LP_AON_STORE2 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S)
#define LP_AON_LP_AON_STORE2_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE2_S 0
/** LP_AON_STORE3_REG register
* store the software massege3 in always-on field
*/
#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc)
/** LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0;
* store the software massege3 in always-on field
*/
#define LP_AON_LP_AON_STORE3 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S)
#define LP_AON_LP_AON_STORE3_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE3_S 0
/** LP_AON_STORE4_REG register
* store the software massege4 in always-on field
*/
#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10)
/** LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0;
* store the software massege4 in always-on field
*/
#define LP_AON_LP_AON_STORE4 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S)
#define LP_AON_LP_AON_STORE4_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE4_S 0
/** LP_AON_STORE5_REG register
* store the software massege5 in always-on field
*/
#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14)
/** LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0;
* store the software massege5 in always-on field
*/
#define LP_AON_LP_AON_STORE5 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S)
#define LP_AON_LP_AON_STORE5_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE5_S 0
/** LP_AON_STORE6_REG register
* store the software massege6 in always-on field
*/
#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18)
/** LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0;
* store the software massege6 in always-on field
*/
#define LP_AON_LP_AON_STORE6 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S)
#define LP_AON_LP_AON_STORE6_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE6_S 0
/** LP_AON_STORE7_REG register
* store the software massege7 in always-on field
*/
#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c)
/** LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0;
* store the software massege7 in always-on field
*/
#define LP_AON_LP_AON_STORE7 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S)
#define LP_AON_LP_AON_STORE7_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE7_S 0
/** LP_AON_STORE8_REG register
* store the software massege8 in always-on field
*/
#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20)
/** LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0;
* store the software massege8 in always-on field
*/
#define LP_AON_LP_AON_STORE8 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S)
#define LP_AON_LP_AON_STORE8_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE8_S 0
/** LP_AON_STORE9_REG register
* store the software massege9 in always-on field
*/
#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24)
/** LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0;
* store the software massege9 in always-on field
*/
#define LP_AON_LP_AON_STORE9 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S)
#define LP_AON_LP_AON_STORE9_V 0xFFFFFFFFU
#define LP_AON_LP_AON_STORE9_S 0
/** LP_AON_GPIO_MUX_REG register
* select the lp io controlled by hp iomux or lp iomux
*/
#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28)
/** LP_AON_GPIO_MUX_SEL : R/W; bitpos: [5:0]; default: 0;
* select the lp io 0~5 controlled by hp iomux or lp iomux
* 1: controlled by lp iomux
* 0: controlled by hp iomux
*/
#define LP_AON_GPIO_MUX_SEL 0x0000003FU
#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S)
#define LP_AON_GPIO_MUX_SEL_V 0x0000003FU
#define LP_AON_GPIO_MUX_SEL_S 0
/** LP_AON_GPIO_HOLD0_REG register
* configure all io hold
*/
#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c)
/** LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0;
* configure io0~28 hold enable,when io in hold status, all io configure and output
* will be latch , input function is useful
*/
#define LP_AON_GPIO_HOLD0 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S)
#define LP_AON_GPIO_HOLD0_V 0xFFFFFFFFU
#define LP_AON_GPIO_HOLD0_S 0
/** LP_AON_SYS_CFG_REG register
* configure system register
*/
#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34)
/** LP_AON_FIB_REG : RO; bitpos: [7:0]; default: 255;
* get fib reg information
*/
#define LP_AON_FIB_REG 0x000000FFU
#define LP_AON_FIB_REG_M (LP_AON_FIB_REG_V << LP_AON_FIB_REG_S)
#define LP_AON_FIB_REG_V 0x000000FFU
#define LP_AON_FIB_REG_S 0
/** LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0;
* enable hp system reset by software or not
* 1: reset
* 0: no operation
*/
#define LP_AON_HPSYS_SW_RESET (BIT(31))
#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S)
#define LP_AON_HPSYS_SW_RESET_V 0x00000001U
#define LP_AON_HPSYS_SW_RESET_S 31
/** LP_AON_CPUCORE_CFG_REG register
* configure core reset register
*/
#define LP_AON_CPUCORE_CFG_REG (DR_REG_LP_AON_BASE + 0x38)
/** LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0;
* enable cpu 0 entry stall status
* 0x86: entry stall status
* Others : no operation
*/
#define LP_AON_CPU_CORE0_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S)
#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE0_SW_STALL_S 0
/** LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [8]; default: 0;
* enable core 0 reset by software
* 1: reset
* 0: no operation
*/
#define LP_AON_CPU_CORE0_SW_RESET (BIT(8))
#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S)
#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE0_SW_RESET_S 8
/** LP_AON_CPU_CORE1_SW_STALL : R/W; bitpos: [23:16]; default: 0;
* enable core 1 entry stall status
* 0x86: entry stall status
* Others : no operation
*/
#define LP_AON_CPU_CORE1_SW_STALL 0x000000FFU
#define LP_AON_CPU_CORE1_SW_STALL_M (LP_AON_CPU_CORE1_SW_STALL_V << LP_AON_CPU_CORE1_SW_STALL_S)
#define LP_AON_CPU_CORE1_SW_STALL_V 0x000000FFU
#define LP_AON_CPU_CORE1_SW_STALL_S 16
/** LP_AON_CPU_CORE1_SW_RESET : WT; bitpos: [24]; default: 0;
* enable core1 reset by software
* 1: reset
* 0: no operation
*/
#define LP_AON_CPU_CORE1_SW_RESET (BIT(24))
#define LP_AON_CPU_CORE1_SW_RESET_M (LP_AON_CPU_CORE1_SW_RESET_V << LP_AON_CPU_CORE1_SW_RESET_S)
#define LP_AON_CPU_CORE1_SW_RESET_V 0x00000001U
#define LP_AON_CPU_CORE1_SW_RESET_S 24
/** LP_AON_SYSTIMER_STALL_SEL : R/W; bitpos: [31]; default: 0;
* delete which core run_stall to lp_timer
* 1: core1
* 0: core0
*/
#define LP_AON_SYSTIMER_STALL_SEL (BIT(31))
#define LP_AON_SYSTIMER_STALL_SEL_M (LP_AON_SYSTIMER_STALL_SEL_V << LP_AON_SYSTIMER_STALL_SEL_S)
#define LP_AON_SYSTIMER_STALL_SEL_V 0x00000001U
#define LP_AON_SYSTIMER_STALL_SEL_S 31
/** LP_AON_IO_MUX_REG register
* configure hp iomux reset bypass
*/
#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c)
/** LP_AON_IO_MUX_PULL_LDO : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
#define LP_AON_IO_MUX_PULL_LDO 0x00000007U
#define LP_AON_IO_MUX_PULL_LDO_M (LP_AON_IO_MUX_PULL_LDO_V << LP_AON_IO_MUX_PULL_LDO_S)
#define LP_AON_IO_MUX_PULL_LDO_V 0x00000007U
#define LP_AON_IO_MUX_PULL_LDO_S 28
/** LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* bypass hp iomux reset from hp system reset event
* 1: bypass
* 0: no operation
*/
#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31))
#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S)
#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001U
#define LP_AON_IO_MUX_RESET_DISABLE_S 31
/** LP_AON_EXT_WAKEUP_CNTL_REG register
* configure alwayson external io wakeup
*/
#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40)
/** LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [15:0]; default: 0;
* enable io0~15 bit map use to external wakeup
* 1: enable
* 0: disable
*/
#define LP_AON_EXT_WAKEUP_SEL 0x0000FFFFU
#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S)
#define LP_AON_EXT_WAKEUP_SEL_V 0x0000FFFFU
#define LP_AON_EXT_WAKEUP_SEL_S 0
/** LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [31:16]; default: 0;
* select external wakeup io level
* 1: io high level wakeup
* 0: io low level wakeup
*/
#define LP_AON_EXT_WAKEUP_LV 0x0000FFFFU
#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S)
#define LP_AON_EXT_WAKEUP_LV_V 0x0000FFFFU
#define LP_AON_EXT_WAKEUP_LV_S 16
/** LP_AON_EXT_WAKEUP_CNTL1_REG register
* configure alwayson external io wakeup
*/
#define LP_AON_EXT_WAKEUP_CNTL1_REG (DR_REG_LP_AON_BASE + 0x44)
/** LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [15:0]; default: 0;
* get external wakeup status bitmap
*/
#define LP_AON_EXT_WAKEUP_STATUS 0x0000FFFFU
#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S)
#define LP_AON_EXT_WAKEUP_STATUS_V 0x0000FFFFU
#define LP_AON_EXT_WAKEUP_STATUS_S 0
/** LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [30]; default: 0;
* clear external wakeup status
* 1: clear
* 0: no operation
*/
#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(30))
#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S)
#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001U
#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 30
/** LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0;
* enable external filter or not
* 1: enable
* 0: disable
*/
#define LP_AON_EXT_WAKEUP_FILTER (BIT(31))
#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S)
#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001U
#define LP_AON_EXT_WAKEUP_FILTER_S 31
/** LP_AON_USB_REG register
* configure usb reset bypass
*/
#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x48)
/** LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0;
* bypass usb reset from hp system reset event
* 1: bypass
* 0: no operation
*/
#define LP_AON_USB_RESET_DISABLE (BIT(31))
#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S)
#define LP_AON_USB_RESET_DISABLE_V 0x00000001U
#define LP_AON_USB_RESET_DISABLE_S 31
/** LP_AON_LPBUS_REG register
* Select lp memory bus
*/
#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x4c)
/** LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1;
* get current lp memory bus fsm status
*/
#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28))
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S)
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28
/** LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1;
* get current lp memory bus mode
*/
#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29))
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S)
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29
/** LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0;
* enable reg_fast_mem_sel configure
* 1: enable
* 0: no operation
*/
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30))
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S)
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30
/** LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1;
* select lp memory bus is high speed mode or low speed mode
* 1: high speed from hp system ahb
* 0: low speed from lp system
*/
#define LP_AON_FAST_MEM_MUX_SEL (BIT(31))
#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S)
#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001U
#define LP_AON_FAST_MEM_MUX_SEL_S 31
/** LP_AON_BACKUP_DMA_CFG0_REG register
* configure regdma always on register
*/
#define LP_AON_BACKUP_DMA_CFG0_REG (DR_REG_LP_AON_BASE + 0x70)
/** LP_AON_BURST_LIMIT_AON : R/W; bitpos: [4:0]; default: 10;
* Set this field to configure max value of burst in single transfer.
*/
#define LP_AON_BURST_LIMIT_AON 0x0000001FU
#define LP_AON_BURST_LIMIT_AON_M (LP_AON_BURST_LIMIT_AON_V << LP_AON_BURST_LIMIT_AON_S)
#define LP_AON_BURST_LIMIT_AON_V 0x0000001FU
#define LP_AON_BURST_LIMIT_AON_S 0
/** LP_AON_READ_INTERVAL_AON : R/W; bitpos: [11:5]; default: 10;
* Set this field to configure read registers' interval time in reading mode.
*/
#define LP_AON_READ_INTERVAL_AON 0x0000007FU
#define LP_AON_READ_INTERVAL_AON_M (LP_AON_READ_INTERVAL_AON_V << LP_AON_READ_INTERVAL_AON_S)
#define LP_AON_READ_INTERVAL_AON_V 0x0000007FU
#define LP_AON_READ_INTERVAL_AON_S 5
/** LP_AON_BRANCH_LINK_LENGTH_AON : R/W; bitpos: [15:12]; default: 0;
* Set this field to configure link address.
*/
#define LP_AON_BRANCH_LINK_LENGTH_AON 0x0000000FU
#define LP_AON_BRANCH_LINK_LENGTH_AON_M (LP_AON_BRANCH_LINK_LENGTH_AON_V << LP_AON_BRANCH_LINK_LENGTH_AON_S)
#define LP_AON_BRANCH_LINK_LENGTH_AON_V 0x0000000FU
#define LP_AON_BRANCH_LINK_LENGTH_AON_S 12
/** LP_AON_REGDMA_ERROR : RO; bitpos: [18:16]; default: 0;
* regdma error code
*/
#define LP_AON_REGDMA_ERROR 0x00000007U
#define LP_AON_REGDMA_ERROR_M (LP_AON_REGDMA_ERROR_V << LP_AON_REGDMA_ERROR_S)
#define LP_AON_REGDMA_ERROR_V 0x00000007U
#define LP_AON_REGDMA_ERROR_S 16
/** LP_AON_BACKUP_DMA_CFG1_REG register
* configure regdma always on register
*/
#define LP_AON_BACKUP_DMA_CFG1_REG (DR_REG_LP_AON_BASE + 0x74)
/** LP_AON_LINK_WAIT_TOUT_THRES_AON : R/W; bitpos: [9:0]; default: 100;
* Set this field to configure the number of consecutive links of link list.
*/
#define LP_AON_LINK_WAIT_TOUT_THRES_AON 0x000003FFU
#define LP_AON_LINK_WAIT_TOUT_THRES_AON_M (LP_AON_LINK_WAIT_TOUT_THRES_AON_V << LP_AON_LINK_WAIT_TOUT_THRES_AON_S)
#define LP_AON_LINK_WAIT_TOUT_THRES_AON_V 0x000003FFU
#define LP_AON_LINK_WAIT_TOUT_THRES_AON_S 0
/** LP_AON_LINK_WORK_TOUT_THRES_AON : R/W; bitpos: [19:10]; default: 100;
* Set this field to configure maximum waiting time in waiting mode.
*/
#define LP_AON_LINK_WORK_TOUT_THRES_AON 0x000003FFU
#define LP_AON_LINK_WORK_TOUT_THRES_AON_M (LP_AON_LINK_WORK_TOUT_THRES_AON_V << LP_AON_LINK_WORK_TOUT_THRES_AON_S)
#define LP_AON_LINK_WORK_TOUT_THRES_AON_V 0x000003FFU
#define LP_AON_LINK_WORK_TOUT_THRES_AON_S 10
/** LP_AON_LINK_BACKUP_TOUT_THRES_AON : R/W; bitpos: [29:20]; default: 100;
* Set this field to configure maximum waiting time in backup mode.
*/
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON 0x000003FFU
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_M (LP_AON_LINK_BACKUP_TOUT_THRES_AON_V << LP_AON_LINK_BACKUP_TOUT_THRES_AON_S)
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_V 0x000003FFU
#define LP_AON_LINK_BACKUP_TOUT_THRES_AON_S 20
/** LP_AON_BACKUP_DMA_CFG2_REG register
* configure regdma always on register
*/
#define LP_AON_BACKUP_DMA_CFG2_REG (DR_REG_LP_AON_BASE + 0x78)
/** LP_AON_LINK_ADDR_AON : R/W; bitpos: [31:0]; default: 0;
* Set this field to configure link address.
*/
#define LP_AON_LINK_ADDR_AON 0xFFFFFFFFU
#define LP_AON_LINK_ADDR_AON_M (LP_AON_LINK_ADDR_AON_V << LP_AON_LINK_ADDR_AON_S)
#define LP_AON_LINK_ADDR_AON_V 0xFFFFFFFFU
#define LP_AON_LINK_ADDR_AON_S 0
/** LP_AON_MEM_CTRL_REG register
* configure rmemory power in lp system register
*/
#define LP_AON_MEM_CTRL_REG (DR_REG_LP_AON_BASE + 0x7c)
/** LP_AON_EFUSE_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
* Configures efuse memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define LP_AON_EFUSE_MEM_LP_MODE 0x00000003U
#define LP_AON_EFUSE_MEM_LP_MODE_M (LP_AON_EFUSE_MEM_LP_MODE_V << LP_AON_EFUSE_MEM_LP_MODE_S)
#define LP_AON_EFUSE_MEM_LP_MODE_V 0x00000003U
#define LP_AON_EFUSE_MEM_LP_MODE_S 0
/** LP_AON_EFUSE_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down efuse memory.
*/
#define LP_AON_EFUSE_MEM_LP_EN (BIT(2))
#define LP_AON_EFUSE_MEM_LP_EN_M (LP_AON_EFUSE_MEM_LP_EN_V << LP_AON_EFUSE_MEM_LP_EN_S)
#define LP_AON_EFUSE_MEM_LP_EN_V 0x00000001U
#define LP_AON_EFUSE_MEM_LP_EN_S 2
/** LP_AON_EFUSE_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control efuse memory, disable hardware control.
*/
#define LP_AON_EFUSE_MEM_FORCE_CTRL (BIT(3))
#define LP_AON_EFUSE_MEM_FORCE_CTRL_M (LP_AON_EFUSE_MEM_FORCE_CTRL_V << LP_AON_EFUSE_MEM_FORCE_CTRL_S)
#define LP_AON_EFUSE_MEM_FORCE_CTRL_V 0x00000001U
#define LP_AON_EFUSE_MEM_FORCE_CTRL_S 3
/** LP_AON_HUK_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 2;
* Configures huk memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define LP_AON_HUK_MEM_LP_MODE 0x00000003U
#define LP_AON_HUK_MEM_LP_MODE_M (LP_AON_HUK_MEM_LP_MODE_V << LP_AON_HUK_MEM_LP_MODE_S)
#define LP_AON_HUK_MEM_LP_MODE_V 0x00000003U
#define LP_AON_HUK_MEM_LP_MODE_S 4
/** LP_AON_HUK_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
* Set this bit to power down huk memory.
*/
#define LP_AON_HUK_MEM_LP_EN (BIT(6))
#define LP_AON_HUK_MEM_LP_EN_M (LP_AON_HUK_MEM_LP_EN_V << LP_AON_HUK_MEM_LP_EN_S)
#define LP_AON_HUK_MEM_LP_EN_V 0x00000001U
#define LP_AON_HUK_MEM_LP_EN_S 6
/** LP_AON_HUK_MEM_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
* Set this bit to force software control huk memory, disable hardware control.
*/
#define LP_AON_HUK_MEM_FORCE_CTRL (BIT(7))
#define LP_AON_HUK_MEM_FORCE_CTRL_M (LP_AON_HUK_MEM_FORCE_CTRL_V << LP_AON_HUK_MEM_FORCE_CTRL_S)
#define LP_AON_HUK_MEM_FORCE_CTRL_V 0x00000001U
#define LP_AON_HUK_MEM_FORCE_CTRL_S 7
/** LP_AON_HP_MEM_CTRL_REG register
* configure rmemory power in lp system register
*/
#define LP_AON_HP_MEM_CTRL_REG (DR_REG_LP_AON_BASE + 0x80)
/** LP_AON_MODEM_MEM_LP_MODE : R/W; bitpos: [1:0]; default: 0;
* Configures modem memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define LP_AON_MODEM_MEM_LP_MODE 0x00000003U
#define LP_AON_MODEM_MEM_LP_MODE_M (LP_AON_MODEM_MEM_LP_MODE_V << LP_AON_MODEM_MEM_LP_MODE_S)
#define LP_AON_MODEM_MEM_LP_MODE_V 0x00000003U
#define LP_AON_MODEM_MEM_LP_MODE_S 0
/** LP_AON_MODEM_MEM_LP_EN : R/W; bitpos: [2]; default: 0;
* Set this bit to power down modem memory.
*/
#define LP_AON_MODEM_MEM_LP_EN (BIT(2))
#define LP_AON_MODEM_MEM_LP_EN_M (LP_AON_MODEM_MEM_LP_EN_V << LP_AON_MODEM_MEM_LP_EN_S)
#define LP_AON_MODEM_MEM_LP_EN_V 0x00000001U
#define LP_AON_MODEM_MEM_LP_EN_S 2
/** LP_AON_MODEM_MEM_FORCE_CTRL : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control modem memory, disable hardware control.
*/
#define LP_AON_MODEM_MEM_FORCE_CTRL (BIT(3))
#define LP_AON_MODEM_MEM_FORCE_CTRL_M (LP_AON_MODEM_MEM_FORCE_CTRL_V << LP_AON_MODEM_MEM_FORCE_CTRL_S)
#define LP_AON_MODEM_MEM_FORCE_CTRL_V 0x00000001U
#define LP_AON_MODEM_MEM_FORCE_CTRL_S 3
/** LP_AON_MMU_MEM_LP_MODE : R/W; bitpos: [5:4]; default: 0;
* Configures mmu memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
#define LP_AON_MMU_MEM_LP_MODE 0x00000003U
#define LP_AON_MMU_MEM_LP_MODE_M (LP_AON_MMU_MEM_LP_MODE_V << LP_AON_MMU_MEM_LP_MODE_S)
#define LP_AON_MMU_MEM_LP_MODE_V 0x00000003U
#define LP_AON_MMU_MEM_LP_MODE_S 4
/** LP_AON_MMU_MEM_LP_EN : R/W; bitpos: [6]; default: 0;
* Set this bit to power down mmu memory.
*/
#define LP_AON_MMU_MEM_LP_EN (BIT(6))
#define LP_AON_MMU_MEM_LP_EN_M (LP_AON_MMU_MEM_LP_EN_V << LP_AON_MMU_MEM_LP_EN_S)
#define LP_AON_MMU_MEM_LP_EN_V 0x00000001U
#define LP_AON_MMU_MEM_LP_EN_S 6
/** LP_AON_MMU_MEM_FORCE_CTRL : R/W; bitpos: [7]; default: 0;
* Set this bit to force software control mmu memory, disable hardware control.
*/
#define LP_AON_MMU_MEM_FORCE_CTRL (BIT(7))
#define LP_AON_MMU_MEM_FORCE_CTRL_M (LP_AON_MMU_MEM_FORCE_CTRL_V << LP_AON_MMU_MEM_FORCE_CTRL_S)
#define LP_AON_MMU_MEM_FORCE_CTRL_V 0x00000001U
#define LP_AON_MMU_MEM_FORCE_CTRL_S 7
/** LP_AON_HP_SRAM_MEM_LP_MODE : R/W; bitpos: [17:16]; default: 0;
* Configures hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
#define LP_AON_HP_SRAM_MEM_LP_MODE 0x00000003U
#define LP_AON_HP_SRAM_MEM_LP_MODE_M (LP_AON_HP_SRAM_MEM_LP_MODE_V << LP_AON_HP_SRAM_MEM_LP_MODE_S)
#define LP_AON_HP_SRAM_MEM_LP_MODE_V 0x00000003U
#define LP_AON_HP_SRAM_MEM_LP_MODE_S 16
/** LP_AON_HP_SRAM_MEM_LP_EN : R/W; bitpos: [24:18]; default: 0;
* Set this bit to power down hp_sram memory.
*/
#define LP_AON_HP_SRAM_MEM_LP_EN 0x0000007FU
#define LP_AON_HP_SRAM_MEM_LP_EN_M (LP_AON_HP_SRAM_MEM_LP_EN_V << LP_AON_HP_SRAM_MEM_LP_EN_S)
#define LP_AON_HP_SRAM_MEM_LP_EN_V 0x0000007FU
#define LP_AON_HP_SRAM_MEM_LP_EN_S 18
/** LP_AON_HP_SRAM_MEM_FORCE_CTRL : R/W; bitpos: [31:25]; default: 0;
* Set this bit to force software control hp_sram memory, disable hardware control.
*/
#define LP_AON_HP_SRAM_MEM_FORCE_CTRL 0x0000007FU
#define LP_AON_HP_SRAM_MEM_FORCE_CTRL_M (LP_AON_HP_SRAM_MEM_FORCE_CTRL_V << LP_AON_HP_SRAM_MEM_FORCE_CTRL_S)
#define LP_AON_HP_SRAM_MEM_FORCE_CTRL_V 0x0000007FU
#define LP_AON_HP_SRAM_MEM_FORCE_CTRL_S 25
/** LP_AON_IO_LDO_CFG_REG register
* need_des
*/
#define LP_AON_IO_LDO_CFG_REG (DR_REG_LP_AON_BASE + 0x84)
/** LP_AON_IO_LDO_3P3_SW : R/W; bitpos: [21]; default: 0;
* need_des
*/
#define LP_AON_IO_LDO_3P3_SW (BIT(21))
#define LP_AON_IO_LDO_3P3_SW_M (LP_AON_IO_LDO_3P3_SW_V << LP_AON_IO_LDO_3P3_SW_S)
#define LP_AON_IO_LDO_3P3_SW_V 0x00000001U
#define LP_AON_IO_LDO_3P3_SW_S 21
/** LP_AON_IO_LDO_3P3_SW_EN : R/W; bitpos: [22]; default: 0;
* need_des
*/
#define LP_AON_IO_LDO_3P3_SW_EN (BIT(22))
#define LP_AON_IO_LDO_3P3_SW_EN_M (LP_AON_IO_LDO_3P3_SW_EN_V << LP_AON_IO_LDO_3P3_SW_EN_S)
#define LP_AON_IO_LDO_3P3_SW_EN_V 0x00000001U
#define LP_AON_IO_LDO_3P3_SW_EN_S 22
/** LP_AON_IO_LDO_ADJUST_SW : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
#define LP_AON_IO_LDO_ADJUST_SW 0x000000FFU
#define LP_AON_IO_LDO_ADJUST_SW_M (LP_AON_IO_LDO_ADJUST_SW_V << LP_AON_IO_LDO_ADJUST_SW_S)
#define LP_AON_IO_LDO_ADJUST_SW_V 0x000000FFU
#define LP_AON_IO_LDO_ADJUST_SW_S 23
/** LP_AON_IO_LDO_ADJUST_SW_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_AON_IO_LDO_ADJUST_SW_EN (BIT(31))
#define LP_AON_IO_LDO_ADJUST_SW_EN_M (LP_AON_IO_LDO_ADJUST_SW_EN_V << LP_AON_IO_LDO_ADJUST_SW_EN_S)
#define LP_AON_IO_LDO_ADJUST_SW_EN_V 0x00000001U
#define LP_AON_IO_LDO_ADJUST_SW_EN_S 31
/** LP_AON_LP_GPIO_SECURITY_REG register
* need des
*/
#define LP_AON_LP_GPIO_SECURITY_REG (DR_REG_LP_AON_BASE + 0x8c)
/** LP_AON_LP_GPIO_LOCK : R/W; bitpos: [5:0]; default: 0;
* This field decides whether lp_gpio_config can be locked, or not. 0 (default):
* unlocked. 1: locked.
*/
#define LP_AON_LP_GPIO_LOCK 0x0000003FU
#define LP_AON_LP_GPIO_LOCK_M (LP_AON_LP_GPIO_LOCK_V << LP_AON_LP_GPIO_LOCK_S)
#define LP_AON_LP_GPIO_LOCK_V 0x0000003FU
#define LP_AON_LP_GPIO_LOCK_S 0
/** LP_AON_HP_GPIO_SECURITY_1_REG register
* need des
*/
#define LP_AON_HP_GPIO_SECURITY_1_REG (DR_REG_LP_AON_BASE + 0x90)
/** LP_AON_HP_GPIO_LOCK_P1 : R/W; bitpos: [31:0]; default: 0;
* This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
#define LP_AON_HP_GPIO_LOCK_P1 0xFFFFFFFFU
#define LP_AON_HP_GPIO_LOCK_P1_M (LP_AON_HP_GPIO_LOCK_P1_V << LP_AON_HP_GPIO_LOCK_P1_S)
#define LP_AON_HP_GPIO_LOCK_P1_V 0xFFFFFFFFU
#define LP_AON_HP_GPIO_LOCK_P1_S 0
/** LP_AON_HP_GPIO_SECURITY_2_REG register
* need des
*/
#define LP_AON_HP_GPIO_SECURITY_2_REG (DR_REG_LP_AON_BASE + 0x94)
/** LP_AON_HP_GPIO_LOCK_P2 : R/W; bitpos: [7:0]; default: 0;
* This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
#define LP_AON_HP_GPIO_LOCK_P2 0x000000FFU
#define LP_AON_HP_GPIO_LOCK_P2_M (LP_AON_HP_GPIO_LOCK_P2_V << LP_AON_HP_GPIO_LOCK_P2_S)
#define LP_AON_HP_GPIO_LOCK_P2_V 0x000000FFU
#define LP_AON_HP_GPIO_LOCK_P2_S 0
/** LP_AON_SRAM_USAGE_CONF_REG register
* HP memory usage configuration register
*/
#define LP_AON_SRAM_USAGE_CONF_REG (DR_REG_LP_AON_BASE + 0x98)
/** LP_AON_DCACHE_USAGE : R/W; bitpos: [0]; default: 0;
* hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is
* used to control the first layer(Layer0) usage. 0: cpu use hp-memory. 1: dcache use
* hp-mmory.
* By default, dcache is closed, and typically users can enable dcache after
* boot-loader, but before user's BIN start running.
*/
#define LP_AON_DCACHE_USAGE (BIT(0))
#define LP_AON_DCACHE_USAGE_M (LP_AON_DCACHE_USAGE_V << LP_AON_DCACHE_USAGE_S)
#define LP_AON_DCACHE_USAGE_V 0x00000001U
#define LP_AON_DCACHE_USAGE_S 0
/** LP_AON_ICACHE1_USAGE : R/W; bitpos: [1]; default: 1;
* hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is
* used to control the last layer(Layer6) usage. 0: cpu use hp-memory. 1: icache1 use
* hp-mmory.
* By default, icache1 is not disabled, and the last layer memory belongs to icache1.
* Typically users can set this bit to 0 to disable icache1 in boot-loader.
*/
#define LP_AON_ICACHE1_USAGE (BIT(1))
#define LP_AON_ICACHE1_USAGE_M (LP_AON_ICACHE1_USAGE_V << LP_AON_ICACHE1_USAGE_S)
#define LP_AON_ICACHE1_USAGE_V 0x00000001U
#define LP_AON_ICACHE1_USAGE_S 1
/** LP_AON_DATE_REG register
* reserved
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 37823056;
* version register
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* version register
*/
#define LP_AON_CLK_EN (BIT(31))
#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S)
#define LP_AON_CLK_EN_V 0x00000001U
#define LP_AON_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_aon_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of aon_store0 register
* store the software massege0 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store0 : R/W; bitpos: [31:0]; default: 0;
* store the software massege0 in always-on field
*/
uint32_t aon_lp_aon_store0:32;
};
uint32_t val;
} lp_aon_store0_reg_t;
/** Type of aon_store1 register
* store the software massege1 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store1 : R/W; bitpos: [31:0]; default: 0;
* store the software massege1 in always-on field
*/
uint32_t aon_lp_aon_store1:32;
};
uint32_t val;
} lp_aon_store1_reg_t;
/** Type of aon_store2 register
* store the software massege2 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store2 : R/W; bitpos: [31:0]; default: 0;
* store the software massege2 in always-on field
*/
uint32_t aon_lp_aon_store2:32;
};
uint32_t val;
} lp_aon_store2_reg_t;
/** Type of aon_store3 register
* store the software massege3 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store3 : R/W; bitpos: [31:0]; default: 0;
* store the software massege3 in always-on field
*/
uint32_t aon_lp_aon_store3:32;
};
uint32_t val;
} lp_aon_store3_reg_t;
/** Type of aon_store4 register
* store the software massege4 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store4 : R/W; bitpos: [31:0]; default: 0;
* store the software massege4 in always-on field
*/
uint32_t aon_lp_aon_store4:32;
};
uint32_t val;
} lp_aon_store4_reg_t;
/** Type of aon_store5 register
* store the software massege5 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store5 : R/W; bitpos: [31:0]; default: 0;
* store the software massege5 in always-on field
*/
uint32_t aon_lp_aon_store5:32;
};
uint32_t val;
} lp_aon_store5_reg_t;
/** Type of aon_store6 register
* store the software massege6 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store6 : R/W; bitpos: [31:0]; default: 0;
* store the software massege6 in always-on field
*/
uint32_t aon_lp_aon_store6:32;
};
uint32_t val;
} lp_aon_store6_reg_t;
/** Type of aon_store7 register
* store the software massege7 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store7 : R/W; bitpos: [31:0]; default: 0;
* store the software massege7 in always-on field
*/
uint32_t aon_lp_aon_store7:32;
};
uint32_t val;
} lp_aon_store7_reg_t;
/** Type of aon_store8 register
* store the software massege8 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store8 : R/W; bitpos: [31:0]; default: 0;
* store the software massege8 in always-on field
*/
uint32_t aon_lp_aon_store8:32;
};
uint32_t val;
} lp_aon_store8_reg_t;
/** Type of aon_store9 register
* store the software massege9 in always-on field
*/
typedef union {
struct {
/** aon_lp_aon_store9 : R/W; bitpos: [31:0]; default: 0;
* store the software massege9 in always-on field
*/
uint32_t aon_lp_aon_store9:32;
};
uint32_t val;
} lp_aon_store9_reg_t;
/** Type of aon_gpio_mux register
* select the lp io controlled by hp iomux or lp iomux
*/
typedef union {
struct {
/** aon_gpio_mux_sel : R/W; bitpos: [5:0]; default: 0;
* select the lp io 0~5 controlled by hp iomux or lp iomux
* 1: controlled by lp iomux
* 0: controlled by hp iomux
*/
uint32_t gpio_mux_sel:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_aon_gpio_mux_reg_t;
/** Type of aon_gpio_hold0 register
* configure all io hold
*/
typedef union {
struct {
/** aon_gpio_hold0 : R/W; bitpos: [31:0]; default: 0;
* configure io0~28 hold enable,when io in hold status, all io configure and output
* will be latch , input function is useful
*/
uint32_t gpio_hold0:32;
};
uint32_t val;
} lp_aon_gpio_hold0_reg_t;
/** Type of aon_sys_cfg register
* configure system register
*/
typedef union {
struct {
/** aon_fib_reg : RO; bitpos: [7:0]; default: 255;
* get fib reg information
*/
uint32_t aon_fib_reg:8;
uint32_t reserved_8:23;
/** aon_hpsys_sw_reset : WT; bitpos: [31]; default: 0;
* enable hp system reset by software or not
* 1: reset
* 0: no operation
*/
uint32_t aon_hpsys_sw_reset:1;
};
uint32_t val;
} lp_aon_sys_cfg_reg_t;
/** Type of aon_cpucore_cfg register
* configure core reset register
*/
typedef union {
struct {
/** aon_cpu_core0_sw_stall : R/W; bitpos: [7:0]; default: 0;
* enable cpu 0 entry stall status
* 0x86: entry stall status
* Others : no operation
*/
uint32_t aon_cpu_core0_sw_stall:8;
/** aon_cpu_core0_sw_reset : WT; bitpos: [8]; default: 0;
* enable core 0 reset by software
* 1: reset
* 0: no operation
*/
uint32_t aon_cpu_core0_sw_reset:1;
uint32_t reserved_9:7;
/** aon_cpu_core1_sw_stall : R/W; bitpos: [23:16]; default: 0;
* enable core 1 entry stall status
* 0x86: entry stall status
* Others : no operation
*/
uint32_t aon_cpu_core1_sw_stall:8;
/** aon_cpu_core1_sw_reset : WT; bitpos: [24]; default: 0;
* enable core1 reset by software
* 1: reset
* 0: no operation
*/
uint32_t aon_cpu_core1_sw_reset:1;
uint32_t reserved_25:6;
/** aon_systimer_stall_sel : R/W; bitpos: [31]; default: 0;
* delete which core run_stall to lp_timer
* 1: core1
* 0: core0
*/
uint32_t aon_systimer_stall_sel:1;
};
uint32_t val;
} lp_aon_cpucore_cfg_reg_t;
/** Type of aon_io_mux register
* configure hp iomux reset bypass
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** aon_io_mux_pull_ldo : R/W; bitpos: [30:28]; default: 0;
* need_des
*/
uint32_t aon_io_mux_pull_ldo:3;
/** aon_io_mux_reset_disable : R/W; bitpos: [31]; default: 0;
* bypass hp iomux reset from hp system reset event
* 1: bypass
* 0: no operation
*/
uint32_t aon_io_mux_reset_disable:1;
};
uint32_t val;
} lp_aon_io_mux_reg_t;
/** Type of aon_ext_wakeup_cntl register
* configure alwayson external io wakeup
*/
typedef union {
struct {
/** aon_ext_wakeup_sel : R/W; bitpos: [15:0]; default: 0;
* enable io0~15 bit map use to external wakeup
* 1: enable
* 0: disable
*/
uint32_t aon_ext_wakeup_sel:16;
/** aon_ext_wakeup_lv : R/W; bitpos: [31:16]; default: 0;
* select external wakeup io level
* 1: io high level wakeup
* 0: io low level wakeup
*/
uint32_t aon_ext_wakeup_lv:16;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl_reg_t;
/** Type of aon_ext_wakeup_cntl1 register
* configure alwayson external io wakeup
*/
typedef union {
struct {
/** aon_ext_wakeup_status : RO; bitpos: [15:0]; default: 0;
* get external wakeup status bitmap
*/
uint32_t aon_ext_wakeup_status:16;
uint32_t reserved_16:14;
/** aon_ext_wakeup_status_clr : WT; bitpos: [30]; default: 0;
* clear external wakeup status
* 1: clear
* 0: no operation
*/
uint32_t aon_ext_wakeup_status_clr:1;
/** aon_ext_wakeup_filter : R/W; bitpos: [31]; default: 0;
* enable external filter or not
* 1: enable
* 0: disable
*/
uint32_t aon_ext_wakeup_filter:1;
};
uint32_t val;
} lp_aon_ext_wakeup_cntl1_reg_t;
/** Type of aon_usb register
* configure usb reset bypass
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** aon_usb_reset_disable : R/W; bitpos: [31]; default: 0;
* bypass usb reset from hp system reset event
* 1: bypass
* 0: no operation
*/
uint32_t aon_usb_reset_disable:1;
};
uint32_t val;
} lp_aon_usb_reg_t;
/** Type of aon_lpbus register
* Select lp memory bus
*/
typedef union {
struct {
uint32_t reserved_0:28;
/** aon_fast_mem_mux_fsm_idle : RO; bitpos: [28]; default: 1;
* get current lp memory bus fsm status
*/
uint32_t aon_fast_mem_mux_fsm_idle:1;
/** aon_fast_mem_mux_sel_status : RO; bitpos: [29]; default: 1;
* get current lp memory bus mode
*/
uint32_t aon_fast_mem_mux_sel_status:1;
/** aon_fast_mem_mux_sel_update : WT; bitpos: [30]; default: 0;
* enable reg_fast_mem_sel configure
* 1: enable
* 0: no operation
*/
uint32_t aon_fast_mem_mux_sel_update:1;
/** aon_fast_mem_mux_sel : R/W; bitpos: [31]; default: 1;
* select lp memory bus is high speed mode or low speed mode
* 1: high speed from hp system ahb
* 0: low speed from lp system
*/
uint32_t aon_fast_mem_mux_sel:1;
};
uint32_t val;
} lp_aon_lpbus_reg_t;
/** Type of aon_backup_dma_cfg0 register
* configure regdma always on register
*/
typedef union {
struct {
/** aon_burst_limit_aon : R/W; bitpos: [4:0]; default: 10;
* Set this field to configure max value of burst in single transfer.
*/
uint32_t aon_burst_limit_aon:5;
/** aon_read_interval_aon : R/W; bitpos: [11:5]; default: 10;
* Set this field to configure read registers' interval time in reading mode.
*/
uint32_t aon_read_interval_aon:7;
/** aon_branch_link_length_aon : R/W; bitpos: [15:12]; default: 0;
* Set this field to configure link address.
*/
uint32_t aon_branch_link_length_aon:4;
/** aon_regdma_error : RO; bitpos: [18:16]; default: 0;
* regdma error code
*/
uint32_t aon_regdma_error:3;
uint32_t reserved_19:13;
};
uint32_t val;
} lp_aon_backup_dma_cfg0_reg_t;
/** Type of aon_backup_dma_cfg1 register
* configure regdma always on register
*/
typedef union {
struct {
/** aon_link_wait_tout_thres_aon : R/W; bitpos: [9:0]; default: 100;
* Set this field to configure the number of consecutive links of link list.
*/
uint32_t aon_link_wait_tout_thres_aon:10;
/** aon_link_work_tout_thres_aon : R/W; bitpos: [19:10]; default: 100;
* Set this field to configure maximum waiting time in waiting mode.
*/
uint32_t aon_link_work_tout_thres_aon:10;
/** aon_link_backup_tout_thres_aon : R/W; bitpos: [29:20]; default: 100;
* Set this field to configure maximum waiting time in backup mode.
*/
uint32_t aon_link_backup_tout_thres_aon:10;
uint32_t reserved_30:2;
};
uint32_t val;
} lp_aon_backup_dma_cfg1_reg_t;
/** Type of aon_backup_dma_cfg2 register
* configure regdma always on register
*/
typedef union {
struct {
/** aon_link_addr_aon : R/W; bitpos: [31:0]; default: 0;
* Set this field to configure link address.
*/
uint32_t aon_link_addr_aon:32;
};
uint32_t val;
} lp_aon_backup_dma_cfg2_reg_t;
/** Type of aon_mem_ctrl register
* configure rmemory power in lp system register
*/
typedef union {
struct {
/** aon_efuse_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
* Configures efuse memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t aon_efuse_mem_lp_mode:2;
/** aon_efuse_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down efuse memory.
*/
uint32_t aon_efuse_mem_lp_en:1;
/** aon_efuse_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control efuse memory, disable hardware control.
*/
uint32_t aon_efuse_mem_force_ctrl:1;
/** aon_huk_mem_lp_mode : R/W; bitpos: [5:4]; default: 2;
* Configures huk memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t aon_huk_mem_lp_mode:2;
/** aon_huk_mem_lp_en : R/W; bitpos: [6]; default: 0;
* Set this bit to power down huk memory.
*/
uint32_t aon_huk_mem_lp_en:1;
/** aon_huk_mem_force_ctrl : R/W; bitpos: [7]; default: 0;
* Set this bit to force software control huk memory, disable hardware control.
*/
uint32_t aon_huk_mem_force_ctrl:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_mem_ctrl_reg_t;
/** Type of aon_hp_mem_ctrl register
* configure rmemory power in lp system register
*/
typedef union {
struct {
/** aon_modem_mem_lp_mode : R/W; bitpos: [1:0]; default: 0;
* Configures modem memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t aon_modem_mem_lp_mode:2;
/** aon_modem_mem_lp_en : R/W; bitpos: [2]; default: 0;
* Set this bit to power down modem memory.
*/
uint32_t aon_modem_mem_lp_en:1;
/** aon_modem_mem_force_ctrl : R/W; bitpos: [3]; default: 0;
* Set this bit to force software control modem memory, disable hardware control.
*/
uint32_t aon_modem_mem_force_ctrl:1;
/** aon_mmu_mem_lp_mode : R/W; bitpos: [5:4]; default: 0;
* Configures mmu memory low power mode in low power stage.
* 0: deep sleep
* 1: light sleep
* 2(default): shut down
* 3: disable low power stage
*/
uint32_t aon_mmu_mem_lp_mode:2;
/** aon_mmu_mem_lp_en : R/W; bitpos: [6]; default: 0;
* Set this bit to power down mmu memory.
*/
uint32_t aon_mmu_mem_lp_en:1;
/** aon_mmu_mem_force_ctrl : R/W; bitpos: [7]; default: 0;
* Set this bit to force software control mmu memory, disable hardware control.
*/
uint32_t aon_mmu_mem_force_ctrl:1;
uint32_t reserved_8:8;
/** aon_hp_sram_mem_lp_mode : R/W; bitpos: [17:16]; default: 0;
* Configures hp_sram memory low power mode in low power stage.
* 0(default): deep sleep
* 1: light sleep
* 2: shut down
* 3: disable low power stage
*/
uint32_t aon_hp_sram_mem_lp_mode:2;
/** aon_hp_sram_mem_lp_en : R/W; bitpos: [24:18]; default: 0;
* Set this bit to power down hp_sram memory.
*/
uint32_t aon_hp_sram_mem_lp_en:7;
/** aon_hp_sram_mem_force_ctrl : R/W; bitpos: [31:25]; default: 0;
* Set this bit to force software control hp_sram memory, disable hardware control.
*/
uint32_t aon_hp_sram_mem_force_ctrl:7;
};
uint32_t val;
} lp_aon_hp_mem_ctrl_reg_t;
/** Type of aon_io_ldo_cfg register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** aon_io_ldo_3p3_sw : R/W; bitpos: [21]; default: 0;
* need_des
*/
uint32_t aon_io_ldo_3p3_sw:1;
/** aon_io_ldo_3p3_sw_en : R/W; bitpos: [22]; default: 0;
* need_des
*/
uint32_t aon_io_ldo_3p3_sw_en:1;
/** aon_io_ldo_adjust_sw : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
uint32_t aon_io_ldo_adjust_sw:8;
/** aon_io_ldo_adjust_sw_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t aon_io_ldo_adjust_sw_en:1;
};
uint32_t val;
} lp_aon_io_ldo_cfg_reg_t;
/** Type of aon_lp_gpio_security register
* need des
*/
typedef union {
struct {
/** aon_lp_gpio_lock : R/W; bitpos: [5:0]; default: 0;
* This field decides whether lp_gpio_config can be locked, or not. 0 (default):
* unlocked. 1: locked.
*/
uint32_t aon_lp_gpio_lock:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_aon_lp_gpio_security_reg_t;
/** Type of aon_hp_gpio_security_1 register
* need des
*/
typedef union {
struct {
/** aon_hp_gpio_lock_p1 : R/W; bitpos: [31:0]; default: 0;
* This field decides whether hp_gpio_config of PIN0~31 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
uint32_t aon_hp_gpio_lock_p1:32;
};
uint32_t val;
} lp_aon_hp_gpio_security_1_reg_t;
/** Type of aon_hp_gpio_security_2 register
* need des
*/
typedef union {
struct {
/** aon_hp_gpio_lock_p2 : R/W; bitpos: [7:0]; default: 0;
* This field decides whether hp_gpio_config of PIN32~39 can be locked, or not. 0
* (default): unlocked. 1: locked.
*/
uint32_t aon_hp_gpio_lock_p2:8;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_aon_hp_gpio_security_2_reg_t;
/** Type of aon_sram_usage_conf register
* HP memory usage configuration register
*/
typedef union {
struct {
/** aon_dcache_usage : R/W; bitpos: [0]; default: 0;
* hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is
* used to control the first layer(Layer0) usage. 0: cpu use hp-memory. 1: dcache use
* hp-mmory.
* By default, dcache is closed, and typically users can enable dcache after
* boot-loader, but before user's BIN start running.
*/
uint32_t aon_dcache_usage:1;
/** aon_icache1_usage : R/W; bitpos: [1]; default: 1;
* hp system memory is split to 7 layers(Layer0 ~ Layer6) in total, this field is
* used to control the last layer(Layer6) usage. 0: cpu use hp-memory. 1: icache1 use
* hp-mmory.
* By default, icache1 is not disabled, and the last layer memory belongs to icache1.
* Typically users can set this bit to 0 to disable icache1 in boot-loader.
*/
uint32_t aon_icache1_usage:1;
uint32_t reserved_2:30;
};
uint32_t val;
} lp_aon_sram_usage_conf_reg_t;
/** Type of aon_date register
* reserved
*/
typedef union {
struct {
/** aon_date : R/W; bitpos: [30:0]; default: 37823056;
* version register
*/
uint32_t aon_date:31;
/** aon_clk_en : R/W; bitpos: [31]; default: 0;
* version register
*/
uint32_t aon_clk_en:1;
};
uint32_t val;
} lp_aon_date_reg_t;
typedef struct {
volatile lp_aon_store0_reg_t store0;
volatile lp_aon_store1_reg_t store1;
volatile lp_aon_store2_reg_t store2;
volatile lp_aon_store3_reg_t store3;
volatile lp_aon_store4_reg_t store4;
volatile lp_aon_store5_reg_t store5;
volatile lp_aon_store6_reg_t store6;
volatile lp_aon_store7_reg_t store7;
volatile lp_aon_store8_reg_t store8;
volatile lp_aon_store9_reg_t store9;
volatile lp_aon_gpio_mux_reg_t gpio_mux;
volatile lp_aon_gpio_hold0_reg_t gpio_hold0;
uint32_t reserved_030;
volatile lp_aon_sys_cfg_reg_t sys_cfg;
volatile lp_aon_cpucore_cfg_reg_t cpucore_cfg;
volatile lp_aon_io_mux_reg_t io_mux;
volatile lp_aon_ext_wakeup_cntl_reg_t ext_wakeup_cntl;
volatile lp_aon_ext_wakeup_cntl1_reg_t ext_wakeup_cntl1;
volatile lp_aon_usb_reg_t usb;
volatile lp_aon_lpbus_reg_t lpbus;
uint32_t reserved_050[8];
volatile lp_aon_backup_dma_cfg0_reg_t backup_dma_cfg0;
volatile lp_aon_backup_dma_cfg1_reg_t backup_dma_cfg1;
volatile lp_aon_backup_dma_cfg2_reg_t backup_dma_cfg2;
volatile lp_aon_mem_ctrl_reg_t mem_ctrl;
volatile lp_aon_hp_mem_ctrl_reg_t hp_mem_ctrl;
volatile lp_aon_io_ldo_cfg_reg_t io_ldo_cfg;
uint32_t reserved_088;
volatile lp_aon_lp_gpio_security_reg_t lp_gpio_security;
volatile lp_aon_hp_gpio_security_1_reg_t hp_gpio_security_1;
volatile lp_aon_hp_gpio_security_2_reg_t hp_gpio_security_2;
volatile lp_aon_sram_usage_conf_reg_t sram_usage_conf;
uint32_t reserved_09c[216];
volatile lp_aon_date_reg_t date;
} lp_aon_dev_t;
extern lp_aon_dev_t LP_AON;
#ifndef __cplusplus
_Static_assert(sizeof(lp_aon_dev_t) == 0x400, "Invalid size of lp_aon_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_clkrst_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_CLKRST_LP_CLK_CONF_REG register
* Configures the root clk of LP system
*/
#define LP_CLKRST_LP_CLK_CONF_REG (DR_REG_LP_BASE + 0x0)
/** LP_CLKRST_SLOW_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
* Configures the source of LP_SLOW_CLK.
* 0: RC_SLOW_CLK
* 1: XTAL32K_CLK
* 2: RC32K_CLK
* 3:OSC_SLOW_CLK
*/
#define LP_CLKRST_SLOW_CLK_SEL 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_M (LP_CLKRST_SLOW_CLK_SEL_V << LP_CLKRST_SLOW_CLK_SEL_S)
#define LP_CLKRST_SLOW_CLK_SEL_V 0x00000003U
#define LP_CLKRST_SLOW_CLK_SEL_S 0
/** LP_CLKRST_FAST_CLK_SEL : R/W; bitpos: [2]; default: 1;
* configures the source of LP_FAST_CLK.
* 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
*/
#define LP_CLKRST_FAST_CLK_SEL (BIT(2))
#define LP_CLKRST_FAST_CLK_SEL_M (LP_CLKRST_FAST_CLK_SEL_V << LP_CLKRST_FAST_CLK_SEL_S)
#define LP_CLKRST_FAST_CLK_SEL_V 0x00000001U
#define LP_CLKRST_FAST_CLK_SEL_S 2
/** LP_CLKRST_LP_PERI_DIV_NUM : R/W; bitpos: [10:3]; default: 0;
* reserved
*/
#define LP_CLKRST_LP_PERI_DIV_NUM 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_M (LP_CLKRST_LP_PERI_DIV_NUM_V << LP_CLKRST_LP_PERI_DIV_NUM_S)
#define LP_CLKRST_LP_PERI_DIV_NUM_V 0x000000FFU
#define LP_CLKRST_LP_PERI_DIV_NUM_S 3
/** LP_CLKRST_LP_CLK_PO_EN_REG register
* Configures the clk gate to pad
*/
#define LP_CLKRST_LP_CLK_PO_EN_REG (DR_REG_LP_BASE + 0x4)
/** LP_CLKRST_AON_SLOW_OEN : R/W; bitpos: [0]; default: 1;
* Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_AON_SLOW_OEN (BIT(0))
#define LP_CLKRST_AON_SLOW_OEN_M (LP_CLKRST_AON_SLOW_OEN_V << LP_CLKRST_AON_SLOW_OEN_S)
#define LP_CLKRST_AON_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_AON_SLOW_OEN_S 0
/** LP_CLKRST_AON_FAST_OEN : R/W; bitpos: [1]; default: 1;
* Configures the clock gate to pad of the LP_DYN_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_AON_FAST_OEN (BIT(1))
#define LP_CLKRST_AON_FAST_OEN_M (LP_CLKRST_AON_FAST_OEN_V << LP_CLKRST_AON_FAST_OEN_S)
#define LP_CLKRST_AON_FAST_OEN_V 0x00000001U
#define LP_CLKRST_AON_FAST_OEN_S 1
/** LP_CLKRST_SOSC_OEN : R/W; bitpos: [2]; default: 1;
* Configures the clock gate to pad of the OSC_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_SOSC_OEN (BIT(2))
#define LP_CLKRST_SOSC_OEN_M (LP_CLKRST_SOSC_OEN_V << LP_CLKRST_SOSC_OEN_S)
#define LP_CLKRST_SOSC_OEN_V 0x00000001U
#define LP_CLKRST_SOSC_OEN_S 2
/** LP_CLKRST_FOSC_OEN : R/W; bitpos: [3]; default: 1;
* Configures the clock gate to pad of the RC_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_FOSC_OEN (BIT(3))
#define LP_CLKRST_FOSC_OEN_M (LP_CLKRST_FOSC_OEN_V << LP_CLKRST_FOSC_OEN_S)
#define LP_CLKRST_FOSC_OEN_V 0x00000001U
#define LP_CLKRST_FOSC_OEN_S 3
/** LP_CLKRST_OSC32K_OEN : R/W; bitpos: [4]; default: 1;
* Configures the clock gate to pad of the RC32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_OSC32K_OEN (BIT(4))
#define LP_CLKRST_OSC32K_OEN_M (LP_CLKRST_OSC32K_OEN_V << LP_CLKRST_OSC32K_OEN_S)
#define LP_CLKRST_OSC32K_OEN_V 0x00000001U
#define LP_CLKRST_OSC32K_OEN_S 4
/** LP_CLKRST_XTAL32K_OEN : R/W; bitpos: [5]; default: 1;
* Configures the clock gate to pad of the XTAL32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_XTAL32K_OEN (BIT(5))
#define LP_CLKRST_XTAL32K_OEN_M (LP_CLKRST_XTAL32K_OEN_V << LP_CLKRST_XTAL32K_OEN_S)
#define LP_CLKRST_XTAL32K_OEN_V 0x00000001U
#define LP_CLKRST_XTAL32K_OEN_S 5
/** LP_CLKRST_CORE_EFUSE_OEN : R/W; bitpos: [6]; default: 1;
* Configures the clock gate to pad of the EFUSE_CTRL clock.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_CORE_EFUSE_OEN (BIT(6))
#define LP_CLKRST_CORE_EFUSE_OEN_M (LP_CLKRST_CORE_EFUSE_OEN_V << LP_CLKRST_CORE_EFUSE_OEN_S)
#define LP_CLKRST_CORE_EFUSE_OEN_V 0x00000001U
#define LP_CLKRST_CORE_EFUSE_OEN_S 6
/** LP_CLKRST_SLOW_OEN : R/W; bitpos: [7]; default: 1;
* Configures the clock gate to pad of the LP_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_SLOW_OEN (BIT(7))
#define LP_CLKRST_SLOW_OEN_M (LP_CLKRST_SLOW_OEN_V << LP_CLKRST_SLOW_OEN_S)
#define LP_CLKRST_SLOW_OEN_V 0x00000001U
#define LP_CLKRST_SLOW_OEN_S 7
/** LP_CLKRST_FAST_OEN : R/W; bitpos: [8]; default: 1;
* Configures the clock gate to pad of the LP_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_FAST_OEN (BIT(8))
#define LP_CLKRST_FAST_OEN_M (LP_CLKRST_FAST_OEN_V << LP_CLKRST_FAST_OEN_S)
#define LP_CLKRST_FAST_OEN_V 0x00000001U
#define LP_CLKRST_FAST_OEN_S 8
/** LP_CLKRST_RNG_OEN : R/W; bitpos: [9]; default: 1;
* Configures the clock gate to pad of the RNG clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_RNG_OEN (BIT(9))
#define LP_CLKRST_RNG_OEN_M (LP_CLKRST_RNG_OEN_V << LP_CLKRST_RNG_OEN_S)
#define LP_CLKRST_RNG_OEN_V 0x00000001U
#define LP_CLKRST_RNG_OEN_S 9
/** LP_CLKRST_LPBUS_OEN : R/W; bitpos: [10]; default: 1;
* Configures the clock gate to pad of the LP bus clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_LPBUS_OEN (BIT(10))
#define LP_CLKRST_LPBUS_OEN_M (LP_CLKRST_LPBUS_OEN_V << LP_CLKRST_LPBUS_OEN_S)
#define LP_CLKRST_LPBUS_OEN_V 0x00000001U
#define LP_CLKRST_LPBUS_OEN_S 10
/** LP_CLKRST_LP_CLK_EN_REG register
* Configure LP root clk source gate
*/
#define LP_CLKRST_LP_CLK_EN_REG (DR_REG_LP_BASE + 0x8)
/** LP_CLKRST_RTC_BLE_TIMER_APB_GATE : R/W; bitpos: [27]; default: 1;
* Configures the clock gate to RTC_BLE_TIMER_APB_CLK
* 0: Invalid. The clock gate controlled
* 1: Force the clk pass clock gate
*/
#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE (BIT(27))
#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE_M (LP_CLKRST_RTC_BLE_TIMER_APB_GATE_V << LP_CLKRST_RTC_BLE_TIMER_APB_GATE_S)
#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE_V 0x00000001U
#define LP_CLKRST_RTC_BLE_TIMER_APB_GATE_S 27
/** LP_CLKRST_TOTAL_CORE_EFUSE_GATE : R/W; bitpos: [28]; default: 1;
* Configures the clock gate to TOTAL_EFUSE_AON_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE (BIT(28))
#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE_M (LP_CLKRST_TOTAL_CORE_EFUSE_GATE_V << LP_CLKRST_TOTAL_CORE_EFUSE_GATE_S)
#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE_V 0x00000001U
#define LP_CLKRST_TOTAL_CORE_EFUSE_GATE_S 28
/** LP_CLKRST_AON_CORE_EFUSE_GATE : R/W; bitpos: [29]; default: 1;
* Configures the clock gate to CORE_EFUSE_AON_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
#define LP_CLKRST_AON_CORE_EFUSE_GATE (BIT(29))
#define LP_CLKRST_AON_CORE_EFUSE_GATE_M (LP_CLKRST_AON_CORE_EFUSE_GATE_V << LP_CLKRST_AON_CORE_EFUSE_GATE_S)
#define LP_CLKRST_AON_CORE_EFUSE_GATE_V 0x00000001U
#define LP_CLKRST_AON_CORE_EFUSE_GATE_S 29
/** LP_CLKRST_AON_TOUCH_GATE : R/W; bitpos: [30]; default: 1;
* Configures the clock gate to TOUCH_AON_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
#define LP_CLKRST_AON_TOUCH_GATE (BIT(30))
#define LP_CLKRST_AON_TOUCH_GATE_M (LP_CLKRST_AON_TOUCH_GATE_V << LP_CLKRST_AON_TOUCH_GATE_S)
#define LP_CLKRST_AON_TOUCH_GATE_V 0x00000001U
#define LP_CLKRST_AON_TOUCH_GATE_S 30
/** LP_CLKRST_FAST_ORI_GATE : R/W; bitpos: [31]; default: 0;
* Configures the clock gate to LP_FAST_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
#define LP_CLKRST_FAST_ORI_GATE (BIT(31))
#define LP_CLKRST_FAST_ORI_GATE_M (LP_CLKRST_FAST_ORI_GATE_V << LP_CLKRST_FAST_ORI_GATE_S)
#define LP_CLKRST_FAST_ORI_GATE_V 0x00000001U
#define LP_CLKRST_FAST_ORI_GATE_S 31
/** LP_CLKRST_LP_RST_EN_REG register
* Configures the peri of LP system software reset
*/
#define LP_CLKRST_LP_RST_EN_REG (DR_REG_LP_BASE + 0xc)
/** LP_CLKRST_HUK_RESET_EN : R/W; bitpos: [25]; default: 0;
* Configures whether or not to reset HUK
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_HUK_RESET_EN (BIT(25))
#define LP_CLKRST_HUK_RESET_EN_M (LP_CLKRST_HUK_RESET_EN_V << LP_CLKRST_HUK_RESET_EN_S)
#define LP_CLKRST_HUK_RESET_EN_V 0x00000001U
#define LP_CLKRST_HUK_RESET_EN_S 25
/** LP_CLKRST_AON_BLETIMER_RESET_EN : R/W; bitpos: [26]; default: 0;
* Configures whether or not to reset bletimer part
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_AON_BLETIMER_RESET_EN (BIT(26))
#define LP_CLKRST_AON_BLETIMER_RESET_EN_M (LP_CLKRST_AON_BLETIMER_RESET_EN_V << LP_CLKRST_AON_BLETIMER_RESET_EN_S)
#define LP_CLKRST_AON_BLETIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_BLETIMER_RESET_EN_S 26
/** LP_CLKRST_AON_TOUCH_RESET_EN : R/W; bitpos: [27]; default: 0;
* Configures whether or not to reset TOUCH part
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_AON_TOUCH_RESET_EN (BIT(27))
#define LP_CLKRST_AON_TOUCH_RESET_EN_M (LP_CLKRST_AON_TOUCH_RESET_EN_V << LP_CLKRST_AON_TOUCH_RESET_EN_S)
#define LP_CLKRST_AON_TOUCH_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_TOUCH_RESET_EN_S 27
/** LP_CLKRST_AON_EFUSE_CORE_RESET_EN : R/W; bitpos: [28]; default: 0;
* Configures whether or not to reset EFUSE_CTRL always-on part
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN (BIT(28))
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_M (LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V << LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S)
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_V 0x00000001U
#define LP_CLKRST_AON_EFUSE_CORE_RESET_EN_S 28
/** LP_CLKRST_LP_TIMER_RESET_EN : R/W; bitpos: [29]; default: 0;
* Configures whether or not to reset LP_TIMER
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_LP_TIMER_RESET_EN (BIT(29))
#define LP_CLKRST_LP_TIMER_RESET_EN_M (LP_CLKRST_LP_TIMER_RESET_EN_V << LP_CLKRST_LP_TIMER_RESET_EN_S)
#define LP_CLKRST_LP_TIMER_RESET_EN_V 0x00000001U
#define LP_CLKRST_LP_TIMER_RESET_EN_S 29
/** LP_CLKRST_WDT_RESET_EN : R/W; bitpos: [30]; default: 0;
* Configures whether or not to reset LP_WDT and super watch dog
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_WDT_RESET_EN (BIT(30))
#define LP_CLKRST_WDT_RESET_EN_M (LP_CLKRST_WDT_RESET_EN_V << LP_CLKRST_WDT_RESET_EN_S)
#define LP_CLKRST_WDT_RESET_EN_V 0x00000001U
#define LP_CLKRST_WDT_RESET_EN_S 30
/** LP_CLKRST_ANA_PERI_RESET_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not to reset analog peri, include brownout controller
* 0: Invalid.No effect
* 1: Reset
*/
#define LP_CLKRST_ANA_PERI_RESET_EN (BIT(31))
#define LP_CLKRST_ANA_PERI_RESET_EN_M (LP_CLKRST_ANA_PERI_RESET_EN_V << LP_CLKRST_ANA_PERI_RESET_EN_S)
#define LP_CLKRST_ANA_PERI_RESET_EN_V 0x00000001U
#define LP_CLKRST_ANA_PERI_RESET_EN_S 31
/** LP_CLKRST_RESET_CORE0_CAUSE_REG register
* Represents the reset cause
*/
#define LP_CLKRST_RESET_CORE0_CAUSE_REG (DR_REG_LP_BASE + 0x10)
/** LP_CLKRST_CORE0_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* Represents the reset cause
*/
#define LP_CLKRST_CORE0_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_CORE0_RESET_CAUSE_M (LP_CLKRST_CORE0_RESET_CAUSE_V << LP_CLKRST_CORE0_RESET_CAUSE_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_CORE0_RESET_CAUSE_S 0
/** LP_CLKRST_CORE0_RESET_FLAG : RO; bitpos: [5]; default: 1;
* Represents the reset flag
*/
#define LP_CLKRST_CORE0_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE0_RESET_FLAG_M (LP_CLKRST_CORE0_RESET_FLAG_V << LP_CLKRST_CORE0_RESET_FLAG_S)
#define LP_CLKRST_CORE0_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_S 5
/** LP_CLKRST_CORE0_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* 0: no operation
*/
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_M (LP_CLKRST_CORE0_RESET_CAUSE_CLR_V << LP_CLKRST_CORE0_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE0_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* configure set reset flag
*/
#define LP_CLKRST_CORE0_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE0_RESET_FLAG_SET_M (LP_CLKRST_CORE0_RESET_FLAG_SET_V << LP_CLKRST_CORE0_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE0_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE0_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* configure clear reset flag
* 0: no operation
* 1: clear flag to 0
*/
#define LP_CLKRST_CORE0_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_M (LP_CLKRST_CORE0_RESET_FLAG_CLR_V << LP_CLKRST_CORE0_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE0_RESET_FLAG_CLR_S 31
/** LP_CLKRST_RESET_CORE1_CAUSE_REG register
* Represents the reset cause
*/
#define LP_CLKRST_RESET_CORE1_CAUSE_REG (DR_REG_LP_BASE + 0x14)
/** LP_CLKRST_CORE1_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;
* Represents the reset cause
*/
#define LP_CLKRST_CORE1_RESET_CAUSE 0x0000001FU
#define LP_CLKRST_CORE1_RESET_CAUSE_M (LP_CLKRST_CORE1_RESET_CAUSE_V << LP_CLKRST_CORE1_RESET_CAUSE_S)
#define LP_CLKRST_CORE1_RESET_CAUSE_V 0x0000001FU
#define LP_CLKRST_CORE1_RESET_CAUSE_S 0
/** LP_CLKRST_CORE1_RESET_FLAG : RO; bitpos: [5]; default: 1;
* Represents the reset flag
*/
#define LP_CLKRST_CORE1_RESET_FLAG (BIT(5))
#define LP_CLKRST_CORE1_RESET_FLAG_M (LP_CLKRST_CORE1_RESET_FLAG_V << LP_CLKRST_CORE1_RESET_FLAG_S)
#define LP_CLKRST_CORE1_RESET_FLAG_V 0x00000001U
#define LP_CLKRST_CORE1_RESET_FLAG_S 5
/** LP_CLKRST_CORE1_RESET_CAUSE_CLR : WT; bitpos: [29]; default: 0;
* 0: no operation
*/
#define LP_CLKRST_CORE1_RESET_CAUSE_CLR (BIT(29))
#define LP_CLKRST_CORE1_RESET_CAUSE_CLR_M (LP_CLKRST_CORE1_RESET_CAUSE_CLR_V << LP_CLKRST_CORE1_RESET_CAUSE_CLR_S)
#define LP_CLKRST_CORE1_RESET_CAUSE_CLR_V 0x00000001U
#define LP_CLKRST_CORE1_RESET_CAUSE_CLR_S 29
/** LP_CLKRST_CORE1_RESET_FLAG_SET : WT; bitpos: [30]; default: 0;
* configure set reset flag
*/
#define LP_CLKRST_CORE1_RESET_FLAG_SET (BIT(30))
#define LP_CLKRST_CORE1_RESET_FLAG_SET_M (LP_CLKRST_CORE1_RESET_FLAG_SET_V << LP_CLKRST_CORE1_RESET_FLAG_SET_S)
#define LP_CLKRST_CORE1_RESET_FLAG_SET_V 0x00000001U
#define LP_CLKRST_CORE1_RESET_FLAG_SET_S 30
/** LP_CLKRST_CORE1_RESET_FLAG_CLR : WT; bitpos: [31]; default: 0;
* configure clear reset flag
* 0: no operation
* 1: clear flag to 0
*/
#define LP_CLKRST_CORE1_RESET_FLAG_CLR (BIT(31))
#define LP_CLKRST_CORE1_RESET_FLAG_CLR_M (LP_CLKRST_CORE1_RESET_FLAG_CLR_V << LP_CLKRST_CORE1_RESET_FLAG_CLR_S)
#define LP_CLKRST_CORE1_RESET_FLAG_CLR_V 0x00000001U
#define LP_CLKRST_CORE1_RESET_FLAG_CLR_S 31
/** LP_CLKRST_CPU_CORE0_RESET_REG register
* Configures CPU reset
*/
#define LP_CLKRST_CPU_CORE0_RESET_REG (DR_REG_LP_BASE + 0x18)
/** LP_CLKRST_HPCORE0_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
* configure the hpcore0 luckup reset enable
* 0: disable
* 1:enable
*/
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN (BIT(21))
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S)
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_V 0x00000001U
#define LP_CLKRST_HPCORE0_LOCKUP_RESET_EN_S 21
/** LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* configures the reset length of LP_WDT reset CPU
* Measurement unit: LP_DYN_FAST_CLK
*/
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN : R/W; bitpos: [25]; default: 0;
* Configures whether or not LP_WDT can reset CPU
* 0: LP_WDT could not reset CPU when LP_WDT timeout
* 1: LP_WDT could reset CPU when LP_WDT timeout
*/
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_CORE0_RESET_EN_S 25
/** LP_CLKRST_CPU_CORE0_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* configure the time between CPU stall and reset
* Measurement unit: LP_DYN_FAST_CLK
*/
#define LP_CLKRST_CPU_CORE0_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_CORE0_STALL_WAIT_M (LP_CLKRST_CPU_CORE0_STALL_WAIT_V << LP_CLKRST_CPU_CORE0_STALL_WAIT_S)
#define LP_CLKRST_CPU_CORE0_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_CORE0_STALL_WAIT_S 26
/** LP_CLKRST_CPU_CORE0_STALL_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
* 0: CPU will not entry stall state before LP_WDT and software reset CPU
* 1: CPU will entry stall state before LP_WDT and software reset CPU
*/
#define LP_CLKRST_CPU_CORE0_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_CORE0_STALL_EN_M (LP_CLKRST_CPU_CORE0_STALL_EN_V << LP_CLKRST_CPU_CORE0_STALL_EN_S)
#define LP_CLKRST_CPU_CORE0_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_CORE0_STALL_EN_S 31
/** LP_CLKRST_CPU_CORE1_RESET_REG register
* Configures CPU reset
*/
#define LP_CLKRST_CPU_CORE1_RESET_REG (DR_REG_LP_BASE + 0x1c)
/** LP_CLKRST_HPCORE1_LOCKUP_RESET_EN : R/W; bitpos: [21]; default: 1;
* configure the hpcore0 luckup reset enable
* 0: disable
* 1:enable
*/
#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN (BIT(21))
#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_M (LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V << LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S)
#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_V 0x00000001U
#define LP_CLKRST_HPCORE1_LOCKUP_RESET_EN_S 21
/** LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH : R/W; bitpos: [24:22]; default: 1;
* configures the reset length of LP_WDT reset CPU
* Measurement unit: LP_DYN_FAST_CLK
*/
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_M (LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_V << LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_S)
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_V 0x00000007U
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_LENGTH_S 22
/** LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN : R/W; bitpos: [25]; default: 0;
* Configures whether or not LP_WDT can reset CPU
* 0: LP_WDT could not reset CPU when LP_WDT timeout
* 1: LP_WDT could reset CPU when LP_WDT timeout
*/
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN (BIT(25))
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_M (LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_V << LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_S)
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_V 0x00000001U
#define LP_CLKRST_RTC_WDT_CPU_CORE1_RESET_EN_S 25
/** LP_CLKRST_CPU_CORE1_STALL_WAIT : R/W; bitpos: [30:26]; default: 1;
* configure the time between CPU stall and reset
* Measurement unit: LP_DYN_FAST_CLK
*/
#define LP_CLKRST_CPU_CORE1_STALL_WAIT 0x0000001FU
#define LP_CLKRST_CPU_CORE1_STALL_WAIT_M (LP_CLKRST_CPU_CORE1_STALL_WAIT_V << LP_CLKRST_CPU_CORE1_STALL_WAIT_S)
#define LP_CLKRST_CPU_CORE1_STALL_WAIT_V 0x0000001FU
#define LP_CLKRST_CPU_CORE1_STALL_WAIT_S 26
/** LP_CLKRST_CPU_CORE1_STALL_EN : R/W; bitpos: [31]; default: 0;
* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
* 0: CPU will not entry stall state before LP_WDT and software reset CPU
* 1: CPU will entry stall state before LP_WDT and software reset CPU
*/
#define LP_CLKRST_CPU_CORE1_STALL_EN (BIT(31))
#define LP_CLKRST_CPU_CORE1_STALL_EN_M (LP_CLKRST_CPU_CORE1_STALL_EN_V << LP_CLKRST_CPU_CORE1_STALL_EN_S)
#define LP_CLKRST_CPU_CORE1_STALL_EN_V 0x00000001U
#define LP_CLKRST_CPU_CORE1_STALL_EN_S 31
/** LP_CLKRST_FOSC_CNTL_REG register
* Configures the RC_FAST_CLK frequency
*/
#define LP_CLKRST_FOSC_CNTL_REG (DR_REG_LP_BASE + 0x20)
/** LP_CLKRST_FOSC_DFREQ : R/W; bitpos: [31:22]; default: 547;
* Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
* field
*/
#define LP_CLKRST_FOSC_DFREQ 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_M (LP_CLKRST_FOSC_DFREQ_V << LP_CLKRST_FOSC_DFREQ_S)
#define LP_CLKRST_FOSC_DFREQ_V 0x000003FFU
#define LP_CLKRST_FOSC_DFREQ_S 22
/** LP_CLKRST_SOSC_CNTL_REG register
* Configures the RC_SLOW_CLK frequency
*/
#define LP_CLKRST_SOSC_CNTL_REG (DR_REG_LP_BASE + 0x24)
/** LP_CLKRST_SLOW_DFREQ : R/W; bitpos: [31:26]; default: 10;
* Configures the RC_SLOW_CLK frequency,the clock frequency will increase with this
* field
*/
#define LP_CLKRST_SLOW_DFREQ 0x0000003FU
#define LP_CLKRST_SLOW_DFREQ_M (LP_CLKRST_SLOW_DFREQ_V << LP_CLKRST_SLOW_DFREQ_S)
#define LP_CLKRST_SLOW_DFREQ_V 0x0000003FU
#define LP_CLKRST_SLOW_DFREQ_S 26
/** LP_CLKRST_RC32K_CNTL_REG register
* Configures the RC32K_CLK frequency
*/
#define LP_CLKRST_RC32K_CNTL_REG (DR_REG_LP_BASE + 0x28)
/** LP_CLKRST_RC32K_DFREQ : R/W; bitpos: [31:22]; default: 172;
* Configures the RC32K_CLK frequency, the clock frequency will increase with this
* field
*/
#define LP_CLKRST_RC32K_DFREQ 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_M (LP_CLKRST_RC32K_DFREQ_V << LP_CLKRST_RC32K_DFREQ_S)
#define LP_CLKRST_RC32K_DFREQ_V 0x000003FFU
#define LP_CLKRST_RC32K_DFREQ_S 22
/** LP_CLKRST_CLK_TO_HP_REG register
* Configures the clk gate of LP clk to HP system
*/
#define LP_CLKRST_CLK_TO_HP_REG (DR_REG_LP_BASE + 0x2c)
/** LP_CLKRST_CLK_PWR_FOSC_EN : R/W; bitpos: [25]; default: 1;
* Configures the clock gate to modem of the fosc clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_CLK_PWR_FOSC_EN (BIT(25))
#define LP_CLKRST_CLK_PWR_FOSC_EN_M (LP_CLKRST_CLK_PWR_FOSC_EN_V << LP_CLKRST_CLK_PWR_FOSC_EN_S)
#define LP_CLKRST_CLK_PWR_FOSC_EN_V 0x00000001U
#define LP_CLKRST_CLK_PWR_FOSC_EN_S 25
/** LP_CLKRST_CLK_PWR_XTAL_EN : R/W; bitpos: [26]; default: 1;
* Configures the clock gate to modem of the xtal clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
#define LP_CLKRST_CLK_PWR_XTAL_EN (BIT(26))
#define LP_CLKRST_CLK_PWR_XTAL_EN_M (LP_CLKRST_CLK_PWR_XTAL_EN_V << LP_CLKRST_CLK_PWR_XTAL_EN_S)
#define LP_CLKRST_CLK_PWR_XTAL_EN_V 0x00000001U
#define LP_CLKRST_CLK_PWR_XTAL_EN_S 26
/** LP_CLKRST_ICG_HP_XTAL32K : R/W; bitpos: [28]; default: 1;
* Configures the clk gate of XTAL32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_XTAL32K (BIT(28))
#define LP_CLKRST_ICG_HP_XTAL32K_M (LP_CLKRST_ICG_HP_XTAL32K_V << LP_CLKRST_ICG_HP_XTAL32K_S)
#define LP_CLKRST_ICG_HP_XTAL32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_XTAL32K_S 28
/** LP_CLKRST_ICG_HP_SOSC : R/W; bitpos: [29]; default: 1;
* Configures the clk gate of RC_SLOW_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_SOSC (BIT(29))
#define LP_CLKRST_ICG_HP_SOSC_M (LP_CLKRST_ICG_HP_SOSC_V << LP_CLKRST_ICG_HP_SOSC_S)
#define LP_CLKRST_ICG_HP_SOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_SOSC_S 29
/** LP_CLKRST_ICG_HP_OSC32K : R/W; bitpos: [30]; default: 1;
* Configures the clk gate of RC32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_OSC32K (BIT(30))
#define LP_CLKRST_ICG_HP_OSC32K_M (LP_CLKRST_ICG_HP_OSC32K_V << LP_CLKRST_ICG_HP_OSC32K_S)
#define LP_CLKRST_ICG_HP_OSC32K_V 0x00000001U
#define LP_CLKRST_ICG_HP_OSC32K_S 30
/** LP_CLKRST_ICG_HP_FOSC : R/W; bitpos: [31]; default: 1;
* Configures the clk gate of RC_FAST_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
#define LP_CLKRST_ICG_HP_FOSC (BIT(31))
#define LP_CLKRST_ICG_HP_FOSC_M (LP_CLKRST_ICG_HP_FOSC_V << LP_CLKRST_ICG_HP_FOSC_S)
#define LP_CLKRST_ICG_HP_FOSC_V 0x00000001U
#define LP_CLKRST_ICG_HP_FOSC_S 31
/** LP_CLKRST_LPMEM_FORCE_REG register
* Configures the LP_MEM clk gate force parameter
*/
#define LP_CLKRST_LPMEM_FORCE_REG (DR_REG_LP_BASE + 0x30)
/** LP_CLKRST_LPMEM_CLK_FORCE_ON : R/W; bitpos: [31]; default: 0;
* Configures whether ot not force open the clock gate of LP MEM
* 0: Invalid. The clock gate controlled by hardware FSM
* 1: Force open clock gate of LP MEM
*/
#define LP_CLKRST_LPMEM_CLK_FORCE_ON (BIT(31))
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_M (LP_CLKRST_LPMEM_CLK_FORCE_ON_V << LP_CLKRST_LPMEM_CLK_FORCE_ON_S)
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_V 0x00000001U
#define LP_CLKRST_LPMEM_CLK_FORCE_ON_S 31
/** LP_CLKRST_XTAL32K_REG register
* Configures the XTAL32K parameter
*/
#define LP_CLKRST_XTAL32K_REG (DR_REG_LP_BASE + 0x34)
/** LP_CLKRST_RTC_SEL_POWER_XTAL32K : R/W; bitpos: [21]; default: 0;
* need_des
*/
#define LP_CLKRST_RTC_SEL_POWER_XTAL32K (BIT(21))
#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_M (LP_CLKRST_RTC_SEL_POWER_XTAL32K_V << LP_CLKRST_RTC_SEL_POWER_XTAL32K_S)
#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_V 0x00000001U
#define LP_CLKRST_RTC_SEL_POWER_XTAL32K_S 21
/** LP_CLKRST_DRES_XTAL32K : R/W; bitpos: [24:22]; default: 3;
* Configures DRES
*/
#define LP_CLKRST_DRES_XTAL32K 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_M (LP_CLKRST_DRES_XTAL32K_V << LP_CLKRST_DRES_XTAL32K_S)
#define LP_CLKRST_DRES_XTAL32K_V 0x00000007U
#define LP_CLKRST_DRES_XTAL32K_S 22
/** LP_CLKRST_DGM_XTAL32K : R/W; bitpos: [27:25]; default: 3;
* Configures DGM
*/
#define LP_CLKRST_DGM_XTAL32K 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_M (LP_CLKRST_DGM_XTAL32K_V << LP_CLKRST_DGM_XTAL32K_S)
#define LP_CLKRST_DGM_XTAL32K_V 0x00000007U
#define LP_CLKRST_DGM_XTAL32K_S 25
/** LP_CLKRST_DBUF_XTAL32K : R/W; bitpos: [28]; default: 0;
* Configures DBUF
*/
#define LP_CLKRST_DBUF_XTAL32K (BIT(28))
#define LP_CLKRST_DBUF_XTAL32K_M (LP_CLKRST_DBUF_XTAL32K_V << LP_CLKRST_DBUF_XTAL32K_S)
#define LP_CLKRST_DBUF_XTAL32K_V 0x00000001U
#define LP_CLKRST_DBUF_XTAL32K_S 28
/** LP_CLKRST_DAC_XTAL32K : R/W; bitpos: [31:29]; default: 3;
* Configures DAC
*/
#define LP_CLKRST_DAC_XTAL32K 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_M (LP_CLKRST_DAC_XTAL32K_V << LP_CLKRST_DAC_XTAL32K_S)
#define LP_CLKRST_DAC_XTAL32K_V 0x00000007U
#define LP_CLKRST_DAC_XTAL32K_S 29
/** LP_CLKRST_CALI0_REG register
* need_des
*/
#define LP_CLKRST_CALI0_REG (DR_REG_LP_BASE + 0x38)
/** LP_CLKRST_LP_CALI_DIV_CYCLE : R/W; bitpos: [7:0]; default: 1;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_CYCLE 0x000000FFU
#define LP_CLKRST_LP_CALI_DIV_CYCLE_M (LP_CLKRST_LP_CALI_DIV_CYCLE_V << LP_CLKRST_LP_CALI_DIV_CYCLE_S)
#define LP_CLKRST_LP_CALI_DIV_CYCLE_V 0x000000FFU
#define LP_CLKRST_LP_CALI_DIV_CYCLE_S 0
/** LP_CLKRST_LP_CALI_FULL_CNT_DONE : RO; bitpos: [8]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE (BIT(8))
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_M (LP_CLKRST_LP_CALI_FULL_CNT_DONE_V << LP_CLKRST_LP_CALI_FULL_CNT_DONE_S)
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_V 0x00000001U
#define LP_CLKRST_LP_CALI_FULL_CNT_DONE_S 8
/** LP_CLKRST_LP_CALI_DIV_CALI_CNT : RO; bitpos: [24:9]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_M (LP_CLKRST_LP_CALI_DIV_CALI_CNT_V << LP_CLKRST_LP_CALI_DIV_CALI_CNT_S)
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_CALI_CNT_S 9
/** LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE : RO; bitpos: [25]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE (BIT(25))
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S)
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_V 0x00000001U
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_TYPE_S 25
/** LP_CLKRST_LP_CALI_DIV_NUM : RO; bitpos: [31:26]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_NUM 0x0000003FU
#define LP_CLKRST_LP_CALI_DIV_NUM_M (LP_CLKRST_LP_CALI_DIV_NUM_V << LP_CLKRST_LP_CALI_DIV_NUM_S)
#define LP_CLKRST_LP_CALI_DIV_NUM_V 0x0000003FU
#define LP_CLKRST_LP_CALI_DIV_NUM_S 26
/** LP_CLKRST_CALI1_REG register
* need_des
*/
#define LP_CLKRST_CALI1_REG (DR_REG_LP_BASE + 0x3c)
/** LP_CLKRST_LP_CALI_DIV_NUMERATOR : RO; bitpos: [15:0]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_M (LP_CLKRST_LP_CALI_DIV_NUMERATOR_V << LP_CLKRST_LP_CALI_DIV_NUMERATOR_S)
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_NUMERATOR_S 0
/** LP_CLKRST_LP_CALI_DIV_DENOMINATOR : RO; bitpos: [31:16]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_M (LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V << LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S)
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_DENOMINATOR_S 16
/** LP_CLKRST_CALI2_REG register
* need_des
*/
#define LP_CLKRST_CALI2_REG (DR_REG_LP_BASE + 0x40)
/** LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD : R/W; bitpos: [8:0]; default: 255;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD 0x000001FFU
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_M (LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V << LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S)
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_V 0x000001FFU
#define LP_CLKRST_LP_CALI_DIV_WAIT_PWR_GOOD_S 0
/** LP_CLKRST_LP_CALI_DIV_SLP_VAL : R/W; bitpos: [30:15]; default: 1;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_M (LP_CLKRST_LP_CALI_DIV_SLP_VAL_V << LP_CLKRST_LP_CALI_DIV_SLP_VAL_S)
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_V 0x0000FFFFU
#define LP_CLKRST_LP_CALI_DIV_SLP_VAL_S 15
/** LP_CLKRST_LP_CALI_DIV_TIMER_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN (BIT(31))
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_M (LP_CLKRST_LP_CALI_DIV_TIMER_EN_V << LP_CLKRST_LP_CALI_DIV_TIMER_EN_S)
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_V 0x00000001U
#define LP_CLKRST_LP_CALI_DIV_TIMER_EN_S 31
/** LP_CLKRST_LPPERI_REG register
* need_des
*/
#define LP_CLKRST_LPPERI_REG (DR_REG_LP_BASE + 0x44)
/** LP_CLKRST_HUK_CLK_SEL : R/W; bitpos: [11]; default: 1;
* Configures the source clk of HUK
* 0: 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
*/
#define LP_CLKRST_HUK_CLK_SEL (BIT(11))
#define LP_CLKRST_HUK_CLK_SEL_M (LP_CLKRST_HUK_CLK_SEL_V << LP_CLKRST_HUK_CLK_SEL_S)
#define LP_CLKRST_HUK_CLK_SEL_V 0x00000001U
#define LP_CLKRST_HUK_CLK_SEL_S 11
/** LP_CLKRST_LP_BLETIMER_DIV_NUM : R/W; bitpos: [23:12]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_BLETIMER_DIV_NUM 0x00000FFFU
#define LP_CLKRST_LP_BLETIMER_DIV_NUM_M (LP_CLKRST_LP_BLETIMER_DIV_NUM_V << LP_CLKRST_LP_BLETIMER_DIV_NUM_S)
#define LP_CLKRST_LP_BLETIMER_DIV_NUM_V 0x00000FFFU
#define LP_CLKRST_LP_BLETIMER_DIV_NUM_S 12
/** LP_CLKRST_LP_BLETIMER_32K_SEL : R/W; bitpos: [25:24]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_BLETIMER_32K_SEL 0x00000003U
#define LP_CLKRST_LP_BLETIMER_32K_SEL_M (LP_CLKRST_LP_BLETIMER_32K_SEL_V << LP_CLKRST_LP_BLETIMER_32K_SEL_S)
#define LP_CLKRST_LP_BLETIMER_32K_SEL_V 0x00000003U
#define LP_CLKRST_LP_BLETIMER_32K_SEL_S 24
/** LP_CLKRST_LP_SEL_OSC_SLOW : R/W; bitpos: [26]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_SEL_OSC_SLOW (BIT(26))
#define LP_CLKRST_LP_SEL_OSC_SLOW_M (LP_CLKRST_LP_SEL_OSC_SLOW_V << LP_CLKRST_LP_SEL_OSC_SLOW_S)
#define LP_CLKRST_LP_SEL_OSC_SLOW_V 0x00000001U
#define LP_CLKRST_LP_SEL_OSC_SLOW_S 26
/** LP_CLKRST_LP_SEL_OSC_FAST : R/W; bitpos: [27]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_SEL_OSC_FAST (BIT(27))
#define LP_CLKRST_LP_SEL_OSC_FAST_M (LP_CLKRST_LP_SEL_OSC_FAST_V << LP_CLKRST_LP_SEL_OSC_FAST_S)
#define LP_CLKRST_LP_SEL_OSC_FAST_V 0x00000001U
#define LP_CLKRST_LP_SEL_OSC_FAST_S 27
/** LP_CLKRST_LP_SEL_XTAL : R/W; bitpos: [28]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_SEL_XTAL (BIT(28))
#define LP_CLKRST_LP_SEL_XTAL_M (LP_CLKRST_LP_SEL_XTAL_V << LP_CLKRST_LP_SEL_XTAL_S)
#define LP_CLKRST_LP_SEL_XTAL_V 0x00000001U
#define LP_CLKRST_LP_SEL_XTAL_S 28
/** LP_CLKRST_LP_SEL_XTAL32K : R/W; bitpos: [29]; default: 0;
* need_des
*/
#define LP_CLKRST_LP_SEL_XTAL32K (BIT(29))
#define LP_CLKRST_LP_SEL_XTAL32K_M (LP_CLKRST_LP_SEL_XTAL32K_V << LP_CLKRST_LP_SEL_XTAL32K_S)
#define LP_CLKRST_LP_SEL_XTAL32K_V 0x00000001U
#define LP_CLKRST_LP_SEL_XTAL32K_S 29
/** LP_CLKRST_DATE_REG register
* Version control register
*/
#define LP_CLKRST_DATE_REG (DR_REG_LP_BASE + 0x3fc)
/** LP_CLKRST_CLKRST_DATE : R/W; bitpos: [30:0]; default: 37818640;
* Version control register
*/
#define LP_CLKRST_CLKRST_DATE 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_M (LP_CLKRST_CLKRST_DATE_V << LP_CLKRST_CLKRST_DATE_S)
#define LP_CLKRST_CLKRST_DATE_V 0x7FFFFFFFU
#define LP_CLKRST_CLKRST_DATE_S 0
/** LP_CLKRST_CLK_EN : R/W; bitpos: [31]; default: 0;
* configure register clk bypass clk gate
*/
#define LP_CLKRST_CLK_EN (BIT(31))
#define LP_CLKRST_CLK_EN_M (LP_CLKRST_CLK_EN_V << LP_CLKRST_CLK_EN_S)
#define LP_CLKRST_CLK_EN_V 0x00000001U
#define LP_CLKRST_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_clkrst_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of lp_clk_conf register
* Configures the root clk of LP system
*/
typedef union {
struct {
/** slow_clk_sel : R/W; bitpos: [1:0]; default: 0;
* Configures the source of LP_SLOW_CLK.
* 0: RC_SLOW_CLK
* 1: XTAL32K_CLK
* 2: RC32K_CLK
* 3:OSC_SLOW_CLK
*/
uint32_t slow_clk_sel:2;
/** fast_clk_sel : R/W; bitpos: [2]; default: 1;
* configures the source of LP_FAST_CLK.
* 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
*/
uint32_t fast_clk_sel:1;
/** lp_peri_div_num : R/W; bitpos: [10:3]; default: 0;
* reserved
*/
uint32_t lp_peri_div_num:8;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_conf_reg_t;
/** Type of lp_clk_po_en register
* Configures the clk gate to pad
*/
typedef union {
struct {
/** aon_slow_oen : R/W; bitpos: [0]; default: 1;
* Configures the clock gate to pad of the LP_DYN_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t aon_slow_oen:1;
/** aon_fast_oen : R/W; bitpos: [1]; default: 1;
* Configures the clock gate to pad of the LP_DYN_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t aon_fast_oen:1;
/** sosc_oen : R/W; bitpos: [2]; default: 1;
* Configures the clock gate to pad of the OSC_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t sosc_oen:1;
/** fosc_oen : R/W; bitpos: [3]; default: 1;
* Configures the clock gate to pad of the RC_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t fosc_oen:1;
/** osc32k_oen : R/W; bitpos: [4]; default: 1;
* Configures the clock gate to pad of the RC32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t osc32k_oen:1;
/** xtal32k_oen : R/W; bitpos: [5]; default: 1;
* Configures the clock gate to pad of the XTAL32K_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t xtal32k_oen:1;
/** core_efuse_oen : R/W; bitpos: [6]; default: 1;
* Configures the clock gate to pad of the EFUSE_CTRL clock.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t core_efuse_oen:1;
/** slow_oen : R/W; bitpos: [7]; default: 1;
* Configures the clock gate to pad of the LP_SLOW_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t slow_oen:1;
/** fast_oen : R/W; bitpos: [8]; default: 1;
* Configures the clock gate to pad of the LP_FAST_CLK.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t fast_oen:1;
/** rng_oen : R/W; bitpos: [9]; default: 1;
* Configures the clock gate to pad of the RNG clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t rng_oen:1;
/** lpbus_oen : R/W; bitpos: [10]; default: 1;
* Configures the clock gate to pad of the LP bus clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t lpbus_oen:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_clkrst_lp_clk_po_en_reg_t;
/** Type of lp_clk_en register
* Configure LP root clk source gate
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** rtc_ble_timer_apb_gate : R/W; bitpos: [27]; default: 1;
* Configures the clock gate to RTC_BLE_TIMER_APB_CLK
* 0: Invalid. The clock gate controlled
* 1: Force the clk pass clock gate
*/
uint32_t rtc_ble_timer_apb_gate:1;
/** total_core_efuse_gate : R/W; bitpos: [28]; default: 1;
* Configures the clock gate to TOTAL_EFUSE_AON_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
uint32_t total_core_efuse_gate:1;
/** aon_core_efuse_gate : R/W; bitpos: [29]; default: 1;
* Configures the clock gate to CORE_EFUSE_AON_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
uint32_t aon_core_efuse_gate:1;
/** aon_touch_gate : R/W; bitpos: [30]; default: 1;
* Configures the clock gate to TOUCH_AON_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
uint32_t aon_touch_gate:1;
/** fast_ori_gate : R/W; bitpos: [31]; default: 0;
* Configures the clock gate to LP_FAST_CLK
* 0: Invalid. The clock gate controlled by hardware fsm
* 1: Force the clk pass clock gate
*/
uint32_t fast_ori_gate:1;
};
uint32_t val;
} lp_clkrst_lp_clk_en_reg_t;
/** Type of lp_rst_en register
* Configures the peri of LP system software reset
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** huk_reset_en : R/W; bitpos: [25]; default: 0;
* Configures whether or not to reset HUK
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t huk_reset_en:1;
/** aon_bletimer_reset_en : R/W; bitpos: [26]; default: 0;
* Configures whether or not to reset bletimer part
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t aon_bletimer_reset_en:1;
/** aon_touch_reset_en : R/W; bitpos: [27]; default: 0;
* Configures whether or not to reset TOUCH part
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t aon_touch_reset_en:1;
/** aon_efuse_core_reset_en : R/W; bitpos: [28]; default: 0;
* Configures whether or not to reset EFUSE_CTRL always-on part
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t aon_efuse_core_reset_en:1;
/** lp_timer_reset_en : R/W; bitpos: [29]; default: 0;
* Configures whether or not to reset LP_TIMER
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t lp_timer_reset_en:1;
/** wdt_reset_en : R/W; bitpos: [30]; default: 0;
* Configures whether or not to reset LP_WDT and super watch dog
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t wdt_reset_en:1;
/** ana_peri_reset_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not to reset analog peri, include brownout controller
* 0: Invalid.No effect
* 1: Reset
*/
uint32_t ana_peri_reset_en:1;
};
uint32_t val;
} lp_clkrst_lp_rst_en_reg_t;
/** Type of reset_core0_cause register
* Represents the reset cause
*/
typedef union {
struct {
/** core0_reset_cause : RO; bitpos: [4:0]; default: 0;
* Represents the reset cause
*/
uint32_t core0_reset_cause:5;
/** core0_reset_flag : RO; bitpos: [5]; default: 1;
* Represents the reset flag
*/
uint32_t core0_reset_flag:1;
uint32_t reserved_6:23;
/** core0_reset_cause_clr : WT; bitpos: [29]; default: 0;
* 0: no operation
*/
uint32_t core0_reset_cause_clr:1;
/** core0_reset_flag_set : WT; bitpos: [30]; default: 0;
* configure set reset flag
*/
uint32_t core0_reset_flag_set:1;
/** core0_reset_flag_clr : WT; bitpos: [31]; default: 0;
* configure clear reset flag
* 0: no operation
* 1: clear flag to 0
*/
uint32_t core0_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_core0_cause_reg_t;
/** Type of reset_core1_cause register
* Represents the reset cause
*/
typedef union {
struct {
/** core1_reset_cause : RO; bitpos: [4:0]; default: 0;
* Represents the reset cause
*/
uint32_t core1_reset_cause:5;
/** core1_reset_flag : RO; bitpos: [5]; default: 1;
* Represents the reset flag
*/
uint32_t core1_reset_flag:1;
uint32_t reserved_6:23;
/** core1_reset_cause_clr : WT; bitpos: [29]; default: 0;
* 0: no operation
*/
uint32_t core1_reset_cause_clr:1;
/** core1_reset_flag_set : WT; bitpos: [30]; default: 0;
* configure set reset flag
*/
uint32_t core1_reset_flag_set:1;
/** core1_reset_flag_clr : WT; bitpos: [31]; default: 0;
* configure clear reset flag
* 0: no operation
* 1: clear flag to 0
*/
uint32_t core1_reset_flag_clr:1;
};
uint32_t val;
} lp_clkrst_reset_core1_cause_reg_t;
/** Type of cpu_core0_reset register
* Configures CPU reset
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** hpcore0_lockup_reset_en : R/W; bitpos: [21]; default: 1;
* configure the hpcore0 luckup reset enable
* 0: disable
* 1:enable
*/
uint32_t hpcore0_lockup_reset_en:1;
/** rtc_wdt_cpu_core0_reset_length : R/W; bitpos: [24:22]; default: 1;
* configures the reset length of LP_WDT reset CPU
* Measurement unit: LP_DYN_FAST_CLK
*/
uint32_t rtc_wdt_cpu_core0_reset_length:3;
/** rtc_wdt_cpu_core0_reset_en : R/W; bitpos: [25]; default: 0;
* Configures whether or not LP_WDT can reset CPU
* 0: LP_WDT could not reset CPU when LP_WDT timeout
* 1: LP_WDT could reset CPU when LP_WDT timeout
*/
uint32_t rtc_wdt_cpu_core0_reset_en:1;
/** cpu_core0_stall_wait : R/W; bitpos: [30:26]; default: 1;
* configure the time between CPU stall and reset
* Measurement unit: LP_DYN_FAST_CLK
*/
uint32_t cpu_core0_stall_wait:5;
/** cpu_core0_stall_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
* 0: CPU will not entry stall state before LP_WDT and software reset CPU
* 1: CPU will entry stall state before LP_WDT and software reset CPU
*/
uint32_t cpu_core0_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_core0_reset_reg_t;
/** Type of cpu_core1_reset register
* Configures CPU reset
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** hpcore1_lockup_reset_en : R/W; bitpos: [21]; default: 1;
* configure the hpcore0 luckup reset enable
* 0: disable
* 1:enable
*/
uint32_t hpcore1_lockup_reset_en:1;
/** rtc_wdt_cpu_core1_reset_length : R/W; bitpos: [24:22]; default: 1;
* configures the reset length of LP_WDT reset CPU
* Measurement unit: LP_DYN_FAST_CLK
*/
uint32_t rtc_wdt_cpu_core1_reset_length:3;
/** rtc_wdt_cpu_core1_reset_en : R/W; bitpos: [25]; default: 0;
* Configures whether or not LP_WDT can reset CPU
* 0: LP_WDT could not reset CPU when LP_WDT timeout
* 1: LP_WDT could reset CPU when LP_WDT timeout
*/
uint32_t rtc_wdt_cpu_core1_reset_en:1;
/** cpu_core1_stall_wait : R/W; bitpos: [30:26]; default: 1;
* configure the time between CPU stall and reset
* Measurement unit: LP_DYN_FAST_CLK
*/
uint32_t cpu_core1_stall_wait:5;
/** cpu_core1_stall_en : R/W; bitpos: [31]; default: 0;
* Configures whether or not CPU entry stall state before LP_WDT and software reset CPU
* 0: CPU will not entry stall state before LP_WDT and software reset CPU
* 1: CPU will entry stall state before LP_WDT and software reset CPU
*/
uint32_t cpu_core1_stall_en:1;
};
uint32_t val;
} lp_clkrst_cpu_core1_reset_reg_t;
/** Type of fosc_cntl register
* Configures the RC_FAST_CLK frequency
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** fosc_dfreq : R/W; bitpos: [31:22]; default: 547;
* Configures the RC_FAST_CLK frequency,the clock frequency will increase with this
* field
*/
uint32_t fosc_dfreq:10;
};
uint32_t val;
} lp_clkrst_fosc_cntl_reg_t;
/** Type of sosc_cntl register
* Configures the RC_SLOW_CLK frequency
*/
typedef union {
struct {
uint32_t reserved_0:26;
/** slow_dfreq : R/W; bitpos: [31:26]; default: 10;
* Configures the RC_SLOW_CLK frequency,the clock frequency will increase with this
* field
*/
uint32_t slow_dfreq:6;
};
uint32_t val;
} lp_clkrst_sosc_cntl_reg_t;
/** Type of rc32k_cntl register
* Configures the RC32K_CLK frequency
*/
typedef union {
struct {
uint32_t reserved_0:22;
/** rc32k_dfreq : R/W; bitpos: [31:22]; default: 172;
* Configures the RC32K_CLK frequency, the clock frequency will increase with this
* field
*/
uint32_t rc32k_dfreq:10;
};
uint32_t val;
} lp_clkrst_rc32k_cntl_reg_t;
/** Type of clk_to_hp register
* Configures the clk gate of LP clk to HP system
*/
typedef union {
struct {
uint32_t reserved_0:25;
/** clk_pwr_fosc_en : R/W; bitpos: [25]; default: 1;
* Configures the clock gate to modem of the fosc clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t clk_pwr_fosc_en:1;
/** clk_pwr_xtal_en : R/W; bitpos: [26]; default: 1;
* Configures the clock gate to modem of the xtal clk.
* 0: Disable the clk pass clock gate
* 1: Enable the clk pass clock gate
*/
uint32_t clk_pwr_xtal_en:1;
uint32_t reserved_27:1;
/** icg_hp_xtal32k : R/W; bitpos: [28]; default: 1;
* Configures the clk gate of XTAL32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_xtal32k:1;
/** icg_hp_sosc : R/W; bitpos: [29]; default: 1;
* Configures the clk gate of RC_SLOW_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_sosc:1;
/** icg_hp_osc32k : R/W; bitpos: [30]; default: 1;
* Configures the clk gate of RC32K_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_osc32k:1;
/** icg_hp_fosc : R/W; bitpos: [31]; default: 1;
* Configures the clk gate of RC_FAST_CLK to HP system
* 0: The clk could not pass to HP system
* 1: The clk could pass to HP system
*/
uint32_t icg_hp_fosc:1;
};
uint32_t val;
} lp_clkrst_clk_to_hp_reg_t;
/** Type of lpmem_force register
* Configures the LP_MEM clk gate force parameter
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** lpmem_clk_force_on : R/W; bitpos: [31]; default: 0;
* Configures whether ot not force open the clock gate of LP MEM
* 0: Invalid. The clock gate controlled by hardware FSM
* 1: Force open clock gate of LP MEM
*/
uint32_t lpmem_clk_force_on:1;
};
uint32_t val;
} lp_clkrst_lpmem_force_reg_t;
/** Type of xtal32k register
* Configures the XTAL32K parameter
*/
typedef union {
struct {
uint32_t reserved_0:21;
/** rtc_sel_power_xtal32k : R/W; bitpos: [21]; default: 0;
* need_des
*/
uint32_t rtc_sel_power_xtal32k:1;
/** dres_xtal32k : R/W; bitpos: [24:22]; default: 3;
* Configures DRES
*/
uint32_t dres_xtal32k:3;
/** dgm_xtal32k : R/W; bitpos: [27:25]; default: 3;
* Configures DGM
*/
uint32_t dgm_xtal32k:3;
/** dbuf_xtal32k : R/W; bitpos: [28]; default: 0;
* Configures DBUF
*/
uint32_t dbuf_xtal32k:1;
/** dac_xtal32k : R/W; bitpos: [31:29]; default: 3;
* Configures DAC
*/
uint32_t dac_xtal32k:3;
};
uint32_t val;
} lp_clkrst_xtal32k_reg_t;
/** Type of cali0 register
* need_des
*/
typedef union {
struct {
/** lp_cali_div_cycle : R/W; bitpos: [7:0]; default: 1;
* need_des
*/
uint32_t lp_cali_div_cycle:8;
/** lp_cali_full_cnt_done : RO; bitpos: [8]; default: 0;
* need_des
*/
uint32_t lp_cali_full_cnt_done:1;
/** lp_cali_div_cali_cnt : RO; bitpos: [24:9]; default: 0;
* need_des
*/
uint32_t lp_cali_div_cali_cnt:16;
/** lp_cali_div_numerator_type : RO; bitpos: [25]; default: 0;
* need_des
*/
uint32_t lp_cali_div_numerator_type:1;
/** lp_cali_div_num : RO; bitpos: [31:26]; default: 0;
* need_des
*/
uint32_t lp_cali_div_num:6;
};
uint32_t val;
} lp_clkrst_cali0_reg_t;
/** Type of cali1 register
* need_des
*/
typedef union {
struct {
/** lp_cali_div_numerator : RO; bitpos: [15:0]; default: 0;
* need_des
*/
uint32_t lp_cali_div_numerator:16;
/** lp_cali_div_denominator : RO; bitpos: [31:16]; default: 0;
* need_des
*/
uint32_t lp_cali_div_denominator:16;
};
uint32_t val;
} lp_clkrst_cali1_reg_t;
/** Type of cali2 register
* need_des
*/
typedef union {
struct {
/** lp_cali_div_wait_pwr_good : R/W; bitpos: [8:0]; default: 255;
* need_des
*/
uint32_t lp_cali_div_wait_pwr_good:9;
uint32_t reserved_9:6;
/** lp_cali_div_slp_val : R/W; bitpos: [30:15]; default: 1;
* need_des
*/
uint32_t lp_cali_div_slp_val:16;
/** lp_cali_div_timer_en : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t lp_cali_div_timer_en:1;
};
uint32_t val;
} lp_clkrst_cali2_reg_t;
/** Type of lpperi register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:11;
/** huk_clk_sel : R/W; bitpos: [11]; default: 1;
* Configures the source clk of HUK
* 0: 0: RC_FAST_CLK
* 1: XTAL_D2_CLK
*/
uint32_t huk_clk_sel:1;
/** lp_bletimer_div_num : R/W; bitpos: [23:12]; default: 0;
* need_des
*/
uint32_t lp_bletimer_div_num:12;
/** lp_bletimer_32k_sel : R/W; bitpos: [25:24]; default: 0;
* need_des
*/
uint32_t lp_bletimer_32k_sel:2;
/** lp_sel_osc_slow : R/W; bitpos: [26]; default: 0;
* need_des
*/
uint32_t lp_sel_osc_slow:1;
/** lp_sel_osc_fast : R/W; bitpos: [27]; default: 0;
* need_des
*/
uint32_t lp_sel_osc_fast:1;
/** lp_sel_xtal : R/W; bitpos: [28]; default: 0;
* need_des
*/
uint32_t lp_sel_xtal:1;
/** lp_sel_xtal32k : R/W; bitpos: [29]; default: 0;
* need_des
*/
uint32_t lp_sel_xtal32k:1;
uint32_t reserved_30:2;
};
uint32_t val;
} lp_clkrst_lpperi_reg_t;
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 37818640;
* Version control register
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* configure register clk bypass clk gate
*/
uint32_t clk_en:1;
};
uint32_t val;
} lp_clkrst_date_reg_t;
typedef struct {
volatile lp_clkrst_lp_clk_conf_reg_t lp_clk_conf;
volatile lp_clkrst_lp_clk_po_en_reg_t lp_clk_po_en;
volatile lp_clkrst_lp_clk_en_reg_t lp_clk_en;
volatile lp_clkrst_lp_rst_en_reg_t lp_rst_en;
volatile lp_clkrst_reset_core0_cause_reg_t reset_core0_cause;
volatile lp_clkrst_reset_core1_cause_reg_t reset_core1_cause;
volatile lp_clkrst_cpu_core0_reset_reg_t cpu_core0_reset;
volatile lp_clkrst_cpu_core1_reset_reg_t cpu_core1_reset;
volatile lp_clkrst_fosc_cntl_reg_t fosc_cntl;
volatile lp_clkrst_sosc_cntl_reg_t sosc_cntl;
volatile lp_clkrst_rc32k_cntl_reg_t rc32k_cntl;
volatile lp_clkrst_clk_to_hp_reg_t clk_to_hp;
volatile lp_clkrst_lpmem_force_reg_t lpmem_force;
volatile lp_clkrst_xtal32k_reg_t xtal32k;
volatile lp_clkrst_cali0_reg_t cali0;
volatile lp_clkrst_cali1_reg_t cali1;
volatile lp_clkrst_cali2_reg_t cali2;
volatile lp_clkrst_lpperi_reg_t lpperi;
uint32_t reserved_048[237];
volatile lp_clkrst_date_reg_t date;
} lp_clkrst_dev_t;
extern lp_clkrst_dev_t LP_CLKRST;
#ifndef __cplusplus
_Static_assert(sizeof(lp_clkrst_dev_t) == 0x400, "Invalid size of lp_clkrst_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_gpio_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_GPIO_OUT_REG register
* LP_GPIO output register
*/
#define LP_GPIO_OUT_REG (DR_REG_LP_BASE + 0x4)
/** LP_GPIO_OUT_DATA_ORIG : R/W/WTC; bitpos: [5:0]; default: 0;
* Configures the output value of LP_GPIO0 ~ 5 output in simple LP_GPIO output mode.
* 0: Low level
* 1: High level
* The value of bit0 ~ bit5 correspond to the output value of LP_GPIO0 ~ LP_GPIO5
* respectively. Bitxx ~ bitxx is invalid.
*/
#define LP_GPIO_OUT_DATA_ORIG 0x0000003FU
#define LP_GPIO_OUT_DATA_ORIG_M (LP_GPIO_OUT_DATA_ORIG_V << LP_GPIO_OUT_DATA_ORIG_S)
#define LP_GPIO_OUT_DATA_ORIG_V 0x0000003FU
#define LP_GPIO_OUT_DATA_ORIG_S 0
/** LP_GPIO_OUT_W1TS_REG register
* LP_GPIO output set register
*/
#define LP_GPIO_OUT_W1TS_REG (DR_REG_LP_BASE + 0x8)
/** LP_GPIO_OUT_W1TS : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~
* LP_GPIO5.
* 0: Not set
* 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set LP_GPIO_OUT_REG.
*/
#define LP_GPIO_OUT_W1TS 0x0000003FU
#define LP_GPIO_OUT_W1TS_M (LP_GPIO_OUT_W1TS_V << LP_GPIO_OUT_W1TS_S)
#define LP_GPIO_OUT_W1TS_V 0x0000003FU
#define LP_GPIO_OUT_W1TS_S 0
/** LP_GPIO_OUT_W1TC_REG register
* LP_GPIO output clear register
*/
#define LP_GPIO_OUT_W1TC_REG (DR_REG_LP_BASE + 0xc)
/** LP_GPIO_OUT_W1TC : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0
* ~ LP_GPIO5 output.
* 0: Not clear
* 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared.
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear LP_GPIO_OUT_REG.
*/
#define LP_GPIO_OUT_W1TC 0x0000003FU
#define LP_GPIO_OUT_W1TC_M (LP_GPIO_OUT_W1TC_V << LP_GPIO_OUT_W1TC_S)
#define LP_GPIO_OUT_W1TC_V 0x0000003FU
#define LP_GPIO_OUT_W1TC_S 0
/** LP_GPIO_ENABLE_REG register
* LP_GPIO output enable register
*/
#define LP_GPIO_ENABLE_REG (DR_REG_LP_BASE + 0x10)
/** LP_GPIO_ENABLE_DATA : R/W/WTC; bitpos: [5:0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO5.
* 0: Not enable
* 1: Enable
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
*/
#define LP_GPIO_ENABLE_DATA 0x0000003FU
#define LP_GPIO_ENABLE_DATA_M (LP_GPIO_ENABLE_DATA_V << LP_GPIO_ENABLE_DATA_S)
#define LP_GPIO_ENABLE_DATA_V 0x0000003FU
#define LP_GPIO_ENABLE_DATA_S 0
/** LP_GPIO_ENABLE_W1TS_REG register
* LP_GPIO output enable set register
*/
#define LP_GPIO_ENABLE_W1TS_REG (DR_REG_LP_BASE + 0x14)
/** LP_GPIO_ENABLE_W1TS : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of
* LP_GPIO0 ~ LP_GPIO5.
* 0: Not set
* 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set LP_GPIO_ENABLE_REG.
*/
#define LP_GPIO_ENABLE_W1TS 0x0000003FU
#define LP_GPIO_ENABLE_W1TS_M (LP_GPIO_ENABLE_W1TS_V << LP_GPIO_ENABLE_W1TS_S)
#define LP_GPIO_ENABLE_W1TS_V 0x0000003FU
#define LP_GPIO_ENABLE_W1TS_S 0
/** LP_GPIO_ENABLE_W1TC_REG register
* LP_GPIO output enable clear register
*/
#define LP_GPIO_ENABLE_W1TC_REG (DR_REG_LP_BASE + 0x18)
/** LP_GPIO_ENABLE_W1TC : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of
* LP_GPIO0 ~ LP_GPIO5.
* 0: Not clear
* 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear LP_GPIO_ENABLE_REG.
*/
#define LP_GPIO_ENABLE_W1TC 0x0000003FU
#define LP_GPIO_ENABLE_W1TC_M (LP_GPIO_ENABLE_W1TC_V << LP_GPIO_ENABLE_W1TC_S)
#define LP_GPIO_ENABLE_W1TC_V 0x0000003FU
#define LP_GPIO_ENABLE_W1TC_S 0
/** LP_GPIO_IN_REG register
* LP_GPIO input register
*/
#define LP_GPIO_IN_REG (DR_REG_LP_BASE + 0x1c)
/** LP_GPIO_IN_DATA_NEXT : RO; bitpos: [5:0]; default: 0;
* Represents the input value of LP_GPIO0 ~ LP_GPIO5. Each bit represents a pin input
* value:
* 0: Low level
* 1: High level
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
*/
#define LP_GPIO_IN_DATA_NEXT 0x0000003FU
#define LP_GPIO_IN_DATA_NEXT_M (LP_GPIO_IN_DATA_NEXT_V << LP_GPIO_IN_DATA_NEXT_S)
#define LP_GPIO_IN_DATA_NEXT_V 0x0000003FU
#define LP_GPIO_IN_DATA_NEXT_S 0
/** LP_GPIO_STATUS_REG register
* LP_GPIO interrupt status register
*/
#define LP_GPIO_STATUS_REG (DR_REG_LP_BASE + 0x20)
/** LP_GPIO_STATUS_INTERRUPT : R/W/WTC; bitpos: [5:0]; default: 0;
* The interrupt status of LP_GPIO0 ~ LP_GPIO5, can be configured by the software.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* - Each bit represents the status of its corresponding LP_GPIO:
*
* - 0: Represents the LP_GPIO does not generate the interrupt configured by
* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
* - 1: Represents the LP_GPIO generates the interrupt configured by
* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software.
*
*/
#define LP_GPIO_STATUS_INTERRUPT 0x0000003FU
#define LP_GPIO_STATUS_INTERRUPT_M (LP_GPIO_STATUS_INTERRUPT_V << LP_GPIO_STATUS_INTERRUPT_S)
#define LP_GPIO_STATUS_INTERRUPT_V 0x0000003FU
#define LP_GPIO_STATUS_INTERRUPT_S 0
/** LP_GPIO_STATUS_W1TS_REG register
* LP_GPIO interrupt status set register
*/
#define LP_GPIO_STATUS_W1TS_REG (DR_REG_LP_BASE + 0x24)
/** LP_GPIO_STATUS_W1TS : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the interrupt status register
* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
* register to set LP_GPIO_STATUS_INTERRUPT.
*/
#define LP_GPIO_STATUS_W1TS 0x0000003FU
#define LP_GPIO_STATUS_W1TS_M (LP_GPIO_STATUS_W1TS_V << LP_GPIO_STATUS_W1TS_S)
#define LP_GPIO_STATUS_W1TS_V 0x0000003FU
#define LP_GPIO_STATUS_W1TS_S 0
/** LP_GPIO_STATUS_W1TC_REG register
* LP_GPIO interrupt status clear register
*/
#define LP_GPIO_STATUS_W1TC_REG (DR_REG_LP_BASE + 0x28)
/** LP_GPIO_STATUS_W1TC : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the interrupt status register
* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
* register to clear LP_GPIO_STATUS_INTERRUPT.
*/
#define LP_GPIO_STATUS_W1TC 0x0000003FU
#define LP_GPIO_STATUS_W1TC_M (LP_GPIO_STATUS_W1TC_V << LP_GPIO_STATUS_W1TC_S)
#define LP_GPIO_STATUS_W1TC_V 0x0000003FU
#define LP_GPIO_STATUS_W1TC_S 0
/** LP_GPIO_STATUS_NEXT_REG register
* LP_GPIO interrupt source register
*/
#define LP_GPIO_STATUS_NEXT_REG (DR_REG_LP_BASE + 0x2c)
/** LP_GPIO_STATUS_INTERRUPT_NEXT : RO; bitpos: [5:0]; default: 0;
* Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO5.
* Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Each bit represents:
* 0: The LP_GPIO does not generate the interrupt configured by LP_GPIO_PIN$n_INT_TYPE.
* 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE.
* The interrupt could be rising edge interrupt, falling edge interrupt, level
* sensitive interrupt and any edge interrupt.
*/
#define LP_GPIO_STATUS_INTERRUPT_NEXT 0x0000003FU
#define LP_GPIO_STATUS_INTERRUPT_NEXT_M (LP_GPIO_STATUS_INTERRUPT_NEXT_V << LP_GPIO_STATUS_INTERRUPT_NEXT_S)
#define LP_GPIO_STATUS_INTERRUPT_NEXT_V 0x0000003FU
#define LP_GPIO_STATUS_INTERRUPT_NEXT_S 0
/** LP_GPIO_PIN0_REG register
* LP_GPIO0 configuration register
*/
#define LP_GPIO_PIN0_REG (DR_REG_LP_BASE + 0x30)
/** LP_GPIO_PIN0_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN0_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN0_SYNC2_BYPASS_M (LP_GPIO_PIN0_SYNC2_BYPASS_V << LP_GPIO_PIN0_SYNC2_BYPASS_S)
#define LP_GPIO_PIN0_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN0_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN0_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
#define LP_GPIO_PIN0_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN0_PAD_DRIVER_M (LP_GPIO_PIN0_PAD_DRIVER_V << LP_GPIO_PIN0_PAD_DRIVER_S)
#define LP_GPIO_PIN0_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN0_PAD_DRIVER_S 2
/** LP_GPIO_PIN0_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN0_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN0_SYNC1_BYPASS_M (LP_GPIO_PIN0_SYNC1_BYPASS_V << LP_GPIO_PIN0_SYNC1_BYPASS_S)
#define LP_GPIO_PIN0_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN0_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN0_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN0_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN0_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
#define LP_GPIO_PIN0_INT_TYPE 0x00000007U
#define LP_GPIO_PIN0_INT_TYPE_M (LP_GPIO_PIN0_INT_TYPE_V << LP_GPIO_PIN0_INT_TYPE_S)
#define LP_GPIO_PIN0_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN0_INT_TYPE_S 7
/** LP_GPIO_PIN0_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
#define LP_GPIO_PIN0_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN0_WAKEUP_ENABLE_M (LP_GPIO_PIN0_WAKEUP_ENABLE_V << LP_GPIO_PIN0_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN0_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN0_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN1_REG register
* LP_GPIO1 configuration register
*/
#define LP_GPIO_PIN1_REG (DR_REG_LP_BASE + 0x34)
/** LP_GPIO_PIN1_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN1_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN1_SYNC2_BYPASS_M (LP_GPIO_PIN1_SYNC2_BYPASS_V << LP_GPIO_PIN1_SYNC2_BYPASS_S)
#define LP_GPIO_PIN1_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN1_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN1_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
#define LP_GPIO_PIN1_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN1_PAD_DRIVER_M (LP_GPIO_PIN1_PAD_DRIVER_V << LP_GPIO_PIN1_PAD_DRIVER_S)
#define LP_GPIO_PIN1_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN1_PAD_DRIVER_S 2
/** LP_GPIO_PIN1_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN1_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN1_SYNC1_BYPASS_M (LP_GPIO_PIN1_SYNC1_BYPASS_V << LP_GPIO_PIN1_SYNC1_BYPASS_S)
#define LP_GPIO_PIN1_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN1_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN1_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN1_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN1_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
#define LP_GPIO_PIN1_INT_TYPE 0x00000007U
#define LP_GPIO_PIN1_INT_TYPE_M (LP_GPIO_PIN1_INT_TYPE_V << LP_GPIO_PIN1_INT_TYPE_S)
#define LP_GPIO_PIN1_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN1_INT_TYPE_S 7
/** LP_GPIO_PIN1_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
#define LP_GPIO_PIN1_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN1_WAKEUP_ENABLE_M (LP_GPIO_PIN1_WAKEUP_ENABLE_V << LP_GPIO_PIN1_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN1_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN1_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN2_REG register
* LP_GPIO2 configuration register
*/
#define LP_GPIO_PIN2_REG (DR_REG_LP_BASE + 0x38)
/** LP_GPIO_PIN2_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN2_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN2_SYNC2_BYPASS_M (LP_GPIO_PIN2_SYNC2_BYPASS_V << LP_GPIO_PIN2_SYNC2_BYPASS_S)
#define LP_GPIO_PIN2_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN2_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN2_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
#define LP_GPIO_PIN2_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN2_PAD_DRIVER_M (LP_GPIO_PIN2_PAD_DRIVER_V << LP_GPIO_PIN2_PAD_DRIVER_S)
#define LP_GPIO_PIN2_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN2_PAD_DRIVER_S 2
/** LP_GPIO_PIN2_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN2_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN2_SYNC1_BYPASS_M (LP_GPIO_PIN2_SYNC1_BYPASS_V << LP_GPIO_PIN2_SYNC1_BYPASS_S)
#define LP_GPIO_PIN2_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN2_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN2_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN2_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN2_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
#define LP_GPIO_PIN2_INT_TYPE 0x00000007U
#define LP_GPIO_PIN2_INT_TYPE_M (LP_GPIO_PIN2_INT_TYPE_V << LP_GPIO_PIN2_INT_TYPE_S)
#define LP_GPIO_PIN2_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN2_INT_TYPE_S 7
/** LP_GPIO_PIN2_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
#define LP_GPIO_PIN2_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN2_WAKEUP_ENABLE_M (LP_GPIO_PIN2_WAKEUP_ENABLE_V << LP_GPIO_PIN2_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN2_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN2_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN3_REG register
* LP_GPIO3 configuration register
*/
#define LP_GPIO_PIN3_REG (DR_REG_LP_BASE + 0x3c)
/** LP_GPIO_PIN3_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN3_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN3_SYNC2_BYPASS_M (LP_GPIO_PIN3_SYNC2_BYPASS_V << LP_GPIO_PIN3_SYNC2_BYPASS_S)
#define LP_GPIO_PIN3_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN3_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN3_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
#define LP_GPIO_PIN3_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN3_PAD_DRIVER_M (LP_GPIO_PIN3_PAD_DRIVER_V << LP_GPIO_PIN3_PAD_DRIVER_S)
#define LP_GPIO_PIN3_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN3_PAD_DRIVER_S 2
/** LP_GPIO_PIN3_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN3_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN3_SYNC1_BYPASS_M (LP_GPIO_PIN3_SYNC1_BYPASS_V << LP_GPIO_PIN3_SYNC1_BYPASS_S)
#define LP_GPIO_PIN3_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN3_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN3_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN3_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN3_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
#define LP_GPIO_PIN3_INT_TYPE 0x00000007U
#define LP_GPIO_PIN3_INT_TYPE_M (LP_GPIO_PIN3_INT_TYPE_V << LP_GPIO_PIN3_INT_TYPE_S)
#define LP_GPIO_PIN3_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN3_INT_TYPE_S 7
/** LP_GPIO_PIN3_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
#define LP_GPIO_PIN3_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN3_WAKEUP_ENABLE_M (LP_GPIO_PIN3_WAKEUP_ENABLE_V << LP_GPIO_PIN3_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN3_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN3_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN4_REG register
* LP_GPIO4 configuration register
*/
#define LP_GPIO_PIN4_REG (DR_REG_LP_BASE + 0x40)
/** LP_GPIO_PIN4_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN4_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN4_SYNC2_BYPASS_M (LP_GPIO_PIN4_SYNC2_BYPASS_V << LP_GPIO_PIN4_SYNC2_BYPASS_S)
#define LP_GPIO_PIN4_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN4_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN4_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
#define LP_GPIO_PIN4_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN4_PAD_DRIVER_M (LP_GPIO_PIN4_PAD_DRIVER_V << LP_GPIO_PIN4_PAD_DRIVER_S)
#define LP_GPIO_PIN4_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN4_PAD_DRIVER_S 2
/** LP_GPIO_PIN4_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN4_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN4_SYNC1_BYPASS_M (LP_GPIO_PIN4_SYNC1_BYPASS_V << LP_GPIO_PIN4_SYNC1_BYPASS_S)
#define LP_GPIO_PIN4_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN4_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN4_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN4_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN4_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
#define LP_GPIO_PIN4_INT_TYPE 0x00000007U
#define LP_GPIO_PIN4_INT_TYPE_M (LP_GPIO_PIN4_INT_TYPE_V << LP_GPIO_PIN4_INT_TYPE_S)
#define LP_GPIO_PIN4_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN4_INT_TYPE_S 7
/** LP_GPIO_PIN4_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
#define LP_GPIO_PIN4_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN4_WAKEUP_ENABLE_M (LP_GPIO_PIN4_WAKEUP_ENABLE_V << LP_GPIO_PIN4_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN4_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN4_WAKEUP_ENABLE_S 10
/** LP_GPIO_PIN5_REG register
* LP_GPIO5 configuration register
*/
#define LP_GPIO_PIN5_REG (DR_REG_LP_BASE + 0x44)
/** LP_GPIO_PIN5_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN5_SYNC2_BYPASS 0x00000003U
#define LP_GPIO_PIN5_SYNC2_BYPASS_M (LP_GPIO_PIN5_SYNC2_BYPASS_V << LP_GPIO_PIN5_SYNC2_BYPASS_S)
#define LP_GPIO_PIN5_SYNC2_BYPASS_V 0x00000003U
#define LP_GPIO_PIN5_SYNC2_BYPASS_S 0
/** LP_GPIO_PIN5_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
#define LP_GPIO_PIN5_PAD_DRIVER (BIT(2))
#define LP_GPIO_PIN5_PAD_DRIVER_M (LP_GPIO_PIN5_PAD_DRIVER_V << LP_GPIO_PIN5_PAD_DRIVER_S)
#define LP_GPIO_PIN5_PAD_DRIVER_V 0x00000001U
#define LP_GPIO_PIN5_PAD_DRIVER_S 2
/** LP_GPIO_PIN5_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
#define LP_GPIO_PIN5_SYNC1_BYPASS 0x00000003U
#define LP_GPIO_PIN5_SYNC1_BYPASS_M (LP_GPIO_PIN5_SYNC1_BYPASS_V << LP_GPIO_PIN5_SYNC1_BYPASS_S)
#define LP_GPIO_PIN5_SYNC1_BYPASS_V 0x00000003U
#define LP_GPIO_PIN5_SYNC1_BYPASS_S 3
/** LP_GPIO_PIN5_EDGE_WAKEUP_CLR : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR (BIT(5))
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_M (LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V << LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S)
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_V 0x00000001U
#define LP_GPIO_PIN5_EDGE_WAKEUP_CLR_S 5
/** LP_GPIO_PIN5_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
#define LP_GPIO_PIN5_INT_TYPE 0x00000007U
#define LP_GPIO_PIN5_INT_TYPE_M (LP_GPIO_PIN5_INT_TYPE_V << LP_GPIO_PIN5_INT_TYPE_S)
#define LP_GPIO_PIN5_INT_TYPE_V 0x00000007U
#define LP_GPIO_PIN5_INT_TYPE_S 7
/** LP_GPIO_PIN5_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
#define LP_GPIO_PIN5_WAKEUP_ENABLE (BIT(10))
#define LP_GPIO_PIN5_WAKEUP_ENABLE_M (LP_GPIO_PIN5_WAKEUP_ENABLE_V << LP_GPIO_PIN5_WAKEUP_ENABLE_S)
#define LP_GPIO_PIN5_WAKEUP_ENABLE_V 0x00000001U
#define LP_GPIO_PIN5_WAKEUP_ENABLE_S 10
/** LP_GPIO_FUNC0_OUT_SEL_CFG_REG register
* Configuration register for LP_GPIO0 output
*/
#define LP_GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2b0)
/** LP_GPIO_FUNC0_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC0_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC0_OUT_INV_SEL_M (LP_GPIO_FUNC0_OUT_INV_SEL_V << LP_GPIO_FUNC0_OUT_INV_SEL_S)
#define LP_GPIO_FUNC0_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC0_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC0_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC0_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC0_OE_INV_SEL_M (LP_GPIO_FUNC0_OE_INV_SEL_V << LP_GPIO_FUNC0_OE_INV_SEL_S)
#define LP_GPIO_FUNC0_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC0_OE_INV_SEL_S 2
/** LP_GPIO_FUNC1_OUT_SEL_CFG_REG register
* Configuration register for LP_GPIO1 output
*/
#define LP_GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2b4)
/** LP_GPIO_FUNC1_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC1_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC1_OUT_INV_SEL_M (LP_GPIO_FUNC1_OUT_INV_SEL_V << LP_GPIO_FUNC1_OUT_INV_SEL_S)
#define LP_GPIO_FUNC1_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC1_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC1_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC1_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC1_OE_INV_SEL_M (LP_GPIO_FUNC1_OE_INV_SEL_V << LP_GPIO_FUNC1_OE_INV_SEL_S)
#define LP_GPIO_FUNC1_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC1_OE_INV_SEL_S 2
/** LP_GPIO_FUNC2_OUT_SEL_CFG_REG register
* Configuration register for LP_GPIO2 output
*/
#define LP_GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2b8)
/** LP_GPIO_FUNC2_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC2_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC2_OUT_INV_SEL_M (LP_GPIO_FUNC2_OUT_INV_SEL_V << LP_GPIO_FUNC2_OUT_INV_SEL_S)
#define LP_GPIO_FUNC2_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC2_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC2_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC2_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC2_OE_INV_SEL_M (LP_GPIO_FUNC2_OE_INV_SEL_V << LP_GPIO_FUNC2_OE_INV_SEL_S)
#define LP_GPIO_FUNC2_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC2_OE_INV_SEL_S 2
/** LP_GPIO_FUNC3_OUT_SEL_CFG_REG register
* Configuration register for LP_GPIO3 output
*/
#define LP_GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2bc)
/** LP_GPIO_FUNC3_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC3_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC3_OUT_INV_SEL_M (LP_GPIO_FUNC3_OUT_INV_SEL_V << LP_GPIO_FUNC3_OUT_INV_SEL_S)
#define LP_GPIO_FUNC3_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC3_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC3_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC3_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC3_OE_INV_SEL_M (LP_GPIO_FUNC3_OE_INV_SEL_V << LP_GPIO_FUNC3_OE_INV_SEL_S)
#define LP_GPIO_FUNC3_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC3_OE_INV_SEL_S 2
/** LP_GPIO_FUNC4_OUT_SEL_CFG_REG register
* Configuration register for LP_GPIO4 output
*/
#define LP_GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2c0)
/** LP_GPIO_FUNC4_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC4_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC4_OUT_INV_SEL_M (LP_GPIO_FUNC4_OUT_INV_SEL_V << LP_GPIO_FUNC4_OUT_INV_SEL_S)
#define LP_GPIO_FUNC4_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC4_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC4_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC4_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC4_OE_INV_SEL_M (LP_GPIO_FUNC4_OE_INV_SEL_V << LP_GPIO_FUNC4_OE_INV_SEL_S)
#define LP_GPIO_FUNC4_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC4_OE_INV_SEL_S 2
/** LP_GPIO_FUNC5_OUT_SEL_CFG_REG register
* Configuration register for LP_GPIO5 output
*/
#define LP_GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_LP_BASE + 0x2c4)
/** LP_GPIO_FUNC5_OUT_INV_SEL : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC5_OUT_INV_SEL (BIT(0))
#define LP_GPIO_FUNC5_OUT_INV_SEL_M (LP_GPIO_FUNC5_OUT_INV_SEL_V << LP_GPIO_FUNC5_OUT_INV_SEL_S)
#define LP_GPIO_FUNC5_OUT_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC5_OUT_INV_SEL_S 0
/** LP_GPIO_FUNC5_OE_INV_SEL : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
#define LP_GPIO_FUNC5_OE_INV_SEL (BIT(2))
#define LP_GPIO_FUNC5_OE_INV_SEL_M (LP_GPIO_FUNC5_OE_INV_SEL_V << LP_GPIO_FUNC5_OE_INV_SEL_S)
#define LP_GPIO_FUNC5_OE_INV_SEL_V 0x00000001U
#define LP_GPIO_FUNC5_OE_INV_SEL_S 2
/** LP_GPIO_CLOCK_GATE_REG register
* LP_GPIO clock gate register
*/
#define LP_GPIO_CLOCK_GATE_REG (DR_REG_LP_BASE + 0x3f8)
/** LP_GPIO_CLK_EN : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable clock gate.
* 0: Not enable
* 1: Enable, the clock is free running.
*/
#define LP_GPIO_CLK_EN (BIT(0))
#define LP_GPIO_CLK_EN_M (LP_GPIO_CLK_EN_V << LP_GPIO_CLK_EN_S)
#define LP_GPIO_CLK_EN_V 0x00000001U
#define LP_GPIO_CLK_EN_S 0
/** LP_GPIO_DATE_REG register
* LP_GPIO version register
*/
#define LP_GPIO_DATE_REG (DR_REG_LP_BASE + 0x3fc)
/** LP_GPIO_DATE : R/W; bitpos: [27:0]; default: 37769744;
* Version control register.
*/
#define LP_GPIO_DATE 0x0FFFFFFFU
#define LP_GPIO_DATE_M (LP_GPIO_DATE_V << LP_GPIO_DATE_S)
#define LP_GPIO_DATE_V 0x0FFFFFFFU
#define LP_GPIO_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_gpio_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of gpio_out register
* LP_GPIO output register
*/
typedef union {
struct {
/** gpio_out_data_orig : R/W/WTC; bitpos: [5:0]; default: 0;
* Configures the output value of LP_GPIO0 ~ 5 output in simple LP_GPIO output mode.
* 0: Low level
* 1: High level
* The value of bit0 ~ bit5 correspond to the output value of LP_GPIO0 ~ LP_GPIO5
* respectively. Bitxx ~ bitxx is invalid.
*/
uint32_t gpio_out_data_orig:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_out_reg_t;
/** Type of gpio_out_w1ts register
* LP_GPIO output set register
*/
typedef union {
struct {
/** gpio_out_w1ts : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the output register LP_GPIO_OUT_REG of LP_GPIO0 ~
* LP_GPIO5.
* 0: Not set
* 1: The corresponding bit in LP_GPIO_OUT_REG will be set to 1
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set LP_GPIO_OUT_REG.
*/
uint32_t gpio_out_w1ts:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_out_w1ts_reg_t;
/** Type of gpio_out_w1tc register
* LP_GPIO output clear register
*/
typedef union {
struct {
/** gpio_out_w1tc : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the output register LP_GPIO_OUT_REG of LP_GPIO0
* ~ LP_GPIO5 output.
* 0: Not clear
* 1: The corresponding bit in LP_GPIO_OUT_REG will be cleared.
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear LP_GPIO_OUT_REG.
*/
uint32_t gpio_out_w1tc:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_out_w1tc_reg_t;
/** Type of gpio_enable register
* LP_GPIO output enable register
*/
typedef union {
struct {
/** gpio_enable_data : R/W/WTC; bitpos: [5:0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO0 ~ LP_GPIO5.
* 0: Not enable
* 1: Enable
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
*/
uint32_t gpio_enable_data:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_enable_reg_t;
/** Type of gpio_enable_w1ts register
* LP_GPIO output enable set register
*/
typedef union {
struct {
/** gpio_enable_w1ts : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the output enable register LP_GPIO_ENABLE_REG of
* LP_GPIO0 ~ LP_GPIO5.
* 0: Not set
* 1: The corresponding bit in LP_GPIO_ENABLE_REG will be set to 1
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to set LP_GPIO_ENABLE_REG.
*/
uint32_t gpio_enable_w1ts:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_enable_w1ts_reg_t;
/** Type of gpio_enable_w1tc register
* LP_GPIO output enable clear register
*/
typedef union {
struct {
/** gpio_enable_w1tc : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the output enable register LP_GPIO_ENABLE_REG of
* LP_GPIO0 ~ LP_GPIO5.
* 0: Not clear
* 1: The corresponding bit in LP_GPIO_ENABLE_REG will be cleared
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Recommended operation: use this register to clear LP_GPIO_ENABLE_REG.
*/
uint32_t gpio_enable_w1tc:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_enable_w1tc_reg_t;
/** Type of gpio_in register
* LP_GPIO input register
*/
typedef union {
struct {
/** gpio_in_data_next : RO; bitpos: [5:0]; default: 0;
* Represents the input value of LP_GPIO0 ~ LP_GPIO5. Each bit represents a pin input
* value:
* 0: Low level
* 1: High level
* Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
*/
uint32_t gpio_in_data_next:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_in_reg_t;
/** Group: Interrupt Status Registers */
/** Type of gpio_status register
* LP_GPIO interrupt status register
*/
typedef union {
struct {
/** gpio_status_interrupt : R/W/WTC; bitpos: [5:0]; default: 0;
* The interrupt status of LP_GPIO0 ~ LP_GPIO5, can be configured by the software.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* - Each bit represents the status of its corresponding LP_GPIO:
*
* - 0: Represents the LP_GPIO does not generate the interrupt configured by
* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 0 by the software.
* - 1: Represents the LP_GPIO generates the interrupt configured by
* LP_GPIO_PIN$n_INT_TYPE, or this bit is configured to 1 by the software.
*
*/
uint32_t gpio_status_interrupt:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_reg_t;
/** Type of gpio_status_w1ts register
* LP_GPIO interrupt status set register
*/
typedef union {
struct {
/** gpio_status_w1ts : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to set the interrupt status register
* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_GPIO_STATUS_INTERRUPT will be set to 1. \item Recommended operation: use this
* register to set LP_GPIO_STATUS_INTERRUPT.
*/
uint32_t gpio_status_w1ts:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_w1ts_reg_t;
/** Type of gpio_status_w1tc register
* LP_GPIO interrupt status clear register
*/
typedef union {
struct {
/** gpio_status_w1tc : WT; bitpos: [5:0]; default: 0;
* Configures whether or not to clear the interrupt status register
* LP_GPIO_STATUS_INTERRUPT of LP_GPIO0 ~ LP_GPIO5.
*
* - Bit0 ~ bit5 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* - If the value 1 is written to a bit here, the corresponding bit in
* LP_GPIO_STATUS_INTERRUPT will be cleared. \item Recommended operation: use this
* register to clear LP_GPIO_STATUS_INTERRUPT.
*/
uint32_t gpio_status_w1tc:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_w1tc_reg_t;
/** Type of gpio_status_next register
* LP_GPIO interrupt source register
*/
typedef union {
struct {
/** gpio_status_interrupt_next : RO; bitpos: [5:0]; default: 0;
* Represents the interrupt source signal of LP_GPIO0 ~ LP_GPIO5.
* Bit0 ~ bit24 are corresponding to LP_GPIO0 ~ LP_GPIO5. Bitxx ~ bitxx is invalid.
* Each bit represents:
* 0: The LP_GPIO does not generate the interrupt configured by LP_GPIO_PIN$n_INT_TYPE.
* 1: The LP_GPIO generates an interrupt configured by LP_GPIO_PIN$n_INT_TYPE.
* The interrupt could be rising edge interrupt, falling edge interrupt, level
* sensitive interrupt and any edge interrupt.
*/
uint32_t gpio_status_interrupt_next:6;
uint32_t reserved_6:26;
};
uint32_t val;
} lp_gpio_status_next_reg_t;
/** Group: Pin Configuration Registers */
/** Type of gpio_pinn register
* LP_GPIOn configuration register
*/
typedef union {
struct {
/** gpio_pinn_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the second-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
uint32_t gpio_pinn_sync2_bypass:2;
/** gpio_pinn_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode.
* 0: Normal output
* 1: Open drain output
*/
uint32_t gpio_pinn_pad_driver:1;
/** gpio_pinn_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize LP_GPIO input data on either edge of LP IO
* MUX operating clock for the first-level synchronization.
* 0: Not synchronize
* 1: Synchronize on falling edge
* 2: Synchronize on rising edge
* 3: Synchronize on rising edge
*/
uint32_t gpio_pinn_sync1_bypass:2;
/** gpio_pinn_edge_wakeup_clr : WT; bitpos: [5]; default: 0;
* LP_GPIO wakeup clear register.
*/
uint32_t gpio_pinn_edge_wakeup_clr:1;
uint32_t reserved_6:1;
/** gpio_pinn_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures LP_GPIO interrupt type.
* 0: LP_GPIO interrupt disabled
* 1: Rising edge trigger
* 2: Falling edge trigger
* 3: Any edge trigger
* 4: Low level trigger
* 5: High level trigger
*/
uint32_t gpio_pinn_int_type:3;
/** gpio_pinn_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable LP_GPIO wake-up function.
* 0: Disable
* 1: Enable
* This function only wakes up the CPU from Light-sleep.
*/
uint32_t gpio_pinn_wakeup_enable:1;
uint32_t reserved_11:21;
};
uint32_t val;
} lp_gpio_pinn_reg_t;
/** Group: Output Configuration Registers */
/** Type of gpio_funcn_out_sel_cfg register
* Configuration register for LP_GPIOn output
*/
typedef union {
struct {
/** gpio_funcn_out_inv_sel : R/W; bitpos: [0]; default: 0;
* Configures whether or not to invert the output value.
* 0: Not invert
* 1: Invert
*/
uint32_t gpio_funcn_out_inv_sel:1;
uint32_t reserved_1:1;
/** gpio_funcn_oe_inv_sel : R/W; bitpos: [2]; default: 0;
* Configures whether or not to invert the output enable signal.
* 0: Not invert
* 1: Invert
*/
uint32_t gpio_funcn_oe_inv_sel:1;
uint32_t reserved_3:29;
};
uint32_t val;
} lp_gpio_funcn_out_sel_cfg_reg_t;
/** Group: Clock Gate Register */
/** Type of gpio_clock_gate register
* LP_GPIO clock gate register
*/
typedef union {
struct {
/** gpio_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether or not to enable clock gate.
* 0: Not enable
* 1: Enable, the clock is free running.
*/
uint32_t gpio_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_gpio_clock_gate_reg_t;
/** Group: Version Register */
/** Type of gpio_date register
* LP_GPIO version register
*/
typedef union {
struct {
/** gpio_date : R/W; bitpos: [27:0]; default: 37769744;
* Version control register.
*/
uint32_t gpio_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_gpio_date_reg_t;
typedef struct {
uint32_t reserved_000;
volatile lp_gpio_out_reg_t gpio_out;
volatile lp_gpio_out_w1ts_reg_t gpio_out_w1ts;
volatile lp_gpio_out_w1tc_reg_t gpio_out_w1tc;
volatile lp_gpio_enable_reg_t gpio_enable;
volatile lp_gpio_enable_w1ts_reg_t gpio_enable_w1ts;
volatile lp_gpio_enable_w1tc_reg_t gpio_enable_w1tc;
volatile lp_gpio_in_reg_t gpio_in;
volatile lp_gpio_status_reg_t gpio_status;
volatile lp_gpio_status_w1ts_reg_t gpio_status_w1ts;
volatile lp_gpio_status_w1tc_reg_t gpio_status_w1tc;
volatile lp_gpio_status_next_reg_t gpio_status_next;
volatile lp_gpio_pinn_reg_t gpio_pinn[6];
uint32_t reserved_048[154];
volatile lp_gpio_funcn_out_sel_cfg_reg_t gpio_funcn_out_sel_cfg[6];
uint32_t reserved_2c8[76];
volatile lp_gpio_clock_gate_reg_t gpio_clock_gate;
volatile lp_gpio_date_reg_t gpio_date;
} lp_gpio_dev_t;
extern lp_gpio_dev_t LP_GPIO;
#ifndef __cplusplus
_Static_assert(sizeof(lp_gpio_dev_t) == 0x400, "Invalid size of lp_gpio_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_iomux_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_IO_MUX_GPIO0_REG register
* LP IO MUX configuration register for LP_GPIO0
*/
#define LP_IO_MUX_GPIO0_REG (DR_REG_LP_BASE + 0x0)
/** LP_IO_MUX_GPIO0_MCU_OE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO0 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_MCU_OE (BIT(0))
#define LP_IO_MUX_GPIO0_MCU_OE_M (LP_IO_MUX_GPIO0_MCU_OE_V << LP_IO_MUX_GPIO0_MCU_OE_S)
#define LP_IO_MUX_GPIO0_MCU_OE_V 0x00000001U
#define LP_IO_MUX_GPIO0_MCU_OE_S 0
/** LP_IO_MUX_GPIO0_SLP_SEL : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIO0.
* 0: Not enter
* 1: Enter
*/
#define LP_IO_MUX_GPIO0_SLP_SEL (BIT(1))
#define LP_IO_MUX_GPIO0_SLP_SEL_M (LP_IO_MUX_GPIO0_SLP_SEL_V << LP_IO_MUX_GPIO0_SLP_SEL_S)
#define LP_IO_MUX_GPIO0_SLP_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO0_SLP_SEL_S 1
/** LP_IO_MUX_GPIO0_MCU_WPD : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIO0 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_MCU_WPD (BIT(2))
#define LP_IO_MUX_GPIO0_MCU_WPD_M (LP_IO_MUX_GPIO0_MCU_WPD_V << LP_IO_MUX_GPIO0_MCU_WPD_S)
#define LP_IO_MUX_GPIO0_MCU_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO0_MCU_WPD_S 2
/** LP_IO_MUX_GPIO0_MCU_WPU : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIO0 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_MCU_WPU (BIT(3))
#define LP_IO_MUX_GPIO0_MCU_WPU_M (LP_IO_MUX_GPIO0_MCU_WPU_V << LP_IO_MUX_GPIO0_MCU_WPU_S)
#define LP_IO_MUX_GPIO0_MCU_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO0_MCU_WPU_S 3
/** LP_IO_MUX_GPIO0_MCU_IE : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIO0 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_MCU_IE (BIT(4))
#define LP_IO_MUX_GPIO0_MCU_IE_M (LP_IO_MUX_GPIO0_MCU_IE_V << LP_IO_MUX_GPIO0_MCU_IE_S)
#define LP_IO_MUX_GPIO0_MCU_IE_V 0x00000001U
#define LP_IO_MUX_GPIO0_MCU_IE_S 4
/** LP_IO_MUX_GPIO0_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIO0 during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO0_MCU_DRV 0x00000003U
#define LP_IO_MUX_GPIO0_MCU_DRV_M (LP_IO_MUX_GPIO0_MCU_DRV_V << LP_IO_MUX_GPIO0_MCU_DRV_S)
#define LP_IO_MUX_GPIO0_MCU_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO0_MCU_DRV_S 5
/** LP_IO_MUX_GPIO0_FUN_WPD : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIO0.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_FUN_WPD (BIT(7))
#define LP_IO_MUX_GPIO0_FUN_WPD_M (LP_IO_MUX_GPIO0_FUN_WPD_V << LP_IO_MUX_GPIO0_FUN_WPD_S)
#define LP_IO_MUX_GPIO0_FUN_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO0_FUN_WPD_S 7
/** LP_IO_MUX_GPIO0_FUN_WPU : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIO0.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_FUN_WPU (BIT(8))
#define LP_IO_MUX_GPIO0_FUN_WPU_M (LP_IO_MUX_GPIO0_FUN_WPU_V << LP_IO_MUX_GPIO0_FUN_WPU_S)
#define LP_IO_MUX_GPIO0_FUN_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO0_FUN_WPU_S 8
/** LP_IO_MUX_GPIO0_FUN_IE : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIO0.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_FUN_IE (BIT(9))
#define LP_IO_MUX_GPIO0_FUN_IE_M (LP_IO_MUX_GPIO0_FUN_IE_V << LP_IO_MUX_GPIO0_FUN_IE_S)
#define LP_IO_MUX_GPIO0_FUN_IE_V 0x00000001U
#define LP_IO_MUX_GPIO0_FUN_IE_S 9
/** LP_IO_MUX_GPIO0_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIO0.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO0_FUN_DRV 0x00000003U
#define LP_IO_MUX_GPIO0_FUN_DRV_M (LP_IO_MUX_GPIO0_FUN_DRV_V << LP_IO_MUX_GPIO0_FUN_DRV_S)
#define LP_IO_MUX_GPIO0_FUN_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO0_FUN_DRV_S 10
/** LP_IO_MUX_GPIO0_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
#define LP_IO_MUX_GPIO0_MCU_SEL 0x00000007U
#define LP_IO_MUX_GPIO0_MCU_SEL_M (LP_IO_MUX_GPIO0_MCU_SEL_V << LP_IO_MUX_GPIO0_MCU_SEL_S)
#define LP_IO_MUX_GPIO0_MCU_SEL_V 0x00000007U
#define LP_IO_MUX_GPIO0_MCU_SEL_S 12
/** LP_IO_MUX_GPIO0_FILTER_EN : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_FILTER_EN (BIT(15))
#define LP_IO_MUX_GPIO0_FILTER_EN_M (LP_IO_MUX_GPIO0_FILTER_EN_V << LP_IO_MUX_GPIO0_FILTER_EN_S)
#define LP_IO_MUX_GPIO0_FILTER_EN_V 0x00000001U
#define LP_IO_MUX_GPIO0_FILTER_EN_S 15
/** LP_IO_MUX_GPIO0_HYS_EN : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIO0_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO0_HYS_EN (BIT(16))
#define LP_IO_MUX_GPIO0_HYS_EN_M (LP_IO_MUX_GPIO0_HYS_EN_V << LP_IO_MUX_GPIO0_HYS_EN_S)
#define LP_IO_MUX_GPIO0_HYS_EN_V 0x00000001U
#define LP_IO_MUX_GPIO0_HYS_EN_S 16
/** LP_IO_MUX_GPIO0_HYS_SEL : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIO0.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIO0_HYS_EN
*/
#define LP_IO_MUX_GPIO0_HYS_SEL (BIT(17))
#define LP_IO_MUX_GPIO0_HYS_SEL_M (LP_IO_MUX_GPIO0_HYS_SEL_V << LP_IO_MUX_GPIO0_HYS_SEL_S)
#define LP_IO_MUX_GPIO0_HYS_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO0_HYS_SEL_S 17
/** LP_IO_MUX_GPIO1_REG register
* LP IO MUX configuration register for LP_GPIO1
*/
#define LP_IO_MUX_GPIO1_REG (DR_REG_LP_BASE + 0x4)
/** LP_IO_MUX_GPIO1_MCU_OE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO1 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_MCU_OE (BIT(0))
#define LP_IO_MUX_GPIO1_MCU_OE_M (LP_IO_MUX_GPIO1_MCU_OE_V << LP_IO_MUX_GPIO1_MCU_OE_S)
#define LP_IO_MUX_GPIO1_MCU_OE_V 0x00000001U
#define LP_IO_MUX_GPIO1_MCU_OE_S 0
/** LP_IO_MUX_GPIO1_SLP_SEL : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIO1.
* 0: Not enter
* 1: Enter
*/
#define LP_IO_MUX_GPIO1_SLP_SEL (BIT(1))
#define LP_IO_MUX_GPIO1_SLP_SEL_M (LP_IO_MUX_GPIO1_SLP_SEL_V << LP_IO_MUX_GPIO1_SLP_SEL_S)
#define LP_IO_MUX_GPIO1_SLP_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO1_SLP_SEL_S 1
/** LP_IO_MUX_GPIO1_MCU_WPD : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIO1 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_MCU_WPD (BIT(2))
#define LP_IO_MUX_GPIO1_MCU_WPD_M (LP_IO_MUX_GPIO1_MCU_WPD_V << LP_IO_MUX_GPIO1_MCU_WPD_S)
#define LP_IO_MUX_GPIO1_MCU_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO1_MCU_WPD_S 2
/** LP_IO_MUX_GPIO1_MCU_WPU : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIO1 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_MCU_WPU (BIT(3))
#define LP_IO_MUX_GPIO1_MCU_WPU_M (LP_IO_MUX_GPIO1_MCU_WPU_V << LP_IO_MUX_GPIO1_MCU_WPU_S)
#define LP_IO_MUX_GPIO1_MCU_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO1_MCU_WPU_S 3
/** LP_IO_MUX_GPIO1_MCU_IE : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIO1 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_MCU_IE (BIT(4))
#define LP_IO_MUX_GPIO1_MCU_IE_M (LP_IO_MUX_GPIO1_MCU_IE_V << LP_IO_MUX_GPIO1_MCU_IE_S)
#define LP_IO_MUX_GPIO1_MCU_IE_V 0x00000001U
#define LP_IO_MUX_GPIO1_MCU_IE_S 4
/** LP_IO_MUX_GPIO1_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIO1 during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO1_MCU_DRV 0x00000003U
#define LP_IO_MUX_GPIO1_MCU_DRV_M (LP_IO_MUX_GPIO1_MCU_DRV_V << LP_IO_MUX_GPIO1_MCU_DRV_S)
#define LP_IO_MUX_GPIO1_MCU_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO1_MCU_DRV_S 5
/** LP_IO_MUX_GPIO1_FUN_WPD : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIO1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_FUN_WPD (BIT(7))
#define LP_IO_MUX_GPIO1_FUN_WPD_M (LP_IO_MUX_GPIO1_FUN_WPD_V << LP_IO_MUX_GPIO1_FUN_WPD_S)
#define LP_IO_MUX_GPIO1_FUN_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO1_FUN_WPD_S 7
/** LP_IO_MUX_GPIO1_FUN_WPU : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIO1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_FUN_WPU (BIT(8))
#define LP_IO_MUX_GPIO1_FUN_WPU_M (LP_IO_MUX_GPIO1_FUN_WPU_V << LP_IO_MUX_GPIO1_FUN_WPU_S)
#define LP_IO_MUX_GPIO1_FUN_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO1_FUN_WPU_S 8
/** LP_IO_MUX_GPIO1_FUN_IE : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIO1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_FUN_IE (BIT(9))
#define LP_IO_MUX_GPIO1_FUN_IE_M (LP_IO_MUX_GPIO1_FUN_IE_V << LP_IO_MUX_GPIO1_FUN_IE_S)
#define LP_IO_MUX_GPIO1_FUN_IE_V 0x00000001U
#define LP_IO_MUX_GPIO1_FUN_IE_S 9
/** LP_IO_MUX_GPIO1_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIO1.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO1_FUN_DRV 0x00000003U
#define LP_IO_MUX_GPIO1_FUN_DRV_M (LP_IO_MUX_GPIO1_FUN_DRV_V << LP_IO_MUX_GPIO1_FUN_DRV_S)
#define LP_IO_MUX_GPIO1_FUN_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO1_FUN_DRV_S 10
/** LP_IO_MUX_GPIO1_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
#define LP_IO_MUX_GPIO1_MCU_SEL 0x00000007U
#define LP_IO_MUX_GPIO1_MCU_SEL_M (LP_IO_MUX_GPIO1_MCU_SEL_V << LP_IO_MUX_GPIO1_MCU_SEL_S)
#define LP_IO_MUX_GPIO1_MCU_SEL_V 0x00000007U
#define LP_IO_MUX_GPIO1_MCU_SEL_S 12
/** LP_IO_MUX_GPIO1_FILTER_EN : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_FILTER_EN (BIT(15))
#define LP_IO_MUX_GPIO1_FILTER_EN_M (LP_IO_MUX_GPIO1_FILTER_EN_V << LP_IO_MUX_GPIO1_FILTER_EN_S)
#define LP_IO_MUX_GPIO1_FILTER_EN_V 0x00000001U
#define LP_IO_MUX_GPIO1_FILTER_EN_S 15
/** LP_IO_MUX_GPIO1_HYS_EN : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIO1_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO1_HYS_EN (BIT(16))
#define LP_IO_MUX_GPIO1_HYS_EN_M (LP_IO_MUX_GPIO1_HYS_EN_V << LP_IO_MUX_GPIO1_HYS_EN_S)
#define LP_IO_MUX_GPIO1_HYS_EN_V 0x00000001U
#define LP_IO_MUX_GPIO1_HYS_EN_S 16
/** LP_IO_MUX_GPIO1_HYS_SEL : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIO1.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIO1_HYS_EN
*/
#define LP_IO_MUX_GPIO1_HYS_SEL (BIT(17))
#define LP_IO_MUX_GPIO1_HYS_SEL_M (LP_IO_MUX_GPIO1_HYS_SEL_V << LP_IO_MUX_GPIO1_HYS_SEL_S)
#define LP_IO_MUX_GPIO1_HYS_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO1_HYS_SEL_S 17
/** LP_IO_MUX_GPIO2_REG register
* LP IO MUX configuration register for LP_GPIO2
*/
#define LP_IO_MUX_GPIO2_REG (DR_REG_LP_BASE + 0x8)
/** LP_IO_MUX_GPIO2_MCU_OE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO2 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_MCU_OE (BIT(0))
#define LP_IO_MUX_GPIO2_MCU_OE_M (LP_IO_MUX_GPIO2_MCU_OE_V << LP_IO_MUX_GPIO2_MCU_OE_S)
#define LP_IO_MUX_GPIO2_MCU_OE_V 0x00000001U
#define LP_IO_MUX_GPIO2_MCU_OE_S 0
/** LP_IO_MUX_GPIO2_SLP_SEL : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIO2.
* 0: Not enter
* 1: Enter
*/
#define LP_IO_MUX_GPIO2_SLP_SEL (BIT(1))
#define LP_IO_MUX_GPIO2_SLP_SEL_M (LP_IO_MUX_GPIO2_SLP_SEL_V << LP_IO_MUX_GPIO2_SLP_SEL_S)
#define LP_IO_MUX_GPIO2_SLP_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO2_SLP_SEL_S 1
/** LP_IO_MUX_GPIO2_MCU_WPD : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIO2 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_MCU_WPD (BIT(2))
#define LP_IO_MUX_GPIO2_MCU_WPD_M (LP_IO_MUX_GPIO2_MCU_WPD_V << LP_IO_MUX_GPIO2_MCU_WPD_S)
#define LP_IO_MUX_GPIO2_MCU_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO2_MCU_WPD_S 2
/** LP_IO_MUX_GPIO2_MCU_WPU : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIO2 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_MCU_WPU (BIT(3))
#define LP_IO_MUX_GPIO2_MCU_WPU_M (LP_IO_MUX_GPIO2_MCU_WPU_V << LP_IO_MUX_GPIO2_MCU_WPU_S)
#define LP_IO_MUX_GPIO2_MCU_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO2_MCU_WPU_S 3
/** LP_IO_MUX_GPIO2_MCU_IE : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIO2 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_MCU_IE (BIT(4))
#define LP_IO_MUX_GPIO2_MCU_IE_M (LP_IO_MUX_GPIO2_MCU_IE_V << LP_IO_MUX_GPIO2_MCU_IE_S)
#define LP_IO_MUX_GPIO2_MCU_IE_V 0x00000001U
#define LP_IO_MUX_GPIO2_MCU_IE_S 4
/** LP_IO_MUX_GPIO2_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIO2 during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO2_MCU_DRV 0x00000003U
#define LP_IO_MUX_GPIO2_MCU_DRV_M (LP_IO_MUX_GPIO2_MCU_DRV_V << LP_IO_MUX_GPIO2_MCU_DRV_S)
#define LP_IO_MUX_GPIO2_MCU_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO2_MCU_DRV_S 5
/** LP_IO_MUX_GPIO2_FUN_WPD : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIO2.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_FUN_WPD (BIT(7))
#define LP_IO_MUX_GPIO2_FUN_WPD_M (LP_IO_MUX_GPIO2_FUN_WPD_V << LP_IO_MUX_GPIO2_FUN_WPD_S)
#define LP_IO_MUX_GPIO2_FUN_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO2_FUN_WPD_S 7
/** LP_IO_MUX_GPIO2_FUN_WPU : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIO2.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_FUN_WPU (BIT(8))
#define LP_IO_MUX_GPIO2_FUN_WPU_M (LP_IO_MUX_GPIO2_FUN_WPU_V << LP_IO_MUX_GPIO2_FUN_WPU_S)
#define LP_IO_MUX_GPIO2_FUN_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO2_FUN_WPU_S 8
/** LP_IO_MUX_GPIO2_FUN_IE : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIO2.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_FUN_IE (BIT(9))
#define LP_IO_MUX_GPIO2_FUN_IE_M (LP_IO_MUX_GPIO2_FUN_IE_V << LP_IO_MUX_GPIO2_FUN_IE_S)
#define LP_IO_MUX_GPIO2_FUN_IE_V 0x00000001U
#define LP_IO_MUX_GPIO2_FUN_IE_S 9
/** LP_IO_MUX_GPIO2_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIO2.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO2_FUN_DRV 0x00000003U
#define LP_IO_MUX_GPIO2_FUN_DRV_M (LP_IO_MUX_GPIO2_FUN_DRV_V << LP_IO_MUX_GPIO2_FUN_DRV_S)
#define LP_IO_MUX_GPIO2_FUN_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO2_FUN_DRV_S 10
/** LP_IO_MUX_GPIO2_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
#define LP_IO_MUX_GPIO2_MCU_SEL 0x00000007U
#define LP_IO_MUX_GPIO2_MCU_SEL_M (LP_IO_MUX_GPIO2_MCU_SEL_V << LP_IO_MUX_GPIO2_MCU_SEL_S)
#define LP_IO_MUX_GPIO2_MCU_SEL_V 0x00000007U
#define LP_IO_MUX_GPIO2_MCU_SEL_S 12
/** LP_IO_MUX_GPIO2_FILTER_EN : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_FILTER_EN (BIT(15))
#define LP_IO_MUX_GPIO2_FILTER_EN_M (LP_IO_MUX_GPIO2_FILTER_EN_V << LP_IO_MUX_GPIO2_FILTER_EN_S)
#define LP_IO_MUX_GPIO2_FILTER_EN_V 0x00000001U
#define LP_IO_MUX_GPIO2_FILTER_EN_S 15
/** LP_IO_MUX_GPIO2_HYS_EN : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIO2_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO2_HYS_EN (BIT(16))
#define LP_IO_MUX_GPIO2_HYS_EN_M (LP_IO_MUX_GPIO2_HYS_EN_V << LP_IO_MUX_GPIO2_HYS_EN_S)
#define LP_IO_MUX_GPIO2_HYS_EN_V 0x00000001U
#define LP_IO_MUX_GPIO2_HYS_EN_S 16
/** LP_IO_MUX_GPIO2_HYS_SEL : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIO2.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIO2_HYS_EN
*/
#define LP_IO_MUX_GPIO2_HYS_SEL (BIT(17))
#define LP_IO_MUX_GPIO2_HYS_SEL_M (LP_IO_MUX_GPIO2_HYS_SEL_V << LP_IO_MUX_GPIO2_HYS_SEL_S)
#define LP_IO_MUX_GPIO2_HYS_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO2_HYS_SEL_S 17
/** LP_IO_MUX_GPIO3_REG register
* LP IO MUX configuration register for LP_GPIO3
*/
#define LP_IO_MUX_GPIO3_REG (DR_REG_LP_BASE + 0xc)
/** LP_IO_MUX_GPIO3_MCU_OE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO3 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_MCU_OE (BIT(0))
#define LP_IO_MUX_GPIO3_MCU_OE_M (LP_IO_MUX_GPIO3_MCU_OE_V << LP_IO_MUX_GPIO3_MCU_OE_S)
#define LP_IO_MUX_GPIO3_MCU_OE_V 0x00000001U
#define LP_IO_MUX_GPIO3_MCU_OE_S 0
/** LP_IO_MUX_GPIO3_SLP_SEL : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIO3.
* 0: Not enter
* 1: Enter
*/
#define LP_IO_MUX_GPIO3_SLP_SEL (BIT(1))
#define LP_IO_MUX_GPIO3_SLP_SEL_M (LP_IO_MUX_GPIO3_SLP_SEL_V << LP_IO_MUX_GPIO3_SLP_SEL_S)
#define LP_IO_MUX_GPIO3_SLP_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO3_SLP_SEL_S 1
/** LP_IO_MUX_GPIO3_MCU_WPD : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIO3 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_MCU_WPD (BIT(2))
#define LP_IO_MUX_GPIO3_MCU_WPD_M (LP_IO_MUX_GPIO3_MCU_WPD_V << LP_IO_MUX_GPIO3_MCU_WPD_S)
#define LP_IO_MUX_GPIO3_MCU_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO3_MCU_WPD_S 2
/** LP_IO_MUX_GPIO3_MCU_WPU : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIO3 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_MCU_WPU (BIT(3))
#define LP_IO_MUX_GPIO3_MCU_WPU_M (LP_IO_MUX_GPIO3_MCU_WPU_V << LP_IO_MUX_GPIO3_MCU_WPU_S)
#define LP_IO_MUX_GPIO3_MCU_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO3_MCU_WPU_S 3
/** LP_IO_MUX_GPIO3_MCU_IE : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIO3 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_MCU_IE (BIT(4))
#define LP_IO_MUX_GPIO3_MCU_IE_M (LP_IO_MUX_GPIO3_MCU_IE_V << LP_IO_MUX_GPIO3_MCU_IE_S)
#define LP_IO_MUX_GPIO3_MCU_IE_V 0x00000001U
#define LP_IO_MUX_GPIO3_MCU_IE_S 4
/** LP_IO_MUX_GPIO3_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIO3 during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO3_MCU_DRV 0x00000003U
#define LP_IO_MUX_GPIO3_MCU_DRV_M (LP_IO_MUX_GPIO3_MCU_DRV_V << LP_IO_MUX_GPIO3_MCU_DRV_S)
#define LP_IO_MUX_GPIO3_MCU_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO3_MCU_DRV_S 5
/** LP_IO_MUX_GPIO3_FUN_WPD : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIO3.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_FUN_WPD (BIT(7))
#define LP_IO_MUX_GPIO3_FUN_WPD_M (LP_IO_MUX_GPIO3_FUN_WPD_V << LP_IO_MUX_GPIO3_FUN_WPD_S)
#define LP_IO_MUX_GPIO3_FUN_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO3_FUN_WPD_S 7
/** LP_IO_MUX_GPIO3_FUN_WPU : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIO3.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_FUN_WPU (BIT(8))
#define LP_IO_MUX_GPIO3_FUN_WPU_M (LP_IO_MUX_GPIO3_FUN_WPU_V << LP_IO_MUX_GPIO3_FUN_WPU_S)
#define LP_IO_MUX_GPIO3_FUN_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO3_FUN_WPU_S 8
/** LP_IO_MUX_GPIO3_FUN_IE : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIO3.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_FUN_IE (BIT(9))
#define LP_IO_MUX_GPIO3_FUN_IE_M (LP_IO_MUX_GPIO3_FUN_IE_V << LP_IO_MUX_GPIO3_FUN_IE_S)
#define LP_IO_MUX_GPIO3_FUN_IE_V 0x00000001U
#define LP_IO_MUX_GPIO3_FUN_IE_S 9
/** LP_IO_MUX_GPIO3_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIO3.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO3_FUN_DRV 0x00000003U
#define LP_IO_MUX_GPIO3_FUN_DRV_M (LP_IO_MUX_GPIO3_FUN_DRV_V << LP_IO_MUX_GPIO3_FUN_DRV_S)
#define LP_IO_MUX_GPIO3_FUN_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO3_FUN_DRV_S 10
/** LP_IO_MUX_GPIO3_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
#define LP_IO_MUX_GPIO3_MCU_SEL 0x00000007U
#define LP_IO_MUX_GPIO3_MCU_SEL_M (LP_IO_MUX_GPIO3_MCU_SEL_V << LP_IO_MUX_GPIO3_MCU_SEL_S)
#define LP_IO_MUX_GPIO3_MCU_SEL_V 0x00000007U
#define LP_IO_MUX_GPIO3_MCU_SEL_S 12
/** LP_IO_MUX_GPIO3_FILTER_EN : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_FILTER_EN (BIT(15))
#define LP_IO_MUX_GPIO3_FILTER_EN_M (LP_IO_MUX_GPIO3_FILTER_EN_V << LP_IO_MUX_GPIO3_FILTER_EN_S)
#define LP_IO_MUX_GPIO3_FILTER_EN_V 0x00000001U
#define LP_IO_MUX_GPIO3_FILTER_EN_S 15
/** LP_IO_MUX_GPIO3_HYS_EN : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIO3_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO3_HYS_EN (BIT(16))
#define LP_IO_MUX_GPIO3_HYS_EN_M (LP_IO_MUX_GPIO3_HYS_EN_V << LP_IO_MUX_GPIO3_HYS_EN_S)
#define LP_IO_MUX_GPIO3_HYS_EN_V 0x00000001U
#define LP_IO_MUX_GPIO3_HYS_EN_S 16
/** LP_IO_MUX_GPIO3_HYS_SEL : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIO3.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIO3_HYS_EN
*/
#define LP_IO_MUX_GPIO3_HYS_SEL (BIT(17))
#define LP_IO_MUX_GPIO3_HYS_SEL_M (LP_IO_MUX_GPIO3_HYS_SEL_V << LP_IO_MUX_GPIO3_HYS_SEL_S)
#define LP_IO_MUX_GPIO3_HYS_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO3_HYS_SEL_S 17
/** LP_IO_MUX_GPIO4_REG register
* LP IO MUX configuration register for LP_GPIO4
*/
#define LP_IO_MUX_GPIO4_REG (DR_REG_LP_BASE + 0x10)
/** LP_IO_MUX_GPIO4_MCU_OE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO4 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_MCU_OE (BIT(0))
#define LP_IO_MUX_GPIO4_MCU_OE_M (LP_IO_MUX_GPIO4_MCU_OE_V << LP_IO_MUX_GPIO4_MCU_OE_S)
#define LP_IO_MUX_GPIO4_MCU_OE_V 0x00000001U
#define LP_IO_MUX_GPIO4_MCU_OE_S 0
/** LP_IO_MUX_GPIO4_SLP_SEL : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIO4.
* 0: Not enter
* 1: Enter
*/
#define LP_IO_MUX_GPIO4_SLP_SEL (BIT(1))
#define LP_IO_MUX_GPIO4_SLP_SEL_M (LP_IO_MUX_GPIO4_SLP_SEL_V << LP_IO_MUX_GPIO4_SLP_SEL_S)
#define LP_IO_MUX_GPIO4_SLP_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO4_SLP_SEL_S 1
/** LP_IO_MUX_GPIO4_MCU_WPD : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIO4 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_MCU_WPD (BIT(2))
#define LP_IO_MUX_GPIO4_MCU_WPD_M (LP_IO_MUX_GPIO4_MCU_WPD_V << LP_IO_MUX_GPIO4_MCU_WPD_S)
#define LP_IO_MUX_GPIO4_MCU_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO4_MCU_WPD_S 2
/** LP_IO_MUX_GPIO4_MCU_WPU : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIO4 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_MCU_WPU (BIT(3))
#define LP_IO_MUX_GPIO4_MCU_WPU_M (LP_IO_MUX_GPIO4_MCU_WPU_V << LP_IO_MUX_GPIO4_MCU_WPU_S)
#define LP_IO_MUX_GPIO4_MCU_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO4_MCU_WPU_S 3
/** LP_IO_MUX_GPIO4_MCU_IE : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIO4 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_MCU_IE (BIT(4))
#define LP_IO_MUX_GPIO4_MCU_IE_M (LP_IO_MUX_GPIO4_MCU_IE_V << LP_IO_MUX_GPIO4_MCU_IE_S)
#define LP_IO_MUX_GPIO4_MCU_IE_V 0x00000001U
#define LP_IO_MUX_GPIO4_MCU_IE_S 4
/** LP_IO_MUX_GPIO4_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIO4 during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO4_MCU_DRV 0x00000003U
#define LP_IO_MUX_GPIO4_MCU_DRV_M (LP_IO_MUX_GPIO4_MCU_DRV_V << LP_IO_MUX_GPIO4_MCU_DRV_S)
#define LP_IO_MUX_GPIO4_MCU_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO4_MCU_DRV_S 5
/** LP_IO_MUX_GPIO4_FUN_WPD : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIO4.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_FUN_WPD (BIT(7))
#define LP_IO_MUX_GPIO4_FUN_WPD_M (LP_IO_MUX_GPIO4_FUN_WPD_V << LP_IO_MUX_GPIO4_FUN_WPD_S)
#define LP_IO_MUX_GPIO4_FUN_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO4_FUN_WPD_S 7
/** LP_IO_MUX_GPIO4_FUN_WPU : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIO4.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_FUN_WPU (BIT(8))
#define LP_IO_MUX_GPIO4_FUN_WPU_M (LP_IO_MUX_GPIO4_FUN_WPU_V << LP_IO_MUX_GPIO4_FUN_WPU_S)
#define LP_IO_MUX_GPIO4_FUN_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO4_FUN_WPU_S 8
/** LP_IO_MUX_GPIO4_FUN_IE : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIO4.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_FUN_IE (BIT(9))
#define LP_IO_MUX_GPIO4_FUN_IE_M (LP_IO_MUX_GPIO4_FUN_IE_V << LP_IO_MUX_GPIO4_FUN_IE_S)
#define LP_IO_MUX_GPIO4_FUN_IE_V 0x00000001U
#define LP_IO_MUX_GPIO4_FUN_IE_S 9
/** LP_IO_MUX_GPIO4_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIO4.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO4_FUN_DRV 0x00000003U
#define LP_IO_MUX_GPIO4_FUN_DRV_M (LP_IO_MUX_GPIO4_FUN_DRV_V << LP_IO_MUX_GPIO4_FUN_DRV_S)
#define LP_IO_MUX_GPIO4_FUN_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO4_FUN_DRV_S 10
/** LP_IO_MUX_GPIO4_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
#define LP_IO_MUX_GPIO4_MCU_SEL 0x00000007U
#define LP_IO_MUX_GPIO4_MCU_SEL_M (LP_IO_MUX_GPIO4_MCU_SEL_V << LP_IO_MUX_GPIO4_MCU_SEL_S)
#define LP_IO_MUX_GPIO4_MCU_SEL_V 0x00000007U
#define LP_IO_MUX_GPIO4_MCU_SEL_S 12
/** LP_IO_MUX_GPIO4_FILTER_EN : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_FILTER_EN (BIT(15))
#define LP_IO_MUX_GPIO4_FILTER_EN_M (LP_IO_MUX_GPIO4_FILTER_EN_V << LP_IO_MUX_GPIO4_FILTER_EN_S)
#define LP_IO_MUX_GPIO4_FILTER_EN_V 0x00000001U
#define LP_IO_MUX_GPIO4_FILTER_EN_S 15
/** LP_IO_MUX_GPIO4_HYS_EN : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIO4_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO4_HYS_EN (BIT(16))
#define LP_IO_MUX_GPIO4_HYS_EN_M (LP_IO_MUX_GPIO4_HYS_EN_V << LP_IO_MUX_GPIO4_HYS_EN_S)
#define LP_IO_MUX_GPIO4_HYS_EN_V 0x00000001U
#define LP_IO_MUX_GPIO4_HYS_EN_S 16
/** LP_IO_MUX_GPIO4_HYS_SEL : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIO4.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIO4_HYS_EN
*/
#define LP_IO_MUX_GPIO4_HYS_SEL (BIT(17))
#define LP_IO_MUX_GPIO4_HYS_SEL_M (LP_IO_MUX_GPIO4_HYS_SEL_V << LP_IO_MUX_GPIO4_HYS_SEL_S)
#define LP_IO_MUX_GPIO4_HYS_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO4_HYS_SEL_S 17
/** LP_IO_MUX_GPIO5_REG register
* LP IO MUX configuration register for LP_GPIO5
*/
#define LP_IO_MUX_GPIO5_REG (DR_REG_LP_BASE + 0x14)
/** LP_IO_MUX_GPIO5_MCU_OE : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIO5 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_MCU_OE (BIT(0))
#define LP_IO_MUX_GPIO5_MCU_OE_M (LP_IO_MUX_GPIO5_MCU_OE_V << LP_IO_MUX_GPIO5_MCU_OE_S)
#define LP_IO_MUX_GPIO5_MCU_OE_V 0x00000001U
#define LP_IO_MUX_GPIO5_MCU_OE_S 0
/** LP_IO_MUX_GPIO5_SLP_SEL : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIO5.
* 0: Not enter
* 1: Enter
*/
#define LP_IO_MUX_GPIO5_SLP_SEL (BIT(1))
#define LP_IO_MUX_GPIO5_SLP_SEL_M (LP_IO_MUX_GPIO5_SLP_SEL_V << LP_IO_MUX_GPIO5_SLP_SEL_S)
#define LP_IO_MUX_GPIO5_SLP_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO5_SLP_SEL_S 1
/** LP_IO_MUX_GPIO5_MCU_WPD : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIO5 in sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_MCU_WPD (BIT(2))
#define LP_IO_MUX_GPIO5_MCU_WPD_M (LP_IO_MUX_GPIO5_MCU_WPD_V << LP_IO_MUX_GPIO5_MCU_WPD_S)
#define LP_IO_MUX_GPIO5_MCU_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO5_MCU_WPD_S 2
/** LP_IO_MUX_GPIO5_MCU_WPU : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIO5 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_MCU_WPU (BIT(3))
#define LP_IO_MUX_GPIO5_MCU_WPU_M (LP_IO_MUX_GPIO5_MCU_WPU_V << LP_IO_MUX_GPIO5_MCU_WPU_S)
#define LP_IO_MUX_GPIO5_MCU_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO5_MCU_WPU_S 3
/** LP_IO_MUX_GPIO5_MCU_IE : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIO5 during sleep mode.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_MCU_IE (BIT(4))
#define LP_IO_MUX_GPIO5_MCU_IE_M (LP_IO_MUX_GPIO5_MCU_IE_V << LP_IO_MUX_GPIO5_MCU_IE_S)
#define LP_IO_MUX_GPIO5_MCU_IE_V 0x00000001U
#define LP_IO_MUX_GPIO5_MCU_IE_S 4
/** LP_IO_MUX_GPIO5_MCU_DRV : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIO5 during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO5_MCU_DRV 0x00000003U
#define LP_IO_MUX_GPIO5_MCU_DRV_M (LP_IO_MUX_GPIO5_MCU_DRV_V << LP_IO_MUX_GPIO5_MCU_DRV_S)
#define LP_IO_MUX_GPIO5_MCU_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO5_MCU_DRV_S 5
/** LP_IO_MUX_GPIO5_FUN_WPD : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIO5.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_FUN_WPD (BIT(7))
#define LP_IO_MUX_GPIO5_FUN_WPD_M (LP_IO_MUX_GPIO5_FUN_WPD_V << LP_IO_MUX_GPIO5_FUN_WPD_S)
#define LP_IO_MUX_GPIO5_FUN_WPD_V 0x00000001U
#define LP_IO_MUX_GPIO5_FUN_WPD_S 7
/** LP_IO_MUX_GPIO5_FUN_WPU : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIO5.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_FUN_WPU (BIT(8))
#define LP_IO_MUX_GPIO5_FUN_WPU_M (LP_IO_MUX_GPIO5_FUN_WPU_V << LP_IO_MUX_GPIO5_FUN_WPU_S)
#define LP_IO_MUX_GPIO5_FUN_WPU_V 0x00000001U
#define LP_IO_MUX_GPIO5_FUN_WPU_S 8
/** LP_IO_MUX_GPIO5_FUN_IE : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIO5.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_FUN_IE (BIT(9))
#define LP_IO_MUX_GPIO5_FUN_IE_M (LP_IO_MUX_GPIO5_FUN_IE_V << LP_IO_MUX_GPIO5_FUN_IE_S)
#define LP_IO_MUX_GPIO5_FUN_IE_V 0x00000001U
#define LP_IO_MUX_GPIO5_FUN_IE_S 9
/** LP_IO_MUX_GPIO5_FUN_DRV : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIO5.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
#define LP_IO_MUX_GPIO5_FUN_DRV 0x00000003U
#define LP_IO_MUX_GPIO5_FUN_DRV_M (LP_IO_MUX_GPIO5_FUN_DRV_V << LP_IO_MUX_GPIO5_FUN_DRV_S)
#define LP_IO_MUX_GPIO5_FUN_DRV_V 0x00000003U
#define LP_IO_MUX_GPIO5_FUN_DRV_S 10
/** LP_IO_MUX_GPIO5_MCU_SEL : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
#define LP_IO_MUX_GPIO5_MCU_SEL 0x00000007U
#define LP_IO_MUX_GPIO5_MCU_SEL_M (LP_IO_MUX_GPIO5_MCU_SEL_V << LP_IO_MUX_GPIO5_MCU_SEL_S)
#define LP_IO_MUX_GPIO5_MCU_SEL_V 0x00000007U
#define LP_IO_MUX_GPIO5_MCU_SEL_S 12
/** LP_IO_MUX_GPIO5_FILTER_EN : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_FILTER_EN (BIT(15))
#define LP_IO_MUX_GPIO5_FILTER_EN_M (LP_IO_MUX_GPIO5_FILTER_EN_V << LP_IO_MUX_GPIO5_FILTER_EN_S)
#define LP_IO_MUX_GPIO5_FILTER_EN_V 0x00000001U
#define LP_IO_MUX_GPIO5_FILTER_EN_S 15
/** LP_IO_MUX_GPIO5_HYS_EN : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIO5_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
#define LP_IO_MUX_GPIO5_HYS_EN (BIT(16))
#define LP_IO_MUX_GPIO5_HYS_EN_M (LP_IO_MUX_GPIO5_HYS_EN_V << LP_IO_MUX_GPIO5_HYS_EN_S)
#define LP_IO_MUX_GPIO5_HYS_EN_V 0x00000001U
#define LP_IO_MUX_GPIO5_HYS_EN_S 16
/** LP_IO_MUX_GPIO5_HYS_SEL : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIO5.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIO5_HYS_EN
*/
#define LP_IO_MUX_GPIO5_HYS_SEL (BIT(17))
#define LP_IO_MUX_GPIO5_HYS_SEL_M (LP_IO_MUX_GPIO5_HYS_SEL_V << LP_IO_MUX_GPIO5_HYS_SEL_S)
#define LP_IO_MUX_GPIO5_HYS_SEL_V 0x00000001U
#define LP_IO_MUX_GPIO5_HYS_SEL_S 17
/** LP_IO_MUX_DATE_REG register
* Version control register
*/
#define LP_IO_MUX_DATE_REG (DR_REG_LP_BASE + 0x1fc)
/** LP_IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 37769744;
* Version control register
*/
#define LP_IO_MUX_REG_DATE 0x0FFFFFFFU
#define LP_IO_MUX_REG_DATE_M (LP_IO_MUX_REG_DATE_V << LP_IO_MUX_REG_DATE_S)
#define LP_IO_MUX_REG_DATE_V 0x0FFFFFFFU
#define LP_IO_MUX_REG_DATE_S 0
#ifdef __cplusplus
}
#endif

145
components/soc/esp32h4/register/soc/lp_iomux_struct.h Normal file
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@@ -0,0 +1,145 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of io_mux_gpion register
* LP IO MUX configuration register for LP_GPIOn
*/
typedef union {
struct {
/** io_mux_gpion_mcu_oe : R/W; bitpos: [0]; default: 0;
* Configures whether or not to enable the output of LP_GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_oe:1;
/** io_mux_gpion_slp_sel : R/W; bitpos: [1]; default: 0;
* Configures whether or not to enter sleep mode for LP_GPIOn.
* 0: Not enter
* 1: Enter
*/
uint32_t io_mux_gpion_slp_sel:1;
/** io_mux_gpion_mcu_wpd : R/W; bitpos: [2]; default: 0;
* Configure whether or not to enable pull-down resistor of LP_GPIOn in sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_wpd:1;
/** io_mux_gpion_mcu_wpu : R/W; bitpos: [3]; default: 0;
* Configures whether or not to enable pull-up resistor of LP_GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_wpu:1;
/** io_mux_gpion_mcu_ie : R/W; bitpos: [4]; default: 0;
* Configures whether or not to enable the input of LP_GPIOn during sleep mode.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_mcu_ie:1;
/** io_mux_gpion_mcu_drv : R/W; bitpos: [6:5]; default: 0;
* Configures the drive strength of LP_GPIOn during sleep mode.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t io_mux_gpion_mcu_drv:2;
/** io_mux_gpion_fun_wpd : R/W; bitpos: [7]; default: 0;
* Configures whether or not to enable pull-down resistor of LP_GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_fun_wpd:1;
/** io_mux_gpion_fun_wpu : R/W; bitpos: [8]; default: 0;
* Configures whether or not enable pull-up resistor of LP_GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_fun_wpu:1;
/** io_mux_gpion_fun_ie : R/W; bitpos: [9]; default: 0;
* Configures whether or not to enable input of LP_GPIOn.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_fun_ie:1;
/** io_mux_gpion_fun_drv : R/W; bitpos: [11:10]; default: 2;
* Configures the drive strength of LP_GPIOn.
* 0: ~5 mA
* 1: ~10 mA
* 2: ~20 mA
* 3: ~40 mA
*/
uint32_t io_mux_gpion_fun_drv:2;
/** io_mux_gpion_mcu_sel : R/W; bitpos: [14:12]; default: 1;
* Configures to select LP IO MUX function for this signal.
* 0: Select Function 0
* 1: Select Function 1
* ......
*/
uint32_t io_mux_gpion_mcu_sel:3;
/** io_mux_gpion_filter_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable filter for pin input signals.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_filter_en:1;
/** io_mux_gpion_hys_en : R/W; bitpos: [16]; default: 0;
* Configures whether or not to enable the hysteresis function of the pin when
* LP_IO_MUX_GPIOn_HYS_SEL is set to 1.
* 0: Disable
* 1: Enable
*/
uint32_t io_mux_gpion_hys_en:1;
/** io_mux_gpion_hys_sel : R/W; bitpos: [17]; default: 0;
* Configures to choose the signal for enabling the hysteresis function for LP_GPIOn.
* 0: Choose the output enable signal of eFuse
* 1: Choose the output enable signal of LP_IO_MUX_GPIOn_HYS_EN
*/
uint32_t io_mux_gpion_hys_sel:1;
uint32_t reserved_18:14;
};
uint32_t val;
} lp_io_mux_gpion_reg_t;
/** Group: Version Register */
/** Type of io_mux_date register
* Version control register
*/
typedef union {
struct {
/** io_mux_reg_date : R/W; bitpos: [27:0]; default: 37769744;
* Version control register
*/
uint32_t io_mux_reg_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_io_mux_date_reg_t;
typedef struct {
volatile lp_io_mux_gpion_reg_t io_mux_gpion[6];
uint32_t reserved_018[121];
volatile lp_io_mux_date_reg_t io_mux_date;
} lp_iomux_dev_t;
extern lp_iomux_dev_t LP_IO_MUX;
#ifndef __cplusplus
_Static_assert(sizeof(lp_iomux_dev_t) == 0x200, "Invalid size of lp_iomux_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LPPERI_CLK_EN_REG register
* configure peri in lp system clk enable
*/
#define LPPERI_CLK_EN_REG (DR_REG_LPPERI_BASE + 0x0)
/** LPPERI_RNG_APB_CK_EN : R/W; bitpos: [23]; default: 1;
* lp rng apb clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_RNG_APB_CK_EN (BIT(23))
#define LPPERI_RNG_APB_CK_EN_M (LPPERI_RNG_APB_CK_EN_V << LPPERI_RNG_APB_CK_EN_S)
#define LPPERI_RNG_APB_CK_EN_V 0x00000001U
#define LPPERI_RNG_APB_CK_EN_S 23
/** LPPERI_RNG_CK_EN : R/W; bitpos: [24]; default: 1;
* lp rng clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_RNG_CK_EN (BIT(24))
#define LPPERI_RNG_CK_EN_M (LPPERI_RNG_CK_EN_V << LPPERI_RNG_CK_EN_S)
#define LPPERI_RNG_CK_EN_V 0x00000001U
#define LPPERI_RNG_CK_EN_S 24
/** LPPERI_OTP_DBG_CK_EN : R/W; bitpos: [25]; default: 1;
* lp optdebug clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_OTP_DBG_CK_EN (BIT(25))
#define LPPERI_OTP_DBG_CK_EN_M (LPPERI_OTP_DBG_CK_EN_V << LPPERI_OTP_DBG_CK_EN_S)
#define LPPERI_OTP_DBG_CK_EN_V 0x00000001U
#define LPPERI_OTP_DBG_CK_EN_S 25
/** LPPERI_LP_TOUCH_CK_EN : R/W; bitpos: [26]; default: 1;
* lp touch clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_LP_TOUCH_CK_EN (BIT(26))
#define LPPERI_LP_TOUCH_CK_EN_M (LPPERI_LP_TOUCH_CK_EN_V << LPPERI_LP_TOUCH_CK_EN_S)
#define LPPERI_LP_TOUCH_CK_EN_V 0x00000001U
#define LPPERI_LP_TOUCH_CK_EN_S 26
/** LPPERI_LP_IO_CK_EN : R/W; bitpos: [27]; default: 1;
* lp io clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_LP_IO_CK_EN (BIT(27))
#define LPPERI_LP_IO_CK_EN_M (LPPERI_LP_IO_CK_EN_V << LPPERI_LP_IO_CK_EN_S)
#define LPPERI_LP_IO_CK_EN_V 0x00000001U
#define LPPERI_LP_IO_CK_EN_S 27
/** LPPERI_EFUSE_CK_EN : R/W; bitpos: [30]; default: 1;
* efuse core clk enable
* 1: enable clock
* 0: disable clock
*/
#define LPPERI_EFUSE_CK_EN (BIT(30))
#define LPPERI_EFUSE_CK_EN_M (LPPERI_EFUSE_CK_EN_V << LPPERI_EFUSE_CK_EN_S)
#define LPPERI_EFUSE_CK_EN_V 0x00000001U
#define LPPERI_EFUSE_CK_EN_S 30
/** LPPERI_RESET_EN_REG register
* configure peri in lp system reset enable
*/
#define LPPERI_RESET_EN_REG (DR_REG_LPPERI_BASE + 0x4)
/** LPPERI_BUS_RESET_EN : WT; bitpos: [23]; default: 0;
* lp bus reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_BUS_RESET_EN (BIT(23))
#define LPPERI_BUS_RESET_EN_M (LPPERI_BUS_RESET_EN_V << LPPERI_BUS_RESET_EN_S)
#define LPPERI_BUS_RESET_EN_V 0x00000001U
#define LPPERI_BUS_RESET_EN_S 23
/** LPPERI_LP_RNG_APB_RESET_EN : R/W; bitpos: [24]; default: 0;
* lp rng apb reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_RNG_APB_RESET_EN (BIT(24))
#define LPPERI_LP_RNG_APB_RESET_EN_M (LPPERI_LP_RNG_APB_RESET_EN_V << LPPERI_LP_RNG_APB_RESET_EN_S)
#define LPPERI_LP_RNG_APB_RESET_EN_V 0x00000001U
#define LPPERI_LP_RNG_APB_RESET_EN_S 24
/** LPPERI_OTP_DBG_RESET_EN : R/W; bitpos: [25]; default: 0;
* lp optdebug reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_OTP_DBG_RESET_EN (BIT(25))
#define LPPERI_OTP_DBG_RESET_EN_M (LPPERI_OTP_DBG_RESET_EN_V << LPPERI_OTP_DBG_RESET_EN_S)
#define LPPERI_OTP_DBG_RESET_EN_V 0x00000001U
#define LPPERI_OTP_DBG_RESET_EN_S 25
/** LPPERI_LP_TOUCH_RESET_EN : R/W; bitpos: [26]; default: 0;
* lp touch reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_TOUCH_RESET_EN (BIT(26))
#define LPPERI_LP_TOUCH_RESET_EN_M (LPPERI_LP_TOUCH_RESET_EN_V << LPPERI_LP_TOUCH_RESET_EN_S)
#define LPPERI_LP_TOUCH_RESET_EN_V 0x00000001U
#define LPPERI_LP_TOUCH_RESET_EN_S 26
/** LPPERI_LP_IO_RESET_EN : R/W; bitpos: [27]; default: 0;
* lp io reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_LP_IO_RESET_EN (BIT(27))
#define LPPERI_LP_IO_RESET_EN_M (LPPERI_LP_IO_RESET_EN_V << LPPERI_LP_IO_RESET_EN_S)
#define LPPERI_LP_IO_RESET_EN_V 0x00000001U
#define LPPERI_LP_IO_RESET_EN_S 27
/** LPPERI_EFUSE_RESET_EN : R/W; bitpos: [30]; default: 0;
* efuse core reset enable
* 1: enable reset
* 0: disable reset
*/
#define LPPERI_EFUSE_RESET_EN (BIT(30))
#define LPPERI_EFUSE_RESET_EN_M (LPPERI_EFUSE_RESET_EN_V << LPPERI_EFUSE_RESET_EN_S)
#define LPPERI_EFUSE_RESET_EN_V 0x00000001U
#define LPPERI_EFUSE_RESET_EN_S 30
/** LPPERI_LP_PERI_PMS_CONF_REG register
* LP Peripherals PMS configuration register
*/
#define LPPERI_LP_PERI_PMS_CONF_REG (DR_REG_LPPERI_BASE + 0x10)
/** LPPERI_LP_PERI_PMS_EXCEPTION_CLR : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear lp peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR (BIT(0))
#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR_M (LPPERI_LP_PERI_PMS_EXCEPTION_CLR_V << LPPERI_LP_PERI_PMS_EXCEPTION_CLR_S)
#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR_V 0x00000001U
#define LPPERI_LP_PERI_PMS_EXCEPTION_CLR_S 0
/** LPPERI_LP_PERI_PMS_EXCEPTION_INFO_REG register
* LP Peripherals PMS exception info record register
*/
#define LPPERI_LP_PERI_PMS_EXCEPTION_INFO_REG (DR_REG_LPPERI_BASE + 0x14)
/** LPPERI_LP_PERI_PMS_EXCEPTION_DET : RO; bitpos: [0]; default: 0;
* Represents whether the lp peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
#define LPPERI_LP_PERI_PMS_EXCEPTION_DET (BIT(0))
#define LPPERI_LP_PERI_PMS_EXCEPTION_DET_M (LPPERI_LP_PERI_PMS_EXCEPTION_DET_V << LPPERI_LP_PERI_PMS_EXCEPTION_DET_S)
#define LPPERI_LP_PERI_PMS_EXCEPTION_DET_V 0x00000001U
#define LPPERI_LP_PERI_PMS_EXCEPTION_DET_S 0
/** LPPERI_LP_PERI_PMS_EXCEPTION_ID : RO; bitpos: [5:1]; default: 0;
* Represents the master id when lp peripheral pms has been triggered.
*/
#define LPPERI_LP_PERI_PMS_EXCEPTION_ID 0x0000001FU
#define LPPERI_LP_PERI_PMS_EXCEPTION_ID_M (LPPERI_LP_PERI_PMS_EXCEPTION_ID_V << LPPERI_LP_PERI_PMS_EXCEPTION_ID_S)
#define LPPERI_LP_PERI_PMS_EXCEPTION_ID_V 0x0000001FU
#define LPPERI_LP_PERI_PMS_EXCEPTION_ID_S 1
/** LPPERI_LP_PERI_PMS_EXCEPTION_MODE : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when lp peripheral pms has been triggered.
*/
#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE 0x00000003U
#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE_M (LPPERI_LP_PERI_PMS_EXCEPTION_MODE_V << LPPERI_LP_PERI_PMS_EXCEPTION_MODE_S)
#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE_V 0x00000003U
#define LPPERI_LP_PERI_PMS_EXCEPTION_MODE_S 6
/** LPPERI_LP_PERI_PMS_EXCEPTION_ADDR : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when lp peripheral pms has been
* triggered.
*/
#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR 0x00FFFFFFU
#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_M (LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_V << LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_S)
#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_V 0x00FFFFFFU
#define LPPERI_LP_PERI_PMS_EXCEPTION_ADDR_S 8
/** LPPERI_INTERRUPT_SOURCE_REG register
* record the lp cpu interrupt
*/
#define LPPERI_INTERRUPT_SOURCE_REG (DR_REG_LPPERI_BASE + 0x20)
/** LPPERI_LP_INTERRUPT_SOURCE : RO; bitpos: [4:0]; default: 0;
* BIT4~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_analog_peri_int, lp_io_int
*/
#define LPPERI_LP_INTERRUPT_SOURCE 0x0000001FU
#define LPPERI_LP_INTERRUPT_SOURCE_M (LPPERI_LP_INTERRUPT_SOURCE_V << LPPERI_LP_INTERRUPT_SOURCE_S)
#define LPPERI_LP_INTERRUPT_SOURCE_V 0x0000001FU
#define LPPERI_LP_INTERRUPT_SOURCE_S 0
/** LPPERI_DATE_REG register
* version register
*/
#define LPPERI_DATE_REG (DR_REG_LPPERI_BASE + 0x3fc)
/** LPPERI_LPPERI_DATE : R/W; bitpos: [30:0]; default: 37819136;
* version register
*/
#define LPPERI_LPPERI_DATE 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_M (LPPERI_LPPERI_DATE_V << LPPERI_LPPERI_DATE_S)
#define LPPERI_LPPERI_DATE_V 0x7FFFFFFFU
#define LPPERI_LPPERI_DATE_S 0
/** LPPERI_CLK_EN : R/W; bitpos: [31]; default: 0;
* force on reg clk
*/
#define LPPERI_CLK_EN (BIT(31))
#define LPPERI_CLK_EN_M (LPPERI_CLK_EN_V << LPPERI_CLK_EN_S)
#define LPPERI_CLK_EN_V 0x00000001U
#define LPPERI_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of clk_en register
* configure peri in lp system clk enable
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** rng_apb_ck_en : R/W; bitpos: [23]; default: 1;
* lp rng apb clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t rng_apb_ck_en:1;
/** rng_ck_en : R/W; bitpos: [24]; default: 1;
* lp rng clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t rng_ck_en:1;
/** otp_dbg_ck_en : R/W; bitpos: [25]; default: 1;
* lp optdebug clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t otp_dbg_ck_en:1;
/** lp_touch_ck_en : R/W; bitpos: [26]; default: 1;
* lp touch clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t lp_touch_ck_en:1;
/** lp_io_ck_en : R/W; bitpos: [27]; default: 1;
* lp io clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t lp_io_ck_en:1;
uint32_t reserved_28:2;
/** efuse_ck_en : R/W; bitpos: [30]; default: 1;
* efuse core clk enable
* 1: enable clock
* 0: disable clock
*/
uint32_t efuse_ck_en:1;
uint32_t reserved_31:1;
};
uint32_t val;
} lpperi_clk_en_reg_t;
/** Type of reset_en register
* configure peri in lp system reset enable
*/
typedef union {
struct {
uint32_t reserved_0:23;
/** bus_reset_en : WT; bitpos: [23]; default: 0;
* lp bus reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t bus_reset_en:1;
/** lp_rng_apb_reset_en : R/W; bitpos: [24]; default: 0;
* lp rng apb reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_rng_apb_reset_en:1;
/** otp_dbg_reset_en : R/W; bitpos: [25]; default: 0;
* lp optdebug reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t otp_dbg_reset_en:1;
/** lp_touch_reset_en : R/W; bitpos: [26]; default: 0;
* lp touch reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_touch_reset_en:1;
/** lp_io_reset_en : R/W; bitpos: [27]; default: 0;
* lp io reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t lp_io_reset_en:1;
uint32_t reserved_28:2;
/** efuse_reset_en : R/W; bitpos: [30]; default: 0;
* efuse core reset enable
* 1: enable reset
* 0: disable reset
*/
uint32_t efuse_reset_en:1;
uint32_t reserved_31:1;
};
uint32_t val;
} lpperi_reset_en_reg_t;
/** Type of interrupt_source register
* record the lp cpu interrupt
*/
typedef union {
struct {
/** lp_interrupt_source : RO; bitpos: [4:0]; default: 0;
* BIT4~BIT0: pmu_lp_int, modem_lp_int, lp_timer_lp_int, lp_analog_peri_int, lp_io_int
*/
uint32_t lp_interrupt_source:5;
uint32_t reserved_5:27;
};
uint32_t val;
} lpperi_interrupt_source_reg_t;
/** Group: PMS Register */
/** Type of lp_peri_pms_conf register
* LP Peripherals PMS configuration register
*/
typedef union {
struct {
/** lp_peri_pms_exception_clr : WT; bitpos: [0]; default: 0;
* Configures whether or not to clear lp peri_pms_record_reg.
* 0: No clear
* 1: Clear peri_pms_record_reg
*/
uint32_t lp_peri_pms_exception_clr:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lpperi_lp_peri_pms_conf_reg_t;
/** Type of lp_peri_pms_exception_info register
* LP Peripherals PMS exception info record register
*/
typedef union {
struct {
/** lp_peri_pms_exception_det : RO; bitpos: [0]; default: 0;
* Represents whether the lp peripheral pms has been triggered.
* 0: No triggered
* 1: Has been triggered
*/
uint32_t lp_peri_pms_exception_det:1;
/** lp_peri_pms_exception_id : RO; bitpos: [5:1]; default: 0;
* Represents the master id when lp peripheral pms has been triggered.
*/
uint32_t lp_peri_pms_exception_id:5;
/** lp_peri_pms_exception_mode : RO; bitpos: [7:6]; default: 0;
* Represents the security mode when lp peripheral pms has been triggered.
*/
uint32_t lp_peri_pms_exception_mode:2;
/** lp_peri_pms_exception_addr : RO; bitpos: [31:8]; default: 0;
* Represents the access address (bit23~bit0) when lp peripheral pms has been
* triggered.
*/
uint32_t lp_peri_pms_exception_addr:24;
};
uint32_t val;
} lpperi_lp_peri_pms_exception_info_reg_t;
/** Group: Version register */
/** Type of date register
* version register
*/
typedef union {
struct {
/** lpperi_date : R/W; bitpos: [30:0]; default: 37819136;
* version register
*/
uint32_t lpperi_date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* force on reg clk
*/
uint32_t clk_en:1;
};
uint32_t val;
} lpperi_date_reg_t;
typedef struct {
volatile lpperi_clk_en_reg_t clk_en;
volatile lpperi_reset_en_reg_t reset_en;
uint32_t reserved_008[2];
volatile lpperi_lp_peri_pms_conf_reg_t lp_peri_pms_conf;
volatile lpperi_lp_peri_pms_exception_info_reg_t lp_peri_pms_exception_info;
uint32_t reserved_018[2];
volatile lpperi_interrupt_source_reg_t interrupt_source;
uint32_t reserved_024[246];
volatile lpperi_date_reg_t date;
} lpperi_dev_t;
extern lpperi_dev_t LPPERI;
#ifndef __cplusplus
_Static_assert(sizeof(lpperi_dev_t) == 0x400, "Invalid size of lpperi_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: read write control register */
/** Type of tee_trng_ctrl register
* trng read/write control register
*/
typedef union {
struct {
/** tee_read_tee_trng : R/W; bitpos: [0]; default: 1;
* Configures trng registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_trng:1;
/** tee_read_ree0_trng : R/W; bitpos: [1]; default: 0;
* Configures trng registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_trng:1;
/** tee_read_ree1_trng : R/W; bitpos: [2]; default: 0;
* Configures trng registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_trng:1;
/** tee_read_ree2_trng : R/W; bitpos: [3]; default: 0;
* Configures trng registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_trng:1;
/** tee_write_tee_trng : R/W; bitpos: [4]; default: 1;
* Configures trng registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_trng:1;
/** tee_write_ree0_trng : R/W; bitpos: [5]; default: 0;
* Configures trng registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_trng:1;
/** tee_write_ree1_trng : R/W; bitpos: [6]; default: 0;
* Configures trng registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_trng:1;
/** tee_write_ree2_trng : R/W; bitpos: [7]; default: 0;
* Configures trng registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_trng:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_trng_ctrl_reg_t;
/** Type of tee_efuse_ctrl register
* efuse read/write control register
*/
typedef union {
struct {
/** tee_read_tee_efuse : R/W; bitpos: [0]; default: 1;
* Configures efuse registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_efuse:1;
/** tee_read_ree0_efuse : R/W; bitpos: [1]; default: 0;
* Configures efuse registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_efuse:1;
/** tee_read_ree1_efuse : R/W; bitpos: [2]; default: 0;
* Configures efuse registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_efuse:1;
/** tee_read_ree2_efuse : R/W; bitpos: [3]; default: 0;
* Configures efuse registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_efuse:1;
/** tee_write_tee_efuse : R/W; bitpos: [4]; default: 1;
* Configures efuse registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_efuse:1;
/** tee_write_ree0_efuse : R/W; bitpos: [5]; default: 0;
* Configures efuse registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_efuse:1;
/** tee_write_ree1_efuse : R/W; bitpos: [6]; default: 0;
* Configures efuse registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_efuse:1;
/** tee_write_ree2_efuse : R/W; bitpos: [7]; default: 0;
* Configures efuse registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_efuse:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_efuse_ctrl_reg_t;
/** Type of tee_pmu_ctrl register
* pmu read/write control register
*/
typedef union {
struct {
/** tee_read_tee_pmu : R/W; bitpos: [0]; default: 1;
* Configures pmu registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_pmu:1;
/** tee_read_ree0_pmu : R/W; bitpos: [1]; default: 0;
* Configures pmu registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_pmu:1;
/** tee_read_ree1_pmu : R/W; bitpos: [2]; default: 0;
* Configures pmu registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_pmu:1;
/** tee_read_ree2_pmu : R/W; bitpos: [3]; default: 0;
* Configures pmu registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_pmu:1;
/** tee_write_tee_pmu : R/W; bitpos: [4]; default: 1;
* Configures pmu registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_pmu:1;
/** tee_write_ree0_pmu : R/W; bitpos: [5]; default: 0;
* Configures pmu registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_pmu:1;
/** tee_write_ree1_pmu : R/W; bitpos: [6]; default: 0;
* Configures pmu registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_pmu:1;
/** tee_write_ree2_pmu : R/W; bitpos: [7]; default: 0;
* Configures pmu registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_pmu:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_pmu_ctrl_reg_t;
/** Type of tee_clkrst_ctrl register
* clkrst read/write control register
*/
typedef union {
struct {
/** tee_read_tee_clkrst : R/W; bitpos: [0]; default: 1;
* Configures clkrst registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_clkrst:1;
/** tee_read_ree0_clkrst : R/W; bitpos: [1]; default: 0;
* Configures clkrst registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_clkrst:1;
/** tee_read_ree1_clkrst : R/W; bitpos: [2]; default: 0;
* Configures clkrst registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_clkrst:1;
/** tee_read_ree2_clkrst : R/W; bitpos: [3]; default: 0;
* Configures clkrst registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_clkrst:1;
/** tee_write_tee_clkrst : R/W; bitpos: [4]; default: 1;
* Configures clkrst registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_clkrst:1;
/** tee_write_ree0_clkrst : R/W; bitpos: [5]; default: 0;
* Configures clkrst registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_clkrst:1;
/** tee_write_ree1_clkrst : R/W; bitpos: [6]; default: 0;
* Configures clkrst registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_clkrst:1;
/** tee_write_ree2_clkrst : R/W; bitpos: [7]; default: 0;
* Configures clkrst registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_clkrst:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_clkrst_ctrl_reg_t;
/** Type of tee_lp_aon_ctrl_ctrl register
* lp_aon_ctrl read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_aon_ctrl : R/W; bitpos: [0]; default: 1;
* Configures lp_aon_ctrl registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_aon_ctrl:1;
/** tee_read_ree0_lp_aon_ctrl : R/W; bitpos: [1]; default: 0;
* Configures lp_aon_ctrl registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_aon_ctrl:1;
/** tee_read_ree1_lp_aon_ctrl : R/W; bitpos: [2]; default: 0;
* Configures lp_aon_ctrl registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_aon_ctrl:1;
/** tee_read_ree2_lp_aon_ctrl : R/W; bitpos: [3]; default: 0;
* Configures lp_aon_ctrl registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_aon_ctrl:1;
/** tee_write_tee_lp_aon_ctrl : R/W; bitpos: [4]; default: 1;
* Configures lp_aon_ctrl registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_aon_ctrl:1;
/** tee_write_ree0_lp_aon_ctrl : R/W; bitpos: [5]; default: 0;
* Configures lp_aon_ctrl registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_aon_ctrl:1;
/** tee_write_ree1_lp_aon_ctrl : R/W; bitpos: [6]; default: 0;
* Configures lp_aon_ctrl registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_aon_ctrl:1;
/** tee_write_ree2_lp_aon_ctrl : R/W; bitpos: [7]; default: 0;
* Configures lp_aon_ctrl registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_aon_ctrl:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_aon_ctrl_ctrl_reg_t;
/** Type of tee_lp_timer_ctrl register
* lp_timer read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_timer : R/W; bitpos: [0]; default: 1;
* Configures lp_timer registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_timer:1;
/** tee_read_ree0_lp_timer : R/W; bitpos: [1]; default: 0;
* Configures lp_timer registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_timer:1;
/** tee_read_ree1_lp_timer : R/W; bitpos: [2]; default: 0;
* Configures lp_timer registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_timer:1;
/** tee_read_ree2_lp_timer : R/W; bitpos: [3]; default: 0;
* Configures lp_timer registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_timer:1;
/** tee_write_tee_lp_timer : R/W; bitpos: [4]; default: 1;
* Configures lp_timer registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_timer:1;
/** tee_write_ree0_lp_timer : R/W; bitpos: [5]; default: 0;
* Configures lp_timer registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_timer:1;
/** tee_write_ree1_lp_timer : R/W; bitpos: [6]; default: 0;
* Configures lp_timer registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_timer:1;
/** tee_write_ree2_lp_timer : R/W; bitpos: [7]; default: 0;
* Configures lp_timer registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_timer:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_timer_ctrl_reg_t;
/** Type of tee_lp_wdt_ctrl register
* lp_wdt read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_wdt : R/W; bitpos: [0]; default: 1;
* Configures lp_wdt registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_wdt:1;
/** tee_read_ree0_lp_wdt : R/W; bitpos: [1]; default: 0;
* Configures lp_wdt registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_wdt:1;
/** tee_read_ree1_lp_wdt : R/W; bitpos: [2]; default: 0;
* Configures lp_wdt registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_wdt:1;
/** tee_read_ree2_lp_wdt : R/W; bitpos: [3]; default: 0;
* Configures lp_wdt registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_wdt:1;
/** tee_write_tee_lp_wdt : R/W; bitpos: [4]; default: 1;
* Configures lp_wdt registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_wdt:1;
/** tee_write_ree0_lp_wdt : R/W; bitpos: [5]; default: 0;
* Configures lp_wdt registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_wdt:1;
/** tee_write_ree1_lp_wdt : R/W; bitpos: [6]; default: 0;
* Configures lp_wdt registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_wdt:1;
/** tee_write_ree2_lp_wdt : R/W; bitpos: [7]; default: 0;
* Configures lp_wdt registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_wdt:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_wdt_ctrl_reg_t;
/** Type of tee_lpperi_ctrl register
* lpperi read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lpperi : R/W; bitpos: [0]; default: 1;
* Configures lpperi registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lpperi:1;
/** tee_read_ree0_lpperi : R/W; bitpos: [1]; default: 0;
* Configures lpperi registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lpperi:1;
/** tee_read_ree1_lpperi : R/W; bitpos: [2]; default: 0;
* Configures lpperi registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lpperi:1;
/** tee_read_ree2_lpperi : R/W; bitpos: [3]; default: 0;
* Configures lpperi registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lpperi:1;
/** tee_write_tee_lpperi : R/W; bitpos: [4]; default: 1;
* Configures lpperi registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lpperi:1;
/** tee_write_ree0_lpperi : R/W; bitpos: [5]; default: 0;
* Configures lpperi registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lpperi:1;
/** tee_write_ree1_lpperi : R/W; bitpos: [6]; default: 0;
* Configures lpperi registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lpperi:1;
/** tee_write_ree2_lpperi : R/W; bitpos: [7]; default: 0;
* Configures lpperi registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lpperi:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lpperi_ctrl_reg_t;
/** Type of tee_lp_ana_peri_ctrl register
* lp_ana_peri read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_ana_peri : R/W; bitpos: [0]; default: 1;
* Configures lp_ana_peri registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_ana_peri:1;
/** tee_read_ree0_lp_ana_peri : R/W; bitpos: [1]; default: 0;
* Configures lp_ana_peri registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_ana_peri:1;
/** tee_read_ree1_lp_ana_peri : R/W; bitpos: [2]; default: 0;
* Configures lp_ana_peri registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_ana_peri:1;
/** tee_read_ree2_lp_ana_peri : R/W; bitpos: [3]; default: 0;
* Configures lp_ana_peri registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_ana_peri:1;
/** tee_write_tee_lp_ana_peri : R/W; bitpos: [4]; default: 1;
* Configures lp_ana_peri registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_ana_peri:1;
/** tee_write_ree0_lp_ana_peri : R/W; bitpos: [5]; default: 0;
* Configures lp_ana_peri registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_ana_peri:1;
/** tee_write_ree1_lp_ana_peri : R/W; bitpos: [6]; default: 0;
* Configures lp_ana_peri registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_ana_peri:1;
/** tee_write_ree2_lp_ana_peri : R/W; bitpos: [7]; default: 0;
* Configures lp_ana_peri registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_ana_peri:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_ana_peri_ctrl_reg_t;
/** Type of tee_lp_touch_ctrl register
* lp_touch read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_touch : R/W; bitpos: [0]; default: 1;
* Configures lp_touch registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_touch:1;
/** tee_read_ree0_lp_touch : R/W; bitpos: [1]; default: 0;
* Configures lp_touch registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_touch:1;
/** tee_read_ree1_lp_touch : R/W; bitpos: [2]; default: 0;
* Configures lp_touch registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_touch:1;
/** tee_read_ree2_lp_touch : R/W; bitpos: [3]; default: 0;
* Configures lp_touch registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_touch:1;
/** tee_write_tee_lp_touch : R/W; bitpos: [4]; default: 1;
* Configures lp_touch registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_touch:1;
/** tee_write_ree0_lp_touch : R/W; bitpos: [5]; default: 0;
* Configures lp_touch registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_touch:1;
/** tee_write_ree1_lp_touch : R/W; bitpos: [6]; default: 0;
* Configures lp_touch registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_touch:1;
/** tee_write_ree2_lp_touch : R/W; bitpos: [7]; default: 0;
* Configures lp_touch registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_touch:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_touch_ctrl_reg_t;
/** Type of tee_touch_aon_ctrl register
* touch_aon read/write control register
*/
typedef union {
struct {
/** tee_read_tee_touch_aon : R/W; bitpos: [0]; default: 1;
* Configures touch_aon registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_touch_aon:1;
/** tee_read_ree0_touch_aon : R/W; bitpos: [1]; default: 0;
* Configures touch_aon registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_touch_aon:1;
/** tee_read_ree1_touch_aon : R/W; bitpos: [2]; default: 0;
* Configures touch_aon registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_touch_aon:1;
/** tee_read_ree2_touch_aon : R/W; bitpos: [3]; default: 0;
* Configures touch_aon registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_touch_aon:1;
/** tee_write_tee_touch_aon : R/W; bitpos: [4]; default: 1;
* Configures touch_aon registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_touch_aon:1;
/** tee_write_ree0_touch_aon : R/W; bitpos: [5]; default: 0;
* Configures touch_aon registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_touch_aon:1;
/** tee_write_ree1_touch_aon : R/W; bitpos: [6]; default: 0;
* Configures touch_aon registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_touch_aon:1;
/** tee_write_ree2_touch_aon : R/W; bitpos: [7]; default: 0;
* Configures touch_aon registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_touch_aon:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_touch_aon_ctrl_reg_t;
/** Type of tee_lp_io_ctrl register
* lp_io read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_io : R/W; bitpos: [0]; default: 1;
* Configures lp_io registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_io:1;
/** tee_read_ree0_lp_io : R/W; bitpos: [1]; default: 0;
* Configures lp_io registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_io:1;
/** tee_read_ree1_lp_io : R/W; bitpos: [2]; default: 0;
* Configures lp_io registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_io:1;
/** tee_read_ree2_lp_io : R/W; bitpos: [3]; default: 0;
* Configures lp_io registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_io:1;
/** tee_write_tee_lp_io : R/W; bitpos: [4]; default: 1;
* Configures lp_io registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_io:1;
/** tee_write_ree0_lp_io : R/W; bitpos: [5]; default: 0;
* Configures lp_io registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_io:1;
/** tee_write_ree1_lp_io : R/W; bitpos: [6]; default: 0;
* Configures lp_io registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_io:1;
/** tee_write_ree2_lp_io : R/W; bitpos: [7]; default: 0;
* Configures lp_io registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_io:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_io_ctrl_reg_t;
/** Type of tee_lp_ble_timer_ctrl register
* lp_ble_timer read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_ble_timer : R/W; bitpos: [0]; default: 1;
* Configures lp_ble_timer registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_ble_timer:1;
/** tee_read_ree0_lp_ble_timer : R/W; bitpos: [1]; default: 0;
* Configures lp_ble_timer registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_ble_timer:1;
/** tee_read_ree1_lp_ble_timer : R/W; bitpos: [2]; default: 0;
* Configures lp_ble_timer registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_ble_timer:1;
/** tee_read_ree2_lp_ble_timer : R/W; bitpos: [3]; default: 0;
* Configures lp_ble_timer registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_ble_timer:1;
/** tee_write_tee_lp_ble_timer : R/W; bitpos: [4]; default: 1;
* Configures lp_ble_timer registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_ble_timer:1;
/** tee_write_ree0_lp_ble_timer : R/W; bitpos: [5]; default: 0;
* Configures lp_ble_timer registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_ble_timer:1;
/** tee_write_ree1_lp_ble_timer : R/W; bitpos: [6]; default: 0;
* Configures lp_ble_timer registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_ble_timer:1;
/** tee_write_ree2_lp_ble_timer : R/W; bitpos: [7]; default: 0;
* Configures lp_ble_timer registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_ble_timer:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_ble_timer_ctrl_reg_t;
/** Type of tee_lp_tee_ctrl register
* lp_tee read/write control register
*/
typedef union {
struct {
/** tee_read_tee_lp_tee : R/W; bitpos: [0]; default: 1;
* Configures lp_tee registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_lp_tee:1;
/** tee_read_ree0_lp_tee : HRO; bitpos: [1]; default: 0;
* Configures lp_tee registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_lp_tee:1;
/** tee_read_ree1_lp_tee : HRO; bitpos: [2]; default: 0;
* Configures lp_tee registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_lp_tee:1;
/** tee_read_ree2_lp_tee : HRO; bitpos: [3]; default: 0;
* Configures lp_tee registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_lp_tee:1;
/** tee_write_tee_lp_tee : R/W; bitpos: [4]; default: 1;
* Configures lp_tee registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_lp_tee:1;
/** tee_write_ree0_lp_tee : HRO; bitpos: [5]; default: 0;
* Configures lp_tee registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_lp_tee:1;
/** tee_write_ree1_lp_tee : HRO; bitpos: [6]; default: 0;
* Configures lp_tee registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_lp_tee:1;
/** tee_write_ree2_lp_tee : HRO; bitpos: [7]; default: 0;
* Configures lp_tee registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_lp_tee:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_lp_tee_ctrl_reg_t;
/** Type of tee_huk_ctrl register
* lp_tee read/write control register
*/
typedef union {
struct {
/** tee_read_tee_huk : R/W; bitpos: [0]; default: 1;
* Configures huk registers read permission in tee mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_tee_huk:1;
/** tee_read_ree0_huk : R/W; bitpos: [1]; default: 0;
* Configures huk registers read permission in ree0 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree0_huk:1;
/** tee_read_ree1_huk : R/W; bitpos: [2]; default: 0;
* Configures huk registers read permission in ree1 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree1_huk:1;
/** tee_read_ree2_huk : R/W; bitpos: [3]; default: 0;
* Configures huk registers read permission in ree2 mode.
* 0: can not be read
* 1: can be read
*/
uint32_t tee_read_ree2_huk:1;
/** tee_write_tee_huk : R/W; bitpos: [4]; default: 1;
* Configures huk registers write permission in tee mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_tee_huk:1;
/** tee_write_ree0_huk : R/W; bitpos: [5]; default: 0;
* Configures huk registers write permission in ree0 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree0_huk:1;
/** tee_write_ree1_huk : R/W; bitpos: [6]; default: 0;
* Configures huk registers write permission in ree1 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree1_huk:1;
/** tee_write_ree2_huk : R/W; bitpos: [7]; default: 0;
* Configures huk registers write permission in ree2 mode.
* 0: can not be write
* 1: can be write
*/
uint32_t tee_write_ree2_huk:1;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_tee_huk_ctrl_reg_t;
/** Group: config register */
/** Type of tee_bus_err_conf register
* Clock gating register
*/
typedef union {
struct {
/** tee_bus_err_resp_en : R/W; bitpos: [0]; default: 0;
* Configures whether return error response to cpu when access blocked
* 0: disable error response
* 1: enable error response
*/
uint32_t tee_bus_err_resp_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_bus_err_conf_reg_t;
/** Group: clock gating register */
/** Type of tee_clock_gate register
* Clock gating register
*/
typedef union {
struct {
/** tee_clk_en : R/W; bitpos: [0]; default: 1;
* Configures whether to keep the clock always on.
* 0: enable automatic clock gating
* 1: keep the clock always on
*/
uint32_t tee_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} lp_tee_clock_gate_reg_t;
/** Group: Version control register */
/** Type of tee_date register
* Version control register
*/
typedef union {
struct {
/** tee_date : R/W; bitpos: [27:0]; default: 37818640;
* Version control register
*/
uint32_t tee_date:28;
uint32_t reserved_28:4;
};
uint32_t val;
} lp_tee_date_reg_t;
typedef struct {
volatile lp_tee_trng_ctrl_reg_t tee_trng_ctrl;
volatile lp_tee_efuse_ctrl_reg_t tee_efuse_ctrl;
volatile lp_tee_pmu_ctrl_reg_t tee_pmu_ctrl;
volatile lp_tee_clkrst_ctrl_reg_t tee_clkrst_ctrl;
volatile lp_tee_lp_aon_ctrl_ctrl_reg_t tee_lp_aon_ctrl_ctrl;
volatile lp_tee_lp_timer_ctrl_reg_t tee_lp_timer_ctrl;
volatile lp_tee_lp_wdt_ctrl_reg_t tee_lp_wdt_ctrl;
volatile lp_tee_lpperi_ctrl_reg_t tee_lpperi_ctrl;
volatile lp_tee_lp_ana_peri_ctrl_reg_t tee_lp_ana_peri_ctrl;
volatile lp_tee_lp_touch_ctrl_reg_t tee_lp_touch_ctrl;
volatile lp_tee_touch_aon_ctrl_reg_t tee_touch_aon_ctrl;
volatile lp_tee_lp_io_ctrl_reg_t tee_lp_io_ctrl;
volatile lp_tee_lp_ble_timer_ctrl_reg_t tee_lp_ble_timer_ctrl;
volatile lp_tee_lp_tee_ctrl_reg_t tee_lp_tee_ctrl;
volatile lp_tee_huk_ctrl_reg_t tee_huk_ctrl;
uint32_t reserved_03c[45];
volatile lp_tee_bus_err_conf_reg_t tee_bus_err_conf;
uint32_t reserved_0f4;
volatile lp_tee_clock_gate_reg_t tee_clock_gate;
volatile lp_tee_date_reg_t tee_date;
} lp_tee_dev_t;
extern lp_tee_dev_t LP_TEE;
#ifndef __cplusplus
_Static_assert(sizeof(lp_tee_dev_t) == 0x100, "Invalid size of lp_tee_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_timer_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_TIMER_TAR0_LOW_REG register
* RTC timer threshold low bits register0
*/
#define LP_TIMER_TAR0_LOW_REG (DR_REG_LP_BASE + 0x0)
/** LP_TIMER_MAIN_TIMER_TAR_LOW0 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare0.
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW0 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_M (LP_TIMER_MAIN_TIMER_TAR_LOW0_V << LP_TIMER_MAIN_TIMER_TAR_LOW0_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW0_S 0
/** LP_TIMER_TAR0_HIGH_REG register
* RTC timer enable register0
*/
#define LP_TIMER_TAR0_HIGH_REG (DR_REG_LP_BASE + 0x4)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH0 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare0
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_M (LP_TIMER_MAIN_TIMER_TAR_HIGH0_V << LP_TIMER_MAIN_TIMER_TAR_HIGH0_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH0_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN0 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare0 alarm.
* 0: Disable
* 1: Enable
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN0 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN0_M (LP_TIMER_MAIN_TIMER_TAR_EN0_V << LP_TIMER_MAIN_TIMER_TAR_EN0_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN0_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN0_S 31
/** LP_TIMER_TAR1_LOW_REG register
* RTC timer threshold low bits register1
*/
#define LP_TIMER_TAR1_LOW_REG (DR_REG_LP_BASE + 0x8)
/** LP_TIMER_MAIN_TIMER_TAR_LOW1 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare1.
*/
#define LP_TIMER_MAIN_TIMER_TAR_LOW1 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_M (LP_TIMER_MAIN_TIMER_TAR_LOW1_V << LP_TIMER_MAIN_TIMER_TAR_LOW1_S)
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_TAR_LOW1_S 0
/** LP_TIMER_TAR1_HIGH_REG register
* RTC timer threshold high bits register0
*/
#define LP_TIMER_TAR1_HIGH_REG (DR_REG_LP_BASE + 0xc)
/** LP_TIMER_MAIN_TIMER_TAR_HIGH1 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare1
*/
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_M (LP_TIMER_MAIN_TIMER_TAR_HIGH1_V << LP_TIMER_MAIN_TIMER_TAR_HIGH1_S)
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_TAR_HIGH1_S 0
/** LP_TIMER_MAIN_TIMER_TAR_EN1 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare1 alarm.
* 0: Disable
* 1: Enable
*/
#define LP_TIMER_MAIN_TIMER_TAR_EN1 (BIT(31))
#define LP_TIMER_MAIN_TIMER_TAR_EN1_M (LP_TIMER_MAIN_TIMER_TAR_EN1_V << LP_TIMER_MAIN_TIMER_TAR_EN1_S)
#define LP_TIMER_MAIN_TIMER_TAR_EN1_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_TAR_EN1_S 31
/** LP_TIMER_UPDATE_REG register
* RTC timer update control register
*/
#define LP_TIMER_UPDATE_REG (DR_REG_LP_BASE + 0x10)
/** LP_TIMER_MAIN_TIMER_UPDATE : WT; bitpos: [27]; default: 0;
* Triggers timer by software
*/
#define LP_TIMER_MAIN_TIMER_UPDATE (BIT(27))
#define LP_TIMER_MAIN_TIMER_UPDATE_M (LP_TIMER_MAIN_TIMER_UPDATE_V << LP_TIMER_MAIN_TIMER_UPDATE_S)
#define LP_TIMER_MAIN_TIMER_UPDATE_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_UPDATE_S 27
/** LP_TIMER_MAIN_TIMER_REGDMA_WORK : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK (BIT(28))
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_M (LP_TIMER_MAIN_TIMER_REGDMA_WORK_V << LP_TIMER_MAIN_TIMER_REGDMA_WORK_S)
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_REGDMA_WORK_S 28
/** LP_TIMER_MAIN_TIMER_XTAL_OFF : R/W; bitpos: [29]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers
* up
*/
#define LP_TIMER_MAIN_TIMER_XTAL_OFF (BIT(29))
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_M (LP_TIMER_MAIN_TIMER_XTAL_OFF_V << LP_TIMER_MAIN_TIMER_XTAL_OFF_S)
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_XTAL_OFF_S 29
/** LP_TIMER_MAIN_TIMER_SYS_STALL : R/W; bitpos: [30]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when CPU enters or
* exits the stall state.
*/
#define LP_TIMER_MAIN_TIMER_SYS_STALL (BIT(30))
#define LP_TIMER_MAIN_TIMER_SYS_STALL_M (LP_TIMER_MAIN_TIMER_SYS_STALL_V << LP_TIMER_MAIN_TIMER_SYS_STALL_S)
#define LP_TIMER_MAIN_TIMER_SYS_STALL_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_STALL_S 30
/** LP_TIMER_MAIN_TIMER_SYS_RST : R/W; bitpos: [31]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when resetting digital
* core completes
*/
#define LP_TIMER_MAIN_TIMER_SYS_RST (BIT(31))
#define LP_TIMER_MAIN_TIMER_SYS_RST_M (LP_TIMER_MAIN_TIMER_SYS_RST_V << LP_TIMER_MAIN_TIMER_SYS_RST_S)
#define LP_TIMER_MAIN_TIMER_SYS_RST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_SYS_RST_S 31
/** LP_TIMER_MAIN_BUF0_LOW_REG register
* RTC timer buffer0 low bits register
*/
#define LP_TIMER_MAIN_BUF0_LOW_REG (DR_REG_LP_BASE + 0x14)
/** LP_TIMER_MAIN_TIMER_BUF0_LOW : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer0 low bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF0_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_M (LP_TIMER_MAIN_TIMER_BUF0_LOW_V << LP_TIMER_MAIN_TIMER_BUF0_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_LOW_S 0
/** LP_TIMER_MAIN_BUF0_HIGH_REG register
* RTC timer buffer0 high bits register
*/
#define LP_TIMER_MAIN_BUF0_HIGH_REG (DR_REG_LP_BASE + 0x18)
/** LP_TIMER_MAIN_TIMER_BUF0_HIGH : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer0 high bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_M (LP_TIMER_MAIN_TIMER_BUF0_HIGH_V << LP_TIMER_MAIN_TIMER_BUF0_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF0_HIGH_S 0
/** LP_TIMER_MAIN_BUF1_LOW_REG register
* RTC timer buffer1 low bits register
*/
#define LP_TIMER_MAIN_BUF1_LOW_REG (DR_REG_LP_BASE + 0x1c)
/** LP_TIMER_MAIN_TIMER_BUF1_LOW : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer1 low bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF1_LOW 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_M (LP_TIMER_MAIN_TIMER_BUF1_LOW_V << LP_TIMER_MAIN_TIMER_BUF1_LOW_S)
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_V 0xFFFFFFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_LOW_S 0
/** LP_TIMER_MAIN_BUF1_HIGH_REG register
* RTC timer buffer1 high bits register
*/
#define LP_TIMER_MAIN_BUF1_HIGH_REG (DR_REG_LP_BASE + 0x20)
/** LP_TIMER_MAIN_TIMER_BUF1_HIGH : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer1 high bits register
*/
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_M (LP_TIMER_MAIN_TIMER_BUF1_HIGH_V << LP_TIMER_MAIN_TIMER_BUF1_HIGH_S)
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_V 0x0000FFFFU
#define LP_TIMER_MAIN_TIMER_BUF1_HIGH_S 0
/** LP_TIMER_INT_RAW_REG register
* RTC timer interrupt raw register
*/
#define LP_TIMER_INT_RAW_REG (DR_REG_LP_BASE + 0x28)
/** LP_TIMER_OVERFLOW_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow.
*/
#define LP_TIMER_OVERFLOW_RAW (BIT(30))
#define LP_TIMER_OVERFLOW_RAW_M (LP_TIMER_OVERFLOW_RAW_V << LP_TIMER_OVERFLOW_RAW_S)
#define LP_TIMER_OVERFLOW_RAW_V 0x00000001U
#define LP_TIMER_OVERFLOW_RAW_S 30
/** LP_TIMER_SOC_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value.
*/
#define LP_TIMER_SOC_WAKEUP_INT_RAW (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_RAW_M (LP_TIMER_SOC_WAKEUP_INT_RAW_V << LP_TIMER_SOC_WAKEUP_INT_RAW_S)
#define LP_TIMER_SOC_WAKEUP_INT_RAW_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_RAW_S 31
/** LP_TIMER_INT_ST_REG register
* RTC timer interrupt status register
*/
#define LP_TIMER_INT_ST_REG (DR_REG_LP_BASE + 0x2c)
/** LP_TIMER_OVERFLOW_ST : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
#define LP_TIMER_OVERFLOW_ST (BIT(30))
#define LP_TIMER_OVERFLOW_ST_M (LP_TIMER_OVERFLOW_ST_V << LP_TIMER_OVERFLOW_ST_S)
#define LP_TIMER_OVERFLOW_ST_V 0x00000001U
#define LP_TIMER_OVERFLOW_ST_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ST : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
#define LP_TIMER_SOC_WAKEUP_INT_ST (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ST_M (LP_TIMER_SOC_WAKEUP_INT_ST_V << LP_TIMER_SOC_WAKEUP_INT_ST_S)
#define LP_TIMER_SOC_WAKEUP_INT_ST_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ST_S 31
/** LP_TIMER_INT_ENA_REG register
* RTC timer interrupt enable register
*/
#define LP_TIMER_INT_ENA_REG (DR_REG_LP_BASE + 0x30)
/** LP_TIMER_OVERFLOW_ENA : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..
* 0 : Disable
* 1: Enable
*/
#define LP_TIMER_OVERFLOW_ENA (BIT(30))
#define LP_TIMER_OVERFLOW_ENA_M (LP_TIMER_OVERFLOW_ENA_V << LP_TIMER_OVERFLOW_ENA_S)
#define LP_TIMER_OVERFLOW_ENA_V 0x00000001U
#define LP_TIMER_OVERFLOW_ENA_S 30
/** LP_TIMER_SOC_WAKEUP_INT_ENA : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..
* 0 : Disable
* 1: Enable
*/
#define LP_TIMER_SOC_WAKEUP_INT_ENA (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_ENA_M (LP_TIMER_SOC_WAKEUP_INT_ENA_V << LP_TIMER_SOC_WAKEUP_INT_ENA_S)
#define LP_TIMER_SOC_WAKEUP_INT_ENA_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_ENA_S 31
/** LP_TIMER_INT_CLR_REG register
* RTC timer interrupt clear register
*/
#define LP_TIMER_INT_CLR_REG (DR_REG_LP_BASE + 0x34)
/** LP_TIMER_OVERFLOW_CLR : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow raw interrupt..
*/
#define LP_TIMER_OVERFLOW_CLR (BIT(30))
#define LP_TIMER_OVERFLOW_CLR_M (LP_TIMER_OVERFLOW_CLR_V << LP_TIMER_OVERFLOW_CLR_S)
#define LP_TIMER_OVERFLOW_CLR_V 0x00000001U
#define LP_TIMER_OVERFLOW_CLR_S 30
/** LP_TIMER_SOC_WAKEUP_INT_CLR : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer raw interrupt..
*/
#define LP_TIMER_SOC_WAKEUP_INT_CLR (BIT(31))
#define LP_TIMER_SOC_WAKEUP_INT_CLR_M (LP_TIMER_SOC_WAKEUP_INT_CLR_V << LP_TIMER_SOC_WAKEUP_INT_CLR_S)
#define LP_TIMER_SOC_WAKEUP_INT_CLR_V 0x00000001U
#define LP_TIMER_SOC_WAKEUP_INT_CLR_S 31
/** LP_TIMER_LP_INT_RAW_REG register
* RTC timer interrupt raw register(For ULP)
*/
#define LP_TIMER_LP_INT_RAW_REG (DR_REG_LP_BASE + 0x38)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_RAW_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_M (LP_TIMER_MAIN_TIMER_LP_INT_RAW_V << LP_TIMER_MAIN_TIMER_LP_INT_RAW_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_RAW_S 31
/** LP_TIMER_LP_INT_ST_REG register
* RTC timer interrupt status register(For ULP)
*/
#define LP_TIMER_LP_INT_ST_REG (DR_REG_LP_BASE + 0x3c)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ST_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ST : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ST (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_M (LP_TIMER_MAIN_TIMER_LP_INT_ST_V << LP_TIMER_MAIN_TIMER_LP_INT_ST_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ST_S 31
/** LP_TIMER_LP_INT_ENA_REG register
* RTC timer interrupt enable register(For ULP)
*/
#define LP_TIMER_LP_INT_ENA_REG (DR_REG_LP_BASE + 0x40)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..
* 0 : Disable
* 1: Enable
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_ENA_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..
* 0 : Disable
* 1: Enable
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_M (LP_TIMER_MAIN_TIMER_LP_INT_ENA_V << LP_TIMER_MAIN_TIMER_LP_INT_ENA_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_ENA_S 31
/** LP_TIMER_LP_INT_CLR_REG register
* RTC timer interrupt clear register(For ULP)
*/
#define LP_TIMER_LP_INT_CLR_REG (DR_REG_LP_BASE + 0x44)
/** LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow clear interrupt..
*/
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR (BIT(30))
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_OVERFLOW_LP_INT_CLR_S 30
/** LP_TIMER_MAIN_TIMER_LP_INT_CLR : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer clear interrupt..
*/
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR (BIT(31))
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_M (LP_TIMER_MAIN_TIMER_LP_INT_CLR_V << LP_TIMER_MAIN_TIMER_LP_INT_CLR_S)
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_V 0x00000001U
#define LP_TIMER_MAIN_TIMER_LP_INT_CLR_S 31
/** LP_TIMER_DATE_REG register
* Date register
*/
#define LP_TIMER_DATE_REG (DR_REG_LP_BASE + 0x3fc)
/** LP_TIMER_DATE : R/W; bitpos: [30:0]; default: 36769936;
* Version data
*/
#define LP_TIMER_DATE 0x7FFFFFFFU
#define LP_TIMER_DATE_M (LP_TIMER_DATE_V << LP_TIMER_DATE_S)
#define LP_TIMER_DATE_V 0x7FFFFFFFU
#define LP_TIMER_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_timer_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of timer_tar0_low register
* RTC timer threshold low bits register0
*/
typedef union {
struct {
/** timer_main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare0.
*/
uint32_t timer_main_timer_tar_low0:32;
};
uint32_t val;
} lp_timer_tar0_low_reg_t;
/** Type of timer_tar0_high register
* RTC timer enable register0
*/
typedef union {
struct {
/** timer_main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare0
*/
uint32_t timer_main_timer_tar_high0:16;
uint32_t reserved_16:15;
/** timer_main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare0 alarm.
* 0: Disable
* 1: Enable
*/
uint32_t timer_main_timer_tar_en0:1;
};
uint32_t val;
} lp_timer_tar0_high_reg_t;
/** Type of timer_tar1_low register
* RTC timer threshold low bits register1
*/
typedef union {
struct {
/** timer_main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
* Configures the lower 32 bits of the trigger threshold for the RTC timer compare1.
*/
uint32_t timer_main_timer_tar_low1:32;
};
uint32_t val;
} lp_timer_tar1_low_reg_t;
/** Type of timer_tar1_high register
* RTC timer threshold high bits register0
*/
typedef union {
struct {
/** timer_main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
* Configures the higher 16 bits of the trigger threshold for the RTC timer compare1
*/
uint32_t timer_main_timer_tar_high1:16;
uint32_t reserved_16:15;
/** timer_main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
* Configure this bit to enable the timer compare1 alarm.
* 0: Disable
* 1: Enable
*/
uint32_t timer_main_timer_tar_en1:1;
};
uint32_t val;
} lp_timer_tar1_high_reg_t;
/** Type of timer_update register
* RTC timer update control register
*/
typedef union {
struct {
uint32_t reserved_0:27;
/** timer_main_timer_update : WT; bitpos: [27]; default: 0;
* Triggers timer by software
*/
uint32_t timer_main_timer_update:1;
/** timer_main_timer_regdma_work : R/W; bitpos: [28]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when regdma working
*/
uint32_t timer_main_timer_regdma_work:1;
/** timer_main_timer_xtal_off : R/W; bitpos: [29]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when XTAL\_CLK powers
* up
*/
uint32_t timer_main_timer_xtal_off:1;
/** timer_main_timer_sys_stall : R/W; bitpos: [30]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when CPU enters or
* exits the stall state.
*/
uint32_t timer_main_timer_sys_stall:1;
/** timer_main_timer_sys_rst : R/W; bitpos: [31]; default: 0;
* Selects the triggering condition for the RTC timer,triggered when resetting digital
* core completes
*/
uint32_t timer_main_timer_sys_rst:1;
};
uint32_t val;
} lp_timer_update_reg_t;
/** Type of timer_main_buf0_low register
* RTC timer buffer0 low bits register
*/
typedef union {
struct {
/** timer_main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer0 low bits register
*/
uint32_t timer_main_timer_buf0_low:32;
};
uint32_t val;
} lp_timer_main_buf0_low_reg_t;
/** Type of timer_main_buf0_high register
* RTC timer buffer0 high bits register
*/
typedef union {
struct {
/** timer_main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer0 high bits register
*/
uint32_t timer_main_timer_buf0_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf0_high_reg_t;
/** Type of timer_main_buf1_low register
* RTC timer buffer1 low bits register
*/
typedef union {
struct {
/** timer_main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
* RTC timer buffer1 low bits register
*/
uint32_t timer_main_timer_buf1_low:32;
};
uint32_t val;
} lp_timer_main_buf1_low_reg_t;
/** Type of timer_main_buf1_high register
* RTC timer buffer1 high bits register
*/
typedef union {
struct {
/** timer_main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
* RTC timer buffer1 high bits register
*/
uint32_t timer_main_timer_buf1_high:16;
uint32_t reserved_16:16;
};
uint32_t val;
} lp_timer_main_buf1_high_reg_t;
/** Type of timer_int_raw register
* RTC timer interrupt raw register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow.
*/
uint32_t timer_overflow_raw:1;
/** timer_soc_wakeup_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value.
*/
uint32_t timer_soc_wakeup_int_raw:1;
};
uint32_t val;
} lp_timer_int_raw_reg_t;
/** Type of timer_int_st register
* RTC timer interrupt status register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_st : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
uint32_t timer_overflow_st:1;
/** timer_soc_wakeup_int_st : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
uint32_t timer_soc_wakeup_int_st:1;
};
uint32_t val;
} lp_timer_int_st_reg_t;
/** Type of timer_int_ena register
* RTC timer interrupt enable register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_ena : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..
* 0 : Disable
* 1: Enable
*/
uint32_t timer_overflow_ena:1;
/** timer_soc_wakeup_int_ena : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..
* 0 : Disable
* 1: Enable
*/
uint32_t timer_soc_wakeup_int_ena:1;
};
uint32_t val;
} lp_timer_int_ena_reg_t;
/** Type of timer_int_clr register
* RTC timer interrupt clear register
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_overflow_clr : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow raw interrupt..
*/
uint32_t timer_overflow_clr:1;
/** timer_soc_wakeup_int_clr : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer raw interrupt..
*/
uint32_t timer_soc_wakeup_int_clr:1;
};
uint32_t val;
} lp_timer_int_clr_reg_t;
/** Type of timer_lp_int_raw register
* RTC timer interrupt raw register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_main_timer_overflow_lp_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Triggered when counter register of RTC main timer overflow
*/
uint32_t timer_main_timer_overflow_lp_int_raw:1;
/** timer_main_timer_lp_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Triggered when RTC main timer reach the target value
*/
uint32_t timer_main_timer_lp_int_raw:1;
};
uint32_t val;
} lp_timer_lp_int_raw_reg_t;
/** Type of timer_lp_int_st register
* RTC timer interrupt status register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_main_timer_overflow_lp_int_st : RO; bitpos: [30]; default: 0;
* Status of RTC main timer overflow interrupt .
*/
uint32_t timer_main_timer_overflow_lp_int_st:1;
/** timer_main_timer_lp_int_st : RO; bitpos: [31]; default: 0;
* Status of RTC main timer interrupt .
*/
uint32_t timer_main_timer_lp_int_st:1;
};
uint32_t val;
} lp_timer_lp_int_st_reg_t;
/** Type of timer_lp_int_ena register
* RTC timer interrupt enable register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_main_timer_overflow_lp_int_ena : R/W; bitpos: [30]; default: 0;
* Enable the RTC main timer overflow interrupt..
* 0 : Disable
* 1: Enable
*/
uint32_t timer_main_timer_overflow_lp_int_ena:1;
/** timer_main_timer_lp_int_ena : R/W; bitpos: [31]; default: 0;
* Enable the RTC main timer interrupt..
* 0 : Disable
* 1: Enable
*/
uint32_t timer_main_timer_lp_int_ena:1;
};
uint32_t val;
} lp_timer_lp_int_ena_reg_t;
/** Type of timer_lp_int_clr register
* RTC timer interrupt clear register(For ULP)
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** timer_main_timer_overflow_lp_int_clr : WT; bitpos: [30]; default: 0;
* Clear the RTC main timer overflow clear interrupt..
*/
uint32_t timer_main_timer_overflow_lp_int_clr:1;
/** timer_main_timer_lp_int_clr : WT; bitpos: [31]; default: 0;
* Clear the RTC main timer clear interrupt..
*/
uint32_t timer_main_timer_lp_int_clr:1;
};
uint32_t val;
} lp_timer_lp_int_clr_reg_t;
/** Type of timer_date register
* Date register
*/
typedef union {
struct {
/** timer_date : R/W; bitpos: [30:0]; default: 36769936;
* Version data
*/
uint32_t timer_date:31;
uint32_t reserved_31:1;
};
uint32_t val;
} lp_timer_date_reg_t;
typedef struct {
volatile lp_timer_tar0_low_reg_t timer_tar0_low;
volatile lp_timer_tar0_high_reg_t timer_tar0_high;
volatile lp_timer_tar1_low_reg_t timer_tar1_low;
volatile lp_timer_tar1_high_reg_t timer_tar1_high;
volatile lp_timer_update_reg_t timer_update;
volatile lp_timer_main_buf0_low_reg_t timer_main_buf0_low;
volatile lp_timer_main_buf0_high_reg_t timer_main_buf0_high;
volatile lp_timer_main_buf1_low_reg_t timer_main_buf1_low;
volatile lp_timer_main_buf1_high_reg_t timer_main_buf1_high;
uint32_t reserved_024;
volatile lp_timer_int_raw_reg_t timer_int_raw;
volatile lp_timer_int_st_reg_t timer_int_st;
volatile lp_timer_int_ena_reg_t timer_int_ena;
volatile lp_timer_int_clr_reg_t timer_int_clr;
volatile lp_timer_lp_int_raw_reg_t timer_lp_int_raw;
volatile lp_timer_lp_int_st_reg_t timer_lp_int_st;
volatile lp_timer_lp_int_ena_reg_t timer_lp_int_ena;
volatile lp_timer_lp_int_clr_reg_t timer_lp_int_clr;
uint32_t reserved_048[237];
volatile lp_timer_date_reg_t timer_date;
} lp_timer_dev_t;
extern lp_timer_dev_t LP_TIMER;
#ifndef __cplusplus
_Static_assert(sizeof(lp_timer_dev_t) == 0x400, "Invalid size of lp_timer_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_wdt_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** LP_WDT_CONFIG0_REG register
* Configure the RWDT operation.
*/
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
* Configure whether or not pause RWDT when chip is in sleep mode.
* 0:Enable
* 1:Disable
*/
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
* Configure whether or not enable RWDT when chip is in SPI boot mode.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
* Configure the HP core reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
* Configure the HP CPU reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
* Configure the timeout action of stage3.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG3 0x00000007U
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
#define LP_WDT_WDT_STG3_V 0x00000007U
#define LP_WDT_WDT_STG3_S 19
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
* Configure the timeout action of stage2.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG2 0x00000007U
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
#define LP_WDT_WDT_STG2_V 0x00000007U
#define LP_WDT_WDT_STG2_S 22
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
* Configure the timeout action of stage1.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG1 0x00000007U
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
#define LP_WDT_WDT_STG1_V 0x00000007U
#define LP_WDT_WDT_STG1_S 25
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
* Configure the timeout action of stage0.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
#define LP_WDT_WDT_STG0 0x00000007U
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
#define LP_WDT_WDT_STG0_V 0x00000007U
#define LP_WDT_WDT_STG0_S 28
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable RWDT.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_WDT_EN (BIT(31))
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
#define LP_WDT_WDT_EN_V 0x00000001U
#define LP_WDT_WDT_EN_S 31
/** LP_WDT_CONFIG1_REG register
* Configure the RWDT timeout of stage0
*/
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
* Configure the timeout time for stage0.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG0_HOLD_S 0
/** LP_WDT_CONFIG2_REG register
* Configure the RWDT timeout of stage1
*/
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
* Configure the timeout time for stage1.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG1_HOLD_S 0
/** LP_WDT_CONFIG3_REG register
* Configure the RWDT timeout of stage2
*/
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage2.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG2_HOLD_S 0
/** LP_WDT_CONFIG4_REG register
* Configure the RWDT timeout of stage3
*/
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage3.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
#define LP_WDT_WDT_STG3_HOLD_S 0
/** LP_WDT_FEED_REG register
* Configure the feed function of RWDT
*/
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x18)
/** LP_WDT_RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the RWDT.
* 0: Invalid
* 1: Feed RWDT
*/
#define LP_WDT_RTC_WDT_FEED (BIT(31))
#define LP_WDT_RTC_WDT_FEED_M (LP_WDT_RTC_WDT_FEED_V << LP_WDT_RTC_WDT_FEED_S)
#define LP_WDT_RTC_WDT_FEED_V 0x00000001U
#define LP_WDT_RTC_WDT_FEED_S 31
/** LP_WDT_WPROTECT_REG register
* Configure the lock function of SWD
*/
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x1c)
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock RWDT`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
#define LP_WDT_WDT_WKEY_S 0
/** LP_WDT_SWD_CONFIG_REG register
* Configure the SWD operation
*/
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x20)
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
* Represents the SWD whether has generated the reset signal.
* 0 :No
* 1: Yes
*/
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
#define LP_WDT_SWD_RESET_FLAG_S 0
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
* Configure this bit to enable to feed SWD automatically by hardware.
* 0: Disable
* 1: Enable
*/
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
* Configure this bit to clear SWD reset flag.
* 0:Invalid
* 1: Clear the reset flag
*/
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
* Configure the SWD signal length that output to analog circuit.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
* Configure this bit to disable the SWD.
* 0: Enable the SWD
* 1: Disable the SWD
*/
#define LP_WDT_SWD_DISABLE (BIT(30))
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
#define LP_WDT_SWD_DISABLE_V 0x00000001U
#define LP_WDT_SWD_DISABLE_S 30
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the SWD.
* 0: Invalid
* 1: Feed SWD
*/
#define LP_WDT_SWD_FEED (BIT(31))
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
#define LP_WDT_SWD_FEED_V 0x00000001U
#define LP_WDT_SWD_FEED_S 31
/** LP_WDT_SWD_WPROTECT_REG register
* Configure the lock function of SWD
*/
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x24)
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock SWD`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
#define LP_WDT_SWD_WKEY_S 0
/** LP_WDT_INT_RAW_REG register
* Configure whether to generate timeout interrupt
*/
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x28)
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
* Represents the SWD whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
* Represents the RWDT whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
#define LP_WDT_LP_WDT_INT_RAW_S 31
/** LP_WDT_INT_ST_REG register
* The interrupt status register of WDT
*/
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x2c)
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
* Represents the SWD whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ST_S 30
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
* Represents the RWDT whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ST_S 31
/** LP_WDT_INT_ENA_REG register
* The interrupt enable register of WDT
*/
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x30)
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
* Configure whether or not to enable the SWD to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable the RWDT to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
#define LP_WDT_LP_WDT_INT_ENA_S 31
/** LP_WDT_INT_CLR_REG register
* The interrupt clear register of WDT
*/
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x34)
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.
* 0: No
* 1: Yes
*/
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.
* 0: No
* 1: Yes
*/
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
#define LP_WDT_LP_WDT_INT_CLR_S 31
/** LP_WDT_DATE_REG register
* need_des
*/
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 37765456;
* Version control register
*/
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
#define LP_WDT_LP_WDT_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/lp_wdt_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of wdt_config0 register
* Configure the RWDT operation.
*/
typedef union {
struct {
uint32_t reserved_0:9;
/** wdt_pause_in_slp : R/W; bitpos: [9]; default: 1;
* Configure whether or not pause RWDT when chip is in sleep mode.
* 0:Enable
* 1:Disable
*/
uint32_t wdt_pause_in_slp:1;
/** wdt_appcpu_reset_en : R/W; bitpos: [10]; default: 0;
* Configure whether or not to enable RWDT to reset CPU.
* 0:Disable
* 1:Enable
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wdt_appcpu_reset_en:1;
/** wdt_procpu_reset_en : R/W; bitpos: [11]; default: 0;
* need_des
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t wdt_procpu_reset_en:1;
/** wdt_flashboot_mod_en : R/W; bitpos: [12]; default: 1;
* Configure whether or not enable RWDT when chip is in SPI boot mode.
* 0:Disable
* 1:Enable
*/
uint32_t wdt_flashboot_mod_en:1;
/** wdt_sys_reset_length : R/W; bitpos: [15:13]; default: 1;
* Configure the HP core reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_sys_reset_length:3;
/** wdt_cpu_reset_length : R/W; bitpos: [18:16]; default: 1;
* Configure the HP CPU reset time.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_cpu_reset_length:3;
/** wdt_stg3 : R/W; bitpos: [21:19]; default: 0;
* Configure the timeout action of stage3.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg3:3;
/** wdt_stg2 : R/W; bitpos: [24:22]; default: 0;
* Configure the timeout action of stage2.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg2:3;
/** wdt_stg1 : R/W; bitpos: [27:25]; default: 0;
* Configure the timeout action of stage1.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg1:3;
/** wdt_stg0 : R/W; bitpos: [30:28]; default: 0;
* Configure the timeout action of stage0.
* 0: No operation
* 1:Generate interrupt
* 2 :Generate HP CPU reset
* 3:Generate HP core reset
* 4 :Generate system reset.
*/
uint32_t wdt_stg0:3;
/** wdt_en : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable RWDT.
* 0:Disable
* 1:Enable
*/
uint32_t wdt_en:1;
};
uint32_t val;
} lp_wdt_config0_reg_t;
/** Type of wdt_config1 register
* Configure the RWDT timeout of stage0
*/
typedef union {
struct {
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 200000;
* Configure the timeout time for stage0.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg0_hold:32;
};
uint32_t val;
} lp_wdt_config1_reg_t;
/** Type of wdt_config2 register
* Configure the RWDT timeout of stage1
*/
typedef union {
struct {
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 80000;
* Configure the timeout time for stage1.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg1_hold:32;
};
uint32_t val;
} lp_wdt_config2_reg_t;
/** Type of wdt_config3 register
* Configure the RWDT timeout of stage2
*/
typedef union {
struct {
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage2.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg2_hold:32;
};
uint32_t val;
} lp_wdt_config3_reg_t;
/** Type of wdt_config4 register
* Configure the RWDT timeout of stage3
*/
typedef union {
struct {
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 4095;
* Configure the timeout time for stage3.
* Measurement unit: LP\_DYN\_SLOW\_CLK
*/
uint32_t wdt_stg3_hold:32;
};
uint32_t val;
} lp_wdt_config4_reg_t;
/** Type of wdt_config5 register
* need_des
*/
typedef union {
struct {
/** wdt_chip_reset_target : R/W; bitpos: [7:0]; default: 255;
* need_des
*/
uint32_t wdt_chip_reset_target:8;
/** wdt_chip_reset_en : R/W; bitpos: [8]; default: 0;
* need_des
*/
uint32_t wdt_chip_reset_en:1;
/** wdt_chip_reset_key : R/W; bitpos: [16:9]; default: 0;
* need_des
*/
uint32_t wdt_chip_reset_key:8;
uint32_t reserved_17:15;
};
uint32_t val;
} lp_wdt_config5_reg_t;
/** Type of wdt_feed register
* Configure the feed function of RWDT
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** wdt_rtc_wdt_feed : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the RWDT.
* 0: Invalid
* 1: Feed RWDT
*/
uint32_t rtc_wdt_feed:1;
};
uint32_t val;
} lp_wdt_feed_reg_t;
/** Type of wdt_wprotect register
* Configure the lock function of SWD
*/
typedef union {
struct {
/** wdt_wkey : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock RWDT`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
uint32_t wdt_wkey:32;
};
uint32_t val;
} lp_wdt_wprotect_reg_t;
/** Type of wdt_swd_config register
* Configure the SWD operation
*/
typedef union {
struct {
/** wdt_swd_reset_flag : RO; bitpos: [0]; default: 0;
* Represents the SWD whether has generated the reset signal.
* 0 :No
* 1: Yes
*/
uint32_t wdt_swd_reset_flag:1;
uint32_t reserved_1:17;
/** wdt_swd_auto_feed_en : R/W; bitpos: [18]; default: 0;
* Configure this bit to enable to feed SWD automatically by hardware.
* 0: Disable
* 1: Enable
*/
uint32_t wdt_swd_auto_feed_en:1;
/** wdt_swd_rst_flag_clr : WT; bitpos: [19]; default: 0;
* Configure this bit to clear SWD reset flag.
* 0:Invalid
* 1: Clear the reset flag
*/
uint32_t wdt_swd_rst_flag_clr:1;
/** wdt_swd_signal_width : R/W; bitpos: [29:20]; default: 300;
* Configure the SWD signal length that output to analog circuit.
* Measurement unit: LP\_DYN\_FAST\_CLK
*/
uint32_t wdt_swd_signal_width:10;
/** wdt_swd_disable : R/W; bitpos: [30]; default: 0;
* Configure this bit to disable the SWD.
* 0: Enable the SWD
* 1: Disable the SWD
*/
uint32_t wdt_swd_disable:1;
/** wdt_swd_feed : WT; bitpos: [31]; default: 0;
* Configure this bit to feed the SWD.
* 0: Invalid
* 1: Feed SWD
*/
uint32_t wdt_swd_feed:1;
};
uint32_t val;
} lp_wdt_swd_config_reg_t;
/** Type of wdt_swd_wprotect register
* Configure the lock function of SWD
*/
typedef union {
struct {
/** wdt_swd_wkey : R/W; bitpos: [31:0]; default: 0;
* Configure this field to lock or unlock SWD`s configuration registers.
* 0x50D83AA1: unlock the RWDT configuration registers.
* Others value: Lock the RWDT configuration register which can`t be modified by
* software.
*/
uint32_t wdt_swd_wkey:32;
};
uint32_t val;
} lp_wdt_swd_wprotect_reg_t;
/** Type of wdt_int_raw register
* Configure whether to generate timeout interrupt
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** wdt_super_wdt_int_raw : R/WTC/SS; bitpos: [30]; default: 0;
* Represents the SWD whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
uint32_t wdt_super_wdt_int_raw:1;
/** wdt_lp_wdt_int_raw : R/WTC/SS; bitpos: [31]; default: 0;
* Represents the RWDT whether or not generates timeout interrupt.
* 0:No
* 1: Yes
*/
uint32_t wdt_lp_wdt_int_raw:1;
};
uint32_t val;
} lp_wdt_int_raw_reg_t;
/** Type of wdt_int_st register
* The interrupt status register of WDT
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** wdt_super_wdt_int_st : RO; bitpos: [30]; default: 0;
* Represents the SWD whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
uint32_t wdt_super_wdt_int_st:1;
/** lp_wdt_int_st : RO; bitpos: [31]; default: 0;
* Represents the RWDT whether or not has generated and sent timeout interrupt to CPU.
* 0:No
* 1: Yes
*/
uint32_t lp_wdt_int_st:1;
};
uint32_t val;
} lp_wdt_int_st_reg_t;
/** Type of wdt_int_ena register
* The interrupt enable register of WDT
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** wdt_super_wdt_int_ena : R/W; bitpos: [30]; default: 0;
* Configure whether or not to enable the SWD to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
uint32_t wdt_super_wdt_int_ena:1;
/** lp_wdt_int_ena : R/W; bitpos: [31]; default: 0;
* Configure whether or not to enable the RWDT to send timeout interrupt.
* 0:Disable
* 1:Enable
*/
uint32_t lp_wdt_int_ena:1;
};
uint32_t val;
} lp_wdt_int_ena_reg_t;
/** Type of wdt_int_clr register
* The interrupt clear register of WDT
*/
typedef union {
struct {
uint32_t reserved_0:30;
/** wdt_super_wdt_int_clr : WT; bitpos: [30]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by SWD to CPU.
* 0: No
* 1: Yes
*/
uint32_t wdt_super_wdt_int_clr:1;
/** lp_wdt_int_clr : WT; bitpos: [31]; default: 0;
* Configure whether to clear the timeout interrupt signal sent by RWDT to CPU.
* 0: No
* 1: Yes
*/
uint32_t lp_wdt_int_clr:1;
};
uint32_t val;
} lp_wdt_int_clr_reg_t;
/** Type of wdt_date register
* need_des
*/
typedef union {
struct {
/** wdt_lp_wdt_date : R/W; bitpos: [30:0]; default: 37765456;
* Version control register
*/
uint32_t wdt_lp_wdt_date:31;
uint32_t reserved_31:1;
};
uint32_t val;
} lp_wdt_date_reg_t;
typedef struct {
volatile lp_wdt_config0_reg_t config0;
volatile lp_wdt_config1_reg_t config1;
volatile lp_wdt_config2_reg_t config2;
volatile lp_wdt_config3_reg_t config3;
volatile lp_wdt_config4_reg_t config4;
volatile lp_wdt_config5_reg_t config5;
volatile lp_wdt_feed_reg_t feed;
volatile lp_wdt_wprotect_reg_t wprotect;
volatile lp_wdt_swd_config_reg_t swd_config;
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
volatile lp_wdt_int_raw_reg_t int_raw;
volatile lp_wdt_int_st_reg_t int_st;
volatile lp_wdt_int_ena_reg_t int_ena;
volatile lp_wdt_int_clr_reg_t int_clr;
uint32_t reserved_038[241];
volatile lp_wdt_date_reg_t date;
} lp_wdt_dev_t;
extern lp_wdt_dev_t LP_WDT;
#ifndef __cplusplus
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** RNG_DATA_REG register
* RNG result register
*/
#define RNG_DATA_REG (DR_REG_RNG_BASE + 0x0)
/** RNG_RND_DATA : RO; bitpos: [31:0]; default: 0;
* get rng data
*/
#define RNG_RND_DATA 0xFFFFFFFFU
#define RNG_RND_DATA_M (RNG_RND_DATA_V << RNG_RND_DATA_S)
#define RNG_RND_DATA_V 0xFFFFFFFFU
#define RNG_RND_DATA_S 0
/** RNG_CFG_REG register
* configure rng register
*/
#define RNG_CFG_REG (DR_REG_RNG_BASE + 0x4)
/** RNG_SAMPLE_ENABLE : R/W; bitpos: [0]; default: 0;
* reserved
*/
#define RNG_SAMPLE_ENABLE (BIT(0))
#define RNG_SAMPLE_ENABLE_M (RNG_SAMPLE_ENABLE_V << RNG_SAMPLE_ENABLE_S)
#define RNG_SAMPLE_ENABLE_V 0x00000001U
#define RNG_SAMPLE_ENABLE_S 0
/** RNG_TIMER_PSCALE : R/W; bitpos: [8:1]; default: 255;
* configure rng timer clk div
*/
#define RNG_TIMER_PSCALE 0x000000FFU
#define RNG_TIMER_PSCALE_M (RNG_TIMER_PSCALE_V << RNG_TIMER_PSCALE_S)
#define RNG_TIMER_PSCALE_V 0x000000FFU
#define RNG_TIMER_PSCALE_S 1
/** RNG_TIMER_EN : R/W; bitpos: [9]; default: 1;
* enable rng xor async rng timer
*/
#define RNG_TIMER_EN (BIT(9))
#define RNG_TIMER_EN_M (RNG_TIMER_EN_V << RNG_TIMER_EN_S)
#define RNG_TIMER_EN_V 0x00000001U
#define RNG_TIMER_EN_S 9
/** RNG_RTC_TIMER_EN : R/W; bitpos: [11:10]; default: 3;
* reserved
*/
#define RNG_RTC_TIMER_EN 0x00000003U
#define RNG_RTC_TIMER_EN_M (RNG_RTC_TIMER_EN_V << RNG_RTC_TIMER_EN_S)
#define RNG_RTC_TIMER_EN_V 0x00000003U
#define RNG_RTC_TIMER_EN_S 10
/** RNG_SAMPLE_CNT : RO; bitpos: [31:24]; default: 0;
* reserved
*/
#define RNG_SAMPLE_CNT 0x000000FFU
#define RNG_SAMPLE_CNT_M (RNG_SAMPLE_CNT_V << RNG_SAMPLE_CNT_S)
#define RNG_SAMPLE_CNT_V 0x000000FFU
#define RNG_SAMPLE_CNT_S 24
/** RNG_DATA_SYNC_REG register
* rng result sync register
*/
#define RNG_DATA_SYNC_REG (DR_REG_RNG_BASE + 0x8)
/** RNG_RND_SYNC_DATA : RO; bitpos: [31:0]; default: 0;
* get rnd sync result
*/
#define RNG_RND_SYNC_DATA 0xFFFFFFFFU
#define RNG_RND_SYNC_DATA_M (RNG_RND_SYNC_DATA_V << RNG_RND_SYNC_DATA_S)
#define RNG_RND_SYNC_DATA_V 0xFFFFFFFFU
#define RNG_RND_SYNC_DATA_S 0
/** RNG_DATE_REG register
* Date register.
*/
#define RNG_DATE_REG (DR_REG_RNG_BASE + 0x3fc)
/** RNG_DATE : R/W; bitpos: [30:0]; default: 36708608;
* RNG date information/ RNG version information.
*/
#define RNG_DATE 0x7FFFFFFFU
#define RNG_DATE_M (RNG_DATE_V << RNG_DATE_S)
#define RNG_DATE_V 0x7FFFFFFFU
#define RNG_DATE_S 0
/** RNG_CLK_EN : R/W; bitpos: [31]; default: 0;
* force on reg clk
*/
#define RNG_CLK_EN (BIT(31))
#define RNG_CLK_EN_M (RNG_CLK_EN_V << RNG_CLK_EN_S)
#define RNG_CLK_EN_V 0x00000001U
#define RNG_CLK_EN_S 31
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: configure_register */
/** Type of data register
* RNG result register
*/
typedef union {
struct {
/** rnd_data : RO; bitpos: [31:0]; default: 0;
* get rng data
*/
uint32_t rnd_data:32;
};
uint32_t val;
} rng_data_reg_t;
/** Type of cfg register
* configure rng register
*/
typedef union {
struct {
/** sample_enable : R/W; bitpos: [0]; default: 0;
* reserved
*/
uint32_t sample_enable:1;
/** timer_pscale : R/W; bitpos: [8:1]; default: 255;
* configure rng timer clk div
*/
uint32_t timer_pscale:8;
/** timer_en : R/W; bitpos: [9]; default: 1;
* enable rng xor async rng timer
*/
uint32_t timer_en:1;
/** rtc_timer_en : R/W; bitpos: [11:10]; default: 3;
* reserved
*/
uint32_t rtc_timer_en:2;
uint32_t reserved_12:12;
/** sample_cnt : RO; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t sample_cnt:8;
};
uint32_t val;
} rng_cfg_reg_t;
/** Type of data_sync register
* rng result sync register
*/
typedef union {
struct {
/** rnd_sync_data : RO; bitpos: [31:0]; default: 0;
* get rnd sync result
*/
uint32_t rnd_sync_data:32;
};
uint32_t val;
} rng_data_sync_reg_t;
/** Group: Version Register */
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** date : R/W; bitpos: [30:0]; default: 36708608;
* RNG date information/ RNG version information.
*/
uint32_t date:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* force on reg clk
*/
uint32_t clk_en:1;
};
uint32_t val;
} rng_date_reg_t;
typedef struct {
volatile rng_data_reg_t data;
volatile rng_cfg_reg_t cfg;
volatile rng_data_sync_reg_t data_sync;
uint32_t reserved_00c[252];
volatile rng_date_reg_t date;
} rng_dev_t;
extern rng_dev_t TRNG;
#ifndef __cplusplus
_Static_assert(sizeof(rng_dev_t) == 0x400, "Invalid size of rng_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** SHA_MODE_REG register
* Configures SHA algorithm
*/
#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
/** SHA_MODE : R/W; bitpos: [3:0]; default: 2;
* Configures the SHA algorithm.
* 0: SHA-1
* 1: SHA2-224
* 2: SHA2-256
* 3: SHA2-384
* 4: SHA2-512
* 5: SHA2-512/224
* 6: SHA2-512/256
* 7: SHA2-512/t
* 8: SHA3-224
* 9: SHA3-256
* 10: SHA3-384
* 11: SHA3-512
* 12: SHAKE128
* 13: SHAKE256
* 14: SM3
*/
#define SHA_MODE 0x0000000FU
#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
#define SHA_MODE_V 0x0000000FU
#define SHA_MODE_S 0
/** SHA_DMA_BLOCK_NUM_REG register
* Block number register (only effective for DMA-SHA)
*/
#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [15:0]; default: 0;
* Configures the DMA-SHA block number.
*/
#define SHA_DMA_BLOCK_NUM 0x0000FFFFU
#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
#define SHA_DMA_BLOCK_NUM_V 0x0000FFFFU
#define SHA_DMA_BLOCK_NUM_S 0
/** SHA_START_REG register
* Starts the SHA accelerator for Typical SHA operation
*/
#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
/** SHA_START : WO; bitpos: [0]; default: 0;
* Start typical sha.
*/
#define SHA_START (BIT(0))
#define SHA_START_M (SHA_START_V << SHA_START_S)
#define SHA_START_V 0x00000001U
#define SHA_START_S 0
/** SHA_CONTINUE_REG register
* Continues SHA operation (only effective in Typical SHA mode)
*/
#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
/** SHA_CONTINUE : WO; bitpos: [0]; default: 0;
* Continue typical sha.
*/
#define SHA_CONTINUE (BIT(0))
#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
#define SHA_CONTINUE_V 0x00000001U
#define SHA_CONTINUE_S 0
/** SHA_BUSY_REG register
* Represents if SHA Accelerator is busy or not
*/
#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
* Represents the states of SHA accelerator.
* 0: idle
* 1: busy
*/
#define SHA_BUSY_STATE (BIT(0))
#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
#define SHA_BUSY_STATE_V 0x00000001U
#define SHA_BUSY_STATE_S 0
/** SHA_DMA_START_REG register
* Starts the SHA accelerator for DMA-SHA operation
*/
#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
* Write 1 to start DMA-SHA calculation.
*/
#define SHA_DMA_START (BIT(0))
#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
#define SHA_DMA_START_V 0x00000001U
#define SHA_DMA_START_S 0
/** SHA_DMA_CONTINUE_REG register
* Continues SHA operation (only effective in DMA-SHA mode)
*/
#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
* Write 1 to continue DMA-SHA calculation.
*/
#define SHA_DMA_CONTINUE (BIT(0))
#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
#define SHA_DMA_CONTINUE_V 0x00000001U
#define SHA_DMA_CONTINUE_S 0
/** SHA_CLEAR_IRQ_REG register
* DMA-SHA interrupt clear register
*/
#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
* Write 1 to clear DMA-SHA interrupt.
*/
#define SHA_CLEAR_INTERRUPT (BIT(0))
#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
#define SHA_CLEAR_INTERRUPT_V 0x00000001U
#define SHA_CLEAR_INTERRUPT_S 0
/** SHA_IRQ_ENA_REG register
* DMA-SHA interrupt enable register
*/
#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
* Write 1 to enable DMA-SHA interrupt.
*/
#define SHA_INTERRUPT_ENA (BIT(0))
#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
#define SHA_INTERRUPT_ENA_V 0x00000001U
#define SHA_INTERRUPT_ENA_S 0
/** SHA_DATE_REG register
* Version control register
*/
#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
/** SHA_DATE : R/W; bitpos: [29:0]; default: 539232291;
* Version control register.
*/
#define SHA_DATE 0x3FFFFFFFU
#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
#define SHA_DATE_V 0x3FFFFFFFU
#define SHA_DATE_S 0
/** SHA_DMA_RX_RESET_REG register
* DMA RX FIFO Reset Signal
*/
#define SHA_DMA_RX_RESET_REG (DR_REG_SHA_BASE + 0x30)
/** SHA_DMA_RX_RESET : WO; bitpos: [0]; default: 0;
* Write 1 to reset DMA RX FIFO
*/
#define SHA_DMA_RX_RESET (BIT(0))
#define SHA_DMA_RX_RESET_M (SHA_DMA_RX_RESET_V << SHA_DMA_RX_RESET_S)
#define SHA_DMA_RX_RESET_V 0x00000001U
#define SHA_DMA_RX_RESET_S 0
/** SHA_2_SM_3_H_MEM register
* SHA1, SHA2-256, SM3 H memory which contains intermediate hash or final hash.
* SHA1, SHA2-256, SM3 : 0x00~0x20 (R/W)
* SHA2-512 : 0x00~0x40 (R/W)
*/
#define SHA_2_SM_3_H_MEM (DR_REG_SHA_BASE + 0x40)
#define SHA_2_SM_3_H_MEM_SIZE_BYTES 64
/** SHA_2_SM_3_M_MEM register
* SHA1, SHA2-256, SM3 M memory which contains message.
* SHA1, SHA2-256, SM3 : 0x00~0x40
* SHA2-512 : 0x00~0x80
*/
#define SHA_2_SM_3_M_MEM (DR_REG_SHA_BASE + 0x80)
#define SHA_2_SM_3_M_MEM_SIZE_BYTES 128
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Control/Configuration Registers */
/** Type of mode register
* Configures SHA algorithm
*/
typedef union {
struct {
/** mode : R/W; bitpos: [3:0]; default: 2;
* Configures the SHA algorithm.
* 0: SHA-1
* 1: SHA2-224
* 2: SHA2-256
* 3: SHA2-384
* 4: SHA2-512
* 5: SHA2-512/224
* 6: SHA2-512/256
* 7: SHA2-512/t
* 8: SHA3-224
* 9: SHA3-256
* 10: SHA3-384
* 11: SHA3-512
* 12: SHAKE128
* 13: SHAKE256
* 14: SM3
*/
uint32_t mode:4;
uint32_t reserved_4:28;
};
uint32_t val;
} sha_mode_reg_t;
/** Type of dma_block_num register
* Block number register (only effective for DMA-SHA)
*/
typedef union {
struct {
/** dma_block_num : R/W; bitpos: [15:0]; default: 0;
* Configures the DMA-SHA block number.
*/
uint32_t dma_block_num:16;
uint32_t reserved_16:16;
};
uint32_t val;
} sha_dma_block_num_reg_t;
/** Type of start register
* Starts the SHA accelerator for Typical SHA operation
*/
typedef union {
struct {
/** start : WO; bitpos: [0]; default: 0;
* Start typical sha.
*/
uint32_t start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_start_reg_t;
/** Type of continue register
* Continues SHA operation (only effective in Typical SHA mode)
*/
typedef union {
struct {
/** continue : WO; bitpos: [0]; default: 0;
* Continue typical sha.
*/
uint32_t continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_continue_reg_t;
/** Type of dma_start register
* Starts the SHA accelerator for DMA-SHA operation
*/
typedef union {
struct {
/** dma_start : WO; bitpos: [0]; default: 0;
* Write 1 to start DMA-SHA calculation.
*/
uint32_t dma_start:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_start_reg_t;
/** Type of dma_continue register
* Continues SHA operation (only effective in DMA-SHA mode)
*/
typedef union {
struct {
/** dma_continue : WO; bitpos: [0]; default: 0;
* Write 1 to continue DMA-SHA calculation.
*/
uint32_t dma_continue:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_continue_reg_t;
/** Type of dma_rx_reset register
* DMA RX FIFO Reset Signal
*/
typedef union {
struct {
/** dma_rx_reset : WO; bitpos: [0]; default: 0;
* Write 1 to reset DMA RX FIFO
*/
uint32_t dma_rx_reset:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_dma_rx_reset_reg_t;
/** Group: Status Registers */
/** Type of busy register
* Represents if SHA Accelerator is busy or not
*/
typedef union {
struct {
/** busy_state : RO; bitpos: [0]; default: 0;
* Represents the states of SHA accelerator.
* 0: idle
* 1: busy
*/
uint32_t busy_state:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_busy_reg_t;
/** Group: Interrupt Registers */
/** Type of clear_irq register
* DMA-SHA interrupt clear register
*/
typedef union {
struct {
/** clear_interrupt : WO; bitpos: [0]; default: 0;
* Write 1 to clear DMA-SHA interrupt.
*/
uint32_t clear_interrupt:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_clear_irq_reg_t;
/** Type of irq_ena register
* DMA-SHA interrupt enable register
*/
typedef union {
struct {
/** interrupt_ena : R/W; bitpos: [0]; default: 0;
* Write 1 to enable DMA-SHA interrupt.
*/
uint32_t interrupt_ena:1;
uint32_t reserved_1:31;
};
uint32_t val;
} sha_irq_ena_reg_t;
/** Group: Version Register */
/** Type of date register
* Version control register
*/
typedef union {
struct {
/** date : R/W; bitpos: [29:0]; default: 539232291;
* Version control register.
*/
uint32_t date:30;
uint32_t reserved_30:2;
};
uint32_t val;
} sha_date_reg_t;
/** Group: memory type */
typedef struct {
volatile sha_mode_reg_t mode;
uint32_t reserved_004[2];
volatile sha_dma_block_num_reg_t dma_block_num;
volatile sha_start_reg_t start;
volatile sha_continue_reg_t continue;
volatile sha_busy_reg_t busy;
volatile sha_dma_start_reg_t dma_start;
volatile sha_dma_continue_reg_t dma_continue;
volatile sha_clear_irq_reg_t clear_irq;
volatile sha_irq_ena_reg_t irq_ena;
volatile sha_date_reg_t date;
volatile sha_dma_rx_reset_reg_t dma_rx_reset;
uint32_t reserved_034[3];
volatile uint32_t 2_sm_3_h[16];
volatile uint32_t 2_sm_3_m[32];
} sha_dev_t;
extern sha_dev_t SHA;
#ifndef __cplusplus
_Static_assert(sizeof(sha_dev_t) == 0x100, "Invalid size of sha_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: Configuration Registers */
/** Type of serial_jtag_ep1 register
* FIFO access for the CDC-ACM data IN and OUT endpoints.
*/
typedef union {
struct {
/** serial_jtag_rdwr_byte : R/W; bitpos: [7:0]; default: 0;
* Write and read byte data to/from UART Tx/Rx FIFO through this field. When
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64
* bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t serial_jtag_rdwr_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
/** Type of serial_jtag_ep1_conf register
* Configuration and control registers for the CDC-ACM FIFOs.
*/
typedef union {
struct {
/** serial_jtag_wr_done : WT; bitpos: [0]; default: 0;
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
*/
uint32_t serial_jtag_wr_done:1;
/** serial_jtag_serial_in_ep_data_free : RO; bitpos: [1]; default: 1;
* 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing
* USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
* USB Host.
*/
uint32_t serial_jtag_serial_in_ep_data_free:1;
/** serial_jtag_serial_out_ep_data_avail : RO; bitpos: [2]; default: 0;
* 1'b1: Indicate there is data in UART Rx FIFO.
*/
uint32_t serial_jtag_serial_out_ep_data_avail:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_ep1_conf_reg_t;
/** Type of serial_jtag_conf0 register
* PHY hardware configuration.
*/
typedef union {
struct {
uint32_t reserved_0:1;
/** serial_jtag_exchg_pins_override : R/W; bitpos: [1]; default: 0;
* Enable software control USB D+ D- exchange
*/
uint32_t serial_jtag_exchg_pins_override:1;
/** serial_jtag_exchg_pins : R/W; bitpos: [2]; default: 0;
* USB D+ D- exchange
*/
uint32_t serial_jtag_exchg_pins:1;
/** serial_jtag_vrefh : R/W; bitpos: [4:3]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV
*/
uint32_t serial_jtag_vrefh:2;
/** serial_jtag_vrefl : R/W; bitpos: [6:5]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV
*/
uint32_t serial_jtag_vrefl:2;
/** serial_jtag_vref_override : R/W; bitpos: [7]; default: 0;
* Enable software control input threshold
*/
uint32_t serial_jtag_vref_override:1;
/** serial_jtag_pad_pull_override : R/W; bitpos: [8]; default: 0;
* Enable software control USB D+ D- pullup pulldown
*/
uint32_t serial_jtag_pad_pull_override:1;
/** serial_jtag_dp_pullup : R/W; bitpos: [9]; default: 1;
* Control USB D+ pull up.
*/
uint32_t serial_jtag_dp_pullup:1;
/** serial_jtag_dp_pulldown : R/W; bitpos: [10]; default: 0;
* Control USB D+ pull down.
*/
uint32_t serial_jtag_dp_pulldown:1;
/** serial_jtag_dm_pullup : R/W; bitpos: [11]; default: 0;
* Control USB D- pull up.
*/
uint32_t serial_jtag_dm_pullup:1;
/** serial_jtag_dm_pulldown : R/W; bitpos: [12]; default: 0;
* Control USB D- pull down.
*/
uint32_t serial_jtag_dm_pulldown:1;
/** serial_jtag_pullup_value : R/W; bitpos: [13]; default: 0;
* Control pull up value.
*/
uint32_t serial_jtag_pullup_value:1;
/** serial_jtag_usb_pad_enable : R/W; bitpos: [14]; default: 1;
* Enable USB pad function.
*/
uint32_t serial_jtag_usb_pad_enable:1;
/** serial_jtag_usb_jtag_bridge_en : R/W; bitpos: [15]; default: 0;
* Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is
* disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input
* through GPIO Matrix.
*/
uint32_t serial_jtag_usb_jtag_bridge_en:1;
/** serial_jtag_usb_phy_tx_edge_sel : R/W; bitpos: [16]; default: 0;
* Control at which clock edge the dp and dm are sent to USB PHY, 0: tx output at
* clock negative edge. 1: tx output at clock positive edge.
*/
uint32_t serial_jtag_usb_phy_tx_edge_sel:1;
uint32_t reserved_17:15;
};
uint32_t val;
} usb_serial_jtag_conf0_reg_t;
/** Type of serial_jtag_test register
* Registers used for debugging the PHY.
*/
typedef union {
struct {
/** serial_jtag_test_enable : R/W; bitpos: [0]; default: 0;
* Enable test of the USB pad
*/
uint32_t serial_jtag_test_enable:1;
/** serial_jtag_test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
*/
uint32_t serial_jtag_test_usb_oe:1;
/** serial_jtag_test_tx_dp : R/W; bitpos: [2]; default: 0;
* USB D+ tx value in test
*/
uint32_t serial_jtag_test_tx_dp:1;
/** serial_jtag_test_tx_dm : R/W; bitpos: [3]; default: 0;
* USB D- tx value in test
*/
uint32_t serial_jtag_test_tx_dm:1;
/** serial_jtag_test_rx_rcv : RO; bitpos: [4]; default: 1;
* USB RCV value in test
*/
uint32_t serial_jtag_test_rx_rcv:1;
/** serial_jtag_test_rx_dp : RO; bitpos: [5]; default: 1;
* USB D+ rx value in test
*/
uint32_t serial_jtag_test_rx_dp:1;
/** serial_jtag_test_rx_dm : RO; bitpos: [6]; default: 0;
* USB D- rx value in test
*/
uint32_t serial_jtag_test_rx_dm:1;
uint32_t reserved_7:25;
};
uint32_t val;
} usb_serial_jtag_test_reg_t;
/** Type of serial_jtag_misc_conf register
* Clock enable control
*/
typedef union {
struct {
/** serial_jtag_clk_en : R/W; bitpos: [0]; default: 0;
* 1'h1: Force clock on for register. 1'h0: Support clock only when application writes
* registers.
*/
uint32_t serial_jtag_clk_en:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_misc_conf_reg_t;
/** Type of serial_jtag_mem_conf register
* Memory power control
*/
typedef union {
struct {
/** serial_jtag_usb_mem_pd : R/W; bitpos: [0]; default: 0;
* 1: power down usb memory.
*/
uint32_t serial_jtag_usb_mem_pd:1;
/** serial_jtag_usb_mem_clk_en : R/W; bitpos: [1]; default: 1;
* 1: Force clock on for usb memory.
*/
uint32_t serial_jtag_usb_mem_clk_en:1;
uint32_t reserved_2:30;
};
uint32_t val;
} usb_serial_jtag_mem_conf_reg_t;
/** Type of serial_jtag_chip_rst register
* CDC-ACM chip reset control.
*/
typedef union {
struct {
/** serial_jtag_rts : RO; bitpos: [0]; default: 0;
* 1: Chip reset is detected from usb serial channel. Software write 1 to clear it.
*/
uint32_t serial_jtag_rts:1;
/** serial_jtag_dtr : RO; bitpos: [1]; default: 0;
* 1: Chip reset is detected from usb jtag channel. Software write 1 to clear it.
*/
uint32_t serial_jtag_dtr:1;
/** serial_jtag_usb_uart_chip_rst_dis : R/W; bitpos: [2]; default: 0;
* Set this bit to disable chip reset from usb serial channel to reset chip.
*/
uint32_t serial_jtag_usb_uart_chip_rst_dis:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_chip_rst_reg_t;
/** Type of serial_jtag_get_line_code_w0 register
* W0 of GET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_get_dw_dte_rate : R/W; bitpos: [31:0]; default: 0;
* The value of dwDTERate set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_dw_dte_rate:32;
};
uint32_t val;
} usb_serial_jtag_get_line_code_w0_reg_t;
/** Type of serial_jtag_get_line_code_w1 register
* W1 of GET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_get_bdata_bits : R/W; bitpos: [7:0]; default: 0;
* The value of bCharFormat set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_bdata_bits:8;
/** serial_jtag_get_bparity_type : R/W; bitpos: [15:8]; default: 0;
* The value of bParityTpye set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_bparity_type:8;
/** serial_jtag_get_bchar_format : R/W; bitpos: [23:16]; default: 0;
* The value of bDataBits set by software which is requested by GET_LINE_CODING
* command.
*/
uint32_t serial_jtag_get_bchar_format:8;
uint32_t reserved_24:8;
};
uint32_t val;
} usb_serial_jtag_get_line_code_w1_reg_t;
/** Type of serial_jtag_config_update register
* Configuration registers' value update
*/
typedef union {
struct {
/** serial_jtag_config_update : WT; bitpos: [0]; default: 0;
* Write 1 to this register would update the value of configure registers from APB
* clock domain to 48MHz clock domain.
*/
uint32_t serial_jtag_config_update:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_config_update_reg_t;
/** Type of serial_jtag_ser_afifo_config register
* Serial AFIFO configure register
*/
typedef union {
struct {
/** serial_jtag_serial_in_afifo_reset_wr : R/W; bitpos: [0]; default: 0;
* Write 1 to reset CDC_ACM IN async FIFO write clock domain.
*/
uint32_t serial_jtag_serial_in_afifo_reset_wr:1;
/** serial_jtag_serial_in_afifo_reset_rd : R/W; bitpos: [1]; default: 0;
* Write 1 to reset CDC_ACM IN async FIFO read clock domain.
*/
uint32_t serial_jtag_serial_in_afifo_reset_rd:1;
/** serial_jtag_serial_out_afifo_reset_wr : R/W; bitpos: [2]; default: 0;
* Write 1 to reset CDC_ACM OUT async FIFO write clock domain.
*/
uint32_t serial_jtag_serial_out_afifo_reset_wr:1;
/** serial_jtag_serial_out_afifo_reset_rd : R/W; bitpos: [3]; default: 0;
* Write 1 to reset CDC_ACM OUT async FIFO read clock domain.
*/
uint32_t serial_jtag_serial_out_afifo_reset_rd:1;
/** serial_jtag_serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/
uint32_t serial_jtag_serial_out_afifo_rempty:1;
/** serial_jtag_serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;
* CDC_ACM OUT IN async FIFO empty signal in write clock domain.
*/
uint32_t serial_jtag_serial_in_afifo_wfull:1;
uint32_t reserved_6:26;
};
uint32_t val;
} usb_serial_jtag_ser_afifo_config_reg_t;
/** Type of serial_jtag_serial_ep_timeout0 register
* USB uart out endpoint timeout configuration.
*/
typedef union {
struct {
/** serial_jtag_serial_timeout_en : R/W; bitpos: [0]; default: 0;
* USB serial out ep timeout enable. When a timeout event occurs, serial out ep buffer
* is automatically cleared and reg_serial_timeout_status is asserted.
*/
uint32_t serial_jtag_serial_timeout_en:1;
/** serial_jtag_serial_timeout_status : R/WTC/SS; bitpos: [1]; default: 0;
* Serial out ep triggers a timeout event.
*/
uint32_t serial_jtag_serial_timeout_status:1;
/** serial_jtag_serial_timeout_status_clr : WT; bitpos: [2]; default: 0;
* Write 1 to clear reg_serial_timeout_status.
*/
uint32_t serial_jtag_serial_timeout_status_clr:1;
uint32_t reserved_3:29;
};
uint32_t val;
} usb_serial_jtag_serial_ep_timeout0_reg_t;
/** Type of serial_jtag_serial_ep_timeout1 register
* USB uart out endpoint timeout configuration.
*/
typedef union {
struct {
/** serial_jtag_serial_timeout_max : R/W; bitpos: [31:0]; default: 4800768;
* USB serial out ep timeout max threshold value, indicates the maximum time that
* waiting for ESP to take away data in memory. This value is in steps of 20.83ns.
*/
uint32_t serial_jtag_serial_timeout_max:32;
};
uint32_t val;
} usb_serial_jtag_serial_ep_timeout1_reg_t;
/** Group: Interrupt Registers */
/** Type of serial_jtag_int_raw register
* Interrupt raw status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
* The raw interrupt bit turns to high level when flush cmd is received for IN
* endpoint 2 of JTAG.
*/
uint32_t serial_jtag_jtag_in_flush_int_raw:1;
/** serial_jtag_sof_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
* The raw interrupt bit turns to high level when SOF frame is received.
*/
uint32_t serial_jtag_sof_int_raw:1;
/** serial_jtag_serial_out_recv_pkt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
* one packet.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_raw:1;
/** serial_jtag_serial_in_empty_int_raw : R/WTC/SS; bitpos: [3]; default: 1;
* The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
*/
uint32_t serial_jtag_serial_in_empty_int_raw:1;
/** serial_jtag_pid_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
* The raw interrupt bit turns to high level when pid error is detected.
*/
uint32_t serial_jtag_pid_err_int_raw:1;
/** serial_jtag_crc5_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0;
* The raw interrupt bit turns to high level when CRC5 error is detected.
*/
uint32_t serial_jtag_crc5_err_int_raw:1;
/** serial_jtag_crc16_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* The raw interrupt bit turns to high level when CRC16 error is detected.
*/
uint32_t serial_jtag_crc16_err_int_raw:1;
/** serial_jtag_stuff_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0;
* The raw interrupt bit turns to high level when stuff error is detected.
*/
uint32_t serial_jtag_stuff_err_int_raw:1;
/** serial_jtag_in_token_rec_in_ep1_int_raw : R/WTC/SS; bitpos: [8]; default: 0;
* The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
* received.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_raw:1;
/** serial_jtag_usb_bus_reset_int_raw : R/WTC/SS; bitpos: [9]; default: 0;
* The raw interrupt bit turns to high level when usb bus reset is detected.
*/
uint32_t serial_jtag_usb_bus_reset_int_raw:1;
/** serial_jtag_out_ep1_zero_payload_int_raw : R/WTC/SS; bitpos: [10]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 1 received packet with
* zero palyload.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_raw:1;
/** serial_jtag_out_ep2_zero_payload_int_raw : R/WTC/SS; bitpos: [11]; default: 0;
* The raw interrupt bit turns to high level when OUT endpoint 2 received packet with
* zero palyload.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_raw:1;
/** serial_jtag_rts_chg_int_raw : R/WTC/SS; bitpos: [12]; default: 0;
* The raw interrupt bit turns to high level when level of RTS from usb serial channel
* is changed.
*/
uint32_t serial_jtag_rts_chg_int_raw:1;
/** serial_jtag_dtr_chg_int_raw : R/WTC/SS; bitpos: [13]; default: 0;
* The raw interrupt bit turns to high level when level of DTR from usb serial channel
* is changed.
*/
uint32_t serial_jtag_dtr_chg_int_raw:1;
/** serial_jtag_get_line_code_int_raw : R/WTC/SS; bitpos: [14]; default: 0;
* The raw interrupt bit turns to high level when level of GET LINE CODING request is
* received.
*/
uint32_t serial_jtag_get_line_code_int_raw:1;
/** serial_jtag_set_line_code_int_raw : R/WTC/SS; bitpos: [15]; default: 0;
* The raw interrupt bit turns to high level when level of SET LINE CODING request is
* received.
*/
uint32_t serial_jtag_set_line_code_int_raw:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_raw_reg_t;
/** Type of serial_jtag_int_st register
* Interrupt status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_st : RO; bitpos: [0]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t serial_jtag_jtag_in_flush_int_st:1;
/** serial_jtag_sof_int_st : RO; bitpos: [1]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t serial_jtag_sof_int_st:1;
/** serial_jtag_serial_out_recv_pkt_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* interrupt.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_st:1;
/** serial_jtag_serial_in_empty_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_jtag_serial_in_empty_int_st:1;
/** serial_jtag_pid_err_int_st : RO; bitpos: [4]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t serial_jtag_pid_err_int_st:1;
/** serial_jtag_crc5_err_int_st : RO; bitpos: [5]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc5_err_int_st:1;
/** serial_jtag_crc16_err_int_st : RO; bitpos: [6]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc16_err_int_st:1;
/** serial_jtag_stuff_err_int_st : RO; bitpos: [7]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t serial_jtag_stuff_err_int_st:1;
/** serial_jtag_in_token_rec_in_ep1_int_st : RO; bitpos: [8]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
* interrupt.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_st:1;
/** serial_jtag_usb_bus_reset_int_st : RO; bitpos: [9]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t serial_jtag_usb_bus_reset_int_st:1;
/** serial_jtag_out_ep1_zero_payload_int_st : RO; bitpos: [10]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_st:1;
/** serial_jtag_out_ep2_zero_payload_int_st : RO; bitpos: [11]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
* interrupt.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_st:1;
/** serial_jtag_rts_chg_int_st : RO; bitpos: [12]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t serial_jtag_rts_chg_int_st:1;
/** serial_jtag_dtr_chg_int_st : RO; bitpos: [13]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t serial_jtag_dtr_chg_int_st:1;
/** serial_jtag_get_line_code_int_st : RO; bitpos: [14]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_get_line_code_int_st:1;
/** serial_jtag_set_line_code_int_st : RO; bitpos: [15]; default: 0;
* The raw interrupt status bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_set_line_code_int_st:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_st_reg_t;
/** Type of serial_jtag_int_ena register
* Interrupt enable status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_ena : R/W; bitpos: [0]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t serial_jtag_jtag_in_flush_int_ena:1;
/** serial_jtag_sof_int_ena : R/W; bitpos: [1]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.
*/
uint32_t serial_jtag_sof_int_ena:1;
/** serial_jtag_serial_out_recv_pkt_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_ena:1;
/** serial_jtag_serial_in_empty_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_jtag_serial_in_empty_int_ena:1;
/** serial_jtag_pid_err_int_ena : R/W; bitpos: [4]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t serial_jtag_pid_err_int_ena:1;
/** serial_jtag_crc5_err_int_ena : R/W; bitpos: [5]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc5_err_int_ena:1;
/** serial_jtag_crc16_err_int_ena : R/W; bitpos: [6]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc16_err_int_ena:1;
/** serial_jtag_stuff_err_int_ena : R/W; bitpos: [7]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t serial_jtag_stuff_err_int_ena:1;
/** serial_jtag_in_token_rec_in_ep1_int_ena : R/W; bitpos: [8]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_ena:1;
/** serial_jtag_usb_bus_reset_int_ena : R/W; bitpos: [9]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t serial_jtag_usb_bus_reset_int_ena:1;
/** serial_jtag_out_ep1_zero_payload_int_ena : R/W; bitpos: [10]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_ena:1;
/** serial_jtag_out_ep2_zero_payload_int_ena : R/W; bitpos: [11]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_ena:1;
/** serial_jtag_rts_chg_int_ena : R/W; bitpos: [12]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t serial_jtag_rts_chg_int_ena:1;
/** serial_jtag_dtr_chg_int_ena : R/W; bitpos: [13]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t serial_jtag_dtr_chg_int_ena:1;
/** serial_jtag_get_line_code_int_ena : R/W; bitpos: [14]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_get_line_code_int_ena:1;
/** serial_jtag_set_line_code_int_ena : R/W; bitpos: [15]; default: 0;
* The interrupt enable bit for the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_set_line_code_int_ena:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_ena_reg_t;
/** Type of serial_jtag_int_clr register
* Interrupt clear status register.
*/
typedef union {
struct {
/** serial_jtag_jtag_in_flush_int_clr : WT; bitpos: [0]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.
*/
uint32_t serial_jtag_jtag_in_flush_int_clr:1;
/** serial_jtag_sof_int_clr : WT; bitpos: [1]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.
*/
uint32_t serial_jtag_sof_int_clr:1;
/** serial_jtag_serial_out_recv_pkt_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.
*/
uint32_t serial_jtag_serial_out_recv_pkt_int_clr:1;
/** serial_jtag_serial_in_empty_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.
*/
uint32_t serial_jtag_serial_in_empty_int_clr:1;
/** serial_jtag_pid_err_int_clr : WT; bitpos: [4]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.
*/
uint32_t serial_jtag_pid_err_int_clr:1;
/** serial_jtag_crc5_err_int_clr : WT; bitpos: [5]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc5_err_int_clr:1;
/** serial_jtag_crc16_err_int_clr : WT; bitpos: [6]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.
*/
uint32_t serial_jtag_crc16_err_int_clr:1;
/** serial_jtag_stuff_err_int_clr : WT; bitpos: [7]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.
*/
uint32_t serial_jtag_stuff_err_int_clr:1;
/** serial_jtag_in_token_rec_in_ep1_int_clr : WT; bitpos: [8]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.
*/
uint32_t serial_jtag_in_token_rec_in_ep1_int_clr:1;
/** serial_jtag_usb_bus_reset_int_clr : WT; bitpos: [9]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.
*/
uint32_t serial_jtag_usb_bus_reset_int_clr:1;
/** serial_jtag_out_ep1_zero_payload_int_clr : WT; bitpos: [10]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep1_zero_payload_int_clr:1;
/** serial_jtag_out_ep2_zero_payload_int_clr : WT; bitpos: [11]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
*/
uint32_t serial_jtag_out_ep2_zero_payload_int_clr:1;
/** serial_jtag_rts_chg_int_clr : WT; bitpos: [12]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_RTS_CHG_INT interrupt.
*/
uint32_t serial_jtag_rts_chg_int_clr:1;
/** serial_jtag_dtr_chg_int_clr : WT; bitpos: [13]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_DTR_CHG_INT interrupt.
*/
uint32_t serial_jtag_dtr_chg_int_clr:1;
/** serial_jtag_get_line_code_int_clr : WT; bitpos: [14]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_GET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_get_line_code_int_clr:1;
/** serial_jtag_set_line_code_int_clr : WT; bitpos: [15]; default: 0;
* Set this bit to clear the USB_SERIAL_JTAG_SET_LINE_CODE_INT interrupt.
*/
uint32_t serial_jtag_set_line_code_int_clr:1;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_int_clr_reg_t;
/** Group: Status Registers */
/** Type of serial_jtag_jfifo_st register
* JTAG FIFO status and control registers.
*/
typedef union {
struct {
/** serial_jtag_in_fifo_cnt : RO; bitpos: [1:0]; default: 0;
* JTAT in fifo counter.
*/
uint32_t serial_jtag_in_fifo_cnt:2;
/** serial_jtag_in_fifo_empty : RO; bitpos: [2]; default: 1;
* 1: JTAG in fifo is empty.
*/
uint32_t serial_jtag_in_fifo_empty:1;
/** serial_jtag_in_fifo_full : RO; bitpos: [3]; default: 0;
* 1: JTAG in fifo is full.
*/
uint32_t serial_jtag_in_fifo_full:1;
/** serial_jtag_out_fifo_cnt : RO; bitpos: [5:4]; default: 0;
* JTAT out fifo counter.
*/
uint32_t serial_jtag_out_fifo_cnt:2;
/** serial_jtag_out_fifo_empty : RO; bitpos: [6]; default: 1;
* 1: JTAG out fifo is empty.
*/
uint32_t serial_jtag_out_fifo_empty:1;
/** serial_jtag_out_fifo_full : RO; bitpos: [7]; default: 0;
* 1: JTAG out fifo is full.
*/
uint32_t serial_jtag_out_fifo_full:1;
/** serial_jtag_in_fifo_reset : R/W; bitpos: [8]; default: 0;
* Write 1 to reset JTAG in fifo.
*/
uint32_t serial_jtag_in_fifo_reset:1;
/** serial_jtag_out_fifo_reset : R/W; bitpos: [9]; default: 0;
* Write 1 to reset JTAG out fifo.
*/
uint32_t serial_jtag_out_fifo_reset:1;
uint32_t reserved_10:22;
};
uint32_t val;
} usb_serial_jtag_jfifo_st_reg_t;
/** Type of serial_jtag_fram_num register
* Last received SOF frame index register.
*/
typedef union {
struct {
/** serial_jtag_sof_frame_index : RO; bitpos: [10:0]; default: 0;
* Frame index of received SOF frame.
*/
uint32_t serial_jtag_sof_frame_index:11;
uint32_t reserved_11:21;
};
uint32_t val;
} usb_serial_jtag_fram_num_reg_t;
/** Type of serial_jtag_in_ep0_st register
* Control IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep0_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 0.
*/
uint32_t serial_jtag_in_ep0_state:2;
/** serial_jtag_in_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 0.
*/
uint32_t serial_jtag_in_ep0_wr_addr:7;
/** serial_jtag_in_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 0.
*/
uint32_t serial_jtag_in_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep0_st_reg_t;
/** Type of serial_jtag_in_ep1_st register
* CDC-ACM IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep1_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 1.
*/
uint32_t serial_jtag_in_ep1_state:2;
/** serial_jtag_in_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 1.
*/
uint32_t serial_jtag_in_ep1_wr_addr:7;
/** serial_jtag_in_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 1.
*/
uint32_t serial_jtag_in_ep1_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep1_st_reg_t;
/** Type of serial_jtag_in_ep2_st register
* CDC-ACM interrupt IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep2_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 2.
*/
uint32_t serial_jtag_in_ep2_state:2;
/** serial_jtag_in_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 2.
*/
uint32_t serial_jtag_in_ep2_wr_addr:7;
/** serial_jtag_in_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 2.
*/
uint32_t serial_jtag_in_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep2_st_reg_t;
/** Type of serial_jtag_in_ep3_st register
* JTAG IN endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_in_ep3_state : RO; bitpos: [1:0]; default: 1;
* State of IN Endpoint 3.
*/
uint32_t serial_jtag_in_ep3_state:2;
/** serial_jtag_in_ep3_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of IN endpoint 3.
*/
uint32_t serial_jtag_in_ep3_wr_addr:7;
/** serial_jtag_in_ep3_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of IN endpoint 3.
*/
uint32_t serial_jtag_in_ep3_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_in_ep3_st_reg_t;
/** Type of serial_jtag_out_ep0_st register
* Control OUT endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_out_ep0_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 0.
*/
uint32_t serial_jtag_out_ep0_state:2;
/** serial_jtag_out_ep0_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
*/
uint32_t serial_jtag_out_ep0_wr_addr:7;
/** serial_jtag_out_ep0_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 0.
*/
uint32_t serial_jtag_out_ep0_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep0_st_reg_t;
/** Type of serial_jtag_out_ep1_st register
* CDC-ACM OUT endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_out_ep1_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 1.
*/
uint32_t serial_jtag_out_ep1_state:2;
/** serial_jtag_out_ep1_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
*/
uint32_t serial_jtag_out_ep1_wr_addr:7;
/** serial_jtag_out_ep1_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 1.
*/
uint32_t serial_jtag_out_ep1_rd_addr:7;
/** serial_jtag_out_ep1_rec_data_cnt : RO; bitpos: [22:16]; default: 0;
* Data count in OUT endpoint 1 when one packet is received.
*/
uint32_t serial_jtag_out_ep1_rec_data_cnt:7;
uint32_t reserved_23:9;
};
uint32_t val;
} usb_serial_jtag_out_ep1_st_reg_t;
/** Type of serial_jtag_out_ep2_st register
* JTAG OUT endpoint status information.
*/
typedef union {
struct {
/** serial_jtag_out_ep2_state : RO; bitpos: [1:0]; default: 0;
* State of OUT Endpoint 2.
*/
uint32_t serial_jtag_out_ep2_state:2;
/** serial_jtag_out_ep2_wr_addr : RO; bitpos: [8:2]; default: 0;
* Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
* is detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
*/
uint32_t serial_jtag_out_ep2_wr_addr:7;
/** serial_jtag_out_ep2_rd_addr : RO; bitpos: [15:9]; default: 0;
* Read data address of OUT endpoint 2.
*/
uint32_t serial_jtag_out_ep2_rd_addr:7;
uint32_t reserved_16:16;
};
uint32_t val;
} usb_serial_jtag_out_ep2_st_reg_t;
/** Type of serial_jtag_set_line_code_w0 register
* W0 of SET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_dw_dte_rate : RO; bitpos: [31:0]; default: 0;
* The value of dwDTERate set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_dw_dte_rate:32;
};
uint32_t val;
} usb_serial_jtag_set_line_code_w0_reg_t;
/** Type of serial_jtag_set_line_code_w1 register
* W1 of SET_LINE_CODING command.
*/
typedef union {
struct {
/** serial_jtag_bchar_format : RO; bitpos: [7:0]; default: 0;
* The value of bCharFormat set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_bchar_format:8;
/** serial_jtag_bparity_type : RO; bitpos: [15:8]; default: 0;
* The value of bParityTpye set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_bparity_type:8;
/** serial_jtag_bdata_bits : RO; bitpos: [23:16]; default: 0;
* The value of bDataBits set by host through SET_LINE_CODING command.
*/
uint32_t serial_jtag_bdata_bits:8;
uint32_t reserved_24:8;
};
uint32_t val;
} usb_serial_jtag_set_line_code_w1_reg_t;
/** Type of serial_jtag_bus_reset_st register
* USB Bus reset status register
*/
typedef union {
struct {
/** serial_jtag_usb_bus_reset_st : RO; bitpos: [0]; default: 1;
* USB bus reset status. 0: USB-Serial-JTAG is in usb bus reset status. 1: USB bus
* reset is released.
*/
uint32_t serial_jtag_usb_bus_reset_st:1;
uint32_t reserved_1:31;
};
uint32_t val;
} usb_serial_jtag_bus_reset_st_reg_t;
/** Group: Version Registers */
/** Type of serial_jtag_date register
* Date register
*/
typedef union {
struct {
/** serial_jtag_date : R/W; bitpos: [31:0]; default: 37777456;
* register version.
*/
uint32_t serial_jtag_date:32;
};
uint32_t val;
} usb_serial_jtag_date_reg_t;
typedef struct {
volatile usb_serial_jtag_ep1_reg_t serial_jtag_ep1;
volatile usb_serial_jtag_ep1_conf_reg_t serial_jtag_ep1_conf;
volatile usb_serial_jtag_int_raw_reg_t serial_jtag_int_raw;
volatile usb_serial_jtag_int_st_reg_t serial_jtag_int_st;
volatile usb_serial_jtag_int_ena_reg_t serial_jtag_int_ena;
volatile usb_serial_jtag_int_clr_reg_t serial_jtag_int_clr;
volatile usb_serial_jtag_conf0_reg_t serial_jtag_conf0;
volatile usb_serial_jtag_test_reg_t serial_jtag_test;
volatile usb_serial_jtag_jfifo_st_reg_t serial_jtag_jfifo_st;
volatile usb_serial_jtag_fram_num_reg_t serial_jtag_fram_num;
volatile usb_serial_jtag_in_ep0_st_reg_t serial_jtag_in_ep0_st;
volatile usb_serial_jtag_in_ep1_st_reg_t serial_jtag_in_ep1_st;
volatile usb_serial_jtag_in_ep2_st_reg_t serial_jtag_in_ep2_st;
volatile usb_serial_jtag_in_ep3_st_reg_t serial_jtag_in_ep3_st;
volatile usb_serial_jtag_out_ep0_st_reg_t serial_jtag_out_ep0_st;
volatile usb_serial_jtag_out_ep1_st_reg_t serial_jtag_out_ep1_st;
volatile usb_serial_jtag_out_ep2_st_reg_t serial_jtag_out_ep2_st;
volatile usb_serial_jtag_misc_conf_reg_t serial_jtag_misc_conf;
volatile usb_serial_jtag_mem_conf_reg_t serial_jtag_mem_conf;
volatile usb_serial_jtag_chip_rst_reg_t serial_jtag_chip_rst;
volatile usb_serial_jtag_set_line_code_w0_reg_t serial_jtag_set_line_code_w0;
volatile usb_serial_jtag_set_line_code_w1_reg_t serial_jtag_set_line_code_w1;
volatile usb_serial_jtag_get_line_code_w0_reg_t serial_jtag_get_line_code_w0;
volatile usb_serial_jtag_get_line_code_w1_reg_t serial_jtag_get_line_code_w1;
volatile usb_serial_jtag_config_update_reg_t serial_jtag_config_update;
volatile usb_serial_jtag_ser_afifo_config_reg_t serial_jtag_ser_afifo_config;
volatile usb_serial_jtag_bus_reset_st_reg_t serial_jtag_bus_reset_st;
volatile usb_serial_jtag_serial_ep_timeout0_reg_t serial_jtag_serial_ep_timeout0;
volatile usb_serial_jtag_serial_ep_timeout1_reg_t serial_jtag_serial_ep_timeout1;
uint32_t reserved_074[3];
volatile usb_serial_jtag_date_reg_t serial_jtag_date;
} usb_dev_t;
extern usb_dev_t USB_SERIAL_JTAG;
#ifndef __cplusplus
_Static_assert(sizeof(usb_dev_t) == 0x84, "Invalid size of usb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/usb_wrap_reg.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
/** USB_WRAP_OTG_CONF_REG register
* USB wrapper configuration registers.
*/
#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_BASE + 0x0)
/** USB_WRAP_SRP_SESSEND_OVERRIDE : R/W; bitpos: [0]; default: 0;
* This bit is used to enable the software over-ride of srp session end signal. 1'b0:
* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
* software.
*/
#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (USB_WRAP_SRP_SESSEND_OVERRIDE_V << USB_WRAP_SRP_SESSEND_OVERRIDE_S)
#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x00000001U
#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0
/** USB_WRAP_SRP_SESSEND_VALUE : R/W; bitpos: [1]; default: 0;
* Software over-ride value of srp session end signal.
*/
#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1))
#define USB_WRAP_SRP_SESSEND_VALUE_M (USB_WRAP_SRP_SESSEND_VALUE_V << USB_WRAP_SRP_SESSEND_VALUE_S)
#define USB_WRAP_SRP_SESSEND_VALUE_V 0x00000001U
#define USB_WRAP_SRP_SESSEND_VALUE_S 1
/** USB_WRAP_PHY_SEL : R/W; bitpos: [2]; default: 0;
* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
*/
#define USB_WRAP_PHY_SEL (BIT(2))
#define USB_WRAP_PHY_SEL_M (USB_WRAP_PHY_SEL_V << USB_WRAP_PHY_SEL_S)
#define USB_WRAP_PHY_SEL_V 0x00000001U
#define USB_WRAP_PHY_SEL_S 2
/** USB_WRAP_DBNCE_FLTR_BYPASS : R/W; bitpos: [4]; default: 0;
* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
*/
#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4))
#define USB_WRAP_DBNCE_FLTR_BYPASS_M (USB_WRAP_DBNCE_FLTR_BYPASS_V << USB_WRAP_DBNCE_FLTR_BYPASS_S)
#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x00000001U
#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4
/** USB_WRAP_EXCHG_PINS_OVERRIDE : R/W; bitpos: [5]; default: 0;
* Enable software controlle USB D+ D- exchange
*/
#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5))
#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (USB_WRAP_EXCHG_PINS_OVERRIDE_V << USB_WRAP_EXCHG_PINS_OVERRIDE_S)
#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x00000001U
#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5
/** USB_WRAP_EXCHG_PINS : R/W; bitpos: [6]; default: 0;
* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
*/
#define USB_WRAP_EXCHG_PINS (BIT(6))
#define USB_WRAP_EXCHG_PINS_M (USB_WRAP_EXCHG_PINS_V << USB_WRAP_EXCHG_PINS_S)
#define USB_WRAP_EXCHG_PINS_V 0x00000001U
#define USB_WRAP_EXCHG_PINS_S 6
/** USB_WRAP_VREFH : R/W; bitpos: [8:7]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV.
*/
#define USB_WRAP_VREFH 0x00000003U
#define USB_WRAP_VREFH_M (USB_WRAP_VREFH_V << USB_WRAP_VREFH_S)
#define USB_WRAP_VREFH_V 0x00000003U
#define USB_WRAP_VREFH_S 7
/** USB_WRAP_VREFL : R/W; bitpos: [10:9]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
*/
#define USB_WRAP_VREFL 0x00000003U
#define USB_WRAP_VREFL_M (USB_WRAP_VREFL_V << USB_WRAP_VREFL_S)
#define USB_WRAP_VREFL_V 0x00000003U
#define USB_WRAP_VREFL_S 9
/** USB_WRAP_VREF_OVERRIDE : R/W; bitpos: [11]; default: 0;
* Enable software controlle input threshold.
*/
#define USB_WRAP_VREF_OVERRIDE (BIT(11))
#define USB_WRAP_VREF_OVERRIDE_M (USB_WRAP_VREF_OVERRIDE_V << USB_WRAP_VREF_OVERRIDE_S)
#define USB_WRAP_VREF_OVERRIDE_V 0x00000001U
#define USB_WRAP_VREF_OVERRIDE_S 11
/** USB_WRAP_PAD_PULL_OVERRIDE : R/W; bitpos: [12]; default: 0;
* Enable software controlle USB D+ D- pullup pulldown.
*/
#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12))
#define USB_WRAP_PAD_PULL_OVERRIDE_M (USB_WRAP_PAD_PULL_OVERRIDE_V << USB_WRAP_PAD_PULL_OVERRIDE_S)
#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x00000001U
#define USB_WRAP_PAD_PULL_OVERRIDE_S 12
/** USB_WRAP_DP_PULLUP : R/W; bitpos: [13]; default: 0;
* Controlle USB D+ pullup.
*/
#define USB_WRAP_DP_PULLUP (BIT(13))
#define USB_WRAP_DP_PULLUP_M (USB_WRAP_DP_PULLUP_V << USB_WRAP_DP_PULLUP_S)
#define USB_WRAP_DP_PULLUP_V 0x00000001U
#define USB_WRAP_DP_PULLUP_S 13
/** USB_WRAP_DP_PULLDOWN : R/W; bitpos: [14]; default: 0;
* Controlle USB D+ pulldown.
*/
#define USB_WRAP_DP_PULLDOWN (BIT(14))
#define USB_WRAP_DP_PULLDOWN_M (USB_WRAP_DP_PULLDOWN_V << USB_WRAP_DP_PULLDOWN_S)
#define USB_WRAP_DP_PULLDOWN_V 0x00000001U
#define USB_WRAP_DP_PULLDOWN_S 14
/** USB_WRAP_DM_PULLUP : R/W; bitpos: [15]; default: 0;
* Controlle USB D+ pullup.
*/
#define USB_WRAP_DM_PULLUP (BIT(15))
#define USB_WRAP_DM_PULLUP_M (USB_WRAP_DM_PULLUP_V << USB_WRAP_DM_PULLUP_S)
#define USB_WRAP_DM_PULLUP_V 0x00000001U
#define USB_WRAP_DM_PULLUP_S 15
/** USB_WRAP_DM_PULLDOWN : R/W; bitpos: [16]; default: 0;
* Controlle USB D+ pulldown.
*/
#define USB_WRAP_DM_PULLDOWN (BIT(16))
#define USB_WRAP_DM_PULLDOWN_M (USB_WRAP_DM_PULLDOWN_V << USB_WRAP_DM_PULLDOWN_S)
#define USB_WRAP_DM_PULLDOWN_V 0x00000001U
#define USB_WRAP_DM_PULLDOWN_S 16
/** USB_WRAP_PULLUP_VALUE : R/W; bitpos: [17]; default: 0;
* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
*/
#define USB_WRAP_PULLUP_VALUE (BIT(17))
#define USB_WRAP_PULLUP_VALUE_M (USB_WRAP_PULLUP_VALUE_V << USB_WRAP_PULLUP_VALUE_S)
#define USB_WRAP_PULLUP_VALUE_V 0x00000001U
#define USB_WRAP_PULLUP_VALUE_S 17
/** USB_WRAP_USB_PAD_ENABLE : R/W; bitpos: [18]; default: 0;
* Enable USB pad function.
*/
#define USB_WRAP_USB_PAD_ENABLE (BIT(18))
#define USB_WRAP_USB_PAD_ENABLE_M (USB_WRAP_USB_PAD_ENABLE_V << USB_WRAP_USB_PAD_ENABLE_S)
#define USB_WRAP_USB_PAD_ENABLE_V 0x00000001U
#define USB_WRAP_USB_PAD_ENABLE_S 18
/** USB_WRAP_AHB_CLK_FORCE_ON : R/W; bitpos: [19]; default: 0;
* Force ahb clock always on.
*/
#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19))
#define USB_WRAP_AHB_CLK_FORCE_ON_M (USB_WRAP_AHB_CLK_FORCE_ON_V << USB_WRAP_AHB_CLK_FORCE_ON_S)
#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x00000001U
#define USB_WRAP_AHB_CLK_FORCE_ON_S 19
/** USB_WRAP_PHY_CLK_FORCE_ON : R/W; bitpos: [20]; default: 1;
* Force phy clock always on.
*/
#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20))
#define USB_WRAP_PHY_CLK_FORCE_ON_M (USB_WRAP_PHY_CLK_FORCE_ON_V << USB_WRAP_PHY_CLK_FORCE_ON_S)
#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x00000001U
#define USB_WRAP_PHY_CLK_FORCE_ON_S 20
/** USB_WRAP_CLK_EN : R/W; bitpos: [31]; default: 0;
* Disable auto clock gating of CSR registers.
*/
#define USB_WRAP_CLK_EN (BIT(31))
#define USB_WRAP_CLK_EN_M (USB_WRAP_CLK_EN_V << USB_WRAP_CLK_EN_S)
#define USB_WRAP_CLK_EN_V 0x00000001U
#define USB_WRAP_CLK_EN_S 31
/** USB_WRAP_DATE_REG register
* Date register.
*/
#define USB_WRAP_DATE_REG (DR_REG_USB_BASE + 0x3fc)
/** USB_WRAP_USB_WRAP_DATE : R/W; bitpos: [31:0]; default: 37761536;
* Date register.
*/
#define USB_WRAP_USB_WRAP_DATE 0xFFFFFFFFU
#define USB_WRAP_USB_WRAP_DATE_M (USB_WRAP_USB_WRAP_DATE_V << USB_WRAP_USB_WRAP_DATE_S)
#define USB_WRAP_USB_WRAP_DATE_V 0xFFFFFFFFU
#define USB_WRAP_USB_WRAP_DATE_S 0
#ifdef __cplusplus
}
#endif

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components/soc/esp32h4/register/soc/usb_wrap_struct.h Normal file
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/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: USB wrapper registers. */
/** Type of wrap_otg_conf register
* USB wrapper configuration registers.
*/
typedef union {
struct {
/** wrap_srp_sessend_override : R/W; bitpos: [0]; default: 0;
* This bit is used to enable the software over-ride of srp session end signal. 1'b0:
* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
* software.
*/
uint32_t wrap_srp_sessend_override:1;
/** wrap_srp_sessend_value : R/W; bitpos: [1]; default: 0;
* Software over-ride value of srp session end signal.
*/
uint32_t wrap_srp_sessend_value:1;
/** wrap_phy_sel : R/W; bitpos: [2]; default: 0;
* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
*/
uint32_t wrap_phy_sel:1;
uint32_t reserved_3:1;
/** wrap_dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
*/
uint32_t wrap_dbnce_fltr_bypass:1;
/** wrap_exchg_pins_override : R/W; bitpos: [5]; default: 0;
* Enable software controlle USB D+ D- exchange
*/
uint32_t wrap_exchg_pins_override:1;
/** wrap_exchg_pins : R/W; bitpos: [6]; default: 0;
* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
*/
uint32_t wrap_exchg_pins:1;
/** wrap_vrefh : R/W; bitpos: [8:7]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV.
*/
uint32_t wrap_vrefh:2;
/** wrap_vrefl : R/W; bitpos: [10:9]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
*/
uint32_t wrap_vrefl:2;
/** wrap_vref_override : R/W; bitpos: [11]; default: 0;
* Enable software controlle input threshold.
*/
uint32_t wrap_vref_override:1;
/** wrap_pad_pull_override : R/W; bitpos: [12]; default: 0;
* Enable software controlle USB D+ D- pullup pulldown.
*/
uint32_t wrap_pad_pull_override:1;
/** wrap_dp_pullup : R/W; bitpos: [13]; default: 0;
* Controlle USB D+ pullup.
*/
uint32_t wrap_dp_pullup:1;
/** wrap_dp_pulldown : R/W; bitpos: [14]; default: 0;
* Controlle USB D+ pulldown.
*/
uint32_t wrap_dp_pulldown:1;
/** wrap_dm_pullup : R/W; bitpos: [15]; default: 0;
* Controlle USB D+ pullup.
*/
uint32_t wrap_dm_pullup:1;
/** wrap_dm_pulldown : R/W; bitpos: [16]; default: 0;
* Controlle USB D+ pulldown.
*/
uint32_t wrap_dm_pulldown:1;
/** wrap_pullup_value : R/W; bitpos: [17]; default: 0;
* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
*/
uint32_t wrap_pullup_value:1;
/** wrap_usb_pad_enable : R/W; bitpos: [18]; default: 0;
* Enable USB pad function.
*/
uint32_t wrap_usb_pad_enable:1;
/** wrap_ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
* Force ahb clock always on.
*/
uint32_t wrap_ahb_clk_force_on:1;
/** wrap_phy_clk_force_on : R/W; bitpos: [20]; default: 1;
* Force phy clock always on.
*/
uint32_t wrap_phy_clk_force_on:1;
uint32_t reserved_21:10;
/** wrap_clk_en : R/W; bitpos: [31]; default: 0;
* Disable auto clock gating of CSR registers.
*/
uint32_t wrap_clk_en:1;
};
uint32_t val;
} usb_wrap_otg_conf_reg_t;
/** Type of wrap_date register
* Date register.
*/
typedef union {
struct {
/** wrap_usb_wrap_date : R/W; bitpos: [31:0]; default: 37761536;
* Date register.
*/
uint32_t wrap_usb_wrap_date:32;
};
uint32_t val;
} usb_wrap_date_reg_t;
typedef struct {
volatile usb_wrap_otg_conf_reg_t wrap_otg_conf;
uint32_t reserved_004[254];
volatile usb_wrap_date_reg_t wrap_date;
} usb_dev_t;
#ifndef __cplusplus
_Static_assert(sizeof(usb_dev_t) == 0x400, "Invalid size of usb_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif