mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-31 11:17:20 +02:00
feat(i2s): support i2s on esp32-h4
This commit is contained in:
laokaiyao
@ -1,2 +1,2 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
@ -1,12 +1,15 @@
|
||||
set(srcs "test_app_main.c"
|
||||
"test_i2s.c"
|
||||
"test_i2s_iram.c"
|
||||
"test_i2s_sleep.c")
|
||||
"test_i2s_iram.c")
|
||||
|
||||
if(CONFIG_SOC_I2S_SUPPORTS_ETM AND CONFIG_SOC_GPIO_SUPPORT_ETM)
|
||||
set(srcs ${srcs} "test_i2s_etm.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_LIGHT_SLEEP_SUPPORTED)
|
||||
list(APPEND srcs "test_i2s_sleep.c")
|
||||
endif()
|
||||
|
||||
idf_component_register(SRCS ${srcs}
|
||||
PRIV_REQUIRES unity esp_driver_pcnt spi_flash
|
||||
esp_driver_gpio esp_driver_i2s esp_driver_uart esp_psram
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
|
||||
1349
components/hal/esp32h4/include/hal/i2s_ll.h
Normal file
1349
components/hal/esp32h4/include/hal/i2s_ll.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -233,6 +233,9 @@ typedef enum {
|
||||
typedef enum {
|
||||
I2S_ETM_TASK_START, /*!< Start the I2S channel */
|
||||
I2S_ETM_TASK_STOP, /*!< Stop the I2S channel */
|
||||
#if SOC_I2S_SUPPORTS_ETM_SYNC
|
||||
I2S_ETM_TASK_SYNC_CHECK, /*!< Stop the I2S channel */
|
||||
#endif
|
||||
I2S_ETM_TASK_MAX, /*!< Maximum number of tasks */
|
||||
} i2s_etm_task_type_t;
|
||||
|
||||
|
||||
34
components/soc/esp32h4/i2s_periph.c
Normal file
34
components/soc/esp32h4/i2s_periph.c
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include "soc/i2s_periph.h"
|
||||
#include "soc/i2s_reg.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
|
||||
*/
|
||||
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
|
||||
{
|
||||
.mck_out_sig = I2S_MCLK_OUT_IDX,
|
||||
.mck_in_sig = I2S_MCLK_IN_IDX,
|
||||
|
||||
.m_tx_bck_sig = I2SO_BCK_OUT_IDX,
|
||||
.m_rx_bck_sig = I2SI_BCK_OUT_IDX,
|
||||
.m_tx_ws_sig = I2SO_WS_OUT_IDX,
|
||||
.m_rx_ws_sig = I2SI_WS_OUT_IDX,
|
||||
|
||||
.s_tx_bck_sig = I2SO_BCK_IN_IDX,
|
||||
.s_rx_bck_sig = I2SI_BCK_IN_IDX,
|
||||
.s_tx_ws_sig = I2SO_WS_IN_IDX,
|
||||
.s_rx_ws_sig = I2SI_WS_IN_IDX,
|
||||
|
||||
.data_out_sig = I2SO_SD_OUT_IDX,
|
||||
.data_in_sig = I2SI_SD_IN_IDX,
|
||||
|
||||
.irq = ETS_I2S_INTR_SOURCE,
|
||||
}
|
||||
};
|
||||
@ -31,6 +31,10 @@ config SOC_EFUSE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
@ -291,6 +295,70 @@ config SOC_I2C_SUPPORT_SLEEP_RETENTION
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_NUM
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_I2S_HW_VERSION_2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_ETM_SYNC
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PLL_F96M
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PLL_F64M
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PCM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PDM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PDM_TX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PCM2PDM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_PDM_RX
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_SUPPORTS_TX_SYNC_CNT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_PDM_MAX_TX_LINES
|
||||
int
|
||||
default 2
|
||||
|
||||
config SOC_I2S_PDM_MAX_RX_LINES
|
||||
int
|
||||
default 1
|
||||
|
||||
config SOC_I2S_SUPPORTS_TDM
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_I2S_TDM_FULL_DATA_WIDTH
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LEDC_CHANNEL_NUM
|
||||
int
|
||||
default 6
|
||||
|
||||
@ -299,6 +299,24 @@ typedef enum {
|
||||
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
|
||||
} soc_periph_i2c_clk_src_t;
|
||||
|
||||
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
|
||||
|
||||
/**
|
||||
* @brief Array initializer for all supported clock sources of I2S
|
||||
*/
|
||||
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
|
||||
|
||||
/**
|
||||
* @brief I2S clock source enum
|
||||
*/
|
||||
typedef enum {
|
||||
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
|
||||
I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
|
||||
// I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
|
||||
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
|
||||
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
|
||||
} soc_periph_i2s_clk_src_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -54,7 +54,7 @@
|
||||
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268
|
||||
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
|
||||
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
|
||||
// #define SOC_I2S_SUPPORTED 1 // TODO: [ESP32H4] IDF-12385
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
// #define SOC_RMT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12402
|
||||
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12348
|
||||
// #define SOC_GPSPI_SUPPORTED 1 // TODO: [ESP32H4] IDF-12362 IDF-12364 IDF-12366
|
||||
@ -268,15 +268,26 @@
|
||||
#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
|
||||
|
||||
/*-------------------------- I2S CAPS ----------------------------------------*/
|
||||
// #define SOC_I2S_NUM (1U)
|
||||
// #define SOC_I2S_HW_VERSION_2 (1)
|
||||
// #define SOC_I2S_SUPPORTS_XTAL (1)
|
||||
// #define SOC_I2S_SUPPORTS_PLL_F160M (1)
|
||||
// #define SOC_I2S_SUPPORTS_PCM (1)
|
||||
// #define SOC_I2S_SUPPORTS_PDM (1)
|
||||
// #define SOC_I2S_SUPPORTS_PDM_TX (1)
|
||||
// #define SOC_I2S_PDM_MAX_TX_LINES (2)
|
||||
// #define SOC_I2S_SUPPORTS_TDM (1)
|
||||
#define SOC_I2S_NUM (1U)
|
||||
#define SOC_I2S_HW_VERSION_2 (1)
|
||||
// #define SOC_I2S_SUPPORTS_ETM (1)
|
||||
#define SOC_I2S_SUPPORTS_ETM_SYNC (1)
|
||||
#define SOC_I2S_SUPPORTS_XTAL (1)
|
||||
#define SOC_I2S_SUPPORTS_PLL_F96M (1)
|
||||
#define SOC_I2S_SUPPORTS_PLL_F64M (1)
|
||||
#define SOC_I2S_SUPPORTS_PCM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM (1)
|
||||
#define SOC_I2S_SUPPORTS_PDM_TX (1) // Support to output raw PDM format data
|
||||
#define SOC_I2S_SUPPORTS_PCM2PDM (1) // Support to write PCM format but output PDM format data with the help of PCM to PDM filter
|
||||
#define SOC_I2S_SUPPORTS_PDM_RX (1) // Support to input raw PDM format data
|
||||
#define SOC_I2S_SUPPORTS_TX_SYNC_CNT (1)
|
||||
#define SOC_I2S_PDM_MAX_TX_LINES (2)
|
||||
#define SOC_I2S_PDM_MAX_RX_LINES (1U)
|
||||
#define SOC_I2S_SUPPORTS_TDM (1)
|
||||
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
|
||||
|
||||
// TODO: [ESP32H4] IDF-12386
|
||||
// #define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
|
||||
|
||||
/*-------------------------- LEDC CAPS ---------------------------------------*/
|
||||
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
|
||||
|
||||
@ -573,173 +573,6 @@ extern "C" {
|
||||
#define I2S_TX_TDM_CHAN_BITS_V 0x0000001FU
|
||||
#define I2S_TX_TDM_CHAN_BITS_S 27
|
||||
|
||||
/** I2S_RX_RECOMB_CTRL_REG register
|
||||
* I2S RX configure register 1
|
||||
*/
|
||||
#define I2S_RX_RECOMB_CTRL_REG (DR_REG_I2S_BASE + 0x30)
|
||||
/** I2S_RX_RECOMB_EN : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable i2s rx data recombination.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_EN (BIT(0))
|
||||
#define I2S_RX_RECOMB_EN_M (I2S_RX_RECOMB_EN_V << I2S_RX_RECOMB_EN_S)
|
||||
#define I2S_RX_RECOMB_EN_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_EN_S 0
|
||||
/** I2S_RX_RECOMB_EXT_CH_NUM : R/W; bitpos: [2:1]; default: 0;
|
||||
* The channel number that i2s will extract the data into.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_EXT_CH_NUM 0x00000003U
|
||||
#define I2S_RX_RECOMB_EXT_CH_NUM_M (I2S_RX_RECOMB_EXT_CH_NUM_V << I2S_RX_RECOMB_EXT_CH_NUM_S)
|
||||
#define I2S_RX_RECOMB_EXT_CH_NUM_V 0x00000003U
|
||||
#define I2S_RX_RECOMB_EXT_CH_NUM_S 1
|
||||
/** I2S_RX_RECOMB_UPDATE : WT; bitpos: [31]; default: 0;
|
||||
* Set this bit to update i2s data recombination configuration, must be performed
|
||||
* after changing the config of any recombined-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_UPDATE (BIT(31))
|
||||
#define I2S_RX_RECOMB_UPDATE_M (I2S_RX_RECOMB_UPDATE_V << I2S_RX_RECOMB_UPDATE_S)
|
||||
#define I2S_RX_RECOMB_UPDATE_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_UPDATE_S 31
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH0_REG register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH0_REG (DR_REG_I2S_BASE + 0x34)
|
||||
/** I2S_RX_RECOMB_DMA_CH0_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH0_VALID (BIT(0))
|
||||
#define I2S_RX_RECOMB_DMA_CH0_VALID_M (I2S_RX_RECOMB_DMA_CH0_VALID_V << I2S_RX_RECOMB_DMA_CH0_VALID_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH0_VALID_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_DMA_CH0_VALID_S 0
|
||||
/** I2S_RX_RECOMB_DMA_CH0_STYLE : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH0_STYLE 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_STYLE_M (I2S_RX_RECOMB_DMA_CH0_STYLE_V << I2S_RX_RECOMB_DMA_CH0_STYLE_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH0_STYLE_V 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_STYLE_S 1
|
||||
/** I2S_RX_RECOMB_DMA_CH0_ORDER : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH0_ORDER 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_ORDER_M (I2S_RX_RECOMB_DMA_CH0_ORDER_V << I2S_RX_RECOMB_DMA_CH0_ORDER_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH0_ORDER_V 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_ORDER_S 5
|
||||
/** I2S_RX_RECOMB_DMA_CH0_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH0_EOF_NUM_S 13
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH1_REG register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH1_REG (DR_REG_I2S_BASE + 0x38)
|
||||
/** I2S_RX_RECOMB_DMA_CH1_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH1_VALID (BIT(0))
|
||||
#define I2S_RX_RECOMB_DMA_CH1_VALID_M (I2S_RX_RECOMB_DMA_CH1_VALID_V << I2S_RX_RECOMB_DMA_CH1_VALID_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH1_VALID_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_DMA_CH1_VALID_S 0
|
||||
/** I2S_RX_RECOMB_DMA_CH1_STYLE : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH1_STYLE 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_STYLE_M (I2S_RX_RECOMB_DMA_CH1_STYLE_V << I2S_RX_RECOMB_DMA_CH1_STYLE_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH1_STYLE_V 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_STYLE_S 1
|
||||
/** I2S_RX_RECOMB_DMA_CH1_ORDER : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH1_ORDER 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_ORDER_M (I2S_RX_RECOMB_DMA_CH1_ORDER_V << I2S_RX_RECOMB_DMA_CH1_ORDER_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH1_ORDER_V 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_ORDER_S 5
|
||||
/** I2S_RX_RECOMB_DMA_CH1_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH1_EOF_NUM_S 13
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH2_REG register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH2_REG (DR_REG_I2S_BASE + 0x3c)
|
||||
/** I2S_RX_RECOMB_DMA_CH2_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH2_VALID (BIT(0))
|
||||
#define I2S_RX_RECOMB_DMA_CH2_VALID_M (I2S_RX_RECOMB_DMA_CH2_VALID_V << I2S_RX_RECOMB_DMA_CH2_VALID_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH2_VALID_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_DMA_CH2_VALID_S 0
|
||||
/** I2S_RX_RECOMB_DMA_CH2_STYLE : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH2_STYLE 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_STYLE_M (I2S_RX_RECOMB_DMA_CH2_STYLE_V << I2S_RX_RECOMB_DMA_CH2_STYLE_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH2_STYLE_V 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_STYLE_S 1
|
||||
/** I2S_RX_RECOMB_DMA_CH2_ORDER : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH2_ORDER 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_ORDER_M (I2S_RX_RECOMB_DMA_CH2_ORDER_V << I2S_RX_RECOMB_DMA_CH2_ORDER_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH2_ORDER_V 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_ORDER_S 5
|
||||
/** I2S_RX_RECOMB_DMA_CH2_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH2_EOF_NUM_S 13
|
||||
|
||||
/** I2S_RX_RECOMB_DMA_CH3_REG register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH3_REG (DR_REG_I2S_BASE + 0x40)
|
||||
/** I2S_RX_RECOMB_DMA_CH3_VALID : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH3_VALID (BIT(0))
|
||||
#define I2S_RX_RECOMB_DMA_CH3_VALID_M (I2S_RX_RECOMB_DMA_CH3_VALID_V << I2S_RX_RECOMB_DMA_CH3_VALID_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH3_VALID_V 0x00000001U
|
||||
#define I2S_RX_RECOMB_DMA_CH3_VALID_S 0
|
||||
/** I2S_RX_RECOMB_DMA_CH3_STYLE : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH3_STYLE 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_STYLE_M (I2S_RX_RECOMB_DMA_CH3_STYLE_V << I2S_RX_RECOMB_DMA_CH3_STYLE_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH3_STYLE_V 0x0000000FU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_STYLE_S 1
|
||||
/** I2S_RX_RECOMB_DMA_CH3_ORDER : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH3_ORDER 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_ORDER_M (I2S_RX_RECOMB_DMA_CH3_ORDER_V << I2S_RX_RECOMB_DMA_CH3_ORDER_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH3_ORDER_V 0x000000FFU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_ORDER_S 5
|
||||
/** I2S_RX_RECOMB_DMA_CH3_EOF_NUM : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_M (I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V << I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S)
|
||||
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_V 0x0000FFFFU
|
||||
#define I2S_RX_RECOMB_DMA_CH3_EOF_NUM_S 13
|
||||
|
||||
/** I2S_TX_PCM2PDM_CONF_REG register
|
||||
* I2S TX PCM2PDM configuration register
|
||||
*/
|
||||
@ -857,56 +690,6 @@ extern "C" {
|
||||
#define I2S_TX_IIR_HP_MULT12_0_V 0x00000007U
|
||||
#define I2S_TX_IIR_HP_MULT12_0_S 23
|
||||
|
||||
/** I2S_RX_PDM2PCM_CONF_REG register
|
||||
* I2S RX configure register
|
||||
*/
|
||||
#define I2S_RX_PDM2PCM_CONF_REG (DR_REG_I2S_BASE + 0x4c)
|
||||
/** I2S_RX_PDM2PCM_EN : R/W; bitpos: [19]; default: 0;
|
||||
* 1: Enable PDM2PCM RX mode. 0: DIsable.
|
||||
*/
|
||||
#define I2S_RX_PDM2PCM_EN (BIT(19))
|
||||
#define I2S_RX_PDM2PCM_EN_M (I2S_RX_PDM2PCM_EN_V << I2S_RX_PDM2PCM_EN_S)
|
||||
#define I2S_RX_PDM2PCM_EN_V 0x00000001U
|
||||
#define I2S_RX_PDM2PCM_EN_S 19
|
||||
/** I2S_RX_PDM_SINC_DSR_16_EN : R/W; bitpos: [20]; default: 0;
|
||||
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
|
||||
* sampling rate is 128. 0: down sampling rate is 64.
|
||||
*/
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(20))
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_M (I2S_RX_PDM_SINC_DSR_16_EN_V << I2S_RX_PDM_SINC_DSR_16_EN_S)
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x00000001U
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_S 20
|
||||
/** I2S_RX_PDM2PCM_AMPLIFY_NUM : R/W; bitpos: [24:21]; default: 1;
|
||||
* Configure PDM RX amplify number.
|
||||
*/
|
||||
#define I2S_RX_PDM2PCM_AMPLIFY_NUM 0x0000000FU
|
||||
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_M (I2S_RX_PDM2PCM_AMPLIFY_NUM_V << I2S_RX_PDM2PCM_AMPLIFY_NUM_S)
|
||||
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_V 0x0000000FU
|
||||
#define I2S_RX_PDM2PCM_AMPLIFY_NUM_S 21
|
||||
/** I2S_RX_PDM_HP_BYPASS : R/W; bitpos: [25]; default: 0;
|
||||
* I2S PDM RX bypass hp filter or not.
|
||||
*/
|
||||
#define I2S_RX_PDM_HP_BYPASS (BIT(25))
|
||||
#define I2S_RX_PDM_HP_BYPASS_M (I2S_RX_PDM_HP_BYPASS_V << I2S_RX_PDM_HP_BYPASS_S)
|
||||
#define I2S_RX_PDM_HP_BYPASS_V 0x00000001U
|
||||
#define I2S_RX_PDM_HP_BYPASS_S 25
|
||||
/** I2S_RX_IIR_HP_MULT12_5 : R/W; bitpos: [28:26]; default: 6;
|
||||
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
|
||||
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
|
||||
*/
|
||||
#define I2S_RX_IIR_HP_MULT12_5 0x00000007U
|
||||
#define I2S_RX_IIR_HP_MULT12_5_M (I2S_RX_IIR_HP_MULT12_5_V << I2S_RX_IIR_HP_MULT12_5_S)
|
||||
#define I2S_RX_IIR_HP_MULT12_5_V 0x00000007U
|
||||
#define I2S_RX_IIR_HP_MULT12_5_S 26
|
||||
/** I2S_RX_IIR_HP_MULT12_0 : R/W; bitpos: [31:29]; default: 7;
|
||||
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
|
||||
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
|
||||
*/
|
||||
#define I2S_RX_IIR_HP_MULT12_0 0x00000007U
|
||||
#define I2S_RX_IIR_HP_MULT12_0_M (I2S_RX_IIR_HP_MULT12_0_V << I2S_RX_IIR_HP_MULT12_0_S)
|
||||
#define I2S_RX_IIR_HP_MULT12_0_V 0x00000007U
|
||||
#define I2S_RX_IIR_HP_MULT12_0_S 29
|
||||
|
||||
/** I2S_RX_TDM_CTRL_REG register
|
||||
* I2S TX TDM mode control register
|
||||
*/
|
||||
|
||||
@ -260,178 +260,6 @@ typedef union {
|
||||
uint32_t val;
|
||||
} i2s_rx_conf1_reg_t;
|
||||
|
||||
/** Type of rx_recomb_ctrl register
|
||||
* I2S RX configure register 1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_en : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable i2s rx data recombination.
|
||||
*/
|
||||
uint32_t rx_recomb_en:1;
|
||||
/** rx_recomb_ext_ch_num : R/W; bitpos: [2:1]; default: 0;
|
||||
* The channel number that i2s will extract the data into.
|
||||
*/
|
||||
uint32_t rx_recomb_ext_ch_num:2;
|
||||
uint32_t reserved_3:28;
|
||||
/** rx_recomb_update : WT; bitpos: [31]; default: 0;
|
||||
* Set this bit to update i2s data recombination configuration, must be performed
|
||||
* after changing the config of any recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_update:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_ctrl_reg_t;
|
||||
|
||||
/** Type of rx_recomb_dma_ch0 register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch0_valid : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch0_valid:1;
|
||||
/** rx_recomb_dma_ch0_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch0_style:4;
|
||||
/** rx_recomb_dma_ch0_order : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch0_order:8;
|
||||
/** rx_recomb_dma_ch0_eof_num : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch0_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch0_reg_t;
|
||||
|
||||
/** Type of rx_recomb_dma_ch1 register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch1_valid : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_valid:1;
|
||||
/** rx_recomb_dma_ch1_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_style:4;
|
||||
/** rx_recomb_dma_ch1_order : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_order:8;
|
||||
/** rx_recomb_dma_ch1_eof_num : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch1_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch1_reg_t;
|
||||
|
||||
/** Type of rx_recomb_dma_ch2 register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch2_valid : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_valid:1;
|
||||
/** rx_recomb_dma_ch2_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_style:4;
|
||||
/** rx_recomb_dma_ch2_order : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_order:8;
|
||||
/** rx_recomb_dma_ch2_eof_num : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch2_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch2_reg_t;
|
||||
|
||||
/** Type of rx_recomb_dma_ch3 register
|
||||
* I2S RX recombined-dma-channel configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rx_recomb_dma_ch3_valid : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to enable the adc-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_valid:1;
|
||||
/** rx_recomb_dma_ch3_style : R/W; bitpos: [4:1]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel style. If choose to use i2s
|
||||
* extracted ch 1&3 in 4 channels, the style should be: 6'b1010.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_style:4;
|
||||
/** rx_recomb_dma_ch3_order : R/W; bitpos: [12:5]; default: 0;
|
||||
* Set this field to set the recombined-dma-channel order. If choose to use the order
|
||||
* ch3 -> ch1, the order should be: 8'd7 = {2'd0,2'd0,2'd1,2'd3}.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_order:8;
|
||||
/** rx_recomb_dma_ch3_eof_num : R/W; bitpos: [28:13]; default: 0;
|
||||
* Set this field to set the receive eof byte length of the recombined-dma-channel.
|
||||
*/
|
||||
uint32_t rx_recomb_dma_ch3_eof_num:16;
|
||||
uint32_t reserved_29:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_recomb_dma_ch3_reg_t;
|
||||
|
||||
/** Type of rx_pdm2pcm_conf register
|
||||
* I2S RX configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:19;
|
||||
/** rx_pdm2pcm_en : R/W; bitpos: [19]; default: 0;
|
||||
* 1: Enable PDM2PCM RX mode. 0: DIsable.
|
||||
*/
|
||||
uint32_t rx_pdm2pcm_en:1;
|
||||
/** rx_pdm_sinc_dsr_16_en : R/W; bitpos: [20]; default: 0;
|
||||
* Configure the down sampling rate of PDM RX filter group1 module. 1: The down
|
||||
* sampling rate is 128. 0: down sampling rate is 64.
|
||||
*/
|
||||
uint32_t rx_pdm_sinc_dsr_16_en:1;
|
||||
/** rx_pdm2pcm_amplify_num : R/W; bitpos: [24:21]; default: 1;
|
||||
* Configure PDM RX amplify number.
|
||||
*/
|
||||
uint32_t rx_pdm2pcm_amplify_num:4;
|
||||
/** rx_pdm_hp_bypass : R/W; bitpos: [25]; default: 0;
|
||||
* I2S PDM RX bypass hp filter or not.
|
||||
*/
|
||||
uint32_t rx_pdm_hp_bypass:1;
|
||||
/** rx_iir_hp_mult12_5 : R/W; bitpos: [28:26]; default: 6;
|
||||
* The fourth parameter of PDM RX IIR_HP filter stage 2 is (504 +
|
||||
* LP_I2S_RX_IIR_HP_MULT12_5[2:0])
|
||||
*/
|
||||
uint32_t rx_iir_hp_mult12_5:3;
|
||||
/** rx_iir_hp_mult12_0 : R/W; bitpos: [31:29]; default: 7;
|
||||
* The fourth parameter of PDM RX IIR_HP filter stage 1 is (504 +
|
||||
* LP_I2S_RX_IIR_HP_MULT12_0[2:0])
|
||||
*/
|
||||
uint32_t rx_iir_hp_mult12_0:3;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rx_pdm2pcm_conf_reg_t;
|
||||
|
||||
/** Type of rx_tdm_ctrl register
|
||||
* I2S TX TDM mode control register
|
||||
*/
|
||||
@ -526,7 +354,7 @@ typedef union {
|
||||
uint32_t val;
|
||||
} i2s_rx_tdm_ctrl_reg_t;
|
||||
|
||||
/** Type of rxeof_num register
|
||||
/** Type of rx_eof_num register
|
||||
* I2S RX data number control register.
|
||||
*/
|
||||
typedef union {
|
||||
@ -539,7 +367,7 @@ typedef union {
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2s_rxeof_num_reg_t;
|
||||
} i2s_rx_eof_num_reg_t;
|
||||
|
||||
|
||||
/** Group: TX Control and configuration registers */
|
||||
@ -1225,21 +1053,17 @@ typedef struct {
|
||||
volatile i2s_tx_conf_reg_t tx_conf;
|
||||
volatile i2s_rx_conf1_reg_t rx_conf1;
|
||||
volatile i2s_tx_conf1_reg_t tx_conf1;
|
||||
volatile i2s_rx_recomb_ctrl_reg_t rx_recomb_ctrl;
|
||||
volatile i2s_rx_recomb_dma_ch0_reg_t rx_recomb_dma_ch0;
|
||||
volatile i2s_rx_recomb_dma_ch1_reg_t rx_recomb_dma_ch1;
|
||||
volatile i2s_rx_recomb_dma_ch2_reg_t rx_recomb_dma_ch2;
|
||||
volatile i2s_rx_recomb_dma_ch3_reg_t rx_recomb_dma_ch3;
|
||||
uint32_t reserved_030[5];
|
||||
volatile i2s_tx_pcm2pdm_conf_reg_t tx_pcm2pdm_conf;
|
||||
volatile i2s_tx_pcm2pdm_conf1_reg_t tx_pcm2pdm_conf1;
|
||||
volatile i2s_rx_pdm2pcm_conf_reg_t rx_pdm2pcm_conf;
|
||||
uint32_t reserved_04c;
|
||||
volatile i2s_rx_tdm_ctrl_reg_t rx_tdm_ctrl;
|
||||
volatile i2s_tx_tdm_ctrl_reg_t tx_tdm_ctrl;
|
||||
volatile i2s_rx_timing_reg_t rx_timing;
|
||||
volatile i2s_tx_timing_reg_t tx_timing;
|
||||
volatile i2s_lc_hung_conf_reg_t lc_hung_conf;
|
||||
volatile i2s_rxeof_num_reg_t rxeof_num;
|
||||
volatile i2s_conf_sigle_data_reg_t conf_sigle_data;
|
||||
volatile i2s_rx_eof_num_reg_t rx_eof_num;
|
||||
volatile i2s_conf_single_data_reg_t conf_single_data;
|
||||
volatile i2s_state_reg_t state;
|
||||
volatile i2s_etm_conf_reg_t etm_conf;
|
||||
volatile i2s_ideal_cnt_reg_t ideal_cnt;
|
||||
|
||||
@ -728,8 +728,8 @@ typedef union {
|
||||
/** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
|
||||
* Configures the clock source of I2S TX.
|
||||
* 0 (default): XTAL_CLK
|
||||
* 1: PLL_F240M_CLK
|
||||
* 2: PLL_F160M_CLK
|
||||
* 1: PLL_F96M_CLK
|
||||
* 2: PLL_F64M_CLK
|
||||
* 3: I2S_MCLK_in
|
||||
*/
|
||||
uint32_t i2s_tx_clkm_sel:2;
|
||||
@ -785,8 +785,8 @@ typedef union {
|
||||
/** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0;
|
||||
* Configures the clock source of I2S RX.
|
||||
* 0 (default): XTAL_CLK
|
||||
* 1: PLL_F240M_CLK
|
||||
* 2: PLL_F160M_CLK
|
||||
* 1: PLL_F96M_CLK
|
||||
* 2: PLL_F64M_CLK
|
||||
* 3: I2S_MCLK_in
|
||||
*/
|
||||
uint32_t i2s_rx_clkm_sel:2;
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S Basic PDM Mode Example
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S Basic Standard Mode Example
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
|
||||
| ----------------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S Basic TDM Mode Example
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- | -------- |
|
||||
|
||||
# I2S ES8311 Example
|
||||
|
||||
|
||||
Reference in New Issue
Block a user