mirror of
https://github.com/espressif/esp-idf.git
synced 2025-07-29 18:27:20 +02:00
Merge branch 'feature/adds_efuse_adc_calib_data_v5.3' into 'release/v5.3'
feat(efuse): Adds efuse ADC calib data for P4 C5 C61 (v5.3) See merge request espressif/esp-idf!35119
This commit is contained in:
morris
@ -9,7 +9,7 @@
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#include <assert.h>
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#include "esp_efuse_table.h"
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// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
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// md5_digest_table b26e7466c400977081a142076ef1a5bb
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// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
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// If you want to change some fields, you need to change esp_efuse_table.csv file
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// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
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@ -287,14 +287,102 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
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};
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static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBG,
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};
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static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBG,
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};
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static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS,
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};
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static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
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{EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP,
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};
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static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
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};
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static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMPERATURE_SENSOR,
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};
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static const esp_efuse_desc_t WR_DIS_OCODE[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF,
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};
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static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
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{EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
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};
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@ -648,14 +736,102 @@ static const esp_efuse_desc_t TRIM_P_BIAS[] = {
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{EFUSE_BLK1, 101, 5}, // [] PADC CAL P bias,
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};
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static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = {
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{EFUSE_BLK1, 106, 4}, // [] Active HP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = {
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{EFUSE_BLK1, 110, 4}, // [] Active LP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t LSLP_HP_DBG[] = {
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{EFUSE_BLK1, 114, 2}, // [] LSLP HP DBG of fixed voltage,
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};
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static const esp_efuse_desc_t LSLP_HP_DBIAS[] = {
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{EFUSE_BLK1, 116, 4}, // [] LSLP HP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t DSLP_LP_DBG[] = {
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{EFUSE_BLK1, 120, 4}, // [] DSLP LP DBG of fixed voltage,
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};
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static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
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{EFUSE_BLK1, 124, 5}, // [] DSLP LP DBIAS of fixed voltage,
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};
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static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = {
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{EFUSE_BLK1, 129, 5}, // [] DBIAS gap between LP and HP,
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};
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static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
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{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
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};
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static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
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{EFUSE_BLK2, 128, 9}, // [] Temperature calibration data,
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};
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static const esp_efuse_desc_t OCODE[] = {
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{EFUSE_BLK2, 137, 8}, // [] ADC OCode,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
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{EFUSE_BLK2, 145, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
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{EFUSE_BLK2, 155, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
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{EFUSE_BLK2, 165, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
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{EFUSE_BLK2, 175, 10}, // [] Average initcode of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
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{EFUSE_BLK2, 185, 10}, // [] HI DOUT of ADC1 atten0,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
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{EFUSE_BLK2, 195, 10}, // [] HI DOUT of ADC1 atten1,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
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{EFUSE_BLK2, 205, 10}, // [] HI DOUT of ADC1 atten2,
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};
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static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
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{EFUSE_BLK2, 215, 10}, // [] HI DOUT of ADC1 atten3,
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};
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static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 225, 4}, // [] Gap between ADC1 CH0 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 229, 4}, // [] Gap between ADC1 CH1 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 233, 4}, // [] Gap between ADC1 CH2 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 237, 4}, // [] Gap between ADC1 CH3 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 241, 4}, // [] Gap between ADC1 CH4 and average initcode,
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};
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static const esp_efuse_desc_t ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
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{EFUSE_BLK2, 245, 4}, // [] Gap between ADC1 CH5 and average initcode,
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};
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static const esp_efuse_desc_t USER_DATA[] = {
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{EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data,
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};
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@ -1036,16 +1212,126 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = {
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&WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = {
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&WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = {
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&WR_DIS_LSLP_HP_DBG[0], // [] wr_dis of LSLP_HP_DBG
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = {
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&WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = {
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&WR_DIS_DSLP_LP_DBG[0], // [] wr_dis of DSLP_LP_DBG
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
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&WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = {
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&WR_DIS_LP_HP_DBIAS_VOL_GAP[0], // [] wr_dis of LP_HP_DBIAS_VOL_GAP
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
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&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
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&WR_DIS_TEMPERATURE_SENSOR[0], // [] wr_dis of TEMPERATURE_SENSOR
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
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&WR_DIS_OCODE[0], // [] wr_dis of OCODE
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
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&WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
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&WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
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||||
NULL
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||||
};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
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NULL
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||||
};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
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NULL
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};
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const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
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&WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
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||||
NULL
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||||
};
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||||
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||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
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&WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
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||||
NULL
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||||
@ -1486,16 +1772,126 @@ const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[] = {
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NULL
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||||
};
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||||
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const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = {
|
||||
&ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = {
|
||||
&ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage
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||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = {
|
||||
&LSLP_HP_DBG[0], // [] LSLP HP DBG of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = {
|
||||
&LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = {
|
||||
&DSLP_LP_DBG[0], // [] DSLP LP DBG of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
|
||||
&DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = {
|
||||
&LP_HP_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and HP
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
|
||||
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
|
||||
&TEMPERATURE_SENSOR[0], // [] Temperature calibration data
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
|
||||
&OCODE[0], // [] ADC OCode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
|
||||
&ADC1_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
|
||||
&ADC1_HI_DOUT_ATTEN0[0], // [] HI DOUT of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
|
||||
&ADC1_HI_DOUT_ATTEN1[0], // [] HI DOUT of ADC1 atten1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
|
||||
&ADC1_HI_DOUT_ATTEN2[0], // [] HI DOUT of ADC1 atten2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
|
||||
&ADC1_HI_DOUT_ATTEN3[0], // [] HI DOUT of ADC1 atten3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH4 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH5_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH5 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
|
||||
&USER_DATA[0], // [BLOCK_USR_DATA] User data
|
||||
NULL
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: b09fa417de505238a601eddce188b696
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 287a0ed4951aba84b9571a5f31000275
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
@ -79,8 +79,30 @@ WR_DIS.PA_TRIM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis
|
||||
WR_DIS.TRIM_N_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_N_BIAS
|
||||
WR_DIS.TRIM_P_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_P_BIAS
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
|
||||
WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
|
||||
WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG
|
||||
WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS
|
||||
WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG
|
||||
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
|
||||
WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
|
||||
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -173,8 +195,30 @@ PKG_VERSION, EFUSE_BLK1, 90, 3, [] Packag
|
||||
PA_TRIM_VERSION, EFUSE_BLK1, 93, 3, [] PADC CAL PA trim version
|
||||
TRIM_N_BIAS, EFUSE_BLK1, 96, 5, [] PADC CAL N bias
|
||||
TRIM_P_BIAS, EFUSE_BLK1, 101, 5, [] PADC CAL P bias
|
||||
ACTIVE_HP_DBIAS, EFUSE_BLK1, 106, 4, [] Active HP DBIAS of fixed voltage
|
||||
ACTIVE_LP_DBIAS, EFUSE_BLK1, 110, 4, [] Active LP DBIAS of fixed voltage
|
||||
LSLP_HP_DBG, EFUSE_BLK1, 114, 2, [] LSLP HP DBG of fixed voltage
|
||||
LSLP_HP_DBIAS, EFUSE_BLK1, 116, 4, [] LSLP HP DBIAS of fixed voltage
|
||||
DSLP_LP_DBG, EFUSE_BLK1, 120, 4, [] DSLP LP DBG of fixed voltage
|
||||
DSLP_LP_DBIAS, EFUSE_BLK1, 124, 5, [] DSLP LP DBIAS of fixed voltage
|
||||
LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 129, 5, [] DBIAS gap between LP and HP
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
|
||||
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 145, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 155, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 165, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 175, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] HI DOUT of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] HI DOUT of ADC1 atten1
|
||||
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] HI DOUT of ADC1 atten2
|
||||
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] HI DOUT of ADC1 atten3
|
||||
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] Gap between ADC1 CH0 and average initcode
|
||||
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] Gap between ADC1 CH1 and average initcode
|
||||
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] Gap between ADC1 CH2 and average initcode
|
||||
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] Gap between ADC1 CH3 and average initcode
|
||||
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 241, 4, [] Gap between ADC1 CH4 and average initcode
|
||||
ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 245, 4, [] Gap between ADC1 CH5 and average initcode
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 13b0a8106fd483a0fcfa8b2f7388a95f
|
||||
// md5_digest_table b26e7466c400977081a142076ef1a5bb
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -92,8 +92,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PA_TRIM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_N_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TRIM_P_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -205,8 +227,30 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PA_TRIM_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_N_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TRIM_P_BIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
#include <assert.h>
|
||||
#include "esp_efuse_table.h"
|
||||
|
||||
// md5_digest_table 604cf47a9075de209e7b488c4c6a3cd6
|
||||
// md5_digest_table 29adf9ce1eb138af2755665a720d03d9
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -159,8 +159,64 @@ static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA1[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK_SYS_DATA1,
|
||||
static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_TEMPERATURE_SENSOR[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMPERATURE_SENSOR,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_OCODE[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
|
||||
@ -360,7 +416,7 @@ static const esp_efuse_desc_t UART_PRINT_CONTROL[] = {
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FORCE_SEND_RESUME[] = {
|
||||
{EFUSE_BLK0, 103, 1}, // [] Represents whether ROM code is forced to send a resume commmand during SPI boot,
|
||||
{EFUSE_BLK0, 103, 1}, // [] Represents whether ROM code is forced to send a resume command during SPI boot,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t SECURE_VERSION[] = {
|
||||
@ -404,8 +460,112 @@ static const esp_efuse_desc_t MAC[] = {
|
||||
{EFUSE_BLK1, 0, 8}, // [MAC_FACTORY] MAC address,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t BLOCK_SYS_DATA1[] = {
|
||||
{EFUSE_BLK2, 0, 256}, // [] System data part 1 (reserved),
|
||||
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
|
||||
{EFUSE_BLK1, 64, 4}, // [] Minor chip version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 68, 2}, // [] Major chip version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 70, 1}, // [] Disables check of wafer version major,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 71, 1}, // [] Disables check of blk version major,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
|
||||
{EFUSE_BLK1, 72, 3}, // [] BLK_VERSION_MINOR of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
|
||||
{EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_CAP[] = {
|
||||
{EFUSE_BLK1, 77, 3}, // [] Flash capacity,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t FLASH_VENDOR[] = {
|
||||
{EFUSE_BLK1, 80, 3}, // [] Flash vendor,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_CAP[] = {
|
||||
{EFUSE_BLK1, 83, 3}, // [] PSRAM capacity,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PSRAM_VENDOR[] = {
|
||||
{EFUSE_BLK1, 86, 2}, // [] PSRAM vendor,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t TEMP[] = {
|
||||
{EFUSE_BLK1, 88, 2}, // [] Temperature,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t PKG_VERSION[] = {
|
||||
{EFUSE_BLK1, 90, 3}, // [] Package version,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
|
||||
{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t TEMPERATURE_SENSOR[] = {
|
||||
{EFUSE_BLK2, 128, 9}, // [] Temperature calibration data,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t OCODE[] = {
|
||||
{EFUSE_BLK2, 137, 8}, // [] ADC OCode calibration,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN0[] = {
|
||||
{EFUSE_BLK2, 145, 10}, // [] Average initcode of ADC1 atten0,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN1[] = {
|
||||
{EFUSE_BLK2, 155, 10}, // [] Average initcode of ADC1 atten1,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN2[] = {
|
||||
{EFUSE_BLK2, 165, 10}, // [] Average initcode of ADC1 atten2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_AVE_INIT_CODE_ATTEN3[] = {
|
||||
{EFUSE_BLK2, 175, 10}, // [] Average initcode of ADC1 atten3,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
|
||||
{EFUSE_BLK2, 185, 10}, // [] HI_DOUT of ADC1 atten0,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
|
||||
{EFUSE_BLK2, 195, 10}, // [] HI_DOUT of ADC1 atten1,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
|
||||
{EFUSE_BLK2, 205, 10}, // [] HI_DOUT of ADC1 atten2,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
|
||||
{EFUSE_BLK2, 215, 10}, // [] HI_DOUT of ADC1 atten3,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK2, 225, 4}, // [] Gap between ADC1 CH0 and average initcode,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK2, 229, 4}, // [] Gap between ADC1 CH1 and average initcode,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK2, 233, 4}, // [] Gap between ADC1 CH2 and average initcode,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
|
||||
{EFUSE_BLK2, 237, 4}, // [] Gap between ADC1 CH3 and average initcode,
|
||||
};
|
||||
|
||||
static const esp_efuse_desc_t USER_DATA[] = {
|
||||
@ -628,8 +788,78 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[] = {
|
||||
&WR_DIS_BLOCK_SYS_DATA1[0], // [] wr_dis of BLOCK_SYS_DATA1
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
|
||||
&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[] = {
|
||||
&WR_DIS_TEMPERATURE_SENSOR[0], // [] wr_dis of TEMPERATURE_SENSOR
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
|
||||
&WR_DIS_OCODE[0], // [] wr_dis of OCODE
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[] = {
|
||||
&WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[] = {
|
||||
&WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[] = {
|
||||
&WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[] = {
|
||||
&WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
|
||||
&WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
|
||||
&WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
|
||||
&WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
|
||||
&WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
|
||||
&WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
|
||||
&WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
|
||||
&WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
|
||||
&WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -879,7 +1109,7 @@ const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = {
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = {
|
||||
&FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume commmand during SPI boot
|
||||
&FORCE_SEND_RESUME[0], // [] Represents whether ROM code is forced to send a resume command during SPI boot
|
||||
NULL
|
||||
};
|
||||
|
||||
@ -933,8 +1163,138 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = {
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[] = {
|
||||
&BLOCK_SYS_DATA1[0], // [] System data part 1 (reserved)
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
|
||||
&WAFER_VERSION_MINOR[0], // [] Minor chip version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
|
||||
&WAFER_VERSION_MAJOR[0], // [] Major chip version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
|
||||
&DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
|
||||
&DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
|
||||
&BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
|
||||
&BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
|
||||
&FLASH_CAP[0], // [] Flash capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
|
||||
&FLASH_VENDOR[0], // [] Flash vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
|
||||
&PSRAM_CAP[0], // [] PSRAM capacity
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
|
||||
&PSRAM_VENDOR[0], // [] PSRAM vendor
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
|
||||
&TEMP[0], // [] Temperature
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
|
||||
&PKG_VERSION[0], // [] Package version
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
|
||||
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[] = {
|
||||
&TEMPERATURE_SENSOR[0], // [] Temperature calibration data
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
|
||||
&OCODE[0], // [] ADC OCode calibration
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0[] = {
|
||||
&ADC1_AVE_INIT_CODE_ATTEN0[0], // [] Average initcode of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1[] = {
|
||||
&ADC1_AVE_INIT_CODE_ATTEN1[0], // [] Average initcode of ADC1 atten1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2[] = {
|
||||
&ADC1_AVE_INIT_CODE_ATTEN2[0], // [] Average initcode of ADC1 atten2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3[] = {
|
||||
&ADC1_AVE_INIT_CODE_ATTEN3[0], // [] Average initcode of ADC1 atten3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
|
||||
&ADC1_HI_DOUT_ATTEN0[0], // [] HI_DOUT of ADC1 atten0
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
|
||||
&ADC1_HI_DOUT_ATTEN1[0], // [] HI_DOUT of ADC1 atten1
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
|
||||
&ADC1_HI_DOUT_ATTEN2[0], // [] HI_DOUT of ADC1 atten2
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
|
||||
&ADC1_HI_DOUT_ATTEN3[0], // [] HI_DOUT of ADC1 atten3
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
|
||||
&ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode
|
||||
NULL
|
||||
};
|
||||
|
||||
|
||||
@ -9,7 +9,7 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: beb6fa3bf4a43a464c3365fda28815f5
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f05ff9d292b10d2360200fae1d15e8d
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
@ -47,7 +47,21 @@ WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 19, 1, [] wr_dis
|
||||
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
|
||||
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.BLOCK_SYS_DATA1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK_SYS_DATA1
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR
|
||||
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
|
||||
WR_DIS.ADC1_AVE_INIT_CODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN0
|
||||
WR_DIS.ADC1_AVE_INIT_CODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN1
|
||||
WR_DIS.ADC1_AVE_INIT_CODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN2
|
||||
WR_DIS.ADC1_AVE_INIT_CODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INIT_CODE_ATTEN3
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
|
||||
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -97,7 +111,7 @@ DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 98, 1, [] Repres
|
||||
DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 99, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\
|
||||
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 100, 1, [] Represents whether security download is enabled or disabled.\\ 1: Enable\\ 0: Disable\\
|
||||
UART_PRINT_CONTROL, EFUSE_BLK0, 101, 2, [] Represents the types of UART printing
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume commmand during SPI boot
|
||||
FORCE_SEND_RESUME, EFUSE_BLK0, 103, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot
|
||||
SECURE_VERSION, EFUSE_BLK0, 104, 16, [] Represents the version used by ESP-IDF anti-rollback feature
|
||||
SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 120, 1, [] Represents whether FAST_VERIFY_ON_WAKE is disable or enable when Secure Boot is enable
|
||||
HYS_EN_PAD, EFUSE_BLK0, 121, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\
|
||||
@ -112,7 +126,33 @@ MAC, EFUSE_BLK1, 40, 8, [MAC_FACT
|
||||
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
|
||||
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
|
||||
BLOCK_SYS_DATA1, EFUSE_BLK2, 0, 256, [] System data part 1 (reserved)
|
||||
WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version
|
||||
WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Major chip version
|
||||
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major
|
||||
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major
|
||||
BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2
|
||||
BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2
|
||||
FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity
|
||||
FLASH_VENDOR, EFUSE_BLK1, 80, 3, [] Flash vendor
|
||||
PSRAM_CAP, EFUSE_BLK1, 83, 3, [] PSRAM capacity
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] PSRAM vendor
|
||||
TEMP, EFUSE_BLK1, 88, 2, [] Temperature
|
||||
PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data
|
||||
OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode calibration
|
||||
ADC1_AVE_INIT_CODE_ATTEN0, EFUSE_BLK2, 145, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INIT_CODE_ATTEN1, EFUSE_BLK2, 155, 10, [] Average initcode of ADC1 atten1
|
||||
ADC1_AVE_INIT_CODE_ATTEN2, EFUSE_BLK2, 165, 10, [] Average initcode of ADC1 atten2
|
||||
ADC1_AVE_INIT_CODE_ATTEN3, EFUSE_BLK2, 175, 10, [] Average initcode of ADC1 atten3
|
||||
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] HI_DOUT of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] HI_DOUT of ADC1 atten1
|
||||
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] HI_DOUT of ADC1 atten2
|
||||
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] HI_DOUT of ADC1 atten3
|
||||
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] Gap between ADC1 CH0 and average initcode
|
||||
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] Gap between ADC1 CH1 and average initcode
|
||||
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] Gap between ADC1 CH2 and average initcode
|
||||
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] Gap between ADC1 CH3 and average initcode
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 604cf47a9075de209e7b488c4c6a3cd6
|
||||
// md5_digest_table 29adf9ce1eb138af2755665a720d03d9
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -60,7 +60,21 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
|
||||
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -144,7 +158,33 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_DISABLE_P192[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
|
||||
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK_SYS_DATA1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INIT_CODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -9,7 +9,7 @@
|
||||
# this will generate new source files, next rebuild all the sources.
|
||||
# !!!!!!!!!!! #
|
||||
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: d4a48929387e281bd05db8cfb3a85f60
|
||||
# This file was generated by regtools.py based on the efuses.yaml file with the version: 73787d3f5ae45b80abca925a7562120b
|
||||
|
||||
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
|
||||
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
|
||||
@ -79,7 +79,35 @@ WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis
|
||||
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
|
||||
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
|
||||
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
|
||||
WR_DIS.LDO_VO1_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_DREF
|
||||
WR_DIS.LDO_VO2_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_DREF
|
||||
WR_DIS.LDO_VO1_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_MUL
|
||||
WR_DIS.LDO_VO2_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_MUL
|
||||
WR_DIS.LDO_VO3_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_K
|
||||
WR_DIS.LDO_VO3_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_VOS
|
||||
WR_DIS.LDO_VO3_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_C
|
||||
WR_DIS.LDO_VO4_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_K
|
||||
WR_DIS.LDO_VO4_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_VOS
|
||||
WR_DIS.LDO_VO4_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_C
|
||||
WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
|
||||
WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
|
||||
WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS
|
||||
WR_DIS.DSLP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBG
|
||||
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
|
||||
WR_DIS.LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
|
||||
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
|
||||
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
|
||||
WR_DIS.ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
|
||||
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
|
||||
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
|
||||
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
|
||||
@ -89,6 +117,25 @@ WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.K
|
||||
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
|
||||
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
|
||||
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN0
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN1
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN2
|
||||
WR_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN3
|
||||
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
|
||||
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 29, 1, [] wr_dis of TEMPERATURE_SENSOR
|
||||
WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS
|
||||
WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG11_EXCHG_PINS
|
||||
WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL
|
||||
@ -101,6 +148,25 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K
|
||||
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
|
||||
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
|
||||
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN0
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN1
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN2
|
||||
RD_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN3
|
||||
RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
|
||||
RD_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 38, 1, [] rd_dis of TEMPERATURE_SENSOR
|
||||
USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 39, 1, [] Enable usb device exchange pins of D+ and D-
|
||||
USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 40, 1, [] Enable usb otg11 exchange pins of D+ and D-
|
||||
DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled. 0: enabled
|
||||
@ -177,7 +243,35 @@ PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM
|
||||
TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip
|
||||
PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor
|
||||
PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version
|
||||
LDO_VO1_DREF, EFUSE_BLK1, 88, 4, [] Output VO1 parameter
|
||||
LDO_VO2_DREF, EFUSE_BLK1, 92, 4, [] Output VO2 parameter
|
||||
LDO_VO1_MUL, EFUSE_BLK1, 96, 3, [] Output VO1 parameter
|
||||
LDO_VO2_MUL, EFUSE_BLK1, 99, 3, [] Output VO2 parameter
|
||||
LDO_VO3_K, EFUSE_BLK1, 102, 8, [] Output VO3 calibration parameter
|
||||
LDO_VO3_VOS, EFUSE_BLK1, 110, 6, [] Output VO3 calibration parameter
|
||||
LDO_VO3_C, EFUSE_BLK1, 116, 6, [] Output VO3 calibration parameter
|
||||
LDO_VO4_K, EFUSE_BLK1, 122, 8, [] Output VO4 calibration parameter
|
||||
LDO_VO4_VOS, EFUSE_BLK1, 130, 6, [] Output VO4 calibration parameter
|
||||
LDO_VO4_C, EFUSE_BLK1, 136, 6, [] Output VO4 calibration parameter
|
||||
ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage
|
||||
ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage
|
||||
LSLP_HP_DBIAS, EFUSE_BLK1, 152, 4, [] LSLP HP DBIAS of fixed voltage
|
||||
DSLP_DBG, EFUSE_BLK1, 156, 4, [] DSLP BDG of fixed voltage
|
||||
DSLP_LP_DBIAS, EFUSE_BLK1, 160, 5, [] DSLP LP DBIAS of fixed voltage
|
||||
LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK1, 165, 5, [] DBIAS gap between LP and DCDC
|
||||
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
|
||||
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 128, 10, [] Average initcode of ADC1 atten0
|
||||
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 138, 10, [] Average initcode of ADC1 atten1
|
||||
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 148, 10, [] Average initcode of ADC1 atten2
|
||||
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 158, 10, [] Average initcode of ADC1 atten3
|
||||
ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 168, 10, [] Average initcode of ADC2 atten0
|
||||
ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 178, 10, [] Average initcode of ADC2 atten1
|
||||
ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 188, 10, [] Average initcode of ADC2 atten2
|
||||
ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 198, 10, [] Average initcode of ADC2 atten3
|
||||
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 208, 10, [] HI_DOUT of ADC1 atten0
|
||||
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 218, 10, [] HI_DOUT of ADC1 atten1
|
||||
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 228, 10, [] HI_DOUT of ADC1 atten2
|
||||
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 238, 10, [] HI_DOUT of ADC1 atten3
|
||||
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
|
||||
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
|
||||
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
|
||||
@ -186,4 +280,22 @@ KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KE
|
||||
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
|
||||
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
|
||||
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
|
||||
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
|
||||
ADC2_HI_DOUT_ATTEN0, EFUSE_BLK10, 0, 10, [] HI_DOUT of ADC2 atten0
|
||||
ADC2_HI_DOUT_ATTEN1, EFUSE_BLK10, 10, 10, [] HI_DOUT of ADC2 atten1
|
||||
ADC2_HI_DOUT_ATTEN2, EFUSE_BLK10, 20, 10, [] HI_DOUT of ADC2 atten2
|
||||
ADC2_HI_DOUT_ATTEN3, EFUSE_BLK10, 30, 10, [] HI_DOUT of ADC2 atten3
|
||||
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 40, 4, [] Gap between ADC1_ch0 and average initcode
|
||||
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 44, 4, [] Gap between ADC1_ch1 and average initcode
|
||||
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 48, 4, [] Gap between ADC1_ch2 and average initcode
|
||||
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 52, 4, [] Gap between ADC1_ch3 and average initcode
|
||||
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 56, 4, [] Gap between ADC1_ch4 and average initcode
|
||||
ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 60, 4, [] Gap between ADC1_ch5 and average initcode
|
||||
ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 64, 4, [] Gap between ADC1_ch6 and average initcode
|
||||
ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 68, 4, [] Gap between ADC1_ch7 and average initcode
|
||||
ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 72, 4, [] Gap between ADC2_ch0 and average initcode
|
||||
ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 76, 4, [] Gap between ADC2_ch1 and average initcode
|
||||
ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 80, 4, [] Gap between ADC2_ch2 and average initcode
|
||||
ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 84, 4, [] Gap between ADC2_ch3 and average initcode
|
||||
ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 88, 4, [] Gap between ADC2_ch4 and average initcode
|
||||
ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 92, 4, [] Gap between ADC2_ch5 and average initcode
|
||||
TEMPERATURE_SENSOR, EFUSE_BLK10, 96, 9, [] Temperature calibration data
|
||||
|
||||
|
Can't render this file because it contains an unexpected character in line 8 and column 53.
|
@ -10,7 +10,7 @@ extern "C" {
|
||||
|
||||
#include "esp_efuse.h"
|
||||
|
||||
// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b
|
||||
// md5_digest_table c56ed98dde7a08c8f70d57a01faba96a
|
||||
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
|
||||
// If you want to change some fields, you need to change esp_efuse_table.csv file
|
||||
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
|
||||
@ -92,7 +92,35 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
|
||||
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
|
||||
@ -112,6 +140,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
|
||||
@ -131,6 +178,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
|
||||
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
|
||||
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
|
||||
@ -209,7 +275,35 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
|
||||
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
|
||||
@ -227,8 +321,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
|
||||
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
|
||||
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
|
||||
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
|
||||
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@ -804,32 +804,74 @@ extern "C" {
|
||||
#define EFUSE_TRIM_P_BIAS_M (EFUSE_TRIM_P_BIAS_V << EFUSE_TRIM_P_BIAS_S)
|
||||
#define EFUSE_TRIM_P_BIAS_V 0x0000001FU
|
||||
#define EFUSE_TRIM_P_BIAS_S 5
|
||||
/** EFUSE_RESERVED_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [13:10]; default: 0;
|
||||
* Active HP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_106 0x000000FFU
|
||||
#define EFUSE_RESERVED_1_106_M (EFUSE_RESERVED_1_106_V << EFUSE_RESERVED_1_106_S)
|
||||
#define EFUSE_RESERVED_1_106_V 0x000000FFU
|
||||
#define EFUSE_RESERVED_1_106_S 10
|
||||
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_S 10
|
||||
/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [17:14]; default: 0;
|
||||
* Active LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
|
||||
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
|
||||
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
|
||||
#define EFUSE_SYS_DATA_PART0_0_S 18
|
||||
#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_S 14
|
||||
/** EFUSE_LSLP_HP_DBG : R; bitpos: [19:18]; default: 0;
|
||||
* LSLP HP DBG of fixed voltage
|
||||
*/
|
||||
#define EFUSE_LSLP_HP_DBG 0x00000003U
|
||||
#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S)
|
||||
#define EFUSE_LSLP_HP_DBG_V 0x00000003U
|
||||
#define EFUSE_LSLP_HP_DBG_S 18
|
||||
/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [23:20]; default: 0;
|
||||
* LSLP HP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_LSLP_HP_DBIAS 0x0000000FU
|
||||
#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
|
||||
#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_LSLP_HP_DBIAS_S 20
|
||||
/** EFUSE_DSLP_LP_DBG : R; bitpos: [27:24]; default: 0;
|
||||
* DSLP LP DBG of fixed voltage
|
||||
*/
|
||||
#define EFUSE_DSLP_LP_DBG 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S)
|
||||
#define EFUSE_DSLP_LP_DBG_V 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBG_S 24
|
||||
/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [31:28]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_DSLP_LP_DBIAS 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
|
||||
#define EFUSE_DSLP_LP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_DSLP_LP_DBIAS_S 28
|
||||
|
||||
/** EFUSE_RD_MAC_SYS4_REG register
|
||||
* Represents rd_mac_sys
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS4_REG (DR_REG_EFUSE_BASE + 0x54)
|
||||
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
/** EFUSE_DSLP_LP_DBIAS_1 : R; bitpos: [0]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
|
||||
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_1_S 0
|
||||
#define EFUSE_DSLP_LP_DBIAS_1 (BIT(0))
|
||||
#define EFUSE_DSLP_LP_DBIAS_1_M (EFUSE_DSLP_LP_DBIAS_1_V << EFUSE_DSLP_LP_DBIAS_1_S)
|
||||
#define EFUSE_DSLP_LP_DBIAS_1_V 0x00000001U
|
||||
#define EFUSE_DSLP_LP_DBIAS_1_S 0
|
||||
/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [5:1]; default: 0;
|
||||
* DBIAS gap between LP and HP
|
||||
*/
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S)
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU
|
||||
#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 1
|
||||
/** EFUSE_RESERVED_1_134 : R; bitpos: [31:6]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_134 0x03FFFFFFU
|
||||
#define EFUSE_RESERVED_1_134_M (EFUSE_RESERVED_1_134_V << EFUSE_RESERVED_1_134_S)
|
||||
#define EFUSE_RESERVED_1_134_V 0x03FFFFFFU
|
||||
#define EFUSE_RESERVED_1_134_S 6
|
||||
|
||||
/** EFUSE_RD_MAC_SYS5_REG register
|
||||
* Represents rd_mac_sys
|
||||
@ -895,13 +937,13 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data4
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
|
||||
/** EFUSE_RESERVED_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_128 0x000001FFU
|
||||
#define EFUSE_RESERVED_2_128_M (EFUSE_RESERVED_2_128_V << EFUSE_RESERVED_2_128_S)
|
||||
#define EFUSE_RESERVED_2_128_V 0x000001FFU
|
||||
#define EFUSE_RESERVED_2_128_S 0
|
||||
#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
|
||||
#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_S 0
|
||||
/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
@ -909,49 +951,147 @@ extern "C" {
|
||||
#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
|
||||
#define EFUSE_OCODE_V 0x000000FFU
|
||||
#define EFUSE_OCODE_S 9
|
||||
/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_145 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S)
|
||||
#define EFUSE_RESERVED_2_145_V 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_145_S 17
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 17
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 27
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA5_REG register
|
||||
* Represents rd_sys_part1_data5
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
|
||||
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
|
||||
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_S 0
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_1_S 0
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 5
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 15
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA6_REG register
|
||||
* Represents rd_sys_part1_data6
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
|
||||
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
|
||||
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI DOUT of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI DOUT of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA7_REG register
|
||||
* Represents rd_sys_part1_data7
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
|
||||
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
|
||||
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0))
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1
|
||||
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5
|
||||
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9
|
||||
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13
|
||||
/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [20:17]; default: 0;
|
||||
* Gap between ADC1 CH4 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 17
|
||||
/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [24:21]; default: 0;
|
||||
* Gap between ADC1 CH5 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 21
|
||||
/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_249 0x0000007FU
|
||||
#define EFUSE_RESERVED_2_249_M (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S)
|
||||
#define EFUSE_RESERVED_2_249_V 0x0000007FU
|
||||
#define EFUSE_RESERVED_2_249_S 25
|
||||
|
||||
/** EFUSE_RD_USR_DATA0_REG register
|
||||
* Represents rd_usr_data0
|
||||
|
||||
@ -615,14 +615,30 @@ typedef union {
|
||||
* PADC CAL P bias
|
||||
*/
|
||||
uint32_t trim_p_bias:5;
|
||||
/** reserved_1_106 : R; bitpos: [17:10]; default: 0;
|
||||
* reserved
|
||||
/** active_hp_dbias : R; bitpos: [13:10]; default: 0;
|
||||
* Active HP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t reserved_1_106:8;
|
||||
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
uint32_t active_hp_dbias:4;
|
||||
/** active_lp_dbias : R; bitpos: [17:14]; default: 0;
|
||||
* Active LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t sys_data_part0_0:14;
|
||||
uint32_t active_lp_dbias:4;
|
||||
/** lslp_hp_dbg : R; bitpos: [19:18]; default: 0;
|
||||
* LSLP HP DBG of fixed voltage
|
||||
*/
|
||||
uint32_t lslp_hp_dbg:2;
|
||||
/** lslp_hp_dbias : R; bitpos: [23:20]; default: 0;
|
||||
* LSLP HP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t lslp_hp_dbias:4;
|
||||
/** dslp_lp_dbg : R; bitpos: [27:24]; default: 0;
|
||||
* DSLP LP DBG of fixed voltage
|
||||
*/
|
||||
uint32_t dslp_lp_dbg:4;
|
||||
/** dslp_lp_dbias : R; bitpos: [31:28]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t dslp_lp_dbias:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys3_reg_t;
|
||||
@ -632,10 +648,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the first 14-bit of zeroth part of system data.
|
||||
/** dslp_lp_dbias_1 : R; bitpos: [0]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t sys_data_part0_1:32;
|
||||
uint32_t dslp_lp_dbias_1:1;
|
||||
/** lp_hp_dbias_vol_gap : R; bitpos: [5:1]; default: 0;
|
||||
* DBIAS gap between LP and HP
|
||||
*/
|
||||
uint32_t lp_hp_dbias_vol_gap:5;
|
||||
/** reserved_1_134 : R; bitpos: [31:6]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_134:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys4_reg_t;
|
||||
@ -712,18 +736,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** reserved_2_128 : R; bitpos: [8:0]; default: 0;
|
||||
* reserved
|
||||
/** temperature_sensor : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
uint32_t reserved_2_128:9;
|
||||
uint32_t temperature_sensor:9;
|
||||
/** ocode : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode
|
||||
*/
|
||||
uint32_t ocode:8;
|
||||
/** reserved_2_145 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
/** adc1_ave_initcode_atten0 : R; bitpos: [26:17]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t reserved_2_145:15;
|
||||
uint32_t adc1_ave_initcode_atten0:10;
|
||||
/** adc1_ave_initcode_atten1 : R; bitpos: [31:27]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten1:5;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@ -733,10 +761,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_ave_initcode_atten1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_5:32;
|
||||
uint32_t adc1_ave_initcode_atten1_1:5;
|
||||
/** adc1_ave_initcode_atten2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten2:10;
|
||||
/** adc1_ave_initcode_atten3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten3:10;
|
||||
/** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten0:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data5_reg_t;
|
||||
@ -746,10 +786,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_6:32;
|
||||
uint32_t adc1_hi_dout_atten0_1:3;
|
||||
/** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI DOUT of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten1:10;
|
||||
/** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI DOUT of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten2:10;
|
||||
/** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten3:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data6_reg_t;
|
||||
@ -759,10 +811,38 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t sys_data_part1_7:32;
|
||||
uint32_t adc1_hi_dout_atten3_1:1;
|
||||
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch0_atten0_initcode_diff:4;
|
||||
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch1_atten0_initcode_diff:4;
|
||||
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch2_atten0_initcode_diff:4;
|
||||
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch3_atten0_initcode_diff:4;
|
||||
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [20:17]; default: 0;
|
||||
* Gap between ADC1 CH4 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch4_atten0_initcode_diff:4;
|
||||
/** adc1_ch5_atten0_initcode_diff : R; bitpos: [24:21]; default: 0;
|
||||
* Gap between ADC1 CH5 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch5_atten0_initcode_diff:4;
|
||||
/** reserved_2_249 : R; bitpos: [31:25]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_249:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
@ -2090,123 +2170,6 @@ typedef union {
|
||||
uint32_t val;
|
||||
} efuse_conf_reg_t;
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of dac_conf register
|
||||
* Controls the eFuse programming voltage.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
|
||||
* Controls the division factor of the rising clock of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_clk_div:8;
|
||||
/** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
|
||||
* Don't care.
|
||||
*/
|
||||
uint32_t dac_clk_pad_sel:1;
|
||||
/** dac_num : R/W; bitpos: [16:9]; default: 255;
|
||||
* Controls the rising period of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_num:8;
|
||||
/** oe_clr : R/W; bitpos: [17]; default: 0;
|
||||
* Reduces the power supply of the programming voltage.
|
||||
*/
|
||||
uint32_t oe_clr:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_dac_conf_reg_t;
|
||||
|
||||
/** Type of rd_tim_conf register
|
||||
* Configures read timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** thr_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the read hold time.
|
||||
*/
|
||||
uint32_t thr_a:8;
|
||||
/** trd : R/W; bitpos: [15:8]; default: 2;
|
||||
* Configures the read time.
|
||||
*/
|
||||
uint32_t trd:8;
|
||||
/** tsur_a : R/W; bitpos: [23:16]; default: 1;
|
||||
* Configures the read setup time.
|
||||
*/
|
||||
uint32_t tsur_a:8;
|
||||
/** read_init_num : R/W; bitpos: [31:24]; default: 22;
|
||||
* Configures the waiting time of reading eFuse memory.
|
||||
*/
|
||||
uint32_t read_init_num:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_tim_conf_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf1 register
|
||||
* Configurarion register 1 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tsup_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the programming setup time.
|
||||
*/
|
||||
uint32_t tsup_a:8;
|
||||
/** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
|
||||
* Configures the power up time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_on_num:16;
|
||||
/** thp_a : R/W; bitpos: [31:24]; default: 1;
|
||||
* Configures the programming hold time.
|
||||
*/
|
||||
uint32_t thp_a:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf1_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf2 register
|
||||
* Configurarion register 2 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
|
||||
* Configures the power outage time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_off_num:16;
|
||||
/** tpgm : R/W; bitpos: [31:16]; default: 200;
|
||||
* Configures the active programming time.
|
||||
*/
|
||||
uint32_t tpgm:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf2_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf0_rs_bypass register
|
||||
* Configurarion register0 of eFuse programming time parameters and rs bypass
|
||||
* operation.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to bypass reed solomon correction step.
|
||||
*/
|
||||
uint32_t bypass_rs_correction:1;
|
||||
/** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
|
||||
* Configures block number of programming twice operation.
|
||||
*/
|
||||
uint32_t bypass_rs_blk_num:11;
|
||||
/** update : WT; bitpos: [12]; default: 0;
|
||||
* Set this bit to update multi-bit register signals.
|
||||
*/
|
||||
uint32_t update:1;
|
||||
/** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
|
||||
* Configures the inactive programming time.
|
||||
*/
|
||||
uint32_t tpgm_inactive:8;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf0_rs_bypass_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE Status Registers */
|
||||
/** Type of status register
|
||||
@ -2355,6 +2318,124 @@ typedef union {
|
||||
} efuse_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of dac_conf register
|
||||
* Controls the eFuse programming voltage.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dac_clk_div : R/W; bitpos: [7:0]; default: 23;
|
||||
* Controls the division factor of the rising clock of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_clk_div:8;
|
||||
/** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0;
|
||||
* Don't care.
|
||||
*/
|
||||
uint32_t dac_clk_pad_sel:1;
|
||||
/** dac_num : R/W; bitpos: [16:9]; default: 255;
|
||||
* Controls the rising period of the programming voltage.
|
||||
*/
|
||||
uint32_t dac_num:8;
|
||||
/** oe_clr : R/W; bitpos: [17]; default: 0;
|
||||
* Reduces the power supply of the programming voltage.
|
||||
*/
|
||||
uint32_t oe_clr:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_dac_conf_reg_t;
|
||||
|
||||
/** Type of rd_tim_conf register
|
||||
* Configures read timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** thr_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the read hold time.
|
||||
*/
|
||||
uint32_t thr_a:8;
|
||||
/** trd : R/W; bitpos: [15:8]; default: 2;
|
||||
* Configures the read time.
|
||||
*/
|
||||
uint32_t trd:8;
|
||||
/** tsur_a : R/W; bitpos: [23:16]; default: 1;
|
||||
* Configures the read setup time.
|
||||
*/
|
||||
uint32_t tsur_a:8;
|
||||
/** read_init_num : R/W; bitpos: [31:24]; default: 22;
|
||||
* Configures the waiting time of reading eFuse memory.
|
||||
*/
|
||||
uint32_t read_init_num:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_tim_conf_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf1 register
|
||||
* Configurarion register 1 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tsup_a : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configures the programming setup time.
|
||||
*/
|
||||
uint32_t tsup_a:8;
|
||||
/** pwr_on_num : R/W; bitpos: [23:8]; default: 12288;
|
||||
* Configures the power up time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_on_num:16;
|
||||
/** thp_a : R/W; bitpos: [31:24]; default: 1;
|
||||
* Configures the programming hold time.
|
||||
*/
|
||||
uint32_t thp_a:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf1_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf2 register
|
||||
* Configurarion register 2 of eFuse programming timing parameters.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pwr_off_num : R/W; bitpos: [15:0]; default: 400;
|
||||
* Configures the power outage time for VDDQ.
|
||||
*/
|
||||
uint32_t pwr_off_num:16;
|
||||
/** tpgm : R/W; bitpos: [31:16]; default: 200;
|
||||
* Configures the active programming time.
|
||||
*/
|
||||
uint32_t tpgm:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf2_reg_t;
|
||||
|
||||
/** Type of wr_tim_conf0_rs_bypass register
|
||||
* Configurarion register0 of eFuse programming time parameters and rs bypass
|
||||
* operation.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** bypass_rs_correction : R/W; bitpos: [0]; default: 0;
|
||||
* Set this bit to bypass reed solomon correction step.
|
||||
*/
|
||||
uint32_t bypass_rs_correction:1;
|
||||
/** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0;
|
||||
* Configures block number of programming twice operation.
|
||||
*/
|
||||
uint32_t bypass_rs_blk_num:11;
|
||||
/** update : WT; bitpos: [12]; default: 0;
|
||||
* Set this bit to update multi-bit register signals.
|
||||
*/
|
||||
uint32_t update:1;
|
||||
/** tpgm_inactive : R/W; bitpos: [20:13]; default: 1;
|
||||
* Configures the inactive programming time.
|
||||
*/
|
||||
uint32_t tpgm_inactive:8;
|
||||
uint32_t reserved_21:11;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_wr_tim_conf0_rs_bypass_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE_APB2OTP Block0 Write Disable Data */
|
||||
/** Type of apb2otp_wr_dis register
|
||||
* eFuse apb2otp block0 data register1.
|
||||
|
||||
@ -40,7 +40,7 @@ extern "C" {
|
||||
*/
|
||||
#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE0_BASE + 0x8)
|
||||
/** EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0;
|
||||
* Configures the 0th 32-bit data to be programmed.
|
||||
* Configures the 0th 32-bit data to be programmmmmed.
|
||||
*/
|
||||
#define EFUSE_PGM_DATA_2 0xFFFFFFFFU
|
||||
#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S)
|
||||
@ -233,14 +233,14 @@ extern "C" {
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U
|
||||
#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 14
|
||||
/** EFUSE_USB_DREFH : RO; bitpos: [16:15]; default: 0;
|
||||
* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
#define EFUSE_USB_DREFH 0x00000003U
|
||||
#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S)
|
||||
#define EFUSE_USB_DREFH_V 0x00000003U
|
||||
#define EFUSE_USB_DREFH_S 15
|
||||
/** EFUSE_USB_DREFL : RO; bitpos: [18:17]; default: 0;
|
||||
* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
#define EFUSE_USB_DREFL 0x00000003U
|
||||
#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S)
|
||||
@ -441,7 +441,7 @@ extern "C" {
|
||||
#define EFUSE_UART_PRINT_CONTROL_V 0x00000003U
|
||||
#define EFUSE_UART_PRINT_CONTROL_S 5
|
||||
/** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [7]; default: 0;
|
||||
* Represents whether ROM code is forced to send a resume commmand during SPI boot.
|
||||
* Represents whether ROM code is forced to send a resume command during SPI boot.
|
||||
*/
|
||||
#define EFUSE_FORCE_SEND_RESUME (BIT(7))
|
||||
#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S)
|
||||
@ -679,49 +679,147 @@ extern "C" {
|
||||
* Represents rd_sys_part1_data4
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE0_BASE + 0x6c)
|
||||
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
|
||||
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_S 0
|
||||
#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
|
||||
#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_S 0
|
||||
/** EFUSE_OCODE : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode calibration
|
||||
*/
|
||||
#define EFUSE_OCODE 0x000000FFU
|
||||
#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S)
|
||||
#define EFUSE_OCODE_V 0x000000FFU
|
||||
#define EFUSE_OCODE_S 9
|
||||
/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 : R; bitpos: [26:17]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S)
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN0_S 17
|
||||
/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 : R; bitpos: [31:27]; default: 0;
|
||||
* Average initcode of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S)
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_S 27
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA5_REG register
|
||||
* Represents rd_sys_part1_data5
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE0_BASE + 0x70)
|
||||
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
|
||||
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_S 0
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S)
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_V 0x0000001FU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN1_1_S 0
|
||||
/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S)
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN2_S 5
|
||||
/** EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_M (EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V << EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INIT_CODE_ATTEN3_S 15
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x0000007FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 25
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA6_REG register
|
||||
* Represents rd_sys_part1_data6
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE0_BASE + 0x74)
|
||||
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
|
||||
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_M (EFUSE_ADC1_HI_DOUT_ATTEN0_1_V << EFUSE_ADC1_HI_DOUT_ATTEN0_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_V 0x00000007U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_1_S 0
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 3
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI_DOUT of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 13
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000001FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 23
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA7_REG register
|
||||
* Represents rd_sys_part1_data7
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE0_BASE + 0x78)
|
||||
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
|
||||
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1 (BIT(0))
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_M (EFUSE_ADC1_HI_DOUT_ATTEN3_1_V << EFUSE_ADC1_HI_DOUT_ATTEN3_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_V 0x00000001U
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 1
|
||||
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 5
|
||||
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 9
|
||||
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 13
|
||||
/** EFUSE_RESERVED_2_241 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_241 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_241_M (EFUSE_RESERVED_2_241_V << EFUSE_RESERVED_2_241_S)
|
||||
#define EFUSE_RESERVED_2_241_V 0x00007FFFU
|
||||
#define EFUSE_RESERVED_2_241_S 17
|
||||
|
||||
/** EFUSE_RD_USR_DATA0_REG register
|
||||
* Represents rd_usr_data0
|
||||
@ -2071,7 +2169,7 @@ extern "C" {
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
|
||||
/** EFUSE_CONF_REG register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
#define EFUSE_CONF_REG (DR_REG_EFUSE0_BASE + 0x1cc)
|
||||
/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
|
||||
|
||||
@ -223,11 +223,11 @@ typedef union {
|
||||
*/
|
||||
uint32_t dis_download_manual_encrypt:1;
|
||||
/** usb_drefh : RO; bitpos: [16:15]; default: 0;
|
||||
* Represents the single-end input threhold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
uint32_t usb_drefh:2;
|
||||
/** usb_drefl : RO; bitpos: [18:17]; default: 0;
|
||||
* Represents the single-end input threhold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
* Represents the single-end input threshold vrefl, 1.76 V to 2 V with step of 80 mV.
|
||||
*/
|
||||
uint32_t usb_drefl:2;
|
||||
/** usb_exchg_pins : RO; bitpos: [19]; default: 0;
|
||||
@ -361,7 +361,7 @@ typedef union {
|
||||
*/
|
||||
uint32_t uart_print_control:2;
|
||||
/** force_send_resume : RO; bitpos: [7]; default: 0;
|
||||
* Represents whether ROM code is forced to send a resume commmand during SPI boot.
|
||||
* Represents whether ROM code is forced to send a resume command during SPI boot.
|
||||
*/
|
||||
uint32_t force_send_resume:1;
|
||||
/** secure_version : RO; bitpos: [23:8]; default: 0;
|
||||
@ -583,10 +583,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** temperature_sensor : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
uint32_t sys_data_part1_4:32;
|
||||
uint32_t temperature_sensor:9;
|
||||
/** ocode : R; bitpos: [16:9]; default: 0;
|
||||
* ADC OCode calibration
|
||||
*/
|
||||
uint32_t ocode:8;
|
||||
/** adc1_ave_init_code_atten0 : R; bitpos: [26:17]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_ave_init_code_atten0:10;
|
||||
/** adc1_ave_init_code_atten1 : R; bitpos: [31:27]; default: 0;
|
||||
* Average initcode of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_ave_init_code_atten1:5;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@ -596,10 +608,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_ave_init_code_atten1_1 : R; bitpos: [4:0]; default: 0;
|
||||
* Average initcode of ADC1 atten1
|
||||
*/
|
||||
uint32_t sys_data_part1_5:32;
|
||||
uint32_t adc1_ave_init_code_atten1_1:5;
|
||||
/** adc1_ave_init_code_atten2 : R; bitpos: [14:5]; default: 0;
|
||||
* Average initcode of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_ave_init_code_atten2:10;
|
||||
/** adc1_ave_init_code_atten3 : R; bitpos: [24:15]; default: 0;
|
||||
* Average initcode of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_ave_init_code_atten3:10;
|
||||
/** adc1_hi_dout_atten0 : R; bitpos: [31:25]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten0:7;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data5_reg_t;
|
||||
@ -609,10 +633,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten0_1 : R; bitpos: [2:0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_6:32;
|
||||
uint32_t adc1_hi_dout_atten0_1:3;
|
||||
/** adc1_hi_dout_atten1 : R; bitpos: [12:3]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten1:10;
|
||||
/** adc1_hi_dout_atten2 : R; bitpos: [22:13]; default: 0;
|
||||
* HI_DOUT of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten2:10;
|
||||
/** adc1_hi_dout_atten3 : R; bitpos: [31:23]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten3:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data6_reg_t;
|
||||
@ -622,10 +658,30 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents the zeroth 32-bit of first part of system data.
|
||||
/** adc1_hi_dout_atten3_1 : R; bitpos: [0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t sys_data_part1_7:32;
|
||||
uint32_t adc1_hi_dout_atten3_1:1;
|
||||
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:1]; default: 0;
|
||||
* Gap between ADC1 CH0 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch0_atten0_initcode_diff:4;
|
||||
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [8:5]; default: 0;
|
||||
* Gap between ADC1 CH1 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch1_atten0_initcode_diff:4;
|
||||
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [12:9]; default: 0;
|
||||
* Gap between ADC1 CH2 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch2_atten0_initcode_diff:4;
|
||||
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [16:13]; default: 0;
|
||||
* Gap between ADC1 CH3 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch3_atten0_initcode_diff:4;
|
||||
/** reserved_2_241 : R; bitpos: [31:17]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_241:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
@ -1893,7 +1949,7 @@ typedef union {
|
||||
|
||||
/** Group: EFUSE Configure Registers */
|
||||
/** Type of conf register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@ -4111,7 +4167,7 @@ typedef union {
|
||||
} efuse_apb2otp_blk10_w11_reg_t;
|
||||
|
||||
|
||||
/** Group: EFUSE_APB2OTP Function Enable Singal */
|
||||
/** Group: EFUSE_APB2OTP Function Enable Signal */
|
||||
/** Type of apb2otp_en register
|
||||
* eFuse apb2otp enable configuration register.
|
||||
*/
|
||||
|
||||
@ -654,16 +654,16 @@ extern "C" {
|
||||
#define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU
|
||||
#define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8
|
||||
/** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0;
|
||||
* Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step
|
||||
* of 80 mV.
|
||||
* Represents the usb device single-end input low threshold; 0.8 V to 1.04 V with step
|
||||
* of 80 mV
|
||||
*/
|
||||
#define EFUSE_USB_DEVICE_DREFL 0x00000003U
|
||||
#define EFUSE_USB_DEVICE_DREFL_M (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S)
|
||||
#define EFUSE_USB_DEVICE_DREFL_V 0x00000003U
|
||||
#define EFUSE_USB_DEVICE_DREFL_S 12
|
||||
/** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0;
|
||||
* Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step
|
||||
* of 80 mV.
|
||||
* Represents the usb otg11 single-end input low threshold; 0.8 V to 1.04 V with step
|
||||
* of 80 mV
|
||||
*/
|
||||
#define EFUSE_USB_OTG11_DREFL 0x00000003U
|
||||
#define EFUSE_USB_OTG11_DREFL_M (EFUSE_USB_OTG11_DREFL_V << EFUSE_USB_OTG11_DREFL_S)
|
||||
@ -817,56 +817,161 @@ extern "C" {
|
||||
#define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S)
|
||||
#define EFUSE_PKG_VERSION_V 0x00000007U
|
||||
#define EFUSE_PKG_VERSION_S 20
|
||||
/** EFUSE_RESERVED_1_87 : R; bitpos: [31:23]; default: 0;
|
||||
/** EFUSE_RESERVED_1_87 : R; bitpos: [23]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_87 0x000001FFU
|
||||
#define EFUSE_RESERVED_1_87 (BIT(23))
|
||||
#define EFUSE_RESERVED_1_87_M (EFUSE_RESERVED_1_87_V << EFUSE_RESERVED_1_87_S)
|
||||
#define EFUSE_RESERVED_1_87_V 0x000001FFU
|
||||
#define EFUSE_RESERVED_1_87_V 0x00000001U
|
||||
#define EFUSE_RESERVED_1_87_S 23
|
||||
/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0;
|
||||
* Output VO1 parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO1_DREF 0x0000000FU
|
||||
#define EFUSE_LDO_VO1_DREF_M (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S)
|
||||
#define EFUSE_LDO_VO1_DREF_V 0x0000000FU
|
||||
#define EFUSE_LDO_VO1_DREF_S 24
|
||||
/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0;
|
||||
* Output VO2 parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO2_DREF 0x0000000FU
|
||||
#define EFUSE_LDO_VO2_DREF_M (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S)
|
||||
#define EFUSE_LDO_VO2_DREF_V 0x0000000FU
|
||||
#define EFUSE_LDO_VO2_DREF_S 28
|
||||
|
||||
/** EFUSE_RD_MAC_SYS_3_REG register
|
||||
* BLOCK1 data register $n.
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
|
||||
/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
|
||||
* Reserved.
|
||||
/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
|
||||
* Output VO1 parameter
|
||||
*/
|
||||
#define EFUSE_MAC_RESERVED_2 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
|
||||
#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
|
||||
#define EFUSE_MAC_RESERVED_2_S 0
|
||||
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Stores the first 14 bits of the zeroth part of system data.
|
||||
#define EFUSE_LDO_VO1_MUL 0x00000007U
|
||||
#define EFUSE_LDO_VO1_MUL_M (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S)
|
||||
#define EFUSE_LDO_VO1_MUL_V 0x00000007U
|
||||
#define EFUSE_LDO_VO1_MUL_S 0
|
||||
/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0;
|
||||
* Output VO2 parameter
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
|
||||
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
|
||||
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
|
||||
#define EFUSE_SYS_DATA_PART0_0_S 18
|
||||
#define EFUSE_LDO_VO2_MUL 0x00000007U
|
||||
#define EFUSE_LDO_VO2_MUL_M (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S)
|
||||
#define EFUSE_LDO_VO2_MUL_V 0x00000007U
|
||||
#define EFUSE_LDO_VO2_MUL_S 3
|
||||
/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0;
|
||||
* Output VO3 calibration parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO3_K 0x000000FFU
|
||||
#define EFUSE_LDO_VO3_K_M (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S)
|
||||
#define EFUSE_LDO_VO3_K_V 0x000000FFU
|
||||
#define EFUSE_LDO_VO3_K_S 6
|
||||
/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0;
|
||||
* Output VO3 calibration parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO3_VOS 0x0000003FU
|
||||
#define EFUSE_LDO_VO3_VOS_M (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S)
|
||||
#define EFUSE_LDO_VO3_VOS_V 0x0000003FU
|
||||
#define EFUSE_LDO_VO3_VOS_S 14
|
||||
/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0;
|
||||
* Output VO3 calibration parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO3_C 0x0000003FU
|
||||
#define EFUSE_LDO_VO3_C_M (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S)
|
||||
#define EFUSE_LDO_VO3_C_V 0x0000003FU
|
||||
#define EFUSE_LDO_VO3_C_S 20
|
||||
/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO4_K 0x0000003FU
|
||||
#define EFUSE_LDO_VO4_K_M (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S)
|
||||
#define EFUSE_LDO_VO4_K_V 0x0000003FU
|
||||
#define EFUSE_LDO_VO4_K_S 26
|
||||
|
||||
/** EFUSE_RD_MAC_SYS_4_REG register
|
||||
* BLOCK1 data register $n.
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
|
||||
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the first 32 bits of the zeroth part of system data.
|
||||
/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
|
||||
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_1_S 0
|
||||
#define EFUSE_LDO_VO4_K_1 0x00000003U
|
||||
#define EFUSE_LDO_VO4_K_1_M (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S)
|
||||
#define EFUSE_LDO_VO4_K_1_V 0x00000003U
|
||||
#define EFUSE_LDO_VO4_K_1_S 0
|
||||
/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO4_VOS 0x0000003FU
|
||||
#define EFUSE_LDO_VO4_VOS_M (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S)
|
||||
#define EFUSE_LDO_VO4_VOS_V 0x0000003FU
|
||||
#define EFUSE_LDO_VO4_VOS_S 2
|
||||
/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
#define EFUSE_LDO_VO4_C 0x0000003FU
|
||||
#define EFUSE_LDO_VO4_C_M (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S)
|
||||
#define EFUSE_LDO_VO4_C_V 0x0000003FU
|
||||
#define EFUSE_LDO_VO4_C_S 8
|
||||
/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_142 0x00000003U
|
||||
#define EFUSE_RESERVED_1_142_M (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S)
|
||||
#define EFUSE_RESERVED_1_142_V 0x00000003U
|
||||
#define EFUSE_RESERVED_1_142_S 14
|
||||
/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0;
|
||||
* Active HP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_ACTIVE_HP_DBIAS_S 16
|
||||
/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0;
|
||||
* Active LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_ACTIVE_LP_DBIAS_S 20
|
||||
/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [27:24]; default: 0;
|
||||
* LSLP HP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_LSLP_HP_DBIAS 0x0000000FU
|
||||
#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S)
|
||||
#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU
|
||||
#define EFUSE_LSLP_HP_DBIAS_S 24
|
||||
/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
|
||||
* DSLP BDG of fixed voltage
|
||||
*/
|
||||
#define EFUSE_DSLP_DBG 0x0000000FU
|
||||
#define EFUSE_DSLP_DBG_M (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S)
|
||||
#define EFUSE_DSLP_DBG_V 0x0000000FU
|
||||
#define EFUSE_DSLP_DBG_S 28
|
||||
|
||||
/** EFUSE_RD_MAC_SYS_5_REG register
|
||||
* BLOCK1 data register $n.
|
||||
*/
|
||||
#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
|
||||
/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the second 32 bits of the zeroth part of system data.
|
||||
/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
|
||||
#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART0_2_S 0
|
||||
#define EFUSE_DSLP_LP_DBIAS 0x0000001FU
|
||||
#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
|
||||
#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU
|
||||
#define EFUSE_DSLP_LP_DBIAS_S 0
|
||||
/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0;
|
||||
* DBIAS gap between LP and DCDC
|
||||
*/
|
||||
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP 0x0000001FU
|
||||
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
|
||||
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V 0x0000001FU
|
||||
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S 5
|
||||
/** EFUSE_RESERVED_1_170 : R; bitpos: [31:10]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_1_170 0x003FFFFFU
|
||||
#define EFUSE_RESERVED_1_170_M (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
|
||||
#define EFUSE_RESERVED_1_170_V 0x003FFFFFU
|
||||
#define EFUSE_RESERVED_1_170_S 10
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA0_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
@ -920,49 +1025,133 @@ extern "C" {
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
|
||||
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fourth 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
|
||||
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_4_S 0
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 0
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0;
|
||||
* Average initcode of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 10
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0;
|
||||
* Average initcode of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 20
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0;
|
||||
* Average initcode of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x00000003U
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x00000003U
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 30
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA5_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
|
||||
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fifth 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
|
||||
* Average initcode of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
|
||||
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_5_S 0
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 0x000000FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S)
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V 0x000000FFU
|
||||
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0;
|
||||
* Average initcode of ADC2 atten0
|
||||
*/
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S)
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S 8
|
||||
/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0;
|
||||
* Average initcode of ADC2 atten1
|
||||
*/
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S)
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S 18
|
||||
/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0;
|
||||
* Average initcode of ADC2 atten2
|
||||
*/
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2 0x0000000FU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S)
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V 0x0000000FU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S 28
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA6_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
|
||||
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the sixth 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
|
||||
* Average initcode of ADC2 atten2
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
|
||||
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_6_S 0
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 0x0000003FU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S)
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V 0x0000003FU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S 0
|
||||
/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0;
|
||||
* Average initcode of ADC2 atten3
|
||||
*/
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S)
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S 6
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 16
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x0000003FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x0000003FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 26
|
||||
|
||||
/** EFUSE_RD_SYS_PART1_DATA7_REG register
|
||||
* Register $n of BLOCK2 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
|
||||
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the seventh 32 bits of the first part of system data.
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
|
||||
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART1_7_S 0
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1 0x0000000FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V 0x0000000FU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S 0
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0;
|
||||
* HI_DOUT of ADC1 atten2
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 4
|
||||
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000003FFU
|
||||
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 14
|
||||
/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_2_248 0x000000FFU
|
||||
#define EFUSE_RESERVED_2_248_M (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S)
|
||||
#define EFUSE_RESERVED_2_248_V 0x000000FFU
|
||||
#define EFUSE_RESERVED_2_248_S 24
|
||||
|
||||
/** EFUSE_RD_USR_DATA0_REG register
|
||||
* Register $n of BLOCK3 (user).
|
||||
@ -1654,49 +1843,168 @@ extern "C" {
|
||||
* Register $n of BLOCK10 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
|
||||
/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
|
||||
* HI_DOUT of ADC2 atten0
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
|
||||
#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_0_S 0
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN0 0x000003FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN0_M (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S)
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN0_V 0x000003FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN0_S 0
|
||||
/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0;
|
||||
* HI_DOUT of ADC2 atten1
|
||||
*/
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN1 0x000003FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN1_M (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S)
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN1_V 0x000003FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN1_S 10
|
||||
/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0;
|
||||
* HI_DOUT of ADC2 atten2
|
||||
*/
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN2 0x000003FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN2_M (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S)
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN2_V 0x000003FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN2_S 20
|
||||
/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0;
|
||||
* HI_DOUT of ADC2 atten3
|
||||
*/
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3 0x00000003U
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_M (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S)
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_V 0x00000003U
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_S 30
|
||||
|
||||
/** EFUSE_RD_SYS_PART2_DATA1_REG register
|
||||
* Register $n of BLOCK9 (KEY5).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
|
||||
/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
|
||||
* HI_DOUT of ADC2 atten3
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
|
||||
#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_1_S 0
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1 0x000000FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S)
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V 0x000000FFU
|
||||
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S 0
|
||||
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
|
||||
* Gap between ADC1_ch0 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 8
|
||||
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
|
||||
* Gap between ADC1_ch1 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 12
|
||||
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
|
||||
* Gap between ADC1_ch2 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 16
|
||||
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
|
||||
* Gap between ADC1_ch3 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 20
|
||||
/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
|
||||
* Gap between ADC1_ch4 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 24
|
||||
/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
|
||||
* Gap between ADC1_ch5 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 28
|
||||
|
||||
/** EFUSE_RD_SYS_PART2_DATA2_REG register
|
||||
* Register $n of BLOCK10 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
|
||||
/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
|
||||
* Gap between ADC1_ch6 and average initcode
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
|
||||
#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_2_S 0
|
||||
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S 0
|
||||
/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0;
|
||||
* Gap between ADC1_ch7 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S 4
|
||||
/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
|
||||
* Gap between ADC2_ch0 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S 8
|
||||
/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
|
||||
* Gap between ADC2_ch1 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S 12
|
||||
/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
|
||||
* Gap between ADC2_ch2 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S 16
|
||||
/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
|
||||
* Gap between ADC2_ch3 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S 20
|
||||
/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
|
||||
* Gap between ADC2_ch4 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S 24
|
||||
/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
|
||||
* Gap between ADC2_ch5 and average initcode
|
||||
*/
|
||||
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
|
||||
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S)
|
||||
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
|
||||
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S 28
|
||||
|
||||
/** EFUSE_RD_SYS_PART2_DATA3_REG register
|
||||
* Register $n of BLOCK10 (system).
|
||||
*/
|
||||
#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
|
||||
/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
|
||||
#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU
|
||||
#define EFUSE_SYS_DATA_PART2_3_S 0
|
||||
#define EFUSE_TEMPERATURE_SENSOR 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
|
||||
#define EFUSE_TEMPERATURE_SENSOR_V 0x000001FFU
|
||||
#define EFUSE_TEMPERATURE_SENSOR_S 0
|
||||
/** EFUSE_RESERVED_10_105 : R; bitpos: [31:9]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
#define EFUSE_RESERVED_10_105 0x007FFFFFU
|
||||
#define EFUSE_RESERVED_10_105_M (EFUSE_RESERVED_10_105_V << EFUSE_RESERVED_10_105_S)
|
||||
#define EFUSE_RESERVED_10_105_V 0x007FFFFFU
|
||||
#define EFUSE_RESERVED_10_105_S 9
|
||||
|
||||
/** EFUSE_RD_SYS_PART2_DATA4_REG register
|
||||
* Register $n of BLOCK10 (system).
|
||||
|
||||
@ -607,10 +607,18 @@ typedef union {
|
||||
* Package version
|
||||
*/
|
||||
uint32_t pkg_version:3;
|
||||
/** reserved_1_87 : R; bitpos: [31:23]; default: 0;
|
||||
/** reserved_1_87 : R; bitpos: [23]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_87:9;
|
||||
uint32_t reserved_1_87:1;
|
||||
/** ldo_vo1_dref : R; bitpos: [27:24]; default: 0;
|
||||
* Output VO1 parameter
|
||||
*/
|
||||
uint32_t ldo_vo1_dref:4;
|
||||
/** ldo_vo2_dref : R; bitpos: [31:28]; default: 0;
|
||||
* Output VO2 parameter
|
||||
*/
|
||||
uint32_t ldo_vo2_dref:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys_2_reg_t;
|
||||
@ -620,14 +628,30 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
|
||||
* Reserved.
|
||||
/** ldo_vo1_mul : R; bitpos: [2:0]; default: 0;
|
||||
* Output VO1 parameter
|
||||
*/
|
||||
uint32_t mac_reserved_2:18;
|
||||
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
|
||||
* Stores the first 14 bits of the zeroth part of system data.
|
||||
uint32_t ldo_vo1_mul:3;
|
||||
/** ldo_vo2_mul : R; bitpos: [5:3]; default: 0;
|
||||
* Output VO2 parameter
|
||||
*/
|
||||
uint32_t sys_data_part0_0:14;
|
||||
uint32_t ldo_vo2_mul:3;
|
||||
/** ldo_vo3_k : R; bitpos: [13:6]; default: 0;
|
||||
* Output VO3 calibration parameter
|
||||
*/
|
||||
uint32_t ldo_vo3_k:8;
|
||||
/** ldo_vo3_vos : R; bitpos: [19:14]; default: 0;
|
||||
* Output VO3 calibration parameter
|
||||
*/
|
||||
uint32_t ldo_vo3_vos:6;
|
||||
/** ldo_vo3_c : R; bitpos: [25:20]; default: 0;
|
||||
* Output VO3 calibration parameter
|
||||
*/
|
||||
uint32_t ldo_vo3_c:6;
|
||||
/** ldo_vo4_k : R; bitpos: [31:26]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
uint32_t ldo_vo4_k:6;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys_3_reg_t;
|
||||
@ -637,10 +661,38 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the first 32 bits of the zeroth part of system data.
|
||||
/** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
uint32_t sys_data_part0_1:32;
|
||||
uint32_t ldo_vo4_k_1:2;
|
||||
/** ldo_vo4_vos : R; bitpos: [7:2]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
uint32_t ldo_vo4_vos:6;
|
||||
/** ldo_vo4_c : R; bitpos: [13:8]; default: 0;
|
||||
* Output VO4 calibration parameter
|
||||
*/
|
||||
uint32_t ldo_vo4_c:6;
|
||||
/** reserved_1_142 : R; bitpos: [15:14]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_142:2;
|
||||
/** active_hp_dbias : R; bitpos: [19:16]; default: 0;
|
||||
* Active HP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t active_hp_dbias:4;
|
||||
/** active_lp_dbias : R; bitpos: [23:20]; default: 0;
|
||||
* Active LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t active_lp_dbias:4;
|
||||
/** lslp_hp_dbias : R; bitpos: [27:24]; default: 0;
|
||||
* LSLP HP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t lslp_hp_dbias:4;
|
||||
/** dslp_dbg : R; bitpos: [31:28]; default: 0;
|
||||
* DSLP BDG of fixed voltage
|
||||
*/
|
||||
uint32_t dslp_dbg:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys_4_reg_t;
|
||||
@ -650,10 +702,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the second 32 bits of the zeroth part of system data.
|
||||
/** dslp_lp_dbias : R; bitpos: [4:0]; default: 0;
|
||||
* DSLP LP DBIAS of fixed voltage
|
||||
*/
|
||||
uint32_t sys_data_part0_2:32;
|
||||
uint32_t dslp_lp_dbias:5;
|
||||
/** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0;
|
||||
* DBIAS gap between LP and DCDC
|
||||
*/
|
||||
uint32_t lp_dcdc_dbias_vol_gap:5;
|
||||
/** reserved_1_170 : R; bitpos: [31:10]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_1_170:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_mac_sys_5_reg_t;
|
||||
@ -715,10 +775,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fourth 32 bits of the first part of system data.
|
||||
/** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0;
|
||||
* Average initcode of ADC1 atten0
|
||||
*/
|
||||
uint32_t sys_data_part1_4:32;
|
||||
uint32_t adc1_ave_initcode_atten0:10;
|
||||
/** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0;
|
||||
* Average initcode of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten1:10;
|
||||
/** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0;
|
||||
* Average initcode of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten2:10;
|
||||
/** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0;
|
||||
* Average initcode of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_ave_initcode_atten3:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data4_reg_t;
|
||||
@ -728,10 +800,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the fifth 32 bits of the first part of system data.
|
||||
/** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0;
|
||||
* Average initcode of ADC1 atten3
|
||||
*/
|
||||
uint32_t sys_data_part1_5:32;
|
||||
uint32_t adc1_ave_initcode_atten3_1:8;
|
||||
/** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0;
|
||||
* Average initcode of ADC2 atten0
|
||||
*/
|
||||
uint32_t adc2_ave_initcode_atten0:10;
|
||||
/** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0;
|
||||
* Average initcode of ADC2 atten1
|
||||
*/
|
||||
uint32_t adc2_ave_initcode_atten1:10;
|
||||
/** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0;
|
||||
* Average initcode of ADC2 atten2
|
||||
*/
|
||||
uint32_t adc2_ave_initcode_atten2:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data5_reg_t;
|
||||
@ -741,10 +825,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the sixth 32 bits of the first part of system data.
|
||||
/** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0;
|
||||
* Average initcode of ADC2 atten2
|
||||
*/
|
||||
uint32_t sys_data_part1_6:32;
|
||||
uint32_t adc2_ave_initcode_atten2_1:6;
|
||||
/** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0;
|
||||
* Average initcode of ADC2 atten3
|
||||
*/
|
||||
uint32_t adc2_ave_initcode_atten3:10;
|
||||
/** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0;
|
||||
* HI_DOUT of ADC1 atten0
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten0:10;
|
||||
/** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten1:6;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data6_reg_t;
|
||||
@ -754,10 +850,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the seventh 32 bits of the first part of system data.
|
||||
/** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0;
|
||||
* HI_DOUT of ADC1 atten1
|
||||
*/
|
||||
uint32_t sys_data_part1_7:32;
|
||||
uint32_t adc1_hi_dout_atten1_1:4;
|
||||
/** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0;
|
||||
* HI_DOUT of ADC1 atten2
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten2:10;
|
||||
/** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0;
|
||||
* HI_DOUT of ADC1 atten3
|
||||
*/
|
||||
uint32_t adc1_hi_dout_atten3:10;
|
||||
/** reserved_2_248 : R; bitpos: [31:24]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_2_248:8;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part1_data7_reg_t;
|
||||
@ -1503,10 +1611,22 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0;
|
||||
* HI_DOUT of ADC2 atten0
|
||||
*/
|
||||
uint32_t sys_data_part2_0:32;
|
||||
uint32_t adc2_hi_dout_atten0:10;
|
||||
/** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0;
|
||||
* HI_DOUT of ADC2 atten1
|
||||
*/
|
||||
uint32_t adc2_hi_dout_atten1:10;
|
||||
/** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0;
|
||||
* HI_DOUT of ADC2 atten2
|
||||
*/
|
||||
uint32_t adc2_hi_dout_atten2:10;
|
||||
/** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0;
|
||||
* HI_DOUT of ADC2 atten3
|
||||
*/
|
||||
uint32_t adc2_hi_dout_atten3:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part2_data0_reg_t;
|
||||
@ -1516,10 +1636,34 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0;
|
||||
* HI_DOUT of ADC2 atten3
|
||||
*/
|
||||
uint32_t sys_data_part2_1:32;
|
||||
uint32_t adc2_hi_dout_atten3_1:8;
|
||||
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
|
||||
* Gap between ADC1_ch0 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch0_atten0_initcode_diff:4;
|
||||
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
|
||||
* Gap between ADC1_ch1 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch1_atten0_initcode_diff:4;
|
||||
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
|
||||
* Gap between ADC1_ch2 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch2_atten0_initcode_diff:4;
|
||||
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
|
||||
* Gap between ADC1_ch3 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch3_atten0_initcode_diff:4;
|
||||
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
|
||||
* Gap between ADC1_ch4 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch4_atten0_initcode_diff:4;
|
||||
/** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
|
||||
* Gap between ADC1_ch5 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch5_atten0_initcode_diff:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part2_data1_reg_t;
|
||||
@ -1529,10 +1673,38 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0;
|
||||
* Gap between ADC1_ch6 and average initcode
|
||||
*/
|
||||
uint32_t sys_data_part2_2:32;
|
||||
uint32_t adc1_ch6_atten0_initcode_diff:4;
|
||||
/** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0;
|
||||
* Gap between ADC1_ch7 and average initcode
|
||||
*/
|
||||
uint32_t adc1_ch7_atten0_initcode_diff:4;
|
||||
/** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
|
||||
* Gap between ADC2_ch0 and average initcode
|
||||
*/
|
||||
uint32_t adc2_ch0_atten0_initcode_diff:4;
|
||||
/** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
|
||||
* Gap between ADC2_ch1 and average initcode
|
||||
*/
|
||||
uint32_t adc2_ch1_atten0_initcode_diff:4;
|
||||
/** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
|
||||
* Gap between ADC2_ch2 and average initcode
|
||||
*/
|
||||
uint32_t adc2_ch2_atten0_initcode_diff:4;
|
||||
/** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
|
||||
* Gap between ADC2_ch3 and average initcode
|
||||
*/
|
||||
uint32_t adc2_ch3_atten0_initcode_diff:4;
|
||||
/** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
|
||||
* Gap between ADC2_ch4 and average initcode
|
||||
*/
|
||||
uint32_t adc2_ch4_atten0_initcode_diff:4;
|
||||
/** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
|
||||
* Gap between ADC2_ch5 and average initcode
|
||||
*/
|
||||
uint32_t adc2_ch5_atten0_initcode_diff:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part2_data2_reg_t;
|
||||
@ -1542,10 +1714,14 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
|
||||
* Stores the $nth 32 bits of the 2nd part of system data.
|
||||
/** temperature_sensor : R; bitpos: [8:0]; default: 0;
|
||||
* Temperature calibration data
|
||||
*/
|
||||
uint32_t sys_data_part2_3:32;
|
||||
uint32_t temperature_sensor:9;
|
||||
/** reserved_10_105 : R; bitpos: [31:9]; default: 0;
|
||||
* reserved
|
||||
*/
|
||||
uint32_t reserved_10_105:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} efuse_rd_sys_part2_data3_reg_t;
|
||||
|
||||
Reference in New Issue
Block a user