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feat(i2s): add PLL240M clock source on S3 and C6

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Closes https://github.com/espressif/esp-idf/issues/17056
This commit is contained in:
laokaiyao
2025-08-01 11:39:36 +08:00
committed by Kevin (Lao Kaiyao)
parent 3d5d0c939e
commit 3b034c6886
4 changed files with 19 additions and 3 deletions
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6
components/hal/esp32c6/include/hal/i2s_ll.h
View File

@@ -220,6 +220,9 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
case I2S_CLK_SRC_XTAL: case I2S_CLK_SRC_XTAL:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0; PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 0;
break; break;
case I2S_CLK_SRC_PLL_240M:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 1;
break;
case I2S_CLK_SRC_PLL_160M: case I2S_CLK_SRC_PLL_160M:
PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2; PCR.i2s_tx_clkm_conf.i2s_tx_clkm_sel = 2;
break; break;
@@ -246,6 +249,9 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
case I2S_CLK_SRC_XTAL: case I2S_CLK_SRC_XTAL:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0; PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 0;
break; break;
case I2S_CLK_SRC_PLL_240M:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 1;
break;
case I2S_CLK_SRC_PLL_160M: case I2S_CLK_SRC_PLL_160M:
PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 2; PCR.i2s_rx_clkm_conf.i2s_rx_clkm_sel = 2;
break; break;

6
components/hal/esp32s3/include/hal/i2s_ll.h
View File

@@ -233,6 +233,9 @@ static inline void i2s_ll_tx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
case I2S_CLK_SRC_XTAL: case I2S_CLK_SRC_XTAL:
hw->tx_clkm_conf.tx_clk_sel = 0; hw->tx_clkm_conf.tx_clk_sel = 0;
break; break;
case I2S_CLK_SRC_PLL_240M:
hw->tx_clkm_conf.tx_clk_sel = 1;
break;
case I2S_CLK_SRC_PLL_160M: case I2S_CLK_SRC_PLL_160M:
hw->tx_clkm_conf.tx_clk_sel = 2; hw->tx_clkm_conf.tx_clk_sel = 2;
break; break;
@@ -258,6 +261,9 @@ static inline void i2s_ll_rx_clk_set_src(i2s_dev_t *hw, i2s_clock_src_t src)
case I2S_CLK_SRC_XTAL: case I2S_CLK_SRC_XTAL:
hw->rx_clkm_conf.rx_clk_sel = 0; hw->rx_clkm_conf.rx_clk_sel = 0;
break; break;
case I2S_CLK_SRC_PLL_240M:
hw->rx_clkm_conf.rx_clk_sel = 1;
break;
case I2S_CLK_SRC_PLL_160M: case I2S_CLK_SRC_PLL_160M:
hw->rx_clkm_conf.rx_clk_sel = 2; hw->rx_clkm_conf.rx_clk_sel = 2;
break; break;

3
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@@ -295,13 +295,14 @@ typedef enum {
/** /**
* @brief Array initializer for all supported clock sources of I2S * @brief Array initializer for all supported clock sources of I2S
*/ */
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F240M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
/** /**
* @brief I2S clock source enum * @brief I2S clock source enum
*/ */
typedef enum { typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_F240M, /*!< Select PLL_F240M as the source clock */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */

7
components/soc/esp32s3/include/soc/clk_tree_defs.h
View File

@@ -280,16 +280,19 @@ typedef enum {
/** /**
* @brief Array initializer for all supported clock sources of I2S * @brief Array initializer for all supported clock sources of I2S
*/ */
#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL} #define SOC_I2S_CLKS {SOC_MOD_CLK_PLL_F240M, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_XTAL, I2S_CLK_SRC_EXTERNAL}
/** /**
* @brief I2S clock source enum * @brief I2S clock source enum
*/ */
typedef enum { typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */ I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default source clock */
I2S_CLK_SRC_PLL_240M = SOC_MOD_CLK_PLL_D2, /*!< Select PLL_D2 as the source clock.
It is default to 240MHz while PLL is 480MHz,
but it will be 160MHz if PLL is 320MHz */
I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */ I2S_CLK_SRC_PLL_160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */ I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
} soc_periph_i2s_clk_src_t; } soc_periph_i2s_clk_src_t;
/////////////////////////////////////////////////I2C//////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////