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Merge branch 'bugfix/esp32s3_rom_has_ets_printf_issue' into 'master'

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esp_rom: fix esp32s3 rom ets_printf bug

See merge request espressif/esp-idf!20590
This commit is contained in:
morris
2022-10-17 17:54:02 +08:00
parent dc09f30778 8774db59f0
commit 3b0354acb8
7 changed files with 7 additions and 24 deletions
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11
components/bootloader_support/src/bootloader_console.c
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@@ -50,12 +50,8 @@ void bootloader_console_init(void)
{ {
const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM; const int uart_num = CONFIG_ESP_CONSOLE_UART_NUM;
#if !ESP_ROM_SUPPORT_MULTIPLE_UART // Install rom uart printf as console.
/* esp_rom_install_channel_put is not available unless multiple UARTs are supported */
esp_rom_install_uart_printf(); esp_rom_install_uart_printf();
#else
esp_rom_install_channel_putc(1, esp_rom_uart_putc);
#endif
// Wait for UART FIFO to be empty. // Wait for UART FIFO to be empty.
esp_rom_uart_tx_wait_idle(0); esp_rom_uart_tx_wait_idle(0);
@@ -64,10 +60,7 @@ void bootloader_console_init(void)
// Some constants to make the following code less upper-case // Some constants to make the following code less upper-case
const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO; const int uart_tx_gpio = CONFIG_ESP_CONSOLE_UART_TX_GPIO;
const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO; const int uart_rx_gpio = CONFIG_ESP_CONSOLE_UART_RX_GPIO;
// Switch to the new UART (this just changes UART number used for esp_rom_printf in ROM code).
#if ESP_ROM_SUPPORT_MULTIPLE_UART
esp_rom_uart_set_as_console(uart_num);
#endif
// If console is attached to UART1 or if non-default pins are used, // If console is attached to UART1 or if non-default pins are used,
// need to reconfigure pins using GPIO matrix // need to reconfigure pins using GPIO matrix
if (uart_num != 0 || if (uart_num != 0 ||

4
components/esp_rom/esp32/Kconfig.soc_caps.in
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@@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE
bool bool
default y default y
config ESP_ROM_SUPPORT_MULTIPLE_UART
bool
default y
config ESP_ROM_NEEDS_SWSETUP_WORKAROUND config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
bool bool
default y default y

1
components/esp_rom/esp32/esp_rom_caps.h
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@@ -9,5 +9,4 @@
#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library
#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging
#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing

4
components/esp_rom/esp32s2/Kconfig.soc_caps.in
View File

@@ -7,10 +7,6 @@ config ESP_ROM_HAS_CRC_LE
bool bool
default y default y
config ESP_ROM_SUPPORT_MULTIPLE_UART
bool
default y
config ESP_ROM_NEEDS_SWSETUP_WORKAROUND config ESP_ROM_NEEDS_SWSETUP_WORKAROUND
bool bool
default y default y

1
components/esp_rom/esp32s2/esp_rom_caps.h
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@@ -7,5 +7,4 @@
#pragma once #pragma once
#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging
#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing

8
components/esp_rom/esp32s3/Kconfig.soc_caps.in
View File

@@ -15,10 +15,6 @@ config ESP_ROM_HAS_JPEG_DECODE
bool bool
default y default y
config ESP_ROM_SUPPORT_MULTIPLE_UART
bool
default y
config ESP_ROM_UART_CLK_IS_XTAL config ESP_ROM_UART_CLK_IS_XTAL
bool bool
default y default y
@@ -54,3 +50,7 @@ config ESP_ROM_HAS_LAYOUT_TABLE
config ESP_ROM_HAS_SPI_FLASH config ESP_ROM_HAS_SPI_FLASH
bool bool
default y default y
config ESP_ROM_HAS_ETS_PRINTF_BUG
bool
default y

2
components/esp_rom/esp32s3/esp_rom_caps.h
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@@ -9,7 +9,6 @@
#define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian #define ESP_ROM_HAS_CRC_LE (1) // ROM CRC library supports Little Endian
#define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian #define ESP_ROM_HAS_CRC_BE (1) // ROM CRC library supports Big Endian
#define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library #define ESP_ROM_HAS_JPEG_DECODE (1) // ROM has JPEG decode library
#define ESP_ROM_SUPPORT_MULTIPLE_UART (1) // ROM has multiple UARTs available for logging
#define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM #define ESP_ROM_UART_CLK_IS_XTAL (1) // UART clock source is selected to XTAL in ROM
#define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking #define ESP_ROM_HAS_RETARGETABLE_LOCKING (1) // ROM was built with retargetable locking
#define ESP_ROM_USB_SERIAL_DEVICE_NUM (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM. #define ESP_ROM_USB_SERIAL_DEVICE_NUM (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
@@ -19,3 +18,4 @@
#define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing #define ESP_ROM_NEEDS_SWSETUP_WORKAROUND (1) // ROM uses 32-bit time_t. A workaround is required to prevent printf functions from crashing
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table #define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
#define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver #define ESP_ROM_HAS_SPI_FLASH (1) // ROM has the implementation of SPI Flash driver
#define ESP_ROM_HAS_ETS_PRINTF_BUG (1) // ROM has ets_printf bug when disable the ROM log either by eFuse or RTC storage register