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Merge branch 'mbedtls/ecc_alt' into 'master'

Browse Source 
mbedtls: Added ECC hardware accelerator support on ESP32C2

Closes IDF-3845

See merge request espressif/esp-idf!16667
This commit is contained in:
Mahavir Jain
2022-03-08 22:40:18 +08:00
parent 8b902739ac 5ca79a00dd
commit 3da54c4f8e
19 changed files with 1164 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
components/hal/CMakeLists.txt
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@@ -156,6 +156,7 @@ if(NOT BOOTLOADER_BUILD)
if(${target} STREQUAL "esp32c2")
list(APPEND srcs
"ecc_hal.c"
"gdma_hal.c"
"spi_flash_hal_gpspi.c"
"spi_slave_hd_hal.c"

82
components/hal/ecc_hal.c Normal file
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@@ -0,0 +1,82 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/ecc_hal.h"
#include "hal/ecc_ll.h"
void ecc_hal_set_mode(ecc_mode_t mode)
{
ecc_ll_set_mode(mode);
}
void ecc_hal_set_curve(ecc_curve_t curve)
{
ecc_ll_set_curve(curve);
}
void ecc_hal_start_calc(void)
{
ecc_ll_clear_interrupt();
ecc_ll_start_calc();
}
int ecc_hal_is_calc_finished(void)
{
return ecc_ll_is_calc_finished();
}
static void clear_param_registers(void)
{
uint8_t buf[32] = {0};
ecc_ll_write_param(ECC_PARAM_PX, buf, sizeof(buf));
ecc_ll_write_param(ECC_PARAM_PY, buf, sizeof(buf));
ecc_ll_write_param(ECC_PARAM_K, buf, sizeof(buf));
}
void ecc_hal_write_mul_param(const uint8_t *k, const uint8_t *px, const uint8_t *py, uint16_t len)
{
ecc_curve_t curve = len == 32 ? ECC_CURVE_SECP256R1 : ECC_CURVE_SECP192R1;
ecc_ll_set_curve(curve);
clear_param_registers();
ecc_ll_write_param(ECC_PARAM_K, k, len);
ecc_ll_write_param(ECC_PARAM_PX, px, len);
ecc_ll_write_param(ECC_PARAM_PY, py, len);
}
void ecc_hal_write_verify_param(const uint8_t *px, const uint8_t *py, uint16_t len)
{
ecc_curve_t curve = len == 32 ? ECC_CURVE_SECP256R1 : ECC_CURVE_SECP192R1;
ecc_ll_set_curve(curve);
clear_param_registers();
ecc_ll_write_param(ECC_PARAM_PX, px, len);
ecc_ll_write_param(ECC_PARAM_PY, py, len);
}
int ecc_hal_read_mul_result(uint8_t *rx, uint8_t *ry, uint16_t len)
{
ecc_mode_t mode = ecc_ll_get_mode();
if (mode == ECC_MODE_VERIFY_THEN_POINT_MUL) {
if (!ecc_ll_get_verification_result()) {
memset(rx, 0x0, len);
memset(ry, 0x0, len);
return -1;
}
}
ecc_ll_read_param(ECC_PARAM_PX, rx, len);
ecc_ll_read_param(ECC_PARAM_PY, ry, len);
return 0;
}
int ecc_hal_read_verify_result(void)
{
return ecc_ll_get_verification_result();
}

6
components/hal/esp32c2/include/hal/clk_gate_ll.h
View File

@@ -40,6 +40,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return SYSTEM_SPI2_CLK_EN;
case PERIPH_GDMA_MODULE:
return SYSTEM_DMA_CLK_EN;
case PERIPH_ECC_MODULE:
return SYSTEM_CRYPTO_ECC_CLK_EN;
case PERIPH_SHA_MODULE:
return SYSTEM_CRYPTO_SHA_CLK_EN;
case PERIPH_RNG_MODULE:
@@ -81,6 +83,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return SYSTEM_SYSTIMER_RST;
case PERIPH_GDMA_MODULE:
return SYSTEM_DMA_RST;
case PERIPH_ECC_MODULE:
return SYSTEM_CRYPTO_ECC_RST;
case PERIPH_SPI_MODULE:
return SYSTEM_SPI01_RST;
case PERIPH_SPI2_MODULE:
@@ -111,6 +115,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
case PERIPH_SHA_MODULE:
case PERIPH_GDMA_MODULE:
case PERIPH_ECC_MODULE:
return SYSTEM_PERIP_CLK_EN1_REG;
default:
return SYSTEM_PERIP_CLK_EN0_REG;
@@ -130,6 +135,7 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
case PERIPH_SHA_MODULE:
case PERIPH_GDMA_MODULE:
case PERIPH_ECC_MODULE:
return SYSTEM_PERIP_RST_EN1_REG;
default:
return SYSTEM_PERIP_RST_EN0_REG;

147
components/hal/esp32c2/include/hal/ecc_ll.h Normal file
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@@ -0,0 +1,147 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <string.h>
#include "hal/assert.h"
#include "soc/ecc_mult_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ECC_PARAM_PX = 0x0,
ECC_PARAM_PY,
ECC_PARAM_K,
} ecc_ll_param_t;
static inline void ecc_ll_enable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1);
}
static inline void ecc_ll_disable_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0);
}
static inline void ecc_ll_clear_interrupt(void)
{
REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1);
}
static inline void ecc_ll_set_mode(ecc_mode_t mode)
{
switch(mode) {
case ECC_MODE_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
break;
case ECC_MODE_INVERSE_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 1);
break;
case ECC_MODE_VERIFY:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
break;
case ECC_MODE_VERIFY_THEN_POINT_MUL:
REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
break;
default:
HAL_ASSERT(false && "Unsupported mode");
break;
}
}
static inline void ecc_ll_set_curve(ecc_curve_t curve)
{
switch(curve) {
case ECC_CURVE_SECP256R1:
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
break;
case ECC_CURVE_SECP192R1:
REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
break;
default:
HAL_ASSERT(false && "Unsupported curve");
return;
}
}
static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len)
{
uint32_t reg;
uint32_t word;
switch (param) {
case ECC_PARAM_PX:
reg = ECC_MULT_PX_1_REG;
break;
case ECC_PARAM_PY:
reg = ECC_MULT_PY_1_REG;
break;
case ECC_PARAM_K:
reg = ECC_MULT_K_1_REG;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
for (int i = 0; i < len; i += 4) {
memcpy(&word, buf + i, 4);
REG_WRITE(reg + i, word);
}
}
static inline void ecc_ll_start_calc(void)
{
REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START);
}
static inline int ecc_ll_is_calc_finished(void)
{
return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW);
}
static inline ecc_mode_t ecc_ll_get_mode(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE);
}
static inline int ecc_ll_get_verification_result(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT);
}
static inline ecc_curve_t ecc_ll_get_curve(void)
{
return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
}
static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len)
{
uint32_t reg;
switch (param) {
case ECC_PARAM_PX:
reg = ECC_MULT_PX_1_REG;
break;
case ECC_PARAM_PY:
reg = ECC_MULT_PY_1_REG;
break;
case ECC_PARAM_K:
reg = ECC_MULT_K_1_REG;
break;
default:
HAL_ASSERT(false && "Invalid parameter");
return;
}
memcpy(buf, (void *)reg, len);
}
#ifdef __cplusplus
}
#endif

101
components/hal/include/hal/ecc_hal.h Normal file
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@@ -0,0 +1,101 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The HAL is not public api, don't use in application code.
* See readme.md in soc/README.md
******************************************************************************/
#pragma once
#include "stdint.h"
#include "hal/ecc_types.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set the work mode of the operation
*
* @param mode Mode of operation
*/
void ecc_hal_set_mode(ecc_mode_t mode);
/**
* @brief Set the ECC curve of operation
*
* @param curve Curve to use for operation
*/
void ecc_hal_set_curve(ecc_curve_t curve);
/**
* @brief Start calculation
*
*/
void ecc_hal_start_calc(void);
/**
* @brief Check whether the calculation has finished
*
* @return - 1 if the hardware has finished calculating
* - 0 otherwise
*/
int ecc_hal_is_calc_finished(void);
/**
* @brief Write parameters for point multiplication (K * (Px, Py))
*
* @param k Scalar value
* @param px X coordinate of the ECC point
* @param py Y coordinate of the ECC point
* @param len Length (in bytes) of the ECC point
* - 32 bytes for SECP256R1
* - 24 bytes for SECP192R1
*/
void ecc_hal_write_mul_param(const uint8_t *k, const uint8_t *px, const uint8_t *py, uint16_t len);
/**
* @brief Write parameters for point verification,
* i.e to check if the point lies on the curve
*
* @param px X coordinate of the ECC point
* @param py Y coordinate of the ECC point
* @param len Length (in bytes) of the ECC point
* - 32 for SECP256R1
* - 24 for SECP192R1
*/
void ecc_hal_write_verify_param(const uint8_t *px, const uint8_t *py, uint16_t len);
/**
* @brief Read point multiplication result
*
* @param rx X coordinate of the multiplication result
* @param ry Y coordinate of the multiplication result
* @param len Length (in bytes) of the ECC point
* - 32 for SECP256R1
* - 24 for SECP192R1
*
* @return - 0 if the operation was successful
* - -1 if the operation was not successful
*
* In case the operation is not successful, rx and ry will contain
* all zeros
*/
int ecc_hal_read_mul_result(uint8_t *rx, uint8_t *ry, uint16_t len);
/**
* @brief Read point verification result
*
* @return - 1 if point lies on curve
* - 0 otherwise
*/
int ecc_hal_read_verify_result(void);
#ifdef __cplusplus
}
#endif

18
components/hal/include/hal/ecc_types.h Normal file
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@@ -0,0 +1,18 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
typedef enum {
ECC_MODE_POINT_MUL = 0x0, // (Rx, Ry) = K * (Px, Py)
ECC_MODE_INVERSE_MUL, // R = K^(-1) * Py
ECC_MODE_VERIFY, // Check if (Px, Py) are points on the curve
ECC_MODE_VERIFY_THEN_POINT_MUL, // Verify and then perform point multiplication
} ecc_mode_t;
typedef enum {
ECC_CURVE_SECP192R1 = 0x0,
ECC_CURVE_SECP256R1,
} ecc_curve_t;

5
components/mbedtls/CMakeLists.txt
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@@ -182,6 +182,11 @@ if(CONFIG_MBEDTLS_HARDWARE_GCM)
target_sources(mbedcrypto PRIVATE "${COMPONENT_DIR}/port/aes/esp_aes_gcm.c")
endif()
if(CONFIG_MBEDTLS_HARDWARE_ECC)
target_sources(mbedcrypto PRIVATE "${COMPONENT_DIR}/port/ecc/esp_ecc.c"
"${COMPONENT_DIR}/port/ecc/ecc_alt.c")
endif()
if(CONFIG_MBEDTLS_ROM_MD5)
target_sources(mbedcrypto PRIVATE "${COMPONENT_DIR}/port/md/esp_md.c")
endif()

16
components/mbedtls/Kconfig
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@@ -414,6 +414,22 @@ menu "mbedTLS"
SHA hardware acceleration is faster than software in some situations but
slower in others. You should benchmark to find the best setting for you.
config MBEDTLS_HARDWARE_ECC
bool "Enable hardware ECC acceleration"
default y
depends on SOC_ECC_SUPPORTED
help
Enable hardware accelerated ECC point multiplication and point verification for points
on curve SECP192R1 and SECP256R1 in mbedTLS
config MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK
bool "Fallback to software implementation for curves not supported in hardware"
depends on MBEDTLS_HARDWARE_ECC
default y
help
Fallback to software implementation of ECC point multiplication and point verification
for curves not supported in hardware.
config MBEDTLS_ROM_MD5
bool "Use MD5 implementation in ROM"
default y

129
components/mbedtls/port/ecc/ecc_alt.c Normal file
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@@ -0,0 +1,129 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include "soc/hwcrypto_periph.h"
#include "ecc_impl.h"
/* TBD: Remove this and use proper getter/setter methods to access
* private members of EC data structures once they are available
* in mbedTLS stack */
#define MBEDTLS_ALLOW_PRIVATE_ACCESS
#include "mbedtls/ecp.h"
#include "mbedtls/platform_util.h"
#define ECP_VALIDATE_RET( cond ) \
MBEDTLS_INTERNAL_VALIDATE_RET( cond, MBEDTLS_ERR_ECP_BAD_INPUT_DATA )
#define ECP_VALIDATE( cond ) \
MBEDTLS_INTERNAL_VALIDATE( cond )
#if defined(MBEDTLS_ECP_MUL_ALT) || defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK)
#define MAX_SIZE 32 // 256 bits
static int esp_mbedtls_ecp_point_multiply(const mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
const mbedtls_mpi *m, const mbedtls_ecp_point *P)
{
int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
uint8_t x_tmp[MAX_SIZE];
uint8_t y_tmp[MAX_SIZE];
ecc_point_t p_pt = {0};
ecc_point_t r_pt = {0};
p_pt.len = grp->pbits / 8;
memcpy(&p_pt.x, P->X.p, mbedtls_mpi_size(&P->X));
memcpy(&p_pt.y, P->Y.p, mbedtls_mpi_size(&P->Y));
ret = esp_ecc_point_multiply(&p_pt, (uint8_t *)m->p, &r_pt, false);
for (int i = 0; i < MAX_SIZE; i++) {
x_tmp[MAX_SIZE - i - 1] = r_pt.x[i];
y_tmp[MAX_SIZE - i - 1] = r_pt.y[i];
}
mbedtls_mpi_read_binary(&R->X, x_tmp, MAX_SIZE);
mbedtls_mpi_read_binary(&R->Y, y_tmp, MAX_SIZE);
mbedtls_mpi_lset(&R->Z, 1);
return ret;
}
/*
* Restartable multiplication R = m * P
*/
int mbedtls_ecp_mul_restartable( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
const mbedtls_mpi *m, const mbedtls_ecp_point *P,
int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
mbedtls_ecp_restart_ctx *rs_ctx )
{
int ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
if (grp->id != MBEDTLS_ECP_DP_SECP192R1 && grp->id != MBEDTLS_ECP_DP_SECP256R1) {
#if defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK)
return mbedtls_ecp_mul_restartable_soft(grp, R, m, P, f_rng, p_rng, rs_ctx);
#else
return ret;
#endif
}
ECP_VALIDATE_RET( grp != NULL );
ECP_VALIDATE_RET( R != NULL );
ECP_VALIDATE_RET( m != NULL );
ECP_VALIDATE_RET( P != NULL );
/* Common sanity checks */
MBEDTLS_MPI_CHK( mbedtls_ecp_check_privkey( grp, m ) );
MBEDTLS_MPI_CHK( mbedtls_ecp_check_pubkey( grp, P ) );
ret = MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
/* MBEDTLS_MPI_CHK macro assigns the return value of the function to
* `ret` variable
*/
MBEDTLS_MPI_CHK( esp_mbedtls_ecp_point_multiply(grp, R, m, P) );
cleanup:
return( ret );
}
#endif /* defined(MBEDTLS_ECP_MUL_ALT) || defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK) */
#if defined(MBEDTLS_ECP_VERIFY_ALT) || defined(MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK)
int mbedtls_ecp_check_pubkey( const mbedtls_ecp_group *grp,
const mbedtls_ecp_point *pt )
{
int res;
ecc_point_t point;
if (grp->id != MBEDTLS_ECP_DP_SECP192R1 && grp->id != MBEDTLS_ECP_DP_SECP256R1) {
#if defined(MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK)
return mbedtls_ecp_check_pubkey_soft(grp, pt);
#else
return MBEDTLS_ERR_ECP_BAD_INPUT_DATA;
#endif
}
ECP_VALIDATE_RET( grp != NULL );
ECP_VALIDATE_RET( pt != NULL );
/* Must use affine coordinates */
if( mbedtls_mpi_cmp_int( &pt->Z, 1 ) != 0 )
return( MBEDTLS_ERR_ECP_INVALID_KEY );
mbedtls_platform_zeroize((void *)&point, sizeof(ecc_point_t));
memcpy(&point.x, pt->X.p, mbedtls_mpi_size(&pt->X));
memcpy(&point.y, pt->Y.p, mbedtls_mpi_size(&pt->Y));
point.len = grp->pbits / 8;
res = esp_ecc_point_verify(&point);
if (res == 1) {
return 0;
} else {
return MBEDTLS_ERR_ECP_INVALID_KEY;
}
}
#endif /* defined(MBEDTLS_ECP_VERIFY_ALT) || defined(MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK) */

78
components/mbedtls/port/ecc/esp_ecc.c Normal file
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@@ -0,0 +1,78 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <stdio.h>
#include "soc/ecc_mult_reg.h"
#include "soc/system_reg.h"
#include "esp_private/periph_ctrl.h"
#include "ecc_impl.h"
#include "hal/ecc_hal.h"
static _lock_t s_crypto_ecc_lock;
static void esp_ecc_acquire_hardware(void)
{
_lock_acquire(&s_crypto_ecc_lock);
periph_module_enable(PERIPH_ECC_MODULE);
}
static void esp_ecc_release_hardware(void)
{
periph_module_disable(PERIPH_ECC_MODULE);
_lock_release(&s_crypto_ecc_lock);
}
int esp_ecc_point_multiply(const ecc_point_t *point, const uint8_t *scalar, ecc_point_t *result, bool verify_first)
{
int ret = -1;
uint16_t len = point->len;
ecc_mode_t work_mode = verify_first ? ECC_MODE_VERIFY_THEN_POINT_MUL : ECC_MODE_POINT_MUL;
esp_ecc_acquire_hardware();
ecc_hal_write_mul_param(scalar, point->x, point->y, len);
ecc_hal_set_mode(work_mode);
ecc_hal_start_calc();
memset(result, 0, sizeof(ecc_point_t));
result->len = len;
while (!ecc_hal_is_calc_finished()) {
;
}
ret = ecc_hal_read_mul_result(result->x, result->y, len);
esp_ecc_release_hardware();
return ret;
}
int esp_ecc_point_verify(const ecc_point_t *point)
{
int result;
esp_ecc_acquire_hardware();
ecc_hal_write_verify_param(point->x, point->y, point->len);
ecc_hal_set_mode(ECC_MODE_VERIFY);
ecc_hal_start_calc();
while (!ecc_hal_is_calc_finished()) {
;
}
result = ecc_hal_read_verify_result();
esp_ecc_release_hardware();
return result;
}

60
components/mbedtls/port/include/ecc_impl.h Normal file
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@@ -0,0 +1,60 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#define P256_LEN (256/8)
#define P192_LEN (192/8)
/* Note: x & y are stored in little endian order (same as CPU byte order, and order used internally by most libraries).
This is the same order used in hardware
Note this is opposite to most byte string formats used to represent keys, which are often big endian
*/
typedef struct {
uint8_t x[P256_LEN]; /* Little endian order */
uint8_t y[P256_LEN]; /* Little endian order */
unsigned len; /* P192_LEN or P256_LEN */
} ecc_point_t;
/**
* @brief Perform ECC point multiplication (R = K * (Px, Py))
*
* @param point ECC point (multiplicand)
* @param scalar Integer represented in byte array format (multiplier)
* @param result Result of the multiplication
* @param verify_first Verify that the point is on the curve before performing multiplication
*
* @return - 0 if the multiplication was successful
* - -1 otherwise
*
* @note 'scalar' is expected as a byte array in little endian order.
* Most byte string formats used to represent keys are in big endian order.
*/
int esp_ecc_point_multiply(const ecc_point_t *point, const uint8_t *scalar, ecc_point_t *result, bool verify_first);
/**
* @brief Perform ECC point verification,
* i.e check whether the point (Px, Py) lies on the curve
*
* @param point ECC point that needs to be verified
*
* @return - 1, if point lies on the curve
* - 0, otherwise
*
*/
int esp_ecc_point_verify(const ecc_point_t *point);
#ifdef __cplusplus
}
#endif

32
components/mbedtls/port/include/mbedtls/ecp.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include_next "mbedtls/ecp.h"
#include "sdkconfig.h"
#ifdef __cplusplus
extern "C" {
#endif
#if defined(MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK)
int mbedtls_ecp_mul_restartable_soft(mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
const mbedtls_mpi *m, const mbedtls_ecp_point *P,
int (*f_rng)(void *, unsigned char *, size_t), void *p_rng,
mbedtls_ecp_restart_ctx *rs_ctx );
#endif
#if defined(MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK)
int mbedtls_ecp_check_pubkey_soft(const mbedtls_ecp_group *grp,
const mbedtls_ecp_point *pt );
#endif
#ifdef __cplusplus
}
#endif

19
components/mbedtls/port/include/mbedtls/esp_config.h
View File

@@ -178,6 +178,25 @@
#define MBEDTLS_ECDSA_VERIFY_ALT
#endif
#ifdef CONFIG_MBEDTLS_HARDWARE_ECC
#ifdef CONFIG_MBEDTLS_ECC_OTHER_CURVES_SOFT_FALLBACK
/* Use hardware accelerator for SECP192R1 and SECP256R1 curves,
* software implementation for rest of the curves
*/
#define MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK
#define MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK
#else
/* Only hardware accelerator support */
#define MBEDTLS_ECP_MUL_ALT
#define MBEDTLS_ECP_VERIFY_ALT
#endif
#else
#undef MBEDTLS_ECP_MUL_ALT
#undef MBEDTLS_ECP_MUL_ALT_SOFT_FALLBACK
#undef MBEDTLS_ECP_VERIFY_ALT
#undef MBEDTLS_ECP_VERIFY_ALT_SOFT_FALLBACK
#endif
/**
* \def MBEDTLS_ENTROPY_HARDWARE_ALT
*

172
components/mbedtls/test/test_ecp.c
View File

@@ -10,7 +10,7 @@
#include <string.h>
#include <stdio.h>
#include <stdbool.h>
#include <esp_system.h>
#include <esp_random.h>
/* ToDo - Remove this once appropriate solution is available.
We need to define this for the file as ssl_misc.h uses private structures from mbedtls,
@@ -84,3 +84,173 @@ TEST_CASE("mbedtls ECP mul w/ koblitz", "[mbedtls]")
mbedtls_ctr_drbg_free(&ctxRandom);
mbedtls_entropy_free(&ctxEntropy);
}
#if CONFIG_MBEDTLS_HARDWARE_ECC
/*
* Coordinates and integers stored in big endian format
*/
const uint8_t ecc_p192_point_x[] = {
0x18, 0x8D, 0xA8, 0x0E, 0xB0, 0x30, 0x90, 0xF6,
0x7C, 0xBF, 0x20, 0xEB, 0x43, 0xA1, 0x88, 0x00,
0xF4, 0xFF, 0x0A, 0xFD, 0x82, 0xFF, 0x10, 0x12
};
const uint8_t ecc_p192_point_y[] = {
0x07, 0x19, 0x2B, 0x95, 0xFF, 0xC8, 0xDA, 0x78,
0x63, 0x10, 0x11, 0xED, 0x6B, 0x24, 0xCD, 0xD5,
0x73, 0xF9, 0x77, 0xA1, 0x1E, 0x79, 0x48, 0x11
};
const uint8_t ecc_p192_scalar[] = {
0x6f, 0x18, 0x34, 0xeb, 0x16, 0xb7, 0xac, 0x9f,
0x3c, 0x77, 0x71, 0xb3, 0x02, 0x30, 0x70, 0x48,
0x75, 0x87, 0xbb, 0x6f, 0x80, 0x34, 0x8d, 0x5e
};
const uint8_t ecc_p192_mul_res_x[] = {
0x3F, 0xEE, 0x6F, 0x1F, 0x99, 0xDC, 0xCB, 0x78,
0xB7, 0x47, 0x1C, 0x2A, 0xF5, 0xA0, 0xAC, 0xE6,
0xEC, 0x24, 0x82, 0x37, 0x6C, 0xC0, 0x27, 0xC5,
};
const uint8_t ecc_p192_mul_res_y[] = {
0xDF, 0xF3, 0x9E, 0x76, 0x24, 0xF4, 0xF6, 0xB4,
0xF0, 0x0A, 0x18, 0xE1, 0x0B, 0xD2, 0xD9, 0x83,
0xE8, 0x29, 0x5E, 0xD9, 0x46, 0x54, 0xC3, 0xE1
};
const uint8_t ecc_p256_point_x[] = {
0x6B, 0x17, 0xD1, 0xF2, 0xE1, 0x2C, 0x42, 0x47,
0xF8, 0xBC, 0xE6, 0xE5, 0x63, 0xA4, 0x40, 0xF2,
0x77, 0x03, 0x7D, 0x81, 0x2D, 0xEB, 0x33, 0xA0,
0xF4, 0xA1, 0x39, 0x45, 0xD8, 0x98, 0xC2, 0x96
};
const uint8_t ecc_p256_point_y[] = {
0x4F, 0xE3, 0x42, 0xE2, 0xFE, 0x1A, 0x7F, 0x9B,
0x8E, 0xE7, 0xEB, 0x4A, 0x7C, 0x0F, 0x9E, 0x16,
0x2B, 0xCE, 0x33, 0x57, 0x6B, 0x31, 0x5E, 0xCE,
0xCB, 0xB6, 0x40, 0x68, 0x37, 0xBF, 0x51, 0xF5
};
const uint8_t ecc_p256_scalar[] = {
0xB2, 0xC5, 0x9E, 0x92, 0x64, 0xCD, 0x5F, 0x66,
0x9E, 0xC8, 0x83, 0x6D, 0x99, 0x61, 0x18, 0x72,
0xC8, 0x60, 0x83, 0x1E, 0xE5, 0x79, 0xCC, 0x73,
0xA9, 0xB4, 0x74, 0x85, 0x70, 0x11, 0x2D, 0xA2,
};
const uint8_t ecc_p256_mul_res_x[] = {
0x26, 0x1A, 0x0F, 0xBD, 0xA5, 0xE5, 0x1E, 0xE7,
0xB3, 0xC3, 0xB7, 0x09, 0xD1, 0x4A, 0x7A, 0x2A,
0x16, 0x69, 0x4B, 0xAF, 0x76, 0x5C, 0xD4, 0x0E,
0x93, 0x57, 0xB8, 0x67, 0xF9, 0xA1, 0xE5, 0xE8
};
const uint8_t ecc_p256_mul_res_y[] = {
0xA0, 0xF4, 0x2E, 0x62, 0x36, 0x25, 0x9F, 0xE0,
0xF2, 0xA0, 0x41, 0x42, 0xD2, 0x95, 0x89, 0x41,
0x38, 0xF0, 0xEB, 0x6E, 0xA7, 0x96, 0x29, 0x24,
0xC7, 0xD4, 0x0C, 0x90, 0xA1, 0xC9, 0xD3, 0x3A
};
static int rng_wrapper(void *ctx, unsigned char *buf, size_t len)
{
esp_fill_random(buf, len);
return 0;
}
static void test_ecp_mul(mbedtls_ecp_group_id id, const uint8_t *x_coord, const uint8_t *y_coord, const uint8_t *scalar,
const uint8_t *result_x_coord, const uint8_t *result_y_coord)
{
uint8_t x[32];
uint8_t y[32];
int size;
int ret;
mbedtls_ecp_group grp;
mbedtls_ecp_point R;
mbedtls_ecp_point P;
mbedtls_mpi m;
mbedtls_ecp_group_init(&grp);
mbedtls_ecp_point_init(&R);
mbedtls_ecp_point_init(&P);
mbedtls_mpi_init(&m);
mbedtls_ecp_group_load(&grp, id);
size = grp.pbits / 8;
mbedtls_mpi_read_binary(&m, scalar, size);
mbedtls_mpi_read_binary(&P.X, x_coord, size);
mbedtls_mpi_read_binary(&P.Y, y_coord, size);
mbedtls_mpi_lset(&P.Z, 1);
ret = mbedtls_ecp_mul(&grp, &R, &m, &P, rng_wrapper, NULL);
TEST_ASSERT_EQUAL(0, ret);
mbedtls_mpi_write_binary(&R.X, x, mbedtls_mpi_size(&R.X));
mbedtls_mpi_write_binary(&R.Y, y, mbedtls_mpi_size(&R.Y));
TEST_ASSERT_EQUAL(0, memcmp(x, result_x_coord, mbedtls_mpi_size(&R.X)));
TEST_ASSERT_EQUAL(0, memcmp(y, result_y_coord, mbedtls_mpi_size(&R.Y)));
mbedtls_ecp_point_free(&R);
mbedtls_ecp_point_free(&P);
mbedtls_mpi_free(&m);
mbedtls_ecp_group_free(&grp);
}
TEST_CASE("mbedtls ECP point multiply with SECP192R1", "[mbedtls]")
{
test_ecp_mul(MBEDTLS_ECP_DP_SECP192R1, ecc_p192_point_x, ecc_p192_point_y, ecc_p192_scalar,
ecc_p192_mul_res_x, ecc_p192_mul_res_y);
}
TEST_CASE("mbedtls ECP point multiply with SECP256R1", "[mbedtls]")
{
test_ecp_mul(MBEDTLS_ECP_DP_SECP256R1, ecc_p256_point_x, ecc_p256_point_y, ecc_p256_scalar,
ecc_p256_mul_res_x, ecc_p256_mul_res_y);
}
static void test_ecp_verify(mbedtls_ecp_group_id id, const uint8_t *x_coord, const uint8_t *y_coord)
{
int size;
int ret;
mbedtls_ecp_group grp;
mbedtls_ecp_point P;
mbedtls_ecp_group_init(&grp);
mbedtls_ecp_point_init(&P);
mbedtls_ecp_group_load(&grp, id);
size = grp.pbits / 8;
mbedtls_mpi_read_binary(&P.X, x_coord, size);
mbedtls_mpi_read_binary(&P.Y, y_coord, size);
mbedtls_mpi_lset(&P.Z, 1);
ret = mbedtls_ecp_check_pubkey(&grp, &P);
TEST_ASSERT_EQUAL(0, ret);
mbedtls_ecp_point_free(&P);
mbedtls_ecp_group_free(&grp);
}
TEST_CASE("mbedtls ECP point verify with SECP192R1", "[mbedtls]")
{
test_ecp_verify(MBEDTLS_ECP_DP_SECP192R1, ecc_p192_mul_res_x, ecc_p192_mul_res_y);
}
TEST_CASE("mbedtls ECP point verify with SECP256R1", "[mbedtls]")
{
test_ecp_verify(MBEDTLS_ECP_DP_SECP256R1, ecc_p256_mul_res_x, ecc_p256_mul_res_y);
}
#endif /* CONFIG_MBEDTLS_HARDWARE_ECC */

4
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
View File

@@ -31,6 +31,10 @@ config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
config SOC_ECC_SUPPORTED
bool
default y
config SOC_SUPPORTS_SECURE_DL_MODE
bool
default y

292
components/soc/esp32c2/include/soc/ecc_mult_reg.h Normal file
View File

@@ -0,0 +1,292 @@
/*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc.h"
#ifdef __cplusplus
extern "C" {
#endif
#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xC)
/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/
#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_M (BIT(0))
#define ECC_MULT_CALC_DONE_INT_RAW_V 0x1
#define ECC_MULT_CALC_DONE_INT_RAW_S 0
#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10)
/* ECC_MULT_CALC_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt.*/
#define ECC_MULT_CALC_DONE_INT_ST (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_M (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ST_V 0x1
#define ECC_MULT_CALC_DONE_INT_ST_S 0
#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14)
/* ECC_MULT_CALC_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: The interrupt enable bit for the i2s_rx_done_int interrupt.*/
#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_M (BIT(0))
#define ECC_MULT_CALC_DONE_INT_ENA_V 0x1
#define ECC_MULT_CALC_DONE_INT_ENA_S 0
#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18)
/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/
#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_M (BIT(0))
#define ECC_MULT_CALC_DONE_INT_CLR_V 0x1
#define ECC_MULT_CALC_DONE_INT_CLR_S 0
#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1C)
/* ECC_MULT_VERIFICATION_RESULT : RO/SS ;bitpos:[8] ;default: 1'b0 ; */
/*description: Reserve.*/
#define ECC_MULT_VERIFICATION_RESULT (BIT(8))
#define ECC_MULT_VERIFICATION_RESULT_M (BIT(8))
#define ECC_MULT_VERIFICATION_RESULT_V 0x1
#define ECC_MULT_VERIFICATION_RESULT_S 8
/* ECC_MULT_WORK_MODE : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
/*description: Reserved.*/
#define ECC_MULT_WORK_MODE 0x00000007
#define ECC_MULT_WORK_MODE_M ((ECC_MULT_WORK_MODE_V)<<(ECC_MULT_WORK_MODE_S))
#define ECC_MULT_WORK_MODE_V 0x7
#define ECC_MULT_WORK_MODE_S 5
/* ECC_MULT_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
/*description: clk gate.*/
#define ECC_MULT_CLK_EN (BIT(4))
#define ECC_MULT_CLK_EN_M (BIT(4))
#define ECC_MULT_CLK_EN_V 0x1
#define ECC_MULT_CLK_EN_S 4
/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
/*description: Set this bit to enable slave receiver mode.*/
#define ECC_MULT_SECURITY_MODE (BIT(3))
#define ECC_MULT_SECURITY_MODE_M (BIT(3))
#define ECC_MULT_SECURITY_MODE_V 0x1
#define ECC_MULT_SECURITY_MODE_S 3
/* ECC_MULT_KEY_LENGTH : R/W ;bitpos:[2] ;default: 1'b0 ; */
/*description: Set this bit to start receiving data.*/
#define ECC_MULT_KEY_LENGTH (BIT(2))
#define ECC_MULT_KEY_LENGTH_M (BIT(2))
#define ECC_MULT_KEY_LENGTH_V 0x1
#define ECC_MULT_KEY_LENGTH_S 2
/* ECC_MULT_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */
/*description: Set this bit to reset Rx AFIFO.*/
#define ECC_MULT_RESET (BIT(1))
#define ECC_MULT_RESET_M (BIT(1))
#define ECC_MULT_RESET_V 0x1
#define ECC_MULT_RESET_S 1
/* ECC_MULT_START : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to reset receiver.*/
#define ECC_MULT_START (BIT(0))
#define ECC_MULT_START_M (BIT(0))
#define ECC_MULT_START_V 0x1
#define ECC_MULT_START_S 0
#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xFC)
/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */
/*description: ECC mult version control register.*/
#define ECC_MULT_DATE 0x0FFFFFFF
#define ECC_MULT_DATE_M ((ECC_MULT_DATE_V)<<(ECC_MULT_DATE_S))
#define ECC_MULT_DATE_V 0xFFFFFFF
#define ECC_MULT_DATE_S 0
#define ECC_MULT_K_1_REG (DR_REG_ECC_MULT_BASE + 0x0100)
/* ECC_MULT_MEM_K_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_1 0xFFFFFFFF
#define ECC_MULT_MEM_K_1_M ((ECC_MULT_MEM_K_1_V)<<(ECC_MULT_MEM_K_1_S))
#define ECC_MULT_MEM_K_1_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_1_S 0
#define ECC_MULT_K_2_REG (DR_REG_ECC_MULT_BASE + 0x0104)
/* ECC_MULT_MEM_K_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_2 0xFFFFFFFF
#define ECC_MULT_MEM_K_2_M ((ECC_MULT_MEM_K_2_V)<<(ECC_MULT_MEM_K_2_S))
#define ECC_MULT_MEM_K_2_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_2_S 0
#define ECC_MULT_K_3_REG (DR_REG_ECC_MULT_BASE + 0x0108)
/* ECC_MULT_MEM_K_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_3 0xFFFFFFFF
#define ECC_MULT_MEM_K_3_M ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S))
#define ECC_MULT_MEM_K_3_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_3_S 0
#define ECC_MULT_K_4_REG (DR_REG_ECC_MULT_BASE + 0x010c)
/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_4 0xFFFFFFFF
#define ECC_MULT_MEM_K_4_M ((ECC_MULT_MEM_K_4_V)<<(ECC_MULT_MEM_K_4_S))
#define ECC_MULT_MEM_K_4_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_4_S 0
#define ECC_MULT_K_5_REG (DR_REG_ECC_MULT_BASE + 0x0110)
/* ECC_MULT_MEM_K_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_5 0xFFFFFFFF
#define ECC_MULT_MEM_K_5_M ((ECC_MULT_MEM_K_5_V)<<(ECC_MULT_MEM_K_5_S))
#define ECC_MULT_MEM_K_5_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_5_S 0
#define ECC_MULT_K_6_REG (DR_REG_ECC_MULT_BASE + 0x0114)
/* ECC_MULT_MEM_K_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_6 0xFFFFFFFF
#define ECC_MULT_MEM_K_6_M ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S))
#define ECC_MULT_MEM_K_6_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_6_S 0
#define ECC_MULT_K_7_REG (DR_REG_ECC_MULT_BASE + 0x0118)
/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_7 0xFFFFFFFF
#define ECC_MULT_MEM_K_7_M ((ECC_MULT_MEM_K_7_V)<<(ECC_MULT_MEM_K_7_S))
#define ECC_MULT_MEM_K_7_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_7_S 0
#define ECC_MULT_K_8_REG (DR_REG_ECC_MULT_BASE + 0x011c)
/* ECC_MULT_MEM_K_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter k.*/
#define ECC_MULT_MEM_K_8 0xFFFFFFFF
#define ECC_MULT_MEM_K_8_M ((ECC_MULT_MEM_K_8_V)<<(ECC_MULT_MEM_K_8_S))
#define ECC_MULT_MEM_K_8_V 0xFFFFFFFF
#define ECC_MULT_MEM_K_8_S 0
#define ECC_MULT_PX_1_REG (DR_REG_ECC_MULT_BASE + 0x0120)
/* ECC_MULT_MEM_PX_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_1 0xFFFFFFFF
#define ECC_MULT_MEM_PX_1_M ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S))
#define ECC_MULT_MEM_PX_1_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_1_S 0
#define ECC_MULT_PX_2_REG (DR_REG_ECC_MULT_BASE + 0x0124)
/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_2 0xFFFFFFFF
#define ECC_MULT_MEM_PX_2_M ((ECC_MULT_MEM_PX_2_V)<<(ECC_MULT_MEM_PX_2_S))
#define ECC_MULT_MEM_PX_2_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_2_S 0
#define ECC_MULT_PX_3_REG (DR_REG_ECC_MULT_BASE + 0x0128)
/* ECC_MULT_MEM_PX_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_3 0xFFFFFFFF
#define ECC_MULT_MEM_PX_3_M ((ECC_MULT_MEM_PX_3_V)<<(ECC_MULT_MEM_PX_3_S))
#define ECC_MULT_MEM_PX_3_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_3_S 0
#define ECC_MULT_PX_4_REG (DR_REG_ECC_MULT_BASE + 0x012c)
/* ECC_MULT_MEM_PX_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_4 0xFFFFFFFF
#define ECC_MULT_MEM_PX_4_M ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S))
#define ECC_MULT_MEM_PX_4_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_4_S 0
#define ECC_MULT_PX_5_REG (DR_REG_ECC_MULT_BASE + 0x0130)
/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_5 0xFFFFFFFF
#define ECC_MULT_MEM_PX_5_M ((ECC_MULT_MEM_PX_5_V)<<(ECC_MULT_MEM_PX_5_S))
#define ECC_MULT_MEM_PX_5_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_5_S 0
#define ECC_MULT_PX_6_REG (DR_REG_ECC_MULT_BASE + 0x0134)
/* ECC_MULT_MEM_PX_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_6 0xFFFFFFFF
#define ECC_MULT_MEM_PX_6_M ((ECC_MULT_MEM_PX_6_V)<<(ECC_MULT_MEM_PX_6_S))
#define ECC_MULT_MEM_PX_6_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_6_S 0
#define ECC_MULT_PX_7_REG (DR_REG_ECC_MULT_BASE + 0x0138)
/* ECC_MULT_MEM_PX_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_7 0xFFFFFFFF
#define ECC_MULT_MEM_PX_7_M ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S))
#define ECC_MULT_MEM_PX_7_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_7_S 0
#define ECC_MULT_PX_8_REG (DR_REG_ECC_MULT_BASE + 0x013c)
/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Px.*/
#define ECC_MULT_MEM_PX_8 0xFFFFFFFF
#define ECC_MULT_MEM_PX_8_M ((ECC_MULT_MEM_PX_8_V)<<(ECC_MULT_MEM_PX_8_S))
#define ECC_MULT_MEM_PX_8_V 0xFFFFFFFF
#define ECC_MULT_MEM_PX_8_S 0
#define ECC_MULT_PY_1_REG (DR_REG_ECC_MULT_BASE + 0x0140)
/* ECC_MULT_MEM_PY_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_1 0xFFFFFFFF
#define ECC_MULT_MEM_PY_1_M ((ECC_MULT_MEM_PY_1_V)<<(ECC_MULT_MEM_PY_1_S))
#define ECC_MULT_MEM_PY_1_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_1_S 0
#define ECC_MULT_PY_2_REG (DR_REG_ECC_MULT_BASE + 0x0144)
/* ECC_MULT_MEM_PY_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_2 0xFFFFFFFF
#define ECC_MULT_MEM_PY_2_M ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S))
#define ECC_MULT_MEM_PY_2_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_2_S 0
#define ECC_MULT_PY_3_REG (DR_REG_ECC_MULT_BASE + 0x0148)
/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_3 0xFFFFFFFF
#define ECC_MULT_MEM_PY_3_M ((ECC_MULT_MEM_PY_3_V)<<(ECC_MULT_MEM_PY_3_S))
#define ECC_MULT_MEM_PY_3_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_3_S 0
#define ECC_MULT_PY_4_REG (DR_REG_ECC_MULT_BASE + 0x014c)
/* ECC_MULT_MEM_PY_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_4 0xFFFFFFFF
#define ECC_MULT_MEM_PY_4_M ((ECC_MULT_MEM_PY_4_V)<<(ECC_MULT_MEM_PY_4_S))
#define ECC_MULT_MEM_PY_4_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_4_S 0
#define ECC_MULT_PY_5_REG (DR_REG_ECC_MULT_BASE + 0x0150)
/* ECC_MULT_MEM_PY_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_5 0xFFFFFFFF
#define ECC_MULT_MEM_PY_5_M ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S))
#define ECC_MULT_MEM_PY_5_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_5_S 0
#define ECC_MULT_PY_6_REG (DR_REG_ECC_MULT_BASE + 0x0154)
/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_6 0xFFFFFFFF
#define ECC_MULT_MEM_PY_6_M ((ECC_MULT_MEM_PY_6_V)<<(ECC_MULT_MEM_PY_6_S))
#define ECC_MULT_MEM_PY_6_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_6_S 0
#define ECC_MULT_PY_7_REG (DR_REG_ECC_MULT_BASE + 0x0158)
/* ECC_MULT_MEM_PY_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_7 0xFFFFFFFF
#define ECC_MULT_MEM_PY_7_M ((ECC_MULT_MEM_PY_7_V)<<(ECC_MULT_MEM_PY_7_S))
#define ECC_MULT_MEM_PY_7_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_7_S 0
#define ECC_MULT_PY_8_REG (DR_REG_ECC_MULT_BASE + 0x015c)
/* ECC_MULT_MEM_PY_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: ECC Mem Parameter Py.*/
#define ECC_MULT_MEM_PY_8 0xFFFFFFFF
#define ECC_MULT_MEM_PY_8_M ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S))
#define ECC_MULT_MEM_PY_8_V 0xFFFFFFFF
#define ECC_MULT_MEM_PY_8_S 0
#ifdef __cplusplus
}
#endif

1
components/soc/esp32c2/include/soc/periph_defs.h
View File

@@ -28,6 +28,7 @@ typedef enum {
PERIPH_BT_LC_MODULE,
PERIPH_AES_MODULE,
PERIPH_SHA_MODULE,
PERIPH_ECC_MODULE,
PERIPH_GDMA_MODULE,
PERIPH_SYSTIMER_MODULE,
PERIPH_SARADC_MODULE,

1
components/soc/esp32c2/include/soc/reg_base.h
View File

@@ -9,6 +9,7 @@
#define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG
#define DR_REG_MMU_TABLE 0x600c5000
#define DR_REG_SHA_BASE 0x6003b000
#define DR_REG_ECC_MULT_BASE 0x6003e000
#define DR_REG_GDMA_BASE 0x6003f000
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000

1
components/soc/esp32c2/include/soc/soc_caps.h
View File

@@ -32,6 +32,7 @@
#define SOC_BT_SUPPORTED 0 // Enable during bringup, IDF-4357
#define SOC_WIFI_SUPPORTED 0 // Enable during bringup, IDF-3905
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
#define SOC_ECC_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1
#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 0